1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 static void hns3_clear_all_ring(struct hnae3_handle *h); 25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 26 static void hns3_remove_hw_addr(struct net_device *netdev); 27 28 static const char hns3_driver_name[] = "hns3"; 29 const char hns3_driver_version[] = VERMAGIC_STRING; 30 static const char hns3_driver_string[] = 31 "Hisilicon Ethernet Network Driver for Hip08 Family"; 32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 33 static struct hnae3_client client; 34 35 /* hns3_pci_tbl - PCI Device ID Table 36 * 37 * Last entry must be all 0s 38 * 39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 40 * Class, Class Mask, private data (not used) } 41 */ 42 static const struct pci_device_id hns3_pci_tbl[] = { 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 /* required last entry */ 59 {0, } 60 }; 61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 62 63 static irqreturn_t hns3_irq_handle(int irq, void *vector) 64 { 65 struct hns3_enet_tqp_vector *tqp_vector = vector; 66 67 napi_schedule(&tqp_vector->napi); 68 69 return IRQ_HANDLED; 70 } 71 72 /* This callback function is used to set affinity changes to the irq affinity 73 * masks when the irq_set_affinity_notifier function is used. 74 */ 75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 76 const cpumask_t *mask) 77 { 78 struct hns3_enet_tqp_vector *tqp_vectors = 79 container_of(notify, struct hns3_enet_tqp_vector, 80 affinity_notify); 81 82 tqp_vectors->affinity_mask = *mask; 83 } 84 85 static void hns3_nic_irq_affinity_release(struct kref *ref) 86 { 87 } 88 89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 90 { 91 struct hns3_enet_tqp_vector *tqp_vectors; 92 unsigned int i; 93 94 for (i = 0; i < priv->vector_num; i++) { 95 tqp_vectors = &priv->tqp_vector[i]; 96 97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 98 continue; 99 100 /* clear the affinity notifier and affinity mask */ 101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 103 104 /* release the irq resource */ 105 free_irq(tqp_vectors->vector_irq, tqp_vectors); 106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 107 } 108 } 109 110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 111 { 112 struct hns3_enet_tqp_vector *tqp_vectors; 113 int txrx_int_idx = 0; 114 int rx_int_idx = 0; 115 int tx_int_idx = 0; 116 unsigned int i; 117 int ret; 118 119 for (i = 0; i < priv->vector_num; i++) { 120 tqp_vectors = &priv->tqp_vector[i]; 121 122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 123 continue; 124 125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 127 "%s-%s-%d", priv->netdev->name, "TxRx", 128 txrx_int_idx++); 129 txrx_int_idx++; 130 } else if (tqp_vectors->rx_group.ring) { 131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 132 "%s-%s-%d", priv->netdev->name, "Rx", 133 rx_int_idx++); 134 } else if (tqp_vectors->tx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Tx", 137 tx_int_idx++); 138 } else { 139 /* Skip this unused q_vector */ 140 continue; 141 } 142 143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 144 145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 146 tqp_vectors->name, 147 tqp_vectors); 148 if (ret) { 149 netdev_err(priv->netdev, "request irq(%d) fail\n", 150 tqp_vectors->vector_irq); 151 return ret; 152 } 153 154 tqp_vectors->affinity_notify.notify = 155 hns3_nic_irq_affinity_notify; 156 tqp_vectors->affinity_notify.release = 157 hns3_nic_irq_affinity_release; 158 irq_set_affinity_notifier(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_notify); 160 irq_set_affinity_hint(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_mask); 162 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 164 } 165 166 return 0; 167 } 168 169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 170 u32 mask_en) 171 { 172 writel(mask_en, tqp_vector->mask_addr); 173 } 174 175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 176 { 177 napi_enable(&tqp_vector->napi); 178 179 /* enable vector */ 180 hns3_mask_vector_irq(tqp_vector, 1); 181 } 182 183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 /* disable vector */ 186 hns3_mask_vector_irq(tqp_vector, 0); 187 188 disable_irq(tqp_vector->vector_irq); 189 napi_disable(&tqp_vector->napi); 190 } 191 192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 rl_value) 194 { 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 196 197 /* this defines the configuration for RL (Interrupt Rate Limiter). 198 * Rl defines rate of interrupts i.e. number of interrupts-per-second 199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 200 */ 201 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 203 !tqp_vector->rx_group.coal.gl_adapt_enable) 204 /* According to the hardware, the range of rl_reg is 205 * 0-59 and the unit is 4. 206 */ 207 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 208 209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 210 } 211 212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 213 u32 gl_value) 214 { 215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 216 217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 218 } 219 220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 221 u32 gl_value) 222 { 223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 224 225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 226 } 227 228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 229 struct hns3_nic_priv *priv) 230 { 231 /* initialize the configuration for interrupt coalescing. 232 * 1. GL (Interrupt Gap Limiter) 233 * 2. RL (Interrupt Rate Limiter) 234 */ 235 236 /* Default: enable interrupt coalescing self-adaptive and GL */ 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 238 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 239 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 242 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 245 } 246 247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 248 struct hns3_nic_priv *priv) 249 { 250 struct hnae3_handle *h = priv->ae_handle; 251 252 hns3_set_vector_coalesce_tx_gl(tqp_vector, 253 tqp_vector->tx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rx_gl(tqp_vector, 255 tqp_vector->rx_group.coal.int_gl); 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 257 } 258 259 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 260 { 261 struct hnae3_handle *h = hns3_get_handle(netdev); 262 struct hnae3_knic_private_info *kinfo = &h->kinfo; 263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 264 int i, ret; 265 266 if (kinfo->num_tc <= 1) { 267 netdev_reset_tc(netdev); 268 } else { 269 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 270 if (ret) { 271 netdev_err(netdev, 272 "netdev_set_num_tc fail, ret=%d!\n", ret); 273 return ret; 274 } 275 276 for (i = 0; i < HNAE3_MAX_TC; i++) { 277 if (!kinfo->tc_info[i].enable) 278 continue; 279 280 netdev_set_tc_queue(netdev, 281 kinfo->tc_info[i].tc, 282 kinfo->tc_info[i].tqp_count, 283 kinfo->tc_info[i].tqp_offset); 284 } 285 } 286 287 ret = netif_set_real_num_tx_queues(netdev, queue_size); 288 if (ret) { 289 netdev_err(netdev, 290 "netif_set_real_num_tx_queues fail, ret=%d!\n", 291 ret); 292 return ret; 293 } 294 295 ret = netif_set_real_num_rx_queues(netdev, queue_size); 296 if (ret) { 297 netdev_err(netdev, 298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 299 return ret; 300 } 301 302 return 0; 303 } 304 305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 306 { 307 u16 alloc_tqps, max_rss_size, rss_size; 308 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 310 rss_size = alloc_tqps / h->kinfo.num_tc; 311 312 return min_t(u16, rss_size, max_rss_size); 313 } 314 315 static void hns3_tqp_enable(struct hnae3_queue *tqp) 316 { 317 u32 rcb_reg; 318 319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 320 rcb_reg |= BIT(HNS3_RING_EN_B); 321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 322 } 323 324 static void hns3_tqp_disable(struct hnae3_queue *tqp) 325 { 326 u32 rcb_reg; 327 328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 329 rcb_reg &= ~BIT(HNS3_RING_EN_B); 330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 331 } 332 333 static int hns3_nic_net_up(struct net_device *netdev) 334 { 335 struct hns3_nic_priv *priv = netdev_priv(netdev); 336 struct hnae3_handle *h = priv->ae_handle; 337 int i, j; 338 int ret; 339 340 ret = hns3_nic_reset_all_ring(h); 341 if (ret) 342 return ret; 343 344 /* get irq resource for all vectors */ 345 ret = hns3_nic_init_irq(priv); 346 if (ret) { 347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 348 return ret; 349 } 350 351 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 352 353 /* enable the vectors */ 354 for (i = 0; i < priv->vector_num; i++) 355 hns3_vector_enable(&priv->tqp_vector[i]); 356 357 /* enable rcb */ 358 for (j = 0; j < h->kinfo.num_tqps; j++) 359 hns3_tqp_enable(h->kinfo.tqp[j]); 360 361 /* start the ae_dev */ 362 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 363 if (ret) 364 goto out_start_err; 365 366 return 0; 367 368 out_start_err: 369 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 370 while (j--) 371 hns3_tqp_disable(h->kinfo.tqp[j]); 372 373 for (j = i - 1; j >= 0; j--) 374 hns3_vector_disable(&priv->tqp_vector[j]); 375 376 hns3_nic_uninit_irq(priv); 377 378 return ret; 379 } 380 381 static int hns3_nic_net_open(struct net_device *netdev) 382 { 383 struct hns3_nic_priv *priv = netdev_priv(netdev); 384 struct hnae3_handle *h = hns3_get_handle(netdev); 385 struct hnae3_knic_private_info *kinfo; 386 int i, ret; 387 388 if (hns3_nic_resetting(netdev)) 389 return -EBUSY; 390 391 netif_carrier_off(netdev); 392 393 ret = hns3_nic_set_real_num_queue(netdev); 394 if (ret) 395 return ret; 396 397 ret = hns3_nic_net_up(netdev); 398 if (ret) { 399 netdev_err(netdev, 400 "hns net up fail, ret=%d!\n", ret); 401 return ret; 402 } 403 404 kinfo = &h->kinfo; 405 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 406 netdev_set_prio_tc_map(netdev, i, 407 kinfo->prio_tc[i]); 408 } 409 410 if (h->ae_algo->ops->set_timer_task) 411 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 412 413 return 0; 414 } 415 416 static void hns3_nic_net_down(struct net_device *netdev) 417 { 418 struct hns3_nic_priv *priv = netdev_priv(netdev); 419 struct hnae3_handle *h = hns3_get_handle(netdev); 420 const struct hnae3_ae_ops *ops; 421 int i; 422 423 /* disable vectors */ 424 for (i = 0; i < priv->vector_num; i++) 425 hns3_vector_disable(&priv->tqp_vector[i]); 426 427 /* disable rcb */ 428 for (i = 0; i < h->kinfo.num_tqps; i++) 429 hns3_tqp_disable(h->kinfo.tqp[i]); 430 431 /* stop ae_dev */ 432 ops = priv->ae_handle->ae_algo->ops; 433 if (ops->stop) 434 ops->stop(priv->ae_handle); 435 436 /* free irq resources */ 437 hns3_nic_uninit_irq(priv); 438 439 hns3_clear_all_ring(priv->ae_handle); 440 } 441 442 static int hns3_nic_net_stop(struct net_device *netdev) 443 { 444 struct hns3_nic_priv *priv = netdev_priv(netdev); 445 struct hnae3_handle *h = hns3_get_handle(netdev); 446 447 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 448 return 0; 449 450 if (h->ae_algo->ops->set_timer_task) 451 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 452 453 netif_tx_stop_all_queues(netdev); 454 netif_carrier_off(netdev); 455 456 hns3_nic_net_down(netdev); 457 458 return 0; 459 } 460 461 static int hns3_nic_uc_sync(struct net_device *netdev, 462 const unsigned char *addr) 463 { 464 struct hnae3_handle *h = hns3_get_handle(netdev); 465 466 if (h->ae_algo->ops->add_uc_addr) 467 return h->ae_algo->ops->add_uc_addr(h, addr); 468 469 return 0; 470 } 471 472 static int hns3_nic_uc_unsync(struct net_device *netdev, 473 const unsigned char *addr) 474 { 475 struct hnae3_handle *h = hns3_get_handle(netdev); 476 477 if (h->ae_algo->ops->rm_uc_addr) 478 return h->ae_algo->ops->rm_uc_addr(h, addr); 479 480 return 0; 481 } 482 483 static int hns3_nic_mc_sync(struct net_device *netdev, 484 const unsigned char *addr) 485 { 486 struct hnae3_handle *h = hns3_get_handle(netdev); 487 488 if (h->ae_algo->ops->add_mc_addr) 489 return h->ae_algo->ops->add_mc_addr(h, addr); 490 491 return 0; 492 } 493 494 static int hns3_nic_mc_unsync(struct net_device *netdev, 495 const unsigned char *addr) 496 { 497 struct hnae3_handle *h = hns3_get_handle(netdev); 498 499 if (h->ae_algo->ops->rm_mc_addr) 500 return h->ae_algo->ops->rm_mc_addr(h, addr); 501 502 return 0; 503 } 504 505 static u8 hns3_get_netdev_flags(struct net_device *netdev) 506 { 507 u8 flags = 0; 508 509 if (netdev->flags & IFF_PROMISC) { 510 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 511 } else { 512 flags |= HNAE3_VLAN_FLTR; 513 if (netdev->flags & IFF_ALLMULTI) 514 flags |= HNAE3_USER_MPE; 515 } 516 517 return flags; 518 } 519 520 static void hns3_nic_set_rx_mode(struct net_device *netdev) 521 { 522 struct hnae3_handle *h = hns3_get_handle(netdev); 523 u8 new_flags; 524 int ret; 525 526 new_flags = hns3_get_netdev_flags(netdev); 527 528 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 529 if (ret) { 530 netdev_err(netdev, "sync uc address fail\n"); 531 if (ret == -ENOSPC) 532 new_flags |= HNAE3_OVERFLOW_UPE; 533 } 534 535 if (netdev->flags & IFF_MULTICAST) { 536 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 537 hns3_nic_mc_unsync); 538 if (ret) { 539 netdev_err(netdev, "sync mc address fail\n"); 540 if (ret == -ENOSPC) 541 new_flags |= HNAE3_OVERFLOW_MPE; 542 } 543 } 544 545 /* User mode Promisc mode enable and vlan filtering is disabled to 546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 547 * vlan fitering is enabled 548 */ 549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 550 h->netdev_flags = new_flags; 551 hns3_update_promisc_mode(netdev, new_flags); 552 } 553 554 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 555 { 556 struct hns3_nic_priv *priv = netdev_priv(netdev); 557 struct hnae3_handle *h = priv->ae_handle; 558 559 if (h->ae_algo->ops->set_promisc_mode) { 560 return h->ae_algo->ops->set_promisc_mode(h, 561 promisc_flags & HNAE3_UPE, 562 promisc_flags & HNAE3_MPE); 563 } 564 565 return 0; 566 } 567 568 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 569 { 570 struct hns3_nic_priv *priv = netdev_priv(netdev); 571 struct hnae3_handle *h = priv->ae_handle; 572 bool last_state; 573 574 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 575 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 576 if (enable != last_state) { 577 netdev_info(netdev, 578 "%s vlan filter\n", 579 enable ? "enable" : "disable"); 580 h->ae_algo->ops->enable_vlan_filter(h, enable); 581 } 582 } 583 } 584 585 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 586 u16 *mss, u32 *type_cs_vlan_tso) 587 { 588 u32 l4_offset, hdr_len; 589 union l3_hdr_info l3; 590 union l4_hdr_info l4; 591 u32 l4_paylen; 592 int ret; 593 594 if (!skb_is_gso(skb)) 595 return 0; 596 597 ret = skb_cow_head(skb, 0); 598 if (ret) 599 return ret; 600 601 l3.hdr = skb_network_header(skb); 602 l4.hdr = skb_transport_header(skb); 603 604 /* Software should clear the IPv4's checksum field when tso is 605 * needed. 606 */ 607 if (l3.v4->version == 4) 608 l3.v4->check = 0; 609 610 /* tunnel packet.*/ 611 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 612 SKB_GSO_GRE_CSUM | 613 SKB_GSO_UDP_TUNNEL | 614 SKB_GSO_UDP_TUNNEL_CSUM)) { 615 if ((!(skb_shinfo(skb)->gso_type & 616 SKB_GSO_PARTIAL)) && 617 (skb_shinfo(skb)->gso_type & 618 SKB_GSO_UDP_TUNNEL_CSUM)) { 619 /* Software should clear the udp's checksum 620 * field when tso is needed. 621 */ 622 l4.udp->check = 0; 623 } 624 /* reset l3&l4 pointers from outer to inner headers */ 625 l3.hdr = skb_inner_network_header(skb); 626 l4.hdr = skb_inner_transport_header(skb); 627 628 /* Software should clear the IPv4's checksum field when 629 * tso is needed. 630 */ 631 if (l3.v4->version == 4) 632 l3.v4->check = 0; 633 } 634 635 /* normal or tunnel packet*/ 636 l4_offset = l4.hdr - skb->data; 637 hdr_len = (l4.tcp->doff * 4) + l4_offset; 638 639 /* remove payload length from inner pseudo checksum when tso*/ 640 l4_paylen = skb->len - l4_offset; 641 csum_replace_by_diff(&l4.tcp->check, 642 (__force __wsum)htonl(l4_paylen)); 643 644 /* find the txbd field values */ 645 *paylen = skb->len - hdr_len; 646 hnae3_set_bit(*type_cs_vlan_tso, 647 HNS3_TXD_TSO_B, 1); 648 649 /* get MSS for TSO */ 650 *mss = skb_shinfo(skb)->gso_size; 651 652 return 0; 653 } 654 655 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 656 u8 *il4_proto) 657 { 658 union { 659 struct iphdr *v4; 660 struct ipv6hdr *v6; 661 unsigned char *hdr; 662 } l3; 663 unsigned char *l4_hdr; 664 unsigned char *exthdr; 665 u8 l4_proto_tmp; 666 __be16 frag_off; 667 668 /* find outer header point */ 669 l3.hdr = skb_network_header(skb); 670 l4_hdr = skb_transport_header(skb); 671 672 if (skb->protocol == htons(ETH_P_IPV6)) { 673 exthdr = l3.hdr + sizeof(*l3.v6); 674 l4_proto_tmp = l3.v6->nexthdr; 675 if (l4_hdr != exthdr) 676 ipv6_skip_exthdr(skb, exthdr - skb->data, 677 &l4_proto_tmp, &frag_off); 678 } else if (skb->protocol == htons(ETH_P_IP)) { 679 l4_proto_tmp = l3.v4->protocol; 680 } else { 681 return -EINVAL; 682 } 683 684 *ol4_proto = l4_proto_tmp; 685 686 /* tunnel packet */ 687 if (!skb->encapsulation) { 688 *il4_proto = 0; 689 return 0; 690 } 691 692 /* find inner header point */ 693 l3.hdr = skb_inner_network_header(skb); 694 l4_hdr = skb_inner_transport_header(skb); 695 696 if (l3.v6->version == 6) { 697 exthdr = l3.hdr + sizeof(*l3.v6); 698 l4_proto_tmp = l3.v6->nexthdr; 699 if (l4_hdr != exthdr) 700 ipv6_skip_exthdr(skb, exthdr - skb->data, 701 &l4_proto_tmp, &frag_off); 702 } else if (l3.v4->version == 4) { 703 l4_proto_tmp = l3.v4->protocol; 704 } 705 706 *il4_proto = l4_proto_tmp; 707 708 return 0; 709 } 710 711 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 712 u8 il4_proto, u32 *type_cs_vlan_tso, 713 u32 *ol_type_vlan_len_msec) 714 { 715 union { 716 struct iphdr *v4; 717 struct ipv6hdr *v6; 718 unsigned char *hdr; 719 } l3; 720 union { 721 struct tcphdr *tcp; 722 struct udphdr *udp; 723 struct gre_base_hdr *gre; 724 unsigned char *hdr; 725 } l4; 726 unsigned char *l2_hdr; 727 u8 l4_proto = ol4_proto; 728 u32 ol2_len; 729 u32 ol3_len; 730 u32 ol4_len; 731 u32 l2_len; 732 u32 l3_len; 733 734 l3.hdr = skb_network_header(skb); 735 l4.hdr = skb_transport_header(skb); 736 737 /* compute L2 header size for normal packet, defined in 2 Bytes */ 738 l2_len = l3.hdr - skb->data; 739 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 740 HNS3_TXD_L2LEN_S, l2_len >> 1); 741 742 /* tunnel packet*/ 743 if (skb->encapsulation) { 744 /* compute OL2 header size, defined in 2 Bytes */ 745 ol2_len = l2_len; 746 hnae3_set_field(*ol_type_vlan_len_msec, 747 HNS3_TXD_L2LEN_M, 748 HNS3_TXD_L2LEN_S, ol2_len >> 1); 749 750 /* compute OL3 header size, defined in 4 Bytes */ 751 ol3_len = l4.hdr - l3.hdr; 752 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 753 HNS3_TXD_L3LEN_S, ol3_len >> 2); 754 755 /* MAC in UDP, MAC in GRE (0x6558)*/ 756 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 757 /* switch MAC header ptr from outer to inner header.*/ 758 l2_hdr = skb_inner_mac_header(skb); 759 760 /* compute OL4 header size, defined in 4 Bytes. */ 761 ol4_len = l2_hdr - l4.hdr; 762 hnae3_set_field(*ol_type_vlan_len_msec, 763 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 764 ol4_len >> 2); 765 766 /* switch IP header ptr from outer to inner header */ 767 l3.hdr = skb_inner_network_header(skb); 768 769 /* compute inner l2 header size, defined in 2 Bytes. */ 770 l2_len = l3.hdr - l2_hdr; 771 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 772 HNS3_TXD_L2LEN_S, l2_len >> 1); 773 } else { 774 /* skb packet types not supported by hardware, 775 * txbd len fild doesn't be filled. 776 */ 777 return; 778 } 779 780 /* switch L4 header pointer from outer to inner */ 781 l4.hdr = skb_inner_transport_header(skb); 782 783 l4_proto = il4_proto; 784 } 785 786 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 787 l3_len = l4.hdr - l3.hdr; 788 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 789 HNS3_TXD_L3LEN_S, l3_len >> 2); 790 791 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 792 switch (l4_proto) { 793 case IPPROTO_TCP: 794 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 795 HNS3_TXD_L4LEN_S, l4.tcp->doff); 796 break; 797 case IPPROTO_SCTP: 798 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 799 HNS3_TXD_L4LEN_S, 800 (sizeof(struct sctphdr) >> 2)); 801 break; 802 case IPPROTO_UDP: 803 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 804 HNS3_TXD_L4LEN_S, 805 (sizeof(struct udphdr) >> 2)); 806 break; 807 default: 808 /* skb packet types not supported by hardware, 809 * txbd len fild doesn't be filled. 810 */ 811 return; 812 } 813 } 814 815 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 816 * and it is udp packet, which has a dest port as the IANA assigned. 817 * the hardware is expected to do the checksum offload, but the 818 * hardware will not do the checksum offload when udp dest port is 819 * 4789. 820 */ 821 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 822 { 823 #define IANA_VXLAN_PORT 4789 824 union { 825 struct tcphdr *tcp; 826 struct udphdr *udp; 827 struct gre_base_hdr *gre; 828 unsigned char *hdr; 829 } l4; 830 831 l4.hdr = skb_transport_header(skb); 832 833 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 834 return false; 835 836 skb_checksum_help(skb); 837 838 return true; 839 } 840 841 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 842 u8 il4_proto, u32 *type_cs_vlan_tso, 843 u32 *ol_type_vlan_len_msec) 844 { 845 union { 846 struct iphdr *v4; 847 struct ipv6hdr *v6; 848 unsigned char *hdr; 849 } l3; 850 u32 l4_proto = ol4_proto; 851 852 l3.hdr = skb_network_header(skb); 853 854 /* define OL3 type and tunnel type(OL4).*/ 855 if (skb->encapsulation) { 856 /* define outer network header type.*/ 857 if (skb->protocol == htons(ETH_P_IP)) { 858 if (skb_is_gso(skb)) 859 hnae3_set_field(*ol_type_vlan_len_msec, 860 HNS3_TXD_OL3T_M, 861 HNS3_TXD_OL3T_S, 862 HNS3_OL3T_IPV4_CSUM); 863 else 864 hnae3_set_field(*ol_type_vlan_len_msec, 865 HNS3_TXD_OL3T_M, 866 HNS3_TXD_OL3T_S, 867 HNS3_OL3T_IPV4_NO_CSUM); 868 869 } else if (skb->protocol == htons(ETH_P_IPV6)) { 870 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 871 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 872 } 873 874 /* define tunnel type(OL4).*/ 875 switch (l4_proto) { 876 case IPPROTO_UDP: 877 hnae3_set_field(*ol_type_vlan_len_msec, 878 HNS3_TXD_TUNTYPE_M, 879 HNS3_TXD_TUNTYPE_S, 880 HNS3_TUN_MAC_IN_UDP); 881 break; 882 case IPPROTO_GRE: 883 hnae3_set_field(*ol_type_vlan_len_msec, 884 HNS3_TXD_TUNTYPE_M, 885 HNS3_TXD_TUNTYPE_S, 886 HNS3_TUN_NVGRE); 887 break; 888 default: 889 /* drop the skb tunnel packet if hardware don't support, 890 * because hardware can't calculate csum when TSO. 891 */ 892 if (skb_is_gso(skb)) 893 return -EDOM; 894 895 /* the stack computes the IP header already, 896 * driver calculate l4 checksum when not TSO. 897 */ 898 skb_checksum_help(skb); 899 return 0; 900 } 901 902 l3.hdr = skb_inner_network_header(skb); 903 l4_proto = il4_proto; 904 } 905 906 if (l3.v4->version == 4) { 907 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 908 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 909 910 /* the stack computes the IP header already, the only time we 911 * need the hardware to recompute it is in the case of TSO. 912 */ 913 if (skb_is_gso(skb)) 914 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 915 } else if (l3.v6->version == 6) { 916 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 917 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 918 } 919 920 switch (l4_proto) { 921 case IPPROTO_TCP: 922 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 923 hnae3_set_field(*type_cs_vlan_tso, 924 HNS3_TXD_L4T_M, 925 HNS3_TXD_L4T_S, 926 HNS3_L4T_TCP); 927 break; 928 case IPPROTO_UDP: 929 if (hns3_tunnel_csum_bug(skb)) 930 break; 931 932 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 933 hnae3_set_field(*type_cs_vlan_tso, 934 HNS3_TXD_L4T_M, 935 HNS3_TXD_L4T_S, 936 HNS3_L4T_UDP); 937 break; 938 case IPPROTO_SCTP: 939 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 940 hnae3_set_field(*type_cs_vlan_tso, 941 HNS3_TXD_L4T_M, 942 HNS3_TXD_L4T_S, 943 HNS3_L4T_SCTP); 944 break; 945 default: 946 /* drop the skb tunnel packet if hardware don't support, 947 * because hardware can't calculate csum when TSO. 948 */ 949 if (skb_is_gso(skb)) 950 return -EDOM; 951 952 /* the stack computes the IP header already, 953 * driver calculate l4 checksum when not TSO. 954 */ 955 skb_checksum_help(skb); 956 return 0; 957 } 958 959 return 0; 960 } 961 962 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 963 { 964 /* Config bd buffer end */ 965 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 966 HNS3_TXD_BDTYPE_S, 0); 967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 968 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 969 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 970 } 971 972 static int hns3_fill_desc_vtags(struct sk_buff *skb, 973 struct hns3_enet_ring *tx_ring, 974 u32 *inner_vlan_flag, 975 u32 *out_vlan_flag, 976 u16 *inner_vtag, 977 u16 *out_vtag) 978 { 979 #define HNS3_TX_VLAN_PRIO_SHIFT 13 980 981 if (skb->protocol == htons(ETH_P_8021Q) && 982 !(tx_ring->tqp->handle->kinfo.netdev->features & 983 NETIF_F_HW_VLAN_CTAG_TX)) { 984 /* When HW VLAN acceleration is turned off, and the stack 985 * sets the protocol to 802.1q, the driver just need to 986 * set the protocol to the encapsulated ethertype. 987 */ 988 skb->protocol = vlan_get_protocol(skb); 989 return 0; 990 } 991 992 if (skb_vlan_tag_present(skb)) { 993 u16 vlan_tag; 994 995 vlan_tag = skb_vlan_tag_get(skb); 996 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 997 998 /* Based on hw strategy, use out_vtag in two layer tag case, 999 * and use inner_vtag in one tag case. 1000 */ 1001 if (skb->protocol == htons(ETH_P_8021Q)) { 1002 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 1003 *out_vtag = vlan_tag; 1004 } else { 1005 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 1006 *inner_vtag = vlan_tag; 1007 } 1008 } else if (skb->protocol == htons(ETH_P_8021Q)) { 1009 struct vlan_ethhdr *vhdr; 1010 int rc; 1011 1012 rc = skb_cow_head(skb, 0); 1013 if (rc < 0) 1014 return rc; 1015 vhdr = (struct vlan_ethhdr *)skb->data; 1016 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1017 << HNS3_TX_VLAN_PRIO_SHIFT); 1018 } 1019 1020 skb->protocol = vlan_get_protocol(skb); 1021 return 0; 1022 } 1023 1024 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1025 int size, int frag_end, enum hns_desc_type type) 1026 { 1027 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1028 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1029 struct device *dev = ring_to_dev(ring); 1030 u32 ol_type_vlan_len_msec = 0; 1031 u16 bdtp_fe_sc_vld_ra_ri = 0; 1032 struct skb_frag_struct *frag; 1033 unsigned int frag_buf_num; 1034 u32 type_cs_vlan_tso = 0; 1035 struct sk_buff *skb; 1036 u16 inner_vtag = 0; 1037 u16 out_vtag = 0; 1038 unsigned int k; 1039 int sizeoflast; 1040 u32 paylen = 0; 1041 dma_addr_t dma; 1042 u16 mss = 0; 1043 u8 ol4_proto; 1044 u8 il4_proto; 1045 int ret; 1046 1047 if (type == DESC_TYPE_SKB) { 1048 skb = (struct sk_buff *)priv; 1049 paylen = skb->len; 1050 1051 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1052 &ol_type_vlan_len_msec, 1053 &inner_vtag, &out_vtag); 1054 if (unlikely(ret)) 1055 return ret; 1056 1057 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1058 skb_reset_mac_len(skb); 1059 1060 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1061 if (ret) 1062 return ret; 1063 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1064 &type_cs_vlan_tso, 1065 &ol_type_vlan_len_msec); 1066 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1067 &type_cs_vlan_tso, 1068 &ol_type_vlan_len_msec); 1069 if (ret) 1070 return ret; 1071 1072 ret = hns3_set_tso(skb, &paylen, &mss, 1073 &type_cs_vlan_tso); 1074 if (ret) 1075 return ret; 1076 } 1077 1078 /* Set txbd */ 1079 desc->tx.ol_type_vlan_len_msec = 1080 cpu_to_le32(ol_type_vlan_len_msec); 1081 desc->tx.type_cs_vlan_tso_len = 1082 cpu_to_le32(type_cs_vlan_tso); 1083 desc->tx.paylen = cpu_to_le32(paylen); 1084 desc->tx.mss = cpu_to_le16(mss); 1085 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1086 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1087 1088 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1089 } else { 1090 frag = (struct skb_frag_struct *)priv; 1091 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1092 } 1093 1094 if (dma_mapping_error(ring->dev, dma)) { 1095 ring->stats.sw_err_cnt++; 1096 return -ENOMEM; 1097 } 1098 1099 desc_cb->length = size; 1100 1101 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1102 sizeoflast = size % HNS3_MAX_BD_SIZE; 1103 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1104 1105 /* When frag size is bigger than hardware limit, split this frag */ 1106 for (k = 0; k < frag_buf_num; k++) { 1107 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1108 desc_cb->priv = priv; 1109 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1110 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1111 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1112 1113 /* now, fill the descriptor */ 1114 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1115 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1116 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1117 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1118 frag_end && (k == frag_buf_num - 1) ? 1119 1 : 0); 1120 desc->tx.bdtp_fe_sc_vld_ra_ri = 1121 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1122 1123 /* move ring pointer to next.*/ 1124 ring_ptr_move_fw(ring, next_to_use); 1125 1126 desc_cb = &ring->desc_cb[ring->next_to_use]; 1127 desc = &ring->desc[ring->next_to_use]; 1128 } 1129 1130 return 0; 1131 } 1132 1133 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1134 struct hns3_enet_ring *ring) 1135 { 1136 struct sk_buff *skb = *out_skb; 1137 struct sk_buff *new_skb = NULL; 1138 struct skb_frag_struct *frag; 1139 int bdnum_for_frag; 1140 int frag_num; 1141 int buf_num; 1142 int size; 1143 int i; 1144 1145 size = skb_headlen(skb); 1146 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1147 1148 frag_num = skb_shinfo(skb)->nr_frags; 1149 for (i = 0; i < frag_num; i++) { 1150 frag = &skb_shinfo(skb)->frags[i]; 1151 size = skb_frag_size(frag); 1152 bdnum_for_frag = 1153 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1154 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1155 return -ENOMEM; 1156 1157 buf_num += bdnum_for_frag; 1158 } 1159 1160 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1161 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1162 if (ring_space(ring) < buf_num) 1163 return -EBUSY; 1164 /* manual split the send packet */ 1165 new_skb = skb_copy(skb, GFP_ATOMIC); 1166 if (!new_skb) 1167 return -ENOMEM; 1168 dev_kfree_skb_any(skb); 1169 *out_skb = new_skb; 1170 } 1171 1172 if (unlikely(ring_space(ring) < buf_num)) 1173 return -EBUSY; 1174 1175 *bnum = buf_num; 1176 return 0; 1177 } 1178 1179 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1180 struct hns3_enet_ring *ring) 1181 { 1182 struct sk_buff *skb = *out_skb; 1183 struct sk_buff *new_skb = NULL; 1184 int buf_num; 1185 1186 /* No. of segments (plus a header) */ 1187 buf_num = skb_shinfo(skb)->nr_frags + 1; 1188 1189 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1190 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1191 if (ring_space(ring) < buf_num) 1192 return -EBUSY; 1193 /* manual split the send packet */ 1194 new_skb = skb_copy(skb, GFP_ATOMIC); 1195 if (!new_skb) 1196 return -ENOMEM; 1197 dev_kfree_skb_any(skb); 1198 *out_skb = new_skb; 1199 } 1200 1201 if (unlikely(ring_space(ring) < buf_num)) 1202 return -EBUSY; 1203 1204 *bnum = buf_num; 1205 1206 return 0; 1207 } 1208 1209 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1210 { 1211 struct device *dev = ring_to_dev(ring); 1212 unsigned int i; 1213 1214 for (i = 0; i < ring->desc_num; i++) { 1215 /* check if this is where we started */ 1216 if (ring->next_to_use == next_to_use_orig) 1217 break; 1218 1219 /* unmap the descriptor dma address */ 1220 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1221 dma_unmap_single(dev, 1222 ring->desc_cb[ring->next_to_use].dma, 1223 ring->desc_cb[ring->next_to_use].length, 1224 DMA_TO_DEVICE); 1225 else if (ring->desc_cb[ring->next_to_use].length) 1226 dma_unmap_page(dev, 1227 ring->desc_cb[ring->next_to_use].dma, 1228 ring->desc_cb[ring->next_to_use].length, 1229 DMA_TO_DEVICE); 1230 1231 ring->desc_cb[ring->next_to_use].length = 0; 1232 1233 /* rollback one */ 1234 ring_ptr_move_bw(ring, next_to_use); 1235 } 1236 } 1237 1238 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1239 { 1240 struct hns3_nic_priv *priv = netdev_priv(netdev); 1241 struct hns3_nic_ring_data *ring_data = 1242 &tx_ring_data(priv, skb->queue_mapping); 1243 struct hns3_enet_ring *ring = ring_data->ring; 1244 struct netdev_queue *dev_queue; 1245 struct skb_frag_struct *frag; 1246 int next_to_use_head; 1247 int next_to_use_frag; 1248 int buf_num; 1249 int seg_num; 1250 int size; 1251 int ret; 1252 int i; 1253 1254 /* Prefetch the data used later */ 1255 prefetch(skb->data); 1256 1257 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1258 case -EBUSY: 1259 u64_stats_update_begin(&ring->syncp); 1260 ring->stats.tx_busy++; 1261 u64_stats_update_end(&ring->syncp); 1262 1263 goto out_net_tx_busy; 1264 case -ENOMEM: 1265 u64_stats_update_begin(&ring->syncp); 1266 ring->stats.sw_err_cnt++; 1267 u64_stats_update_end(&ring->syncp); 1268 netdev_err(netdev, "no memory to xmit!\n"); 1269 1270 goto out_err_tx_ok; 1271 default: 1272 break; 1273 } 1274 1275 /* No. of segments (plus a header) */ 1276 seg_num = skb_shinfo(skb)->nr_frags + 1; 1277 /* Fill the first part */ 1278 size = skb_headlen(skb); 1279 1280 next_to_use_head = ring->next_to_use; 1281 1282 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1283 DESC_TYPE_SKB); 1284 if (ret) 1285 goto head_fill_err; 1286 1287 next_to_use_frag = ring->next_to_use; 1288 /* Fill the fragments */ 1289 for (i = 1; i < seg_num; i++) { 1290 frag = &skb_shinfo(skb)->frags[i - 1]; 1291 size = skb_frag_size(frag); 1292 1293 ret = priv->ops.fill_desc(ring, frag, size, 1294 seg_num - 1 == i ? 1 : 0, 1295 DESC_TYPE_PAGE); 1296 1297 if (ret) 1298 goto frag_fill_err; 1299 } 1300 1301 /* Complete translate all packets */ 1302 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1303 netdev_tx_sent_queue(dev_queue, skb->len); 1304 1305 wmb(); /* Commit all data before submit */ 1306 1307 hnae3_queue_xmit(ring->tqp, buf_num); 1308 1309 return NETDEV_TX_OK; 1310 1311 frag_fill_err: 1312 hns3_clear_desc(ring, next_to_use_frag); 1313 1314 head_fill_err: 1315 hns3_clear_desc(ring, next_to_use_head); 1316 1317 out_err_tx_ok: 1318 dev_kfree_skb_any(skb); 1319 return NETDEV_TX_OK; 1320 1321 out_net_tx_busy: 1322 netif_stop_subqueue(netdev, ring_data->queue_index); 1323 smp_mb(); /* Commit all data before submit */ 1324 1325 return NETDEV_TX_BUSY; 1326 } 1327 1328 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1329 { 1330 struct hnae3_handle *h = hns3_get_handle(netdev); 1331 struct sockaddr *mac_addr = p; 1332 int ret; 1333 1334 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1335 return -EADDRNOTAVAIL; 1336 1337 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1338 netdev_info(netdev, "already using mac address %pM\n", 1339 mac_addr->sa_data); 1340 return 0; 1341 } 1342 1343 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1344 if (ret) { 1345 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1346 return ret; 1347 } 1348 1349 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1350 1351 return 0; 1352 } 1353 1354 static int hns3_nic_do_ioctl(struct net_device *netdev, 1355 struct ifreq *ifr, int cmd) 1356 { 1357 struct hnae3_handle *h = hns3_get_handle(netdev); 1358 1359 if (!netif_running(netdev)) 1360 return -EINVAL; 1361 1362 if (!h->ae_algo->ops->do_ioctl) 1363 return -EOPNOTSUPP; 1364 1365 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1366 } 1367 1368 static int hns3_nic_set_features(struct net_device *netdev, 1369 netdev_features_t features) 1370 { 1371 netdev_features_t changed = netdev->features ^ features; 1372 struct hns3_nic_priv *priv = netdev_priv(netdev); 1373 struct hnae3_handle *h = priv->ae_handle; 1374 int ret; 1375 1376 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1377 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1378 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1379 else 1380 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1381 } 1382 1383 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1384 if (features & NETIF_F_GRO_HW) 1385 ret = h->ae_algo->ops->set_gro_en(h, true); 1386 else 1387 ret = h->ae_algo->ops->set_gro_en(h, false); 1388 if (ret) 1389 return ret; 1390 } 1391 1392 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1393 h->ae_algo->ops->enable_vlan_filter) { 1394 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1395 h->ae_algo->ops->enable_vlan_filter(h, true); 1396 else 1397 h->ae_algo->ops->enable_vlan_filter(h, false); 1398 } 1399 1400 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1401 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1402 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1403 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1404 else 1405 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1406 1407 if (ret) 1408 return ret; 1409 } 1410 1411 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1412 if (features & NETIF_F_NTUPLE) 1413 h->ae_algo->ops->enable_fd(h, true); 1414 else 1415 h->ae_algo->ops->enable_fd(h, false); 1416 } 1417 1418 netdev->features = features; 1419 return 0; 1420 } 1421 1422 static void hns3_nic_get_stats64(struct net_device *netdev, 1423 struct rtnl_link_stats64 *stats) 1424 { 1425 struct hns3_nic_priv *priv = netdev_priv(netdev); 1426 int queue_num = priv->ae_handle->kinfo.num_tqps; 1427 struct hnae3_handle *handle = priv->ae_handle; 1428 struct hns3_enet_ring *ring; 1429 u64 rx_length_errors = 0; 1430 u64 rx_crc_errors = 0; 1431 u64 rx_multicast = 0; 1432 unsigned int start; 1433 u64 tx_errors = 0; 1434 u64 rx_errors = 0; 1435 unsigned int idx; 1436 u64 tx_bytes = 0; 1437 u64 rx_bytes = 0; 1438 u64 tx_pkts = 0; 1439 u64 rx_pkts = 0; 1440 u64 tx_drop = 0; 1441 u64 rx_drop = 0; 1442 1443 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1444 return; 1445 1446 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1447 1448 for (idx = 0; idx < queue_num; idx++) { 1449 /* fetch the tx stats */ 1450 ring = priv->ring_data[idx].ring; 1451 do { 1452 start = u64_stats_fetch_begin_irq(&ring->syncp); 1453 tx_bytes += ring->stats.tx_bytes; 1454 tx_pkts += ring->stats.tx_pkts; 1455 tx_drop += ring->stats.sw_err_cnt; 1456 tx_errors += ring->stats.sw_err_cnt; 1457 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1458 1459 /* fetch the rx stats */ 1460 ring = priv->ring_data[idx + queue_num].ring; 1461 do { 1462 start = u64_stats_fetch_begin_irq(&ring->syncp); 1463 rx_bytes += ring->stats.rx_bytes; 1464 rx_pkts += ring->stats.rx_pkts; 1465 rx_drop += ring->stats.non_vld_descs; 1466 rx_drop += ring->stats.l2_err; 1467 rx_errors += ring->stats.non_vld_descs; 1468 rx_errors += ring->stats.l2_err; 1469 rx_crc_errors += ring->stats.l2_err; 1470 rx_crc_errors += ring->stats.l3l4_csum_err; 1471 rx_multicast += ring->stats.rx_multicast; 1472 rx_length_errors += ring->stats.err_pkt_len; 1473 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1474 } 1475 1476 stats->tx_bytes = tx_bytes; 1477 stats->tx_packets = tx_pkts; 1478 stats->rx_bytes = rx_bytes; 1479 stats->rx_packets = rx_pkts; 1480 1481 stats->rx_errors = rx_errors; 1482 stats->multicast = rx_multicast; 1483 stats->rx_length_errors = rx_length_errors; 1484 stats->rx_crc_errors = rx_crc_errors; 1485 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1486 1487 stats->tx_errors = tx_errors; 1488 stats->rx_dropped = rx_drop; 1489 stats->tx_dropped = tx_drop; 1490 stats->collisions = netdev->stats.collisions; 1491 stats->rx_over_errors = netdev->stats.rx_over_errors; 1492 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1493 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1494 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1495 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1496 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1497 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1498 stats->tx_window_errors = netdev->stats.tx_window_errors; 1499 stats->rx_compressed = netdev->stats.rx_compressed; 1500 stats->tx_compressed = netdev->stats.tx_compressed; 1501 } 1502 1503 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1504 { 1505 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1506 struct hnae3_handle *h = hns3_get_handle(netdev); 1507 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1508 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1509 u8 tc = mqprio_qopt->qopt.num_tc; 1510 u16 mode = mqprio_qopt->mode; 1511 u8 hw = mqprio_qopt->qopt.hw; 1512 1513 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1514 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1515 return -EOPNOTSUPP; 1516 1517 if (tc > HNAE3_MAX_TC) 1518 return -EINVAL; 1519 1520 if (!netdev) 1521 return -EINVAL; 1522 1523 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1524 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1525 } 1526 1527 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1528 void *type_data) 1529 { 1530 if (type != TC_SETUP_QDISC_MQPRIO) 1531 return -EOPNOTSUPP; 1532 1533 return hns3_setup_tc(dev, type_data); 1534 } 1535 1536 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1537 __be16 proto, u16 vid) 1538 { 1539 struct hnae3_handle *h = hns3_get_handle(netdev); 1540 struct hns3_nic_priv *priv = netdev_priv(netdev); 1541 int ret = -EIO; 1542 1543 if (h->ae_algo->ops->set_vlan_filter) 1544 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1545 1546 if (!ret) 1547 set_bit(vid, priv->active_vlans); 1548 1549 return ret; 1550 } 1551 1552 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1553 __be16 proto, u16 vid) 1554 { 1555 struct hnae3_handle *h = hns3_get_handle(netdev); 1556 struct hns3_nic_priv *priv = netdev_priv(netdev); 1557 int ret = -EIO; 1558 1559 if (h->ae_algo->ops->set_vlan_filter) 1560 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1561 1562 if (!ret) 1563 clear_bit(vid, priv->active_vlans); 1564 1565 return ret; 1566 } 1567 1568 static int hns3_restore_vlan(struct net_device *netdev) 1569 { 1570 struct hns3_nic_priv *priv = netdev_priv(netdev); 1571 int ret = 0; 1572 u16 vid; 1573 1574 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1575 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1576 if (ret) { 1577 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1578 vid, ret); 1579 return ret; 1580 } 1581 } 1582 1583 return ret; 1584 } 1585 1586 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1587 u8 qos, __be16 vlan_proto) 1588 { 1589 struct hnae3_handle *h = hns3_get_handle(netdev); 1590 int ret = -EIO; 1591 1592 if (h->ae_algo->ops->set_vf_vlan_filter) 1593 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1594 qos, vlan_proto); 1595 1596 return ret; 1597 } 1598 1599 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1600 { 1601 struct hnae3_handle *h = hns3_get_handle(netdev); 1602 int ret; 1603 1604 if (!h->ae_algo->ops->set_mtu) 1605 return -EOPNOTSUPP; 1606 1607 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1608 if (ret) 1609 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1610 ret); 1611 else 1612 netdev->mtu = new_mtu; 1613 1614 return ret; 1615 } 1616 1617 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1618 { 1619 struct hns3_nic_priv *priv = netdev_priv(ndev); 1620 struct hns3_enet_ring *tx_ring = NULL; 1621 int timeout_queue = 0; 1622 int hw_head, hw_tail; 1623 int i; 1624 1625 /* Find the stopped queue the same way the stack does */ 1626 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1627 struct netdev_queue *q; 1628 unsigned long trans_start; 1629 1630 q = netdev_get_tx_queue(ndev, i); 1631 trans_start = q->trans_start; 1632 if (netif_xmit_stopped(q) && 1633 time_after(jiffies, 1634 (trans_start + ndev->watchdog_timeo))) { 1635 timeout_queue = i; 1636 break; 1637 } 1638 } 1639 1640 if (i == ndev->num_tx_queues) { 1641 netdev_info(ndev, 1642 "no netdev TX timeout queue found, timeout count: %llu\n", 1643 priv->tx_timeout_count); 1644 return false; 1645 } 1646 1647 tx_ring = priv->ring_data[timeout_queue].ring; 1648 1649 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1650 HNS3_RING_TX_RING_HEAD_REG); 1651 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1652 HNS3_RING_TX_RING_TAIL_REG); 1653 netdev_info(ndev, 1654 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1655 priv->tx_timeout_count, 1656 timeout_queue, 1657 tx_ring->next_to_use, 1658 tx_ring->next_to_clean, 1659 hw_head, 1660 hw_tail, 1661 readl(tx_ring->tqp_vector->mask_addr)); 1662 1663 return true; 1664 } 1665 1666 static void hns3_nic_net_timeout(struct net_device *ndev) 1667 { 1668 struct hns3_nic_priv *priv = netdev_priv(ndev); 1669 struct hnae3_handle *h = priv->ae_handle; 1670 1671 if (!hns3_get_tx_timeo_queue_info(ndev)) 1672 return; 1673 1674 priv->tx_timeout_count++; 1675 1676 /* request the reset, and let the hclge to determine 1677 * which reset level should be done 1678 */ 1679 if (h->ae_algo->ops->reset_event) 1680 h->ae_algo->ops->reset_event(h->pdev, h); 1681 } 1682 1683 static const struct net_device_ops hns3_nic_netdev_ops = { 1684 .ndo_open = hns3_nic_net_open, 1685 .ndo_stop = hns3_nic_net_stop, 1686 .ndo_start_xmit = hns3_nic_net_xmit, 1687 .ndo_tx_timeout = hns3_nic_net_timeout, 1688 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1689 .ndo_do_ioctl = hns3_nic_do_ioctl, 1690 .ndo_change_mtu = hns3_nic_change_mtu, 1691 .ndo_set_features = hns3_nic_set_features, 1692 .ndo_get_stats64 = hns3_nic_get_stats64, 1693 .ndo_setup_tc = hns3_nic_setup_tc, 1694 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1695 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1696 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1697 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1698 }; 1699 1700 static bool hns3_is_phys_func(struct pci_dev *pdev) 1701 { 1702 u32 dev_id = pdev->device; 1703 1704 switch (dev_id) { 1705 case HNAE3_DEV_ID_GE: 1706 case HNAE3_DEV_ID_25GE: 1707 case HNAE3_DEV_ID_25GE_RDMA: 1708 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1709 case HNAE3_DEV_ID_50GE_RDMA: 1710 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1711 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1712 return true; 1713 case HNAE3_DEV_ID_100G_VF: 1714 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1715 return false; 1716 default: 1717 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1718 dev_id); 1719 } 1720 1721 return false; 1722 } 1723 1724 static void hns3_disable_sriov(struct pci_dev *pdev) 1725 { 1726 /* If our VFs are assigned we cannot shut down SR-IOV 1727 * without causing issues, so just leave the hardware 1728 * available but disabled 1729 */ 1730 if (pci_vfs_assigned(pdev)) { 1731 dev_warn(&pdev->dev, 1732 "disabling driver while VFs are assigned\n"); 1733 return; 1734 } 1735 1736 pci_disable_sriov(pdev); 1737 } 1738 1739 static void hns3_get_dev_capability(struct pci_dev *pdev, 1740 struct hnae3_ae_dev *ae_dev) 1741 { 1742 if (pdev->revision >= 0x21) { 1743 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1744 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1745 } 1746 } 1747 1748 /* hns3_probe - Device initialization routine 1749 * @pdev: PCI device information struct 1750 * @ent: entry in hns3_pci_tbl 1751 * 1752 * hns3_probe initializes a PF identified by a pci_dev structure. 1753 * The OS initialization, configuring of the PF private structure, 1754 * and a hardware reset occur. 1755 * 1756 * Returns 0 on success, negative on failure 1757 */ 1758 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1759 { 1760 struct hnae3_ae_dev *ae_dev; 1761 int ret; 1762 1763 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1764 GFP_KERNEL); 1765 if (!ae_dev) { 1766 ret = -ENOMEM; 1767 return ret; 1768 } 1769 1770 ae_dev->pdev = pdev; 1771 ae_dev->flag = ent->driver_data; 1772 ae_dev->dev_type = HNAE3_DEV_KNIC; 1773 ae_dev->reset_type = HNAE3_NONE_RESET; 1774 hns3_get_dev_capability(pdev, ae_dev); 1775 pci_set_drvdata(pdev, ae_dev); 1776 1777 hnae3_register_ae_dev(ae_dev); 1778 1779 return 0; 1780 } 1781 1782 /* hns3_remove - Device removal routine 1783 * @pdev: PCI device information struct 1784 */ 1785 static void hns3_remove(struct pci_dev *pdev) 1786 { 1787 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1788 1789 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1790 hns3_disable_sriov(pdev); 1791 1792 hnae3_unregister_ae_dev(ae_dev); 1793 pci_set_drvdata(pdev, NULL); 1794 } 1795 1796 /** 1797 * hns3_pci_sriov_configure 1798 * @pdev: pointer to a pci_dev structure 1799 * @num_vfs: number of VFs to allocate 1800 * 1801 * Enable or change the number of VFs. Called when the user updates the number 1802 * of VFs in sysfs. 1803 **/ 1804 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1805 { 1806 int ret; 1807 1808 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1809 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1810 return -EINVAL; 1811 } 1812 1813 if (num_vfs) { 1814 ret = pci_enable_sriov(pdev, num_vfs); 1815 if (ret) 1816 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1817 else 1818 return num_vfs; 1819 } else if (!pci_vfs_assigned(pdev)) { 1820 pci_disable_sriov(pdev); 1821 } else { 1822 dev_warn(&pdev->dev, 1823 "Unable to free VFs because some are assigned to VMs.\n"); 1824 } 1825 1826 return 0; 1827 } 1828 1829 static void hns3_shutdown(struct pci_dev *pdev) 1830 { 1831 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1832 1833 hnae3_unregister_ae_dev(ae_dev); 1834 devm_kfree(&pdev->dev, ae_dev); 1835 pci_set_drvdata(pdev, NULL); 1836 1837 if (system_state == SYSTEM_POWER_OFF) 1838 pci_set_power_state(pdev, PCI_D3hot); 1839 } 1840 1841 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1842 pci_channel_state_t state) 1843 { 1844 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1845 pci_ers_result_t ret; 1846 1847 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1848 1849 if (state == pci_channel_io_perm_failure) 1850 return PCI_ERS_RESULT_DISCONNECT; 1851 1852 if (!ae_dev) { 1853 dev_err(&pdev->dev, 1854 "Can't recover - error happened during device init\n"); 1855 return PCI_ERS_RESULT_NONE; 1856 } 1857 1858 if (ae_dev->ops->handle_hw_ras_error) 1859 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1860 else 1861 return PCI_ERS_RESULT_NONE; 1862 1863 return ret; 1864 } 1865 1866 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1867 { 1868 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1869 struct device *dev = &pdev->dev; 1870 1871 dev_info(dev, "requesting reset due to PCI error\n"); 1872 1873 /* request the reset */ 1874 if (ae_dev->ops->reset_event) { 1875 ae_dev->ops->reset_event(pdev, NULL); 1876 return PCI_ERS_RESULT_RECOVERED; 1877 } 1878 1879 return PCI_ERS_RESULT_DISCONNECT; 1880 } 1881 1882 static void hns3_reset_prepare(struct pci_dev *pdev) 1883 { 1884 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1885 1886 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1887 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1888 ae_dev->ops->flr_prepare(ae_dev); 1889 } 1890 1891 static void hns3_reset_done(struct pci_dev *pdev) 1892 { 1893 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1894 1895 dev_info(&pdev->dev, "hns3 flr done\n"); 1896 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1897 ae_dev->ops->flr_done(ae_dev); 1898 } 1899 1900 static const struct pci_error_handlers hns3_err_handler = { 1901 .error_detected = hns3_error_detected, 1902 .slot_reset = hns3_slot_reset, 1903 .reset_prepare = hns3_reset_prepare, 1904 .reset_done = hns3_reset_done, 1905 }; 1906 1907 static struct pci_driver hns3_driver = { 1908 .name = hns3_driver_name, 1909 .id_table = hns3_pci_tbl, 1910 .probe = hns3_probe, 1911 .remove = hns3_remove, 1912 .shutdown = hns3_shutdown, 1913 .sriov_configure = hns3_pci_sriov_configure, 1914 .err_handler = &hns3_err_handler, 1915 }; 1916 1917 /* set default feature to hns3 */ 1918 static void hns3_set_default_feature(struct net_device *netdev) 1919 { 1920 struct hnae3_handle *h = hns3_get_handle(netdev); 1921 struct pci_dev *pdev = h->pdev; 1922 1923 netdev->priv_flags |= IFF_UNICAST_FLT; 1924 1925 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1926 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1927 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1928 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1929 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1930 1931 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1932 1933 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1934 1935 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1936 NETIF_F_HW_VLAN_CTAG_FILTER | 1937 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1938 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1939 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1940 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1941 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1942 1943 netdev->vlan_features |= 1944 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1945 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1946 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1947 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1948 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1949 1950 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1951 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1952 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1953 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1954 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1955 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1956 1957 if (pdev->revision >= 0x21) { 1958 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | 1959 NETIF_F_GRO_HW; 1960 netdev->features |= NETIF_F_GRO_HW; 1961 1962 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1963 netdev->hw_features |= NETIF_F_NTUPLE; 1964 netdev->features |= NETIF_F_NTUPLE; 1965 } 1966 } 1967 } 1968 1969 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1970 struct hns3_desc_cb *cb) 1971 { 1972 unsigned int order = hnae3_page_order(ring); 1973 struct page *p; 1974 1975 p = dev_alloc_pages(order); 1976 if (!p) 1977 return -ENOMEM; 1978 1979 cb->priv = p; 1980 cb->page_offset = 0; 1981 cb->reuse_flag = 0; 1982 cb->buf = page_address(p); 1983 cb->length = hnae3_page_size(ring); 1984 cb->type = DESC_TYPE_PAGE; 1985 1986 return 0; 1987 } 1988 1989 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1990 struct hns3_desc_cb *cb) 1991 { 1992 if (cb->type == DESC_TYPE_SKB) 1993 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1994 else if (!HNAE3_IS_TX_RING(ring)) 1995 put_page((struct page *)cb->priv); 1996 memset(cb, 0, sizeof(*cb)); 1997 } 1998 1999 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2000 { 2001 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2002 cb->length, ring_to_dma_dir(ring)); 2003 2004 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2005 return -EIO; 2006 2007 return 0; 2008 } 2009 2010 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2011 struct hns3_desc_cb *cb) 2012 { 2013 if (cb->type == DESC_TYPE_SKB) 2014 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2015 ring_to_dma_dir(ring)); 2016 else if (cb->length) 2017 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2018 ring_to_dma_dir(ring)); 2019 } 2020 2021 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2022 { 2023 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2024 ring->desc[i].addr = 0; 2025 } 2026 2027 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2028 { 2029 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2030 2031 if (!ring->desc_cb[i].dma) 2032 return; 2033 2034 hns3_buffer_detach(ring, i); 2035 hns3_free_buffer(ring, cb); 2036 } 2037 2038 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2039 { 2040 int i; 2041 2042 for (i = 0; i < ring->desc_num; i++) 2043 hns3_free_buffer_detach(ring, i); 2044 } 2045 2046 /* free desc along with its attached buffer */ 2047 static void hns3_free_desc(struct hns3_enet_ring *ring) 2048 { 2049 int size = ring->desc_num * sizeof(ring->desc[0]); 2050 2051 hns3_free_buffers(ring); 2052 2053 if (ring->desc) { 2054 dma_free_coherent(ring_to_dev(ring), size, 2055 ring->desc, ring->desc_dma_addr); 2056 ring->desc = NULL; 2057 } 2058 } 2059 2060 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2061 { 2062 int size = ring->desc_num * sizeof(ring->desc[0]); 2063 2064 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2065 &ring->desc_dma_addr, GFP_KERNEL); 2066 if (!ring->desc) 2067 return -ENOMEM; 2068 2069 return 0; 2070 } 2071 2072 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2073 struct hns3_desc_cb *cb) 2074 { 2075 int ret; 2076 2077 ret = hns3_alloc_buffer(ring, cb); 2078 if (ret) 2079 goto out; 2080 2081 ret = hns3_map_buffer(ring, cb); 2082 if (ret) 2083 goto out_with_buf; 2084 2085 return 0; 2086 2087 out_with_buf: 2088 hns3_free_buffer(ring, cb); 2089 out: 2090 return ret; 2091 } 2092 2093 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2094 { 2095 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2096 2097 if (ret) 2098 return ret; 2099 2100 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2101 2102 return 0; 2103 } 2104 2105 /* Allocate memory for raw pkg, and map with dma */ 2106 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2107 { 2108 int i, j, ret; 2109 2110 for (i = 0; i < ring->desc_num; i++) { 2111 ret = hns3_alloc_buffer_attach(ring, i); 2112 if (ret) 2113 goto out_buffer_fail; 2114 } 2115 2116 return 0; 2117 2118 out_buffer_fail: 2119 for (j = i - 1; j >= 0; j--) 2120 hns3_free_buffer_detach(ring, j); 2121 return ret; 2122 } 2123 2124 /* detach a in-used buffer and replace with a reserved one */ 2125 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2126 struct hns3_desc_cb *res_cb) 2127 { 2128 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2129 ring->desc_cb[i] = *res_cb; 2130 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2131 ring->desc[i].rx.bd_base_info = 0; 2132 } 2133 2134 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2135 { 2136 ring->desc_cb[i].reuse_flag = 0; 2137 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2138 + ring->desc_cb[i].page_offset); 2139 ring->desc[i].rx.bd_base_info = 0; 2140 } 2141 2142 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2143 int *pkts) 2144 { 2145 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2146 2147 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2148 (*bytes) += desc_cb->length; 2149 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2150 hns3_free_buffer_detach(ring, ring->next_to_clean); 2151 2152 ring_ptr_move_fw(ring, next_to_clean); 2153 } 2154 2155 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2156 { 2157 int u = ring->next_to_use; 2158 int c = ring->next_to_clean; 2159 2160 if (unlikely(h > ring->desc_num)) 2161 return 0; 2162 2163 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2164 } 2165 2166 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2167 { 2168 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2169 struct hns3_nic_priv *priv = netdev_priv(netdev); 2170 struct netdev_queue *dev_queue; 2171 int bytes, pkts; 2172 int head; 2173 2174 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2175 rmb(); /* Make sure head is ready before touch any data */ 2176 2177 if (is_ring_empty(ring) || head == ring->next_to_clean) 2178 return; /* no data to poll */ 2179 2180 if (unlikely(!is_valid_clean_head(ring, head))) { 2181 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2182 ring->next_to_use, ring->next_to_clean); 2183 2184 u64_stats_update_begin(&ring->syncp); 2185 ring->stats.io_err_cnt++; 2186 u64_stats_update_end(&ring->syncp); 2187 return; 2188 } 2189 2190 bytes = 0; 2191 pkts = 0; 2192 while (head != ring->next_to_clean) { 2193 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2194 /* Issue prefetch for next Tx descriptor */ 2195 prefetch(&ring->desc_cb[ring->next_to_clean]); 2196 } 2197 2198 ring->tqp_vector->tx_group.total_bytes += bytes; 2199 ring->tqp_vector->tx_group.total_packets += pkts; 2200 2201 u64_stats_update_begin(&ring->syncp); 2202 ring->stats.tx_bytes += bytes; 2203 ring->stats.tx_pkts += pkts; 2204 u64_stats_update_end(&ring->syncp); 2205 2206 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2207 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2208 2209 if (unlikely(pkts && netif_carrier_ok(netdev) && 2210 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2211 /* Make sure that anybody stopping the queue after this 2212 * sees the new next_to_clean. 2213 */ 2214 smp_mb(); 2215 if (netif_tx_queue_stopped(dev_queue) && 2216 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2217 netif_tx_wake_queue(dev_queue); 2218 ring->stats.restart_queue++; 2219 } 2220 } 2221 } 2222 2223 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2224 { 2225 int ntc = ring->next_to_clean; 2226 int ntu = ring->next_to_use; 2227 2228 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2229 } 2230 2231 static void 2232 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2233 { 2234 struct hns3_desc_cb *desc_cb; 2235 struct hns3_desc_cb res_cbs; 2236 int i, ret; 2237 2238 for (i = 0; i < cleand_count; i++) { 2239 desc_cb = &ring->desc_cb[ring->next_to_use]; 2240 if (desc_cb->reuse_flag) { 2241 u64_stats_update_begin(&ring->syncp); 2242 ring->stats.reuse_pg_cnt++; 2243 u64_stats_update_end(&ring->syncp); 2244 2245 hns3_reuse_buffer(ring, ring->next_to_use); 2246 } else { 2247 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2248 if (ret) { 2249 u64_stats_update_begin(&ring->syncp); 2250 ring->stats.sw_err_cnt++; 2251 u64_stats_update_end(&ring->syncp); 2252 2253 netdev_err(ring->tqp->handle->kinfo.netdev, 2254 "hnae reserve buffer map failed.\n"); 2255 break; 2256 } 2257 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2258 } 2259 2260 ring_ptr_move_fw(ring, next_to_use); 2261 } 2262 2263 wmb(); /* Make all data has been write before submit */ 2264 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2265 } 2266 2267 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2268 struct hns3_enet_ring *ring, int pull_len, 2269 struct hns3_desc_cb *desc_cb) 2270 { 2271 struct hns3_desc *desc; 2272 u32 truesize; 2273 int size; 2274 int last_offset; 2275 bool twobufs; 2276 2277 twobufs = ((PAGE_SIZE < 8192) && 2278 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2279 2280 desc = &ring->desc[ring->next_to_clean]; 2281 size = le16_to_cpu(desc->rx.size); 2282 2283 truesize = hnae3_buf_size(ring); 2284 2285 if (!twobufs) 2286 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2287 2288 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2289 size - pull_len, truesize); 2290 2291 /* Avoid re-using remote pages,flag default unreuse */ 2292 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2293 return; 2294 2295 if (twobufs) { 2296 /* If we are only owner of page we can reuse it */ 2297 if (likely(page_count(desc_cb->priv) == 1)) { 2298 /* Flip page offset to other buffer */ 2299 desc_cb->page_offset ^= truesize; 2300 2301 desc_cb->reuse_flag = 1; 2302 /* bump ref count on page before it is given*/ 2303 get_page(desc_cb->priv); 2304 } 2305 return; 2306 } 2307 2308 /* Move offset up to the next cache line */ 2309 desc_cb->page_offset += truesize; 2310 2311 if (desc_cb->page_offset <= last_offset) { 2312 desc_cb->reuse_flag = 1; 2313 /* Bump ref count on page before it is given*/ 2314 get_page(desc_cb->priv); 2315 } 2316 } 2317 2318 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2319 struct hns3_desc *desc) 2320 { 2321 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2322 int l3_type, l4_type; 2323 u32 bd_base_info; 2324 int ol4_type; 2325 u32 l234info; 2326 2327 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2328 l234info = le32_to_cpu(desc->rx.l234_info); 2329 2330 skb->ip_summed = CHECKSUM_NONE; 2331 2332 skb_checksum_none_assert(skb); 2333 2334 if (!(netdev->features & NETIF_F_RXCSUM)) 2335 return; 2336 2337 /* We MUST enable hardware checksum before enabling hardware GRO */ 2338 if (skb_shinfo(skb)->gso_size) { 2339 skb->ip_summed = CHECKSUM_UNNECESSARY; 2340 return; 2341 } 2342 2343 /* check if hardware has done checksum */ 2344 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2345 return; 2346 2347 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2348 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2349 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2350 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2351 u64_stats_update_begin(&ring->syncp); 2352 ring->stats.l3l4_csum_err++; 2353 u64_stats_update_end(&ring->syncp); 2354 2355 return; 2356 } 2357 2358 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2359 HNS3_RXD_L3ID_S); 2360 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2361 HNS3_RXD_L4ID_S); 2362 2363 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2364 HNS3_RXD_OL4ID_S); 2365 switch (ol4_type) { 2366 case HNS3_OL4_TYPE_MAC_IN_UDP: 2367 case HNS3_OL4_TYPE_NVGRE: 2368 skb->csum_level = 1; 2369 /* fall through */ 2370 case HNS3_OL4_TYPE_NO_TUN: 2371 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2372 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2373 l3_type == HNS3_L3_TYPE_IPV6) && 2374 (l4_type == HNS3_L4_TYPE_UDP || 2375 l4_type == HNS3_L4_TYPE_TCP || 2376 l4_type == HNS3_L4_TYPE_SCTP)) 2377 skb->ip_summed = CHECKSUM_UNNECESSARY; 2378 break; 2379 default: 2380 break; 2381 } 2382 } 2383 2384 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2385 { 2386 if (skb_has_frag_list(skb)) 2387 napi_gro_flush(&ring->tqp_vector->napi, false); 2388 2389 napi_gro_receive(&ring->tqp_vector->napi, skb); 2390 } 2391 2392 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2393 struct hns3_desc *desc, u32 l234info, 2394 u16 *vlan_tag) 2395 { 2396 struct pci_dev *pdev = ring->tqp->handle->pdev; 2397 2398 if (pdev->revision == 0x20) { 2399 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2400 if (!(*vlan_tag & VLAN_VID_MASK)) 2401 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2402 2403 return (*vlan_tag != 0); 2404 } 2405 2406 #define HNS3_STRP_OUTER_VLAN 0x1 2407 #define HNS3_STRP_INNER_VLAN 0x2 2408 2409 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2410 HNS3_RXD_STRP_TAGP_S)) { 2411 case HNS3_STRP_OUTER_VLAN: 2412 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2413 return true; 2414 case HNS3_STRP_INNER_VLAN: 2415 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2416 return true; 2417 default: 2418 return false; 2419 } 2420 } 2421 2422 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2423 unsigned char *va) 2424 { 2425 #define HNS3_NEED_ADD_FRAG 1 2426 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2427 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2428 struct sk_buff *skb; 2429 2430 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2431 skb = ring->skb; 2432 if (unlikely(!skb)) { 2433 netdev_err(netdev, "alloc rx skb fail\n"); 2434 2435 u64_stats_update_begin(&ring->syncp); 2436 ring->stats.sw_err_cnt++; 2437 u64_stats_update_end(&ring->syncp); 2438 2439 return -ENOMEM; 2440 } 2441 2442 prefetchw(skb->data); 2443 2444 ring->pending_buf = 1; 2445 ring->frag_num = 0; 2446 ring->tail_skb = NULL; 2447 if (length <= HNS3_RX_HEAD_SIZE) { 2448 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2449 2450 /* We can reuse buffer as-is, just make sure it is local */ 2451 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2452 desc_cb->reuse_flag = 1; 2453 else /* This page cannot be reused so discard it */ 2454 put_page(desc_cb->priv); 2455 2456 ring_ptr_move_fw(ring, next_to_clean); 2457 return 0; 2458 } 2459 u64_stats_update_begin(&ring->syncp); 2460 ring->stats.seg_pkt_cnt++; 2461 u64_stats_update_end(&ring->syncp); 2462 2463 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2464 __skb_put(skb, ring->pull_len); 2465 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2466 desc_cb); 2467 ring_ptr_move_fw(ring, next_to_clean); 2468 2469 return HNS3_NEED_ADD_FRAG; 2470 } 2471 2472 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2473 struct sk_buff **out_skb, bool pending) 2474 { 2475 struct sk_buff *skb = *out_skb; 2476 struct sk_buff *head_skb = *out_skb; 2477 struct sk_buff *new_skb; 2478 struct hns3_desc_cb *desc_cb; 2479 struct hns3_desc *pre_desc; 2480 u32 bd_base_info; 2481 int pre_bd; 2482 2483 /* if there is pending bd, the SW param next_to_clean has moved 2484 * to next and the next is NULL 2485 */ 2486 if (pending) { 2487 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2488 ring->desc_num; 2489 pre_desc = &ring->desc[pre_bd]; 2490 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2491 } else { 2492 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2493 } 2494 2495 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2496 desc = &ring->desc[ring->next_to_clean]; 2497 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2498 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2499 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)) 2500 return -ENXIO; 2501 2502 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2503 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2504 HNS3_RX_HEAD_SIZE); 2505 if (unlikely(!new_skb)) { 2506 netdev_err(ring->tqp->handle->kinfo.netdev, 2507 "alloc rx skb frag fail\n"); 2508 return -ENXIO; 2509 } 2510 ring->frag_num = 0; 2511 2512 if (ring->tail_skb) { 2513 ring->tail_skb->next = new_skb; 2514 ring->tail_skb = new_skb; 2515 } else { 2516 skb_shinfo(skb)->frag_list = new_skb; 2517 ring->tail_skb = new_skb; 2518 } 2519 } 2520 2521 if (ring->tail_skb) { 2522 head_skb->truesize += hnae3_buf_size(ring); 2523 head_skb->data_len += le16_to_cpu(desc->rx.size); 2524 head_skb->len += le16_to_cpu(desc->rx.size); 2525 skb = ring->tail_skb; 2526 } 2527 2528 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2529 ring_ptr_move_fw(ring, next_to_clean); 2530 ring->pending_buf++; 2531 } 2532 2533 return 0; 2534 } 2535 2536 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info, 2537 u32 bd_base_info) 2538 { 2539 u16 gro_count; 2540 u32 l3_type; 2541 2542 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2543 HNS3_RXD_GRO_COUNT_S); 2544 /* if there is no HW GRO, do not set gro params */ 2545 if (!gro_count) 2546 return; 2547 2548 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count 2549 * to skb_shinfo(skb)->gso_segs 2550 */ 2551 NAPI_GRO_CB(skb)->count = gro_count; 2552 2553 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2554 HNS3_RXD_L3ID_S); 2555 if (l3_type == HNS3_L3_TYPE_IPV4) 2556 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2557 else if (l3_type == HNS3_L3_TYPE_IPV6) 2558 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2559 else 2560 return; 2561 2562 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2563 HNS3_RXD_GRO_SIZE_M, 2564 HNS3_RXD_GRO_SIZE_S); 2565 if (skb_shinfo(skb)->gso_size) 2566 tcp_gro_complete(skb); 2567 } 2568 2569 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2570 struct sk_buff *skb) 2571 { 2572 struct hnae3_handle *handle = ring->tqp->handle; 2573 enum pkt_hash_types rss_type; 2574 struct hns3_desc *desc; 2575 int last_bd; 2576 2577 /* When driver handle the rss type, ring->next_to_clean indicates the 2578 * first descriptor of next packet, need -1 here. 2579 */ 2580 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num; 2581 desc = &ring->desc[last_bd]; 2582 2583 if (le32_to_cpu(desc->rx.rss_hash)) 2584 rss_type = handle->kinfo.rss_type; 2585 else 2586 rss_type = PKT_HASH_TYPE_NONE; 2587 2588 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2589 } 2590 2591 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2592 struct sk_buff **out_skb) 2593 { 2594 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2595 enum hns3_pkt_l2t_type l2_frame_type; 2596 struct sk_buff *skb = ring->skb; 2597 struct hns3_desc_cb *desc_cb; 2598 struct hns3_desc *desc; 2599 u32 bd_base_info; 2600 u32 l234info; 2601 int length; 2602 int ret; 2603 2604 desc = &ring->desc[ring->next_to_clean]; 2605 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2606 2607 prefetch(desc); 2608 2609 length = le16_to_cpu(desc->rx.size); 2610 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2611 2612 /* Check valid BD */ 2613 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2614 return -ENXIO; 2615 2616 if (!skb) 2617 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2618 2619 /* Prefetch first cache line of first page 2620 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2621 * line size is 64B so need to prefetch twice to make it 128B. But in 2622 * actual we can have greater size of caches with 128B Level 1 cache 2623 * lines. In such a case, single fetch would suffice to cache in the 2624 * relevant part of the header. 2625 */ 2626 prefetch(ring->va); 2627 #if L1_CACHE_BYTES < 128 2628 prefetch(ring->va + L1_CACHE_BYTES); 2629 #endif 2630 2631 if (!skb) { 2632 ret = hns3_alloc_skb(ring, length, ring->va); 2633 *out_skb = skb = ring->skb; 2634 2635 if (ret < 0) /* alloc buffer fail */ 2636 return ret; 2637 if (ret > 0) { /* need add frag */ 2638 ret = hns3_add_frag(ring, desc, &skb, false); 2639 if (ret) 2640 return ret; 2641 2642 /* As the head data may be changed when GRO enable, copy 2643 * the head data in after other data rx completed 2644 */ 2645 memcpy(skb->data, ring->va, 2646 ALIGN(ring->pull_len, sizeof(long))); 2647 } 2648 } else { 2649 ret = hns3_add_frag(ring, desc, &skb, true); 2650 if (ret) 2651 return ret; 2652 2653 /* As the head data may be changed when GRO enable, copy 2654 * the head data in after other data rx completed 2655 */ 2656 memcpy(skb->data, ring->va, 2657 ALIGN(ring->pull_len, sizeof(long))); 2658 } 2659 2660 l234info = le32_to_cpu(desc->rx.l234_info); 2661 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2662 2663 /* Based on hw strategy, the tag offloaded will be stored at 2664 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2665 * in one layer tag case. 2666 */ 2667 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2668 u16 vlan_tag; 2669 2670 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2671 __vlan_hwaccel_put_tag(skb, 2672 htons(ETH_P_8021Q), 2673 vlan_tag); 2674 } 2675 2676 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2677 u64_stats_update_begin(&ring->syncp); 2678 ring->stats.non_vld_descs++; 2679 u64_stats_update_end(&ring->syncp); 2680 2681 dev_kfree_skb_any(skb); 2682 return -EINVAL; 2683 } 2684 2685 if (unlikely((!desc->rx.pkt_len) || 2686 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2687 u64_stats_update_begin(&ring->syncp); 2688 ring->stats.err_pkt_len++; 2689 u64_stats_update_end(&ring->syncp); 2690 2691 dev_kfree_skb_any(skb); 2692 return -EFAULT; 2693 } 2694 2695 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2696 u64_stats_update_begin(&ring->syncp); 2697 ring->stats.l2_err++; 2698 u64_stats_update_end(&ring->syncp); 2699 2700 dev_kfree_skb_any(skb); 2701 return -EFAULT; 2702 } 2703 2704 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2705 HNS3_RXD_DMAC_S); 2706 u64_stats_update_begin(&ring->syncp); 2707 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2708 ring->stats.rx_multicast++; 2709 2710 ring->stats.rx_pkts++; 2711 ring->stats.rx_bytes += skb->len; 2712 u64_stats_update_end(&ring->syncp); 2713 2714 ring->tqp_vector->rx_group.total_bytes += skb->len; 2715 2716 /* This is needed in order to enable forwarding support */ 2717 hns3_set_gro_param(skb, l234info, bd_base_info); 2718 2719 hns3_rx_checksum(ring, skb, desc); 2720 *out_skb = skb; 2721 hns3_set_rx_skb_rss_type(ring, skb); 2722 2723 return 0; 2724 } 2725 2726 int hns3_clean_rx_ring( 2727 struct hns3_enet_ring *ring, int budget, 2728 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2729 { 2730 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2731 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2732 int recv_pkts, recv_bds, clean_count, err; 2733 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2734 struct sk_buff *skb = ring->skb; 2735 int num; 2736 2737 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2738 rmb(); /* Make sure num taken effect before the other data is touched */ 2739 2740 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2741 num -= unused_count; 2742 2743 while (recv_pkts < budget && recv_bds < num) { 2744 /* Reuse or realloc buffers */ 2745 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2746 hns3_nic_alloc_rx_buffers(ring, 2747 clean_count + unused_count); 2748 clean_count = 0; 2749 unused_count = hns3_desc_unused(ring) - 2750 ring->pending_buf; 2751 } 2752 2753 /* Poll one pkt */ 2754 err = hns3_handle_rx_bd(ring, &skb); 2755 if (unlikely(!skb)) /* This fault cannot be repaired */ 2756 goto out; 2757 2758 if (err == -ENXIO) { /* Do not get FE for the packet */ 2759 goto out; 2760 } else if (unlikely(err)) { /* Do jump the err */ 2761 recv_bds += ring->pending_buf; 2762 clean_count += ring->pending_buf; 2763 ring->skb = NULL; 2764 ring->pending_buf = 0; 2765 continue; 2766 } 2767 2768 /* Do update ip stack process */ 2769 skb->protocol = eth_type_trans(skb, netdev); 2770 rx_fn(ring, skb); 2771 recv_bds += ring->pending_buf; 2772 clean_count += ring->pending_buf; 2773 ring->skb = NULL; 2774 ring->pending_buf = 0; 2775 2776 recv_pkts++; 2777 } 2778 2779 out: 2780 /* Make all data has been write before submit */ 2781 if (clean_count + unused_count > 0) 2782 hns3_nic_alloc_rx_buffers(ring, 2783 clean_count + unused_count); 2784 2785 return recv_pkts; 2786 } 2787 2788 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2789 { 2790 struct hns3_enet_tqp_vector *tqp_vector = 2791 ring_group->ring->tqp_vector; 2792 enum hns3_flow_level_range new_flow_level; 2793 int packets_per_msecs; 2794 int bytes_per_msecs; 2795 u32 time_passed_ms; 2796 u16 new_int_gl; 2797 2798 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2799 return false; 2800 2801 if (ring_group->total_packets == 0) { 2802 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2803 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2804 return true; 2805 } 2806 2807 /* Simple throttlerate management 2808 * 0-10MB/s lower (50000 ints/s) 2809 * 10-20MB/s middle (20000 ints/s) 2810 * 20-1249MB/s high (18000 ints/s) 2811 * > 40000pps ultra (8000 ints/s) 2812 */ 2813 new_flow_level = ring_group->coal.flow_level; 2814 new_int_gl = ring_group->coal.int_gl; 2815 time_passed_ms = 2816 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2817 2818 if (!time_passed_ms) 2819 return false; 2820 2821 do_div(ring_group->total_packets, time_passed_ms); 2822 packets_per_msecs = ring_group->total_packets; 2823 2824 do_div(ring_group->total_bytes, time_passed_ms); 2825 bytes_per_msecs = ring_group->total_bytes; 2826 2827 #define HNS3_RX_LOW_BYTE_RATE 10000 2828 #define HNS3_RX_MID_BYTE_RATE 20000 2829 2830 switch (new_flow_level) { 2831 case HNS3_FLOW_LOW: 2832 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2833 new_flow_level = HNS3_FLOW_MID; 2834 break; 2835 case HNS3_FLOW_MID: 2836 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2837 new_flow_level = HNS3_FLOW_HIGH; 2838 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2839 new_flow_level = HNS3_FLOW_LOW; 2840 break; 2841 case HNS3_FLOW_HIGH: 2842 case HNS3_FLOW_ULTRA: 2843 default: 2844 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2845 new_flow_level = HNS3_FLOW_MID; 2846 break; 2847 } 2848 2849 #define HNS3_RX_ULTRA_PACKET_RATE 40 2850 2851 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2852 &tqp_vector->rx_group == ring_group) 2853 new_flow_level = HNS3_FLOW_ULTRA; 2854 2855 switch (new_flow_level) { 2856 case HNS3_FLOW_LOW: 2857 new_int_gl = HNS3_INT_GL_50K; 2858 break; 2859 case HNS3_FLOW_MID: 2860 new_int_gl = HNS3_INT_GL_20K; 2861 break; 2862 case HNS3_FLOW_HIGH: 2863 new_int_gl = HNS3_INT_GL_18K; 2864 break; 2865 case HNS3_FLOW_ULTRA: 2866 new_int_gl = HNS3_INT_GL_8K; 2867 break; 2868 default: 2869 break; 2870 } 2871 2872 ring_group->total_bytes = 0; 2873 ring_group->total_packets = 0; 2874 ring_group->coal.flow_level = new_flow_level; 2875 if (new_int_gl != ring_group->coal.int_gl) { 2876 ring_group->coal.int_gl = new_int_gl; 2877 return true; 2878 } 2879 return false; 2880 } 2881 2882 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2883 { 2884 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2885 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2886 bool rx_update, tx_update; 2887 2888 /* update param every 1000ms */ 2889 if (time_before(jiffies, 2890 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 2891 return; 2892 2893 if (rx_group->coal.gl_adapt_enable) { 2894 rx_update = hns3_get_new_int_gl(rx_group); 2895 if (rx_update) 2896 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2897 rx_group->coal.int_gl); 2898 } 2899 2900 if (tx_group->coal.gl_adapt_enable) { 2901 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2902 if (tx_update) 2903 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2904 tx_group->coal.int_gl); 2905 } 2906 2907 tqp_vector->last_jiffies = jiffies; 2908 } 2909 2910 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2911 { 2912 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2913 struct hns3_enet_ring *ring; 2914 int rx_pkt_total = 0; 2915 2916 struct hns3_enet_tqp_vector *tqp_vector = 2917 container_of(napi, struct hns3_enet_tqp_vector, napi); 2918 bool clean_complete = true; 2919 int rx_budget; 2920 2921 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2922 napi_complete(napi); 2923 return 0; 2924 } 2925 2926 /* Since the actual Tx work is minimal, we can give the Tx a larger 2927 * budget and be more aggressive about cleaning up the Tx descriptors. 2928 */ 2929 hns3_for_each_ring(ring, tqp_vector->tx_group) 2930 hns3_clean_tx_ring(ring); 2931 2932 /* make sure rx ring budget not smaller than 1 */ 2933 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2934 2935 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2936 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2937 hns3_rx_skb); 2938 2939 if (rx_cleaned >= rx_budget) 2940 clean_complete = false; 2941 2942 rx_pkt_total += rx_cleaned; 2943 } 2944 2945 tqp_vector->rx_group.total_packets += rx_pkt_total; 2946 2947 if (!clean_complete) 2948 return budget; 2949 2950 if (napi_complete(napi) && 2951 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2952 hns3_update_new_int_gl(tqp_vector); 2953 hns3_mask_vector_irq(tqp_vector, 1); 2954 } 2955 2956 return rx_pkt_total; 2957 } 2958 2959 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2960 struct hnae3_ring_chain_node *head) 2961 { 2962 struct pci_dev *pdev = tqp_vector->handle->pdev; 2963 struct hnae3_ring_chain_node *cur_chain = head; 2964 struct hnae3_ring_chain_node *chain; 2965 struct hns3_enet_ring *tx_ring; 2966 struct hns3_enet_ring *rx_ring; 2967 2968 tx_ring = tqp_vector->tx_group.ring; 2969 if (tx_ring) { 2970 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2971 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2972 HNAE3_RING_TYPE_TX); 2973 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2974 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2975 2976 cur_chain->next = NULL; 2977 2978 while (tx_ring->next) { 2979 tx_ring = tx_ring->next; 2980 2981 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2982 GFP_KERNEL); 2983 if (!chain) 2984 goto err_free_chain; 2985 2986 cur_chain->next = chain; 2987 chain->tqp_index = tx_ring->tqp->tqp_index; 2988 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2989 HNAE3_RING_TYPE_TX); 2990 hnae3_set_field(chain->int_gl_idx, 2991 HNAE3_RING_GL_IDX_M, 2992 HNAE3_RING_GL_IDX_S, 2993 HNAE3_RING_GL_TX); 2994 2995 cur_chain = chain; 2996 } 2997 } 2998 2999 rx_ring = tqp_vector->rx_group.ring; 3000 if (!tx_ring && rx_ring) { 3001 cur_chain->next = NULL; 3002 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3003 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3004 HNAE3_RING_TYPE_RX); 3005 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3006 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3007 3008 rx_ring = rx_ring->next; 3009 } 3010 3011 while (rx_ring) { 3012 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3013 if (!chain) 3014 goto err_free_chain; 3015 3016 cur_chain->next = chain; 3017 chain->tqp_index = rx_ring->tqp->tqp_index; 3018 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3019 HNAE3_RING_TYPE_RX); 3020 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3021 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3022 3023 cur_chain = chain; 3024 3025 rx_ring = rx_ring->next; 3026 } 3027 3028 return 0; 3029 3030 err_free_chain: 3031 cur_chain = head->next; 3032 while (cur_chain) { 3033 chain = cur_chain->next; 3034 devm_kfree(&pdev->dev, cur_chain); 3035 cur_chain = chain; 3036 } 3037 head->next = NULL; 3038 3039 return -ENOMEM; 3040 } 3041 3042 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3043 struct hnae3_ring_chain_node *head) 3044 { 3045 struct pci_dev *pdev = tqp_vector->handle->pdev; 3046 struct hnae3_ring_chain_node *chain_tmp, *chain; 3047 3048 chain = head->next; 3049 3050 while (chain) { 3051 chain_tmp = chain->next; 3052 devm_kfree(&pdev->dev, chain); 3053 chain = chain_tmp; 3054 } 3055 } 3056 3057 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3058 struct hns3_enet_ring *ring) 3059 { 3060 ring->next = group->ring; 3061 group->ring = ring; 3062 3063 group->count++; 3064 } 3065 3066 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3067 { 3068 struct pci_dev *pdev = priv->ae_handle->pdev; 3069 struct hns3_enet_tqp_vector *tqp_vector; 3070 int num_vectors = priv->vector_num; 3071 int numa_node; 3072 int vector_i; 3073 3074 numa_node = dev_to_node(&pdev->dev); 3075 3076 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3077 tqp_vector = &priv->tqp_vector[vector_i]; 3078 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3079 &tqp_vector->affinity_mask); 3080 } 3081 } 3082 3083 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3084 { 3085 struct hnae3_ring_chain_node vector_ring_chain; 3086 struct hnae3_handle *h = priv->ae_handle; 3087 struct hns3_enet_tqp_vector *tqp_vector; 3088 int ret = 0; 3089 int i; 3090 3091 hns3_nic_set_cpumask(priv); 3092 3093 for (i = 0; i < priv->vector_num; i++) { 3094 tqp_vector = &priv->tqp_vector[i]; 3095 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3096 tqp_vector->num_tqps = 0; 3097 } 3098 3099 for (i = 0; i < h->kinfo.num_tqps; i++) { 3100 u16 vector_i = i % priv->vector_num; 3101 u16 tqp_num = h->kinfo.num_tqps; 3102 3103 tqp_vector = &priv->tqp_vector[vector_i]; 3104 3105 hns3_add_ring_to_group(&tqp_vector->tx_group, 3106 priv->ring_data[i].ring); 3107 3108 hns3_add_ring_to_group(&tqp_vector->rx_group, 3109 priv->ring_data[i + tqp_num].ring); 3110 3111 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3112 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3113 tqp_vector->num_tqps++; 3114 } 3115 3116 for (i = 0; i < priv->vector_num; i++) { 3117 tqp_vector = &priv->tqp_vector[i]; 3118 3119 tqp_vector->rx_group.total_bytes = 0; 3120 tqp_vector->rx_group.total_packets = 0; 3121 tqp_vector->tx_group.total_bytes = 0; 3122 tqp_vector->tx_group.total_packets = 0; 3123 tqp_vector->handle = h; 3124 3125 ret = hns3_get_vector_ring_chain(tqp_vector, 3126 &vector_ring_chain); 3127 if (ret) 3128 goto map_ring_fail; 3129 3130 ret = h->ae_algo->ops->map_ring_to_vector(h, 3131 tqp_vector->vector_irq, &vector_ring_chain); 3132 3133 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3134 3135 if (ret) 3136 goto map_ring_fail; 3137 3138 netif_napi_add(priv->netdev, &tqp_vector->napi, 3139 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3140 } 3141 3142 return 0; 3143 3144 map_ring_fail: 3145 while (i--) 3146 netif_napi_del(&priv->tqp_vector[i].napi); 3147 3148 return ret; 3149 } 3150 3151 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3152 { 3153 #define HNS3_VECTOR_PF_MAX_NUM 64 3154 3155 struct hnae3_handle *h = priv->ae_handle; 3156 struct hns3_enet_tqp_vector *tqp_vector; 3157 struct hnae3_vector_info *vector; 3158 struct pci_dev *pdev = h->pdev; 3159 u16 tqp_num = h->kinfo.num_tqps; 3160 u16 vector_num; 3161 int ret = 0; 3162 u16 i; 3163 3164 /* RSS size, cpu online and vector_num should be the same */ 3165 /* Should consider 2p/4p later */ 3166 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3167 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3168 3169 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3170 GFP_KERNEL); 3171 if (!vector) 3172 return -ENOMEM; 3173 3174 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3175 3176 priv->vector_num = vector_num; 3177 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3178 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3179 GFP_KERNEL); 3180 if (!priv->tqp_vector) { 3181 ret = -ENOMEM; 3182 goto out; 3183 } 3184 3185 for (i = 0; i < priv->vector_num; i++) { 3186 tqp_vector = &priv->tqp_vector[i]; 3187 tqp_vector->idx = i; 3188 tqp_vector->mask_addr = vector[i].io_addr; 3189 tqp_vector->vector_irq = vector[i].vector; 3190 hns3_vector_gl_rl_init(tqp_vector, priv); 3191 } 3192 3193 out: 3194 devm_kfree(&pdev->dev, vector); 3195 return ret; 3196 } 3197 3198 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3199 { 3200 group->ring = NULL; 3201 group->count = 0; 3202 } 3203 3204 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3205 { 3206 struct hnae3_ring_chain_node vector_ring_chain; 3207 struct hnae3_handle *h = priv->ae_handle; 3208 struct hns3_enet_tqp_vector *tqp_vector; 3209 int i, ret; 3210 3211 for (i = 0; i < priv->vector_num; i++) { 3212 tqp_vector = &priv->tqp_vector[i]; 3213 3214 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3215 continue; 3216 3217 ret = hns3_get_vector_ring_chain(tqp_vector, 3218 &vector_ring_chain); 3219 if (ret) 3220 return ret; 3221 3222 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 3223 tqp_vector->vector_irq, &vector_ring_chain); 3224 if (ret) 3225 return ret; 3226 3227 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3228 3229 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3230 irq_set_affinity_notifier(tqp_vector->vector_irq, 3231 NULL); 3232 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3233 free_irq(tqp_vector->vector_irq, tqp_vector); 3234 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3235 } 3236 3237 hns3_clear_ring_group(&tqp_vector->rx_group); 3238 hns3_clear_ring_group(&tqp_vector->tx_group); 3239 netif_napi_del(&priv->tqp_vector[i].napi); 3240 } 3241 3242 return 0; 3243 } 3244 3245 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3246 { 3247 struct hnae3_handle *h = priv->ae_handle; 3248 struct pci_dev *pdev = h->pdev; 3249 int i, ret; 3250 3251 for (i = 0; i < priv->vector_num; i++) { 3252 struct hns3_enet_tqp_vector *tqp_vector; 3253 3254 tqp_vector = &priv->tqp_vector[i]; 3255 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3256 if (ret) 3257 return ret; 3258 } 3259 3260 devm_kfree(&pdev->dev, priv->tqp_vector); 3261 return 0; 3262 } 3263 3264 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3265 int ring_type) 3266 { 3267 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3268 int queue_num = priv->ae_handle->kinfo.num_tqps; 3269 int desc_num = priv->ae_handle->kinfo.num_desc; 3270 struct pci_dev *pdev = priv->ae_handle->pdev; 3271 struct hns3_enet_ring *ring; 3272 3273 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3274 if (!ring) 3275 return -ENOMEM; 3276 3277 if (ring_type == HNAE3_RING_TYPE_TX) { 3278 ring_data[q->tqp_index].ring = ring; 3279 ring_data[q->tqp_index].queue_index = q->tqp_index; 3280 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3281 } else { 3282 ring_data[q->tqp_index + queue_num].ring = ring; 3283 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3284 ring->io_base = q->io_base; 3285 } 3286 3287 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3288 3289 ring->tqp = q; 3290 ring->desc = NULL; 3291 ring->desc_cb = NULL; 3292 ring->dev = priv->dev; 3293 ring->desc_dma_addr = 0; 3294 ring->buf_size = q->buf_size; 3295 ring->desc_num = desc_num; 3296 ring->next_to_use = 0; 3297 ring->next_to_clean = 0; 3298 3299 return 0; 3300 } 3301 3302 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3303 struct hns3_nic_priv *priv) 3304 { 3305 int ret; 3306 3307 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3308 if (ret) 3309 return ret; 3310 3311 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3312 if (ret) { 3313 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3314 return ret; 3315 } 3316 3317 return 0; 3318 } 3319 3320 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3321 { 3322 struct hnae3_handle *h = priv->ae_handle; 3323 struct pci_dev *pdev = h->pdev; 3324 int i, ret; 3325 3326 priv->ring_data = devm_kzalloc(&pdev->dev, 3327 array3_size(h->kinfo.num_tqps, 3328 sizeof(*priv->ring_data), 3329 2), 3330 GFP_KERNEL); 3331 if (!priv->ring_data) 3332 return -ENOMEM; 3333 3334 for (i = 0; i < h->kinfo.num_tqps; i++) { 3335 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3336 if (ret) 3337 goto err; 3338 } 3339 3340 return 0; 3341 err: 3342 while (i--) { 3343 devm_kfree(priv->dev, priv->ring_data[i].ring); 3344 devm_kfree(priv->dev, 3345 priv->ring_data[i + h->kinfo.num_tqps].ring); 3346 } 3347 3348 devm_kfree(&pdev->dev, priv->ring_data); 3349 return ret; 3350 } 3351 3352 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3353 { 3354 struct hnae3_handle *h = priv->ae_handle; 3355 int i; 3356 3357 for (i = 0; i < h->kinfo.num_tqps; i++) { 3358 devm_kfree(priv->dev, priv->ring_data[i].ring); 3359 devm_kfree(priv->dev, 3360 priv->ring_data[i + h->kinfo.num_tqps].ring); 3361 } 3362 devm_kfree(priv->dev, priv->ring_data); 3363 } 3364 3365 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3366 { 3367 int ret; 3368 3369 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3370 return -EINVAL; 3371 3372 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3373 GFP_KERNEL); 3374 if (!ring->desc_cb) { 3375 ret = -ENOMEM; 3376 goto out; 3377 } 3378 3379 ret = hns3_alloc_desc(ring); 3380 if (ret) 3381 goto out_with_desc_cb; 3382 3383 if (!HNAE3_IS_TX_RING(ring)) { 3384 ret = hns3_alloc_ring_buffers(ring); 3385 if (ret) 3386 goto out_with_desc; 3387 } 3388 3389 return 0; 3390 3391 out_with_desc: 3392 hns3_free_desc(ring); 3393 out_with_desc_cb: 3394 kfree(ring->desc_cb); 3395 ring->desc_cb = NULL; 3396 out: 3397 return ret; 3398 } 3399 3400 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3401 { 3402 hns3_free_desc(ring); 3403 kfree(ring->desc_cb); 3404 ring->desc_cb = NULL; 3405 ring->next_to_clean = 0; 3406 ring->next_to_use = 0; 3407 ring->pending_buf = 0; 3408 if (ring->skb) { 3409 dev_kfree_skb_any(ring->skb); 3410 ring->skb = NULL; 3411 } 3412 } 3413 3414 static int hns3_buf_size2type(u32 buf_size) 3415 { 3416 int bd_size_type; 3417 3418 switch (buf_size) { 3419 case 512: 3420 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3421 break; 3422 case 1024: 3423 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3424 break; 3425 case 2048: 3426 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3427 break; 3428 case 4096: 3429 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3430 break; 3431 default: 3432 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3433 } 3434 3435 return bd_size_type; 3436 } 3437 3438 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3439 { 3440 dma_addr_t dma = ring->desc_dma_addr; 3441 struct hnae3_queue *q = ring->tqp; 3442 3443 if (!HNAE3_IS_TX_RING(ring)) { 3444 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3445 (u32)dma); 3446 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3447 (u32)((dma >> 31) >> 1)); 3448 3449 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3450 hns3_buf_size2type(ring->buf_size)); 3451 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3452 ring->desc_num / 8 - 1); 3453 3454 } else { 3455 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3456 (u32)dma); 3457 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3458 (u32)((dma >> 31) >> 1)); 3459 3460 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3461 ring->desc_num / 8 - 1); 3462 } 3463 } 3464 3465 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3466 { 3467 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3468 int i; 3469 3470 for (i = 0; i < HNAE3_MAX_TC; i++) { 3471 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3472 int j; 3473 3474 if (!tc_info->enable) 3475 continue; 3476 3477 for (j = 0; j < tc_info->tqp_count; j++) { 3478 struct hnae3_queue *q; 3479 3480 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3481 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3482 tc_info->tc); 3483 } 3484 } 3485 } 3486 3487 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3488 { 3489 struct hnae3_handle *h = priv->ae_handle; 3490 int ring_num = h->kinfo.num_tqps * 2; 3491 int i, j; 3492 int ret; 3493 3494 for (i = 0; i < ring_num; i++) { 3495 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3496 if (ret) { 3497 dev_err(priv->dev, 3498 "Alloc ring memory fail! ret=%d\n", ret); 3499 goto out_when_alloc_ring_memory; 3500 } 3501 3502 u64_stats_init(&priv->ring_data[i].ring->syncp); 3503 } 3504 3505 return 0; 3506 3507 out_when_alloc_ring_memory: 3508 for (j = i - 1; j >= 0; j--) 3509 hns3_fini_ring(priv->ring_data[j].ring); 3510 3511 return -ENOMEM; 3512 } 3513 3514 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3515 { 3516 struct hnae3_handle *h = priv->ae_handle; 3517 int i; 3518 3519 for (i = 0; i < h->kinfo.num_tqps; i++) { 3520 hns3_fini_ring(priv->ring_data[i].ring); 3521 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3522 } 3523 return 0; 3524 } 3525 3526 /* Set mac addr if it is configured. or leave it to the AE driver */ 3527 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3528 { 3529 struct hns3_nic_priv *priv = netdev_priv(netdev); 3530 struct hnae3_handle *h = priv->ae_handle; 3531 u8 mac_addr_temp[ETH_ALEN]; 3532 int ret = 0; 3533 3534 if (h->ae_algo->ops->get_mac_addr && init) { 3535 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3536 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3537 } 3538 3539 /* Check if the MAC address is valid, if not get a random one */ 3540 if (!is_valid_ether_addr(netdev->dev_addr)) { 3541 eth_hw_addr_random(netdev); 3542 dev_warn(priv->dev, "using random MAC address %pM\n", 3543 netdev->dev_addr); 3544 } 3545 3546 if (h->ae_algo->ops->set_mac_addr) 3547 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3548 3549 return ret; 3550 } 3551 3552 static int hns3_restore_fd_rules(struct net_device *netdev) 3553 { 3554 struct hnae3_handle *h = hns3_get_handle(netdev); 3555 int ret = 0; 3556 3557 if (h->ae_algo->ops->restore_fd_rules) 3558 ret = h->ae_algo->ops->restore_fd_rules(h); 3559 3560 return ret; 3561 } 3562 3563 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3564 { 3565 struct hnae3_handle *h = hns3_get_handle(netdev); 3566 3567 if (h->ae_algo->ops->del_all_fd_entries) 3568 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3569 } 3570 3571 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3572 { 3573 struct hns3_nic_priv *priv = netdev_priv(netdev); 3574 3575 priv->ops.fill_desc = hns3_fill_desc; 3576 if ((netdev->features & NETIF_F_TSO) || 3577 (netdev->features & NETIF_F_TSO6)) 3578 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3579 else 3580 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3581 } 3582 3583 static int hns3_client_start(struct hnae3_handle *handle) 3584 { 3585 if (!handle->ae_algo->ops->client_start) 3586 return 0; 3587 3588 return handle->ae_algo->ops->client_start(handle); 3589 } 3590 3591 static void hns3_client_stop(struct hnae3_handle *handle) 3592 { 3593 if (!handle->ae_algo->ops->client_stop) 3594 return; 3595 3596 handle->ae_algo->ops->client_stop(handle); 3597 } 3598 3599 static int hns3_client_init(struct hnae3_handle *handle) 3600 { 3601 struct pci_dev *pdev = handle->pdev; 3602 u16 alloc_tqps, max_rss_size; 3603 struct hns3_nic_priv *priv; 3604 struct net_device *netdev; 3605 int ret; 3606 3607 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3608 &max_rss_size); 3609 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3610 if (!netdev) 3611 return -ENOMEM; 3612 3613 priv = netdev_priv(netdev); 3614 priv->dev = &pdev->dev; 3615 priv->netdev = netdev; 3616 priv->ae_handle = handle; 3617 priv->tx_timeout_count = 0; 3618 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3619 3620 handle->kinfo.netdev = netdev; 3621 handle->priv = (void *)priv; 3622 3623 hns3_init_mac_addr(netdev, true); 3624 3625 hns3_set_default_feature(netdev); 3626 3627 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3628 netdev->priv_flags |= IFF_UNICAST_FLT; 3629 netdev->netdev_ops = &hns3_nic_netdev_ops; 3630 SET_NETDEV_DEV(netdev, &pdev->dev); 3631 hns3_ethtool_set_ops(netdev); 3632 hns3_nic_set_priv_ops(netdev); 3633 3634 /* Carrier off reporting is important to ethtool even BEFORE open */ 3635 netif_carrier_off(netdev); 3636 3637 ret = hns3_get_ring_config(priv); 3638 if (ret) { 3639 ret = -ENOMEM; 3640 goto out_get_ring_cfg; 3641 } 3642 3643 ret = hns3_nic_alloc_vector_data(priv); 3644 if (ret) { 3645 ret = -ENOMEM; 3646 goto out_alloc_vector_data; 3647 } 3648 3649 ret = hns3_nic_init_vector_data(priv); 3650 if (ret) { 3651 ret = -ENOMEM; 3652 goto out_init_vector_data; 3653 } 3654 3655 ret = hns3_init_all_ring(priv); 3656 if (ret) { 3657 ret = -ENOMEM; 3658 goto out_init_ring_data; 3659 } 3660 3661 ret = register_netdev(netdev); 3662 if (ret) { 3663 dev_err(priv->dev, "probe register netdev fail!\n"); 3664 goto out_reg_netdev_fail; 3665 } 3666 3667 ret = hns3_client_start(handle); 3668 if (ret) { 3669 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3670 goto out_reg_netdev_fail; 3671 } 3672 3673 hns3_dcbnl_setup(handle); 3674 3675 hns3_dbg_init(handle); 3676 3677 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3678 netdev->max_mtu = HNS3_MAX_MTU; 3679 3680 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3681 3682 return ret; 3683 3684 out_reg_netdev_fail: 3685 out_init_ring_data: 3686 (void)hns3_nic_uninit_vector_data(priv); 3687 out_init_vector_data: 3688 hns3_nic_dealloc_vector_data(priv); 3689 out_alloc_vector_data: 3690 priv->ring_data = NULL; 3691 out_get_ring_cfg: 3692 priv->ae_handle = NULL; 3693 free_netdev(netdev); 3694 return ret; 3695 } 3696 3697 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3698 { 3699 struct net_device *netdev = handle->kinfo.netdev; 3700 struct hns3_nic_priv *priv = netdev_priv(netdev); 3701 int ret; 3702 3703 hns3_client_stop(handle); 3704 3705 hns3_remove_hw_addr(netdev); 3706 3707 if (netdev->reg_state != NETREG_UNINITIALIZED) 3708 unregister_netdev(netdev); 3709 3710 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3711 netdev_warn(netdev, "already uninitialized\n"); 3712 goto out_netdev_free; 3713 } 3714 3715 hns3_del_all_fd_rules(netdev, true); 3716 3717 hns3_force_clear_all_rx_ring(handle); 3718 3719 ret = hns3_nic_uninit_vector_data(priv); 3720 if (ret) 3721 netdev_err(netdev, "uninit vector error\n"); 3722 3723 ret = hns3_nic_dealloc_vector_data(priv); 3724 if (ret) 3725 netdev_err(netdev, "dealloc vector error\n"); 3726 3727 ret = hns3_uninit_all_ring(priv); 3728 if (ret) 3729 netdev_err(netdev, "uninit ring error\n"); 3730 3731 hns3_put_ring_config(priv); 3732 3733 hns3_dbg_uninit(handle); 3734 3735 priv->ring_data = NULL; 3736 3737 out_netdev_free: 3738 free_netdev(netdev); 3739 } 3740 3741 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3742 { 3743 struct net_device *netdev = handle->kinfo.netdev; 3744 3745 if (!netdev) 3746 return; 3747 3748 if (linkup) { 3749 netif_carrier_on(netdev); 3750 netif_tx_wake_all_queues(netdev); 3751 netdev_info(netdev, "link up\n"); 3752 } else { 3753 netif_carrier_off(netdev); 3754 netif_tx_stop_all_queues(netdev); 3755 netdev_info(netdev, "link down\n"); 3756 } 3757 } 3758 3759 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3760 { 3761 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3762 struct net_device *ndev = kinfo->netdev; 3763 3764 if (tc > HNAE3_MAX_TC) 3765 return -EINVAL; 3766 3767 if (!ndev) 3768 return -ENODEV; 3769 3770 return hns3_nic_set_real_num_queue(ndev); 3771 } 3772 3773 static int hns3_recover_hw_addr(struct net_device *ndev) 3774 { 3775 struct netdev_hw_addr_list *list; 3776 struct netdev_hw_addr *ha, *tmp; 3777 int ret = 0; 3778 3779 /* go through and sync uc_addr entries to the device */ 3780 list = &ndev->uc; 3781 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3782 ret = hns3_nic_uc_sync(ndev, ha->addr); 3783 if (ret) 3784 return ret; 3785 } 3786 3787 /* go through and sync mc_addr entries to the device */ 3788 list = &ndev->mc; 3789 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3790 ret = hns3_nic_mc_sync(ndev, ha->addr); 3791 if (ret) 3792 return ret; 3793 } 3794 3795 return ret; 3796 } 3797 3798 static void hns3_remove_hw_addr(struct net_device *netdev) 3799 { 3800 struct netdev_hw_addr_list *list; 3801 struct netdev_hw_addr *ha, *tmp; 3802 3803 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3804 3805 /* go through and unsync uc_addr entries to the device */ 3806 list = &netdev->uc; 3807 list_for_each_entry_safe(ha, tmp, &list->list, list) 3808 hns3_nic_uc_unsync(netdev, ha->addr); 3809 3810 /* go through and unsync mc_addr entries to the device */ 3811 list = &netdev->mc; 3812 list_for_each_entry_safe(ha, tmp, &list->list, list) 3813 if (ha->refcount > 1) 3814 hns3_nic_mc_unsync(netdev, ha->addr); 3815 } 3816 3817 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3818 { 3819 while (ring->next_to_clean != ring->next_to_use) { 3820 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3821 hns3_free_buffer_detach(ring, ring->next_to_clean); 3822 ring_ptr_move_fw(ring, next_to_clean); 3823 } 3824 } 3825 3826 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3827 { 3828 struct hns3_desc_cb res_cbs; 3829 int ret; 3830 3831 while (ring->next_to_use != ring->next_to_clean) { 3832 /* When a buffer is not reused, it's memory has been 3833 * freed in hns3_handle_rx_bd or will be freed by 3834 * stack, so we need to replace the buffer here. 3835 */ 3836 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3837 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3838 if (ret) { 3839 u64_stats_update_begin(&ring->syncp); 3840 ring->stats.sw_err_cnt++; 3841 u64_stats_update_end(&ring->syncp); 3842 /* if alloc new buffer fail, exit directly 3843 * and reclear in up flow. 3844 */ 3845 netdev_warn(ring->tqp->handle->kinfo.netdev, 3846 "reserve buffer map failed, ret = %d\n", 3847 ret); 3848 return ret; 3849 } 3850 hns3_replace_buffer(ring, ring->next_to_use, 3851 &res_cbs); 3852 } 3853 ring_ptr_move_fw(ring, next_to_use); 3854 } 3855 3856 return 0; 3857 } 3858 3859 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3860 { 3861 while (ring->next_to_use != ring->next_to_clean) { 3862 /* When a buffer is not reused, it's memory has been 3863 * freed in hns3_handle_rx_bd or will be freed by 3864 * stack, so only need to unmap the buffer here. 3865 */ 3866 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3867 hns3_unmap_buffer(ring, 3868 &ring->desc_cb[ring->next_to_use]); 3869 ring->desc_cb[ring->next_to_use].dma = 0; 3870 } 3871 3872 ring_ptr_move_fw(ring, next_to_use); 3873 } 3874 } 3875 3876 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3877 { 3878 struct net_device *ndev = h->kinfo.netdev; 3879 struct hns3_nic_priv *priv = netdev_priv(ndev); 3880 struct hns3_enet_ring *ring; 3881 u32 i; 3882 3883 for (i = 0; i < h->kinfo.num_tqps; i++) { 3884 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3885 hns3_force_clear_rx_ring(ring); 3886 } 3887 } 3888 3889 static void hns3_clear_all_ring(struct hnae3_handle *h) 3890 { 3891 struct net_device *ndev = h->kinfo.netdev; 3892 struct hns3_nic_priv *priv = netdev_priv(ndev); 3893 u32 i; 3894 3895 for (i = 0; i < h->kinfo.num_tqps; i++) { 3896 struct netdev_queue *dev_queue; 3897 struct hns3_enet_ring *ring; 3898 3899 ring = priv->ring_data[i].ring; 3900 hns3_clear_tx_ring(ring); 3901 dev_queue = netdev_get_tx_queue(ndev, 3902 priv->ring_data[i].queue_index); 3903 netdev_tx_reset_queue(dev_queue); 3904 3905 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3906 /* Continue to clear other rings even if clearing some 3907 * rings failed. 3908 */ 3909 hns3_clear_rx_ring(ring); 3910 } 3911 } 3912 3913 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3914 { 3915 struct net_device *ndev = h->kinfo.netdev; 3916 struct hns3_nic_priv *priv = netdev_priv(ndev); 3917 struct hns3_enet_ring *rx_ring; 3918 int i, j; 3919 int ret; 3920 3921 for (i = 0; i < h->kinfo.num_tqps; i++) { 3922 ret = h->ae_algo->ops->reset_queue(h, i); 3923 if (ret) 3924 return ret; 3925 3926 hns3_init_ring_hw(priv->ring_data[i].ring); 3927 3928 /* We need to clear tx ring here because self test will 3929 * use the ring and will not run down before up 3930 */ 3931 hns3_clear_tx_ring(priv->ring_data[i].ring); 3932 priv->ring_data[i].ring->next_to_clean = 0; 3933 priv->ring_data[i].ring->next_to_use = 0; 3934 3935 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3936 hns3_init_ring_hw(rx_ring); 3937 ret = hns3_clear_rx_ring(rx_ring); 3938 if (ret) 3939 return ret; 3940 3941 /* We can not know the hardware head and tail when this 3942 * function is called in reset flow, so we reuse all desc. 3943 */ 3944 for (j = 0; j < rx_ring->desc_num; j++) 3945 hns3_reuse_buffer(rx_ring, j); 3946 3947 rx_ring->next_to_clean = 0; 3948 rx_ring->next_to_use = 0; 3949 } 3950 3951 hns3_init_tx_ring_tc(priv); 3952 3953 return 0; 3954 } 3955 3956 static void hns3_store_coal(struct hns3_nic_priv *priv) 3957 { 3958 /* ethtool only support setting and querying one coal 3959 * configuation for now, so save the vector 0' coal 3960 * configuation here in order to restore it. 3961 */ 3962 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 3963 sizeof(struct hns3_enet_coalesce)); 3964 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 3965 sizeof(struct hns3_enet_coalesce)); 3966 } 3967 3968 static void hns3_restore_coal(struct hns3_nic_priv *priv) 3969 { 3970 u16 vector_num = priv->vector_num; 3971 int i; 3972 3973 for (i = 0; i < vector_num; i++) { 3974 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 3975 sizeof(struct hns3_enet_coalesce)); 3976 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 3977 sizeof(struct hns3_enet_coalesce)); 3978 } 3979 } 3980 3981 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3982 { 3983 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 3984 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3985 struct net_device *ndev = kinfo->netdev; 3986 struct hns3_nic_priv *priv = netdev_priv(ndev); 3987 3988 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 3989 return 0; 3990 3991 /* it is cumbersome for hardware to pick-and-choose entries for deletion 3992 * from table space. Hence, for function reset software intervention is 3993 * required to delete the entries 3994 */ 3995 if (hns3_dev_ongoing_func_reset(ae_dev)) { 3996 hns3_remove_hw_addr(ndev); 3997 hns3_del_all_fd_rules(ndev, false); 3998 } 3999 4000 if (!netif_running(ndev)) 4001 return 0; 4002 4003 return hns3_nic_net_stop(ndev); 4004 } 4005 4006 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4007 { 4008 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4009 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4010 int ret = 0; 4011 4012 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4013 4014 if (netif_running(kinfo->netdev)) { 4015 ret = hns3_nic_net_open(kinfo->netdev); 4016 if (ret) { 4017 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4018 netdev_err(kinfo->netdev, 4019 "hns net up fail, ret=%d!\n", ret); 4020 return ret; 4021 } 4022 } 4023 4024 return ret; 4025 } 4026 4027 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4028 { 4029 struct net_device *netdev = handle->kinfo.netdev; 4030 struct hns3_nic_priv *priv = netdev_priv(netdev); 4031 int ret; 4032 4033 /* Carrier off reporting is important to ethtool even BEFORE open */ 4034 netif_carrier_off(netdev); 4035 4036 ret = hns3_get_ring_config(priv); 4037 if (ret) 4038 return ret; 4039 4040 ret = hns3_nic_alloc_vector_data(priv); 4041 if (ret) 4042 goto err_put_ring; 4043 4044 hns3_restore_coal(priv); 4045 4046 ret = hns3_nic_init_vector_data(priv); 4047 if (ret) 4048 goto err_dealloc_vector; 4049 4050 ret = hns3_init_all_ring(priv); 4051 if (ret) 4052 goto err_uninit_vector; 4053 4054 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4055 4056 return ret; 4057 4058 err_uninit_vector: 4059 hns3_nic_uninit_vector_data(priv); 4060 priv->ring_data = NULL; 4061 err_dealloc_vector: 4062 hns3_nic_dealloc_vector_data(priv); 4063 err_put_ring: 4064 hns3_put_ring_config(priv); 4065 priv->ring_data = NULL; 4066 4067 return ret; 4068 } 4069 4070 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4071 { 4072 struct net_device *netdev = handle->kinfo.netdev; 4073 bool vlan_filter_enable; 4074 int ret; 4075 4076 ret = hns3_init_mac_addr(netdev, false); 4077 if (ret) 4078 return ret; 4079 4080 ret = hns3_recover_hw_addr(netdev); 4081 if (ret) 4082 return ret; 4083 4084 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4085 if (ret) 4086 return ret; 4087 4088 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4089 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4090 4091 /* Hardware table is only clear when pf resets */ 4092 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4093 ret = hns3_restore_vlan(netdev); 4094 if (ret) 4095 return ret; 4096 } 4097 4098 return hns3_restore_fd_rules(netdev); 4099 } 4100 4101 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4102 { 4103 struct net_device *netdev = handle->kinfo.netdev; 4104 struct hns3_nic_priv *priv = netdev_priv(netdev); 4105 int ret; 4106 4107 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4108 netdev_warn(netdev, "already uninitialized\n"); 4109 return 0; 4110 } 4111 4112 hns3_force_clear_all_rx_ring(handle); 4113 4114 ret = hns3_nic_uninit_vector_data(priv); 4115 if (ret) { 4116 netdev_err(netdev, "uninit vector error\n"); 4117 return ret; 4118 } 4119 4120 hns3_store_coal(priv); 4121 4122 ret = hns3_nic_dealloc_vector_data(priv); 4123 if (ret) 4124 netdev_err(netdev, "dealloc vector error\n"); 4125 4126 ret = hns3_uninit_all_ring(priv); 4127 if (ret) 4128 netdev_err(netdev, "uninit ring error\n"); 4129 4130 hns3_put_ring_config(priv); 4131 priv->ring_data = NULL; 4132 4133 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 4134 4135 return ret; 4136 } 4137 4138 static int hns3_reset_notify(struct hnae3_handle *handle, 4139 enum hnae3_reset_notify_type type) 4140 { 4141 int ret = 0; 4142 4143 switch (type) { 4144 case HNAE3_UP_CLIENT: 4145 ret = hns3_reset_notify_up_enet(handle); 4146 break; 4147 case HNAE3_DOWN_CLIENT: 4148 ret = hns3_reset_notify_down_enet(handle); 4149 break; 4150 case HNAE3_INIT_CLIENT: 4151 ret = hns3_reset_notify_init_enet(handle); 4152 break; 4153 case HNAE3_UNINIT_CLIENT: 4154 ret = hns3_reset_notify_uninit_enet(handle); 4155 break; 4156 case HNAE3_RESTORE_CLIENT: 4157 ret = hns3_reset_notify_restore_enet(handle); 4158 break; 4159 default: 4160 break; 4161 } 4162 4163 return ret; 4164 } 4165 4166 int hns3_set_channels(struct net_device *netdev, 4167 struct ethtool_channels *ch) 4168 { 4169 struct hnae3_handle *h = hns3_get_handle(netdev); 4170 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4171 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4172 u32 new_tqp_num = ch->combined_count; 4173 u16 org_tqp_num; 4174 int ret; 4175 4176 if (ch->rx_count || ch->tx_count) 4177 return -EINVAL; 4178 4179 if (new_tqp_num > hns3_get_max_available_channels(h) || 4180 new_tqp_num < 1) { 4181 dev_err(&netdev->dev, 4182 "Change tqps fail, the tqp range is from 1 to %d", 4183 hns3_get_max_available_channels(h)); 4184 return -EINVAL; 4185 } 4186 4187 if (kinfo->rss_size == new_tqp_num) 4188 return 0; 4189 4190 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4191 if (ret) 4192 return ret; 4193 4194 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4195 if (ret) 4196 return ret; 4197 4198 org_tqp_num = h->kinfo.num_tqps; 4199 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4200 if (ret) { 4201 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4202 rxfh_configured); 4203 if (ret) { 4204 /* If revert to old tqp failed, fatal error occurred */ 4205 dev_err(&netdev->dev, 4206 "Revert to old tqp num fail, ret=%d", ret); 4207 return ret; 4208 } 4209 dev_info(&netdev->dev, 4210 "Change tqp num fail, Revert to old tqp num"); 4211 } 4212 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4213 if (ret) 4214 return ret; 4215 4216 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4217 } 4218 4219 static const struct hnae3_client_ops client_ops = { 4220 .init_instance = hns3_client_init, 4221 .uninit_instance = hns3_client_uninit, 4222 .link_status_change = hns3_link_status_change, 4223 .setup_tc = hns3_client_setup_tc, 4224 .reset_notify = hns3_reset_notify, 4225 }; 4226 4227 /* hns3_init_module - Driver registration routine 4228 * hns3_init_module is the first routine called when the driver is 4229 * loaded. All it does is register with the PCI subsystem. 4230 */ 4231 static int __init hns3_init_module(void) 4232 { 4233 int ret; 4234 4235 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4236 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4237 4238 client.type = HNAE3_CLIENT_KNIC; 4239 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4240 hns3_driver_name); 4241 4242 client.ops = &client_ops; 4243 4244 INIT_LIST_HEAD(&client.node); 4245 4246 hns3_dbg_register_debugfs(hns3_driver_name); 4247 4248 ret = hnae3_register_client(&client); 4249 if (ret) 4250 goto err_reg_client; 4251 4252 ret = pci_register_driver(&hns3_driver); 4253 if (ret) 4254 goto err_reg_driver; 4255 4256 return ret; 4257 4258 err_reg_driver: 4259 hnae3_unregister_client(&client); 4260 err_reg_client: 4261 hns3_dbg_unregister_debugfs(); 4262 return ret; 4263 } 4264 module_init(hns3_init_module); 4265 4266 /* hns3_exit_module - Driver exit cleanup routine 4267 * hns3_exit_module is called just before the driver is removed 4268 * from memory. 4269 */ 4270 static void __exit hns3_exit_module(void) 4271 { 4272 pci_unregister_driver(&hns3_driver); 4273 hnae3_unregister_client(&client); 4274 hns3_dbg_unregister_debugfs(); 4275 } 4276 module_exit(hns3_exit_module); 4277 4278 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4279 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4280 MODULE_LICENSE("GPL"); 4281 MODULE_ALIAS("pci:hns-nic"); 4282 MODULE_VERSION(HNS3_MOD_VERSION); 4283