1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <linux/vermagic.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 30 31 #define hns3_rl_err(fmt, ...) \ 32 do { \ 33 if (net_ratelimit()) \ 34 netdev_err(fmt, ##__VA_ARGS__); \ 35 } while (0) 36 37 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 38 static void hns3_remove_hw_addr(struct net_device *netdev); 39 40 static const char hns3_driver_name[] = "hns3"; 41 const char hns3_driver_version[] = VERMAGIC_STRING; 42 static const char hns3_driver_string[] = 43 "Hisilicon Ethernet Network Driver for Hip08 Family"; 44 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 45 static struct hnae3_client client; 46 47 static int debug = -1; 48 module_param(debug, int, 0); 49 MODULE_PARM_DESC(debug, " Network interface message level setting"); 50 51 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 53 54 #define HNS3_INNER_VLAN_TAG 1 55 #define HNS3_OUTER_VLAN_TAG 2 56 57 /* hns3_pci_tbl - PCI Device ID Table 58 * 59 * Last entry must be all 0s 60 * 61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 62 * Class, Class Mask, private data (not used) } 63 */ 64 static const struct pci_device_id hns3_pci_tbl[] = { 65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 /* required last entry */ 81 {0, } 82 }; 83 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 84 85 static irqreturn_t hns3_irq_handle(int irq, void *vector) 86 { 87 struct hns3_enet_tqp_vector *tqp_vector = vector; 88 89 napi_schedule_irqoff(&tqp_vector->napi); 90 91 return IRQ_HANDLED; 92 } 93 94 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 95 { 96 struct hns3_enet_tqp_vector *tqp_vectors; 97 unsigned int i; 98 99 for (i = 0; i < priv->vector_num; i++) { 100 tqp_vectors = &priv->tqp_vector[i]; 101 102 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 103 continue; 104 105 /* clear the affinity mask */ 106 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 107 108 /* release the irq resource */ 109 free_irq(tqp_vectors->vector_irq, tqp_vectors); 110 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 111 } 112 } 113 114 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 115 { 116 struct hns3_enet_tqp_vector *tqp_vectors; 117 int txrx_int_idx = 0; 118 int rx_int_idx = 0; 119 int tx_int_idx = 0; 120 unsigned int i; 121 int ret; 122 123 for (i = 0; i < priv->vector_num; i++) { 124 tqp_vectors = &priv->tqp_vector[i]; 125 126 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 127 continue; 128 129 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 131 "%s-%s-%d", priv->netdev->name, "TxRx", 132 txrx_int_idx++); 133 txrx_int_idx++; 134 } else if (tqp_vectors->rx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Rx", 137 rx_int_idx++); 138 } else if (tqp_vectors->tx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 140 "%s-%s-%d", priv->netdev->name, "Tx", 141 tx_int_idx++); 142 } else { 143 /* Skip this unused q_vector */ 144 continue; 145 } 146 147 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 148 149 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 150 tqp_vectors->name, tqp_vectors); 151 if (ret) { 152 netdev_err(priv->netdev, "request irq(%d) fail\n", 153 tqp_vectors->vector_irq); 154 hns3_nic_uninit_irq(priv); 155 return ret; 156 } 157 158 irq_set_affinity_hint(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_mask); 160 161 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 162 } 163 164 return 0; 165 } 166 167 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 168 u32 mask_en) 169 { 170 writel(mask_en, tqp_vector->mask_addr); 171 } 172 173 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 174 { 175 napi_enable(&tqp_vector->napi); 176 177 /* enable vector */ 178 hns3_mask_vector_irq(tqp_vector, 1); 179 } 180 181 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 182 { 183 /* disable vector */ 184 hns3_mask_vector_irq(tqp_vector, 0); 185 186 disable_irq(tqp_vector->vector_irq); 187 napi_disable(&tqp_vector->napi); 188 } 189 190 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 191 u32 rl_value) 192 { 193 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 194 195 /* this defines the configuration for RL (Interrupt Rate Limiter). 196 * Rl defines rate of interrupts i.e. number of interrupts-per-second 197 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 198 */ 199 200 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 201 !tqp_vector->rx_group.coal.gl_adapt_enable) 202 /* According to the hardware, the range of rl_reg is 203 * 0-59 and the unit is 4. 204 */ 205 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 206 207 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 208 } 209 210 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 211 u32 gl_value) 212 { 213 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 214 215 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 216 } 217 218 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 219 u32 gl_value) 220 { 221 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 222 223 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 224 } 225 226 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 227 struct hns3_nic_priv *priv) 228 { 229 /* initialize the configuration for interrupt coalescing. 230 * 1. GL (Interrupt Gap Limiter) 231 * 2. RL (Interrupt Rate Limiter) 232 * 233 * Default: enable interrupt coalescing self-adaptive and GL 234 */ 235 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 236 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 237 238 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 239 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 240 241 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 242 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 243 } 244 245 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 246 struct hns3_nic_priv *priv) 247 { 248 struct hnae3_handle *h = priv->ae_handle; 249 250 hns3_set_vector_coalesce_tx_gl(tqp_vector, 251 tqp_vector->tx_group.coal.int_gl); 252 hns3_set_vector_coalesce_rx_gl(tqp_vector, 253 tqp_vector->rx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 255 } 256 257 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 258 { 259 struct hnae3_handle *h = hns3_get_handle(netdev); 260 struct hnae3_knic_private_info *kinfo = &h->kinfo; 261 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 262 int i, ret; 263 264 if (kinfo->num_tc <= 1) { 265 netdev_reset_tc(netdev); 266 } else { 267 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 268 if (ret) { 269 netdev_err(netdev, 270 "netdev_set_num_tc fail, ret=%d!\n", ret); 271 return ret; 272 } 273 274 for (i = 0; i < HNAE3_MAX_TC; i++) { 275 if (!kinfo->tc_info[i].enable) 276 continue; 277 278 netdev_set_tc_queue(netdev, 279 kinfo->tc_info[i].tc, 280 kinfo->tc_info[i].tqp_count, 281 kinfo->tc_info[i].tqp_offset); 282 } 283 } 284 285 ret = netif_set_real_num_tx_queues(netdev, queue_size); 286 if (ret) { 287 netdev_err(netdev, 288 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 289 return ret; 290 } 291 292 ret = netif_set_real_num_rx_queues(netdev, queue_size); 293 if (ret) { 294 netdev_err(netdev, 295 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 296 return ret; 297 } 298 299 return 0; 300 } 301 302 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 303 { 304 u16 alloc_tqps, max_rss_size, rss_size; 305 306 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 307 rss_size = alloc_tqps / h->kinfo.num_tc; 308 309 return min_t(u16, rss_size, max_rss_size); 310 } 311 312 static void hns3_tqp_enable(struct hnae3_queue *tqp) 313 { 314 u32 rcb_reg; 315 316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 317 rcb_reg |= BIT(HNS3_RING_EN_B); 318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 319 } 320 321 static void hns3_tqp_disable(struct hnae3_queue *tqp) 322 { 323 u32 rcb_reg; 324 325 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 326 rcb_reg &= ~BIT(HNS3_RING_EN_B); 327 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 328 } 329 330 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 331 { 332 #ifdef CONFIG_RFS_ACCEL 333 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 334 netdev->rx_cpu_rmap = NULL; 335 #endif 336 } 337 338 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 339 { 340 #ifdef CONFIG_RFS_ACCEL 341 struct hns3_nic_priv *priv = netdev_priv(netdev); 342 struct hns3_enet_tqp_vector *tqp_vector; 343 int i, ret; 344 345 if (!netdev->rx_cpu_rmap) { 346 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 347 if (!netdev->rx_cpu_rmap) 348 return -ENOMEM; 349 } 350 351 for (i = 0; i < priv->vector_num; i++) { 352 tqp_vector = &priv->tqp_vector[i]; 353 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 354 tqp_vector->vector_irq); 355 if (ret) { 356 hns3_free_rx_cpu_rmap(netdev); 357 return ret; 358 } 359 } 360 #endif 361 return 0; 362 } 363 364 static int hns3_nic_net_up(struct net_device *netdev) 365 { 366 struct hns3_nic_priv *priv = netdev_priv(netdev); 367 struct hnae3_handle *h = priv->ae_handle; 368 int i, j; 369 int ret; 370 371 ret = hns3_nic_reset_all_ring(h); 372 if (ret) 373 return ret; 374 375 /* the device can work without cpu rmap, only aRFS needs it */ 376 ret = hns3_set_rx_cpu_rmap(netdev); 377 if (ret) 378 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret); 379 380 /* get irq resource for all vectors */ 381 ret = hns3_nic_init_irq(priv); 382 if (ret) { 383 netdev_err(netdev, "init irq failed! ret=%d\n", ret); 384 goto free_rmap; 385 } 386 387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 388 389 /* enable the vectors */ 390 for (i = 0; i < priv->vector_num; i++) 391 hns3_vector_enable(&priv->tqp_vector[i]); 392 393 /* enable rcb */ 394 for (j = 0; j < h->kinfo.num_tqps; j++) 395 hns3_tqp_enable(h->kinfo.tqp[j]); 396 397 /* start the ae_dev */ 398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 399 if (ret) 400 goto out_start_err; 401 402 return 0; 403 404 out_start_err: 405 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 406 while (j--) 407 hns3_tqp_disable(h->kinfo.tqp[j]); 408 409 for (j = i - 1; j >= 0; j--) 410 hns3_vector_disable(&priv->tqp_vector[j]); 411 412 hns3_nic_uninit_irq(priv); 413 free_rmap: 414 hns3_free_rx_cpu_rmap(netdev); 415 return ret; 416 } 417 418 static void hns3_config_xps(struct hns3_nic_priv *priv) 419 { 420 int i; 421 422 for (i = 0; i < priv->vector_num; i++) { 423 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 424 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 425 426 while (ring) { 427 int ret; 428 429 ret = netif_set_xps_queue(priv->netdev, 430 &tqp_vector->affinity_mask, 431 ring->tqp->tqp_index); 432 if (ret) 433 netdev_warn(priv->netdev, 434 "set xps queue failed: %d", ret); 435 436 ring = ring->next; 437 } 438 } 439 } 440 441 static int hns3_nic_net_open(struct net_device *netdev) 442 { 443 struct hns3_nic_priv *priv = netdev_priv(netdev); 444 struct hnae3_handle *h = hns3_get_handle(netdev); 445 struct hnae3_knic_private_info *kinfo; 446 int i, ret; 447 448 if (hns3_nic_resetting(netdev)) 449 return -EBUSY; 450 451 netif_carrier_off(netdev); 452 453 ret = hns3_nic_set_real_num_queue(netdev); 454 if (ret) 455 return ret; 456 457 ret = hns3_nic_net_up(netdev); 458 if (ret) { 459 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 460 return ret; 461 } 462 463 kinfo = &h->kinfo; 464 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 465 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 466 467 if (h->ae_algo->ops->set_timer_task) 468 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 469 470 hns3_config_xps(priv); 471 472 netif_dbg(h, drv, netdev, "net open\n"); 473 474 return 0; 475 } 476 477 static void hns3_reset_tx_queue(struct hnae3_handle *h) 478 { 479 struct net_device *ndev = h->kinfo.netdev; 480 struct hns3_nic_priv *priv = netdev_priv(ndev); 481 struct netdev_queue *dev_queue; 482 u32 i; 483 484 for (i = 0; i < h->kinfo.num_tqps; i++) { 485 dev_queue = netdev_get_tx_queue(ndev, 486 priv->ring_data[i].queue_index); 487 netdev_tx_reset_queue(dev_queue); 488 } 489 } 490 491 static void hns3_nic_net_down(struct net_device *netdev) 492 { 493 struct hns3_nic_priv *priv = netdev_priv(netdev); 494 struct hnae3_handle *h = hns3_get_handle(netdev); 495 const struct hnae3_ae_ops *ops; 496 int i; 497 498 /* disable vectors */ 499 for (i = 0; i < priv->vector_num; i++) 500 hns3_vector_disable(&priv->tqp_vector[i]); 501 502 /* disable rcb */ 503 for (i = 0; i < h->kinfo.num_tqps; i++) 504 hns3_tqp_disable(h->kinfo.tqp[i]); 505 506 /* stop ae_dev */ 507 ops = priv->ae_handle->ae_algo->ops; 508 if (ops->stop) 509 ops->stop(priv->ae_handle); 510 511 hns3_free_rx_cpu_rmap(netdev); 512 513 /* free irq resources */ 514 hns3_nic_uninit_irq(priv); 515 516 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 517 * during reset process, because driver may not be able 518 * to disable the ring through firmware when downing the netdev. 519 */ 520 if (!hns3_nic_resetting(netdev)) 521 hns3_clear_all_ring(priv->ae_handle, false); 522 523 hns3_reset_tx_queue(priv->ae_handle); 524 } 525 526 static int hns3_nic_net_stop(struct net_device *netdev) 527 { 528 struct hns3_nic_priv *priv = netdev_priv(netdev); 529 struct hnae3_handle *h = hns3_get_handle(netdev); 530 531 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 532 return 0; 533 534 netif_dbg(h, drv, netdev, "net stop\n"); 535 536 if (h->ae_algo->ops->set_timer_task) 537 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 538 539 netif_tx_stop_all_queues(netdev); 540 netif_carrier_off(netdev); 541 542 hns3_nic_net_down(netdev); 543 544 return 0; 545 } 546 547 static int hns3_nic_uc_sync(struct net_device *netdev, 548 const unsigned char *addr) 549 { 550 struct hnae3_handle *h = hns3_get_handle(netdev); 551 552 if (h->ae_algo->ops->add_uc_addr) 553 return h->ae_algo->ops->add_uc_addr(h, addr); 554 555 return 0; 556 } 557 558 static int hns3_nic_uc_unsync(struct net_device *netdev, 559 const unsigned char *addr) 560 { 561 struct hnae3_handle *h = hns3_get_handle(netdev); 562 563 if (h->ae_algo->ops->rm_uc_addr) 564 return h->ae_algo->ops->rm_uc_addr(h, addr); 565 566 return 0; 567 } 568 569 static int hns3_nic_mc_sync(struct net_device *netdev, 570 const unsigned char *addr) 571 { 572 struct hnae3_handle *h = hns3_get_handle(netdev); 573 574 if (h->ae_algo->ops->add_mc_addr) 575 return h->ae_algo->ops->add_mc_addr(h, addr); 576 577 return 0; 578 } 579 580 static int hns3_nic_mc_unsync(struct net_device *netdev, 581 const unsigned char *addr) 582 { 583 struct hnae3_handle *h = hns3_get_handle(netdev); 584 585 if (h->ae_algo->ops->rm_mc_addr) 586 return h->ae_algo->ops->rm_mc_addr(h, addr); 587 588 return 0; 589 } 590 591 static u8 hns3_get_netdev_flags(struct net_device *netdev) 592 { 593 u8 flags = 0; 594 595 if (netdev->flags & IFF_PROMISC) { 596 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 597 } else { 598 flags |= HNAE3_VLAN_FLTR; 599 if (netdev->flags & IFF_ALLMULTI) 600 flags |= HNAE3_USER_MPE; 601 } 602 603 return flags; 604 } 605 606 static void hns3_nic_set_rx_mode(struct net_device *netdev) 607 { 608 struct hnae3_handle *h = hns3_get_handle(netdev); 609 u8 new_flags; 610 int ret; 611 612 new_flags = hns3_get_netdev_flags(netdev); 613 614 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 615 if (ret) { 616 netdev_err(netdev, "sync uc address fail\n"); 617 if (ret == -ENOSPC) 618 new_flags |= HNAE3_OVERFLOW_UPE; 619 } 620 621 if (netdev->flags & IFF_MULTICAST) { 622 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 623 hns3_nic_mc_unsync); 624 if (ret) { 625 netdev_err(netdev, "sync mc address fail\n"); 626 if (ret == -ENOSPC) 627 new_flags |= HNAE3_OVERFLOW_MPE; 628 } 629 } 630 631 /* User mode Promisc mode enable and vlan filtering is disabled to 632 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 633 * vlan fitering is enabled 634 */ 635 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 636 h->netdev_flags = new_flags; 637 hns3_update_promisc_mode(netdev, new_flags); 638 } 639 640 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 641 { 642 struct hns3_nic_priv *priv = netdev_priv(netdev); 643 struct hnae3_handle *h = priv->ae_handle; 644 645 if (h->ae_algo->ops->set_promisc_mode) { 646 return h->ae_algo->ops->set_promisc_mode(h, 647 promisc_flags & HNAE3_UPE, 648 promisc_flags & HNAE3_MPE); 649 } 650 651 return 0; 652 } 653 654 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 655 { 656 struct hns3_nic_priv *priv = netdev_priv(netdev); 657 struct hnae3_handle *h = priv->ae_handle; 658 bool last_state; 659 660 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 661 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 662 if (enable != last_state) { 663 netdev_info(netdev, 664 "%s vlan filter\n", 665 enable ? "enable" : "disable"); 666 h->ae_algo->ops->enable_vlan_filter(h, enable); 667 } 668 } 669 } 670 671 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 672 u16 *mss, u32 *type_cs_vlan_tso) 673 { 674 u32 l4_offset, hdr_len; 675 union l3_hdr_info l3; 676 union l4_hdr_info l4; 677 u32 l4_paylen; 678 int ret; 679 680 if (!skb_is_gso(skb)) 681 return 0; 682 683 ret = skb_cow_head(skb, 0); 684 if (unlikely(ret)) 685 return ret; 686 687 l3.hdr = skb_network_header(skb); 688 l4.hdr = skb_transport_header(skb); 689 690 /* Software should clear the IPv4's checksum field when tso is 691 * needed. 692 */ 693 if (l3.v4->version == 4) 694 l3.v4->check = 0; 695 696 /* tunnel packet */ 697 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 698 SKB_GSO_GRE_CSUM | 699 SKB_GSO_UDP_TUNNEL | 700 SKB_GSO_UDP_TUNNEL_CSUM)) { 701 if ((!(skb_shinfo(skb)->gso_type & 702 SKB_GSO_PARTIAL)) && 703 (skb_shinfo(skb)->gso_type & 704 SKB_GSO_UDP_TUNNEL_CSUM)) { 705 /* Software should clear the udp's checksum 706 * field when tso is needed. 707 */ 708 l4.udp->check = 0; 709 } 710 /* reset l3&l4 pointers from outer to inner headers */ 711 l3.hdr = skb_inner_network_header(skb); 712 l4.hdr = skb_inner_transport_header(skb); 713 714 /* Software should clear the IPv4's checksum field when 715 * tso is needed. 716 */ 717 if (l3.v4->version == 4) 718 l3.v4->check = 0; 719 } 720 721 /* normal or tunnel packet */ 722 l4_offset = l4.hdr - skb->data; 723 hdr_len = (l4.tcp->doff << 2) + l4_offset; 724 725 /* remove payload length from inner pseudo checksum when tso */ 726 l4_paylen = skb->len - l4_offset; 727 csum_replace_by_diff(&l4.tcp->check, 728 (__force __wsum)htonl(l4_paylen)); 729 730 /* find the txbd field values */ 731 *paylen = skb->len - hdr_len; 732 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 733 734 /* get MSS for TSO */ 735 *mss = skb_shinfo(skb)->gso_size; 736 737 return 0; 738 } 739 740 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 741 u8 *il4_proto) 742 { 743 union l3_hdr_info l3; 744 unsigned char *l4_hdr; 745 unsigned char *exthdr; 746 u8 l4_proto_tmp; 747 __be16 frag_off; 748 749 /* find outer header point */ 750 l3.hdr = skb_network_header(skb); 751 l4_hdr = skb_transport_header(skb); 752 753 if (skb->protocol == htons(ETH_P_IPV6)) { 754 exthdr = l3.hdr + sizeof(*l3.v6); 755 l4_proto_tmp = l3.v6->nexthdr; 756 if (l4_hdr != exthdr) 757 ipv6_skip_exthdr(skb, exthdr - skb->data, 758 &l4_proto_tmp, &frag_off); 759 } else if (skb->protocol == htons(ETH_P_IP)) { 760 l4_proto_tmp = l3.v4->protocol; 761 } else { 762 return -EINVAL; 763 } 764 765 *ol4_proto = l4_proto_tmp; 766 767 /* tunnel packet */ 768 if (!skb->encapsulation) { 769 *il4_proto = 0; 770 return 0; 771 } 772 773 /* find inner header point */ 774 l3.hdr = skb_inner_network_header(skb); 775 l4_hdr = skb_inner_transport_header(skb); 776 777 if (l3.v6->version == 6) { 778 exthdr = l3.hdr + sizeof(*l3.v6); 779 l4_proto_tmp = l3.v6->nexthdr; 780 if (l4_hdr != exthdr) 781 ipv6_skip_exthdr(skb, exthdr - skb->data, 782 &l4_proto_tmp, &frag_off); 783 } else if (l3.v4->version == 4) { 784 l4_proto_tmp = l3.v4->protocol; 785 } 786 787 *il4_proto = l4_proto_tmp; 788 789 return 0; 790 } 791 792 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 793 * and it is udp packet, which has a dest port as the IANA assigned. 794 * the hardware is expected to do the checksum offload, but the 795 * hardware will not do the checksum offload when udp dest port is 796 * 4789. 797 */ 798 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 799 { 800 union l4_hdr_info l4; 801 802 l4.hdr = skb_transport_header(skb); 803 804 if (!(!skb->encapsulation && 805 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 806 return false; 807 808 skb_checksum_help(skb); 809 810 return true; 811 } 812 813 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 814 u32 *ol_type_vlan_len_msec) 815 { 816 u32 l2_len, l3_len, l4_len; 817 unsigned char *il2_hdr; 818 union l3_hdr_info l3; 819 union l4_hdr_info l4; 820 821 l3.hdr = skb_network_header(skb); 822 l4.hdr = skb_transport_header(skb); 823 824 /* compute OL2 header size, defined in 2 Bytes */ 825 l2_len = l3.hdr - skb->data; 826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 827 828 /* compute OL3 header size, defined in 4 Bytes */ 829 l3_len = l4.hdr - l3.hdr; 830 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 831 832 il2_hdr = skb_inner_mac_header(skb); 833 /* compute OL4 header size, defined in 4 Bytes */ 834 l4_len = il2_hdr - l4.hdr; 835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 836 837 /* define outer network header type */ 838 if (skb->protocol == htons(ETH_P_IP)) { 839 if (skb_is_gso(skb)) 840 hns3_set_field(*ol_type_vlan_len_msec, 841 HNS3_TXD_OL3T_S, 842 HNS3_OL3T_IPV4_CSUM); 843 else 844 hns3_set_field(*ol_type_vlan_len_msec, 845 HNS3_TXD_OL3T_S, 846 HNS3_OL3T_IPV4_NO_CSUM); 847 848 } else if (skb->protocol == htons(ETH_P_IPV6)) { 849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 850 HNS3_OL3T_IPV6); 851 } 852 853 if (ol4_proto == IPPROTO_UDP) 854 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 855 HNS3_TUN_MAC_IN_UDP); 856 else if (ol4_proto == IPPROTO_GRE) 857 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 858 HNS3_TUN_NVGRE); 859 } 860 861 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 862 u8 il4_proto, u32 *type_cs_vlan_tso, 863 u32 *ol_type_vlan_len_msec) 864 { 865 unsigned char *l2_hdr = skb->data; 866 u32 l4_proto = ol4_proto; 867 union l4_hdr_info l4; 868 union l3_hdr_info l3; 869 u32 l2_len, l3_len; 870 871 l4.hdr = skb_transport_header(skb); 872 l3.hdr = skb_network_header(skb); 873 874 /* handle encapsulation skb */ 875 if (skb->encapsulation) { 876 /* If this is a not UDP/GRE encapsulation skb */ 877 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 878 /* drop the skb tunnel packet if hardware don't support, 879 * because hardware can't calculate csum when TSO. 880 */ 881 if (skb_is_gso(skb)) 882 return -EDOM; 883 884 /* the stack computes the IP header already, 885 * driver calculate l4 checksum when not TSO. 886 */ 887 skb_checksum_help(skb); 888 return 0; 889 } 890 891 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 892 893 /* switch to inner header */ 894 l2_hdr = skb_inner_mac_header(skb); 895 l3.hdr = skb_inner_network_header(skb); 896 l4.hdr = skb_inner_transport_header(skb); 897 l4_proto = il4_proto; 898 } 899 900 if (l3.v4->version == 4) { 901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 902 HNS3_L3T_IPV4); 903 904 /* the stack computes the IP header already, the only time we 905 * need the hardware to recompute it is in the case of TSO. 906 */ 907 if (skb_is_gso(skb)) 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 909 } else if (l3.v6->version == 6) { 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 911 HNS3_L3T_IPV6); 912 } 913 914 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 915 l2_len = l3.hdr - l2_hdr; 916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 917 918 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 919 l3_len = l4.hdr - l3.hdr; 920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 921 922 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 923 switch (l4_proto) { 924 case IPPROTO_TCP: 925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 927 HNS3_L4T_TCP); 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 929 l4.tcp->doff); 930 break; 931 case IPPROTO_UDP: 932 if (hns3_tunnel_csum_bug(skb)) 933 break; 934 935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 937 HNS3_L4T_UDP); 938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 939 (sizeof(struct udphdr) >> 2)); 940 break; 941 case IPPROTO_SCTP: 942 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 943 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 944 HNS3_L4T_SCTP); 945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 946 (sizeof(struct sctphdr) >> 2)); 947 break; 948 default: 949 /* drop the skb tunnel packet if hardware don't support, 950 * because hardware can't calculate csum when TSO. 951 */ 952 if (skb_is_gso(skb)) 953 return -EDOM; 954 955 /* the stack computes the IP header already, 956 * driver calculate l4 checksum when not TSO. 957 */ 958 skb_checksum_help(skb); 959 return 0; 960 } 961 962 return 0; 963 } 964 965 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 966 { 967 /* Config bd buffer end */ 968 if (!!frag_end) 969 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, 1U); 970 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1U); 971 } 972 973 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 974 struct sk_buff *skb) 975 { 976 struct hnae3_handle *handle = tx_ring->tqp->handle; 977 struct vlan_ethhdr *vhdr; 978 int rc; 979 980 if (!(skb->protocol == htons(ETH_P_8021Q) || 981 skb_vlan_tag_present(skb))) 982 return 0; 983 984 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 985 * header is allowed in skb, otherwise it will cause RAS error. 986 */ 987 if (unlikely(skb_vlan_tagged_multi(skb) && 988 handle->port_base_vlan_state == 989 HNAE3_PORT_BASE_VLAN_ENABLE)) 990 return -EINVAL; 991 992 if (skb->protocol == htons(ETH_P_8021Q) && 993 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 994 /* When HW VLAN acceleration is turned off, and the stack 995 * sets the protocol to 802.1q, the driver just need to 996 * set the protocol to the encapsulated ethertype. 997 */ 998 skb->protocol = vlan_get_protocol(skb); 999 return 0; 1000 } 1001 1002 if (skb_vlan_tag_present(skb)) { 1003 /* Based on hw strategy, use out_vtag in two layer tag case, 1004 * and use inner_vtag in one tag case. 1005 */ 1006 if (skb->protocol == htons(ETH_P_8021Q) && 1007 handle->port_base_vlan_state == 1008 HNAE3_PORT_BASE_VLAN_DISABLE) 1009 rc = HNS3_OUTER_VLAN_TAG; 1010 else 1011 rc = HNS3_INNER_VLAN_TAG; 1012 1013 skb->protocol = vlan_get_protocol(skb); 1014 return rc; 1015 } 1016 1017 rc = skb_cow_head(skb, 0); 1018 if (unlikely(rc < 0)) 1019 return rc; 1020 1021 vhdr = (struct vlan_ethhdr *)skb->data; 1022 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1023 & VLAN_PRIO_MASK); 1024 1025 skb->protocol = vlan_get_protocol(skb); 1026 return 0; 1027 } 1028 1029 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1030 struct sk_buff *skb, struct hns3_desc *desc) 1031 { 1032 u32 ol_type_vlan_len_msec = 0; 1033 u32 type_cs_vlan_tso = 0; 1034 u32 paylen = skb->len; 1035 u16 inner_vtag = 0; 1036 u16 out_vtag = 0; 1037 u16 mss = 0; 1038 int ret; 1039 1040 ret = hns3_handle_vtags(ring, skb); 1041 if (unlikely(ret < 0)) { 1042 u64_stats_update_begin(&ring->syncp); 1043 ring->stats.tx_vlan_err++; 1044 u64_stats_update_end(&ring->syncp); 1045 return ret; 1046 } else if (ret == HNS3_INNER_VLAN_TAG) { 1047 inner_vtag = skb_vlan_tag_get(skb); 1048 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1049 VLAN_PRIO_MASK; 1050 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1051 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1052 out_vtag = skb_vlan_tag_get(skb); 1053 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1054 VLAN_PRIO_MASK; 1055 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1056 1); 1057 } 1058 1059 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1060 u8 ol4_proto, il4_proto; 1061 1062 skb_reset_mac_len(skb); 1063 1064 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1065 if (unlikely(ret)) { 1066 u64_stats_update_begin(&ring->syncp); 1067 ring->stats.tx_l4_proto_err++; 1068 u64_stats_update_end(&ring->syncp); 1069 return ret; 1070 } 1071 1072 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1073 &type_cs_vlan_tso, 1074 &ol_type_vlan_len_msec); 1075 if (unlikely(ret)) { 1076 u64_stats_update_begin(&ring->syncp); 1077 ring->stats.tx_l2l3l4_err++; 1078 u64_stats_update_end(&ring->syncp); 1079 return ret; 1080 } 1081 1082 ret = hns3_set_tso(skb, &paylen, &mss, 1083 &type_cs_vlan_tso); 1084 if (unlikely(ret)) { 1085 u64_stats_update_begin(&ring->syncp); 1086 ring->stats.tx_tso_err++; 1087 u64_stats_update_end(&ring->syncp); 1088 return ret; 1089 } 1090 } 1091 1092 /* Set txbd */ 1093 desc->tx.ol_type_vlan_len_msec = 1094 cpu_to_le32(ol_type_vlan_len_msec); 1095 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1096 desc->tx.paylen = cpu_to_le32(paylen); 1097 desc->tx.mss = cpu_to_le16(mss); 1098 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1099 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1100 1101 return 0; 1102 } 1103 1104 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1105 unsigned int size, int frag_end, 1106 enum hns_desc_type type) 1107 { 1108 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1109 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1110 struct device *dev = ring_to_dev(ring); 1111 skb_frag_t *frag; 1112 unsigned int frag_buf_num; 1113 int k, sizeoflast; 1114 dma_addr_t dma; 1115 1116 if (type == DESC_TYPE_SKB) { 1117 struct sk_buff *skb = (struct sk_buff *)priv; 1118 int ret; 1119 1120 ret = hns3_fill_skb_desc(ring, skb, desc); 1121 if (unlikely(ret)) 1122 return ret; 1123 1124 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1125 } else { 1126 frag = (skb_frag_t *)priv; 1127 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1128 } 1129 1130 if (unlikely(dma_mapping_error(dev, dma))) { 1131 u64_stats_update_begin(&ring->syncp); 1132 ring->stats.sw_err_cnt++; 1133 u64_stats_update_end(&ring->syncp); 1134 return -ENOMEM; 1135 } 1136 1137 desc_cb->length = size; 1138 1139 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1140 u16 bdtp_fe_sc_vld_ra_ri = 0; 1141 1142 desc_cb->priv = priv; 1143 desc_cb->dma = dma; 1144 desc_cb->type = type; 1145 desc->addr = cpu_to_le64(dma); 1146 desc->tx.send_size = cpu_to_le16(size); 1147 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 1148 desc->tx.bdtp_fe_sc_vld_ra_ri = 1149 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1150 1151 ring_ptr_move_fw(ring, next_to_use); 1152 return 0; 1153 } 1154 1155 frag_buf_num = hns3_tx_bd_count(size); 1156 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1157 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1158 1159 /* When frag size is bigger than hardware limit, split this frag */ 1160 for (k = 0; k < frag_buf_num; k++) { 1161 u16 bdtp_fe_sc_vld_ra_ri = 0; 1162 1163 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1164 desc_cb->priv = priv; 1165 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1166 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1167 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1168 1169 /* now, fill the descriptor */ 1170 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1171 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1172 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1173 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1174 frag_end && (k == frag_buf_num - 1) ? 1175 1 : 0); 1176 desc->tx.bdtp_fe_sc_vld_ra_ri = 1177 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1178 1179 /* move ring pointer to next */ 1180 ring_ptr_move_fw(ring, next_to_use); 1181 1182 desc_cb = &ring->desc_cb[ring->next_to_use]; 1183 desc = &ring->desc[ring->next_to_use]; 1184 } 1185 1186 return 0; 1187 } 1188 1189 static unsigned int hns3_nic_bd_num(struct sk_buff *skb) 1190 { 1191 unsigned int bd_num; 1192 int i; 1193 1194 /* if the total len is within the max bd limit */ 1195 if (likely(skb->len <= HNS3_MAX_BD_SIZE)) 1196 return skb_shinfo(skb)->nr_frags + 1; 1197 1198 bd_num = hns3_tx_bd_count(skb_headlen(skb)); 1199 1200 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1201 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1202 bd_num += hns3_tx_bd_count(skb_frag_size(frag)); 1203 } 1204 1205 return bd_num; 1206 } 1207 1208 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1209 { 1210 if (!skb->encapsulation) 1211 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1212 1213 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1214 } 1215 1216 /* HW need every continuous 8 buffer data to be larger than MSS, 1217 * we simplify it by ensuring skb_headlen + the first continuous 1218 * 7 frags to to be larger than gso header len + mss, and the remaining 1219 * continuous 7 frags to be larger than MSS except the last 7 frags. 1220 */ 1221 static bool hns3_skb_need_linearized(struct sk_buff *skb) 1222 { 1223 int bd_limit = HNS3_MAX_BD_NUM_NORMAL - 1; 1224 unsigned int tot_len = 0; 1225 int i; 1226 1227 for (i = 0; i < bd_limit; i++) 1228 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i]); 1229 1230 /* ensure headlen + the first 7 frags is greater than mss + header 1231 * and the first 7 frags is greater than mss. 1232 */ 1233 if (((tot_len + skb_headlen(skb)) < (skb_shinfo(skb)->gso_size + 1234 hns3_gso_hdr_len(skb))) || (tot_len < skb_shinfo(skb)->gso_size)) 1235 return true; 1236 1237 /* ensure the remaining continuous 7 buffer is greater than mss */ 1238 for (i = 0; i < (skb_shinfo(skb)->nr_frags - bd_limit - 1); i++) { 1239 tot_len -= skb_frag_size(&skb_shinfo(skb)->frags[i]); 1240 tot_len += skb_frag_size(&skb_shinfo(skb)->frags[i + bd_limit]); 1241 1242 if (tot_len < skb_shinfo(skb)->gso_size) 1243 return true; 1244 } 1245 1246 return false; 1247 } 1248 1249 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1250 struct sk_buff **out_skb) 1251 { 1252 struct sk_buff *skb = *out_skb; 1253 unsigned int bd_num; 1254 1255 bd_num = hns3_nic_bd_num(skb); 1256 if (unlikely(bd_num > HNS3_MAX_BD_NUM_NORMAL)) { 1257 struct sk_buff *new_skb; 1258 1259 if (skb_is_gso(skb) && bd_num <= HNS3_MAX_BD_NUM_TSO && 1260 !hns3_skb_need_linearized(skb)) 1261 goto out; 1262 1263 /* manual split the send packet */ 1264 new_skb = skb_copy(skb, GFP_ATOMIC); 1265 if (!new_skb) 1266 return -ENOMEM; 1267 dev_kfree_skb_any(skb); 1268 *out_skb = new_skb; 1269 1270 bd_num = hns3_nic_bd_num(new_skb); 1271 if ((skb_is_gso(new_skb) && bd_num > HNS3_MAX_BD_NUM_TSO) || 1272 (!skb_is_gso(new_skb) && bd_num > HNS3_MAX_BD_NUM_NORMAL)) 1273 return -ENOMEM; 1274 1275 u64_stats_update_begin(&ring->syncp); 1276 ring->stats.tx_copy++; 1277 u64_stats_update_end(&ring->syncp); 1278 } 1279 1280 out: 1281 if (unlikely(ring_space(ring) < bd_num)) 1282 return -EBUSY; 1283 1284 return bd_num; 1285 } 1286 1287 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1288 { 1289 struct device *dev = ring_to_dev(ring); 1290 unsigned int i; 1291 1292 for (i = 0; i < ring->desc_num; i++) { 1293 /* check if this is where we started */ 1294 if (ring->next_to_use == next_to_use_orig) 1295 break; 1296 1297 /* rollback one */ 1298 ring_ptr_move_bw(ring, next_to_use); 1299 1300 /* unmap the descriptor dma address */ 1301 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1302 dma_unmap_single(dev, 1303 ring->desc_cb[ring->next_to_use].dma, 1304 ring->desc_cb[ring->next_to_use].length, 1305 DMA_TO_DEVICE); 1306 else if (ring->desc_cb[ring->next_to_use].length) 1307 dma_unmap_page(dev, 1308 ring->desc_cb[ring->next_to_use].dma, 1309 ring->desc_cb[ring->next_to_use].length, 1310 DMA_TO_DEVICE); 1311 1312 ring->desc_cb[ring->next_to_use].length = 0; 1313 ring->desc_cb[ring->next_to_use].dma = 0; 1314 } 1315 } 1316 1317 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1318 { 1319 struct hns3_nic_priv *priv = netdev_priv(netdev); 1320 struct hns3_nic_ring_data *ring_data = 1321 &tx_ring_data(priv, skb->queue_mapping); 1322 struct hns3_enet_ring *ring = ring_data->ring; 1323 struct netdev_queue *dev_queue; 1324 skb_frag_t *frag; 1325 int next_to_use_head; 1326 int buf_num; 1327 int seg_num; 1328 int size; 1329 int ret; 1330 int i; 1331 1332 /* Prefetch the data used later */ 1333 prefetch(skb->data); 1334 1335 buf_num = hns3_nic_maybe_stop_tx(ring, &skb); 1336 if (unlikely(buf_num <= 0)) { 1337 if (buf_num == -EBUSY) { 1338 u64_stats_update_begin(&ring->syncp); 1339 ring->stats.tx_busy++; 1340 u64_stats_update_end(&ring->syncp); 1341 goto out_net_tx_busy; 1342 } else if (buf_num == -ENOMEM) { 1343 u64_stats_update_begin(&ring->syncp); 1344 ring->stats.sw_err_cnt++; 1345 u64_stats_update_end(&ring->syncp); 1346 } 1347 1348 hns3_rl_err(netdev, "xmit error: %d!\n", buf_num); 1349 goto out_err_tx_ok; 1350 } 1351 1352 /* No. of segments (plus a header) */ 1353 seg_num = skb_shinfo(skb)->nr_frags + 1; 1354 /* Fill the first part */ 1355 size = skb_headlen(skb); 1356 1357 next_to_use_head = ring->next_to_use; 1358 1359 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1360 DESC_TYPE_SKB); 1361 if (unlikely(ret)) 1362 goto fill_err; 1363 1364 /* Fill the fragments */ 1365 for (i = 1; i < seg_num; i++) { 1366 frag = &skb_shinfo(skb)->frags[i - 1]; 1367 size = skb_frag_size(frag); 1368 1369 ret = hns3_fill_desc(ring, frag, size, 1370 seg_num - 1 == i ? 1 : 0, 1371 DESC_TYPE_PAGE); 1372 1373 if (unlikely(ret)) 1374 goto fill_err; 1375 } 1376 1377 /* Complete translate all packets */ 1378 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1379 netdev_tx_sent_queue(dev_queue, skb->len); 1380 1381 wmb(); /* Commit all data before submit */ 1382 1383 hnae3_queue_xmit(ring->tqp, buf_num); 1384 1385 return NETDEV_TX_OK; 1386 1387 fill_err: 1388 hns3_clear_desc(ring, next_to_use_head); 1389 1390 out_err_tx_ok: 1391 dev_kfree_skb_any(skb); 1392 return NETDEV_TX_OK; 1393 1394 out_net_tx_busy: 1395 netif_stop_subqueue(netdev, ring_data->queue_index); 1396 smp_mb(); /* Commit all data before submit */ 1397 1398 return NETDEV_TX_BUSY; 1399 } 1400 1401 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1402 { 1403 struct hnae3_handle *h = hns3_get_handle(netdev); 1404 struct sockaddr *mac_addr = p; 1405 int ret; 1406 1407 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1408 return -EADDRNOTAVAIL; 1409 1410 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1411 netdev_info(netdev, "already using mac address %pM\n", 1412 mac_addr->sa_data); 1413 return 0; 1414 } 1415 1416 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1417 if (ret) { 1418 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1419 return ret; 1420 } 1421 1422 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1423 1424 return 0; 1425 } 1426 1427 static int hns3_nic_do_ioctl(struct net_device *netdev, 1428 struct ifreq *ifr, int cmd) 1429 { 1430 struct hnae3_handle *h = hns3_get_handle(netdev); 1431 1432 if (!netif_running(netdev)) 1433 return -EINVAL; 1434 1435 if (!h->ae_algo->ops->do_ioctl) 1436 return -EOPNOTSUPP; 1437 1438 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1439 } 1440 1441 static int hns3_nic_set_features(struct net_device *netdev, 1442 netdev_features_t features) 1443 { 1444 netdev_features_t changed = netdev->features ^ features; 1445 struct hns3_nic_priv *priv = netdev_priv(netdev); 1446 struct hnae3_handle *h = priv->ae_handle; 1447 bool enable; 1448 int ret; 1449 1450 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1451 enable = !!(features & NETIF_F_GRO_HW); 1452 ret = h->ae_algo->ops->set_gro_en(h, enable); 1453 if (ret) 1454 return ret; 1455 } 1456 1457 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1458 h->ae_algo->ops->enable_vlan_filter) { 1459 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1460 h->ae_algo->ops->enable_vlan_filter(h, enable); 1461 } 1462 1463 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1464 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1465 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1466 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1467 if (ret) 1468 return ret; 1469 } 1470 1471 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1472 enable = !!(features & NETIF_F_NTUPLE); 1473 h->ae_algo->ops->enable_fd(h, enable); 1474 } 1475 1476 netdev->features = features; 1477 return 0; 1478 } 1479 1480 static void hns3_nic_get_stats64(struct net_device *netdev, 1481 struct rtnl_link_stats64 *stats) 1482 { 1483 struct hns3_nic_priv *priv = netdev_priv(netdev); 1484 int queue_num = priv->ae_handle->kinfo.num_tqps; 1485 struct hnae3_handle *handle = priv->ae_handle; 1486 struct hns3_enet_ring *ring; 1487 u64 rx_length_errors = 0; 1488 u64 rx_crc_errors = 0; 1489 u64 rx_multicast = 0; 1490 unsigned int start; 1491 u64 tx_errors = 0; 1492 u64 rx_errors = 0; 1493 unsigned int idx; 1494 u64 tx_bytes = 0; 1495 u64 rx_bytes = 0; 1496 u64 tx_pkts = 0; 1497 u64 rx_pkts = 0; 1498 u64 tx_drop = 0; 1499 u64 rx_drop = 0; 1500 1501 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1502 return; 1503 1504 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1505 1506 for (idx = 0; idx < queue_num; idx++) { 1507 /* fetch the tx stats */ 1508 ring = priv->ring_data[idx].ring; 1509 do { 1510 start = u64_stats_fetch_begin_irq(&ring->syncp); 1511 tx_bytes += ring->stats.tx_bytes; 1512 tx_pkts += ring->stats.tx_pkts; 1513 tx_drop += ring->stats.sw_err_cnt; 1514 tx_drop += ring->stats.tx_vlan_err; 1515 tx_drop += ring->stats.tx_l4_proto_err; 1516 tx_drop += ring->stats.tx_l2l3l4_err; 1517 tx_drop += ring->stats.tx_tso_err; 1518 tx_errors += ring->stats.sw_err_cnt; 1519 tx_errors += ring->stats.tx_vlan_err; 1520 tx_errors += ring->stats.tx_l4_proto_err; 1521 tx_errors += ring->stats.tx_l2l3l4_err; 1522 tx_errors += ring->stats.tx_tso_err; 1523 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1524 1525 /* fetch the rx stats */ 1526 ring = priv->ring_data[idx + queue_num].ring; 1527 do { 1528 start = u64_stats_fetch_begin_irq(&ring->syncp); 1529 rx_bytes += ring->stats.rx_bytes; 1530 rx_pkts += ring->stats.rx_pkts; 1531 rx_drop += ring->stats.l2_err; 1532 rx_errors += ring->stats.l2_err; 1533 rx_errors += ring->stats.l3l4_csum_err; 1534 rx_crc_errors += ring->stats.l2_err; 1535 rx_multicast += ring->stats.rx_multicast; 1536 rx_length_errors += ring->stats.err_pkt_len; 1537 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1538 } 1539 1540 stats->tx_bytes = tx_bytes; 1541 stats->tx_packets = tx_pkts; 1542 stats->rx_bytes = rx_bytes; 1543 stats->rx_packets = rx_pkts; 1544 1545 stats->rx_errors = rx_errors; 1546 stats->multicast = rx_multicast; 1547 stats->rx_length_errors = rx_length_errors; 1548 stats->rx_crc_errors = rx_crc_errors; 1549 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1550 1551 stats->tx_errors = tx_errors; 1552 stats->rx_dropped = rx_drop; 1553 stats->tx_dropped = tx_drop; 1554 stats->collisions = netdev->stats.collisions; 1555 stats->rx_over_errors = netdev->stats.rx_over_errors; 1556 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1557 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1558 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1559 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1560 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1561 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1562 stats->tx_window_errors = netdev->stats.tx_window_errors; 1563 stats->rx_compressed = netdev->stats.rx_compressed; 1564 stats->tx_compressed = netdev->stats.tx_compressed; 1565 } 1566 1567 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1568 { 1569 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1570 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1571 struct hnae3_knic_private_info *kinfo; 1572 u8 tc = mqprio_qopt->qopt.num_tc; 1573 u16 mode = mqprio_qopt->mode; 1574 u8 hw = mqprio_qopt->qopt.hw; 1575 struct hnae3_handle *h; 1576 1577 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1578 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1579 return -EOPNOTSUPP; 1580 1581 if (tc > HNAE3_MAX_TC) 1582 return -EINVAL; 1583 1584 if (!netdev) 1585 return -EINVAL; 1586 1587 h = hns3_get_handle(netdev); 1588 kinfo = &h->kinfo; 1589 1590 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1591 1592 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1593 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1594 } 1595 1596 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1597 void *type_data) 1598 { 1599 if (type != TC_SETUP_QDISC_MQPRIO) 1600 return -EOPNOTSUPP; 1601 1602 return hns3_setup_tc(dev, type_data); 1603 } 1604 1605 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1606 __be16 proto, u16 vid) 1607 { 1608 struct hnae3_handle *h = hns3_get_handle(netdev); 1609 int ret = -EIO; 1610 1611 if (h->ae_algo->ops->set_vlan_filter) 1612 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1613 1614 return ret; 1615 } 1616 1617 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1618 __be16 proto, u16 vid) 1619 { 1620 struct hnae3_handle *h = hns3_get_handle(netdev); 1621 int ret = -EIO; 1622 1623 if (h->ae_algo->ops->set_vlan_filter) 1624 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1625 1626 return ret; 1627 } 1628 1629 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1630 u8 qos, __be16 vlan_proto) 1631 { 1632 struct hnae3_handle *h = hns3_get_handle(netdev); 1633 int ret = -EIO; 1634 1635 netif_dbg(h, drv, netdev, 1636 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=%u\n", 1637 vf, vlan, qos, vlan_proto); 1638 1639 if (h->ae_algo->ops->set_vf_vlan_filter) 1640 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1641 qos, vlan_proto); 1642 1643 return ret; 1644 } 1645 1646 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1647 { 1648 struct hnae3_handle *h = hns3_get_handle(netdev); 1649 int ret; 1650 1651 if (hns3_nic_resetting(netdev)) 1652 return -EBUSY; 1653 1654 if (!h->ae_algo->ops->set_mtu) 1655 return -EOPNOTSUPP; 1656 1657 netif_dbg(h, drv, netdev, 1658 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1659 1660 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1661 if (ret) 1662 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1663 ret); 1664 else 1665 netdev->mtu = new_mtu; 1666 1667 return ret; 1668 } 1669 1670 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1671 { 1672 struct hns3_nic_priv *priv = netdev_priv(ndev); 1673 struct hnae3_handle *h = hns3_get_handle(ndev); 1674 struct hns3_enet_ring *tx_ring = NULL; 1675 struct napi_struct *napi; 1676 int timeout_queue = 0; 1677 int hw_head, hw_tail; 1678 int fbd_num, fbd_oft; 1679 int ebd_num, ebd_oft; 1680 int bd_num, bd_err; 1681 int ring_en, tc; 1682 int i; 1683 1684 /* Find the stopped queue the same way the stack does */ 1685 for (i = 0; i < ndev->num_tx_queues; i++) { 1686 struct netdev_queue *q; 1687 unsigned long trans_start; 1688 1689 q = netdev_get_tx_queue(ndev, i); 1690 trans_start = q->trans_start; 1691 if (netif_xmit_stopped(q) && 1692 time_after(jiffies, 1693 (trans_start + ndev->watchdog_timeo))) { 1694 timeout_queue = i; 1695 break; 1696 } 1697 } 1698 1699 if (i == ndev->num_tx_queues) { 1700 netdev_info(ndev, 1701 "no netdev TX timeout queue found, timeout count: %llu\n", 1702 priv->tx_timeout_count); 1703 return false; 1704 } 1705 1706 priv->tx_timeout_count++; 1707 1708 tx_ring = priv->ring_data[timeout_queue].ring; 1709 napi = &tx_ring->tqp_vector->napi; 1710 1711 netdev_info(ndev, 1712 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1713 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1714 tx_ring->next_to_clean, napi->state); 1715 1716 netdev_info(ndev, 1717 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1718 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1719 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1720 1721 netdev_info(ndev, 1722 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1723 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1724 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1725 1726 /* When mac received many pause frames continuous, it's unable to send 1727 * packets, which may cause tx timeout 1728 */ 1729 if (h->ae_algo->ops->get_mac_stats) { 1730 struct hns3_mac_stats mac_stats; 1731 1732 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1733 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1734 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1735 } 1736 1737 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1738 HNS3_RING_TX_RING_HEAD_REG); 1739 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1740 HNS3_RING_TX_RING_TAIL_REG); 1741 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1742 HNS3_RING_TX_RING_FBDNUM_REG); 1743 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1744 HNS3_RING_TX_RING_OFFSET_REG); 1745 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1746 HNS3_RING_TX_RING_EBDNUM_REG); 1747 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1748 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1749 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1750 HNS3_RING_TX_RING_BD_NUM_REG); 1751 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1752 HNS3_RING_TX_RING_BD_ERR_REG); 1753 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1754 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1755 1756 netdev_info(ndev, 1757 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1758 bd_num, hw_head, hw_tail, bd_err, 1759 readl(tx_ring->tqp_vector->mask_addr)); 1760 netdev_info(ndev, 1761 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1762 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1763 1764 return true; 1765 } 1766 1767 static void hns3_nic_net_timeout(struct net_device *ndev) 1768 { 1769 struct hns3_nic_priv *priv = netdev_priv(ndev); 1770 struct hnae3_handle *h = priv->ae_handle; 1771 1772 if (!hns3_get_tx_timeo_queue_info(ndev)) 1773 return; 1774 1775 /* request the reset, and let the hclge to determine 1776 * which reset level should be done 1777 */ 1778 if (h->ae_algo->ops->reset_event) 1779 h->ae_algo->ops->reset_event(h->pdev, h); 1780 } 1781 1782 #ifdef CONFIG_RFS_ACCEL 1783 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1784 u16 rxq_index, u32 flow_id) 1785 { 1786 struct hnae3_handle *h = hns3_get_handle(dev); 1787 struct flow_keys fkeys; 1788 1789 if (!h->ae_algo->ops->add_arfs_entry) 1790 return -EOPNOTSUPP; 1791 1792 if (skb->encapsulation) 1793 return -EPROTONOSUPPORT; 1794 1795 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1796 return -EPROTONOSUPPORT; 1797 1798 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1799 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1800 (fkeys.basic.ip_proto != IPPROTO_TCP && 1801 fkeys.basic.ip_proto != IPPROTO_UDP)) 1802 return -EPROTONOSUPPORT; 1803 1804 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1805 } 1806 #endif 1807 1808 static const struct net_device_ops hns3_nic_netdev_ops = { 1809 .ndo_open = hns3_nic_net_open, 1810 .ndo_stop = hns3_nic_net_stop, 1811 .ndo_start_xmit = hns3_nic_net_xmit, 1812 .ndo_tx_timeout = hns3_nic_net_timeout, 1813 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1814 .ndo_do_ioctl = hns3_nic_do_ioctl, 1815 .ndo_change_mtu = hns3_nic_change_mtu, 1816 .ndo_set_features = hns3_nic_set_features, 1817 .ndo_get_stats64 = hns3_nic_get_stats64, 1818 .ndo_setup_tc = hns3_nic_setup_tc, 1819 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1820 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1821 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1822 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1823 #ifdef CONFIG_RFS_ACCEL 1824 .ndo_rx_flow_steer = hns3_rx_flow_steer, 1825 #endif 1826 1827 }; 1828 1829 bool hns3_is_phys_func(struct pci_dev *pdev) 1830 { 1831 u32 dev_id = pdev->device; 1832 1833 switch (dev_id) { 1834 case HNAE3_DEV_ID_GE: 1835 case HNAE3_DEV_ID_25GE: 1836 case HNAE3_DEV_ID_25GE_RDMA: 1837 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1838 case HNAE3_DEV_ID_50GE_RDMA: 1839 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1840 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1841 return true; 1842 case HNAE3_DEV_ID_100G_VF: 1843 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1844 return false; 1845 default: 1846 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1847 dev_id); 1848 } 1849 1850 return false; 1851 } 1852 1853 static void hns3_disable_sriov(struct pci_dev *pdev) 1854 { 1855 /* If our VFs are assigned we cannot shut down SR-IOV 1856 * without causing issues, so just leave the hardware 1857 * available but disabled 1858 */ 1859 if (pci_vfs_assigned(pdev)) { 1860 dev_warn(&pdev->dev, 1861 "disabling driver while VFs are assigned\n"); 1862 return; 1863 } 1864 1865 pci_disable_sriov(pdev); 1866 } 1867 1868 static void hns3_get_dev_capability(struct pci_dev *pdev, 1869 struct hnae3_ae_dev *ae_dev) 1870 { 1871 if (pdev->revision >= 0x21) { 1872 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1873 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1874 } 1875 } 1876 1877 /* hns3_probe - Device initialization routine 1878 * @pdev: PCI device information struct 1879 * @ent: entry in hns3_pci_tbl 1880 * 1881 * hns3_probe initializes a PF identified by a pci_dev structure. 1882 * The OS initialization, configuring of the PF private structure, 1883 * and a hardware reset occur. 1884 * 1885 * Returns 0 on success, negative on failure 1886 */ 1887 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1888 { 1889 struct hnae3_ae_dev *ae_dev; 1890 int ret; 1891 1892 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 1893 if (!ae_dev) { 1894 ret = -ENOMEM; 1895 return ret; 1896 } 1897 1898 ae_dev->pdev = pdev; 1899 ae_dev->flag = ent->driver_data; 1900 ae_dev->reset_type = HNAE3_NONE_RESET; 1901 hns3_get_dev_capability(pdev, ae_dev); 1902 pci_set_drvdata(pdev, ae_dev); 1903 1904 ret = hnae3_register_ae_dev(ae_dev); 1905 if (ret) { 1906 devm_kfree(&pdev->dev, ae_dev); 1907 pci_set_drvdata(pdev, NULL); 1908 } 1909 1910 return ret; 1911 } 1912 1913 /* hns3_remove - Device removal routine 1914 * @pdev: PCI device information struct 1915 */ 1916 static void hns3_remove(struct pci_dev *pdev) 1917 { 1918 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1919 1920 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1921 hns3_disable_sriov(pdev); 1922 1923 hnae3_unregister_ae_dev(ae_dev); 1924 pci_set_drvdata(pdev, NULL); 1925 } 1926 1927 /** 1928 * hns3_pci_sriov_configure 1929 * @pdev: pointer to a pci_dev structure 1930 * @num_vfs: number of VFs to allocate 1931 * 1932 * Enable or change the number of VFs. Called when the user updates the number 1933 * of VFs in sysfs. 1934 **/ 1935 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1936 { 1937 int ret; 1938 1939 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1940 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1941 return -EINVAL; 1942 } 1943 1944 if (num_vfs) { 1945 ret = pci_enable_sriov(pdev, num_vfs); 1946 if (ret) 1947 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1948 else 1949 return num_vfs; 1950 } else if (!pci_vfs_assigned(pdev)) { 1951 pci_disable_sriov(pdev); 1952 } else { 1953 dev_warn(&pdev->dev, 1954 "Unable to free VFs because some are assigned to VMs.\n"); 1955 } 1956 1957 return 0; 1958 } 1959 1960 static void hns3_shutdown(struct pci_dev *pdev) 1961 { 1962 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1963 1964 hnae3_unregister_ae_dev(ae_dev); 1965 devm_kfree(&pdev->dev, ae_dev); 1966 pci_set_drvdata(pdev, NULL); 1967 1968 if (system_state == SYSTEM_POWER_OFF) 1969 pci_set_power_state(pdev, PCI_D3hot); 1970 } 1971 1972 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1973 pci_channel_state_t state) 1974 { 1975 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1976 pci_ers_result_t ret; 1977 1978 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1979 1980 if (state == pci_channel_io_perm_failure) 1981 return PCI_ERS_RESULT_DISCONNECT; 1982 1983 if (!ae_dev || !ae_dev->ops) { 1984 dev_err(&pdev->dev, 1985 "Can't recover - error happened before device initialized\n"); 1986 return PCI_ERS_RESULT_NONE; 1987 } 1988 1989 if (ae_dev->ops->handle_hw_ras_error) 1990 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1991 else 1992 return PCI_ERS_RESULT_NONE; 1993 1994 return ret; 1995 } 1996 1997 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1998 { 1999 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2000 const struct hnae3_ae_ops *ops; 2001 enum hnae3_reset_type reset_type; 2002 struct device *dev = &pdev->dev; 2003 2004 if (!ae_dev || !ae_dev->ops) 2005 return PCI_ERS_RESULT_NONE; 2006 2007 ops = ae_dev->ops; 2008 /* request the reset */ 2009 if (ops->reset_event && ops->get_reset_level) { 2010 if (ae_dev->hw_err_reset_req) { 2011 reset_type = ops->get_reset_level(ae_dev, 2012 &ae_dev->hw_err_reset_req); 2013 ops->set_default_reset_request(ae_dev, reset_type); 2014 dev_info(dev, "requesting reset due to PCI error\n"); 2015 ops->reset_event(pdev, NULL); 2016 } 2017 2018 return PCI_ERS_RESULT_RECOVERED; 2019 } 2020 2021 return PCI_ERS_RESULT_DISCONNECT; 2022 } 2023 2024 static void hns3_reset_prepare(struct pci_dev *pdev) 2025 { 2026 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2027 2028 dev_info(&pdev->dev, "hns3 flr prepare\n"); 2029 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2030 ae_dev->ops->flr_prepare(ae_dev); 2031 } 2032 2033 static void hns3_reset_done(struct pci_dev *pdev) 2034 { 2035 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2036 2037 dev_info(&pdev->dev, "hns3 flr done\n"); 2038 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2039 ae_dev->ops->flr_done(ae_dev); 2040 } 2041 2042 static const struct pci_error_handlers hns3_err_handler = { 2043 .error_detected = hns3_error_detected, 2044 .slot_reset = hns3_slot_reset, 2045 .reset_prepare = hns3_reset_prepare, 2046 .reset_done = hns3_reset_done, 2047 }; 2048 2049 static struct pci_driver hns3_driver = { 2050 .name = hns3_driver_name, 2051 .id_table = hns3_pci_tbl, 2052 .probe = hns3_probe, 2053 .remove = hns3_remove, 2054 .shutdown = hns3_shutdown, 2055 .sriov_configure = hns3_pci_sriov_configure, 2056 .err_handler = &hns3_err_handler, 2057 }; 2058 2059 /* set default feature to hns3 */ 2060 static void hns3_set_default_feature(struct net_device *netdev) 2061 { 2062 struct hnae3_handle *h = hns3_get_handle(netdev); 2063 struct pci_dev *pdev = h->pdev; 2064 2065 netdev->priv_flags |= IFF_UNICAST_FLT; 2066 2067 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2068 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2069 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2070 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2071 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2072 2073 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 2074 2075 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2076 2077 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2078 NETIF_F_HW_VLAN_CTAG_FILTER | 2079 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2080 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2081 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2082 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2083 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2084 2085 netdev->vlan_features |= 2086 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2087 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2088 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2089 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2090 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2091 2092 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2093 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2094 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2095 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2096 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2097 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 2098 2099 if (pdev->revision >= 0x21) { 2100 netdev->hw_features |= NETIF_F_GRO_HW; 2101 netdev->features |= NETIF_F_GRO_HW; 2102 2103 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2104 netdev->hw_features |= NETIF_F_NTUPLE; 2105 netdev->features |= NETIF_F_NTUPLE; 2106 } 2107 } 2108 } 2109 2110 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2111 struct hns3_desc_cb *cb) 2112 { 2113 unsigned int order = hns3_page_order(ring); 2114 struct page *p; 2115 2116 p = dev_alloc_pages(order); 2117 if (!p) 2118 return -ENOMEM; 2119 2120 cb->priv = p; 2121 cb->page_offset = 0; 2122 cb->reuse_flag = 0; 2123 cb->buf = page_address(p); 2124 cb->length = hns3_page_size(ring); 2125 cb->type = DESC_TYPE_PAGE; 2126 2127 return 0; 2128 } 2129 2130 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2131 struct hns3_desc_cb *cb) 2132 { 2133 if (cb->type == DESC_TYPE_SKB) 2134 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2135 else if (!HNAE3_IS_TX_RING(ring)) 2136 put_page((struct page *)cb->priv); 2137 memset(cb, 0, sizeof(*cb)); 2138 } 2139 2140 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2141 { 2142 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2143 cb->length, ring_to_dma_dir(ring)); 2144 2145 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2146 return -EIO; 2147 2148 return 0; 2149 } 2150 2151 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2152 struct hns3_desc_cb *cb) 2153 { 2154 if (cb->type == DESC_TYPE_SKB) 2155 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2156 ring_to_dma_dir(ring)); 2157 else if (cb->length) 2158 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2159 ring_to_dma_dir(ring)); 2160 } 2161 2162 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2163 { 2164 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2165 ring->desc[i].addr = 0; 2166 } 2167 2168 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2169 { 2170 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2171 2172 if (!ring->desc_cb[i].dma) 2173 return; 2174 2175 hns3_buffer_detach(ring, i); 2176 hns3_free_buffer(ring, cb); 2177 } 2178 2179 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2180 { 2181 int i; 2182 2183 for (i = 0; i < ring->desc_num; i++) 2184 hns3_free_buffer_detach(ring, i); 2185 } 2186 2187 /* free desc along with its attached buffer */ 2188 static void hns3_free_desc(struct hns3_enet_ring *ring) 2189 { 2190 int size = ring->desc_num * sizeof(ring->desc[0]); 2191 2192 hns3_free_buffers(ring); 2193 2194 if (ring->desc) { 2195 dma_free_coherent(ring_to_dev(ring), size, 2196 ring->desc, ring->desc_dma_addr); 2197 ring->desc = NULL; 2198 } 2199 } 2200 2201 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2202 { 2203 int size = ring->desc_num * sizeof(ring->desc[0]); 2204 2205 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2206 &ring->desc_dma_addr, GFP_KERNEL); 2207 if (!ring->desc) 2208 return -ENOMEM; 2209 2210 return 0; 2211 } 2212 2213 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2214 struct hns3_desc_cb *cb) 2215 { 2216 int ret; 2217 2218 ret = hns3_alloc_buffer(ring, cb); 2219 if (ret) 2220 goto out; 2221 2222 ret = hns3_map_buffer(ring, cb); 2223 if (ret) 2224 goto out_with_buf; 2225 2226 return 0; 2227 2228 out_with_buf: 2229 hns3_free_buffer(ring, cb); 2230 out: 2231 return ret; 2232 } 2233 2234 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2235 { 2236 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2237 2238 if (ret) 2239 return ret; 2240 2241 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2242 2243 return 0; 2244 } 2245 2246 /* Allocate memory for raw pkg, and map with dma */ 2247 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2248 { 2249 int i, j, ret; 2250 2251 for (i = 0; i < ring->desc_num; i++) { 2252 ret = hns3_alloc_buffer_attach(ring, i); 2253 if (ret) 2254 goto out_buffer_fail; 2255 } 2256 2257 return 0; 2258 2259 out_buffer_fail: 2260 for (j = i - 1; j >= 0; j--) 2261 hns3_free_buffer_detach(ring, j); 2262 return ret; 2263 } 2264 2265 /* detach a in-used buffer and replace with a reserved one */ 2266 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2267 struct hns3_desc_cb *res_cb) 2268 { 2269 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2270 ring->desc_cb[i] = *res_cb; 2271 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2272 ring->desc[i].rx.bd_base_info = 0; 2273 } 2274 2275 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2276 { 2277 ring->desc_cb[i].reuse_flag = 0; 2278 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2279 ring->desc_cb[i].page_offset); 2280 ring->desc[i].rx.bd_base_info = 0; 2281 } 2282 2283 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2284 int *bytes, int *pkts) 2285 { 2286 int ntc = ring->next_to_clean; 2287 struct hns3_desc_cb *desc_cb; 2288 2289 while (head != ntc) { 2290 desc_cb = &ring->desc_cb[ntc]; 2291 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2292 (*bytes) += desc_cb->length; 2293 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2294 hns3_free_buffer_detach(ring, ntc); 2295 2296 if (++ntc == ring->desc_num) 2297 ntc = 0; 2298 2299 /* Issue prefetch for next Tx descriptor */ 2300 prefetch(&ring->desc_cb[ntc]); 2301 } 2302 2303 /* This smp_store_release() pairs with smp_load_acquire() in 2304 * ring_space called by hns3_nic_net_xmit. 2305 */ 2306 smp_store_release(&ring->next_to_clean, ntc); 2307 } 2308 2309 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2310 { 2311 int u = ring->next_to_use; 2312 int c = ring->next_to_clean; 2313 2314 if (unlikely(h > ring->desc_num)) 2315 return 0; 2316 2317 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2318 } 2319 2320 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2321 { 2322 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2323 struct hns3_nic_priv *priv = netdev_priv(netdev); 2324 struct netdev_queue *dev_queue; 2325 int bytes, pkts; 2326 int head; 2327 2328 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2329 rmb(); /* Make sure head is ready before touch any data */ 2330 2331 if (is_ring_empty(ring) || head == ring->next_to_clean) 2332 return; /* no data to poll */ 2333 2334 if (unlikely(!is_valid_clean_head(ring, head))) { 2335 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2336 ring->next_to_use, ring->next_to_clean); 2337 2338 u64_stats_update_begin(&ring->syncp); 2339 ring->stats.io_err_cnt++; 2340 u64_stats_update_end(&ring->syncp); 2341 return; 2342 } 2343 2344 bytes = 0; 2345 pkts = 0; 2346 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2347 2348 ring->tqp_vector->tx_group.total_bytes += bytes; 2349 ring->tqp_vector->tx_group.total_packets += pkts; 2350 2351 u64_stats_update_begin(&ring->syncp); 2352 ring->stats.tx_bytes += bytes; 2353 ring->stats.tx_pkts += pkts; 2354 u64_stats_update_end(&ring->syncp); 2355 2356 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2357 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2358 2359 if (unlikely(pkts && netif_carrier_ok(netdev) && 2360 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2361 /* Make sure that anybody stopping the queue after this 2362 * sees the new next_to_clean. 2363 */ 2364 smp_mb(); 2365 if (netif_tx_queue_stopped(dev_queue) && 2366 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2367 netif_tx_wake_queue(dev_queue); 2368 ring->stats.restart_queue++; 2369 } 2370 } 2371 } 2372 2373 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2374 { 2375 int ntc = ring->next_to_clean; 2376 int ntu = ring->next_to_use; 2377 2378 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2379 } 2380 2381 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2382 int cleand_count) 2383 { 2384 struct hns3_desc_cb *desc_cb; 2385 struct hns3_desc_cb res_cbs; 2386 int i, ret; 2387 2388 for (i = 0; i < cleand_count; i++) { 2389 desc_cb = &ring->desc_cb[ring->next_to_use]; 2390 if (desc_cb->reuse_flag) { 2391 u64_stats_update_begin(&ring->syncp); 2392 ring->stats.reuse_pg_cnt++; 2393 u64_stats_update_end(&ring->syncp); 2394 2395 hns3_reuse_buffer(ring, ring->next_to_use); 2396 } else { 2397 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2398 if (ret) { 2399 u64_stats_update_begin(&ring->syncp); 2400 ring->stats.sw_err_cnt++; 2401 u64_stats_update_end(&ring->syncp); 2402 2403 hns3_rl_err(ring->tqp_vector->napi.dev, 2404 "alloc rx buffer failed: %d\n", 2405 ret); 2406 break; 2407 } 2408 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2409 2410 u64_stats_update_begin(&ring->syncp); 2411 ring->stats.non_reuse_pg++; 2412 u64_stats_update_end(&ring->syncp); 2413 } 2414 2415 ring_ptr_move_fw(ring, next_to_use); 2416 } 2417 2418 wmb(); /* Make all data has been write before submit */ 2419 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2420 } 2421 2422 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2423 struct hns3_enet_ring *ring, int pull_len, 2424 struct hns3_desc_cb *desc_cb) 2425 { 2426 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2427 int size = le16_to_cpu(desc->rx.size); 2428 u32 truesize = hns3_buf_size(ring); 2429 2430 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2431 size - pull_len, truesize); 2432 2433 /* Avoid re-using remote pages, or the stack is still using the page 2434 * when page_offset rollback to zero, flag default unreuse 2435 */ 2436 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) || 2437 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2438 return; 2439 2440 /* Move offset up to the next cache line */ 2441 desc_cb->page_offset += truesize; 2442 2443 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2444 desc_cb->reuse_flag = 1; 2445 /* Bump ref count on page before it is given */ 2446 get_page(desc_cb->priv); 2447 } else if (page_count(desc_cb->priv) == 1) { 2448 desc_cb->reuse_flag = 1; 2449 desc_cb->page_offset = 0; 2450 get_page(desc_cb->priv); 2451 } 2452 } 2453 2454 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2455 { 2456 __be16 type = skb->protocol; 2457 struct tcphdr *th; 2458 int depth = 0; 2459 2460 while (eth_type_vlan(type)) { 2461 struct vlan_hdr *vh; 2462 2463 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2464 return -EFAULT; 2465 2466 vh = (struct vlan_hdr *)(skb->data + depth); 2467 type = vh->h_vlan_encapsulated_proto; 2468 depth += VLAN_HLEN; 2469 } 2470 2471 skb_set_network_header(skb, depth); 2472 2473 if (type == htons(ETH_P_IP)) { 2474 const struct iphdr *iph = ip_hdr(skb); 2475 2476 depth += sizeof(struct iphdr); 2477 skb_set_transport_header(skb, depth); 2478 th = tcp_hdr(skb); 2479 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2480 iph->daddr, 0); 2481 } else if (type == htons(ETH_P_IPV6)) { 2482 const struct ipv6hdr *iph = ipv6_hdr(skb); 2483 2484 depth += sizeof(struct ipv6hdr); 2485 skb_set_transport_header(skb, depth); 2486 th = tcp_hdr(skb); 2487 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2488 &iph->daddr, 0); 2489 } else { 2490 hns3_rl_err(skb->dev, 2491 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2492 be16_to_cpu(type), depth); 2493 return -EFAULT; 2494 } 2495 2496 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2497 if (th->cwr) 2498 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2499 2500 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2501 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2502 2503 skb->csum_start = (unsigned char *)th - skb->head; 2504 skb->csum_offset = offsetof(struct tcphdr, check); 2505 skb->ip_summed = CHECKSUM_PARTIAL; 2506 return 0; 2507 } 2508 2509 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2510 u32 l234info, u32 bd_base_info, u32 ol_info) 2511 { 2512 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2513 int l3_type, l4_type; 2514 int ol4_type; 2515 2516 skb->ip_summed = CHECKSUM_NONE; 2517 2518 skb_checksum_none_assert(skb); 2519 2520 if (!(netdev->features & NETIF_F_RXCSUM)) 2521 return; 2522 2523 /* check if hardware has done checksum */ 2524 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2525 return; 2526 2527 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2528 BIT(HNS3_RXD_OL3E_B) | 2529 BIT(HNS3_RXD_OL4E_B)))) { 2530 u64_stats_update_begin(&ring->syncp); 2531 ring->stats.l3l4_csum_err++; 2532 u64_stats_update_end(&ring->syncp); 2533 2534 return; 2535 } 2536 2537 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2538 HNS3_RXD_OL4ID_S); 2539 switch (ol4_type) { 2540 case HNS3_OL4_TYPE_MAC_IN_UDP: 2541 case HNS3_OL4_TYPE_NVGRE: 2542 skb->csum_level = 1; 2543 /* fall through */ 2544 case HNS3_OL4_TYPE_NO_TUN: 2545 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2546 HNS3_RXD_L3ID_S); 2547 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2548 HNS3_RXD_L4ID_S); 2549 2550 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2551 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2552 l3_type == HNS3_L3_TYPE_IPV6) && 2553 (l4_type == HNS3_L4_TYPE_UDP || 2554 l4_type == HNS3_L4_TYPE_TCP || 2555 l4_type == HNS3_L4_TYPE_SCTP)) 2556 skb->ip_summed = CHECKSUM_UNNECESSARY; 2557 break; 2558 default: 2559 break; 2560 } 2561 } 2562 2563 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2564 { 2565 if (skb_has_frag_list(skb)) 2566 napi_gro_flush(&ring->tqp_vector->napi, false); 2567 2568 napi_gro_receive(&ring->tqp_vector->napi, skb); 2569 } 2570 2571 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2572 struct hns3_desc *desc, u32 l234info, 2573 u16 *vlan_tag) 2574 { 2575 struct hnae3_handle *handle = ring->tqp->handle; 2576 struct pci_dev *pdev = ring->tqp->handle->pdev; 2577 2578 if (pdev->revision == 0x20) { 2579 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2580 if (!(*vlan_tag & VLAN_VID_MASK)) 2581 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2582 2583 return (*vlan_tag != 0); 2584 } 2585 2586 #define HNS3_STRP_OUTER_VLAN 0x1 2587 #define HNS3_STRP_INNER_VLAN 0x2 2588 #define HNS3_STRP_BOTH 0x3 2589 2590 /* Hardware always insert VLAN tag into RX descriptor when 2591 * remove the tag from packet, driver needs to determine 2592 * reporting which tag to stack. 2593 */ 2594 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2595 HNS3_RXD_STRP_TAGP_S)) { 2596 case HNS3_STRP_OUTER_VLAN: 2597 if (handle->port_base_vlan_state != 2598 HNAE3_PORT_BASE_VLAN_DISABLE) 2599 return false; 2600 2601 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2602 return true; 2603 case HNS3_STRP_INNER_VLAN: 2604 if (handle->port_base_vlan_state != 2605 HNAE3_PORT_BASE_VLAN_DISABLE) 2606 return false; 2607 2608 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2609 return true; 2610 case HNS3_STRP_BOTH: 2611 if (handle->port_base_vlan_state == 2612 HNAE3_PORT_BASE_VLAN_DISABLE) 2613 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2614 else 2615 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2616 2617 return true; 2618 default: 2619 return false; 2620 } 2621 } 2622 2623 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2624 unsigned char *va) 2625 { 2626 #define HNS3_NEED_ADD_FRAG 1 2627 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2628 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2629 struct sk_buff *skb; 2630 2631 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2632 skb = ring->skb; 2633 if (unlikely(!skb)) { 2634 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2635 2636 u64_stats_update_begin(&ring->syncp); 2637 ring->stats.sw_err_cnt++; 2638 u64_stats_update_end(&ring->syncp); 2639 2640 return -ENOMEM; 2641 } 2642 2643 prefetchw(skb->data); 2644 2645 ring->pending_buf = 1; 2646 ring->frag_num = 0; 2647 ring->tail_skb = NULL; 2648 if (length <= HNS3_RX_HEAD_SIZE) { 2649 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2650 2651 /* We can reuse buffer as-is, just make sure it is local */ 2652 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id())) 2653 desc_cb->reuse_flag = 1; 2654 else /* This page cannot be reused so discard it */ 2655 put_page(desc_cb->priv); 2656 2657 ring_ptr_move_fw(ring, next_to_clean); 2658 return 0; 2659 } 2660 u64_stats_update_begin(&ring->syncp); 2661 ring->stats.seg_pkt_cnt++; 2662 u64_stats_update_end(&ring->syncp); 2663 2664 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2665 __skb_put(skb, ring->pull_len); 2666 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2667 desc_cb); 2668 ring_ptr_move_fw(ring, next_to_clean); 2669 2670 return HNS3_NEED_ADD_FRAG; 2671 } 2672 2673 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2674 struct sk_buff **out_skb, bool pending) 2675 { 2676 struct sk_buff *skb = *out_skb; 2677 struct sk_buff *head_skb = *out_skb; 2678 struct sk_buff *new_skb; 2679 struct hns3_desc_cb *desc_cb; 2680 struct hns3_desc *pre_desc; 2681 u32 bd_base_info; 2682 int pre_bd; 2683 2684 /* if there is pending bd, the SW param next_to_clean has moved 2685 * to next and the next is NULL 2686 */ 2687 if (pending) { 2688 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2689 ring->desc_num; 2690 pre_desc = &ring->desc[pre_bd]; 2691 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2692 } else { 2693 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2694 } 2695 2696 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2697 desc = &ring->desc[ring->next_to_clean]; 2698 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2699 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2700 /* make sure HW write desc complete */ 2701 dma_rmb(); 2702 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2703 return -ENXIO; 2704 2705 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2706 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2707 HNS3_RX_HEAD_SIZE); 2708 if (unlikely(!new_skb)) { 2709 hns3_rl_err(ring->tqp_vector->napi.dev, 2710 "alloc rx fraglist skb fail\n"); 2711 return -ENXIO; 2712 } 2713 ring->frag_num = 0; 2714 2715 if (ring->tail_skb) { 2716 ring->tail_skb->next = new_skb; 2717 ring->tail_skb = new_skb; 2718 } else { 2719 skb_shinfo(skb)->frag_list = new_skb; 2720 ring->tail_skb = new_skb; 2721 } 2722 } 2723 2724 if (ring->tail_skb) { 2725 head_skb->truesize += hns3_buf_size(ring); 2726 head_skb->data_len += le16_to_cpu(desc->rx.size); 2727 head_skb->len += le16_to_cpu(desc->rx.size); 2728 skb = ring->tail_skb; 2729 } 2730 2731 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2732 ring_ptr_move_fw(ring, next_to_clean); 2733 ring->pending_buf++; 2734 } 2735 2736 return 0; 2737 } 2738 2739 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2740 struct sk_buff *skb, u32 l234info, 2741 u32 bd_base_info, u32 ol_info) 2742 { 2743 u32 l3_type; 2744 2745 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2746 HNS3_RXD_GRO_SIZE_M, 2747 HNS3_RXD_GRO_SIZE_S); 2748 /* if there is no HW GRO, do not set gro params */ 2749 if (!skb_shinfo(skb)->gso_size) { 2750 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2751 return 0; 2752 } 2753 2754 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2755 HNS3_RXD_GRO_COUNT_M, 2756 HNS3_RXD_GRO_COUNT_S); 2757 2758 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2759 if (l3_type == HNS3_L3_TYPE_IPV4) 2760 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2761 else if (l3_type == HNS3_L3_TYPE_IPV6) 2762 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2763 else 2764 return -EFAULT; 2765 2766 return hns3_gro_complete(skb, l234info); 2767 } 2768 2769 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2770 struct sk_buff *skb, u32 rss_hash) 2771 { 2772 struct hnae3_handle *handle = ring->tqp->handle; 2773 enum pkt_hash_types rss_type; 2774 2775 if (rss_hash) 2776 rss_type = handle->kinfo.rss_type; 2777 else 2778 rss_type = PKT_HASH_TYPE_NONE; 2779 2780 skb_set_hash(skb, rss_hash, rss_type); 2781 } 2782 2783 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2784 { 2785 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2786 enum hns3_pkt_l2t_type l2_frame_type; 2787 u32 bd_base_info, l234info, ol_info; 2788 struct hns3_desc *desc; 2789 unsigned int len; 2790 int pre_ntc, ret; 2791 2792 /* bdinfo handled below is only valid on the last BD of the 2793 * current packet, and ring->next_to_clean indicates the first 2794 * descriptor of next packet, so need - 1 below. 2795 */ 2796 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 2797 (ring->desc_num - 1); 2798 desc = &ring->desc[pre_ntc]; 2799 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2800 l234info = le32_to_cpu(desc->rx.l234_info); 2801 ol_info = le32_to_cpu(desc->rx.ol_info); 2802 2803 /* Based on hw strategy, the tag offloaded will be stored at 2804 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2805 * in one layer tag case. 2806 */ 2807 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2808 u16 vlan_tag; 2809 2810 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2811 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2812 vlan_tag); 2813 } 2814 2815 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2816 BIT(HNS3_RXD_L2E_B))))) { 2817 u64_stats_update_begin(&ring->syncp); 2818 if (l234info & BIT(HNS3_RXD_L2E_B)) 2819 ring->stats.l2_err++; 2820 else 2821 ring->stats.err_pkt_len++; 2822 u64_stats_update_end(&ring->syncp); 2823 2824 return -EFAULT; 2825 } 2826 2827 len = skb->len; 2828 2829 /* Do update ip stack process */ 2830 skb->protocol = eth_type_trans(skb, netdev); 2831 2832 /* This is needed in order to enable forwarding support */ 2833 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 2834 bd_base_info, ol_info); 2835 if (unlikely(ret)) { 2836 u64_stats_update_begin(&ring->syncp); 2837 ring->stats.rx_err_cnt++; 2838 u64_stats_update_end(&ring->syncp); 2839 return ret; 2840 } 2841 2842 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2843 HNS3_RXD_DMAC_S); 2844 2845 u64_stats_update_begin(&ring->syncp); 2846 ring->stats.rx_pkts++; 2847 ring->stats.rx_bytes += len; 2848 2849 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2850 ring->stats.rx_multicast++; 2851 2852 u64_stats_update_end(&ring->syncp); 2853 2854 ring->tqp_vector->rx_group.total_bytes += len; 2855 2856 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 2857 return 0; 2858 } 2859 2860 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2861 struct sk_buff **out_skb) 2862 { 2863 struct sk_buff *skb = ring->skb; 2864 struct hns3_desc_cb *desc_cb; 2865 struct hns3_desc *desc; 2866 unsigned int length; 2867 u32 bd_base_info; 2868 int ret; 2869 2870 desc = &ring->desc[ring->next_to_clean]; 2871 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2872 2873 prefetch(desc); 2874 2875 length = le16_to_cpu(desc->rx.size); 2876 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2877 2878 /* Check valid BD */ 2879 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2880 return -ENXIO; 2881 2882 if (!skb) 2883 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2884 2885 /* Prefetch first cache line of first page 2886 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2887 * line size is 64B so need to prefetch twice to make it 128B. But in 2888 * actual we can have greater size of caches with 128B Level 1 cache 2889 * lines. In such a case, single fetch would suffice to cache in the 2890 * relevant part of the header. 2891 */ 2892 prefetch(ring->va); 2893 #if L1_CACHE_BYTES < 128 2894 prefetch(ring->va + L1_CACHE_BYTES); 2895 #endif 2896 2897 if (!skb) { 2898 ret = hns3_alloc_skb(ring, length, ring->va); 2899 *out_skb = skb = ring->skb; 2900 2901 if (ret < 0) /* alloc buffer fail */ 2902 return ret; 2903 if (ret > 0) { /* need add frag */ 2904 ret = hns3_add_frag(ring, desc, &skb, false); 2905 if (ret) 2906 return ret; 2907 2908 /* As the head data may be changed when GRO enable, copy 2909 * the head data in after other data rx completed 2910 */ 2911 memcpy(skb->data, ring->va, 2912 ALIGN(ring->pull_len, sizeof(long))); 2913 } 2914 } else { 2915 ret = hns3_add_frag(ring, desc, &skb, true); 2916 if (ret) 2917 return ret; 2918 2919 /* As the head data may be changed when GRO enable, copy 2920 * the head data in after other data rx completed 2921 */ 2922 memcpy(skb->data, ring->va, 2923 ALIGN(ring->pull_len, sizeof(long))); 2924 } 2925 2926 ret = hns3_handle_bdinfo(ring, skb); 2927 if (unlikely(ret)) { 2928 dev_kfree_skb_any(skb); 2929 return ret; 2930 } 2931 2932 skb_record_rx_queue(skb, ring->tqp->tqp_index); 2933 *out_skb = skb; 2934 2935 return 0; 2936 } 2937 2938 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 2939 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2940 { 2941 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2942 int unused_count = hns3_desc_unused(ring); 2943 struct sk_buff *skb = ring->skb; 2944 int recv_pkts = 0; 2945 int recv_bds = 0; 2946 int err, num; 2947 2948 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2949 rmb(); /* Make sure num taken effect before the other data is touched */ 2950 2951 num -= unused_count; 2952 unused_count -= ring->pending_buf; 2953 2954 while (recv_pkts < budget && recv_bds < num) { 2955 /* Reuse or realloc buffers */ 2956 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2957 hns3_nic_alloc_rx_buffers(ring, unused_count); 2958 unused_count = hns3_desc_unused(ring) - 2959 ring->pending_buf; 2960 } 2961 2962 /* Poll one pkt */ 2963 err = hns3_handle_rx_bd(ring, &skb); 2964 if (unlikely(!skb)) /* This fault cannot be repaired */ 2965 goto out; 2966 2967 if (err == -ENXIO) { /* Do not get FE for the packet */ 2968 goto out; 2969 } else if (unlikely(err)) { /* Do jump the err */ 2970 recv_bds += ring->pending_buf; 2971 unused_count += ring->pending_buf; 2972 ring->skb = NULL; 2973 ring->pending_buf = 0; 2974 continue; 2975 } 2976 2977 rx_fn(ring, skb); 2978 recv_bds += ring->pending_buf; 2979 unused_count += ring->pending_buf; 2980 ring->skb = NULL; 2981 ring->pending_buf = 0; 2982 2983 recv_pkts++; 2984 } 2985 2986 out: 2987 /* Make all data has been write before submit */ 2988 if (unused_count > 0) 2989 hns3_nic_alloc_rx_buffers(ring, unused_count); 2990 2991 return recv_pkts; 2992 } 2993 2994 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 2995 { 2996 #define HNS3_RX_LOW_BYTE_RATE 10000 2997 #define HNS3_RX_MID_BYTE_RATE 20000 2998 #define HNS3_RX_ULTRA_PACKET_RATE 40 2999 3000 enum hns3_flow_level_range new_flow_level; 3001 struct hns3_enet_tqp_vector *tqp_vector; 3002 int packets_per_msecs, bytes_per_msecs; 3003 u32 time_passed_ms; 3004 3005 tqp_vector = ring_group->ring->tqp_vector; 3006 time_passed_ms = 3007 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3008 if (!time_passed_ms) 3009 return false; 3010 3011 do_div(ring_group->total_packets, time_passed_ms); 3012 packets_per_msecs = ring_group->total_packets; 3013 3014 do_div(ring_group->total_bytes, time_passed_ms); 3015 bytes_per_msecs = ring_group->total_bytes; 3016 3017 new_flow_level = ring_group->coal.flow_level; 3018 3019 /* Simple throttlerate management 3020 * 0-10MB/s lower (50000 ints/s) 3021 * 10-20MB/s middle (20000 ints/s) 3022 * 20-1249MB/s high (18000 ints/s) 3023 * > 40000pps ultra (8000 ints/s) 3024 */ 3025 switch (new_flow_level) { 3026 case HNS3_FLOW_LOW: 3027 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3028 new_flow_level = HNS3_FLOW_MID; 3029 break; 3030 case HNS3_FLOW_MID: 3031 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3032 new_flow_level = HNS3_FLOW_HIGH; 3033 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3034 new_flow_level = HNS3_FLOW_LOW; 3035 break; 3036 case HNS3_FLOW_HIGH: 3037 case HNS3_FLOW_ULTRA: 3038 default: 3039 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3040 new_flow_level = HNS3_FLOW_MID; 3041 break; 3042 } 3043 3044 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3045 &tqp_vector->rx_group == ring_group) 3046 new_flow_level = HNS3_FLOW_ULTRA; 3047 3048 ring_group->total_bytes = 0; 3049 ring_group->total_packets = 0; 3050 ring_group->coal.flow_level = new_flow_level; 3051 3052 return true; 3053 } 3054 3055 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3056 { 3057 struct hns3_enet_tqp_vector *tqp_vector; 3058 u16 new_int_gl; 3059 3060 if (!ring_group->ring) 3061 return false; 3062 3063 tqp_vector = ring_group->ring->tqp_vector; 3064 if (!tqp_vector->last_jiffies) 3065 return false; 3066 3067 if (ring_group->total_packets == 0) { 3068 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3069 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3070 return true; 3071 } 3072 3073 if (!hns3_get_new_flow_lvl(ring_group)) 3074 return false; 3075 3076 new_int_gl = ring_group->coal.int_gl; 3077 switch (ring_group->coal.flow_level) { 3078 case HNS3_FLOW_LOW: 3079 new_int_gl = HNS3_INT_GL_50K; 3080 break; 3081 case HNS3_FLOW_MID: 3082 new_int_gl = HNS3_INT_GL_20K; 3083 break; 3084 case HNS3_FLOW_HIGH: 3085 new_int_gl = HNS3_INT_GL_18K; 3086 break; 3087 case HNS3_FLOW_ULTRA: 3088 new_int_gl = HNS3_INT_GL_8K; 3089 break; 3090 default: 3091 break; 3092 } 3093 3094 if (new_int_gl != ring_group->coal.int_gl) { 3095 ring_group->coal.int_gl = new_int_gl; 3096 return true; 3097 } 3098 return false; 3099 } 3100 3101 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3102 { 3103 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3104 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3105 bool rx_update, tx_update; 3106 3107 /* update param every 1000ms */ 3108 if (time_before(jiffies, 3109 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3110 return; 3111 3112 if (rx_group->coal.gl_adapt_enable) { 3113 rx_update = hns3_get_new_int_gl(rx_group); 3114 if (rx_update) 3115 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3116 rx_group->coal.int_gl); 3117 } 3118 3119 if (tx_group->coal.gl_adapt_enable) { 3120 tx_update = hns3_get_new_int_gl(tx_group); 3121 if (tx_update) 3122 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3123 tx_group->coal.int_gl); 3124 } 3125 3126 tqp_vector->last_jiffies = jiffies; 3127 } 3128 3129 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3130 { 3131 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3132 struct hns3_enet_ring *ring; 3133 int rx_pkt_total = 0; 3134 3135 struct hns3_enet_tqp_vector *tqp_vector = 3136 container_of(napi, struct hns3_enet_tqp_vector, napi); 3137 bool clean_complete = true; 3138 int rx_budget = budget; 3139 3140 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3141 napi_complete(napi); 3142 return 0; 3143 } 3144 3145 /* Since the actual Tx work is minimal, we can give the Tx a larger 3146 * budget and be more aggressive about cleaning up the Tx descriptors. 3147 */ 3148 hns3_for_each_ring(ring, tqp_vector->tx_group) 3149 hns3_clean_tx_ring(ring); 3150 3151 /* make sure rx ring budget not smaller than 1 */ 3152 if (tqp_vector->num_tqps > 1) 3153 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3154 3155 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3156 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3157 hns3_rx_skb); 3158 3159 if (rx_cleaned >= rx_budget) 3160 clean_complete = false; 3161 3162 rx_pkt_total += rx_cleaned; 3163 } 3164 3165 tqp_vector->rx_group.total_packets += rx_pkt_total; 3166 3167 if (!clean_complete) 3168 return budget; 3169 3170 if (napi_complete(napi) && 3171 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3172 hns3_update_new_int_gl(tqp_vector); 3173 hns3_mask_vector_irq(tqp_vector, 1); 3174 } 3175 3176 return rx_pkt_total; 3177 } 3178 3179 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3180 struct hnae3_ring_chain_node *head) 3181 { 3182 struct pci_dev *pdev = tqp_vector->handle->pdev; 3183 struct hnae3_ring_chain_node *cur_chain = head; 3184 struct hnae3_ring_chain_node *chain; 3185 struct hns3_enet_ring *tx_ring; 3186 struct hns3_enet_ring *rx_ring; 3187 3188 tx_ring = tqp_vector->tx_group.ring; 3189 if (tx_ring) { 3190 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3191 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3192 HNAE3_RING_TYPE_TX); 3193 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3194 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3195 3196 cur_chain->next = NULL; 3197 3198 while (tx_ring->next) { 3199 tx_ring = tx_ring->next; 3200 3201 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3202 GFP_KERNEL); 3203 if (!chain) 3204 goto err_free_chain; 3205 3206 cur_chain->next = chain; 3207 chain->tqp_index = tx_ring->tqp->tqp_index; 3208 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3209 HNAE3_RING_TYPE_TX); 3210 hnae3_set_field(chain->int_gl_idx, 3211 HNAE3_RING_GL_IDX_M, 3212 HNAE3_RING_GL_IDX_S, 3213 HNAE3_RING_GL_TX); 3214 3215 cur_chain = chain; 3216 } 3217 } 3218 3219 rx_ring = tqp_vector->rx_group.ring; 3220 if (!tx_ring && rx_ring) { 3221 cur_chain->next = NULL; 3222 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3223 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3224 HNAE3_RING_TYPE_RX); 3225 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3226 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3227 3228 rx_ring = rx_ring->next; 3229 } 3230 3231 while (rx_ring) { 3232 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3233 if (!chain) 3234 goto err_free_chain; 3235 3236 cur_chain->next = chain; 3237 chain->tqp_index = rx_ring->tqp->tqp_index; 3238 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3239 HNAE3_RING_TYPE_RX); 3240 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3241 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3242 3243 cur_chain = chain; 3244 3245 rx_ring = rx_ring->next; 3246 } 3247 3248 return 0; 3249 3250 err_free_chain: 3251 cur_chain = head->next; 3252 while (cur_chain) { 3253 chain = cur_chain->next; 3254 devm_kfree(&pdev->dev, cur_chain); 3255 cur_chain = chain; 3256 } 3257 head->next = NULL; 3258 3259 return -ENOMEM; 3260 } 3261 3262 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3263 struct hnae3_ring_chain_node *head) 3264 { 3265 struct pci_dev *pdev = tqp_vector->handle->pdev; 3266 struct hnae3_ring_chain_node *chain_tmp, *chain; 3267 3268 chain = head->next; 3269 3270 while (chain) { 3271 chain_tmp = chain->next; 3272 devm_kfree(&pdev->dev, chain); 3273 chain = chain_tmp; 3274 } 3275 } 3276 3277 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3278 struct hns3_enet_ring *ring) 3279 { 3280 ring->next = group->ring; 3281 group->ring = ring; 3282 3283 group->count++; 3284 } 3285 3286 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3287 { 3288 struct pci_dev *pdev = priv->ae_handle->pdev; 3289 struct hns3_enet_tqp_vector *tqp_vector; 3290 int num_vectors = priv->vector_num; 3291 int numa_node; 3292 int vector_i; 3293 3294 numa_node = dev_to_node(&pdev->dev); 3295 3296 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3297 tqp_vector = &priv->tqp_vector[vector_i]; 3298 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3299 &tqp_vector->affinity_mask); 3300 } 3301 } 3302 3303 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3304 { 3305 struct hnae3_ring_chain_node vector_ring_chain; 3306 struct hnae3_handle *h = priv->ae_handle; 3307 struct hns3_enet_tqp_vector *tqp_vector; 3308 int ret = 0; 3309 int i; 3310 3311 hns3_nic_set_cpumask(priv); 3312 3313 for (i = 0; i < priv->vector_num; i++) { 3314 tqp_vector = &priv->tqp_vector[i]; 3315 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3316 tqp_vector->num_tqps = 0; 3317 } 3318 3319 for (i = 0; i < h->kinfo.num_tqps; i++) { 3320 u16 vector_i = i % priv->vector_num; 3321 u16 tqp_num = h->kinfo.num_tqps; 3322 3323 tqp_vector = &priv->tqp_vector[vector_i]; 3324 3325 hns3_add_ring_to_group(&tqp_vector->tx_group, 3326 priv->ring_data[i].ring); 3327 3328 hns3_add_ring_to_group(&tqp_vector->rx_group, 3329 priv->ring_data[i + tqp_num].ring); 3330 3331 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3332 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3333 tqp_vector->num_tqps++; 3334 } 3335 3336 for (i = 0; i < priv->vector_num; i++) { 3337 tqp_vector = &priv->tqp_vector[i]; 3338 3339 tqp_vector->rx_group.total_bytes = 0; 3340 tqp_vector->rx_group.total_packets = 0; 3341 tqp_vector->tx_group.total_bytes = 0; 3342 tqp_vector->tx_group.total_packets = 0; 3343 tqp_vector->handle = h; 3344 3345 ret = hns3_get_vector_ring_chain(tqp_vector, 3346 &vector_ring_chain); 3347 if (ret) 3348 goto map_ring_fail; 3349 3350 ret = h->ae_algo->ops->map_ring_to_vector(h, 3351 tqp_vector->vector_irq, &vector_ring_chain); 3352 3353 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3354 3355 if (ret) 3356 goto map_ring_fail; 3357 3358 netif_napi_add(priv->netdev, &tqp_vector->napi, 3359 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3360 } 3361 3362 return 0; 3363 3364 map_ring_fail: 3365 while (i--) 3366 netif_napi_del(&priv->tqp_vector[i].napi); 3367 3368 return ret; 3369 } 3370 3371 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3372 { 3373 #define HNS3_VECTOR_PF_MAX_NUM 64 3374 3375 struct hnae3_handle *h = priv->ae_handle; 3376 struct hns3_enet_tqp_vector *tqp_vector; 3377 struct hnae3_vector_info *vector; 3378 struct pci_dev *pdev = h->pdev; 3379 u16 tqp_num = h->kinfo.num_tqps; 3380 u16 vector_num; 3381 int ret = 0; 3382 u16 i; 3383 3384 /* RSS size, cpu online and vector_num should be the same */ 3385 /* Should consider 2p/4p later */ 3386 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3387 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3388 3389 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3390 GFP_KERNEL); 3391 if (!vector) 3392 return -ENOMEM; 3393 3394 /* save the actual available vector number */ 3395 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3396 3397 priv->vector_num = vector_num; 3398 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3399 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3400 GFP_KERNEL); 3401 if (!priv->tqp_vector) { 3402 ret = -ENOMEM; 3403 goto out; 3404 } 3405 3406 for (i = 0; i < priv->vector_num; i++) { 3407 tqp_vector = &priv->tqp_vector[i]; 3408 tqp_vector->idx = i; 3409 tqp_vector->mask_addr = vector[i].io_addr; 3410 tqp_vector->vector_irq = vector[i].vector; 3411 hns3_vector_gl_rl_init(tqp_vector, priv); 3412 } 3413 3414 out: 3415 devm_kfree(&pdev->dev, vector); 3416 return ret; 3417 } 3418 3419 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3420 { 3421 group->ring = NULL; 3422 group->count = 0; 3423 } 3424 3425 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3426 { 3427 struct hnae3_ring_chain_node vector_ring_chain; 3428 struct hnae3_handle *h = priv->ae_handle; 3429 struct hns3_enet_tqp_vector *tqp_vector; 3430 int i; 3431 3432 for (i = 0; i < priv->vector_num; i++) { 3433 tqp_vector = &priv->tqp_vector[i]; 3434 3435 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3436 continue; 3437 3438 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3439 3440 h->ae_algo->ops->unmap_ring_from_vector(h, 3441 tqp_vector->vector_irq, &vector_ring_chain); 3442 3443 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3444 3445 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3446 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3447 free_irq(tqp_vector->vector_irq, tqp_vector); 3448 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3449 } 3450 3451 hns3_clear_ring_group(&tqp_vector->rx_group); 3452 hns3_clear_ring_group(&tqp_vector->tx_group); 3453 netif_napi_del(&priv->tqp_vector[i].napi); 3454 } 3455 } 3456 3457 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3458 { 3459 struct hnae3_handle *h = priv->ae_handle; 3460 struct pci_dev *pdev = h->pdev; 3461 int i, ret; 3462 3463 for (i = 0; i < priv->vector_num; i++) { 3464 struct hns3_enet_tqp_vector *tqp_vector; 3465 3466 tqp_vector = &priv->tqp_vector[i]; 3467 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3468 if (ret) 3469 return ret; 3470 } 3471 3472 devm_kfree(&pdev->dev, priv->tqp_vector); 3473 return 0; 3474 } 3475 3476 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3477 unsigned int ring_type) 3478 { 3479 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3480 int queue_num = priv->ae_handle->kinfo.num_tqps; 3481 struct pci_dev *pdev = priv->ae_handle->pdev; 3482 struct hns3_enet_ring *ring; 3483 int desc_num; 3484 3485 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3486 if (!ring) 3487 return -ENOMEM; 3488 3489 if (ring_type == HNAE3_RING_TYPE_TX) { 3490 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3491 ring_data[q->tqp_index].ring = ring; 3492 ring_data[q->tqp_index].queue_index = q->tqp_index; 3493 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3494 } else { 3495 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3496 ring_data[q->tqp_index + queue_num].ring = ring; 3497 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3498 ring->io_base = q->io_base; 3499 } 3500 3501 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3502 3503 ring->tqp = q; 3504 ring->desc = NULL; 3505 ring->desc_cb = NULL; 3506 ring->dev = priv->dev; 3507 ring->desc_dma_addr = 0; 3508 ring->buf_size = q->buf_size; 3509 ring->desc_num = desc_num; 3510 ring->next_to_use = 0; 3511 ring->next_to_clean = 0; 3512 3513 return 0; 3514 } 3515 3516 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3517 struct hns3_nic_priv *priv) 3518 { 3519 int ret; 3520 3521 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3522 if (ret) 3523 return ret; 3524 3525 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3526 if (ret) { 3527 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3528 return ret; 3529 } 3530 3531 return 0; 3532 } 3533 3534 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3535 { 3536 struct hnae3_handle *h = priv->ae_handle; 3537 struct pci_dev *pdev = h->pdev; 3538 int i, ret; 3539 3540 priv->ring_data = devm_kzalloc(&pdev->dev, 3541 array3_size(h->kinfo.num_tqps, 3542 sizeof(*priv->ring_data), 3543 2), 3544 GFP_KERNEL); 3545 if (!priv->ring_data) 3546 return -ENOMEM; 3547 3548 for (i = 0; i < h->kinfo.num_tqps; i++) { 3549 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3550 if (ret) 3551 goto err; 3552 } 3553 3554 return 0; 3555 err: 3556 while (i--) { 3557 devm_kfree(priv->dev, priv->ring_data[i].ring); 3558 devm_kfree(priv->dev, 3559 priv->ring_data[i + h->kinfo.num_tqps].ring); 3560 } 3561 3562 devm_kfree(&pdev->dev, priv->ring_data); 3563 priv->ring_data = NULL; 3564 return ret; 3565 } 3566 3567 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3568 { 3569 struct hnae3_handle *h = priv->ae_handle; 3570 int i; 3571 3572 if (!priv->ring_data) 3573 return; 3574 3575 for (i = 0; i < h->kinfo.num_tqps; i++) { 3576 devm_kfree(priv->dev, priv->ring_data[i].ring); 3577 devm_kfree(priv->dev, 3578 priv->ring_data[i + h->kinfo.num_tqps].ring); 3579 } 3580 devm_kfree(priv->dev, priv->ring_data); 3581 priv->ring_data = NULL; 3582 } 3583 3584 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3585 { 3586 int ret; 3587 3588 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3589 return -EINVAL; 3590 3591 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3592 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3593 if (!ring->desc_cb) { 3594 ret = -ENOMEM; 3595 goto out; 3596 } 3597 3598 ret = hns3_alloc_desc(ring); 3599 if (ret) 3600 goto out_with_desc_cb; 3601 3602 if (!HNAE3_IS_TX_RING(ring)) { 3603 ret = hns3_alloc_ring_buffers(ring); 3604 if (ret) 3605 goto out_with_desc; 3606 } 3607 3608 return 0; 3609 3610 out_with_desc: 3611 hns3_free_desc(ring); 3612 out_with_desc_cb: 3613 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3614 ring->desc_cb = NULL; 3615 out: 3616 return ret; 3617 } 3618 3619 void hns3_fini_ring(struct hns3_enet_ring *ring) 3620 { 3621 hns3_free_desc(ring); 3622 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3623 ring->desc_cb = NULL; 3624 ring->next_to_clean = 0; 3625 ring->next_to_use = 0; 3626 ring->pending_buf = 0; 3627 if (ring->skb) { 3628 dev_kfree_skb_any(ring->skb); 3629 ring->skb = NULL; 3630 } 3631 } 3632 3633 static int hns3_buf_size2type(u32 buf_size) 3634 { 3635 int bd_size_type; 3636 3637 switch (buf_size) { 3638 case 512: 3639 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3640 break; 3641 case 1024: 3642 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3643 break; 3644 case 2048: 3645 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3646 break; 3647 case 4096: 3648 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3649 break; 3650 default: 3651 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3652 } 3653 3654 return bd_size_type; 3655 } 3656 3657 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3658 { 3659 dma_addr_t dma = ring->desc_dma_addr; 3660 struct hnae3_queue *q = ring->tqp; 3661 3662 if (!HNAE3_IS_TX_RING(ring)) { 3663 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3664 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3665 (u32)((dma >> 31) >> 1)); 3666 3667 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3668 hns3_buf_size2type(ring->buf_size)); 3669 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3670 ring->desc_num / 8 - 1); 3671 3672 } else { 3673 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3674 (u32)dma); 3675 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3676 (u32)((dma >> 31) >> 1)); 3677 3678 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3679 ring->desc_num / 8 - 1); 3680 } 3681 } 3682 3683 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3684 { 3685 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3686 int i; 3687 3688 for (i = 0; i < HNAE3_MAX_TC; i++) { 3689 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3690 int j; 3691 3692 if (!tc_info->enable) 3693 continue; 3694 3695 for (j = 0; j < tc_info->tqp_count; j++) { 3696 struct hnae3_queue *q; 3697 3698 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3699 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3700 tc_info->tc); 3701 } 3702 } 3703 } 3704 3705 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3706 { 3707 struct hnae3_handle *h = priv->ae_handle; 3708 int ring_num = h->kinfo.num_tqps * 2; 3709 int i, j; 3710 int ret; 3711 3712 for (i = 0; i < ring_num; i++) { 3713 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3714 if (ret) { 3715 dev_err(priv->dev, 3716 "Alloc ring memory fail! ret=%d\n", ret); 3717 goto out_when_alloc_ring_memory; 3718 } 3719 3720 u64_stats_init(&priv->ring_data[i].ring->syncp); 3721 } 3722 3723 return 0; 3724 3725 out_when_alloc_ring_memory: 3726 for (j = i - 1; j >= 0; j--) 3727 hns3_fini_ring(priv->ring_data[j].ring); 3728 3729 return -ENOMEM; 3730 } 3731 3732 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3733 { 3734 struct hnae3_handle *h = priv->ae_handle; 3735 int i; 3736 3737 for (i = 0; i < h->kinfo.num_tqps; i++) { 3738 hns3_fini_ring(priv->ring_data[i].ring); 3739 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3740 } 3741 return 0; 3742 } 3743 3744 /* Set mac addr if it is configured. or leave it to the AE driver */ 3745 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3746 { 3747 struct hns3_nic_priv *priv = netdev_priv(netdev); 3748 struct hnae3_handle *h = priv->ae_handle; 3749 u8 mac_addr_temp[ETH_ALEN]; 3750 int ret = 0; 3751 3752 if (h->ae_algo->ops->get_mac_addr && init) { 3753 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3754 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3755 } 3756 3757 /* Check if the MAC address is valid, if not get a random one */ 3758 if (!is_valid_ether_addr(netdev->dev_addr)) { 3759 eth_hw_addr_random(netdev); 3760 dev_warn(priv->dev, "using random MAC address %pM\n", 3761 netdev->dev_addr); 3762 } 3763 3764 if (h->ae_algo->ops->set_mac_addr) 3765 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3766 3767 return ret; 3768 } 3769 3770 static int hns3_init_phy(struct net_device *netdev) 3771 { 3772 struct hnae3_handle *h = hns3_get_handle(netdev); 3773 int ret = 0; 3774 3775 if (h->ae_algo->ops->mac_connect_phy) 3776 ret = h->ae_algo->ops->mac_connect_phy(h); 3777 3778 return ret; 3779 } 3780 3781 static void hns3_uninit_phy(struct net_device *netdev) 3782 { 3783 struct hnae3_handle *h = hns3_get_handle(netdev); 3784 3785 if (h->ae_algo->ops->mac_disconnect_phy) 3786 h->ae_algo->ops->mac_disconnect_phy(h); 3787 } 3788 3789 static int hns3_restore_fd_rules(struct net_device *netdev) 3790 { 3791 struct hnae3_handle *h = hns3_get_handle(netdev); 3792 int ret = 0; 3793 3794 if (h->ae_algo->ops->restore_fd_rules) 3795 ret = h->ae_algo->ops->restore_fd_rules(h); 3796 3797 return ret; 3798 } 3799 3800 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3801 { 3802 struct hnae3_handle *h = hns3_get_handle(netdev); 3803 3804 if (h->ae_algo->ops->del_all_fd_entries) 3805 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3806 } 3807 3808 static int hns3_client_start(struct hnae3_handle *handle) 3809 { 3810 if (!handle->ae_algo->ops->client_start) 3811 return 0; 3812 3813 return handle->ae_algo->ops->client_start(handle); 3814 } 3815 3816 static void hns3_client_stop(struct hnae3_handle *handle) 3817 { 3818 if (!handle->ae_algo->ops->client_stop) 3819 return; 3820 3821 handle->ae_algo->ops->client_stop(handle); 3822 } 3823 3824 static void hns3_info_show(struct hns3_nic_priv *priv) 3825 { 3826 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3827 3828 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3829 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps); 3830 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size); 3831 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size); 3832 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len); 3833 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc); 3834 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc); 3835 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc); 3836 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu); 3837 } 3838 3839 static int hns3_client_init(struct hnae3_handle *handle) 3840 { 3841 struct pci_dev *pdev = handle->pdev; 3842 u16 alloc_tqps, max_rss_size; 3843 struct hns3_nic_priv *priv; 3844 struct net_device *netdev; 3845 int ret; 3846 3847 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3848 &max_rss_size); 3849 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3850 if (!netdev) 3851 return -ENOMEM; 3852 3853 priv = netdev_priv(netdev); 3854 priv->dev = &pdev->dev; 3855 priv->netdev = netdev; 3856 priv->ae_handle = handle; 3857 priv->tx_timeout_count = 0; 3858 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3859 3860 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 3861 3862 handle->kinfo.netdev = netdev; 3863 handle->priv = (void *)priv; 3864 3865 hns3_init_mac_addr(netdev, true); 3866 3867 hns3_set_default_feature(netdev); 3868 3869 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3870 netdev->priv_flags |= IFF_UNICAST_FLT; 3871 netdev->netdev_ops = &hns3_nic_netdev_ops; 3872 SET_NETDEV_DEV(netdev, &pdev->dev); 3873 hns3_ethtool_set_ops(netdev); 3874 3875 /* Carrier off reporting is important to ethtool even BEFORE open */ 3876 netif_carrier_off(netdev); 3877 3878 ret = hns3_get_ring_config(priv); 3879 if (ret) { 3880 ret = -ENOMEM; 3881 goto out_get_ring_cfg; 3882 } 3883 3884 ret = hns3_nic_alloc_vector_data(priv); 3885 if (ret) { 3886 ret = -ENOMEM; 3887 goto out_alloc_vector_data; 3888 } 3889 3890 ret = hns3_nic_init_vector_data(priv); 3891 if (ret) { 3892 ret = -ENOMEM; 3893 goto out_init_vector_data; 3894 } 3895 3896 ret = hns3_init_all_ring(priv); 3897 if (ret) { 3898 ret = -ENOMEM; 3899 goto out_init_ring_data; 3900 } 3901 3902 ret = hns3_init_phy(netdev); 3903 if (ret) 3904 goto out_init_phy; 3905 3906 ret = register_netdev(netdev); 3907 if (ret) { 3908 dev_err(priv->dev, "probe register netdev fail!\n"); 3909 goto out_reg_netdev_fail; 3910 } 3911 3912 ret = hns3_client_start(handle); 3913 if (ret) { 3914 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3915 goto out_client_start; 3916 } 3917 3918 hns3_dcbnl_setup(handle); 3919 3920 hns3_dbg_init(handle); 3921 3922 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3923 netdev->max_mtu = HNS3_MAX_MTU; 3924 3925 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3926 3927 if (netif_msg_drv(handle)) 3928 hns3_info_show(priv); 3929 3930 return ret; 3931 3932 out_client_start: 3933 unregister_netdev(netdev); 3934 out_reg_netdev_fail: 3935 hns3_uninit_phy(netdev); 3936 out_init_phy: 3937 hns3_uninit_all_ring(priv); 3938 out_init_ring_data: 3939 hns3_nic_uninit_vector_data(priv); 3940 out_init_vector_data: 3941 hns3_nic_dealloc_vector_data(priv); 3942 out_alloc_vector_data: 3943 priv->ring_data = NULL; 3944 out_get_ring_cfg: 3945 priv->ae_handle = NULL; 3946 free_netdev(netdev); 3947 return ret; 3948 } 3949 3950 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3951 { 3952 struct net_device *netdev = handle->kinfo.netdev; 3953 struct hns3_nic_priv *priv = netdev_priv(netdev); 3954 int ret; 3955 3956 hns3_remove_hw_addr(netdev); 3957 3958 if (netdev->reg_state != NETREG_UNINITIALIZED) 3959 unregister_netdev(netdev); 3960 3961 hns3_client_stop(handle); 3962 3963 hns3_uninit_phy(netdev); 3964 3965 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3966 netdev_warn(netdev, "already uninitialized\n"); 3967 goto out_netdev_free; 3968 } 3969 3970 hns3_del_all_fd_rules(netdev, true); 3971 3972 hns3_clear_all_ring(handle, true); 3973 3974 hns3_nic_uninit_vector_data(priv); 3975 3976 ret = hns3_nic_dealloc_vector_data(priv); 3977 if (ret) 3978 netdev_err(netdev, "dealloc vector error\n"); 3979 3980 ret = hns3_uninit_all_ring(priv); 3981 if (ret) 3982 netdev_err(netdev, "uninit ring error\n"); 3983 3984 hns3_put_ring_config(priv); 3985 3986 hns3_dbg_uninit(handle); 3987 3988 out_netdev_free: 3989 free_netdev(netdev); 3990 } 3991 3992 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3993 { 3994 struct net_device *netdev = handle->kinfo.netdev; 3995 3996 if (!netdev) 3997 return; 3998 3999 if (linkup) { 4000 netif_carrier_on(netdev); 4001 netif_tx_wake_all_queues(netdev); 4002 if (netif_msg_link(handle)) 4003 netdev_info(netdev, "link up\n"); 4004 } else { 4005 netif_carrier_off(netdev); 4006 netif_tx_stop_all_queues(netdev); 4007 if (netif_msg_link(handle)) 4008 netdev_info(netdev, "link down\n"); 4009 } 4010 } 4011 4012 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4013 { 4014 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4015 struct net_device *ndev = kinfo->netdev; 4016 4017 if (tc > HNAE3_MAX_TC) 4018 return -EINVAL; 4019 4020 if (!ndev) 4021 return -ENODEV; 4022 4023 return hns3_nic_set_real_num_queue(ndev); 4024 } 4025 4026 static int hns3_recover_hw_addr(struct net_device *ndev) 4027 { 4028 struct netdev_hw_addr_list *list; 4029 struct netdev_hw_addr *ha, *tmp; 4030 int ret = 0; 4031 4032 netif_addr_lock_bh(ndev); 4033 /* go through and sync uc_addr entries to the device */ 4034 list = &ndev->uc; 4035 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4036 ret = hns3_nic_uc_sync(ndev, ha->addr); 4037 if (ret) 4038 goto out; 4039 } 4040 4041 /* go through and sync mc_addr entries to the device */ 4042 list = &ndev->mc; 4043 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4044 ret = hns3_nic_mc_sync(ndev, ha->addr); 4045 if (ret) 4046 goto out; 4047 } 4048 4049 out: 4050 netif_addr_unlock_bh(ndev); 4051 return ret; 4052 } 4053 4054 static void hns3_remove_hw_addr(struct net_device *netdev) 4055 { 4056 struct netdev_hw_addr_list *list; 4057 struct netdev_hw_addr *ha, *tmp; 4058 4059 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 4060 4061 netif_addr_lock_bh(netdev); 4062 /* go through and unsync uc_addr entries to the device */ 4063 list = &netdev->uc; 4064 list_for_each_entry_safe(ha, tmp, &list->list, list) 4065 hns3_nic_uc_unsync(netdev, ha->addr); 4066 4067 /* go through and unsync mc_addr entries to the device */ 4068 list = &netdev->mc; 4069 list_for_each_entry_safe(ha, tmp, &list->list, list) 4070 if (ha->refcount > 1) 4071 hns3_nic_mc_unsync(netdev, ha->addr); 4072 4073 netif_addr_unlock_bh(netdev); 4074 } 4075 4076 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4077 { 4078 while (ring->next_to_clean != ring->next_to_use) { 4079 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4080 hns3_free_buffer_detach(ring, ring->next_to_clean); 4081 ring_ptr_move_fw(ring, next_to_clean); 4082 } 4083 } 4084 4085 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4086 { 4087 struct hns3_desc_cb res_cbs; 4088 int ret; 4089 4090 while (ring->next_to_use != ring->next_to_clean) { 4091 /* When a buffer is not reused, it's memory has been 4092 * freed in hns3_handle_rx_bd or will be freed by 4093 * stack, so we need to replace the buffer here. 4094 */ 4095 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4096 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4097 if (ret) { 4098 u64_stats_update_begin(&ring->syncp); 4099 ring->stats.sw_err_cnt++; 4100 u64_stats_update_end(&ring->syncp); 4101 /* if alloc new buffer fail, exit directly 4102 * and reclear in up flow. 4103 */ 4104 netdev_warn(ring->tqp->handle->kinfo.netdev, 4105 "reserve buffer map failed, ret = %d\n", 4106 ret); 4107 return ret; 4108 } 4109 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4110 } 4111 ring_ptr_move_fw(ring, next_to_use); 4112 } 4113 4114 /* Free the pending skb in rx ring */ 4115 if (ring->skb) { 4116 dev_kfree_skb_any(ring->skb); 4117 ring->skb = NULL; 4118 ring->pending_buf = 0; 4119 } 4120 4121 return 0; 4122 } 4123 4124 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4125 { 4126 while (ring->next_to_use != ring->next_to_clean) { 4127 /* When a buffer is not reused, it's memory has been 4128 * freed in hns3_handle_rx_bd or will be freed by 4129 * stack, so only need to unmap the buffer here. 4130 */ 4131 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4132 hns3_unmap_buffer(ring, 4133 &ring->desc_cb[ring->next_to_use]); 4134 ring->desc_cb[ring->next_to_use].dma = 0; 4135 } 4136 4137 ring_ptr_move_fw(ring, next_to_use); 4138 } 4139 } 4140 4141 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4142 { 4143 struct net_device *ndev = h->kinfo.netdev; 4144 struct hns3_nic_priv *priv = netdev_priv(ndev); 4145 u32 i; 4146 4147 for (i = 0; i < h->kinfo.num_tqps; i++) { 4148 struct hns3_enet_ring *ring; 4149 4150 ring = priv->ring_data[i].ring; 4151 hns3_clear_tx_ring(ring); 4152 4153 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4154 /* Continue to clear other rings even if clearing some 4155 * rings failed. 4156 */ 4157 if (force) 4158 hns3_force_clear_rx_ring(ring); 4159 else 4160 hns3_clear_rx_ring(ring); 4161 } 4162 } 4163 4164 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4165 { 4166 struct net_device *ndev = h->kinfo.netdev; 4167 struct hns3_nic_priv *priv = netdev_priv(ndev); 4168 struct hns3_enet_ring *rx_ring; 4169 int i, j; 4170 int ret; 4171 4172 for (i = 0; i < h->kinfo.num_tqps; i++) { 4173 ret = h->ae_algo->ops->reset_queue(h, i); 4174 if (ret) 4175 return ret; 4176 4177 hns3_init_ring_hw(priv->ring_data[i].ring); 4178 4179 /* We need to clear tx ring here because self test will 4180 * use the ring and will not run down before up 4181 */ 4182 hns3_clear_tx_ring(priv->ring_data[i].ring); 4183 priv->ring_data[i].ring->next_to_clean = 0; 4184 priv->ring_data[i].ring->next_to_use = 0; 4185 4186 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4187 hns3_init_ring_hw(rx_ring); 4188 ret = hns3_clear_rx_ring(rx_ring); 4189 if (ret) 4190 return ret; 4191 4192 /* We can not know the hardware head and tail when this 4193 * function is called in reset flow, so we reuse all desc. 4194 */ 4195 for (j = 0; j < rx_ring->desc_num; j++) 4196 hns3_reuse_buffer(rx_ring, j); 4197 4198 rx_ring->next_to_clean = 0; 4199 rx_ring->next_to_use = 0; 4200 } 4201 4202 hns3_init_tx_ring_tc(priv); 4203 4204 return 0; 4205 } 4206 4207 static void hns3_store_coal(struct hns3_nic_priv *priv) 4208 { 4209 /* ethtool only support setting and querying one coal 4210 * configuration for now, so save the vector 0' coal 4211 * configuration here in order to restore it. 4212 */ 4213 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4214 sizeof(struct hns3_enet_coalesce)); 4215 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4216 sizeof(struct hns3_enet_coalesce)); 4217 } 4218 4219 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4220 { 4221 u16 vector_num = priv->vector_num; 4222 int i; 4223 4224 for (i = 0; i < vector_num; i++) { 4225 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4226 sizeof(struct hns3_enet_coalesce)); 4227 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4228 sizeof(struct hns3_enet_coalesce)); 4229 } 4230 } 4231 4232 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4233 { 4234 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4235 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4236 struct net_device *ndev = kinfo->netdev; 4237 struct hns3_nic_priv *priv = netdev_priv(ndev); 4238 4239 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4240 return 0; 4241 4242 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4243 * from table space. Hence, for function reset software intervention is 4244 * required to delete the entries 4245 */ 4246 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4247 hns3_remove_hw_addr(ndev); 4248 hns3_del_all_fd_rules(ndev, false); 4249 } 4250 4251 if (!netif_running(ndev)) 4252 return 0; 4253 4254 return hns3_nic_net_stop(ndev); 4255 } 4256 4257 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4258 { 4259 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4260 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4261 int ret = 0; 4262 4263 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4264 4265 if (netif_running(kinfo->netdev)) { 4266 ret = hns3_nic_net_open(kinfo->netdev); 4267 if (ret) { 4268 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4269 netdev_err(kinfo->netdev, 4270 "net up fail, ret=%d!\n", ret); 4271 return ret; 4272 } 4273 } 4274 4275 return ret; 4276 } 4277 4278 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4279 { 4280 struct net_device *netdev = handle->kinfo.netdev; 4281 struct hns3_nic_priv *priv = netdev_priv(netdev); 4282 int ret; 4283 4284 /* Carrier off reporting is important to ethtool even BEFORE open */ 4285 netif_carrier_off(netdev); 4286 4287 ret = hns3_get_ring_config(priv); 4288 if (ret) 4289 return ret; 4290 4291 ret = hns3_nic_alloc_vector_data(priv); 4292 if (ret) 4293 goto err_put_ring; 4294 4295 hns3_restore_coal(priv); 4296 4297 ret = hns3_nic_init_vector_data(priv); 4298 if (ret) 4299 goto err_dealloc_vector; 4300 4301 ret = hns3_init_all_ring(priv); 4302 if (ret) 4303 goto err_uninit_vector; 4304 4305 ret = hns3_client_start(handle); 4306 if (ret) { 4307 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4308 goto err_uninit_ring; 4309 } 4310 4311 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4312 4313 return ret; 4314 4315 err_uninit_ring: 4316 hns3_uninit_all_ring(priv); 4317 err_uninit_vector: 4318 hns3_nic_uninit_vector_data(priv); 4319 err_dealloc_vector: 4320 hns3_nic_dealloc_vector_data(priv); 4321 err_put_ring: 4322 hns3_put_ring_config(priv); 4323 4324 return ret; 4325 } 4326 4327 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4328 { 4329 struct net_device *netdev = handle->kinfo.netdev; 4330 bool vlan_filter_enable; 4331 int ret; 4332 4333 ret = hns3_init_mac_addr(netdev, false); 4334 if (ret) 4335 return ret; 4336 4337 ret = hns3_recover_hw_addr(netdev); 4338 if (ret) 4339 return ret; 4340 4341 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4342 if (ret) 4343 return ret; 4344 4345 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4346 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4347 4348 if (handle->ae_algo->ops->restore_vlan_table) 4349 handle->ae_algo->ops->restore_vlan_table(handle); 4350 4351 return hns3_restore_fd_rules(netdev); 4352 } 4353 4354 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4355 { 4356 struct net_device *netdev = handle->kinfo.netdev; 4357 struct hns3_nic_priv *priv = netdev_priv(netdev); 4358 int ret; 4359 4360 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4361 netdev_warn(netdev, "already uninitialized\n"); 4362 return 0; 4363 } 4364 4365 hns3_clear_all_ring(handle, true); 4366 hns3_reset_tx_queue(priv->ae_handle); 4367 4368 hns3_nic_uninit_vector_data(priv); 4369 4370 hns3_store_coal(priv); 4371 4372 ret = hns3_nic_dealloc_vector_data(priv); 4373 if (ret) 4374 netdev_err(netdev, "dealloc vector error\n"); 4375 4376 ret = hns3_uninit_all_ring(priv); 4377 if (ret) 4378 netdev_err(netdev, "uninit ring error\n"); 4379 4380 hns3_put_ring_config(priv); 4381 4382 return ret; 4383 } 4384 4385 static int hns3_reset_notify(struct hnae3_handle *handle, 4386 enum hnae3_reset_notify_type type) 4387 { 4388 int ret = 0; 4389 4390 switch (type) { 4391 case HNAE3_UP_CLIENT: 4392 ret = hns3_reset_notify_up_enet(handle); 4393 break; 4394 case HNAE3_DOWN_CLIENT: 4395 ret = hns3_reset_notify_down_enet(handle); 4396 break; 4397 case HNAE3_INIT_CLIENT: 4398 ret = hns3_reset_notify_init_enet(handle); 4399 break; 4400 case HNAE3_UNINIT_CLIENT: 4401 ret = hns3_reset_notify_uninit_enet(handle); 4402 break; 4403 case HNAE3_RESTORE_CLIENT: 4404 ret = hns3_reset_notify_restore_enet(handle); 4405 break; 4406 default: 4407 break; 4408 } 4409 4410 return ret; 4411 } 4412 4413 int hns3_set_channels(struct net_device *netdev, 4414 struct ethtool_channels *ch) 4415 { 4416 struct hnae3_handle *h = hns3_get_handle(netdev); 4417 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4418 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4419 u32 new_tqp_num = ch->combined_count; 4420 u16 org_tqp_num; 4421 int ret; 4422 4423 if (hns3_nic_resetting(netdev)) 4424 return -EBUSY; 4425 4426 if (ch->rx_count || ch->tx_count) 4427 return -EINVAL; 4428 4429 if (new_tqp_num > hns3_get_max_available_channels(h) || 4430 new_tqp_num < 1) { 4431 dev_err(&netdev->dev, 4432 "Change tqps fail, the tqp range is from 1 to %d", 4433 hns3_get_max_available_channels(h)); 4434 return -EINVAL; 4435 } 4436 4437 if (kinfo->rss_size == new_tqp_num) 4438 return 0; 4439 4440 netif_dbg(h, drv, netdev, 4441 "set channels: tqp_num=%u, rxfh=%d\n", 4442 new_tqp_num, rxfh_configured); 4443 4444 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4445 if (ret) 4446 return ret; 4447 4448 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4449 if (ret) 4450 return ret; 4451 4452 org_tqp_num = h->kinfo.num_tqps; 4453 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4454 if (ret) { 4455 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4456 rxfh_configured); 4457 if (ret) { 4458 /* If revert to old tqp failed, fatal error occurred */ 4459 dev_err(&netdev->dev, 4460 "Revert to old tqp num fail, ret=%d", ret); 4461 return ret; 4462 } 4463 dev_info(&netdev->dev, 4464 "Change tqp num fail, Revert to old tqp num"); 4465 } 4466 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4467 if (ret) 4468 return ret; 4469 4470 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4471 } 4472 4473 static const struct hns3_hw_error_info hns3_hw_err[] = { 4474 { .type = HNAE3_PPU_POISON_ERROR, 4475 .msg = "PPU poison" }, 4476 { .type = HNAE3_CMDQ_ECC_ERROR, 4477 .msg = "IMP CMDQ error" }, 4478 { .type = HNAE3_IMP_RD_POISON_ERROR, 4479 .msg = "IMP RD poison" }, 4480 }; 4481 4482 static void hns3_process_hw_error(struct hnae3_handle *handle, 4483 enum hnae3_hw_error_type type) 4484 { 4485 int i; 4486 4487 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4488 if (hns3_hw_err[i].type == type) { 4489 dev_err(&handle->pdev->dev, "Detected %s!\n", 4490 hns3_hw_err[i].msg); 4491 break; 4492 } 4493 } 4494 } 4495 4496 static const struct hnae3_client_ops client_ops = { 4497 .init_instance = hns3_client_init, 4498 .uninit_instance = hns3_client_uninit, 4499 .link_status_change = hns3_link_status_change, 4500 .setup_tc = hns3_client_setup_tc, 4501 .reset_notify = hns3_reset_notify, 4502 .process_hw_error = hns3_process_hw_error, 4503 }; 4504 4505 /* hns3_init_module - Driver registration routine 4506 * hns3_init_module is the first routine called when the driver is 4507 * loaded. All it does is register with the PCI subsystem. 4508 */ 4509 static int __init hns3_init_module(void) 4510 { 4511 int ret; 4512 4513 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4514 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4515 4516 client.type = HNAE3_CLIENT_KNIC; 4517 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4518 hns3_driver_name); 4519 4520 client.ops = &client_ops; 4521 4522 INIT_LIST_HEAD(&client.node); 4523 4524 hns3_dbg_register_debugfs(hns3_driver_name); 4525 4526 ret = hnae3_register_client(&client); 4527 if (ret) 4528 goto err_reg_client; 4529 4530 ret = pci_register_driver(&hns3_driver); 4531 if (ret) 4532 goto err_reg_driver; 4533 4534 return ret; 4535 4536 err_reg_driver: 4537 hnae3_unregister_client(&client); 4538 err_reg_client: 4539 hns3_dbg_unregister_debugfs(); 4540 return ret; 4541 } 4542 module_init(hns3_init_module); 4543 4544 /* hns3_exit_module - Driver exit cleanup routine 4545 * hns3_exit_module is called just before the driver is removed 4546 * from memory. 4547 */ 4548 static void __exit hns3_exit_module(void) 4549 { 4550 pci_unregister_driver(&hns3_driver); 4551 hnae3_unregister_client(&client); 4552 hns3_dbg_unregister_debugfs(); 4553 } 4554 module_exit(hns3_exit_module); 4555 4556 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4557 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4558 MODULE_LICENSE("GPL"); 4559 MODULE_ALIAS("pci:hns-nic"); 4560 MODULE_VERSION(HNS3_MOD_VERSION); 4561