1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \ 95 { ptype, \ 96 l, \ 97 CHECKSUM_##s, \ 98 HNS3_L3_TYPE_##t, \ 99 1 } 100 101 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 102 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 } 103 104 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 105 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 106 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP), 107 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP), 108 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP), 109 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL), 110 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL), 111 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL), 112 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM), 113 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL), 114 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 115 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 116 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 117 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 118 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 119 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 120 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 121 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL), 122 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4), 123 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4), 124 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4), 125 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4), 126 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4), 127 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4), 128 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4), 129 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4), 130 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 134 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL), 135 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL), 136 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4), 137 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4), 138 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4), 139 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4), 140 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4), 141 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4), 142 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4), 143 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 144 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6), 145 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6), 146 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6), 147 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6), 148 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6), 149 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6), 150 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6), 151 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 152 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 153 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 154 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 155 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 156 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 157 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 158 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 159 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 160 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 161 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 162 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 163 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 164 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 165 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 166 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 167 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 216 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6), 217 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6), 218 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6), 219 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6), 220 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6), 221 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6), 222 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6), 223 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6), 224 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 228 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL), 229 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL), 230 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4), 231 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4), 232 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4), 233 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4), 234 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4), 235 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4), 236 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4), 237 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 238 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6), 239 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6), 240 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6), 241 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6), 242 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6), 243 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6), 244 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6), 245 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 246 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 247 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 248 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 249 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 250 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 251 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 252 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 253 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 254 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 255 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 256 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 257 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 258 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 259 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 260 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 261 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 361 }; 362 363 #define HNS3_INVALID_PTYPE \ 364 ARRAY_SIZE(hns3_rx_ptype_tbl) 365 366 static irqreturn_t hns3_irq_handle(int irq, void *vector) 367 { 368 struct hns3_enet_tqp_vector *tqp_vector = vector; 369 370 napi_schedule_irqoff(&tqp_vector->napi); 371 tqp_vector->event_cnt++; 372 373 return IRQ_HANDLED; 374 } 375 376 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 377 { 378 struct hns3_enet_tqp_vector *tqp_vectors; 379 unsigned int i; 380 381 for (i = 0; i < priv->vector_num; i++) { 382 tqp_vectors = &priv->tqp_vector[i]; 383 384 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 385 continue; 386 387 /* clear the affinity mask */ 388 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 389 390 /* release the irq resource */ 391 free_irq(tqp_vectors->vector_irq, tqp_vectors); 392 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 393 } 394 } 395 396 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 397 { 398 struct hns3_enet_tqp_vector *tqp_vectors; 399 int txrx_int_idx = 0; 400 int rx_int_idx = 0; 401 int tx_int_idx = 0; 402 unsigned int i; 403 int ret; 404 405 for (i = 0; i < priv->vector_num; i++) { 406 tqp_vectors = &priv->tqp_vector[i]; 407 408 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 409 continue; 410 411 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 412 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 413 "%s-%s-%s-%d", hns3_driver_name, 414 pci_name(priv->ae_handle->pdev), 415 "TxRx", txrx_int_idx++); 416 txrx_int_idx++; 417 } else if (tqp_vectors->rx_group.ring) { 418 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 419 "%s-%s-%s-%d", hns3_driver_name, 420 pci_name(priv->ae_handle->pdev), 421 "Rx", rx_int_idx++); 422 } else if (tqp_vectors->tx_group.ring) { 423 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 424 "%s-%s-%s-%d", hns3_driver_name, 425 pci_name(priv->ae_handle->pdev), 426 "Tx", tx_int_idx++); 427 } else { 428 /* Skip this unused q_vector */ 429 continue; 430 } 431 432 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 433 434 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 435 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 436 tqp_vectors->name, tqp_vectors); 437 if (ret) { 438 netdev_err(priv->netdev, "request irq(%d) fail\n", 439 tqp_vectors->vector_irq); 440 hns3_nic_uninit_irq(priv); 441 return ret; 442 } 443 444 irq_set_affinity_hint(tqp_vectors->vector_irq, 445 &tqp_vectors->affinity_mask); 446 447 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 448 } 449 450 return 0; 451 } 452 453 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 454 u32 mask_en) 455 { 456 writel(mask_en, tqp_vector->mask_addr); 457 } 458 459 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 460 { 461 napi_enable(&tqp_vector->napi); 462 enable_irq(tqp_vector->vector_irq); 463 464 /* enable vector */ 465 hns3_mask_vector_irq(tqp_vector, 1); 466 } 467 468 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 469 { 470 /* disable vector */ 471 hns3_mask_vector_irq(tqp_vector, 0); 472 473 disable_irq(tqp_vector->vector_irq); 474 napi_disable(&tqp_vector->napi); 475 cancel_work_sync(&tqp_vector->rx_group.dim.work); 476 cancel_work_sync(&tqp_vector->tx_group.dim.work); 477 } 478 479 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 480 u32 rl_value) 481 { 482 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 483 484 /* this defines the configuration for RL (Interrupt Rate Limiter). 485 * Rl defines rate of interrupts i.e. number of interrupts-per-second 486 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 487 */ 488 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 489 !tqp_vector->rx_group.coal.adapt_enable) 490 /* According to the hardware, the range of rl_reg is 491 * 0-59 and the unit is 4. 492 */ 493 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 494 495 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 496 } 497 498 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 499 u32 gl_value) 500 { 501 u32 new_val; 502 503 if (tqp_vector->rx_group.coal.unit_1us) 504 new_val = gl_value | HNS3_INT_GL_1US; 505 else 506 new_val = hns3_gl_usec_to_reg(gl_value); 507 508 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 509 } 510 511 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 512 u32 gl_value) 513 { 514 u32 new_val; 515 516 if (tqp_vector->tx_group.coal.unit_1us) 517 new_val = gl_value | HNS3_INT_GL_1US; 518 else 519 new_val = hns3_gl_usec_to_reg(gl_value); 520 521 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 522 } 523 524 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 525 u32 ql_value) 526 { 527 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 528 } 529 530 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 531 u32 ql_value) 532 { 533 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 534 } 535 536 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 537 struct hns3_nic_priv *priv) 538 { 539 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 540 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 541 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 542 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 543 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 544 545 tx_coal->adapt_enable = ptx_coal->adapt_enable; 546 rx_coal->adapt_enable = prx_coal->adapt_enable; 547 548 tx_coal->int_gl = ptx_coal->int_gl; 549 rx_coal->int_gl = prx_coal->int_gl; 550 551 rx_coal->flow_level = prx_coal->flow_level; 552 tx_coal->flow_level = ptx_coal->flow_level; 553 554 /* device version above V3(include V3), GL can configure 1us 555 * unit, so uses 1us unit. 556 */ 557 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 558 tx_coal->unit_1us = 1; 559 rx_coal->unit_1us = 1; 560 } 561 562 if (ae_dev->dev_specs.int_ql_max) { 563 tx_coal->ql_enable = 1; 564 rx_coal->ql_enable = 1; 565 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 566 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 567 tx_coal->int_ql = ptx_coal->int_ql; 568 rx_coal->int_ql = prx_coal->int_ql; 569 } 570 } 571 572 static void 573 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 574 struct hns3_nic_priv *priv) 575 { 576 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 577 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 578 struct hnae3_handle *h = priv->ae_handle; 579 580 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 581 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 582 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 583 584 if (tx_coal->ql_enable) 585 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 586 587 if (rx_coal->ql_enable) 588 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 589 } 590 591 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 592 { 593 struct hnae3_handle *h = hns3_get_handle(netdev); 594 struct hnae3_knic_private_info *kinfo = &h->kinfo; 595 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 596 unsigned int queue_size = kinfo->num_tqps; 597 int i, ret; 598 599 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 600 netdev_reset_tc(netdev); 601 } else { 602 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 603 if (ret) { 604 netdev_err(netdev, 605 "netdev_set_num_tc fail, ret=%d!\n", ret); 606 return ret; 607 } 608 609 for (i = 0; i < HNAE3_MAX_TC; i++) { 610 if (!test_bit(i, &tc_info->tc_en)) 611 continue; 612 613 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 614 tc_info->tqp_offset[i]); 615 } 616 } 617 618 ret = netif_set_real_num_tx_queues(netdev, queue_size); 619 if (ret) { 620 netdev_err(netdev, 621 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 622 return ret; 623 } 624 625 ret = netif_set_real_num_rx_queues(netdev, queue_size); 626 if (ret) { 627 netdev_err(netdev, 628 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 629 return ret; 630 } 631 632 return 0; 633 } 634 635 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 636 { 637 u16 alloc_tqps, max_rss_size, rss_size; 638 639 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 640 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 641 642 return min_t(u16, rss_size, max_rss_size); 643 } 644 645 static void hns3_tqp_enable(struct hnae3_queue *tqp) 646 { 647 u32 rcb_reg; 648 649 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 650 rcb_reg |= BIT(HNS3_RING_EN_B); 651 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 652 } 653 654 static void hns3_tqp_disable(struct hnae3_queue *tqp) 655 { 656 u32 rcb_reg; 657 658 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 659 rcb_reg &= ~BIT(HNS3_RING_EN_B); 660 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 661 } 662 663 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 664 { 665 #ifdef CONFIG_RFS_ACCEL 666 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 667 netdev->rx_cpu_rmap = NULL; 668 #endif 669 } 670 671 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 672 { 673 #ifdef CONFIG_RFS_ACCEL 674 struct hns3_nic_priv *priv = netdev_priv(netdev); 675 struct hns3_enet_tqp_vector *tqp_vector; 676 int i, ret; 677 678 if (!netdev->rx_cpu_rmap) { 679 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 680 if (!netdev->rx_cpu_rmap) 681 return -ENOMEM; 682 } 683 684 for (i = 0; i < priv->vector_num; i++) { 685 tqp_vector = &priv->tqp_vector[i]; 686 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 687 tqp_vector->vector_irq); 688 if (ret) { 689 hns3_free_rx_cpu_rmap(netdev); 690 return ret; 691 } 692 } 693 #endif 694 return 0; 695 } 696 697 static int hns3_nic_net_up(struct net_device *netdev) 698 { 699 struct hns3_nic_priv *priv = netdev_priv(netdev); 700 struct hnae3_handle *h = priv->ae_handle; 701 int i, j; 702 int ret; 703 704 ret = hns3_nic_reset_all_ring(h); 705 if (ret) 706 return ret; 707 708 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 709 710 /* enable the vectors */ 711 for (i = 0; i < priv->vector_num; i++) 712 hns3_vector_enable(&priv->tqp_vector[i]); 713 714 /* enable rcb */ 715 for (j = 0; j < h->kinfo.num_tqps; j++) 716 hns3_tqp_enable(h->kinfo.tqp[j]); 717 718 /* start the ae_dev */ 719 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 720 if (ret) { 721 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 722 while (j--) 723 hns3_tqp_disable(h->kinfo.tqp[j]); 724 725 for (j = i - 1; j >= 0; j--) 726 hns3_vector_disable(&priv->tqp_vector[j]); 727 } 728 729 return ret; 730 } 731 732 static void hns3_config_xps(struct hns3_nic_priv *priv) 733 { 734 int i; 735 736 for (i = 0; i < priv->vector_num; i++) { 737 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 738 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 739 740 while (ring) { 741 int ret; 742 743 ret = netif_set_xps_queue(priv->netdev, 744 &tqp_vector->affinity_mask, 745 ring->tqp->tqp_index); 746 if (ret) 747 netdev_warn(priv->netdev, 748 "set xps queue failed: %d", ret); 749 750 ring = ring->next; 751 } 752 } 753 } 754 755 static int hns3_nic_net_open(struct net_device *netdev) 756 { 757 struct hns3_nic_priv *priv = netdev_priv(netdev); 758 struct hnae3_handle *h = hns3_get_handle(netdev); 759 struct hnae3_knic_private_info *kinfo; 760 int i, ret; 761 762 if (hns3_nic_resetting(netdev)) 763 return -EBUSY; 764 765 netif_carrier_off(netdev); 766 767 ret = hns3_nic_set_real_num_queue(netdev); 768 if (ret) 769 return ret; 770 771 ret = hns3_nic_net_up(netdev); 772 if (ret) { 773 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 774 return ret; 775 } 776 777 kinfo = &h->kinfo; 778 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 779 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 780 781 if (h->ae_algo->ops->set_timer_task) 782 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 783 784 hns3_config_xps(priv); 785 786 netif_dbg(h, drv, netdev, "net open\n"); 787 788 return 0; 789 } 790 791 static void hns3_reset_tx_queue(struct hnae3_handle *h) 792 { 793 struct net_device *ndev = h->kinfo.netdev; 794 struct hns3_nic_priv *priv = netdev_priv(ndev); 795 struct netdev_queue *dev_queue; 796 u32 i; 797 798 for (i = 0; i < h->kinfo.num_tqps; i++) { 799 dev_queue = netdev_get_tx_queue(ndev, 800 priv->ring[i].queue_index); 801 netdev_tx_reset_queue(dev_queue); 802 } 803 } 804 805 static void hns3_nic_net_down(struct net_device *netdev) 806 { 807 struct hns3_nic_priv *priv = netdev_priv(netdev); 808 struct hnae3_handle *h = hns3_get_handle(netdev); 809 const struct hnae3_ae_ops *ops; 810 int i; 811 812 /* disable vectors */ 813 for (i = 0; i < priv->vector_num; i++) 814 hns3_vector_disable(&priv->tqp_vector[i]); 815 816 /* disable rcb */ 817 for (i = 0; i < h->kinfo.num_tqps; i++) 818 hns3_tqp_disable(h->kinfo.tqp[i]); 819 820 /* stop ae_dev */ 821 ops = priv->ae_handle->ae_algo->ops; 822 if (ops->stop) 823 ops->stop(priv->ae_handle); 824 825 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 826 * during reset process, because driver may not be able 827 * to disable the ring through firmware when downing the netdev. 828 */ 829 if (!hns3_nic_resetting(netdev)) 830 hns3_clear_all_ring(priv->ae_handle, false); 831 832 hns3_reset_tx_queue(priv->ae_handle); 833 } 834 835 static int hns3_nic_net_stop(struct net_device *netdev) 836 { 837 struct hns3_nic_priv *priv = netdev_priv(netdev); 838 struct hnae3_handle *h = hns3_get_handle(netdev); 839 840 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 841 return 0; 842 843 netif_dbg(h, drv, netdev, "net stop\n"); 844 845 if (h->ae_algo->ops->set_timer_task) 846 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 847 848 netif_carrier_off(netdev); 849 netif_tx_disable(netdev); 850 851 hns3_nic_net_down(netdev); 852 853 return 0; 854 } 855 856 static int hns3_nic_uc_sync(struct net_device *netdev, 857 const unsigned char *addr) 858 { 859 struct hnae3_handle *h = hns3_get_handle(netdev); 860 861 if (h->ae_algo->ops->add_uc_addr) 862 return h->ae_algo->ops->add_uc_addr(h, addr); 863 864 return 0; 865 } 866 867 static int hns3_nic_uc_unsync(struct net_device *netdev, 868 const unsigned char *addr) 869 { 870 struct hnae3_handle *h = hns3_get_handle(netdev); 871 872 /* need ignore the request of removing device address, because 873 * we store the device address and other addresses of uc list 874 * in the function's mac filter list. 875 */ 876 if (ether_addr_equal(addr, netdev->dev_addr)) 877 return 0; 878 879 if (h->ae_algo->ops->rm_uc_addr) 880 return h->ae_algo->ops->rm_uc_addr(h, addr); 881 882 return 0; 883 } 884 885 static int hns3_nic_mc_sync(struct net_device *netdev, 886 const unsigned char *addr) 887 { 888 struct hnae3_handle *h = hns3_get_handle(netdev); 889 890 if (h->ae_algo->ops->add_mc_addr) 891 return h->ae_algo->ops->add_mc_addr(h, addr); 892 893 return 0; 894 } 895 896 static int hns3_nic_mc_unsync(struct net_device *netdev, 897 const unsigned char *addr) 898 { 899 struct hnae3_handle *h = hns3_get_handle(netdev); 900 901 if (h->ae_algo->ops->rm_mc_addr) 902 return h->ae_algo->ops->rm_mc_addr(h, addr); 903 904 return 0; 905 } 906 907 static u8 hns3_get_netdev_flags(struct net_device *netdev) 908 { 909 u8 flags = 0; 910 911 if (netdev->flags & IFF_PROMISC) 912 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 913 else if (netdev->flags & IFF_ALLMULTI) 914 flags = HNAE3_USER_MPE; 915 916 return flags; 917 } 918 919 static void hns3_nic_set_rx_mode(struct net_device *netdev) 920 { 921 struct hnae3_handle *h = hns3_get_handle(netdev); 922 u8 new_flags; 923 924 new_flags = hns3_get_netdev_flags(netdev); 925 926 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 927 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 928 929 /* User mode Promisc mode enable and vlan filtering is disabled to 930 * let all packets in. 931 */ 932 h->netdev_flags = new_flags; 933 hns3_request_update_promisc_mode(h); 934 } 935 936 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 937 { 938 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 939 940 if (ops->request_update_promisc_mode) 941 ops->request_update_promisc_mode(handle); 942 } 943 944 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 945 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 946 { 947 u32 l4_offset, hdr_len; 948 union l3_hdr_info l3; 949 union l4_hdr_info l4; 950 u32 l4_paylen; 951 int ret; 952 953 if (!skb_is_gso(skb)) 954 return 0; 955 956 ret = skb_cow_head(skb, 0); 957 if (unlikely(ret < 0)) 958 return ret; 959 960 l3.hdr = skb_network_header(skb); 961 l4.hdr = skb_transport_header(skb); 962 963 /* Software should clear the IPv4's checksum field when tso is 964 * needed. 965 */ 966 if (l3.v4->version == 4) 967 l3.v4->check = 0; 968 969 /* tunnel packet */ 970 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 971 SKB_GSO_GRE_CSUM | 972 SKB_GSO_UDP_TUNNEL | 973 SKB_GSO_UDP_TUNNEL_CSUM)) { 974 /* reset l3&l4 pointers from outer to inner headers */ 975 l3.hdr = skb_inner_network_header(skb); 976 l4.hdr = skb_inner_transport_header(skb); 977 978 /* Software should clear the IPv4's checksum field when 979 * tso is needed. 980 */ 981 if (l3.v4->version == 4) 982 l3.v4->check = 0; 983 } 984 985 /* normal or tunnel packet */ 986 l4_offset = l4.hdr - skb->data; 987 988 /* remove payload length from inner pseudo checksum when tso */ 989 l4_paylen = skb->len - l4_offset; 990 991 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 992 hdr_len = sizeof(*l4.udp) + l4_offset; 993 csum_replace_by_diff(&l4.udp->check, 994 (__force __wsum)htonl(l4_paylen)); 995 } else { 996 hdr_len = (l4.tcp->doff << 2) + l4_offset; 997 csum_replace_by_diff(&l4.tcp->check, 998 (__force __wsum)htonl(l4_paylen)); 999 } 1000 1001 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1002 1003 /* find the txbd field values */ 1004 *paylen_fdop_ol4cs = skb->len - hdr_len; 1005 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1006 1007 /* offload outer UDP header checksum */ 1008 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1009 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1010 1011 /* get MSS for TSO */ 1012 *mss = skb_shinfo(skb)->gso_size; 1013 1014 trace_hns3_tso(skb); 1015 1016 return 0; 1017 } 1018 1019 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1020 u8 *il4_proto) 1021 { 1022 union l3_hdr_info l3; 1023 unsigned char *l4_hdr; 1024 unsigned char *exthdr; 1025 u8 l4_proto_tmp; 1026 __be16 frag_off; 1027 1028 /* find outer header point */ 1029 l3.hdr = skb_network_header(skb); 1030 l4_hdr = skb_transport_header(skb); 1031 1032 if (skb->protocol == htons(ETH_P_IPV6)) { 1033 exthdr = l3.hdr + sizeof(*l3.v6); 1034 l4_proto_tmp = l3.v6->nexthdr; 1035 if (l4_hdr != exthdr) 1036 ipv6_skip_exthdr(skb, exthdr - skb->data, 1037 &l4_proto_tmp, &frag_off); 1038 } else if (skb->protocol == htons(ETH_P_IP)) { 1039 l4_proto_tmp = l3.v4->protocol; 1040 } else { 1041 return -EINVAL; 1042 } 1043 1044 *ol4_proto = l4_proto_tmp; 1045 1046 /* tunnel packet */ 1047 if (!skb->encapsulation) { 1048 *il4_proto = 0; 1049 return 0; 1050 } 1051 1052 /* find inner header point */ 1053 l3.hdr = skb_inner_network_header(skb); 1054 l4_hdr = skb_inner_transport_header(skb); 1055 1056 if (l3.v6->version == 6) { 1057 exthdr = l3.hdr + sizeof(*l3.v6); 1058 l4_proto_tmp = l3.v6->nexthdr; 1059 if (l4_hdr != exthdr) 1060 ipv6_skip_exthdr(skb, exthdr - skb->data, 1061 &l4_proto_tmp, &frag_off); 1062 } else if (l3.v4->version == 4) { 1063 l4_proto_tmp = l3.v4->protocol; 1064 } 1065 1066 *il4_proto = l4_proto_tmp; 1067 1068 return 0; 1069 } 1070 1071 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1072 * and it is udp packet, which has a dest port as the IANA assigned. 1073 * the hardware is expected to do the checksum offload, but the 1074 * hardware will not do the checksum offload when udp dest port is 1075 * 4789, 4790 or 6081. 1076 */ 1077 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1078 { 1079 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1080 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1081 union l4_hdr_info l4; 1082 1083 /* device version above V3(include V3), the hardware can 1084 * do this checksum offload. 1085 */ 1086 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1087 return false; 1088 1089 l4.hdr = skb_transport_header(skb); 1090 1091 if (!(!skb->encapsulation && 1092 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1093 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1094 l4.udp->dest == htons(4790)))) 1095 return false; 1096 1097 return true; 1098 } 1099 1100 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1101 u32 *ol_type_vlan_len_msec) 1102 { 1103 u32 l2_len, l3_len, l4_len; 1104 unsigned char *il2_hdr; 1105 union l3_hdr_info l3; 1106 union l4_hdr_info l4; 1107 1108 l3.hdr = skb_network_header(skb); 1109 l4.hdr = skb_transport_header(skb); 1110 1111 /* compute OL2 header size, defined in 2 Bytes */ 1112 l2_len = l3.hdr - skb->data; 1113 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1114 1115 /* compute OL3 header size, defined in 4 Bytes */ 1116 l3_len = l4.hdr - l3.hdr; 1117 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1118 1119 il2_hdr = skb_inner_mac_header(skb); 1120 /* compute OL4 header size, defined in 4 Bytes */ 1121 l4_len = il2_hdr - l4.hdr; 1122 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1123 1124 /* define outer network header type */ 1125 if (skb->protocol == htons(ETH_P_IP)) { 1126 if (skb_is_gso(skb)) 1127 hns3_set_field(*ol_type_vlan_len_msec, 1128 HNS3_TXD_OL3T_S, 1129 HNS3_OL3T_IPV4_CSUM); 1130 else 1131 hns3_set_field(*ol_type_vlan_len_msec, 1132 HNS3_TXD_OL3T_S, 1133 HNS3_OL3T_IPV4_NO_CSUM); 1134 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1135 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1136 HNS3_OL3T_IPV6); 1137 } 1138 1139 if (ol4_proto == IPPROTO_UDP) 1140 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1141 HNS3_TUN_MAC_IN_UDP); 1142 else if (ol4_proto == IPPROTO_GRE) 1143 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1144 HNS3_TUN_NVGRE); 1145 } 1146 1147 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1148 u8 il4_proto, u32 *type_cs_vlan_tso, 1149 u32 *ol_type_vlan_len_msec) 1150 { 1151 unsigned char *l2_hdr = skb->data; 1152 u32 l4_proto = ol4_proto; 1153 union l4_hdr_info l4; 1154 union l3_hdr_info l3; 1155 u32 l2_len, l3_len; 1156 1157 l4.hdr = skb_transport_header(skb); 1158 l3.hdr = skb_network_header(skb); 1159 1160 /* handle encapsulation skb */ 1161 if (skb->encapsulation) { 1162 /* If this is a not UDP/GRE encapsulation skb */ 1163 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1164 /* drop the skb tunnel packet if hardware don't support, 1165 * because hardware can't calculate csum when TSO. 1166 */ 1167 if (skb_is_gso(skb)) 1168 return -EDOM; 1169 1170 /* the stack computes the IP header already, 1171 * driver calculate l4 checksum when not TSO. 1172 */ 1173 return skb_checksum_help(skb); 1174 } 1175 1176 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1177 1178 /* switch to inner header */ 1179 l2_hdr = skb_inner_mac_header(skb); 1180 l3.hdr = skb_inner_network_header(skb); 1181 l4.hdr = skb_inner_transport_header(skb); 1182 l4_proto = il4_proto; 1183 } 1184 1185 if (l3.v4->version == 4) { 1186 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1187 HNS3_L3T_IPV4); 1188 1189 /* the stack computes the IP header already, the only time we 1190 * need the hardware to recompute it is in the case of TSO. 1191 */ 1192 if (skb_is_gso(skb)) 1193 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1194 } else if (l3.v6->version == 6) { 1195 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1196 HNS3_L3T_IPV6); 1197 } 1198 1199 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1200 l2_len = l3.hdr - l2_hdr; 1201 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1202 1203 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1204 l3_len = l4.hdr - l3.hdr; 1205 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1206 1207 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1208 switch (l4_proto) { 1209 case IPPROTO_TCP: 1210 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1211 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1212 HNS3_L4T_TCP); 1213 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1214 l4.tcp->doff); 1215 break; 1216 case IPPROTO_UDP: 1217 if (hns3_tunnel_csum_bug(skb)) 1218 return skb_checksum_help(skb); 1219 1220 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1221 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1222 HNS3_L4T_UDP); 1223 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1224 (sizeof(struct udphdr) >> 2)); 1225 break; 1226 case IPPROTO_SCTP: 1227 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1228 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1229 HNS3_L4T_SCTP); 1230 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1231 (sizeof(struct sctphdr) >> 2)); 1232 break; 1233 default: 1234 /* drop the skb tunnel packet if hardware don't support, 1235 * because hardware can't calculate csum when TSO. 1236 */ 1237 if (skb_is_gso(skb)) 1238 return -EDOM; 1239 1240 /* the stack computes the IP header already, 1241 * driver calculate l4 checksum when not TSO. 1242 */ 1243 return skb_checksum_help(skb); 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1250 struct sk_buff *skb) 1251 { 1252 struct hnae3_handle *handle = tx_ring->tqp->handle; 1253 struct hnae3_ae_dev *ae_dev; 1254 struct vlan_ethhdr *vhdr; 1255 int rc; 1256 1257 if (!(skb->protocol == htons(ETH_P_8021Q) || 1258 skb_vlan_tag_present(skb))) 1259 return 0; 1260 1261 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1262 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1263 * will cause RAS error. 1264 */ 1265 ae_dev = pci_get_drvdata(handle->pdev); 1266 if (unlikely(skb_vlan_tagged_multi(skb) && 1267 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1268 handle->port_base_vlan_state == 1269 HNAE3_PORT_BASE_VLAN_ENABLE)) 1270 return -EINVAL; 1271 1272 if (skb->protocol == htons(ETH_P_8021Q) && 1273 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1274 /* When HW VLAN acceleration is turned off, and the stack 1275 * sets the protocol to 802.1q, the driver just need to 1276 * set the protocol to the encapsulated ethertype. 1277 */ 1278 skb->protocol = vlan_get_protocol(skb); 1279 return 0; 1280 } 1281 1282 if (skb_vlan_tag_present(skb)) { 1283 /* Based on hw strategy, use out_vtag in two layer tag case, 1284 * and use inner_vtag in one tag case. 1285 */ 1286 if (skb->protocol == htons(ETH_P_8021Q) && 1287 handle->port_base_vlan_state == 1288 HNAE3_PORT_BASE_VLAN_DISABLE) 1289 rc = HNS3_OUTER_VLAN_TAG; 1290 else 1291 rc = HNS3_INNER_VLAN_TAG; 1292 1293 skb->protocol = vlan_get_protocol(skb); 1294 return rc; 1295 } 1296 1297 rc = skb_cow_head(skb, 0); 1298 if (unlikely(rc < 0)) 1299 return rc; 1300 1301 vhdr = (struct vlan_ethhdr *)skb->data; 1302 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1303 & VLAN_PRIO_MASK); 1304 1305 skb->protocol = vlan_get_protocol(skb); 1306 return 0; 1307 } 1308 1309 /* check if the hardware is capable of checksum offloading */ 1310 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1311 { 1312 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1313 1314 /* Kindly note, due to backward compatibility of the TX descriptor, 1315 * HW checksum of the non-IP packets and GSO packets is handled at 1316 * different place in the following code 1317 */ 1318 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1319 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1320 return false; 1321 1322 return true; 1323 } 1324 1325 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1326 struct sk_buff *skb, struct hns3_desc *desc, 1327 struct hns3_desc_cb *desc_cb) 1328 { 1329 u32 ol_type_vlan_len_msec = 0; 1330 u32 paylen_ol4cs = skb->len; 1331 u32 type_cs_vlan_tso = 0; 1332 u16 mss_hw_csum = 0; 1333 u16 inner_vtag = 0; 1334 u16 out_vtag = 0; 1335 int ret; 1336 1337 ret = hns3_handle_vtags(ring, skb); 1338 if (unlikely(ret < 0)) { 1339 u64_stats_update_begin(&ring->syncp); 1340 ring->stats.tx_vlan_err++; 1341 u64_stats_update_end(&ring->syncp); 1342 return ret; 1343 } else if (ret == HNS3_INNER_VLAN_TAG) { 1344 inner_vtag = skb_vlan_tag_get(skb); 1345 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1346 VLAN_PRIO_MASK; 1347 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1348 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1349 out_vtag = skb_vlan_tag_get(skb); 1350 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1351 VLAN_PRIO_MASK; 1352 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1353 1); 1354 } 1355 1356 desc_cb->send_bytes = skb->len; 1357 1358 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1359 u8 ol4_proto, il4_proto; 1360 1361 if (hns3_check_hw_tx_csum(skb)) { 1362 /* set checksum start and offset, defined in 2 Bytes */ 1363 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1364 skb_checksum_start_offset(skb) >> 1); 1365 hns3_set_field(ol_type_vlan_len_msec, 1366 HNS3_TXD_CSUM_OFFSET_S, 1367 skb->csum_offset >> 1); 1368 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1369 goto out_hw_tx_csum; 1370 } 1371 1372 skb_reset_mac_len(skb); 1373 1374 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1375 if (unlikely(ret < 0)) { 1376 u64_stats_update_begin(&ring->syncp); 1377 ring->stats.tx_l4_proto_err++; 1378 u64_stats_update_end(&ring->syncp); 1379 return ret; 1380 } 1381 1382 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1383 &type_cs_vlan_tso, 1384 &ol_type_vlan_len_msec); 1385 if (unlikely(ret < 0)) { 1386 u64_stats_update_begin(&ring->syncp); 1387 ring->stats.tx_l2l3l4_err++; 1388 u64_stats_update_end(&ring->syncp); 1389 return ret; 1390 } 1391 1392 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1393 &type_cs_vlan_tso, &desc_cb->send_bytes); 1394 if (unlikely(ret < 0)) { 1395 u64_stats_update_begin(&ring->syncp); 1396 ring->stats.tx_tso_err++; 1397 u64_stats_update_end(&ring->syncp); 1398 return ret; 1399 } 1400 } 1401 1402 out_hw_tx_csum: 1403 /* Set txbd */ 1404 desc->tx.ol_type_vlan_len_msec = 1405 cpu_to_le32(ol_type_vlan_len_msec); 1406 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1407 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1408 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1409 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1410 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1411 1412 return 0; 1413 } 1414 1415 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1416 unsigned int size, enum hns_desc_type type) 1417 { 1418 #define HNS3_LIKELY_BD_NUM 1 1419 1420 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1421 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1422 struct device *dev = ring_to_dev(ring); 1423 skb_frag_t *frag; 1424 unsigned int frag_buf_num; 1425 int k, sizeoflast; 1426 dma_addr_t dma; 1427 1428 if (type == DESC_TYPE_FRAGLIST_SKB || 1429 type == DESC_TYPE_SKB) { 1430 struct sk_buff *skb = (struct sk_buff *)priv; 1431 1432 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1433 } else { 1434 frag = (skb_frag_t *)priv; 1435 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1436 } 1437 1438 if (unlikely(dma_mapping_error(dev, dma))) { 1439 u64_stats_update_begin(&ring->syncp); 1440 ring->stats.sw_err_cnt++; 1441 u64_stats_update_end(&ring->syncp); 1442 return -ENOMEM; 1443 } 1444 1445 desc_cb->priv = priv; 1446 desc_cb->length = size; 1447 desc_cb->dma = dma; 1448 desc_cb->type = type; 1449 1450 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1451 desc->addr = cpu_to_le64(dma); 1452 desc->tx.send_size = cpu_to_le16(size); 1453 desc->tx.bdtp_fe_sc_vld_ra_ri = 1454 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1455 1456 trace_hns3_tx_desc(ring, ring->next_to_use); 1457 ring_ptr_move_fw(ring, next_to_use); 1458 return HNS3_LIKELY_BD_NUM; 1459 } 1460 1461 frag_buf_num = hns3_tx_bd_count(size); 1462 sizeoflast = size % HNS3_MAX_BD_SIZE; 1463 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1464 1465 /* When frag size is bigger than hardware limit, split this frag */ 1466 for (k = 0; k < frag_buf_num; k++) { 1467 /* now, fill the descriptor */ 1468 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1469 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1470 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1471 desc->tx.bdtp_fe_sc_vld_ra_ri = 1472 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1473 1474 trace_hns3_tx_desc(ring, ring->next_to_use); 1475 /* move ring pointer to next */ 1476 ring_ptr_move_fw(ring, next_to_use); 1477 1478 desc = &ring->desc[ring->next_to_use]; 1479 } 1480 1481 return frag_buf_num; 1482 } 1483 1484 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1485 unsigned int bd_num) 1486 { 1487 unsigned int size; 1488 int i; 1489 1490 size = skb_headlen(skb); 1491 while (size > HNS3_MAX_BD_SIZE) { 1492 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1493 size -= HNS3_MAX_BD_SIZE; 1494 1495 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1496 return bd_num; 1497 } 1498 1499 if (size) { 1500 bd_size[bd_num++] = size; 1501 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1502 return bd_num; 1503 } 1504 1505 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1506 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1507 size = skb_frag_size(frag); 1508 if (!size) 1509 continue; 1510 1511 while (size > HNS3_MAX_BD_SIZE) { 1512 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1513 size -= HNS3_MAX_BD_SIZE; 1514 1515 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1516 return bd_num; 1517 } 1518 1519 bd_size[bd_num++] = size; 1520 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1521 return bd_num; 1522 } 1523 1524 return bd_num; 1525 } 1526 1527 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1528 u8 max_non_tso_bd_num, unsigned int bd_num, 1529 unsigned int recursion_level) 1530 { 1531 #define HNS3_MAX_RECURSION_LEVEL 24 1532 1533 struct sk_buff *frag_skb; 1534 1535 /* If the total len is within the max bd limit */ 1536 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1537 !skb_has_frag_list(skb) && 1538 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1539 return skb_shinfo(skb)->nr_frags + 1U; 1540 1541 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1542 return UINT_MAX; 1543 1544 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1545 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1546 return bd_num; 1547 1548 skb_walk_frags(skb, frag_skb) { 1549 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1550 bd_num, recursion_level + 1); 1551 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1552 return bd_num; 1553 } 1554 1555 return bd_num; 1556 } 1557 1558 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1559 { 1560 if (!skb->encapsulation) 1561 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1562 1563 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1564 } 1565 1566 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1567 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1568 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1569 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1570 * than MSS except the last max_non_tso_bd_num - 1 frags. 1571 */ 1572 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1573 unsigned int bd_num, u8 max_non_tso_bd_num) 1574 { 1575 unsigned int tot_len = 0; 1576 int i; 1577 1578 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1579 tot_len += bd_size[i]; 1580 1581 /* ensure the first max_non_tso_bd_num frags is greater than 1582 * mss + header 1583 */ 1584 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1585 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1586 return true; 1587 1588 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1589 * than mss except the last one. 1590 */ 1591 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1592 tot_len -= bd_size[i]; 1593 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1594 1595 if (tot_len < skb_shinfo(skb)->gso_size) 1596 return true; 1597 } 1598 1599 return false; 1600 } 1601 1602 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1603 { 1604 int i; 1605 1606 for (i = 0; i < MAX_SKB_FRAGS; i++) 1607 size[i] = skb_frag_size(&shinfo->frags[i]); 1608 } 1609 1610 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1611 struct sk_buff *skb, 1612 u8 max_non_tso_bd_num, 1613 unsigned int bd_num) 1614 { 1615 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1616 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1617 */ 1618 if (bd_num == UINT_MAX) { 1619 u64_stats_update_begin(&ring->syncp); 1620 ring->stats.over_max_recursion++; 1621 u64_stats_update_end(&ring->syncp); 1622 return -ENOMEM; 1623 } 1624 1625 /* The skb->len has exceeded the hw limitation, linearization 1626 * will not help. 1627 */ 1628 if (skb->len > HNS3_MAX_TSO_SIZE || 1629 (!skb_is_gso(skb) && skb->len > 1630 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) { 1631 u64_stats_update_begin(&ring->syncp); 1632 ring->stats.hw_limitation++; 1633 u64_stats_update_end(&ring->syncp); 1634 return -ENOMEM; 1635 } 1636 1637 if (__skb_linearize(skb)) { 1638 u64_stats_update_begin(&ring->syncp); 1639 ring->stats.sw_err_cnt++; 1640 u64_stats_update_end(&ring->syncp); 1641 return -ENOMEM; 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1648 struct net_device *netdev, 1649 struct sk_buff *skb) 1650 { 1651 struct hns3_nic_priv *priv = netdev_priv(netdev); 1652 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1653 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1654 unsigned int bd_num; 1655 1656 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1657 if (unlikely(bd_num > max_non_tso_bd_num)) { 1658 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1659 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1660 max_non_tso_bd_num)) { 1661 trace_hns3_over_max_bd(skb); 1662 goto out; 1663 } 1664 1665 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num, 1666 bd_num)) 1667 return -ENOMEM; 1668 1669 bd_num = hns3_tx_bd_count(skb->len); 1670 1671 u64_stats_update_begin(&ring->syncp); 1672 ring->stats.tx_copy++; 1673 u64_stats_update_end(&ring->syncp); 1674 } 1675 1676 out: 1677 if (likely(ring_space(ring) >= bd_num)) 1678 return bd_num; 1679 1680 netif_stop_subqueue(netdev, ring->queue_index); 1681 smp_mb(); /* Memory barrier before checking ring_space */ 1682 1683 /* Start queue in case hns3_clean_tx_ring has just made room 1684 * available and has not seen the queue stopped state performed 1685 * by netif_stop_subqueue above. 1686 */ 1687 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1688 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1689 netif_start_subqueue(netdev, ring->queue_index); 1690 return bd_num; 1691 } 1692 1693 u64_stats_update_begin(&ring->syncp); 1694 ring->stats.tx_busy++; 1695 u64_stats_update_end(&ring->syncp); 1696 1697 return -EBUSY; 1698 } 1699 1700 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1701 { 1702 struct device *dev = ring_to_dev(ring); 1703 unsigned int i; 1704 1705 for (i = 0; i < ring->desc_num; i++) { 1706 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1707 1708 memset(desc, 0, sizeof(*desc)); 1709 1710 /* check if this is where we started */ 1711 if (ring->next_to_use == next_to_use_orig) 1712 break; 1713 1714 /* rollback one */ 1715 ring_ptr_move_bw(ring, next_to_use); 1716 1717 if (!ring->desc_cb[ring->next_to_use].dma) 1718 continue; 1719 1720 /* unmap the descriptor dma address */ 1721 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1722 ring->desc_cb[ring->next_to_use].type == 1723 DESC_TYPE_FRAGLIST_SKB) 1724 dma_unmap_single(dev, 1725 ring->desc_cb[ring->next_to_use].dma, 1726 ring->desc_cb[ring->next_to_use].length, 1727 DMA_TO_DEVICE); 1728 else if (ring->desc_cb[ring->next_to_use].length) 1729 dma_unmap_page(dev, 1730 ring->desc_cb[ring->next_to_use].dma, 1731 ring->desc_cb[ring->next_to_use].length, 1732 DMA_TO_DEVICE); 1733 1734 ring->desc_cb[ring->next_to_use].length = 0; 1735 ring->desc_cb[ring->next_to_use].dma = 0; 1736 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1737 } 1738 } 1739 1740 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1741 struct sk_buff *skb, enum hns_desc_type type) 1742 { 1743 unsigned int size = skb_headlen(skb); 1744 struct sk_buff *frag_skb; 1745 int i, ret, bd_num = 0; 1746 1747 if (size) { 1748 ret = hns3_fill_desc(ring, skb, size, type); 1749 if (unlikely(ret < 0)) 1750 return ret; 1751 1752 bd_num += ret; 1753 } 1754 1755 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1756 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1757 1758 size = skb_frag_size(frag); 1759 if (!size) 1760 continue; 1761 1762 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1763 if (unlikely(ret < 0)) 1764 return ret; 1765 1766 bd_num += ret; 1767 } 1768 1769 skb_walk_frags(skb, frag_skb) { 1770 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1771 DESC_TYPE_FRAGLIST_SKB); 1772 if (unlikely(ret < 0)) 1773 return ret; 1774 1775 bd_num += ret; 1776 } 1777 1778 return bd_num; 1779 } 1780 1781 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1782 bool doorbell) 1783 { 1784 ring->pending_buf += num; 1785 1786 if (!doorbell) { 1787 u64_stats_update_begin(&ring->syncp); 1788 ring->stats.tx_more++; 1789 u64_stats_update_end(&ring->syncp); 1790 return; 1791 } 1792 1793 if (!ring->pending_buf) 1794 return; 1795 1796 writel(ring->pending_buf, 1797 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1798 ring->pending_buf = 0; 1799 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1800 } 1801 1802 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1803 { 1804 struct hns3_nic_priv *priv = netdev_priv(netdev); 1805 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1806 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1807 struct netdev_queue *dev_queue; 1808 int pre_ntu, next_to_use_head; 1809 bool doorbell; 1810 int ret; 1811 1812 /* Hardware can only handle short frames above 32 bytes */ 1813 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1814 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1815 1816 u64_stats_update_begin(&ring->syncp); 1817 ring->stats.sw_err_cnt++; 1818 u64_stats_update_end(&ring->syncp); 1819 1820 return NETDEV_TX_OK; 1821 } 1822 1823 /* Prefetch the data used later */ 1824 prefetch(skb->data); 1825 1826 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1827 if (unlikely(ret <= 0)) { 1828 if (ret == -EBUSY) { 1829 hns3_tx_doorbell(ring, 0, true); 1830 return NETDEV_TX_BUSY; 1831 } 1832 1833 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1834 goto out_err_tx_ok; 1835 } 1836 1837 next_to_use_head = ring->next_to_use; 1838 1839 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 1840 desc_cb); 1841 if (unlikely(ret < 0)) 1842 goto fill_err; 1843 1844 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 1845 * zero, which is unlikely, and 'ret > 0' means how many tx desc 1846 * need to be notified to the hw. 1847 */ 1848 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1849 if (unlikely(ret <= 0)) 1850 goto fill_err; 1851 1852 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1853 (ring->desc_num - 1); 1854 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1855 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1856 trace_hns3_tx_desc(ring, pre_ntu); 1857 1858 /* Complete translate all packets */ 1859 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1860 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 1861 netdev_xmit_more()); 1862 hns3_tx_doorbell(ring, ret, doorbell); 1863 1864 return NETDEV_TX_OK; 1865 1866 fill_err: 1867 hns3_clear_desc(ring, next_to_use_head); 1868 1869 out_err_tx_ok: 1870 dev_kfree_skb_any(skb); 1871 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1872 return NETDEV_TX_OK; 1873 } 1874 1875 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1876 { 1877 struct hnae3_handle *h = hns3_get_handle(netdev); 1878 struct sockaddr *mac_addr = p; 1879 int ret; 1880 1881 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1882 return -EADDRNOTAVAIL; 1883 1884 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1885 netdev_info(netdev, "already using mac address %pM\n", 1886 mac_addr->sa_data); 1887 return 0; 1888 } 1889 1890 /* For VF device, if there is a perm_addr, then the user will not 1891 * be allowed to change the address. 1892 */ 1893 if (!hns3_is_phys_func(h->pdev) && 1894 !is_zero_ether_addr(netdev->perm_addr)) { 1895 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1896 netdev->perm_addr, mac_addr->sa_data); 1897 return -EPERM; 1898 } 1899 1900 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1901 if (ret) { 1902 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1903 return ret; 1904 } 1905 1906 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1907 1908 return 0; 1909 } 1910 1911 static int hns3_nic_do_ioctl(struct net_device *netdev, 1912 struct ifreq *ifr, int cmd) 1913 { 1914 struct hnae3_handle *h = hns3_get_handle(netdev); 1915 1916 if (!netif_running(netdev)) 1917 return -EINVAL; 1918 1919 if (!h->ae_algo->ops->do_ioctl) 1920 return -EOPNOTSUPP; 1921 1922 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1923 } 1924 1925 static int hns3_nic_set_features(struct net_device *netdev, 1926 netdev_features_t features) 1927 { 1928 netdev_features_t changed = netdev->features ^ features; 1929 struct hns3_nic_priv *priv = netdev_priv(netdev); 1930 struct hnae3_handle *h = priv->ae_handle; 1931 bool enable; 1932 int ret; 1933 1934 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1935 enable = !!(features & NETIF_F_GRO_HW); 1936 ret = h->ae_algo->ops->set_gro_en(h, enable); 1937 if (ret) 1938 return ret; 1939 } 1940 1941 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1942 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1943 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1944 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1945 if (ret) 1946 return ret; 1947 } 1948 1949 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1950 enable = !!(features & NETIF_F_NTUPLE); 1951 h->ae_algo->ops->enable_fd(h, enable); 1952 } 1953 1954 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1955 h->ae_algo->ops->cls_flower_active(h)) { 1956 netdev_err(netdev, 1957 "there are offloaded TC filters active, cannot disable HW TC offload"); 1958 return -EINVAL; 1959 } 1960 1961 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1962 h->ae_algo->ops->enable_vlan_filter) { 1963 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1964 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 1965 if (ret) 1966 return ret; 1967 } 1968 1969 netdev->features = features; 1970 return 0; 1971 } 1972 1973 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1974 struct net_device *dev, 1975 netdev_features_t features) 1976 { 1977 #define HNS3_MAX_HDR_LEN 480U 1978 #define HNS3_MAX_L4_HDR_LEN 60U 1979 1980 size_t len; 1981 1982 if (skb->ip_summed != CHECKSUM_PARTIAL) 1983 return features; 1984 1985 if (skb->encapsulation) 1986 len = skb_inner_transport_header(skb) - skb->data; 1987 else 1988 len = skb_transport_header(skb) - skb->data; 1989 1990 /* Assume L4 is 60 byte as TCP is the only protocol with a 1991 * a flexible value, and it's max len is 60 bytes. 1992 */ 1993 len += HNS3_MAX_L4_HDR_LEN; 1994 1995 /* Hardware only supports checksum on the skb with a max header 1996 * len of 480 bytes. 1997 */ 1998 if (len > HNS3_MAX_HDR_LEN) 1999 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2000 2001 return features; 2002 } 2003 2004 static void hns3_nic_get_stats64(struct net_device *netdev, 2005 struct rtnl_link_stats64 *stats) 2006 { 2007 struct hns3_nic_priv *priv = netdev_priv(netdev); 2008 int queue_num = priv->ae_handle->kinfo.num_tqps; 2009 struct hnae3_handle *handle = priv->ae_handle; 2010 struct hns3_enet_ring *ring; 2011 u64 rx_length_errors = 0; 2012 u64 rx_crc_errors = 0; 2013 u64 rx_multicast = 0; 2014 unsigned int start; 2015 u64 tx_errors = 0; 2016 u64 rx_errors = 0; 2017 unsigned int idx; 2018 u64 tx_bytes = 0; 2019 u64 rx_bytes = 0; 2020 u64 tx_pkts = 0; 2021 u64 rx_pkts = 0; 2022 u64 tx_drop = 0; 2023 u64 rx_drop = 0; 2024 2025 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2026 return; 2027 2028 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2029 2030 for (idx = 0; idx < queue_num; idx++) { 2031 /* fetch the tx stats */ 2032 ring = &priv->ring[idx]; 2033 do { 2034 start = u64_stats_fetch_begin_irq(&ring->syncp); 2035 tx_bytes += ring->stats.tx_bytes; 2036 tx_pkts += ring->stats.tx_pkts; 2037 tx_drop += ring->stats.sw_err_cnt; 2038 tx_drop += ring->stats.tx_vlan_err; 2039 tx_drop += ring->stats.tx_l4_proto_err; 2040 tx_drop += ring->stats.tx_l2l3l4_err; 2041 tx_drop += ring->stats.tx_tso_err; 2042 tx_drop += ring->stats.over_max_recursion; 2043 tx_drop += ring->stats.hw_limitation; 2044 tx_errors += ring->stats.sw_err_cnt; 2045 tx_errors += ring->stats.tx_vlan_err; 2046 tx_errors += ring->stats.tx_l4_proto_err; 2047 tx_errors += ring->stats.tx_l2l3l4_err; 2048 tx_errors += ring->stats.tx_tso_err; 2049 tx_errors += ring->stats.over_max_recursion; 2050 tx_errors += ring->stats.hw_limitation; 2051 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2052 2053 /* fetch the rx stats */ 2054 ring = &priv->ring[idx + queue_num]; 2055 do { 2056 start = u64_stats_fetch_begin_irq(&ring->syncp); 2057 rx_bytes += ring->stats.rx_bytes; 2058 rx_pkts += ring->stats.rx_pkts; 2059 rx_drop += ring->stats.l2_err; 2060 rx_errors += ring->stats.l2_err; 2061 rx_errors += ring->stats.l3l4_csum_err; 2062 rx_crc_errors += ring->stats.l2_err; 2063 rx_multicast += ring->stats.rx_multicast; 2064 rx_length_errors += ring->stats.err_pkt_len; 2065 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2066 } 2067 2068 stats->tx_bytes = tx_bytes; 2069 stats->tx_packets = tx_pkts; 2070 stats->rx_bytes = rx_bytes; 2071 stats->rx_packets = rx_pkts; 2072 2073 stats->rx_errors = rx_errors; 2074 stats->multicast = rx_multicast; 2075 stats->rx_length_errors = rx_length_errors; 2076 stats->rx_crc_errors = rx_crc_errors; 2077 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2078 2079 stats->tx_errors = tx_errors; 2080 stats->rx_dropped = rx_drop; 2081 stats->tx_dropped = tx_drop; 2082 stats->collisions = netdev->stats.collisions; 2083 stats->rx_over_errors = netdev->stats.rx_over_errors; 2084 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2085 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2086 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2087 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2088 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2089 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2090 stats->tx_window_errors = netdev->stats.tx_window_errors; 2091 stats->rx_compressed = netdev->stats.rx_compressed; 2092 stats->tx_compressed = netdev->stats.tx_compressed; 2093 } 2094 2095 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2096 { 2097 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2098 struct hnae3_knic_private_info *kinfo; 2099 u8 tc = mqprio_qopt->qopt.num_tc; 2100 u16 mode = mqprio_qopt->mode; 2101 u8 hw = mqprio_qopt->qopt.hw; 2102 struct hnae3_handle *h; 2103 2104 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2105 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2106 return -EOPNOTSUPP; 2107 2108 if (tc > HNAE3_MAX_TC) 2109 return -EINVAL; 2110 2111 if (!netdev) 2112 return -EINVAL; 2113 2114 h = hns3_get_handle(netdev); 2115 kinfo = &h->kinfo; 2116 2117 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2118 2119 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2120 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2121 } 2122 2123 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2124 struct flow_cls_offload *flow) 2125 { 2126 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2127 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2128 2129 switch (flow->command) { 2130 case FLOW_CLS_REPLACE: 2131 if (h->ae_algo->ops->add_cls_flower) 2132 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2133 break; 2134 case FLOW_CLS_DESTROY: 2135 if (h->ae_algo->ops->del_cls_flower) 2136 return h->ae_algo->ops->del_cls_flower(h, flow); 2137 break; 2138 default: 2139 break; 2140 } 2141 2142 return -EOPNOTSUPP; 2143 } 2144 2145 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2146 void *cb_priv) 2147 { 2148 struct hns3_nic_priv *priv = cb_priv; 2149 2150 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2151 return -EOPNOTSUPP; 2152 2153 switch (type) { 2154 case TC_SETUP_CLSFLOWER: 2155 return hns3_setup_tc_cls_flower(priv, type_data); 2156 default: 2157 return -EOPNOTSUPP; 2158 } 2159 } 2160 2161 static LIST_HEAD(hns3_block_cb_list); 2162 2163 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2164 void *type_data) 2165 { 2166 struct hns3_nic_priv *priv = netdev_priv(dev); 2167 int ret; 2168 2169 switch (type) { 2170 case TC_SETUP_QDISC_MQPRIO: 2171 ret = hns3_setup_tc(dev, type_data); 2172 break; 2173 case TC_SETUP_BLOCK: 2174 ret = flow_block_cb_setup_simple(type_data, 2175 &hns3_block_cb_list, 2176 hns3_setup_tc_block_cb, 2177 priv, priv, true); 2178 break; 2179 default: 2180 return -EOPNOTSUPP; 2181 } 2182 2183 return ret; 2184 } 2185 2186 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2187 __be16 proto, u16 vid) 2188 { 2189 struct hnae3_handle *h = hns3_get_handle(netdev); 2190 int ret = -EIO; 2191 2192 if (h->ae_algo->ops->set_vlan_filter) 2193 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2194 2195 return ret; 2196 } 2197 2198 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2199 __be16 proto, u16 vid) 2200 { 2201 struct hnae3_handle *h = hns3_get_handle(netdev); 2202 int ret = -EIO; 2203 2204 if (h->ae_algo->ops->set_vlan_filter) 2205 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2206 2207 return ret; 2208 } 2209 2210 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2211 u8 qos, __be16 vlan_proto) 2212 { 2213 struct hnae3_handle *h = hns3_get_handle(netdev); 2214 int ret = -EIO; 2215 2216 netif_dbg(h, drv, netdev, 2217 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2218 vf, vlan, qos, ntohs(vlan_proto)); 2219 2220 if (h->ae_algo->ops->set_vf_vlan_filter) 2221 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2222 qos, vlan_proto); 2223 2224 return ret; 2225 } 2226 2227 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2228 { 2229 struct hnae3_handle *handle = hns3_get_handle(netdev); 2230 2231 if (hns3_nic_resetting(netdev)) 2232 return -EBUSY; 2233 2234 if (!handle->ae_algo->ops->set_vf_spoofchk) 2235 return -EOPNOTSUPP; 2236 2237 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2238 } 2239 2240 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2241 { 2242 struct hnae3_handle *handle = hns3_get_handle(netdev); 2243 2244 if (!handle->ae_algo->ops->set_vf_trust) 2245 return -EOPNOTSUPP; 2246 2247 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2248 } 2249 2250 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2251 { 2252 struct hnae3_handle *h = hns3_get_handle(netdev); 2253 int ret; 2254 2255 if (hns3_nic_resetting(netdev)) 2256 return -EBUSY; 2257 2258 if (!h->ae_algo->ops->set_mtu) 2259 return -EOPNOTSUPP; 2260 2261 netif_dbg(h, drv, netdev, 2262 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2263 2264 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2265 if (ret) 2266 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2267 ret); 2268 else 2269 netdev->mtu = new_mtu; 2270 2271 return ret; 2272 } 2273 2274 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2275 { 2276 struct hns3_nic_priv *priv = netdev_priv(ndev); 2277 struct hnae3_handle *h = hns3_get_handle(ndev); 2278 struct hns3_enet_ring *tx_ring; 2279 struct napi_struct *napi; 2280 int timeout_queue = 0; 2281 int hw_head, hw_tail; 2282 int fbd_num, fbd_oft; 2283 int ebd_num, ebd_oft; 2284 int bd_num, bd_err; 2285 int ring_en, tc; 2286 int i; 2287 2288 /* Find the stopped queue the same way the stack does */ 2289 for (i = 0; i < ndev->num_tx_queues; i++) { 2290 struct netdev_queue *q; 2291 unsigned long trans_start; 2292 2293 q = netdev_get_tx_queue(ndev, i); 2294 trans_start = q->trans_start; 2295 if (netif_xmit_stopped(q) && 2296 time_after(jiffies, 2297 (trans_start + ndev->watchdog_timeo))) { 2298 timeout_queue = i; 2299 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2300 q->state, 2301 jiffies_to_msecs(jiffies - trans_start)); 2302 break; 2303 } 2304 } 2305 2306 if (i == ndev->num_tx_queues) { 2307 netdev_info(ndev, 2308 "no netdev TX timeout queue found, timeout count: %llu\n", 2309 priv->tx_timeout_count); 2310 return false; 2311 } 2312 2313 priv->tx_timeout_count++; 2314 2315 tx_ring = &priv->ring[timeout_queue]; 2316 napi = &tx_ring->tqp_vector->napi; 2317 2318 netdev_info(ndev, 2319 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2320 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2321 tx_ring->next_to_clean, napi->state); 2322 2323 netdev_info(ndev, 2324 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2325 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2326 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2327 2328 netdev_info(ndev, 2329 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2330 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2331 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2332 2333 /* When mac received many pause frames continuous, it's unable to send 2334 * packets, which may cause tx timeout 2335 */ 2336 if (h->ae_algo->ops->get_mac_stats) { 2337 struct hns3_mac_stats mac_stats; 2338 2339 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2340 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2341 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2342 } 2343 2344 hw_head = readl_relaxed(tx_ring->tqp->io_base + 2345 HNS3_RING_TX_RING_HEAD_REG); 2346 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 2347 HNS3_RING_TX_RING_TAIL_REG); 2348 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 2349 HNS3_RING_TX_RING_FBDNUM_REG); 2350 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 2351 HNS3_RING_TX_RING_OFFSET_REG); 2352 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 2353 HNS3_RING_TX_RING_EBDNUM_REG); 2354 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 2355 HNS3_RING_TX_RING_EBD_OFFSET_REG); 2356 bd_num = readl_relaxed(tx_ring->tqp->io_base + 2357 HNS3_RING_TX_RING_BD_NUM_REG); 2358 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2359 HNS3_RING_TX_RING_BD_ERR_REG); 2360 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2361 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2362 2363 netdev_info(ndev, 2364 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2365 bd_num, hw_head, hw_tail, bd_err, 2366 readl(tx_ring->tqp_vector->mask_addr)); 2367 netdev_info(ndev, 2368 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2369 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2370 2371 return true; 2372 } 2373 2374 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2375 { 2376 struct hns3_nic_priv *priv = netdev_priv(ndev); 2377 struct hnae3_handle *h = priv->ae_handle; 2378 2379 if (!hns3_get_tx_timeo_queue_info(ndev)) 2380 return; 2381 2382 /* request the reset, and let the hclge to determine 2383 * which reset level should be done 2384 */ 2385 if (h->ae_algo->ops->reset_event) 2386 h->ae_algo->ops->reset_event(h->pdev, h); 2387 } 2388 2389 #ifdef CONFIG_RFS_ACCEL 2390 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2391 u16 rxq_index, u32 flow_id) 2392 { 2393 struct hnae3_handle *h = hns3_get_handle(dev); 2394 struct flow_keys fkeys; 2395 2396 if (!h->ae_algo->ops->add_arfs_entry) 2397 return -EOPNOTSUPP; 2398 2399 if (skb->encapsulation) 2400 return -EPROTONOSUPPORT; 2401 2402 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2403 return -EPROTONOSUPPORT; 2404 2405 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2406 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2407 (fkeys.basic.ip_proto != IPPROTO_TCP && 2408 fkeys.basic.ip_proto != IPPROTO_UDP)) 2409 return -EPROTONOSUPPORT; 2410 2411 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2412 } 2413 #endif 2414 2415 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2416 struct ifla_vf_info *ivf) 2417 { 2418 struct hnae3_handle *h = hns3_get_handle(ndev); 2419 2420 if (!h->ae_algo->ops->get_vf_config) 2421 return -EOPNOTSUPP; 2422 2423 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2424 } 2425 2426 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2427 int link_state) 2428 { 2429 struct hnae3_handle *h = hns3_get_handle(ndev); 2430 2431 if (!h->ae_algo->ops->set_vf_link_state) 2432 return -EOPNOTSUPP; 2433 2434 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2435 } 2436 2437 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2438 int min_tx_rate, int max_tx_rate) 2439 { 2440 struct hnae3_handle *h = hns3_get_handle(ndev); 2441 2442 if (!h->ae_algo->ops->set_vf_rate) 2443 return -EOPNOTSUPP; 2444 2445 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2446 false); 2447 } 2448 2449 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2450 { 2451 struct hnae3_handle *h = hns3_get_handle(netdev); 2452 2453 if (!h->ae_algo->ops->set_vf_mac) 2454 return -EOPNOTSUPP; 2455 2456 if (is_multicast_ether_addr(mac)) { 2457 netdev_err(netdev, 2458 "Invalid MAC:%pM specified. Could not set MAC\n", 2459 mac); 2460 return -EINVAL; 2461 } 2462 2463 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2464 } 2465 2466 static const struct net_device_ops hns3_nic_netdev_ops = { 2467 .ndo_open = hns3_nic_net_open, 2468 .ndo_stop = hns3_nic_net_stop, 2469 .ndo_start_xmit = hns3_nic_net_xmit, 2470 .ndo_tx_timeout = hns3_nic_net_timeout, 2471 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2472 .ndo_do_ioctl = hns3_nic_do_ioctl, 2473 .ndo_change_mtu = hns3_nic_change_mtu, 2474 .ndo_set_features = hns3_nic_set_features, 2475 .ndo_features_check = hns3_features_check, 2476 .ndo_get_stats64 = hns3_nic_get_stats64, 2477 .ndo_setup_tc = hns3_nic_setup_tc, 2478 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2479 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2480 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2481 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2482 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2483 .ndo_set_vf_trust = hns3_set_vf_trust, 2484 #ifdef CONFIG_RFS_ACCEL 2485 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2486 #endif 2487 .ndo_get_vf_config = hns3_nic_get_vf_config, 2488 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2489 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2490 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2491 }; 2492 2493 bool hns3_is_phys_func(struct pci_dev *pdev) 2494 { 2495 u32 dev_id = pdev->device; 2496 2497 switch (dev_id) { 2498 case HNAE3_DEV_ID_GE: 2499 case HNAE3_DEV_ID_25GE: 2500 case HNAE3_DEV_ID_25GE_RDMA: 2501 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2502 case HNAE3_DEV_ID_50GE_RDMA: 2503 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2504 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2505 case HNAE3_DEV_ID_200G_RDMA: 2506 return true; 2507 case HNAE3_DEV_ID_VF: 2508 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2509 return false; 2510 default: 2511 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2512 dev_id); 2513 } 2514 2515 return false; 2516 } 2517 2518 static void hns3_disable_sriov(struct pci_dev *pdev) 2519 { 2520 /* If our VFs are assigned we cannot shut down SR-IOV 2521 * without causing issues, so just leave the hardware 2522 * available but disabled 2523 */ 2524 if (pci_vfs_assigned(pdev)) { 2525 dev_warn(&pdev->dev, 2526 "disabling driver while VFs are assigned\n"); 2527 return; 2528 } 2529 2530 pci_disable_sriov(pdev); 2531 } 2532 2533 /* hns3_probe - Device initialization routine 2534 * @pdev: PCI device information struct 2535 * @ent: entry in hns3_pci_tbl 2536 * 2537 * hns3_probe initializes a PF identified by a pci_dev structure. 2538 * The OS initialization, configuring of the PF private structure, 2539 * and a hardware reset occur. 2540 * 2541 * Returns 0 on success, negative on failure 2542 */ 2543 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2544 { 2545 struct hnae3_ae_dev *ae_dev; 2546 int ret; 2547 2548 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2549 if (!ae_dev) 2550 return -ENOMEM; 2551 2552 ae_dev->pdev = pdev; 2553 ae_dev->flag = ent->driver_data; 2554 pci_set_drvdata(pdev, ae_dev); 2555 2556 ret = hnae3_register_ae_dev(ae_dev); 2557 if (ret) 2558 pci_set_drvdata(pdev, NULL); 2559 2560 return ret; 2561 } 2562 2563 /* hns3_remove - Device removal routine 2564 * @pdev: PCI device information struct 2565 */ 2566 static void hns3_remove(struct pci_dev *pdev) 2567 { 2568 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2569 2570 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2571 hns3_disable_sriov(pdev); 2572 2573 hnae3_unregister_ae_dev(ae_dev); 2574 pci_set_drvdata(pdev, NULL); 2575 } 2576 2577 /** 2578 * hns3_pci_sriov_configure 2579 * @pdev: pointer to a pci_dev structure 2580 * @num_vfs: number of VFs to allocate 2581 * 2582 * Enable or change the number of VFs. Called when the user updates the number 2583 * of VFs in sysfs. 2584 **/ 2585 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2586 { 2587 int ret; 2588 2589 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2590 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2591 return -EINVAL; 2592 } 2593 2594 if (num_vfs) { 2595 ret = pci_enable_sriov(pdev, num_vfs); 2596 if (ret) 2597 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2598 else 2599 return num_vfs; 2600 } else if (!pci_vfs_assigned(pdev)) { 2601 pci_disable_sriov(pdev); 2602 } else { 2603 dev_warn(&pdev->dev, 2604 "Unable to free VFs because some are assigned to VMs.\n"); 2605 } 2606 2607 return 0; 2608 } 2609 2610 static void hns3_shutdown(struct pci_dev *pdev) 2611 { 2612 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2613 2614 hnae3_unregister_ae_dev(ae_dev); 2615 pci_set_drvdata(pdev, NULL); 2616 2617 if (system_state == SYSTEM_POWER_OFF) 2618 pci_set_power_state(pdev, PCI_D3hot); 2619 } 2620 2621 static int __maybe_unused hns3_suspend(struct device *dev) 2622 { 2623 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2624 2625 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2626 dev_info(dev, "Begin to suspend.\n"); 2627 if (ae_dev->ops && ae_dev->ops->reset_prepare) 2628 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 2629 } 2630 2631 return 0; 2632 } 2633 2634 static int __maybe_unused hns3_resume(struct device *dev) 2635 { 2636 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2637 2638 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2639 dev_info(dev, "Begin to resume.\n"); 2640 if (ae_dev->ops && ae_dev->ops->reset_done) 2641 ae_dev->ops->reset_done(ae_dev); 2642 } 2643 2644 return 0; 2645 } 2646 2647 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2648 pci_channel_state_t state) 2649 { 2650 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2651 pci_ers_result_t ret; 2652 2653 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 2654 2655 if (state == pci_channel_io_perm_failure) 2656 return PCI_ERS_RESULT_DISCONNECT; 2657 2658 if (!ae_dev || !ae_dev->ops) { 2659 dev_err(&pdev->dev, 2660 "Can't recover - error happened before device initialized\n"); 2661 return PCI_ERS_RESULT_NONE; 2662 } 2663 2664 if (ae_dev->ops->handle_hw_ras_error) 2665 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2666 else 2667 return PCI_ERS_RESULT_NONE; 2668 2669 return ret; 2670 } 2671 2672 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2673 { 2674 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2675 const struct hnae3_ae_ops *ops; 2676 enum hnae3_reset_type reset_type; 2677 struct device *dev = &pdev->dev; 2678 2679 if (!ae_dev || !ae_dev->ops) 2680 return PCI_ERS_RESULT_NONE; 2681 2682 ops = ae_dev->ops; 2683 /* request the reset */ 2684 if (ops->reset_event && ops->get_reset_level && 2685 ops->set_default_reset_request) { 2686 if (ae_dev->hw_err_reset_req) { 2687 reset_type = ops->get_reset_level(ae_dev, 2688 &ae_dev->hw_err_reset_req); 2689 ops->set_default_reset_request(ae_dev, reset_type); 2690 dev_info(dev, "requesting reset due to PCI error\n"); 2691 ops->reset_event(pdev, NULL); 2692 } 2693 2694 return PCI_ERS_RESULT_RECOVERED; 2695 } 2696 2697 return PCI_ERS_RESULT_DISCONNECT; 2698 } 2699 2700 static void hns3_reset_prepare(struct pci_dev *pdev) 2701 { 2702 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2703 2704 dev_info(&pdev->dev, "FLR prepare\n"); 2705 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 2706 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 2707 } 2708 2709 static void hns3_reset_done(struct pci_dev *pdev) 2710 { 2711 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2712 2713 dev_info(&pdev->dev, "FLR done\n"); 2714 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 2715 ae_dev->ops->reset_done(ae_dev); 2716 } 2717 2718 static const struct pci_error_handlers hns3_err_handler = { 2719 .error_detected = hns3_error_detected, 2720 .slot_reset = hns3_slot_reset, 2721 .reset_prepare = hns3_reset_prepare, 2722 .reset_done = hns3_reset_done, 2723 }; 2724 2725 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 2726 2727 static struct pci_driver hns3_driver = { 2728 .name = hns3_driver_name, 2729 .id_table = hns3_pci_tbl, 2730 .probe = hns3_probe, 2731 .remove = hns3_remove, 2732 .shutdown = hns3_shutdown, 2733 .driver.pm = &hns3_pm_ops, 2734 .sriov_configure = hns3_pci_sriov_configure, 2735 .err_handler = &hns3_err_handler, 2736 }; 2737 2738 /* set default feature to hns3 */ 2739 static void hns3_set_default_feature(struct net_device *netdev) 2740 { 2741 struct hnae3_handle *h = hns3_get_handle(netdev); 2742 struct pci_dev *pdev = h->pdev; 2743 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2744 2745 netdev->priv_flags |= IFF_UNICAST_FLT; 2746 2747 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2748 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2749 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2750 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2751 2752 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2753 2754 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2755 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2756 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2757 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2758 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2759 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2760 2761 netdev->vlan_features |= NETIF_F_RXCSUM | 2762 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2763 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2764 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2765 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2766 2767 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2768 NETIF_F_HW_VLAN_CTAG_RX | 2769 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2770 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2771 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2772 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2773 2774 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2775 netdev->hw_features |= NETIF_F_GRO_HW; 2776 netdev->features |= NETIF_F_GRO_HW; 2777 2778 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2779 netdev->hw_features |= NETIF_F_NTUPLE; 2780 netdev->features |= NETIF_F_NTUPLE; 2781 } 2782 } 2783 2784 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2785 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2786 netdev->features |= NETIF_F_GSO_UDP_L4; 2787 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2788 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2789 } 2790 2791 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) { 2792 netdev->hw_features |= NETIF_F_HW_CSUM; 2793 netdev->features |= NETIF_F_HW_CSUM; 2794 netdev->vlan_features |= NETIF_F_HW_CSUM; 2795 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2796 } else { 2797 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2798 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2799 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2800 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2801 } 2802 2803 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) { 2804 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2805 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2806 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2807 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2808 } 2809 2810 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 2811 netdev->hw_features |= NETIF_F_HW_TC; 2812 netdev->features |= NETIF_F_HW_TC; 2813 } 2814 2815 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 2816 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2817 } 2818 2819 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2820 struct hns3_desc_cb *cb) 2821 { 2822 unsigned int order = hns3_page_order(ring); 2823 struct page *p; 2824 2825 p = dev_alloc_pages(order); 2826 if (!p) 2827 return -ENOMEM; 2828 2829 cb->priv = p; 2830 cb->page_offset = 0; 2831 cb->reuse_flag = 0; 2832 cb->buf = page_address(p); 2833 cb->length = hns3_page_size(ring); 2834 cb->type = DESC_TYPE_PAGE; 2835 page_ref_add(p, USHRT_MAX - 1); 2836 cb->pagecnt_bias = USHRT_MAX; 2837 2838 return 0; 2839 } 2840 2841 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2842 struct hns3_desc_cb *cb, int budget) 2843 { 2844 if (cb->type == DESC_TYPE_SKB) 2845 napi_consume_skb(cb->priv, budget); 2846 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2847 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2848 memset(cb, 0, sizeof(*cb)); 2849 } 2850 2851 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2852 { 2853 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2854 cb->length, ring_to_dma_dir(ring)); 2855 2856 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2857 return -EIO; 2858 2859 return 0; 2860 } 2861 2862 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2863 struct hns3_desc_cb *cb) 2864 { 2865 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2866 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2867 ring_to_dma_dir(ring)); 2868 else if (cb->length) 2869 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2870 ring_to_dma_dir(ring)); 2871 } 2872 2873 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2874 { 2875 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2876 ring->desc[i].addr = 0; 2877 } 2878 2879 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2880 int budget) 2881 { 2882 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2883 2884 if (!ring->desc_cb[i].dma) 2885 return; 2886 2887 hns3_buffer_detach(ring, i); 2888 hns3_free_buffer(ring, cb, budget); 2889 } 2890 2891 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2892 { 2893 int i; 2894 2895 for (i = 0; i < ring->desc_num; i++) 2896 hns3_free_buffer_detach(ring, i, 0); 2897 } 2898 2899 /* free desc along with its attached buffer */ 2900 static void hns3_free_desc(struct hns3_enet_ring *ring) 2901 { 2902 int size = ring->desc_num * sizeof(ring->desc[0]); 2903 2904 hns3_free_buffers(ring); 2905 2906 if (ring->desc) { 2907 dma_free_coherent(ring_to_dev(ring), size, 2908 ring->desc, ring->desc_dma_addr); 2909 ring->desc = NULL; 2910 } 2911 } 2912 2913 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2914 { 2915 int size = ring->desc_num * sizeof(ring->desc[0]); 2916 2917 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2918 &ring->desc_dma_addr, GFP_KERNEL); 2919 if (!ring->desc) 2920 return -ENOMEM; 2921 2922 return 0; 2923 } 2924 2925 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2926 struct hns3_desc_cb *cb) 2927 { 2928 int ret; 2929 2930 ret = hns3_alloc_buffer(ring, cb); 2931 if (ret) 2932 goto out; 2933 2934 ret = hns3_map_buffer(ring, cb); 2935 if (ret) 2936 goto out_with_buf; 2937 2938 return 0; 2939 2940 out_with_buf: 2941 hns3_free_buffer(ring, cb, 0); 2942 out: 2943 return ret; 2944 } 2945 2946 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2947 { 2948 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2949 2950 if (ret) 2951 return ret; 2952 2953 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2954 2955 return 0; 2956 } 2957 2958 /* Allocate memory for raw pkg, and map with dma */ 2959 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2960 { 2961 int i, j, ret; 2962 2963 for (i = 0; i < ring->desc_num; i++) { 2964 ret = hns3_alloc_and_attach_buffer(ring, i); 2965 if (ret) 2966 goto out_buffer_fail; 2967 } 2968 2969 return 0; 2970 2971 out_buffer_fail: 2972 for (j = i - 1; j >= 0; j--) 2973 hns3_free_buffer_detach(ring, j, 0); 2974 return ret; 2975 } 2976 2977 /* detach a in-used buffer and replace with a reserved one */ 2978 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2979 struct hns3_desc_cb *res_cb) 2980 { 2981 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2982 ring->desc_cb[i] = *res_cb; 2983 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2984 ring->desc[i].rx.bd_base_info = 0; 2985 } 2986 2987 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2988 { 2989 ring->desc_cb[i].reuse_flag = 0; 2990 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2991 ring->desc_cb[i].page_offset); 2992 ring->desc[i].rx.bd_base_info = 0; 2993 2994 dma_sync_single_for_device(ring_to_dev(ring), 2995 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 2996 hns3_buf_size(ring), 2997 DMA_FROM_DEVICE); 2998 } 2999 3000 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3001 int *bytes, int *pkts, int budget) 3002 { 3003 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3004 * smp_store_release() is not used in hns3_tx_doorbell() because 3005 * the doorbell operation already have the needed barrier operation. 3006 */ 3007 int ltu = smp_load_acquire(&ring->last_to_use); 3008 int ntc = ring->next_to_clean; 3009 struct hns3_desc_cb *desc_cb; 3010 bool reclaimed = false; 3011 struct hns3_desc *desc; 3012 3013 while (ltu != ntc) { 3014 desc = &ring->desc[ntc]; 3015 3016 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3017 BIT(HNS3_TXD_VLD_B)) 3018 break; 3019 3020 desc_cb = &ring->desc_cb[ntc]; 3021 3022 if (desc_cb->type == DESC_TYPE_SKB) { 3023 (*pkts)++; 3024 (*bytes) += desc_cb->send_bytes; 3025 } 3026 3027 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3028 hns3_free_buffer_detach(ring, ntc, budget); 3029 3030 if (++ntc == ring->desc_num) 3031 ntc = 0; 3032 3033 /* Issue prefetch for next Tx descriptor */ 3034 prefetch(&ring->desc_cb[ntc]); 3035 reclaimed = true; 3036 } 3037 3038 if (unlikely(!reclaimed)) 3039 return false; 3040 3041 /* This smp_store_release() pairs with smp_load_acquire() in 3042 * ring_space called by hns3_nic_net_xmit. 3043 */ 3044 smp_store_release(&ring->next_to_clean, ntc); 3045 return true; 3046 } 3047 3048 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3049 { 3050 struct net_device *netdev = ring_to_netdev(ring); 3051 struct hns3_nic_priv *priv = netdev_priv(netdev); 3052 struct netdev_queue *dev_queue; 3053 int bytes, pkts; 3054 3055 bytes = 0; 3056 pkts = 0; 3057 3058 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3059 return; 3060 3061 ring->tqp_vector->tx_group.total_bytes += bytes; 3062 ring->tqp_vector->tx_group.total_packets += pkts; 3063 3064 u64_stats_update_begin(&ring->syncp); 3065 ring->stats.tx_bytes += bytes; 3066 ring->stats.tx_pkts += pkts; 3067 u64_stats_update_end(&ring->syncp); 3068 3069 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3070 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3071 3072 if (unlikely(netif_carrier_ok(netdev) && 3073 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3074 /* Make sure that anybody stopping the queue after this 3075 * sees the new next_to_clean. 3076 */ 3077 smp_mb(); 3078 if (netif_tx_queue_stopped(dev_queue) && 3079 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3080 netif_tx_wake_queue(dev_queue); 3081 ring->stats.restart_queue++; 3082 } 3083 } 3084 } 3085 3086 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3087 { 3088 int ntc = ring->next_to_clean; 3089 int ntu = ring->next_to_use; 3090 3091 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3092 } 3093 3094 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3095 int cleand_count) 3096 { 3097 struct hns3_desc_cb *desc_cb; 3098 struct hns3_desc_cb res_cbs; 3099 int i, ret; 3100 3101 for (i = 0; i < cleand_count; i++) { 3102 desc_cb = &ring->desc_cb[ring->next_to_use]; 3103 if (desc_cb->reuse_flag) { 3104 u64_stats_update_begin(&ring->syncp); 3105 ring->stats.reuse_pg_cnt++; 3106 u64_stats_update_end(&ring->syncp); 3107 3108 hns3_reuse_buffer(ring, ring->next_to_use); 3109 } else { 3110 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3111 if (ret) { 3112 u64_stats_update_begin(&ring->syncp); 3113 ring->stats.sw_err_cnt++; 3114 u64_stats_update_end(&ring->syncp); 3115 3116 hns3_rl_err(ring_to_netdev(ring), 3117 "alloc rx buffer failed: %d\n", 3118 ret); 3119 break; 3120 } 3121 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3122 3123 u64_stats_update_begin(&ring->syncp); 3124 ring->stats.non_reuse_pg++; 3125 u64_stats_update_end(&ring->syncp); 3126 } 3127 3128 ring_ptr_move_fw(ring, next_to_use); 3129 } 3130 3131 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3132 } 3133 3134 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3135 { 3136 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 3137 } 3138 3139 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3140 struct hns3_enet_ring *ring, int pull_len, 3141 struct hns3_desc_cb *desc_cb) 3142 { 3143 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3144 int size = le16_to_cpu(desc->rx.size); 3145 u32 truesize = hns3_buf_size(ring); 3146 3147 desc_cb->pagecnt_bias--; 3148 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 3149 size - pull_len, truesize); 3150 3151 /* Avoid re-using remote and pfmemalloc pages, or the stack is still 3152 * using the page when page_offset rollback to zero, flag default 3153 * unreuse 3154 */ 3155 if (!dev_page_is_reusable(desc_cb->priv) || 3156 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 3157 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3158 return; 3159 } 3160 3161 /* Move offset up to the next cache line */ 3162 desc_cb->page_offset += truesize; 3163 3164 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 3165 desc_cb->reuse_flag = 1; 3166 } else if (hns3_can_reuse_page(desc_cb)) { 3167 desc_cb->reuse_flag = 1; 3168 desc_cb->page_offset = 0; 3169 } else if (desc_cb->pagecnt_bias) { 3170 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3171 return; 3172 } 3173 3174 if (unlikely(!desc_cb->pagecnt_bias)) { 3175 page_ref_add(desc_cb->priv, USHRT_MAX); 3176 desc_cb->pagecnt_bias = USHRT_MAX; 3177 } 3178 } 3179 3180 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3181 { 3182 __be16 type = skb->protocol; 3183 struct tcphdr *th; 3184 int depth = 0; 3185 3186 while (eth_type_vlan(type)) { 3187 struct vlan_hdr *vh; 3188 3189 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3190 return -EFAULT; 3191 3192 vh = (struct vlan_hdr *)(skb->data + depth); 3193 type = vh->h_vlan_encapsulated_proto; 3194 depth += VLAN_HLEN; 3195 } 3196 3197 skb_set_network_header(skb, depth); 3198 3199 if (type == htons(ETH_P_IP)) { 3200 const struct iphdr *iph = ip_hdr(skb); 3201 3202 depth += sizeof(struct iphdr); 3203 skb_set_transport_header(skb, depth); 3204 th = tcp_hdr(skb); 3205 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3206 iph->daddr, 0); 3207 } else if (type == htons(ETH_P_IPV6)) { 3208 const struct ipv6hdr *iph = ipv6_hdr(skb); 3209 3210 depth += sizeof(struct ipv6hdr); 3211 skb_set_transport_header(skb, depth); 3212 th = tcp_hdr(skb); 3213 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3214 &iph->daddr, 0); 3215 } else { 3216 hns3_rl_err(skb->dev, 3217 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3218 be16_to_cpu(type), depth); 3219 return -EFAULT; 3220 } 3221 3222 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3223 if (th->cwr) 3224 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3225 3226 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3227 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3228 3229 skb->csum_start = (unsigned char *)th - skb->head; 3230 skb->csum_offset = offsetof(struct tcphdr, check); 3231 skb->ip_summed = CHECKSUM_PARTIAL; 3232 3233 trace_hns3_gro(skb); 3234 3235 return 0; 3236 } 3237 3238 static bool hns3_checksum_complete(struct hns3_enet_ring *ring, 3239 struct sk_buff *skb, u32 ptype, u16 csum) 3240 { 3241 if (ptype == HNS3_INVALID_PTYPE || 3242 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3243 return false; 3244 3245 u64_stats_update_begin(&ring->syncp); 3246 ring->stats.csum_complete++; 3247 u64_stats_update_end(&ring->syncp); 3248 skb->ip_summed = CHECKSUM_COMPLETE; 3249 skb->csum = csum_unfold((__force __sum16)csum); 3250 3251 return true; 3252 } 3253 3254 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3255 u32 ol_info, u32 ptype) 3256 { 3257 int l3_type, l4_type; 3258 int ol4_type; 3259 3260 if (ptype != HNS3_INVALID_PTYPE) { 3261 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3262 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3263 3264 return; 3265 } 3266 3267 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3268 HNS3_RXD_OL4ID_S); 3269 switch (ol4_type) { 3270 case HNS3_OL4_TYPE_MAC_IN_UDP: 3271 case HNS3_OL4_TYPE_NVGRE: 3272 skb->csum_level = 1; 3273 fallthrough; 3274 case HNS3_OL4_TYPE_NO_TUN: 3275 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3276 HNS3_RXD_L3ID_S); 3277 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3278 HNS3_RXD_L4ID_S); 3279 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3280 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3281 l3_type == HNS3_L3_TYPE_IPV6) && 3282 (l4_type == HNS3_L4_TYPE_UDP || 3283 l4_type == HNS3_L4_TYPE_TCP || 3284 l4_type == HNS3_L4_TYPE_SCTP)) 3285 skb->ip_summed = CHECKSUM_UNNECESSARY; 3286 break; 3287 default: 3288 break; 3289 } 3290 } 3291 3292 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3293 u32 l234info, u32 bd_base_info, u32 ol_info, 3294 u16 csum) 3295 { 3296 struct net_device *netdev = ring_to_netdev(ring); 3297 struct hns3_nic_priv *priv = netdev_priv(netdev); 3298 u32 ptype = HNS3_INVALID_PTYPE; 3299 3300 skb->ip_summed = CHECKSUM_NONE; 3301 3302 skb_checksum_none_assert(skb); 3303 3304 if (!(netdev->features & NETIF_F_RXCSUM)) 3305 return; 3306 3307 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3308 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3309 HNS3_RXD_PTYPE_S); 3310 3311 if (hns3_checksum_complete(ring, skb, ptype, csum)) 3312 return; 3313 3314 /* check if hardware has done checksum */ 3315 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3316 return; 3317 3318 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3319 BIT(HNS3_RXD_OL3E_B) | 3320 BIT(HNS3_RXD_OL4E_B)))) { 3321 u64_stats_update_begin(&ring->syncp); 3322 ring->stats.l3l4_csum_err++; 3323 u64_stats_update_end(&ring->syncp); 3324 3325 return; 3326 } 3327 3328 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3329 } 3330 3331 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3332 { 3333 if (skb_has_frag_list(skb)) 3334 napi_gro_flush(&ring->tqp_vector->napi, false); 3335 3336 napi_gro_receive(&ring->tqp_vector->napi, skb); 3337 } 3338 3339 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3340 struct hns3_desc *desc, u32 l234info, 3341 u16 *vlan_tag) 3342 { 3343 struct hnae3_handle *handle = ring->tqp->handle; 3344 struct pci_dev *pdev = ring->tqp->handle->pdev; 3345 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3346 3347 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3348 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3349 if (!(*vlan_tag & VLAN_VID_MASK)) 3350 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3351 3352 return (*vlan_tag != 0); 3353 } 3354 3355 #define HNS3_STRP_OUTER_VLAN 0x1 3356 #define HNS3_STRP_INNER_VLAN 0x2 3357 #define HNS3_STRP_BOTH 0x3 3358 3359 /* Hardware always insert VLAN tag into RX descriptor when 3360 * remove the tag from packet, driver needs to determine 3361 * reporting which tag to stack. 3362 */ 3363 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3364 HNS3_RXD_STRP_TAGP_S)) { 3365 case HNS3_STRP_OUTER_VLAN: 3366 if (handle->port_base_vlan_state != 3367 HNAE3_PORT_BASE_VLAN_DISABLE) 3368 return false; 3369 3370 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3371 return true; 3372 case HNS3_STRP_INNER_VLAN: 3373 if (handle->port_base_vlan_state != 3374 HNAE3_PORT_BASE_VLAN_DISABLE) 3375 return false; 3376 3377 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3378 return true; 3379 case HNS3_STRP_BOTH: 3380 if (handle->port_base_vlan_state == 3381 HNAE3_PORT_BASE_VLAN_DISABLE) 3382 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3383 else 3384 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3385 3386 return true; 3387 default: 3388 return false; 3389 } 3390 } 3391 3392 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 3393 { 3394 ring->desc[ring->next_to_clean].rx.bd_base_info &= 3395 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 3396 ring->next_to_clean += 1; 3397 3398 if (unlikely(ring->next_to_clean == ring->desc_num)) 3399 ring->next_to_clean = 0; 3400 } 3401 3402 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 3403 unsigned char *va) 3404 { 3405 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 3406 struct net_device *netdev = ring_to_netdev(ring); 3407 struct sk_buff *skb; 3408 3409 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 3410 skb = ring->skb; 3411 if (unlikely(!skb)) { 3412 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3413 3414 u64_stats_update_begin(&ring->syncp); 3415 ring->stats.sw_err_cnt++; 3416 u64_stats_update_end(&ring->syncp); 3417 3418 return -ENOMEM; 3419 } 3420 3421 trace_hns3_rx_desc(ring); 3422 prefetchw(skb->data); 3423 3424 ring->pending_buf = 1; 3425 ring->frag_num = 0; 3426 ring->tail_skb = NULL; 3427 if (length <= HNS3_RX_HEAD_SIZE) { 3428 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3429 3430 /* We can reuse buffer as-is, just make sure it is reusable */ 3431 if (dev_page_is_reusable(desc_cb->priv)) 3432 desc_cb->reuse_flag = 1; 3433 else /* This page cannot be reused so discard it */ 3434 __page_frag_cache_drain(desc_cb->priv, 3435 desc_cb->pagecnt_bias); 3436 3437 hns3_rx_ring_move_fw(ring); 3438 return 0; 3439 } 3440 u64_stats_update_begin(&ring->syncp); 3441 ring->stats.seg_pkt_cnt++; 3442 u64_stats_update_end(&ring->syncp); 3443 3444 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3445 __skb_put(skb, ring->pull_len); 3446 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3447 desc_cb); 3448 hns3_rx_ring_move_fw(ring); 3449 3450 return 0; 3451 } 3452 3453 static int hns3_add_frag(struct hns3_enet_ring *ring) 3454 { 3455 struct sk_buff *skb = ring->skb; 3456 struct sk_buff *head_skb = skb; 3457 struct sk_buff *new_skb; 3458 struct hns3_desc_cb *desc_cb; 3459 struct hns3_desc *desc; 3460 u32 bd_base_info; 3461 3462 do { 3463 desc = &ring->desc[ring->next_to_clean]; 3464 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3465 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3466 /* make sure HW write desc complete */ 3467 dma_rmb(); 3468 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3469 return -ENXIO; 3470 3471 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3472 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3473 if (unlikely(!new_skb)) { 3474 hns3_rl_err(ring_to_netdev(ring), 3475 "alloc rx fraglist skb fail\n"); 3476 return -ENXIO; 3477 } 3478 ring->frag_num = 0; 3479 3480 if (ring->tail_skb) { 3481 ring->tail_skb->next = new_skb; 3482 ring->tail_skb = new_skb; 3483 } else { 3484 skb_shinfo(skb)->frag_list = new_skb; 3485 ring->tail_skb = new_skb; 3486 } 3487 } 3488 3489 if (ring->tail_skb) { 3490 head_skb->truesize += hns3_buf_size(ring); 3491 head_skb->data_len += le16_to_cpu(desc->rx.size); 3492 head_skb->len += le16_to_cpu(desc->rx.size); 3493 skb = ring->tail_skb; 3494 } 3495 3496 dma_sync_single_for_cpu(ring_to_dev(ring), 3497 desc_cb->dma + desc_cb->page_offset, 3498 hns3_buf_size(ring), 3499 DMA_FROM_DEVICE); 3500 3501 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3502 trace_hns3_rx_desc(ring); 3503 hns3_rx_ring_move_fw(ring); 3504 ring->pending_buf++; 3505 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3506 3507 return 0; 3508 } 3509 3510 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3511 struct sk_buff *skb, u32 l234info, 3512 u32 bd_base_info, u32 ol_info, u16 csum) 3513 { 3514 struct net_device *netdev = ring_to_netdev(ring); 3515 struct hns3_nic_priv *priv = netdev_priv(netdev); 3516 u32 l3_type; 3517 3518 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3519 HNS3_RXD_GRO_SIZE_M, 3520 HNS3_RXD_GRO_SIZE_S); 3521 /* if there is no HW GRO, do not set gro params */ 3522 if (!skb_shinfo(skb)->gso_size) { 3523 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 3524 csum); 3525 return 0; 3526 } 3527 3528 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3529 HNS3_RXD_GRO_COUNT_M, 3530 HNS3_RXD_GRO_COUNT_S); 3531 3532 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 3533 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3534 HNS3_RXD_PTYPE_S); 3535 3536 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 3537 } else { 3538 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3539 HNS3_RXD_L3ID_S); 3540 } 3541 3542 if (l3_type == HNS3_L3_TYPE_IPV4) 3543 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3544 else if (l3_type == HNS3_L3_TYPE_IPV6) 3545 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3546 else 3547 return -EFAULT; 3548 3549 return hns3_gro_complete(skb, l234info); 3550 } 3551 3552 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3553 struct sk_buff *skb, u32 rss_hash) 3554 { 3555 struct hnae3_handle *handle = ring->tqp->handle; 3556 enum pkt_hash_types rss_type; 3557 3558 if (rss_hash) 3559 rss_type = handle->kinfo.rss_type; 3560 else 3561 rss_type = PKT_HASH_TYPE_NONE; 3562 3563 skb_set_hash(skb, rss_hash, rss_type); 3564 } 3565 3566 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3567 { 3568 struct net_device *netdev = ring_to_netdev(ring); 3569 enum hns3_pkt_l2t_type l2_frame_type; 3570 u32 bd_base_info, l234info, ol_info; 3571 struct hns3_desc *desc; 3572 unsigned int len; 3573 int pre_ntc, ret; 3574 u16 csum; 3575 3576 /* bdinfo handled below is only valid on the last BD of the 3577 * current packet, and ring->next_to_clean indicates the first 3578 * descriptor of next packet, so need - 1 below. 3579 */ 3580 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3581 (ring->desc_num - 1); 3582 desc = &ring->desc[pre_ntc]; 3583 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3584 l234info = le32_to_cpu(desc->rx.l234_info); 3585 ol_info = le32_to_cpu(desc->rx.ol_info); 3586 csum = le16_to_cpu(desc->csum); 3587 3588 /* Based on hw strategy, the tag offloaded will be stored at 3589 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3590 * in one layer tag case. 3591 */ 3592 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3593 u16 vlan_tag; 3594 3595 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3596 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3597 vlan_tag); 3598 } 3599 3600 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3601 BIT(HNS3_RXD_L2E_B))))) { 3602 u64_stats_update_begin(&ring->syncp); 3603 if (l234info & BIT(HNS3_RXD_L2E_B)) 3604 ring->stats.l2_err++; 3605 else 3606 ring->stats.err_pkt_len++; 3607 u64_stats_update_end(&ring->syncp); 3608 3609 return -EFAULT; 3610 } 3611 3612 len = skb->len; 3613 3614 /* Do update ip stack process */ 3615 skb->protocol = eth_type_trans(skb, netdev); 3616 3617 /* This is needed in order to enable forwarding support */ 3618 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3619 bd_base_info, ol_info, csum); 3620 if (unlikely(ret)) { 3621 u64_stats_update_begin(&ring->syncp); 3622 ring->stats.rx_err_cnt++; 3623 u64_stats_update_end(&ring->syncp); 3624 return ret; 3625 } 3626 3627 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3628 HNS3_RXD_DMAC_S); 3629 3630 u64_stats_update_begin(&ring->syncp); 3631 ring->stats.rx_pkts++; 3632 ring->stats.rx_bytes += len; 3633 3634 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3635 ring->stats.rx_multicast++; 3636 3637 u64_stats_update_end(&ring->syncp); 3638 3639 ring->tqp_vector->rx_group.total_bytes += len; 3640 3641 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3642 return 0; 3643 } 3644 3645 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3646 { 3647 struct sk_buff *skb = ring->skb; 3648 struct hns3_desc_cb *desc_cb; 3649 struct hns3_desc *desc; 3650 unsigned int length; 3651 u32 bd_base_info; 3652 int ret; 3653 3654 desc = &ring->desc[ring->next_to_clean]; 3655 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3656 3657 prefetch(desc); 3658 3659 if (!skb) { 3660 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3661 /* Check valid BD */ 3662 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3663 return -ENXIO; 3664 3665 dma_rmb(); 3666 length = le16_to_cpu(desc->rx.size); 3667 3668 ring->va = desc_cb->buf + desc_cb->page_offset; 3669 3670 dma_sync_single_for_cpu(ring_to_dev(ring), 3671 desc_cb->dma + desc_cb->page_offset, 3672 hns3_buf_size(ring), 3673 DMA_FROM_DEVICE); 3674 3675 /* Prefetch first cache line of first page. 3676 * Idea is to cache few bytes of the header of the packet. 3677 * Our L1 Cache line size is 64B so need to prefetch twice to make 3678 * it 128B. But in actual we can have greater size of caches with 3679 * 128B Level 1 cache lines. In such a case, single fetch would 3680 * suffice to cache in the relevant part of the header. 3681 */ 3682 net_prefetch(ring->va); 3683 3684 ret = hns3_alloc_skb(ring, length, ring->va); 3685 skb = ring->skb; 3686 3687 if (ret < 0) /* alloc buffer fail */ 3688 return ret; 3689 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3690 ret = hns3_add_frag(ring); 3691 if (ret) 3692 return ret; 3693 } 3694 } else { 3695 ret = hns3_add_frag(ring); 3696 if (ret) 3697 return ret; 3698 } 3699 3700 /* As the head data may be changed when GRO enable, copy 3701 * the head data in after other data rx completed 3702 */ 3703 if (skb->len > HNS3_RX_HEAD_SIZE) 3704 memcpy(skb->data, ring->va, 3705 ALIGN(ring->pull_len, sizeof(long))); 3706 3707 ret = hns3_handle_bdinfo(ring, skb); 3708 if (unlikely(ret)) { 3709 dev_kfree_skb_any(skb); 3710 return ret; 3711 } 3712 3713 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3714 return 0; 3715 } 3716 3717 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3718 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3719 { 3720 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3721 int unused_count = hns3_desc_unused(ring); 3722 int recv_pkts = 0; 3723 int err; 3724 3725 unused_count -= ring->pending_buf; 3726 3727 while (recv_pkts < budget) { 3728 /* Reuse or realloc buffers */ 3729 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3730 hns3_nic_alloc_rx_buffers(ring, unused_count); 3731 unused_count = hns3_desc_unused(ring) - 3732 ring->pending_buf; 3733 } 3734 3735 /* Poll one pkt */ 3736 err = hns3_handle_rx_bd(ring); 3737 /* Do not get FE for the packet or failed to alloc skb */ 3738 if (unlikely(!ring->skb || err == -ENXIO)) { 3739 goto out; 3740 } else if (likely(!err)) { 3741 rx_fn(ring, ring->skb); 3742 recv_pkts++; 3743 } 3744 3745 unused_count += ring->pending_buf; 3746 ring->skb = NULL; 3747 ring->pending_buf = 0; 3748 } 3749 3750 out: 3751 /* Make all data has been write before submit */ 3752 if (unused_count > 0) 3753 hns3_nic_alloc_rx_buffers(ring, unused_count); 3754 3755 return recv_pkts; 3756 } 3757 3758 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 3759 { 3760 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3761 struct dim_sample sample = {}; 3762 3763 if (!rx_group->coal.adapt_enable) 3764 return; 3765 3766 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 3767 rx_group->total_bytes, &sample); 3768 net_dim(&rx_group->dim, sample); 3769 } 3770 3771 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 3772 { 3773 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3774 struct dim_sample sample = {}; 3775 3776 if (!tx_group->coal.adapt_enable) 3777 return; 3778 3779 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 3780 tx_group->total_bytes, &sample); 3781 net_dim(&tx_group->dim, sample); 3782 } 3783 3784 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3785 { 3786 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3787 struct hns3_enet_ring *ring; 3788 int rx_pkt_total = 0; 3789 3790 struct hns3_enet_tqp_vector *tqp_vector = 3791 container_of(napi, struct hns3_enet_tqp_vector, napi); 3792 bool clean_complete = true; 3793 int rx_budget = budget; 3794 3795 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3796 napi_complete(napi); 3797 return 0; 3798 } 3799 3800 /* Since the actual Tx work is minimal, we can give the Tx a larger 3801 * budget and be more aggressive about cleaning up the Tx descriptors. 3802 */ 3803 hns3_for_each_ring(ring, tqp_vector->tx_group) 3804 hns3_clean_tx_ring(ring, budget); 3805 3806 /* make sure rx ring budget not smaller than 1 */ 3807 if (tqp_vector->num_tqps > 1) 3808 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3809 3810 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3811 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3812 hns3_rx_skb); 3813 if (rx_cleaned >= rx_budget) 3814 clean_complete = false; 3815 3816 rx_pkt_total += rx_cleaned; 3817 } 3818 3819 tqp_vector->rx_group.total_packets += rx_pkt_total; 3820 3821 if (!clean_complete) 3822 return budget; 3823 3824 if (napi_complete(napi) && 3825 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3826 hns3_update_rx_int_coalesce(tqp_vector); 3827 hns3_update_tx_int_coalesce(tqp_vector); 3828 3829 hns3_mask_vector_irq(tqp_vector, 1); 3830 } 3831 3832 return rx_pkt_total; 3833 } 3834 3835 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3836 struct hnae3_ring_chain_node *head) 3837 { 3838 struct pci_dev *pdev = tqp_vector->handle->pdev; 3839 struct hnae3_ring_chain_node *cur_chain = head; 3840 struct hnae3_ring_chain_node *chain; 3841 struct hns3_enet_ring *tx_ring; 3842 struct hns3_enet_ring *rx_ring; 3843 3844 tx_ring = tqp_vector->tx_group.ring; 3845 if (tx_ring) { 3846 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3847 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3848 HNAE3_RING_TYPE_TX); 3849 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3850 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3851 3852 cur_chain->next = NULL; 3853 3854 while (tx_ring->next) { 3855 tx_ring = tx_ring->next; 3856 3857 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3858 GFP_KERNEL); 3859 if (!chain) 3860 goto err_free_chain; 3861 3862 cur_chain->next = chain; 3863 chain->tqp_index = tx_ring->tqp->tqp_index; 3864 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3865 HNAE3_RING_TYPE_TX); 3866 hnae3_set_field(chain->int_gl_idx, 3867 HNAE3_RING_GL_IDX_M, 3868 HNAE3_RING_GL_IDX_S, 3869 HNAE3_RING_GL_TX); 3870 3871 cur_chain = chain; 3872 } 3873 } 3874 3875 rx_ring = tqp_vector->rx_group.ring; 3876 if (!tx_ring && rx_ring) { 3877 cur_chain->next = NULL; 3878 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3879 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3880 HNAE3_RING_TYPE_RX); 3881 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3882 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3883 3884 rx_ring = rx_ring->next; 3885 } 3886 3887 while (rx_ring) { 3888 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3889 if (!chain) 3890 goto err_free_chain; 3891 3892 cur_chain->next = chain; 3893 chain->tqp_index = rx_ring->tqp->tqp_index; 3894 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3895 HNAE3_RING_TYPE_RX); 3896 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3897 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3898 3899 cur_chain = chain; 3900 3901 rx_ring = rx_ring->next; 3902 } 3903 3904 return 0; 3905 3906 err_free_chain: 3907 cur_chain = head->next; 3908 while (cur_chain) { 3909 chain = cur_chain->next; 3910 devm_kfree(&pdev->dev, cur_chain); 3911 cur_chain = chain; 3912 } 3913 head->next = NULL; 3914 3915 return -ENOMEM; 3916 } 3917 3918 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3919 struct hnae3_ring_chain_node *head) 3920 { 3921 struct pci_dev *pdev = tqp_vector->handle->pdev; 3922 struct hnae3_ring_chain_node *chain_tmp, *chain; 3923 3924 chain = head->next; 3925 3926 while (chain) { 3927 chain_tmp = chain->next; 3928 devm_kfree(&pdev->dev, chain); 3929 chain = chain_tmp; 3930 } 3931 } 3932 3933 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3934 struct hns3_enet_ring *ring) 3935 { 3936 ring->next = group->ring; 3937 group->ring = ring; 3938 3939 group->count++; 3940 } 3941 3942 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3943 { 3944 struct pci_dev *pdev = priv->ae_handle->pdev; 3945 struct hns3_enet_tqp_vector *tqp_vector; 3946 int num_vectors = priv->vector_num; 3947 int numa_node; 3948 int vector_i; 3949 3950 numa_node = dev_to_node(&pdev->dev); 3951 3952 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3953 tqp_vector = &priv->tqp_vector[vector_i]; 3954 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3955 &tqp_vector->affinity_mask); 3956 } 3957 } 3958 3959 static void hns3_rx_dim_work(struct work_struct *work) 3960 { 3961 struct dim *dim = container_of(work, struct dim, work); 3962 struct hns3_enet_ring_group *group = container_of(dim, 3963 struct hns3_enet_ring_group, dim); 3964 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 3965 struct dim_cq_moder cur_moder = 3966 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 3967 3968 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 3969 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 3970 3971 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 3972 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 3973 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 3974 } 3975 3976 dim->state = DIM_START_MEASURE; 3977 } 3978 3979 static void hns3_tx_dim_work(struct work_struct *work) 3980 { 3981 struct dim *dim = container_of(work, struct dim, work); 3982 struct hns3_enet_ring_group *group = container_of(dim, 3983 struct hns3_enet_ring_group, dim); 3984 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 3985 struct dim_cq_moder cur_moder = 3986 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 3987 3988 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 3989 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 3990 3991 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 3992 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 3993 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 3994 } 3995 3996 dim->state = DIM_START_MEASURE; 3997 } 3998 3999 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4000 { 4001 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4002 tqp_vector->rx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4003 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4004 tqp_vector->tx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4005 } 4006 4007 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4008 { 4009 struct hnae3_handle *h = priv->ae_handle; 4010 struct hns3_enet_tqp_vector *tqp_vector; 4011 int ret; 4012 int i; 4013 4014 hns3_nic_set_cpumask(priv); 4015 4016 for (i = 0; i < priv->vector_num; i++) { 4017 tqp_vector = &priv->tqp_vector[i]; 4018 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4019 tqp_vector->num_tqps = 0; 4020 hns3_nic_init_dim(tqp_vector); 4021 } 4022 4023 for (i = 0; i < h->kinfo.num_tqps; i++) { 4024 u16 vector_i = i % priv->vector_num; 4025 u16 tqp_num = h->kinfo.num_tqps; 4026 4027 tqp_vector = &priv->tqp_vector[vector_i]; 4028 4029 hns3_add_ring_to_group(&tqp_vector->tx_group, 4030 &priv->ring[i]); 4031 4032 hns3_add_ring_to_group(&tqp_vector->rx_group, 4033 &priv->ring[i + tqp_num]); 4034 4035 priv->ring[i].tqp_vector = tqp_vector; 4036 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4037 tqp_vector->num_tqps++; 4038 } 4039 4040 for (i = 0; i < priv->vector_num; i++) { 4041 struct hnae3_ring_chain_node vector_ring_chain; 4042 4043 tqp_vector = &priv->tqp_vector[i]; 4044 4045 tqp_vector->rx_group.total_bytes = 0; 4046 tqp_vector->rx_group.total_packets = 0; 4047 tqp_vector->tx_group.total_bytes = 0; 4048 tqp_vector->tx_group.total_packets = 0; 4049 tqp_vector->handle = h; 4050 4051 ret = hns3_get_vector_ring_chain(tqp_vector, 4052 &vector_ring_chain); 4053 if (ret) 4054 goto map_ring_fail; 4055 4056 ret = h->ae_algo->ops->map_ring_to_vector(h, 4057 tqp_vector->vector_irq, &vector_ring_chain); 4058 4059 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4060 4061 if (ret) 4062 goto map_ring_fail; 4063 4064 netif_napi_add(priv->netdev, &tqp_vector->napi, 4065 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 4066 } 4067 4068 return 0; 4069 4070 map_ring_fail: 4071 while (i--) 4072 netif_napi_del(&priv->tqp_vector[i].napi); 4073 4074 return ret; 4075 } 4076 4077 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4078 { 4079 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4080 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4081 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4082 4083 /* initialize the configuration for interrupt coalescing. 4084 * 1. GL (Interrupt Gap Limiter) 4085 * 2. RL (Interrupt Rate Limiter) 4086 * 3. QL (Interrupt Quantity Limiter) 4087 * 4088 * Default: enable interrupt coalescing self-adaptive and GL 4089 */ 4090 tx_coal->adapt_enable = 1; 4091 rx_coal->adapt_enable = 1; 4092 4093 tx_coal->int_gl = HNS3_INT_GL_50K; 4094 rx_coal->int_gl = HNS3_INT_GL_50K; 4095 4096 rx_coal->flow_level = HNS3_FLOW_LOW; 4097 tx_coal->flow_level = HNS3_FLOW_LOW; 4098 4099 if (ae_dev->dev_specs.int_ql_max) { 4100 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4101 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4102 } 4103 } 4104 4105 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4106 { 4107 struct hnae3_handle *h = priv->ae_handle; 4108 struct hns3_enet_tqp_vector *tqp_vector; 4109 struct hnae3_vector_info *vector; 4110 struct pci_dev *pdev = h->pdev; 4111 u16 tqp_num = h->kinfo.num_tqps; 4112 u16 vector_num; 4113 int ret = 0; 4114 u16 i; 4115 4116 /* RSS size, cpu online and vector_num should be the same */ 4117 /* Should consider 2p/4p later */ 4118 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4119 4120 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4121 GFP_KERNEL); 4122 if (!vector) 4123 return -ENOMEM; 4124 4125 /* save the actual available vector number */ 4126 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4127 4128 priv->vector_num = vector_num; 4129 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4130 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4131 GFP_KERNEL); 4132 if (!priv->tqp_vector) { 4133 ret = -ENOMEM; 4134 goto out; 4135 } 4136 4137 for (i = 0; i < priv->vector_num; i++) { 4138 tqp_vector = &priv->tqp_vector[i]; 4139 tqp_vector->idx = i; 4140 tqp_vector->mask_addr = vector[i].io_addr; 4141 tqp_vector->vector_irq = vector[i].vector; 4142 hns3_vector_coalesce_init(tqp_vector, priv); 4143 } 4144 4145 out: 4146 devm_kfree(&pdev->dev, vector); 4147 return ret; 4148 } 4149 4150 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4151 { 4152 group->ring = NULL; 4153 group->count = 0; 4154 } 4155 4156 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4157 { 4158 struct hnae3_ring_chain_node vector_ring_chain; 4159 struct hnae3_handle *h = priv->ae_handle; 4160 struct hns3_enet_tqp_vector *tqp_vector; 4161 int i; 4162 4163 for (i = 0; i < priv->vector_num; i++) { 4164 tqp_vector = &priv->tqp_vector[i]; 4165 4166 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4167 continue; 4168 4169 /* Since the mapping can be overwritten, when fail to get the 4170 * chain between vector and ring, we should go on to deal with 4171 * the remaining options. 4172 */ 4173 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 4174 dev_warn(priv->dev, "failed to get ring chain\n"); 4175 4176 h->ae_algo->ops->unmap_ring_from_vector(h, 4177 tqp_vector->vector_irq, &vector_ring_chain); 4178 4179 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4180 4181 hns3_clear_ring_group(&tqp_vector->rx_group); 4182 hns3_clear_ring_group(&tqp_vector->tx_group); 4183 netif_napi_del(&priv->tqp_vector[i].napi); 4184 } 4185 } 4186 4187 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4188 { 4189 struct hnae3_handle *h = priv->ae_handle; 4190 struct pci_dev *pdev = h->pdev; 4191 int i, ret; 4192 4193 for (i = 0; i < priv->vector_num; i++) { 4194 struct hns3_enet_tqp_vector *tqp_vector; 4195 4196 tqp_vector = &priv->tqp_vector[i]; 4197 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4198 if (ret) 4199 return; 4200 } 4201 4202 devm_kfree(&pdev->dev, priv->tqp_vector); 4203 } 4204 4205 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4206 unsigned int ring_type) 4207 { 4208 int queue_num = priv->ae_handle->kinfo.num_tqps; 4209 struct hns3_enet_ring *ring; 4210 int desc_num; 4211 4212 if (ring_type == HNAE3_RING_TYPE_TX) { 4213 ring = &priv->ring[q->tqp_index]; 4214 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4215 ring->queue_index = q->tqp_index; 4216 } else { 4217 ring = &priv->ring[q->tqp_index + queue_num]; 4218 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4219 ring->queue_index = q->tqp_index; 4220 } 4221 4222 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4223 4224 ring->tqp = q; 4225 ring->desc = NULL; 4226 ring->desc_cb = NULL; 4227 ring->dev = priv->dev; 4228 ring->desc_dma_addr = 0; 4229 ring->buf_size = q->buf_size; 4230 ring->desc_num = desc_num; 4231 ring->next_to_use = 0; 4232 ring->next_to_clean = 0; 4233 ring->last_to_use = 0; 4234 } 4235 4236 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4237 struct hns3_nic_priv *priv) 4238 { 4239 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4240 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4241 } 4242 4243 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4244 { 4245 struct hnae3_handle *h = priv->ae_handle; 4246 struct pci_dev *pdev = h->pdev; 4247 int i; 4248 4249 priv->ring = devm_kzalloc(&pdev->dev, 4250 array3_size(h->kinfo.num_tqps, 4251 sizeof(*priv->ring), 2), 4252 GFP_KERNEL); 4253 if (!priv->ring) 4254 return -ENOMEM; 4255 4256 for (i = 0; i < h->kinfo.num_tqps; i++) 4257 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4258 4259 return 0; 4260 } 4261 4262 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4263 { 4264 if (!priv->ring) 4265 return; 4266 4267 devm_kfree(priv->dev, priv->ring); 4268 priv->ring = NULL; 4269 } 4270 4271 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4272 { 4273 int ret; 4274 4275 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4276 return -EINVAL; 4277 4278 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4279 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4280 if (!ring->desc_cb) { 4281 ret = -ENOMEM; 4282 goto out; 4283 } 4284 4285 ret = hns3_alloc_desc(ring); 4286 if (ret) 4287 goto out_with_desc_cb; 4288 4289 if (!HNAE3_IS_TX_RING(ring)) { 4290 ret = hns3_alloc_ring_buffers(ring); 4291 if (ret) 4292 goto out_with_desc; 4293 } 4294 4295 return 0; 4296 4297 out_with_desc: 4298 hns3_free_desc(ring); 4299 out_with_desc_cb: 4300 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4301 ring->desc_cb = NULL; 4302 out: 4303 return ret; 4304 } 4305 4306 void hns3_fini_ring(struct hns3_enet_ring *ring) 4307 { 4308 hns3_free_desc(ring); 4309 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4310 ring->desc_cb = NULL; 4311 ring->next_to_clean = 0; 4312 ring->next_to_use = 0; 4313 ring->last_to_use = 0; 4314 ring->pending_buf = 0; 4315 if (ring->skb) { 4316 dev_kfree_skb_any(ring->skb); 4317 ring->skb = NULL; 4318 } 4319 } 4320 4321 static int hns3_buf_size2type(u32 buf_size) 4322 { 4323 int bd_size_type; 4324 4325 switch (buf_size) { 4326 case 512: 4327 bd_size_type = HNS3_BD_SIZE_512_TYPE; 4328 break; 4329 case 1024: 4330 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 4331 break; 4332 case 2048: 4333 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4334 break; 4335 case 4096: 4336 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 4337 break; 4338 default: 4339 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4340 } 4341 4342 return bd_size_type; 4343 } 4344 4345 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 4346 { 4347 dma_addr_t dma = ring->desc_dma_addr; 4348 struct hnae3_queue *q = ring->tqp; 4349 4350 if (!HNAE3_IS_TX_RING(ring)) { 4351 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 4352 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 4353 (u32)((dma >> 31) >> 1)); 4354 4355 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 4356 hns3_buf_size2type(ring->buf_size)); 4357 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 4358 ring->desc_num / 8 - 1); 4359 } else { 4360 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 4361 (u32)dma); 4362 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 4363 (u32)((dma >> 31) >> 1)); 4364 4365 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 4366 ring->desc_num / 8 - 1); 4367 } 4368 } 4369 4370 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 4371 { 4372 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4373 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 4374 int i; 4375 4376 for (i = 0; i < HNAE3_MAX_TC; i++) { 4377 int j; 4378 4379 if (!test_bit(i, &tc_info->tc_en)) 4380 continue; 4381 4382 for (j = 0; j < tc_info->tqp_count[i]; j++) { 4383 struct hnae3_queue *q; 4384 4385 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 4386 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 4387 } 4388 } 4389 } 4390 4391 int hns3_init_all_ring(struct hns3_nic_priv *priv) 4392 { 4393 struct hnae3_handle *h = priv->ae_handle; 4394 int ring_num = h->kinfo.num_tqps * 2; 4395 int i, j; 4396 int ret; 4397 4398 for (i = 0; i < ring_num; i++) { 4399 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4400 if (ret) { 4401 dev_err(priv->dev, 4402 "Alloc ring memory fail! ret=%d\n", ret); 4403 goto out_when_alloc_ring_memory; 4404 } 4405 4406 u64_stats_init(&priv->ring[i].syncp); 4407 } 4408 4409 return 0; 4410 4411 out_when_alloc_ring_memory: 4412 for (j = i - 1; j >= 0; j--) 4413 hns3_fini_ring(&priv->ring[j]); 4414 4415 return -ENOMEM; 4416 } 4417 4418 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4419 { 4420 struct hnae3_handle *h = priv->ae_handle; 4421 int i; 4422 4423 for (i = 0; i < h->kinfo.num_tqps; i++) { 4424 hns3_fini_ring(&priv->ring[i]); 4425 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4426 } 4427 } 4428 4429 /* Set mac addr if it is configured. or leave it to the AE driver */ 4430 static int hns3_init_mac_addr(struct net_device *netdev) 4431 { 4432 struct hns3_nic_priv *priv = netdev_priv(netdev); 4433 struct hnae3_handle *h = priv->ae_handle; 4434 u8 mac_addr_temp[ETH_ALEN]; 4435 int ret = 0; 4436 4437 if (h->ae_algo->ops->get_mac_addr) 4438 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4439 4440 /* Check if the MAC address is valid, if not get a random one */ 4441 if (!is_valid_ether_addr(mac_addr_temp)) { 4442 eth_hw_addr_random(netdev); 4443 dev_warn(priv->dev, "using random MAC address %pM\n", 4444 netdev->dev_addr); 4445 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4446 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4447 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4448 } else { 4449 return 0; 4450 } 4451 4452 if (h->ae_algo->ops->set_mac_addr) 4453 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4454 4455 return ret; 4456 } 4457 4458 static int hns3_init_phy(struct net_device *netdev) 4459 { 4460 struct hnae3_handle *h = hns3_get_handle(netdev); 4461 int ret = 0; 4462 4463 if (h->ae_algo->ops->mac_connect_phy) 4464 ret = h->ae_algo->ops->mac_connect_phy(h); 4465 4466 return ret; 4467 } 4468 4469 static void hns3_uninit_phy(struct net_device *netdev) 4470 { 4471 struct hnae3_handle *h = hns3_get_handle(netdev); 4472 4473 if (h->ae_algo->ops->mac_disconnect_phy) 4474 h->ae_algo->ops->mac_disconnect_phy(h); 4475 } 4476 4477 static int hns3_client_start(struct hnae3_handle *handle) 4478 { 4479 if (!handle->ae_algo->ops->client_start) 4480 return 0; 4481 4482 return handle->ae_algo->ops->client_start(handle); 4483 } 4484 4485 static void hns3_client_stop(struct hnae3_handle *handle) 4486 { 4487 if (!handle->ae_algo->ops->client_stop) 4488 return; 4489 4490 handle->ae_algo->ops->client_stop(handle); 4491 } 4492 4493 static void hns3_info_show(struct hns3_nic_priv *priv) 4494 { 4495 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4496 4497 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4498 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4499 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4500 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4501 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4502 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4503 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4504 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 4505 kinfo->tc_info.num_tc); 4506 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4507 } 4508 4509 static int hns3_client_init(struct hnae3_handle *handle) 4510 { 4511 struct pci_dev *pdev = handle->pdev; 4512 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4513 u16 alloc_tqps, max_rss_size; 4514 struct hns3_nic_priv *priv; 4515 struct net_device *netdev; 4516 int ret; 4517 4518 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4519 &max_rss_size); 4520 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4521 if (!netdev) 4522 return -ENOMEM; 4523 4524 priv = netdev_priv(netdev); 4525 priv->dev = &pdev->dev; 4526 priv->netdev = netdev; 4527 priv->ae_handle = handle; 4528 priv->tx_timeout_count = 0; 4529 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4530 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4531 4532 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4533 4534 handle->kinfo.netdev = netdev; 4535 handle->priv = (void *)priv; 4536 4537 hns3_init_mac_addr(netdev); 4538 4539 hns3_set_default_feature(netdev); 4540 4541 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4542 netdev->priv_flags |= IFF_UNICAST_FLT; 4543 netdev->netdev_ops = &hns3_nic_netdev_ops; 4544 SET_NETDEV_DEV(netdev, &pdev->dev); 4545 hns3_ethtool_set_ops(netdev); 4546 4547 /* Carrier off reporting is important to ethtool even BEFORE open */ 4548 netif_carrier_off(netdev); 4549 4550 ret = hns3_get_ring_config(priv); 4551 if (ret) { 4552 ret = -ENOMEM; 4553 goto out_get_ring_cfg; 4554 } 4555 4556 hns3_nic_init_coal_cfg(priv); 4557 4558 ret = hns3_nic_alloc_vector_data(priv); 4559 if (ret) { 4560 ret = -ENOMEM; 4561 goto out_alloc_vector_data; 4562 } 4563 4564 ret = hns3_nic_init_vector_data(priv); 4565 if (ret) { 4566 ret = -ENOMEM; 4567 goto out_init_vector_data; 4568 } 4569 4570 ret = hns3_init_all_ring(priv); 4571 if (ret) { 4572 ret = -ENOMEM; 4573 goto out_init_ring; 4574 } 4575 4576 ret = hns3_init_phy(netdev); 4577 if (ret) 4578 goto out_init_phy; 4579 4580 /* the device can work without cpu rmap, only aRFS needs it */ 4581 ret = hns3_set_rx_cpu_rmap(netdev); 4582 if (ret) 4583 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4584 4585 ret = hns3_nic_init_irq(priv); 4586 if (ret) { 4587 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4588 hns3_free_rx_cpu_rmap(netdev); 4589 goto out_init_irq_fail; 4590 } 4591 4592 ret = hns3_client_start(handle); 4593 if (ret) { 4594 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4595 goto out_client_start; 4596 } 4597 4598 hns3_dcbnl_setup(handle); 4599 4600 ret = hns3_dbg_init(handle); 4601 if (ret) { 4602 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 4603 ret); 4604 goto out_client_start; 4605 } 4606 4607 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 4608 4609 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 4610 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 4611 4612 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 4613 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 4614 4615 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4616 4617 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 4618 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 4619 4620 ret = register_netdev(netdev); 4621 if (ret) { 4622 dev_err(priv->dev, "probe register netdev fail!\n"); 4623 goto out_reg_netdev_fail; 4624 } 4625 4626 if (netif_msg_drv(handle)) 4627 hns3_info_show(priv); 4628 4629 return ret; 4630 4631 out_reg_netdev_fail: 4632 hns3_dbg_uninit(handle); 4633 out_client_start: 4634 hns3_free_rx_cpu_rmap(netdev); 4635 hns3_nic_uninit_irq(priv); 4636 out_init_irq_fail: 4637 hns3_uninit_phy(netdev); 4638 out_init_phy: 4639 hns3_uninit_all_ring(priv); 4640 out_init_ring: 4641 hns3_nic_uninit_vector_data(priv); 4642 out_init_vector_data: 4643 hns3_nic_dealloc_vector_data(priv); 4644 out_alloc_vector_data: 4645 priv->ring = NULL; 4646 out_get_ring_cfg: 4647 priv->ae_handle = NULL; 4648 free_netdev(netdev); 4649 return ret; 4650 } 4651 4652 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4653 { 4654 struct net_device *netdev = handle->kinfo.netdev; 4655 struct hns3_nic_priv *priv = netdev_priv(netdev); 4656 4657 if (netdev->reg_state != NETREG_UNINITIALIZED) 4658 unregister_netdev(netdev); 4659 4660 hns3_client_stop(handle); 4661 4662 hns3_uninit_phy(netdev); 4663 4664 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4665 netdev_warn(netdev, "already uninitialized\n"); 4666 goto out_netdev_free; 4667 } 4668 4669 hns3_free_rx_cpu_rmap(netdev); 4670 4671 hns3_nic_uninit_irq(priv); 4672 4673 hns3_clear_all_ring(handle, true); 4674 4675 hns3_nic_uninit_vector_data(priv); 4676 4677 hns3_nic_dealloc_vector_data(priv); 4678 4679 hns3_uninit_all_ring(priv); 4680 4681 hns3_put_ring_config(priv); 4682 4683 out_netdev_free: 4684 hns3_dbg_uninit(handle); 4685 free_netdev(netdev); 4686 } 4687 4688 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4689 { 4690 struct net_device *netdev = handle->kinfo.netdev; 4691 4692 if (!netdev) 4693 return; 4694 4695 if (linkup) { 4696 netif_tx_wake_all_queues(netdev); 4697 netif_carrier_on(netdev); 4698 if (netif_msg_link(handle)) 4699 netdev_info(netdev, "link up\n"); 4700 } else { 4701 netif_carrier_off(netdev); 4702 netif_tx_stop_all_queues(netdev); 4703 if (netif_msg_link(handle)) 4704 netdev_info(netdev, "link down\n"); 4705 } 4706 } 4707 4708 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4709 { 4710 while (ring->next_to_clean != ring->next_to_use) { 4711 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4712 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4713 ring_ptr_move_fw(ring, next_to_clean); 4714 } 4715 4716 ring->pending_buf = 0; 4717 } 4718 4719 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4720 { 4721 struct hns3_desc_cb res_cbs; 4722 int ret; 4723 4724 while (ring->next_to_use != ring->next_to_clean) { 4725 /* When a buffer is not reused, it's memory has been 4726 * freed in hns3_handle_rx_bd or will be freed by 4727 * stack, so we need to replace the buffer here. 4728 */ 4729 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4730 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4731 if (ret) { 4732 u64_stats_update_begin(&ring->syncp); 4733 ring->stats.sw_err_cnt++; 4734 u64_stats_update_end(&ring->syncp); 4735 /* if alloc new buffer fail, exit directly 4736 * and reclear in up flow. 4737 */ 4738 netdev_warn(ring_to_netdev(ring), 4739 "reserve buffer map failed, ret = %d\n", 4740 ret); 4741 return ret; 4742 } 4743 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4744 } 4745 ring_ptr_move_fw(ring, next_to_use); 4746 } 4747 4748 /* Free the pending skb in rx ring */ 4749 if (ring->skb) { 4750 dev_kfree_skb_any(ring->skb); 4751 ring->skb = NULL; 4752 ring->pending_buf = 0; 4753 } 4754 4755 return 0; 4756 } 4757 4758 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4759 { 4760 while (ring->next_to_use != ring->next_to_clean) { 4761 /* When a buffer is not reused, it's memory has been 4762 * freed in hns3_handle_rx_bd or will be freed by 4763 * stack, so only need to unmap the buffer here. 4764 */ 4765 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4766 hns3_unmap_buffer(ring, 4767 &ring->desc_cb[ring->next_to_use]); 4768 ring->desc_cb[ring->next_to_use].dma = 0; 4769 } 4770 4771 ring_ptr_move_fw(ring, next_to_use); 4772 } 4773 } 4774 4775 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4776 { 4777 struct net_device *ndev = h->kinfo.netdev; 4778 struct hns3_nic_priv *priv = netdev_priv(ndev); 4779 u32 i; 4780 4781 for (i = 0; i < h->kinfo.num_tqps; i++) { 4782 struct hns3_enet_ring *ring; 4783 4784 ring = &priv->ring[i]; 4785 hns3_clear_tx_ring(ring); 4786 4787 ring = &priv->ring[i + h->kinfo.num_tqps]; 4788 /* Continue to clear other rings even if clearing some 4789 * rings failed. 4790 */ 4791 if (force) 4792 hns3_force_clear_rx_ring(ring); 4793 else 4794 hns3_clear_rx_ring(ring); 4795 } 4796 } 4797 4798 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4799 { 4800 struct net_device *ndev = h->kinfo.netdev; 4801 struct hns3_nic_priv *priv = netdev_priv(ndev); 4802 struct hns3_enet_ring *rx_ring; 4803 int i, j; 4804 int ret; 4805 4806 ret = h->ae_algo->ops->reset_queue(h); 4807 if (ret) 4808 return ret; 4809 4810 for (i = 0; i < h->kinfo.num_tqps; i++) { 4811 hns3_init_ring_hw(&priv->ring[i]); 4812 4813 /* We need to clear tx ring here because self test will 4814 * use the ring and will not run down before up 4815 */ 4816 hns3_clear_tx_ring(&priv->ring[i]); 4817 priv->ring[i].next_to_clean = 0; 4818 priv->ring[i].next_to_use = 0; 4819 priv->ring[i].last_to_use = 0; 4820 4821 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4822 hns3_init_ring_hw(rx_ring); 4823 ret = hns3_clear_rx_ring(rx_ring); 4824 if (ret) 4825 return ret; 4826 4827 /* We can not know the hardware head and tail when this 4828 * function is called in reset flow, so we reuse all desc. 4829 */ 4830 for (j = 0; j < rx_ring->desc_num; j++) 4831 hns3_reuse_buffer(rx_ring, j); 4832 4833 rx_ring->next_to_clean = 0; 4834 rx_ring->next_to_use = 0; 4835 } 4836 4837 hns3_init_tx_ring_tc(priv); 4838 4839 return 0; 4840 } 4841 4842 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4843 { 4844 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4845 struct net_device *ndev = kinfo->netdev; 4846 struct hns3_nic_priv *priv = netdev_priv(ndev); 4847 4848 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4849 return 0; 4850 4851 if (!netif_running(ndev)) 4852 return 0; 4853 4854 return hns3_nic_net_stop(ndev); 4855 } 4856 4857 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4858 { 4859 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4860 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4861 int ret = 0; 4862 4863 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4864 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 4865 return -EFAULT; 4866 } 4867 4868 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4869 4870 if (netif_running(kinfo->netdev)) { 4871 ret = hns3_nic_net_open(kinfo->netdev); 4872 if (ret) { 4873 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4874 netdev_err(kinfo->netdev, 4875 "net up fail, ret=%d!\n", ret); 4876 return ret; 4877 } 4878 } 4879 4880 return ret; 4881 } 4882 4883 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4884 { 4885 struct net_device *netdev = handle->kinfo.netdev; 4886 struct hns3_nic_priv *priv = netdev_priv(netdev); 4887 int ret; 4888 4889 /* Carrier off reporting is important to ethtool even BEFORE open */ 4890 netif_carrier_off(netdev); 4891 4892 ret = hns3_get_ring_config(priv); 4893 if (ret) 4894 return ret; 4895 4896 ret = hns3_nic_alloc_vector_data(priv); 4897 if (ret) 4898 goto err_put_ring; 4899 4900 ret = hns3_nic_init_vector_data(priv); 4901 if (ret) 4902 goto err_dealloc_vector; 4903 4904 ret = hns3_init_all_ring(priv); 4905 if (ret) 4906 goto err_uninit_vector; 4907 4908 /* the device can work without cpu rmap, only aRFS needs it */ 4909 ret = hns3_set_rx_cpu_rmap(netdev); 4910 if (ret) 4911 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4912 4913 ret = hns3_nic_init_irq(priv); 4914 if (ret) { 4915 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4916 hns3_free_rx_cpu_rmap(netdev); 4917 goto err_init_irq_fail; 4918 } 4919 4920 if (!hns3_is_phys_func(handle->pdev)) 4921 hns3_init_mac_addr(netdev); 4922 4923 ret = hns3_client_start(handle); 4924 if (ret) { 4925 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4926 goto err_client_start_fail; 4927 } 4928 4929 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4930 4931 return ret; 4932 4933 err_client_start_fail: 4934 hns3_free_rx_cpu_rmap(netdev); 4935 hns3_nic_uninit_irq(priv); 4936 err_init_irq_fail: 4937 hns3_uninit_all_ring(priv); 4938 err_uninit_vector: 4939 hns3_nic_uninit_vector_data(priv); 4940 err_dealloc_vector: 4941 hns3_nic_dealloc_vector_data(priv); 4942 err_put_ring: 4943 hns3_put_ring_config(priv); 4944 4945 return ret; 4946 } 4947 4948 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4949 { 4950 struct net_device *netdev = handle->kinfo.netdev; 4951 struct hns3_nic_priv *priv = netdev_priv(netdev); 4952 4953 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4954 netdev_warn(netdev, "already uninitialized\n"); 4955 return 0; 4956 } 4957 4958 hns3_free_rx_cpu_rmap(netdev); 4959 hns3_nic_uninit_irq(priv); 4960 hns3_clear_all_ring(handle, true); 4961 hns3_reset_tx_queue(priv->ae_handle); 4962 4963 hns3_nic_uninit_vector_data(priv); 4964 4965 hns3_nic_dealloc_vector_data(priv); 4966 4967 hns3_uninit_all_ring(priv); 4968 4969 hns3_put_ring_config(priv); 4970 4971 return 0; 4972 } 4973 4974 static int hns3_reset_notify(struct hnae3_handle *handle, 4975 enum hnae3_reset_notify_type type) 4976 { 4977 int ret = 0; 4978 4979 switch (type) { 4980 case HNAE3_UP_CLIENT: 4981 ret = hns3_reset_notify_up_enet(handle); 4982 break; 4983 case HNAE3_DOWN_CLIENT: 4984 ret = hns3_reset_notify_down_enet(handle); 4985 break; 4986 case HNAE3_INIT_CLIENT: 4987 ret = hns3_reset_notify_init_enet(handle); 4988 break; 4989 case HNAE3_UNINIT_CLIENT: 4990 ret = hns3_reset_notify_uninit_enet(handle); 4991 break; 4992 default: 4993 break; 4994 } 4995 4996 return ret; 4997 } 4998 4999 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5000 bool rxfh_configured) 5001 { 5002 int ret; 5003 5004 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5005 rxfh_configured); 5006 if (ret) { 5007 dev_err(&handle->pdev->dev, 5008 "Change tqp num(%u) fail.\n", new_tqp_num); 5009 return ret; 5010 } 5011 5012 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5013 if (ret) 5014 return ret; 5015 5016 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5017 if (ret) 5018 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5019 5020 return ret; 5021 } 5022 5023 int hns3_set_channels(struct net_device *netdev, 5024 struct ethtool_channels *ch) 5025 { 5026 struct hnae3_handle *h = hns3_get_handle(netdev); 5027 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5028 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5029 u32 new_tqp_num = ch->combined_count; 5030 u16 org_tqp_num; 5031 int ret; 5032 5033 if (hns3_nic_resetting(netdev)) 5034 return -EBUSY; 5035 5036 if (ch->rx_count || ch->tx_count) 5037 return -EINVAL; 5038 5039 if (kinfo->tc_info.mqprio_active) { 5040 dev_err(&netdev->dev, 5041 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5042 return -EINVAL; 5043 } 5044 5045 if (new_tqp_num > hns3_get_max_available_channels(h) || 5046 new_tqp_num < 1) { 5047 dev_err(&netdev->dev, 5048 "Change tqps fail, the tqp range is from 1 to %u", 5049 hns3_get_max_available_channels(h)); 5050 return -EINVAL; 5051 } 5052 5053 if (kinfo->rss_size == new_tqp_num) 5054 return 0; 5055 5056 netif_dbg(h, drv, netdev, 5057 "set channels: tqp_num=%u, rxfh=%d\n", 5058 new_tqp_num, rxfh_configured); 5059 5060 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5061 if (ret) 5062 return ret; 5063 5064 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5065 if (ret) 5066 return ret; 5067 5068 org_tqp_num = h->kinfo.num_tqps; 5069 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5070 if (ret) { 5071 int ret1; 5072 5073 netdev_warn(netdev, 5074 "Change channels fail, revert to old value\n"); 5075 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5076 if (ret1) { 5077 netdev_err(netdev, 5078 "revert to old channel fail\n"); 5079 return ret1; 5080 } 5081 5082 return ret; 5083 } 5084 5085 return 0; 5086 } 5087 5088 static const struct hns3_hw_error_info hns3_hw_err[] = { 5089 { .type = HNAE3_PPU_POISON_ERROR, 5090 .msg = "PPU poison" }, 5091 { .type = HNAE3_CMDQ_ECC_ERROR, 5092 .msg = "IMP CMDQ error" }, 5093 { .type = HNAE3_IMP_RD_POISON_ERROR, 5094 .msg = "IMP RD poison" }, 5095 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5096 .msg = "ROCEE AXI RESP error" }, 5097 }; 5098 5099 static void hns3_process_hw_error(struct hnae3_handle *handle, 5100 enum hnae3_hw_error_type type) 5101 { 5102 int i; 5103 5104 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5105 if (hns3_hw_err[i].type == type) { 5106 dev_err(&handle->pdev->dev, "Detected %s!\n", 5107 hns3_hw_err[i].msg); 5108 break; 5109 } 5110 } 5111 } 5112 5113 static const struct hnae3_client_ops client_ops = { 5114 .init_instance = hns3_client_init, 5115 .uninit_instance = hns3_client_uninit, 5116 .link_status_change = hns3_link_status_change, 5117 .reset_notify = hns3_reset_notify, 5118 .process_hw_error = hns3_process_hw_error, 5119 }; 5120 5121 /* hns3_init_module - Driver registration routine 5122 * hns3_init_module is the first routine called when the driver is 5123 * loaded. All it does is register with the PCI subsystem. 5124 */ 5125 static int __init hns3_init_module(void) 5126 { 5127 int ret; 5128 5129 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5130 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5131 5132 client.type = HNAE3_CLIENT_KNIC; 5133 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5134 hns3_driver_name); 5135 5136 client.ops = &client_ops; 5137 5138 INIT_LIST_HEAD(&client.node); 5139 5140 hns3_dbg_register_debugfs(hns3_driver_name); 5141 5142 ret = hnae3_register_client(&client); 5143 if (ret) 5144 goto err_reg_client; 5145 5146 ret = pci_register_driver(&hns3_driver); 5147 if (ret) 5148 goto err_reg_driver; 5149 5150 return ret; 5151 5152 err_reg_driver: 5153 hnae3_unregister_client(&client); 5154 err_reg_client: 5155 hns3_dbg_unregister_debugfs(); 5156 return ret; 5157 } 5158 module_init(hns3_init_module); 5159 5160 /* hns3_exit_module - Driver exit cleanup routine 5161 * hns3_exit_module is called just before the driver is removed 5162 * from memory. 5163 */ 5164 static void __exit hns3_exit_module(void) 5165 { 5166 pci_unregister_driver(&hns3_driver); 5167 hnae3_unregister_client(&client); 5168 hns3_dbg_unregister_debugfs(); 5169 } 5170 module_exit(hns3_exit_module); 5171 5172 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5173 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5174 MODULE_LICENSE("GPL"); 5175 MODULE_ALIAS("pci:hns-nic"); 5176