1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/ip.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <net/gre.h>
19 #include <net/ip6_checksum.h>
20 #include <net/pkt_cls.h>
21 #include <net/tcp.h>
22 #include <net/vxlan.h>
23 
24 #include "hnae3.h"
25 #include "hns3_enet.h"
26 /* All hns3 tracepoints are defined by the include below, which
27  * must be included exactly once across the whole kernel with
28  * CREATE_TRACE_POINTS defined
29  */
30 #define CREATE_TRACE_POINTS
31 #include "hns3_trace.h"
32 
33 #define hns3_set_field(origin, shift, val)	((origin) |= ((val) << (shift)))
34 #define hns3_tx_bd_count(S)	DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
35 
36 #define hns3_rl_err(fmt, ...)						\
37 	do {								\
38 		if (net_ratelimit())					\
39 			netdev_err(fmt, ##__VA_ARGS__);			\
40 	} while (0)
41 
42 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
43 
44 static const char hns3_driver_name[] = "hns3";
45 static const char hns3_driver_string[] =
46 			"Hisilicon Ethernet Network Driver for Hip08 Family";
47 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
48 static struct hnae3_client client;
49 
50 static int debug = -1;
51 module_param(debug, int, 0);
52 MODULE_PARM_DESC(debug, " Network interface message level setting");
53 
54 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
55 			   NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
56 
57 #define HNS3_INNER_VLAN_TAG	1
58 #define HNS3_OUTER_VLAN_TAG	2
59 
60 #define HNS3_MIN_TX_LEN		33U
61 
62 /* hns3_pci_tbl - PCI Device ID Table
63  *
64  * Last entry must be all 0s
65  *
66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67  *   Class, Class Mask, private data (not used) }
68  */
69 static const struct pci_device_id hns3_pci_tbl[] = {
70 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
71 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
72 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
73 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
74 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
75 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
76 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
77 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
78 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
79 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
80 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
81 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
82 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
83 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
84 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
85 	/* required last entry */
86 	{0, }
87 };
88 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
89 
90 static irqreturn_t hns3_irq_handle(int irq, void *vector)
91 {
92 	struct hns3_enet_tqp_vector *tqp_vector = vector;
93 
94 	napi_schedule_irqoff(&tqp_vector->napi);
95 
96 	return IRQ_HANDLED;
97 }
98 
99 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
100 {
101 	struct hns3_enet_tqp_vector *tqp_vectors;
102 	unsigned int i;
103 
104 	for (i = 0; i < priv->vector_num; i++) {
105 		tqp_vectors = &priv->tqp_vector[i];
106 
107 		if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
108 			continue;
109 
110 		/* clear the affinity mask */
111 		irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
112 
113 		/* release the irq resource */
114 		free_irq(tqp_vectors->vector_irq, tqp_vectors);
115 		tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
116 	}
117 }
118 
119 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
120 {
121 	struct hns3_enet_tqp_vector *tqp_vectors;
122 	int txrx_int_idx = 0;
123 	int rx_int_idx = 0;
124 	int tx_int_idx = 0;
125 	unsigned int i;
126 	int ret;
127 
128 	for (i = 0; i < priv->vector_num; i++) {
129 		tqp_vectors = &priv->tqp_vector[i];
130 
131 		if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
132 			continue;
133 
134 		if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
135 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
136 				 "%s-%s-%s-%d", hns3_driver_name,
137 				 pci_name(priv->ae_handle->pdev),
138 				 "TxRx", txrx_int_idx++);
139 			txrx_int_idx++;
140 		} else if (tqp_vectors->rx_group.ring) {
141 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
142 				 "%s-%s-%s-%d", hns3_driver_name,
143 				 pci_name(priv->ae_handle->pdev),
144 				 "Rx", rx_int_idx++);
145 		} else if (tqp_vectors->tx_group.ring) {
146 			snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
147 				 "%s-%s-%s-%d", hns3_driver_name,
148 				 pci_name(priv->ae_handle->pdev),
149 				 "Tx", tx_int_idx++);
150 		} else {
151 			/* Skip this unused q_vector */
152 			continue;
153 		}
154 
155 		tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
156 
157 		ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
158 				  tqp_vectors->name, tqp_vectors);
159 		if (ret) {
160 			netdev_err(priv->netdev, "request irq(%d) fail\n",
161 				   tqp_vectors->vector_irq);
162 			hns3_nic_uninit_irq(priv);
163 			return ret;
164 		}
165 
166 		disable_irq(tqp_vectors->vector_irq);
167 
168 		irq_set_affinity_hint(tqp_vectors->vector_irq,
169 				      &tqp_vectors->affinity_mask);
170 
171 		tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
172 	}
173 
174 	return 0;
175 }
176 
177 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
178 				 u32 mask_en)
179 {
180 	writel(mask_en, tqp_vector->mask_addr);
181 }
182 
183 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
184 {
185 	napi_enable(&tqp_vector->napi);
186 	enable_irq(tqp_vector->vector_irq);
187 
188 	/* enable vector */
189 	hns3_mask_vector_irq(tqp_vector, 1);
190 }
191 
192 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
193 {
194 	/* disable vector */
195 	hns3_mask_vector_irq(tqp_vector, 0);
196 
197 	disable_irq(tqp_vector->vector_irq);
198 	napi_disable(&tqp_vector->napi);
199 }
200 
201 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
202 				 u32 rl_value)
203 {
204 	u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
205 
206 	/* this defines the configuration for RL (Interrupt Rate Limiter).
207 	 * Rl defines rate of interrupts i.e. number of interrupts-per-second
208 	 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
209 	 */
210 
211 	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
212 	    !tqp_vector->rx_group.coal.gl_adapt_enable)
213 		/* According to the hardware, the range of rl_reg is
214 		 * 0-59 and the unit is 4.
215 		 */
216 		rl_reg |=  HNS3_INT_RL_ENABLE_MASK;
217 
218 	writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
219 }
220 
221 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
222 				    u32 gl_value)
223 {
224 	u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225 
226 	writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
227 }
228 
229 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
230 				    u32 gl_value)
231 {
232 	u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
233 
234 	writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
235 }
236 
237 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
238 				   struct hns3_nic_priv *priv)
239 {
240 	/* initialize the configuration for interrupt coalescing.
241 	 * 1. GL (Interrupt Gap Limiter)
242 	 * 2. RL (Interrupt Rate Limiter)
243 	 *
244 	 * Default: enable interrupt coalescing self-adaptive and GL
245 	 */
246 	tqp_vector->tx_group.coal.gl_adapt_enable = 1;
247 	tqp_vector->rx_group.coal.gl_adapt_enable = 1;
248 
249 	tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
250 	tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
251 
252 	tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
253 	tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
254 }
255 
256 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
257 				      struct hns3_nic_priv *priv)
258 {
259 	struct hnae3_handle *h = priv->ae_handle;
260 
261 	hns3_set_vector_coalesce_tx_gl(tqp_vector,
262 				       tqp_vector->tx_group.coal.int_gl);
263 	hns3_set_vector_coalesce_rx_gl(tqp_vector,
264 				       tqp_vector->rx_group.coal.int_gl);
265 	hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
266 }
267 
268 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
269 {
270 	struct hnae3_handle *h = hns3_get_handle(netdev);
271 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
272 	unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
273 	int i, ret;
274 
275 	if (kinfo->num_tc <= 1) {
276 		netdev_reset_tc(netdev);
277 	} else {
278 		ret = netdev_set_num_tc(netdev, kinfo->num_tc);
279 		if (ret) {
280 			netdev_err(netdev,
281 				   "netdev_set_num_tc fail, ret=%d!\n", ret);
282 			return ret;
283 		}
284 
285 		for (i = 0; i < HNAE3_MAX_TC; i++) {
286 			if (!kinfo->tc_info[i].enable)
287 				continue;
288 
289 			netdev_set_tc_queue(netdev,
290 					    kinfo->tc_info[i].tc,
291 					    kinfo->tc_info[i].tqp_count,
292 					    kinfo->tc_info[i].tqp_offset);
293 		}
294 	}
295 
296 	ret = netif_set_real_num_tx_queues(netdev, queue_size);
297 	if (ret) {
298 		netdev_err(netdev,
299 			   "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
300 		return ret;
301 	}
302 
303 	ret = netif_set_real_num_rx_queues(netdev, queue_size);
304 	if (ret) {
305 		netdev_err(netdev,
306 			   "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
307 		return ret;
308 	}
309 
310 	return 0;
311 }
312 
313 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
314 {
315 	u16 alloc_tqps, max_rss_size, rss_size;
316 
317 	h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
318 	rss_size = alloc_tqps / h->kinfo.num_tc;
319 
320 	return min_t(u16, rss_size, max_rss_size);
321 }
322 
323 static void hns3_tqp_enable(struct hnae3_queue *tqp)
324 {
325 	u32 rcb_reg;
326 
327 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
328 	rcb_reg |= BIT(HNS3_RING_EN_B);
329 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330 }
331 
332 static void hns3_tqp_disable(struct hnae3_queue *tqp)
333 {
334 	u32 rcb_reg;
335 
336 	rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
337 	rcb_reg &= ~BIT(HNS3_RING_EN_B);
338 	hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
339 }
340 
341 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
342 {
343 #ifdef CONFIG_RFS_ACCEL
344 	free_irq_cpu_rmap(netdev->rx_cpu_rmap);
345 	netdev->rx_cpu_rmap = NULL;
346 #endif
347 }
348 
349 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
350 {
351 #ifdef CONFIG_RFS_ACCEL
352 	struct hns3_nic_priv *priv = netdev_priv(netdev);
353 	struct hns3_enet_tqp_vector *tqp_vector;
354 	int i, ret;
355 
356 	if (!netdev->rx_cpu_rmap) {
357 		netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
358 		if (!netdev->rx_cpu_rmap)
359 			return -ENOMEM;
360 	}
361 
362 	for (i = 0; i < priv->vector_num; i++) {
363 		tqp_vector = &priv->tqp_vector[i];
364 		ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
365 				       tqp_vector->vector_irq);
366 		if (ret) {
367 			hns3_free_rx_cpu_rmap(netdev);
368 			return ret;
369 		}
370 	}
371 #endif
372 	return 0;
373 }
374 
375 static int hns3_nic_net_up(struct net_device *netdev)
376 {
377 	struct hns3_nic_priv *priv = netdev_priv(netdev);
378 	struct hnae3_handle *h = priv->ae_handle;
379 	int i, j;
380 	int ret;
381 
382 	ret = hns3_nic_reset_all_ring(h);
383 	if (ret)
384 		return ret;
385 
386 	clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
387 
388 	/* enable the vectors */
389 	for (i = 0; i < priv->vector_num; i++)
390 		hns3_vector_enable(&priv->tqp_vector[i]);
391 
392 	/* enable rcb */
393 	for (j = 0; j < h->kinfo.num_tqps; j++)
394 		hns3_tqp_enable(h->kinfo.tqp[j]);
395 
396 	/* start the ae_dev */
397 	ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
398 	if (ret) {
399 		set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
400 		while (j--)
401 			hns3_tqp_disable(h->kinfo.tqp[j]);
402 
403 		for (j = i - 1; j >= 0; j--)
404 			hns3_vector_disable(&priv->tqp_vector[j]);
405 	}
406 
407 	return ret;
408 }
409 
410 static void hns3_config_xps(struct hns3_nic_priv *priv)
411 {
412 	int i;
413 
414 	for (i = 0; i < priv->vector_num; i++) {
415 		struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
416 		struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
417 
418 		while (ring) {
419 			int ret;
420 
421 			ret = netif_set_xps_queue(priv->netdev,
422 						  &tqp_vector->affinity_mask,
423 						  ring->tqp->tqp_index);
424 			if (ret)
425 				netdev_warn(priv->netdev,
426 					    "set xps queue failed: %d", ret);
427 
428 			ring = ring->next;
429 		}
430 	}
431 }
432 
433 static int hns3_nic_net_open(struct net_device *netdev)
434 {
435 	struct hns3_nic_priv *priv = netdev_priv(netdev);
436 	struct hnae3_handle *h = hns3_get_handle(netdev);
437 	struct hnae3_knic_private_info *kinfo;
438 	int i, ret;
439 
440 	if (hns3_nic_resetting(netdev))
441 		return -EBUSY;
442 
443 	netif_carrier_off(netdev);
444 
445 	ret = hns3_nic_set_real_num_queue(netdev);
446 	if (ret)
447 		return ret;
448 
449 	ret = hns3_nic_net_up(netdev);
450 	if (ret) {
451 		netdev_err(netdev, "net up fail, ret=%d!\n", ret);
452 		return ret;
453 	}
454 
455 	kinfo = &h->kinfo;
456 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
457 		netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
458 
459 	if (h->ae_algo->ops->set_timer_task)
460 		h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
461 
462 	hns3_config_xps(priv);
463 
464 	netif_dbg(h, drv, netdev, "net open\n");
465 
466 	return 0;
467 }
468 
469 static void hns3_reset_tx_queue(struct hnae3_handle *h)
470 {
471 	struct net_device *ndev = h->kinfo.netdev;
472 	struct hns3_nic_priv *priv = netdev_priv(ndev);
473 	struct netdev_queue *dev_queue;
474 	u32 i;
475 
476 	for (i = 0; i < h->kinfo.num_tqps; i++) {
477 		dev_queue = netdev_get_tx_queue(ndev,
478 						priv->ring[i].queue_index);
479 		netdev_tx_reset_queue(dev_queue);
480 	}
481 }
482 
483 static void hns3_nic_net_down(struct net_device *netdev)
484 {
485 	struct hns3_nic_priv *priv = netdev_priv(netdev);
486 	struct hnae3_handle *h = hns3_get_handle(netdev);
487 	const struct hnae3_ae_ops *ops;
488 	int i;
489 
490 	/* disable vectors */
491 	for (i = 0; i < priv->vector_num; i++)
492 		hns3_vector_disable(&priv->tqp_vector[i]);
493 
494 	/* disable rcb */
495 	for (i = 0; i < h->kinfo.num_tqps; i++)
496 		hns3_tqp_disable(h->kinfo.tqp[i]);
497 
498 	/* stop ae_dev */
499 	ops = priv->ae_handle->ae_algo->ops;
500 	if (ops->stop)
501 		ops->stop(priv->ae_handle);
502 
503 	/* delay ring buffer clearing to hns3_reset_notify_uninit_enet
504 	 * during reset process, because driver may not be able
505 	 * to disable the ring through firmware when downing the netdev.
506 	 */
507 	if (!hns3_nic_resetting(netdev))
508 		hns3_clear_all_ring(priv->ae_handle, false);
509 
510 	hns3_reset_tx_queue(priv->ae_handle);
511 }
512 
513 static int hns3_nic_net_stop(struct net_device *netdev)
514 {
515 	struct hns3_nic_priv *priv = netdev_priv(netdev);
516 	struct hnae3_handle *h = hns3_get_handle(netdev);
517 
518 	if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
519 		return 0;
520 
521 	netif_dbg(h, drv, netdev, "net stop\n");
522 
523 	if (h->ae_algo->ops->set_timer_task)
524 		h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
525 
526 	netif_tx_stop_all_queues(netdev);
527 	netif_carrier_off(netdev);
528 
529 	hns3_nic_net_down(netdev);
530 
531 	return 0;
532 }
533 
534 static int hns3_nic_uc_sync(struct net_device *netdev,
535 			    const unsigned char *addr)
536 {
537 	struct hnae3_handle *h = hns3_get_handle(netdev);
538 
539 	if (h->ae_algo->ops->add_uc_addr)
540 		return h->ae_algo->ops->add_uc_addr(h, addr);
541 
542 	return 0;
543 }
544 
545 static int hns3_nic_uc_unsync(struct net_device *netdev,
546 			      const unsigned char *addr)
547 {
548 	struct hnae3_handle *h = hns3_get_handle(netdev);
549 
550 	/* need ignore the request of removing device address, because
551 	 * we store the device address and other addresses of uc list
552 	 * in the function's mac filter list.
553 	 */
554 	if (ether_addr_equal(addr, netdev->dev_addr))
555 		return 0;
556 
557 	if (h->ae_algo->ops->rm_uc_addr)
558 		return h->ae_algo->ops->rm_uc_addr(h, addr);
559 
560 	return 0;
561 }
562 
563 static int hns3_nic_mc_sync(struct net_device *netdev,
564 			    const unsigned char *addr)
565 {
566 	struct hnae3_handle *h = hns3_get_handle(netdev);
567 
568 	if (h->ae_algo->ops->add_mc_addr)
569 		return h->ae_algo->ops->add_mc_addr(h, addr);
570 
571 	return 0;
572 }
573 
574 static int hns3_nic_mc_unsync(struct net_device *netdev,
575 			      const unsigned char *addr)
576 {
577 	struct hnae3_handle *h = hns3_get_handle(netdev);
578 
579 	if (h->ae_algo->ops->rm_mc_addr)
580 		return h->ae_algo->ops->rm_mc_addr(h, addr);
581 
582 	return 0;
583 }
584 
585 static u8 hns3_get_netdev_flags(struct net_device *netdev)
586 {
587 	u8 flags = 0;
588 
589 	if (netdev->flags & IFF_PROMISC) {
590 		flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
591 	} else {
592 		flags |= HNAE3_VLAN_FLTR;
593 		if (netdev->flags & IFF_ALLMULTI)
594 			flags |= HNAE3_USER_MPE;
595 	}
596 
597 	return flags;
598 }
599 
600 static void hns3_nic_set_rx_mode(struct net_device *netdev)
601 {
602 	struct hnae3_handle *h = hns3_get_handle(netdev);
603 	u8 new_flags;
604 
605 	new_flags = hns3_get_netdev_flags(netdev);
606 
607 	__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
608 	__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
609 
610 	/* User mode Promisc mode enable and vlan filtering is disabled to
611 	 * let all packets in.
612 	 */
613 	h->netdev_flags = new_flags;
614 	hns3_request_update_promisc_mode(h);
615 }
616 
617 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
618 {
619 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
620 
621 	if (ops->request_update_promisc_mode)
622 		ops->request_update_promisc_mode(handle);
623 }
624 
625 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
626 {
627 	struct hns3_nic_priv *priv = netdev_priv(netdev);
628 	struct hnae3_handle *h = priv->ae_handle;
629 
630 	if (h->ae_algo->ops->set_promisc_mode) {
631 		return h->ae_algo->ops->set_promisc_mode(h,
632 						promisc_flags & HNAE3_UPE,
633 						promisc_flags & HNAE3_MPE);
634 	}
635 
636 	return 0;
637 }
638 
639 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
640 {
641 	struct hns3_nic_priv *priv = netdev_priv(netdev);
642 	struct hnae3_handle *h = priv->ae_handle;
643 	bool last_state;
644 
645 	if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
646 		last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
647 		if (enable != last_state) {
648 			netdev_info(netdev,
649 				    "%s vlan filter\n",
650 				    enable ? "enable" : "disable");
651 			h->ae_algo->ops->enable_vlan_filter(h, enable);
652 		}
653 	}
654 }
655 
656 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
657 			u16 *mss, u32 *type_cs_vlan_tso)
658 {
659 	u32 l4_offset, hdr_len;
660 	union l3_hdr_info l3;
661 	union l4_hdr_info l4;
662 	u32 l4_paylen;
663 	int ret;
664 
665 	if (!skb_is_gso(skb))
666 		return 0;
667 
668 	ret = skb_cow_head(skb, 0);
669 	if (unlikely(ret < 0))
670 		return ret;
671 
672 	l3.hdr = skb_network_header(skb);
673 	l4.hdr = skb_transport_header(skb);
674 
675 	/* Software should clear the IPv4's checksum field when tso is
676 	 * needed.
677 	 */
678 	if (l3.v4->version == 4)
679 		l3.v4->check = 0;
680 
681 	/* tunnel packet */
682 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
683 					 SKB_GSO_GRE_CSUM |
684 					 SKB_GSO_UDP_TUNNEL |
685 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
686 		if ((!(skb_shinfo(skb)->gso_type &
687 		    SKB_GSO_PARTIAL)) &&
688 		    (skb_shinfo(skb)->gso_type &
689 		    SKB_GSO_UDP_TUNNEL_CSUM)) {
690 			/* Software should clear the udp's checksum
691 			 * field when tso is needed.
692 			 */
693 			l4.udp->check = 0;
694 		}
695 		/* reset l3&l4 pointers from outer to inner headers */
696 		l3.hdr = skb_inner_network_header(skb);
697 		l4.hdr = skb_inner_transport_header(skb);
698 
699 		/* Software should clear the IPv4's checksum field when
700 		 * tso is needed.
701 		 */
702 		if (l3.v4->version == 4)
703 			l3.v4->check = 0;
704 	}
705 
706 	/* normal or tunnel packet */
707 	l4_offset = l4.hdr - skb->data;
708 	hdr_len = (l4.tcp->doff << 2) + l4_offset;
709 
710 	/* remove payload length from inner pseudo checksum when tso */
711 	l4_paylen = skb->len - l4_offset;
712 	csum_replace_by_diff(&l4.tcp->check,
713 			     (__force __wsum)htonl(l4_paylen));
714 
715 	/* find the txbd field values */
716 	*paylen = skb->len - hdr_len;
717 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
718 
719 	/* get MSS for TSO */
720 	*mss = skb_shinfo(skb)->gso_size;
721 
722 	trace_hns3_tso(skb);
723 
724 	return 0;
725 }
726 
727 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
728 				u8 *il4_proto)
729 {
730 	union l3_hdr_info l3;
731 	unsigned char *l4_hdr;
732 	unsigned char *exthdr;
733 	u8 l4_proto_tmp;
734 	__be16 frag_off;
735 
736 	/* find outer header point */
737 	l3.hdr = skb_network_header(skb);
738 	l4_hdr = skb_transport_header(skb);
739 
740 	if (skb->protocol == htons(ETH_P_IPV6)) {
741 		exthdr = l3.hdr + sizeof(*l3.v6);
742 		l4_proto_tmp = l3.v6->nexthdr;
743 		if (l4_hdr != exthdr)
744 			ipv6_skip_exthdr(skb, exthdr - skb->data,
745 					 &l4_proto_tmp, &frag_off);
746 	} else if (skb->protocol == htons(ETH_P_IP)) {
747 		l4_proto_tmp = l3.v4->protocol;
748 	} else {
749 		return -EINVAL;
750 	}
751 
752 	*ol4_proto = l4_proto_tmp;
753 
754 	/* tunnel packet */
755 	if (!skb->encapsulation) {
756 		*il4_proto = 0;
757 		return 0;
758 	}
759 
760 	/* find inner header point */
761 	l3.hdr = skb_inner_network_header(skb);
762 	l4_hdr = skb_inner_transport_header(skb);
763 
764 	if (l3.v6->version == 6) {
765 		exthdr = l3.hdr + sizeof(*l3.v6);
766 		l4_proto_tmp = l3.v6->nexthdr;
767 		if (l4_hdr != exthdr)
768 			ipv6_skip_exthdr(skb, exthdr - skb->data,
769 					 &l4_proto_tmp, &frag_off);
770 	} else if (l3.v4->version == 4) {
771 		l4_proto_tmp = l3.v4->protocol;
772 	}
773 
774 	*il4_proto = l4_proto_tmp;
775 
776 	return 0;
777 }
778 
779 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
780  * and it is udp packet, which has a dest port as the IANA assigned.
781  * the hardware is expected to do the checksum offload, but the
782  * hardware will not do the checksum offload when udp dest port is
783  * 4789.
784  */
785 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
786 {
787 	union l4_hdr_info l4;
788 
789 	l4.hdr = skb_transport_header(skb);
790 
791 	if (!(!skb->encapsulation &&
792 	      l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
793 		return false;
794 
795 	skb_checksum_help(skb);
796 
797 	return true;
798 }
799 
800 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
801 				  u32 *ol_type_vlan_len_msec)
802 {
803 	u32 l2_len, l3_len, l4_len;
804 	unsigned char *il2_hdr;
805 	union l3_hdr_info l3;
806 	union l4_hdr_info l4;
807 
808 	l3.hdr = skb_network_header(skb);
809 	l4.hdr = skb_transport_header(skb);
810 
811 	/* compute OL2 header size, defined in 2 Bytes */
812 	l2_len = l3.hdr - skb->data;
813 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
814 
815 	/* compute OL3 header size, defined in 4 Bytes */
816 	l3_len = l4.hdr - l3.hdr;
817 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
818 
819 	il2_hdr = skb_inner_mac_header(skb);
820 	/* compute OL4 header size, defined in 4 Bytes */
821 	l4_len = il2_hdr - l4.hdr;
822 	hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
823 
824 	/* define outer network header type */
825 	if (skb->protocol == htons(ETH_P_IP)) {
826 		if (skb_is_gso(skb))
827 			hns3_set_field(*ol_type_vlan_len_msec,
828 				       HNS3_TXD_OL3T_S,
829 				       HNS3_OL3T_IPV4_CSUM);
830 		else
831 			hns3_set_field(*ol_type_vlan_len_msec,
832 				       HNS3_TXD_OL3T_S,
833 				       HNS3_OL3T_IPV4_NO_CSUM);
834 
835 	} else if (skb->protocol == htons(ETH_P_IPV6)) {
836 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
837 			       HNS3_OL3T_IPV6);
838 	}
839 
840 	if (ol4_proto == IPPROTO_UDP)
841 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
842 			       HNS3_TUN_MAC_IN_UDP);
843 	else if (ol4_proto == IPPROTO_GRE)
844 		hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
845 			       HNS3_TUN_NVGRE);
846 }
847 
848 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
849 			   u8 il4_proto, u32 *type_cs_vlan_tso,
850 			   u32 *ol_type_vlan_len_msec)
851 {
852 	unsigned char *l2_hdr = skb->data;
853 	u32 l4_proto = ol4_proto;
854 	union l4_hdr_info l4;
855 	union l3_hdr_info l3;
856 	u32 l2_len, l3_len;
857 
858 	l4.hdr = skb_transport_header(skb);
859 	l3.hdr = skb_network_header(skb);
860 
861 	/* handle encapsulation skb */
862 	if (skb->encapsulation) {
863 		/* If this is a not UDP/GRE encapsulation skb */
864 		if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
865 			/* drop the skb tunnel packet if hardware don't support,
866 			 * because hardware can't calculate csum when TSO.
867 			 */
868 			if (skb_is_gso(skb))
869 				return -EDOM;
870 
871 			/* the stack computes the IP header already,
872 			 * driver calculate l4 checksum when not TSO.
873 			 */
874 			skb_checksum_help(skb);
875 			return 0;
876 		}
877 
878 		hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
879 
880 		/* switch to inner header */
881 		l2_hdr = skb_inner_mac_header(skb);
882 		l3.hdr = skb_inner_network_header(skb);
883 		l4.hdr = skb_inner_transport_header(skb);
884 		l4_proto = il4_proto;
885 	}
886 
887 	if (l3.v4->version == 4) {
888 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
889 			       HNS3_L3T_IPV4);
890 
891 		/* the stack computes the IP header already, the only time we
892 		 * need the hardware to recompute it is in the case of TSO.
893 		 */
894 		if (skb_is_gso(skb))
895 			hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
896 	} else if (l3.v6->version == 6) {
897 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
898 			       HNS3_L3T_IPV6);
899 	}
900 
901 	/* compute inner(/normal) L2 header size, defined in 2 Bytes */
902 	l2_len = l3.hdr - l2_hdr;
903 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
904 
905 	/* compute inner(/normal) L3 header size, defined in 4 Bytes */
906 	l3_len = l4.hdr - l3.hdr;
907 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
908 
909 	/* compute inner(/normal) L4 header size, defined in 4 Bytes */
910 	switch (l4_proto) {
911 	case IPPROTO_TCP:
912 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
913 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
914 			       HNS3_L4T_TCP);
915 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
916 			       l4.tcp->doff);
917 		break;
918 	case IPPROTO_UDP:
919 		if (hns3_tunnel_csum_bug(skb))
920 			break;
921 
922 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
923 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
924 			       HNS3_L4T_UDP);
925 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
926 			       (sizeof(struct udphdr) >> 2));
927 		break;
928 	case IPPROTO_SCTP:
929 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
930 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
931 			       HNS3_L4T_SCTP);
932 		hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
933 			       (sizeof(struct sctphdr) >> 2));
934 		break;
935 	default:
936 		/* drop the skb tunnel packet if hardware don't support,
937 		 * because hardware can't calculate csum when TSO.
938 		 */
939 		if (skb_is_gso(skb))
940 			return -EDOM;
941 
942 		/* the stack computes the IP header already,
943 		 * driver calculate l4 checksum when not TSO.
944 		 */
945 		skb_checksum_help(skb);
946 		return 0;
947 	}
948 
949 	return 0;
950 }
951 
952 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
953 			     struct sk_buff *skb)
954 {
955 	struct hnae3_handle *handle = tx_ring->tqp->handle;
956 	struct vlan_ethhdr *vhdr;
957 	int rc;
958 
959 	if (!(skb->protocol == htons(ETH_P_8021Q) ||
960 	      skb_vlan_tag_present(skb)))
961 		return 0;
962 
963 	/* Since HW limitation, if port based insert VLAN enabled, only one VLAN
964 	 * header is allowed in skb, otherwise it will cause RAS error.
965 	 */
966 	if (unlikely(skb_vlan_tagged_multi(skb) &&
967 		     handle->port_base_vlan_state ==
968 		     HNAE3_PORT_BASE_VLAN_ENABLE))
969 		return -EINVAL;
970 
971 	if (skb->protocol == htons(ETH_P_8021Q) &&
972 	    !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
973 		/* When HW VLAN acceleration is turned off, and the stack
974 		 * sets the protocol to 802.1q, the driver just need to
975 		 * set the protocol to the encapsulated ethertype.
976 		 */
977 		skb->protocol = vlan_get_protocol(skb);
978 		return 0;
979 	}
980 
981 	if (skb_vlan_tag_present(skb)) {
982 		/* Based on hw strategy, use out_vtag in two layer tag case,
983 		 * and use inner_vtag in one tag case.
984 		 */
985 		if (skb->protocol == htons(ETH_P_8021Q) &&
986 		    handle->port_base_vlan_state ==
987 		    HNAE3_PORT_BASE_VLAN_DISABLE)
988 			rc = HNS3_OUTER_VLAN_TAG;
989 		else
990 			rc = HNS3_INNER_VLAN_TAG;
991 
992 		skb->protocol = vlan_get_protocol(skb);
993 		return rc;
994 	}
995 
996 	rc = skb_cow_head(skb, 0);
997 	if (unlikely(rc < 0))
998 		return rc;
999 
1000 	vhdr = (struct vlan_ethhdr *)skb->data;
1001 	vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1002 					 & VLAN_PRIO_MASK);
1003 
1004 	skb->protocol = vlan_get_protocol(skb);
1005 	return 0;
1006 }
1007 
1008 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1009 			      struct sk_buff *skb, struct hns3_desc *desc)
1010 {
1011 	u32 ol_type_vlan_len_msec = 0;
1012 	u32 type_cs_vlan_tso = 0;
1013 	u32 paylen = skb->len;
1014 	u16 inner_vtag = 0;
1015 	u16 out_vtag = 0;
1016 	u16 mss = 0;
1017 	int ret;
1018 
1019 	ret = hns3_handle_vtags(ring, skb);
1020 	if (unlikely(ret < 0)) {
1021 		u64_stats_update_begin(&ring->syncp);
1022 		ring->stats.tx_vlan_err++;
1023 		u64_stats_update_end(&ring->syncp);
1024 		return ret;
1025 	} else if (ret == HNS3_INNER_VLAN_TAG) {
1026 		inner_vtag = skb_vlan_tag_get(skb);
1027 		inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1028 				VLAN_PRIO_MASK;
1029 		hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1030 	} else if (ret == HNS3_OUTER_VLAN_TAG) {
1031 		out_vtag = skb_vlan_tag_get(skb);
1032 		out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1033 				VLAN_PRIO_MASK;
1034 		hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1035 			       1);
1036 	}
1037 
1038 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
1039 		u8 ol4_proto, il4_proto;
1040 
1041 		skb_reset_mac_len(skb);
1042 
1043 		ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1044 		if (unlikely(ret < 0)) {
1045 			u64_stats_update_begin(&ring->syncp);
1046 			ring->stats.tx_l4_proto_err++;
1047 			u64_stats_update_end(&ring->syncp);
1048 			return ret;
1049 		}
1050 
1051 		ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1052 				      &type_cs_vlan_tso,
1053 				      &ol_type_vlan_len_msec);
1054 		if (unlikely(ret < 0)) {
1055 			u64_stats_update_begin(&ring->syncp);
1056 			ring->stats.tx_l2l3l4_err++;
1057 			u64_stats_update_end(&ring->syncp);
1058 			return ret;
1059 		}
1060 
1061 		ret = hns3_set_tso(skb, &paylen, &mss,
1062 				   &type_cs_vlan_tso);
1063 		if (unlikely(ret < 0)) {
1064 			u64_stats_update_begin(&ring->syncp);
1065 			ring->stats.tx_tso_err++;
1066 			u64_stats_update_end(&ring->syncp);
1067 			return ret;
1068 		}
1069 	}
1070 
1071 	/* Set txbd */
1072 	desc->tx.ol_type_vlan_len_msec =
1073 		cpu_to_le32(ol_type_vlan_len_msec);
1074 	desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1075 	desc->tx.paylen = cpu_to_le32(paylen);
1076 	desc->tx.mss = cpu_to_le16(mss);
1077 	desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1078 	desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1079 
1080 	return 0;
1081 }
1082 
1083 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1084 			  unsigned int size, enum hns_desc_type type)
1085 {
1086 #define HNS3_LIKELY_BD_NUM	1
1087 
1088 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1089 	struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1090 	struct device *dev = ring_to_dev(ring);
1091 	skb_frag_t *frag;
1092 	unsigned int frag_buf_num;
1093 	int k, sizeoflast;
1094 	dma_addr_t dma;
1095 
1096 	if (type == DESC_TYPE_FRAGLIST_SKB ||
1097 	    type == DESC_TYPE_SKB) {
1098 		struct sk_buff *skb = (struct sk_buff *)priv;
1099 
1100 		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1101 	} else {
1102 		frag = (skb_frag_t *)priv;
1103 		dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1104 	}
1105 
1106 	if (unlikely(dma_mapping_error(dev, dma))) {
1107 		u64_stats_update_begin(&ring->syncp);
1108 		ring->stats.sw_err_cnt++;
1109 		u64_stats_update_end(&ring->syncp);
1110 		return -ENOMEM;
1111 	}
1112 
1113 	desc_cb->priv = priv;
1114 	desc_cb->length = size;
1115 	desc_cb->dma = dma;
1116 	desc_cb->type = type;
1117 
1118 	if (likely(size <= HNS3_MAX_BD_SIZE)) {
1119 		desc->addr = cpu_to_le64(dma);
1120 		desc->tx.send_size = cpu_to_le16(size);
1121 		desc->tx.bdtp_fe_sc_vld_ra_ri =
1122 			cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1123 
1124 		trace_hns3_tx_desc(ring, ring->next_to_use);
1125 		ring_ptr_move_fw(ring, next_to_use);
1126 		return HNS3_LIKELY_BD_NUM;
1127 	}
1128 
1129 	frag_buf_num = hns3_tx_bd_count(size);
1130 	sizeoflast = size % HNS3_MAX_BD_SIZE;
1131 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1132 
1133 	/* When frag size is bigger than hardware limit, split this frag */
1134 	for (k = 0; k < frag_buf_num; k++) {
1135 		/* now, fill the descriptor */
1136 		desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1137 		desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1138 				     (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1139 		desc->tx.bdtp_fe_sc_vld_ra_ri =
1140 				cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1141 
1142 		trace_hns3_tx_desc(ring, ring->next_to_use);
1143 		/* move ring pointer to next */
1144 		ring_ptr_move_fw(ring, next_to_use);
1145 
1146 		desc = &ring->desc[ring->next_to_use];
1147 	}
1148 
1149 	return frag_buf_num;
1150 }
1151 
1152 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1153 				    unsigned int bd_num)
1154 {
1155 	unsigned int size;
1156 	int i;
1157 
1158 	size = skb_headlen(skb);
1159 	while (size > HNS3_MAX_BD_SIZE) {
1160 		bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1161 		size -= HNS3_MAX_BD_SIZE;
1162 
1163 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1164 			return bd_num;
1165 	}
1166 
1167 	if (size) {
1168 		bd_size[bd_num++] = size;
1169 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1170 			return bd_num;
1171 	}
1172 
1173 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1174 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1175 		size = skb_frag_size(frag);
1176 		if (!size)
1177 			continue;
1178 
1179 		while (size > HNS3_MAX_BD_SIZE) {
1180 			bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1181 			size -= HNS3_MAX_BD_SIZE;
1182 
1183 			if (bd_num > HNS3_MAX_TSO_BD_NUM)
1184 				return bd_num;
1185 		}
1186 
1187 		bd_size[bd_num++] = size;
1188 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1189 			return bd_num;
1190 	}
1191 
1192 	return bd_num;
1193 }
1194 
1195 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1196 {
1197 	struct sk_buff *frag_skb;
1198 	unsigned int bd_num = 0;
1199 
1200 	/* If the total len is within the max bd limit */
1201 	if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1202 		   skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1203 		return skb_shinfo(skb)->nr_frags + 1U;
1204 
1205 	/* The below case will always be linearized, return
1206 	 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1207 	 */
1208 	if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1209 		     (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1210 		return HNS3_MAX_TSO_BD_NUM + 1U;
1211 
1212 	bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1213 
1214 	if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1215 		return bd_num;
1216 
1217 	skb_walk_frags(skb, frag_skb) {
1218 		bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1219 		if (bd_num > HNS3_MAX_TSO_BD_NUM)
1220 			return bd_num;
1221 	}
1222 
1223 	return bd_num;
1224 }
1225 
1226 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1227 {
1228 	if (!skb->encapsulation)
1229 		return skb_transport_offset(skb) + tcp_hdrlen(skb);
1230 
1231 	return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1232 }
1233 
1234 /* HW need every continuous 8 buffer data to be larger than MSS,
1235  * we simplify it by ensuring skb_headlen + the first continuous
1236  * 7 frags to to be larger than gso header len + mss, and the remaining
1237  * continuous 7 frags to be larger than MSS except the last 7 frags.
1238  */
1239 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1240 				     unsigned int bd_num)
1241 {
1242 	unsigned int tot_len = 0;
1243 	int i;
1244 
1245 	for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1246 		tot_len += bd_size[i];
1247 
1248 	/* ensure the first 8 frags is greater than mss + header */
1249 	if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1250 	    skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1251 		return true;
1252 
1253 	/* ensure every continuous 7 buffer is greater than mss
1254 	 * except the last one.
1255 	 */
1256 	for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1257 		tot_len -= bd_size[i];
1258 		tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1259 
1260 		if (tot_len < skb_shinfo(skb)->gso_size)
1261 			return true;
1262 	}
1263 
1264 	return false;
1265 }
1266 
1267 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1268 {
1269 	int i = 0;
1270 
1271 	for (i = 0; i < MAX_SKB_FRAGS; i++)
1272 		size[i] = skb_frag_size(&shinfo->frags[i]);
1273 }
1274 
1275 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1276 				  struct net_device *netdev,
1277 				  struct sk_buff *skb)
1278 {
1279 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1280 	unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1281 	unsigned int bd_num;
1282 
1283 	bd_num = hns3_tx_bd_num(skb, bd_size);
1284 	if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1285 		if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1286 		    !hns3_skb_need_linearized(skb, bd_size, bd_num)) {
1287 			trace_hns3_over_8bd(skb);
1288 			goto out;
1289 		}
1290 
1291 		if (__skb_linearize(skb))
1292 			return -ENOMEM;
1293 
1294 		bd_num = hns3_tx_bd_count(skb->len);
1295 		if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1296 		    (!skb_is_gso(skb) &&
1297 		     bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1298 			trace_hns3_over_8bd(skb);
1299 			return -ENOMEM;
1300 		}
1301 
1302 		u64_stats_update_begin(&ring->syncp);
1303 		ring->stats.tx_copy++;
1304 		u64_stats_update_end(&ring->syncp);
1305 	}
1306 
1307 out:
1308 	if (likely(ring_space(ring) >= bd_num))
1309 		return bd_num;
1310 
1311 	netif_stop_subqueue(netdev, ring->queue_index);
1312 	smp_mb(); /* Memory barrier before checking ring_space */
1313 
1314 	/* Start queue in case hns3_clean_tx_ring has just made room
1315 	 * available and has not seen the queue stopped state performed
1316 	 * by netif_stop_subqueue above.
1317 	 */
1318 	if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1319 	    !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1320 		netif_start_subqueue(netdev, ring->queue_index);
1321 		return bd_num;
1322 	}
1323 
1324 	return -EBUSY;
1325 }
1326 
1327 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1328 {
1329 	struct device *dev = ring_to_dev(ring);
1330 	unsigned int i;
1331 
1332 	for (i = 0; i < ring->desc_num; i++) {
1333 		struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1334 
1335 		memset(desc, 0, sizeof(*desc));
1336 
1337 		/* check if this is where we started */
1338 		if (ring->next_to_use == next_to_use_orig)
1339 			break;
1340 
1341 		/* rollback one */
1342 		ring_ptr_move_bw(ring, next_to_use);
1343 
1344 		if (!ring->desc_cb[ring->next_to_use].dma)
1345 			continue;
1346 
1347 		/* unmap the descriptor dma address */
1348 		if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
1349 		    ring->desc_cb[ring->next_to_use].type ==
1350 		    DESC_TYPE_FRAGLIST_SKB)
1351 			dma_unmap_single(dev,
1352 					 ring->desc_cb[ring->next_to_use].dma,
1353 					ring->desc_cb[ring->next_to_use].length,
1354 					DMA_TO_DEVICE);
1355 		else if (ring->desc_cb[ring->next_to_use].length)
1356 			dma_unmap_page(dev,
1357 				       ring->desc_cb[ring->next_to_use].dma,
1358 				       ring->desc_cb[ring->next_to_use].length,
1359 				       DMA_TO_DEVICE);
1360 
1361 		ring->desc_cb[ring->next_to_use].length = 0;
1362 		ring->desc_cb[ring->next_to_use].dma = 0;
1363 		ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
1364 	}
1365 }
1366 
1367 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1368 				 struct sk_buff *skb, enum hns_desc_type type)
1369 {
1370 	unsigned int size = skb_headlen(skb);
1371 	int i, ret, bd_num = 0;
1372 
1373 	if (size) {
1374 		ret = hns3_fill_desc(ring, skb, size, type);
1375 		if (unlikely(ret < 0))
1376 			return ret;
1377 
1378 		bd_num += ret;
1379 	}
1380 
1381 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1382 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1383 
1384 		size = skb_frag_size(frag);
1385 		if (!size)
1386 			continue;
1387 
1388 		ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1389 		if (unlikely(ret < 0))
1390 			return ret;
1391 
1392 		bd_num += ret;
1393 	}
1394 
1395 	return bd_num;
1396 }
1397 
1398 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1399 {
1400 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1401 	struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1402 	struct netdev_queue *dev_queue;
1403 	int pre_ntu, next_to_use_head;
1404 	struct sk_buff *frag_skb;
1405 	int bd_num = 0;
1406 	int ret;
1407 
1408 	/* Hardware can only handle short frames above 32 bytes */
1409 	if (skb_put_padto(skb, HNS3_MIN_TX_LEN))
1410 		return NETDEV_TX_OK;
1411 
1412 	/* Prefetch the data used later */
1413 	prefetch(skb->data);
1414 
1415 	ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
1416 	if (unlikely(ret <= 0)) {
1417 		if (ret == -EBUSY) {
1418 			u64_stats_update_begin(&ring->syncp);
1419 			ring->stats.tx_busy++;
1420 			u64_stats_update_end(&ring->syncp);
1421 			return NETDEV_TX_BUSY;
1422 		} else if (ret == -ENOMEM) {
1423 			u64_stats_update_begin(&ring->syncp);
1424 			ring->stats.sw_err_cnt++;
1425 			u64_stats_update_end(&ring->syncp);
1426 		}
1427 
1428 		hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1429 		goto out_err_tx_ok;
1430 	}
1431 
1432 	next_to_use_head = ring->next_to_use;
1433 
1434 	ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]);
1435 	if (unlikely(ret < 0))
1436 		goto fill_err;
1437 
1438 	ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1439 	if (unlikely(ret < 0))
1440 		goto fill_err;
1441 
1442 	bd_num += ret;
1443 
1444 	skb_walk_frags(skb, frag_skb) {
1445 		ret = hns3_fill_skb_to_desc(ring, frag_skb,
1446 					    DESC_TYPE_FRAGLIST_SKB);
1447 		if (unlikely(ret < 0))
1448 			goto fill_err;
1449 
1450 		bd_num += ret;
1451 	}
1452 
1453 	pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1454 					(ring->desc_num - 1);
1455 	ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1456 				cpu_to_le16(BIT(HNS3_TXD_FE_B));
1457 	trace_hns3_tx_desc(ring, pre_ntu);
1458 
1459 	/* Complete translate all packets */
1460 	dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1461 	netdev_tx_sent_queue(dev_queue, skb->len);
1462 
1463 	wmb(); /* Commit all data before submit */
1464 
1465 	hnae3_queue_xmit(ring->tqp, bd_num);
1466 
1467 	return NETDEV_TX_OK;
1468 
1469 fill_err:
1470 	hns3_clear_desc(ring, next_to_use_head);
1471 
1472 out_err_tx_ok:
1473 	dev_kfree_skb_any(skb);
1474 	return NETDEV_TX_OK;
1475 }
1476 
1477 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1478 {
1479 	struct hnae3_handle *h = hns3_get_handle(netdev);
1480 	struct sockaddr *mac_addr = p;
1481 	int ret;
1482 
1483 	if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1484 		return -EADDRNOTAVAIL;
1485 
1486 	if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1487 		netdev_info(netdev, "already using mac address %pM\n",
1488 			    mac_addr->sa_data);
1489 		return 0;
1490 	}
1491 
1492 	/* For VF device, if there is a perm_addr, then the user will not
1493 	 * be allowed to change the address.
1494 	 */
1495 	if (!hns3_is_phys_func(h->pdev) &&
1496 	    !is_zero_ether_addr(netdev->perm_addr)) {
1497 		netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1498 			   netdev->perm_addr, mac_addr->sa_data);
1499 		return -EPERM;
1500 	}
1501 
1502 	ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1503 	if (ret) {
1504 		netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1505 		return ret;
1506 	}
1507 
1508 	ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1509 
1510 	return 0;
1511 }
1512 
1513 static int hns3_nic_do_ioctl(struct net_device *netdev,
1514 			     struct ifreq *ifr, int cmd)
1515 {
1516 	struct hnae3_handle *h = hns3_get_handle(netdev);
1517 
1518 	if (!netif_running(netdev))
1519 		return -EINVAL;
1520 
1521 	if (!h->ae_algo->ops->do_ioctl)
1522 		return -EOPNOTSUPP;
1523 
1524 	return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1525 }
1526 
1527 static int hns3_nic_set_features(struct net_device *netdev,
1528 				 netdev_features_t features)
1529 {
1530 	netdev_features_t changed = netdev->features ^ features;
1531 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1532 	struct hnae3_handle *h = priv->ae_handle;
1533 	bool enable;
1534 	int ret;
1535 
1536 	if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1537 		enable = !!(features & NETIF_F_GRO_HW);
1538 		ret = h->ae_algo->ops->set_gro_en(h, enable);
1539 		if (ret)
1540 			return ret;
1541 	}
1542 
1543 	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1544 	    h->ae_algo->ops->enable_hw_strip_rxvtag) {
1545 		enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1546 		ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1547 		if (ret)
1548 			return ret;
1549 	}
1550 
1551 	if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1552 		enable = !!(features & NETIF_F_NTUPLE);
1553 		h->ae_algo->ops->enable_fd(h, enable);
1554 	}
1555 
1556 	netdev->features = features;
1557 	return 0;
1558 }
1559 
1560 static netdev_features_t hns3_features_check(struct sk_buff *skb,
1561 					     struct net_device *dev,
1562 					     netdev_features_t features)
1563 {
1564 #define HNS3_MAX_HDR_LEN	480U
1565 #define HNS3_MAX_L4_HDR_LEN	60U
1566 
1567 	size_t len;
1568 
1569 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1570 		return features;
1571 
1572 	if (skb->encapsulation)
1573 		len = skb_inner_transport_header(skb) - skb->data;
1574 	else
1575 		len = skb_transport_header(skb) - skb->data;
1576 
1577 	/* Assume L4 is 60 byte as TCP is the only protocol with a
1578 	 * a flexible value, and it's max len is 60 bytes.
1579 	 */
1580 	len += HNS3_MAX_L4_HDR_LEN;
1581 
1582 	/* Hardware only supports checksum on the skb with a max header
1583 	 * len of 480 bytes.
1584 	 */
1585 	if (len > HNS3_MAX_HDR_LEN)
1586 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
1587 
1588 	return features;
1589 }
1590 
1591 static void hns3_nic_get_stats64(struct net_device *netdev,
1592 				 struct rtnl_link_stats64 *stats)
1593 {
1594 	struct hns3_nic_priv *priv = netdev_priv(netdev);
1595 	int queue_num = priv->ae_handle->kinfo.num_tqps;
1596 	struct hnae3_handle *handle = priv->ae_handle;
1597 	struct hns3_enet_ring *ring;
1598 	u64 rx_length_errors = 0;
1599 	u64 rx_crc_errors = 0;
1600 	u64 rx_multicast = 0;
1601 	unsigned int start;
1602 	u64 tx_errors = 0;
1603 	u64 rx_errors = 0;
1604 	unsigned int idx;
1605 	u64 tx_bytes = 0;
1606 	u64 rx_bytes = 0;
1607 	u64 tx_pkts = 0;
1608 	u64 rx_pkts = 0;
1609 	u64 tx_drop = 0;
1610 	u64 rx_drop = 0;
1611 
1612 	if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1613 		return;
1614 
1615 	handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1616 
1617 	for (idx = 0; idx < queue_num; idx++) {
1618 		/* fetch the tx stats */
1619 		ring = &priv->ring[idx];
1620 		do {
1621 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1622 			tx_bytes += ring->stats.tx_bytes;
1623 			tx_pkts += ring->stats.tx_pkts;
1624 			tx_drop += ring->stats.sw_err_cnt;
1625 			tx_drop += ring->stats.tx_vlan_err;
1626 			tx_drop += ring->stats.tx_l4_proto_err;
1627 			tx_drop += ring->stats.tx_l2l3l4_err;
1628 			tx_drop += ring->stats.tx_tso_err;
1629 			tx_errors += ring->stats.sw_err_cnt;
1630 			tx_errors += ring->stats.tx_vlan_err;
1631 			tx_errors += ring->stats.tx_l4_proto_err;
1632 			tx_errors += ring->stats.tx_l2l3l4_err;
1633 			tx_errors += ring->stats.tx_tso_err;
1634 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1635 
1636 		/* fetch the rx stats */
1637 		ring = &priv->ring[idx + queue_num];
1638 		do {
1639 			start = u64_stats_fetch_begin_irq(&ring->syncp);
1640 			rx_bytes += ring->stats.rx_bytes;
1641 			rx_pkts += ring->stats.rx_pkts;
1642 			rx_drop += ring->stats.l2_err;
1643 			rx_errors += ring->stats.l2_err;
1644 			rx_errors += ring->stats.l3l4_csum_err;
1645 			rx_crc_errors += ring->stats.l2_err;
1646 			rx_multicast += ring->stats.rx_multicast;
1647 			rx_length_errors += ring->stats.err_pkt_len;
1648 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1649 	}
1650 
1651 	stats->tx_bytes = tx_bytes;
1652 	stats->tx_packets = tx_pkts;
1653 	stats->rx_bytes = rx_bytes;
1654 	stats->rx_packets = rx_pkts;
1655 
1656 	stats->rx_errors = rx_errors;
1657 	stats->multicast = rx_multicast;
1658 	stats->rx_length_errors = rx_length_errors;
1659 	stats->rx_crc_errors = rx_crc_errors;
1660 	stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1661 
1662 	stats->tx_errors = tx_errors;
1663 	stats->rx_dropped = rx_drop;
1664 	stats->tx_dropped = tx_drop;
1665 	stats->collisions = netdev->stats.collisions;
1666 	stats->rx_over_errors = netdev->stats.rx_over_errors;
1667 	stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1668 	stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1669 	stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1670 	stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1671 	stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1672 	stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1673 	stats->tx_window_errors = netdev->stats.tx_window_errors;
1674 	stats->rx_compressed = netdev->stats.rx_compressed;
1675 	stats->tx_compressed = netdev->stats.tx_compressed;
1676 }
1677 
1678 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1679 {
1680 	struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1681 	u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1682 	struct hnae3_knic_private_info *kinfo;
1683 	u8 tc = mqprio_qopt->qopt.num_tc;
1684 	u16 mode = mqprio_qopt->mode;
1685 	u8 hw = mqprio_qopt->qopt.hw;
1686 	struct hnae3_handle *h;
1687 
1688 	if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1689 	       mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1690 		return -EOPNOTSUPP;
1691 
1692 	if (tc > HNAE3_MAX_TC)
1693 		return -EINVAL;
1694 
1695 	if (!netdev)
1696 		return -EINVAL;
1697 
1698 	h = hns3_get_handle(netdev);
1699 	kinfo = &h->kinfo;
1700 
1701 	netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1702 
1703 	return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1704 		kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP;
1705 }
1706 
1707 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1708 			     void *type_data)
1709 {
1710 	if (type != TC_SETUP_QDISC_MQPRIO)
1711 		return -EOPNOTSUPP;
1712 
1713 	return hns3_setup_tc(dev, type_data);
1714 }
1715 
1716 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1717 				__be16 proto, u16 vid)
1718 {
1719 	struct hnae3_handle *h = hns3_get_handle(netdev);
1720 	int ret = -EIO;
1721 
1722 	if (h->ae_algo->ops->set_vlan_filter)
1723 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1724 
1725 	return ret;
1726 }
1727 
1728 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1729 				 __be16 proto, u16 vid)
1730 {
1731 	struct hnae3_handle *h = hns3_get_handle(netdev);
1732 	int ret = -EIO;
1733 
1734 	if (h->ae_algo->ops->set_vlan_filter)
1735 		ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1736 
1737 	return ret;
1738 }
1739 
1740 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1741 				u8 qos, __be16 vlan_proto)
1742 {
1743 	struct hnae3_handle *h = hns3_get_handle(netdev);
1744 	int ret = -EIO;
1745 
1746 	netif_dbg(h, drv, netdev,
1747 		  "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
1748 		  vf, vlan, qos, ntohs(vlan_proto));
1749 
1750 	if (h->ae_algo->ops->set_vf_vlan_filter)
1751 		ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1752 							  qos, vlan_proto);
1753 
1754 	return ret;
1755 }
1756 
1757 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1758 {
1759 	struct hnae3_handle *handle = hns3_get_handle(netdev);
1760 
1761 	if (hns3_nic_resetting(netdev))
1762 		return -EBUSY;
1763 
1764 	if (!handle->ae_algo->ops->set_vf_spoofchk)
1765 		return -EOPNOTSUPP;
1766 
1767 	return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1768 }
1769 
1770 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1771 {
1772 	struct hnae3_handle *handle = hns3_get_handle(netdev);
1773 
1774 	if (!handle->ae_algo->ops->set_vf_trust)
1775 		return -EOPNOTSUPP;
1776 
1777 	return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1778 }
1779 
1780 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1781 {
1782 	struct hnae3_handle *h = hns3_get_handle(netdev);
1783 	int ret;
1784 
1785 	if (hns3_nic_resetting(netdev))
1786 		return -EBUSY;
1787 
1788 	if (!h->ae_algo->ops->set_mtu)
1789 		return -EOPNOTSUPP;
1790 
1791 	netif_dbg(h, drv, netdev,
1792 		  "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1793 
1794 	ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1795 	if (ret)
1796 		netdev_err(netdev, "failed to change MTU in hardware %d\n",
1797 			   ret);
1798 	else
1799 		netdev->mtu = new_mtu;
1800 
1801 	return ret;
1802 }
1803 
1804 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1805 {
1806 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1807 	struct hnae3_handle *h = hns3_get_handle(ndev);
1808 	struct hns3_enet_ring *tx_ring;
1809 	struct napi_struct *napi;
1810 	int timeout_queue = 0;
1811 	int hw_head, hw_tail;
1812 	int fbd_num, fbd_oft;
1813 	int ebd_num, ebd_oft;
1814 	int bd_num, bd_err;
1815 	int ring_en, tc;
1816 	int i;
1817 
1818 	/* Find the stopped queue the same way the stack does */
1819 	for (i = 0; i < ndev->num_tx_queues; i++) {
1820 		struct netdev_queue *q;
1821 		unsigned long trans_start;
1822 
1823 		q = netdev_get_tx_queue(ndev, i);
1824 		trans_start = q->trans_start;
1825 		if (netif_xmit_stopped(q) &&
1826 		    time_after(jiffies,
1827 			       (trans_start + ndev->watchdog_timeo))) {
1828 			timeout_queue = i;
1829 			netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
1830 				    q->state,
1831 				    jiffies_to_msecs(jiffies - trans_start));
1832 			break;
1833 		}
1834 	}
1835 
1836 	if (i == ndev->num_tx_queues) {
1837 		netdev_info(ndev,
1838 			    "no netdev TX timeout queue found, timeout count: %llu\n",
1839 			    priv->tx_timeout_count);
1840 		return false;
1841 	}
1842 
1843 	priv->tx_timeout_count++;
1844 
1845 	tx_ring = &priv->ring[timeout_queue];
1846 	napi = &tx_ring->tqp_vector->napi;
1847 
1848 	netdev_info(ndev,
1849 		    "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1850 		    priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1851 		    tx_ring->next_to_clean, napi->state);
1852 
1853 	netdev_info(ndev,
1854 		    "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1855 		    tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1856 		    tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1857 
1858 	netdev_info(ndev,
1859 		    "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1860 		    tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1861 		    tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1862 
1863 	/* When mac received many pause frames continuous, it's unable to send
1864 	 * packets, which may cause tx timeout
1865 	 */
1866 	if (h->ae_algo->ops->get_mac_stats) {
1867 		struct hns3_mac_stats mac_stats;
1868 
1869 		h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1870 		netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1871 			    mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1872 	}
1873 
1874 	hw_head = readl_relaxed(tx_ring->tqp->io_base +
1875 				HNS3_RING_TX_RING_HEAD_REG);
1876 	hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1877 				HNS3_RING_TX_RING_TAIL_REG);
1878 	fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1879 				HNS3_RING_TX_RING_FBDNUM_REG);
1880 	fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1881 				HNS3_RING_TX_RING_OFFSET_REG);
1882 	ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1883 				HNS3_RING_TX_RING_EBDNUM_REG);
1884 	ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1885 				HNS3_RING_TX_RING_EBD_OFFSET_REG);
1886 	bd_num = readl_relaxed(tx_ring->tqp->io_base +
1887 			       HNS3_RING_TX_RING_BD_NUM_REG);
1888 	bd_err = readl_relaxed(tx_ring->tqp->io_base +
1889 			       HNS3_RING_TX_RING_BD_ERR_REG);
1890 	ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1891 	tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1892 
1893 	netdev_info(ndev,
1894 		    "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1895 		    bd_num, hw_head, hw_tail, bd_err,
1896 		    readl(tx_ring->tqp_vector->mask_addr));
1897 	netdev_info(ndev,
1898 		    "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1899 		    ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1900 
1901 	return true;
1902 }
1903 
1904 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
1905 {
1906 	struct hns3_nic_priv *priv = netdev_priv(ndev);
1907 	struct hnae3_handle *h = priv->ae_handle;
1908 
1909 	if (!hns3_get_tx_timeo_queue_info(ndev))
1910 		return;
1911 
1912 	/* request the reset, and let the hclge to determine
1913 	 * which reset level should be done
1914 	 */
1915 	if (h->ae_algo->ops->reset_event)
1916 		h->ae_algo->ops->reset_event(h->pdev, h);
1917 }
1918 
1919 #ifdef CONFIG_RFS_ACCEL
1920 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1921 			      u16 rxq_index, u32 flow_id)
1922 {
1923 	struct hnae3_handle *h = hns3_get_handle(dev);
1924 	struct flow_keys fkeys;
1925 
1926 	if (!h->ae_algo->ops->add_arfs_entry)
1927 		return -EOPNOTSUPP;
1928 
1929 	if (skb->encapsulation)
1930 		return -EPROTONOSUPPORT;
1931 
1932 	if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1933 		return -EPROTONOSUPPORT;
1934 
1935 	if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1936 	     fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1937 	    (fkeys.basic.ip_proto != IPPROTO_TCP &&
1938 	     fkeys.basic.ip_proto != IPPROTO_UDP))
1939 		return -EPROTONOSUPPORT;
1940 
1941 	return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1942 }
1943 #endif
1944 
1945 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1946 				  struct ifla_vf_info *ivf)
1947 {
1948 	struct hnae3_handle *h = hns3_get_handle(ndev);
1949 
1950 	if (!h->ae_algo->ops->get_vf_config)
1951 		return -EOPNOTSUPP;
1952 
1953 	return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1954 }
1955 
1956 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1957 				      int link_state)
1958 {
1959 	struct hnae3_handle *h = hns3_get_handle(ndev);
1960 
1961 	if (!h->ae_algo->ops->set_vf_link_state)
1962 		return -EOPNOTSUPP;
1963 
1964 	return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1965 }
1966 
1967 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1968 				int min_tx_rate, int max_tx_rate)
1969 {
1970 	struct hnae3_handle *h = hns3_get_handle(ndev);
1971 
1972 	if (!h->ae_algo->ops->set_vf_rate)
1973 		return -EOPNOTSUPP;
1974 
1975 	return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1976 					    false);
1977 }
1978 
1979 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1980 {
1981 	struct hnae3_handle *h = hns3_get_handle(netdev);
1982 
1983 	if (!h->ae_algo->ops->set_vf_mac)
1984 		return -EOPNOTSUPP;
1985 
1986 	if (is_multicast_ether_addr(mac)) {
1987 		netdev_err(netdev,
1988 			   "Invalid MAC:%pM specified. Could not set MAC\n",
1989 			   mac);
1990 		return -EINVAL;
1991 	}
1992 
1993 	return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1994 }
1995 
1996 static const struct net_device_ops hns3_nic_netdev_ops = {
1997 	.ndo_open		= hns3_nic_net_open,
1998 	.ndo_stop		= hns3_nic_net_stop,
1999 	.ndo_start_xmit		= hns3_nic_net_xmit,
2000 	.ndo_tx_timeout		= hns3_nic_net_timeout,
2001 	.ndo_set_mac_address	= hns3_nic_net_set_mac_address,
2002 	.ndo_do_ioctl		= hns3_nic_do_ioctl,
2003 	.ndo_change_mtu		= hns3_nic_change_mtu,
2004 	.ndo_set_features	= hns3_nic_set_features,
2005 	.ndo_features_check	= hns3_features_check,
2006 	.ndo_get_stats64	= hns3_nic_get_stats64,
2007 	.ndo_setup_tc		= hns3_nic_setup_tc,
2008 	.ndo_set_rx_mode	= hns3_nic_set_rx_mode,
2009 	.ndo_vlan_rx_add_vid	= hns3_vlan_rx_add_vid,
2010 	.ndo_vlan_rx_kill_vid	= hns3_vlan_rx_kill_vid,
2011 	.ndo_set_vf_vlan	= hns3_ndo_set_vf_vlan,
2012 	.ndo_set_vf_spoofchk	= hns3_set_vf_spoofchk,
2013 	.ndo_set_vf_trust	= hns3_set_vf_trust,
2014 #ifdef CONFIG_RFS_ACCEL
2015 	.ndo_rx_flow_steer	= hns3_rx_flow_steer,
2016 #endif
2017 	.ndo_get_vf_config	= hns3_nic_get_vf_config,
2018 	.ndo_set_vf_link_state	= hns3_nic_set_vf_link_state,
2019 	.ndo_set_vf_rate	= hns3_nic_set_vf_rate,
2020 	.ndo_set_vf_mac		= hns3_nic_set_vf_mac,
2021 };
2022 
2023 bool hns3_is_phys_func(struct pci_dev *pdev)
2024 {
2025 	u32 dev_id = pdev->device;
2026 
2027 	switch (dev_id) {
2028 	case HNAE3_DEV_ID_GE:
2029 	case HNAE3_DEV_ID_25GE:
2030 	case HNAE3_DEV_ID_25GE_RDMA:
2031 	case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
2032 	case HNAE3_DEV_ID_50GE_RDMA:
2033 	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
2034 	case HNAE3_DEV_ID_100G_RDMA_MACSEC:
2035 		return true;
2036 	case HNAE3_DEV_ID_100G_VF:
2037 	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2038 		return false;
2039 	default:
2040 		dev_warn(&pdev->dev, "un-recognized pci device-id %u",
2041 			 dev_id);
2042 	}
2043 
2044 	return false;
2045 }
2046 
2047 static void hns3_disable_sriov(struct pci_dev *pdev)
2048 {
2049 	/* If our VFs are assigned we cannot shut down SR-IOV
2050 	 * without causing issues, so just leave the hardware
2051 	 * available but disabled
2052 	 */
2053 	if (pci_vfs_assigned(pdev)) {
2054 		dev_warn(&pdev->dev,
2055 			 "disabling driver while VFs are assigned\n");
2056 		return;
2057 	}
2058 
2059 	pci_disable_sriov(pdev);
2060 }
2061 
2062 static void hns3_get_dev_capability(struct pci_dev *pdev,
2063 				    struct hnae3_ae_dev *ae_dev)
2064 {
2065 	if (pdev->revision >= 0x21) {
2066 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2067 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2068 	}
2069 }
2070 
2071 /* hns3_probe - Device initialization routine
2072  * @pdev: PCI device information struct
2073  * @ent: entry in hns3_pci_tbl
2074  *
2075  * hns3_probe initializes a PF identified by a pci_dev structure.
2076  * The OS initialization, configuring of the PF private structure,
2077  * and a hardware reset occur.
2078  *
2079  * Returns 0 on success, negative on failure
2080  */
2081 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2082 {
2083 	struct hnae3_ae_dev *ae_dev;
2084 	int ret;
2085 
2086 	ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2087 	if (!ae_dev)
2088 		return -ENOMEM;
2089 
2090 	ae_dev->pdev = pdev;
2091 	ae_dev->flag = ent->driver_data;
2092 	hns3_get_dev_capability(pdev, ae_dev);
2093 	pci_set_drvdata(pdev, ae_dev);
2094 
2095 	ret = hnae3_register_ae_dev(ae_dev);
2096 	if (ret) {
2097 		devm_kfree(&pdev->dev, ae_dev);
2098 		pci_set_drvdata(pdev, NULL);
2099 	}
2100 
2101 	return ret;
2102 }
2103 
2104 /* hns3_remove - Device removal routine
2105  * @pdev: PCI device information struct
2106  */
2107 static void hns3_remove(struct pci_dev *pdev)
2108 {
2109 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2110 
2111 	if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2112 		hns3_disable_sriov(pdev);
2113 
2114 	hnae3_unregister_ae_dev(ae_dev);
2115 	pci_set_drvdata(pdev, NULL);
2116 }
2117 
2118 /**
2119  * hns3_pci_sriov_configure
2120  * @pdev: pointer to a pci_dev structure
2121  * @num_vfs: number of VFs to allocate
2122  *
2123  * Enable or change the number of VFs. Called when the user updates the number
2124  * of VFs in sysfs.
2125  **/
2126 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2127 {
2128 	int ret;
2129 
2130 	if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2131 		dev_warn(&pdev->dev, "Can not config SRIOV\n");
2132 		return -EINVAL;
2133 	}
2134 
2135 	if (num_vfs) {
2136 		ret = pci_enable_sriov(pdev, num_vfs);
2137 		if (ret)
2138 			dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2139 		else
2140 			return num_vfs;
2141 	} else if (!pci_vfs_assigned(pdev)) {
2142 		pci_disable_sriov(pdev);
2143 	} else {
2144 		dev_warn(&pdev->dev,
2145 			 "Unable to free VFs because some are assigned to VMs.\n");
2146 	}
2147 
2148 	return 0;
2149 }
2150 
2151 static void hns3_shutdown(struct pci_dev *pdev)
2152 {
2153 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2154 
2155 	hnae3_unregister_ae_dev(ae_dev);
2156 	devm_kfree(&pdev->dev, ae_dev);
2157 	pci_set_drvdata(pdev, NULL);
2158 
2159 	if (system_state == SYSTEM_POWER_OFF)
2160 		pci_set_power_state(pdev, PCI_D3hot);
2161 }
2162 
2163 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2164 					    pci_channel_state_t state)
2165 {
2166 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2167 	pci_ers_result_t ret;
2168 
2169 	dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2170 
2171 	if (state == pci_channel_io_perm_failure)
2172 		return PCI_ERS_RESULT_DISCONNECT;
2173 
2174 	if (!ae_dev || !ae_dev->ops) {
2175 		dev_err(&pdev->dev,
2176 			"Can't recover - error happened before device initialized\n");
2177 		return PCI_ERS_RESULT_NONE;
2178 	}
2179 
2180 	if (ae_dev->ops->handle_hw_ras_error)
2181 		ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2182 	else
2183 		return PCI_ERS_RESULT_NONE;
2184 
2185 	return ret;
2186 }
2187 
2188 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2189 {
2190 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2191 	const struct hnae3_ae_ops *ops;
2192 	enum hnae3_reset_type reset_type;
2193 	struct device *dev = &pdev->dev;
2194 
2195 	if (!ae_dev || !ae_dev->ops)
2196 		return PCI_ERS_RESULT_NONE;
2197 
2198 	ops = ae_dev->ops;
2199 	/* request the reset */
2200 	if (ops->reset_event && ops->get_reset_level &&
2201 	    ops->set_default_reset_request) {
2202 		if (ae_dev->hw_err_reset_req) {
2203 			reset_type = ops->get_reset_level(ae_dev,
2204 						&ae_dev->hw_err_reset_req);
2205 			ops->set_default_reset_request(ae_dev, reset_type);
2206 			dev_info(dev, "requesting reset due to PCI error\n");
2207 			ops->reset_event(pdev, NULL);
2208 		}
2209 
2210 		return PCI_ERS_RESULT_RECOVERED;
2211 	}
2212 
2213 	return PCI_ERS_RESULT_DISCONNECT;
2214 }
2215 
2216 static void hns3_reset_prepare(struct pci_dev *pdev)
2217 {
2218 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2219 
2220 	dev_info(&pdev->dev, "FLR prepare\n");
2221 	if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2222 		ae_dev->ops->flr_prepare(ae_dev);
2223 }
2224 
2225 static void hns3_reset_done(struct pci_dev *pdev)
2226 {
2227 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2228 
2229 	dev_info(&pdev->dev, "FLR done\n");
2230 	if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2231 		ae_dev->ops->flr_done(ae_dev);
2232 }
2233 
2234 static const struct pci_error_handlers hns3_err_handler = {
2235 	.error_detected = hns3_error_detected,
2236 	.slot_reset     = hns3_slot_reset,
2237 	.reset_prepare	= hns3_reset_prepare,
2238 	.reset_done	= hns3_reset_done,
2239 };
2240 
2241 static struct pci_driver hns3_driver = {
2242 	.name     = hns3_driver_name,
2243 	.id_table = hns3_pci_tbl,
2244 	.probe    = hns3_probe,
2245 	.remove   = hns3_remove,
2246 	.shutdown = hns3_shutdown,
2247 	.sriov_configure = hns3_pci_sriov_configure,
2248 	.err_handler    = &hns3_err_handler,
2249 };
2250 
2251 /* set default feature to hns3 */
2252 static void hns3_set_default_feature(struct net_device *netdev)
2253 {
2254 	struct hnae3_handle *h = hns3_get_handle(netdev);
2255 	struct pci_dev *pdev = h->pdev;
2256 
2257 	netdev->priv_flags |= IFF_UNICAST_FLT;
2258 
2259 	netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2260 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2261 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2262 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2263 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2264 		NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2265 
2266 	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2267 
2268 	netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2269 		NETIF_F_HW_VLAN_CTAG_FILTER |
2270 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2271 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2272 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2273 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2274 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2275 		NETIF_F_FRAGLIST;
2276 
2277 	netdev->vlan_features |=
2278 		NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2279 		NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2280 		NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2281 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2282 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2283 		NETIF_F_FRAGLIST;
2284 
2285 	netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2286 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2287 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2288 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2289 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2290 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2291 		NETIF_F_FRAGLIST;
2292 
2293 	if (pdev->revision >= 0x21) {
2294 		netdev->hw_features |= NETIF_F_GRO_HW;
2295 		netdev->features |= NETIF_F_GRO_HW;
2296 
2297 		if (!(h->flags & HNAE3_SUPPORT_VF)) {
2298 			netdev->hw_features |= NETIF_F_NTUPLE;
2299 			netdev->features |= NETIF_F_NTUPLE;
2300 		}
2301 	}
2302 }
2303 
2304 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2305 			     struct hns3_desc_cb *cb)
2306 {
2307 	unsigned int order = hns3_page_order(ring);
2308 	struct page *p;
2309 
2310 	p = dev_alloc_pages(order);
2311 	if (!p)
2312 		return -ENOMEM;
2313 
2314 	cb->priv = p;
2315 	cb->page_offset = 0;
2316 	cb->reuse_flag = 0;
2317 	cb->buf  = page_address(p);
2318 	cb->length = hns3_page_size(ring);
2319 	cb->type = DESC_TYPE_PAGE;
2320 
2321 	return 0;
2322 }
2323 
2324 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2325 			     struct hns3_desc_cb *cb)
2326 {
2327 	if (cb->type == DESC_TYPE_SKB)
2328 		dev_kfree_skb_any((struct sk_buff *)cb->priv);
2329 	else if (!HNAE3_IS_TX_RING(ring))
2330 		put_page((struct page *)cb->priv);
2331 	memset(cb, 0, sizeof(*cb));
2332 }
2333 
2334 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2335 {
2336 	cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2337 			       cb->length, ring_to_dma_dir(ring));
2338 
2339 	if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2340 		return -EIO;
2341 
2342 	return 0;
2343 }
2344 
2345 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2346 			      struct hns3_desc_cb *cb)
2347 {
2348 	if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
2349 		dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2350 				 ring_to_dma_dir(ring));
2351 	else if (cb->length)
2352 		dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2353 			       ring_to_dma_dir(ring));
2354 }
2355 
2356 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2357 {
2358 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2359 	ring->desc[i].addr = 0;
2360 }
2361 
2362 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2363 {
2364 	struct hns3_desc_cb *cb = &ring->desc_cb[i];
2365 
2366 	if (!ring->desc_cb[i].dma)
2367 		return;
2368 
2369 	hns3_buffer_detach(ring, i);
2370 	hns3_free_buffer(ring, cb);
2371 }
2372 
2373 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2374 {
2375 	int i;
2376 
2377 	for (i = 0; i < ring->desc_num; i++)
2378 		hns3_free_buffer_detach(ring, i);
2379 }
2380 
2381 /* free desc along with its attached buffer */
2382 static void hns3_free_desc(struct hns3_enet_ring *ring)
2383 {
2384 	int size = ring->desc_num * sizeof(ring->desc[0]);
2385 
2386 	hns3_free_buffers(ring);
2387 
2388 	if (ring->desc) {
2389 		dma_free_coherent(ring_to_dev(ring), size,
2390 				  ring->desc, ring->desc_dma_addr);
2391 		ring->desc = NULL;
2392 	}
2393 }
2394 
2395 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2396 {
2397 	int size = ring->desc_num * sizeof(ring->desc[0]);
2398 
2399 	ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2400 					&ring->desc_dma_addr, GFP_KERNEL);
2401 	if (!ring->desc)
2402 		return -ENOMEM;
2403 
2404 	return 0;
2405 }
2406 
2407 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2408 				   struct hns3_desc_cb *cb)
2409 {
2410 	int ret;
2411 
2412 	ret = hns3_alloc_buffer(ring, cb);
2413 	if (ret)
2414 		goto out;
2415 
2416 	ret = hns3_map_buffer(ring, cb);
2417 	if (ret)
2418 		goto out_with_buf;
2419 
2420 	return 0;
2421 
2422 out_with_buf:
2423 	hns3_free_buffer(ring, cb);
2424 out:
2425 	return ret;
2426 }
2427 
2428 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2429 {
2430 	int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2431 
2432 	if (ret)
2433 		return ret;
2434 
2435 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2436 
2437 	return 0;
2438 }
2439 
2440 /* Allocate memory for raw pkg, and map with dma */
2441 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2442 {
2443 	int i, j, ret;
2444 
2445 	for (i = 0; i < ring->desc_num; i++) {
2446 		ret = hns3_alloc_buffer_attach(ring, i);
2447 		if (ret)
2448 			goto out_buffer_fail;
2449 	}
2450 
2451 	return 0;
2452 
2453 out_buffer_fail:
2454 	for (j = i - 1; j >= 0; j--)
2455 		hns3_free_buffer_detach(ring, j);
2456 	return ret;
2457 }
2458 
2459 /* detach a in-used buffer and replace with a reserved one */
2460 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2461 				struct hns3_desc_cb *res_cb)
2462 {
2463 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2464 	ring->desc_cb[i] = *res_cb;
2465 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2466 	ring->desc[i].rx.bd_base_info = 0;
2467 }
2468 
2469 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2470 {
2471 	ring->desc_cb[i].reuse_flag = 0;
2472 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2473 					 ring->desc_cb[i].page_offset);
2474 	ring->desc[i].rx.bd_base_info = 0;
2475 }
2476 
2477 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2478 				  int *bytes, int *pkts)
2479 {
2480 	int ntc = ring->next_to_clean;
2481 	struct hns3_desc_cb *desc_cb;
2482 
2483 	while (head != ntc) {
2484 		desc_cb = &ring->desc_cb[ntc];
2485 		(*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2486 		(*bytes) += desc_cb->length;
2487 		/* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2488 		hns3_free_buffer_detach(ring, ntc);
2489 
2490 		if (++ntc == ring->desc_num)
2491 			ntc = 0;
2492 
2493 		/* Issue prefetch for next Tx descriptor */
2494 		prefetch(&ring->desc_cb[ntc]);
2495 	}
2496 
2497 	/* This smp_store_release() pairs with smp_load_acquire() in
2498 	 * ring_space called by hns3_nic_net_xmit.
2499 	 */
2500 	smp_store_release(&ring->next_to_clean, ntc);
2501 }
2502 
2503 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2504 {
2505 	int u = ring->next_to_use;
2506 	int c = ring->next_to_clean;
2507 
2508 	if (unlikely(h > ring->desc_num))
2509 		return 0;
2510 
2511 	return u > c ? (h > c && h <= u) : (h > c || h <= u);
2512 }
2513 
2514 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2515 {
2516 	struct net_device *netdev = ring_to_netdev(ring);
2517 	struct hns3_nic_priv *priv = netdev_priv(netdev);
2518 	struct netdev_queue *dev_queue;
2519 	int bytes, pkts;
2520 	int head;
2521 
2522 	head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2523 
2524 	if (is_ring_empty(ring) || head == ring->next_to_clean)
2525 		return; /* no data to poll */
2526 
2527 	rmb(); /* Make sure head is ready before touch any data */
2528 
2529 	if (unlikely(!is_valid_clean_head(ring, head))) {
2530 		hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head,
2531 			    ring->next_to_use, ring->next_to_clean);
2532 
2533 		u64_stats_update_begin(&ring->syncp);
2534 		ring->stats.io_err_cnt++;
2535 		u64_stats_update_end(&ring->syncp);
2536 		return;
2537 	}
2538 
2539 	bytes = 0;
2540 	pkts = 0;
2541 	hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2542 
2543 	ring->tqp_vector->tx_group.total_bytes += bytes;
2544 	ring->tqp_vector->tx_group.total_packets += pkts;
2545 
2546 	u64_stats_update_begin(&ring->syncp);
2547 	ring->stats.tx_bytes += bytes;
2548 	ring->stats.tx_pkts += pkts;
2549 	u64_stats_update_end(&ring->syncp);
2550 
2551 	dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2552 	netdev_tx_completed_queue(dev_queue, pkts, bytes);
2553 
2554 	if (unlikely(netif_carrier_ok(netdev) &&
2555 		     ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2556 		/* Make sure that anybody stopping the queue after this
2557 		 * sees the new next_to_clean.
2558 		 */
2559 		smp_mb();
2560 		if (netif_tx_queue_stopped(dev_queue) &&
2561 		    !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2562 			netif_tx_wake_queue(dev_queue);
2563 			ring->stats.restart_queue++;
2564 		}
2565 	}
2566 }
2567 
2568 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2569 {
2570 	int ntc = ring->next_to_clean;
2571 	int ntu = ring->next_to_use;
2572 
2573 	return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2574 }
2575 
2576 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2577 				      int cleand_count)
2578 {
2579 	struct hns3_desc_cb *desc_cb;
2580 	struct hns3_desc_cb res_cbs;
2581 	int i, ret;
2582 
2583 	for (i = 0; i < cleand_count; i++) {
2584 		desc_cb = &ring->desc_cb[ring->next_to_use];
2585 		if (desc_cb->reuse_flag) {
2586 			u64_stats_update_begin(&ring->syncp);
2587 			ring->stats.reuse_pg_cnt++;
2588 			u64_stats_update_end(&ring->syncp);
2589 
2590 			hns3_reuse_buffer(ring, ring->next_to_use);
2591 		} else {
2592 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
2593 			if (ret) {
2594 				u64_stats_update_begin(&ring->syncp);
2595 				ring->stats.sw_err_cnt++;
2596 				u64_stats_update_end(&ring->syncp);
2597 
2598 				hns3_rl_err(ring_to_netdev(ring),
2599 					    "alloc rx buffer failed: %d\n",
2600 					    ret);
2601 				break;
2602 			}
2603 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2604 
2605 			u64_stats_update_begin(&ring->syncp);
2606 			ring->stats.non_reuse_pg++;
2607 			u64_stats_update_end(&ring->syncp);
2608 		}
2609 
2610 		ring_ptr_move_fw(ring, next_to_use);
2611 	}
2612 
2613 	wmb(); /* Make all data has been write before submit */
2614 	writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2615 }
2616 
2617 static bool hns3_page_is_reusable(struct page *page)
2618 {
2619 	return page_to_nid(page) == numa_mem_id() &&
2620 		!page_is_pfmemalloc(page);
2621 }
2622 
2623 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2624 				struct hns3_enet_ring *ring, int pull_len,
2625 				struct hns3_desc_cb *desc_cb)
2626 {
2627 	struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2628 	int size = le16_to_cpu(desc->rx.size);
2629 	u32 truesize = hns3_buf_size(ring);
2630 
2631 	skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2632 			size - pull_len, truesize);
2633 
2634 	/* Avoid re-using remote pages, or the stack is still using the page
2635 	 * when page_offset rollback to zero, flag default unreuse
2636 	 */
2637 	if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
2638 	    (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2639 		return;
2640 
2641 	/* Move offset up to the next cache line */
2642 	desc_cb->page_offset += truesize;
2643 
2644 	if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2645 		desc_cb->reuse_flag = 1;
2646 		/* Bump ref count on page before it is given */
2647 		get_page(desc_cb->priv);
2648 	} else if (page_count(desc_cb->priv) == 1) {
2649 		desc_cb->reuse_flag = 1;
2650 		desc_cb->page_offset = 0;
2651 		get_page(desc_cb->priv);
2652 	}
2653 }
2654 
2655 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2656 {
2657 	__be16 type = skb->protocol;
2658 	struct tcphdr *th;
2659 	int depth = 0;
2660 
2661 	while (eth_type_vlan(type)) {
2662 		struct vlan_hdr *vh;
2663 
2664 		if ((depth + VLAN_HLEN) > skb_headlen(skb))
2665 			return -EFAULT;
2666 
2667 		vh = (struct vlan_hdr *)(skb->data + depth);
2668 		type = vh->h_vlan_encapsulated_proto;
2669 		depth += VLAN_HLEN;
2670 	}
2671 
2672 	skb_set_network_header(skb, depth);
2673 
2674 	if (type == htons(ETH_P_IP)) {
2675 		const struct iphdr *iph = ip_hdr(skb);
2676 
2677 		depth += sizeof(struct iphdr);
2678 		skb_set_transport_header(skb, depth);
2679 		th = tcp_hdr(skb);
2680 		th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2681 					  iph->daddr, 0);
2682 	} else if (type == htons(ETH_P_IPV6)) {
2683 		const struct ipv6hdr *iph = ipv6_hdr(skb);
2684 
2685 		depth += sizeof(struct ipv6hdr);
2686 		skb_set_transport_header(skb, depth);
2687 		th = tcp_hdr(skb);
2688 		th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2689 					  &iph->daddr, 0);
2690 	} else {
2691 		hns3_rl_err(skb->dev,
2692 			    "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2693 			    be16_to_cpu(type), depth);
2694 		return -EFAULT;
2695 	}
2696 
2697 	skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2698 	if (th->cwr)
2699 		skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2700 
2701 	if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2702 		skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2703 
2704 	skb->csum_start = (unsigned char *)th - skb->head;
2705 	skb->csum_offset = offsetof(struct tcphdr, check);
2706 	skb->ip_summed = CHECKSUM_PARTIAL;
2707 
2708 	trace_hns3_gro(skb);
2709 
2710 	return 0;
2711 }
2712 
2713 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2714 			     u32 l234info, u32 bd_base_info, u32 ol_info)
2715 {
2716 	struct net_device *netdev = ring_to_netdev(ring);
2717 	int l3_type, l4_type;
2718 	int ol4_type;
2719 
2720 	skb->ip_summed = CHECKSUM_NONE;
2721 
2722 	skb_checksum_none_assert(skb);
2723 
2724 	if (!(netdev->features & NETIF_F_RXCSUM))
2725 		return;
2726 
2727 	/* check if hardware has done checksum */
2728 	if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2729 		return;
2730 
2731 	if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2732 				 BIT(HNS3_RXD_OL3E_B) |
2733 				 BIT(HNS3_RXD_OL4E_B)))) {
2734 		u64_stats_update_begin(&ring->syncp);
2735 		ring->stats.l3l4_csum_err++;
2736 		u64_stats_update_end(&ring->syncp);
2737 
2738 		return;
2739 	}
2740 
2741 	ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2742 				   HNS3_RXD_OL4ID_S);
2743 	switch (ol4_type) {
2744 	case HNS3_OL4_TYPE_MAC_IN_UDP:
2745 	case HNS3_OL4_TYPE_NVGRE:
2746 		skb->csum_level = 1;
2747 		/* fall through */
2748 	case HNS3_OL4_TYPE_NO_TUN:
2749 		l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2750 					  HNS3_RXD_L3ID_S);
2751 		l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2752 					  HNS3_RXD_L4ID_S);
2753 
2754 		/* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2755 		if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2756 		     l3_type == HNS3_L3_TYPE_IPV6) &&
2757 		    (l4_type == HNS3_L4_TYPE_UDP ||
2758 		     l4_type == HNS3_L4_TYPE_TCP ||
2759 		     l4_type == HNS3_L4_TYPE_SCTP))
2760 			skb->ip_summed = CHECKSUM_UNNECESSARY;
2761 		break;
2762 	default:
2763 		break;
2764 	}
2765 }
2766 
2767 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2768 {
2769 	if (skb_has_frag_list(skb))
2770 		napi_gro_flush(&ring->tqp_vector->napi, false);
2771 
2772 	napi_gro_receive(&ring->tqp_vector->napi, skb);
2773 }
2774 
2775 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2776 				struct hns3_desc *desc, u32 l234info,
2777 				u16 *vlan_tag)
2778 {
2779 	struct hnae3_handle *handle = ring->tqp->handle;
2780 	struct pci_dev *pdev = ring->tqp->handle->pdev;
2781 
2782 	if (pdev->revision == 0x20) {
2783 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2784 		if (!(*vlan_tag & VLAN_VID_MASK))
2785 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2786 
2787 		return (*vlan_tag != 0);
2788 	}
2789 
2790 #define HNS3_STRP_OUTER_VLAN	0x1
2791 #define HNS3_STRP_INNER_VLAN	0x2
2792 #define HNS3_STRP_BOTH		0x3
2793 
2794 	/* Hardware always insert VLAN tag into RX descriptor when
2795 	 * remove the tag from packet, driver needs to determine
2796 	 * reporting which tag to stack.
2797 	 */
2798 	switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2799 				HNS3_RXD_STRP_TAGP_S)) {
2800 	case HNS3_STRP_OUTER_VLAN:
2801 		if (handle->port_base_vlan_state !=
2802 				HNAE3_PORT_BASE_VLAN_DISABLE)
2803 			return false;
2804 
2805 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2806 		return true;
2807 	case HNS3_STRP_INNER_VLAN:
2808 		if (handle->port_base_vlan_state !=
2809 				HNAE3_PORT_BASE_VLAN_DISABLE)
2810 			return false;
2811 
2812 		*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2813 		return true;
2814 	case HNS3_STRP_BOTH:
2815 		if (handle->port_base_vlan_state ==
2816 				HNAE3_PORT_BASE_VLAN_DISABLE)
2817 			*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2818 		else
2819 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2820 
2821 		return true;
2822 	default:
2823 		return false;
2824 	}
2825 }
2826 
2827 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2828 			  unsigned char *va)
2829 {
2830 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2831 	struct net_device *netdev = ring_to_netdev(ring);
2832 	struct sk_buff *skb;
2833 
2834 	ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2835 	skb = ring->skb;
2836 	if (unlikely(!skb)) {
2837 		hns3_rl_err(netdev, "alloc rx skb fail\n");
2838 
2839 		u64_stats_update_begin(&ring->syncp);
2840 		ring->stats.sw_err_cnt++;
2841 		u64_stats_update_end(&ring->syncp);
2842 
2843 		return -ENOMEM;
2844 	}
2845 
2846 	trace_hns3_rx_desc(ring);
2847 	prefetchw(skb->data);
2848 
2849 	ring->pending_buf = 1;
2850 	ring->frag_num = 0;
2851 	ring->tail_skb = NULL;
2852 	if (length <= HNS3_RX_HEAD_SIZE) {
2853 		memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2854 
2855 		/* We can reuse buffer as-is, just make sure it is local */
2856 		if (likely(hns3_page_is_reusable(desc_cb->priv)))
2857 			desc_cb->reuse_flag = 1;
2858 		else /* This page cannot be reused so discard it */
2859 			put_page(desc_cb->priv);
2860 
2861 		ring_ptr_move_fw(ring, next_to_clean);
2862 		return 0;
2863 	}
2864 	u64_stats_update_begin(&ring->syncp);
2865 	ring->stats.seg_pkt_cnt++;
2866 	u64_stats_update_end(&ring->syncp);
2867 
2868 	ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2869 	__skb_put(skb, ring->pull_len);
2870 	hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2871 			    desc_cb);
2872 	ring_ptr_move_fw(ring, next_to_clean);
2873 
2874 	return 0;
2875 }
2876 
2877 static int hns3_add_frag(struct hns3_enet_ring *ring)
2878 {
2879 	struct sk_buff *skb = ring->skb;
2880 	struct sk_buff *head_skb = skb;
2881 	struct sk_buff *new_skb;
2882 	struct hns3_desc_cb *desc_cb;
2883 	struct hns3_desc *desc;
2884 	u32 bd_base_info;
2885 
2886 	do {
2887 		desc = &ring->desc[ring->next_to_clean];
2888 		desc_cb = &ring->desc_cb[ring->next_to_clean];
2889 		bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2890 		/* make sure HW write desc complete */
2891 		dma_rmb();
2892 		if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2893 			return -ENXIO;
2894 
2895 		if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2896 			new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
2897 			if (unlikely(!new_skb)) {
2898 				hns3_rl_err(ring_to_netdev(ring),
2899 					    "alloc rx fraglist skb fail\n");
2900 				return -ENXIO;
2901 			}
2902 			ring->frag_num = 0;
2903 
2904 			if (ring->tail_skb) {
2905 				ring->tail_skb->next = new_skb;
2906 				ring->tail_skb = new_skb;
2907 			} else {
2908 				skb_shinfo(skb)->frag_list = new_skb;
2909 				ring->tail_skb = new_skb;
2910 			}
2911 		}
2912 
2913 		if (ring->tail_skb) {
2914 			head_skb->truesize += hns3_buf_size(ring);
2915 			head_skb->data_len += le16_to_cpu(desc->rx.size);
2916 			head_skb->len += le16_to_cpu(desc->rx.size);
2917 			skb = ring->tail_skb;
2918 		}
2919 
2920 		hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2921 		trace_hns3_rx_desc(ring);
2922 		ring_ptr_move_fw(ring, next_to_clean);
2923 		ring->pending_buf++;
2924 	} while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
2925 
2926 	return 0;
2927 }
2928 
2929 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2930 				     struct sk_buff *skb, u32 l234info,
2931 				     u32 bd_base_info, u32 ol_info)
2932 {
2933 	u32 l3_type;
2934 
2935 	skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2936 						    HNS3_RXD_GRO_SIZE_M,
2937 						    HNS3_RXD_GRO_SIZE_S);
2938 	/* if there is no HW GRO, do not set gro params */
2939 	if (!skb_shinfo(skb)->gso_size) {
2940 		hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2941 		return 0;
2942 	}
2943 
2944 	NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2945 						  HNS3_RXD_GRO_COUNT_M,
2946 						  HNS3_RXD_GRO_COUNT_S);
2947 
2948 	l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2949 	if (l3_type == HNS3_L3_TYPE_IPV4)
2950 		skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2951 	else if (l3_type == HNS3_L3_TYPE_IPV6)
2952 		skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2953 	else
2954 		return -EFAULT;
2955 
2956 	return  hns3_gro_complete(skb, l234info);
2957 }
2958 
2959 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2960 				     struct sk_buff *skb, u32 rss_hash)
2961 {
2962 	struct hnae3_handle *handle = ring->tqp->handle;
2963 	enum pkt_hash_types rss_type;
2964 
2965 	if (rss_hash)
2966 		rss_type = handle->kinfo.rss_type;
2967 	else
2968 		rss_type = PKT_HASH_TYPE_NONE;
2969 
2970 	skb_set_hash(skb, rss_hash, rss_type);
2971 }
2972 
2973 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2974 {
2975 	struct net_device *netdev = ring_to_netdev(ring);
2976 	enum hns3_pkt_l2t_type l2_frame_type;
2977 	u32 bd_base_info, l234info, ol_info;
2978 	struct hns3_desc *desc;
2979 	unsigned int len;
2980 	int pre_ntc, ret;
2981 
2982 	/* bdinfo handled below is only valid on the last BD of the
2983 	 * current packet, and ring->next_to_clean indicates the first
2984 	 * descriptor of next packet, so need - 1 below.
2985 	 */
2986 	pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2987 					(ring->desc_num - 1);
2988 	desc = &ring->desc[pre_ntc];
2989 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2990 	l234info = le32_to_cpu(desc->rx.l234_info);
2991 	ol_info = le32_to_cpu(desc->rx.ol_info);
2992 
2993 	/* Based on hw strategy, the tag offloaded will be stored at
2994 	 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2995 	 * in one layer tag case.
2996 	 */
2997 	if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2998 		u16 vlan_tag;
2999 
3000 		if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
3001 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3002 					       vlan_tag);
3003 	}
3004 
3005 	if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
3006 				  BIT(HNS3_RXD_L2E_B))))) {
3007 		u64_stats_update_begin(&ring->syncp);
3008 		if (l234info & BIT(HNS3_RXD_L2E_B))
3009 			ring->stats.l2_err++;
3010 		else
3011 			ring->stats.err_pkt_len++;
3012 		u64_stats_update_end(&ring->syncp);
3013 
3014 		return -EFAULT;
3015 	}
3016 
3017 	len = skb->len;
3018 
3019 	/* Do update ip stack process */
3020 	skb->protocol = eth_type_trans(skb, netdev);
3021 
3022 	/* This is needed in order to enable forwarding support */
3023 	ret = hns3_set_gro_and_checksum(ring, skb, l234info,
3024 					bd_base_info, ol_info);
3025 	if (unlikely(ret)) {
3026 		u64_stats_update_begin(&ring->syncp);
3027 		ring->stats.rx_err_cnt++;
3028 		u64_stats_update_end(&ring->syncp);
3029 		return ret;
3030 	}
3031 
3032 	l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3033 					HNS3_RXD_DMAC_S);
3034 
3035 	u64_stats_update_begin(&ring->syncp);
3036 	ring->stats.rx_pkts++;
3037 	ring->stats.rx_bytes += len;
3038 
3039 	if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3040 		ring->stats.rx_multicast++;
3041 
3042 	u64_stats_update_end(&ring->syncp);
3043 
3044 	ring->tqp_vector->rx_group.total_bytes += len;
3045 
3046 	hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3047 	return 0;
3048 }
3049 
3050 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3051 {
3052 	struct sk_buff *skb = ring->skb;
3053 	struct hns3_desc_cb *desc_cb;
3054 	struct hns3_desc *desc;
3055 	unsigned int length;
3056 	u32 bd_base_info;
3057 	int ret;
3058 
3059 	desc = &ring->desc[ring->next_to_clean];
3060 	desc_cb = &ring->desc_cb[ring->next_to_clean];
3061 
3062 	prefetch(desc);
3063 
3064 	length = le16_to_cpu(desc->rx.size);
3065 	bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3066 
3067 	/* Check valid BD */
3068 	if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3069 		return -ENXIO;
3070 
3071 	if (!skb)
3072 		ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3073 
3074 	/* Prefetch first cache line of first page
3075 	 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3076 	 * line size is 64B so need to prefetch twice to make it 128B. But in
3077 	 * actual we can have greater size of caches with 128B Level 1 cache
3078 	 * lines. In such a case, single fetch would suffice to cache in the
3079 	 * relevant part of the header.
3080 	 */
3081 	prefetch(ring->va);
3082 #if L1_CACHE_BYTES < 128
3083 	prefetch(ring->va + L1_CACHE_BYTES);
3084 #endif
3085 
3086 	if (!skb) {
3087 		ret = hns3_alloc_skb(ring, length, ring->va);
3088 		skb = ring->skb;
3089 
3090 		if (ret < 0) /* alloc buffer fail */
3091 			return ret;
3092 		if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
3093 			ret = hns3_add_frag(ring);
3094 			if (ret)
3095 				return ret;
3096 		}
3097 	} else {
3098 		ret = hns3_add_frag(ring);
3099 		if (ret)
3100 			return ret;
3101 	}
3102 
3103 	/* As the head data may be changed when GRO enable, copy
3104 	 * the head data in after other data rx completed
3105 	 */
3106 	if (skb->len > HNS3_RX_HEAD_SIZE)
3107 		memcpy(skb->data, ring->va,
3108 		       ALIGN(ring->pull_len, sizeof(long)));
3109 
3110 	ret = hns3_handle_bdinfo(ring, skb);
3111 	if (unlikely(ret)) {
3112 		dev_kfree_skb_any(skb);
3113 		return ret;
3114 	}
3115 
3116 	skb_record_rx_queue(skb, ring->tqp->tqp_index);
3117 	return 0;
3118 }
3119 
3120 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3121 		       void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3122 {
3123 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3124 	int unused_count = hns3_desc_unused(ring);
3125 	int recv_pkts = 0;
3126 	int recv_bds = 0;
3127 	int err, num;
3128 
3129 	num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3130 	num -= unused_count;
3131 	unused_count -= ring->pending_buf;
3132 
3133 	if (num <= 0)
3134 		goto out;
3135 
3136 	rmb(); /* Make sure num taken effect before the other data is touched */
3137 
3138 	while (recv_pkts < budget && recv_bds < num) {
3139 		/* Reuse or realloc buffers */
3140 		if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3141 			hns3_nic_alloc_rx_buffers(ring, unused_count);
3142 			unused_count = hns3_desc_unused(ring) -
3143 					ring->pending_buf;
3144 		}
3145 
3146 		/* Poll one pkt */
3147 		err = hns3_handle_rx_bd(ring);
3148 		/* Do not get FE for the packet or failed to alloc skb */
3149 		if (unlikely(!ring->skb || err == -ENXIO)) {
3150 			goto out;
3151 		} else if (likely(!err)) {
3152 			rx_fn(ring, ring->skb);
3153 			recv_pkts++;
3154 		}
3155 
3156 		recv_bds += ring->pending_buf;
3157 		unused_count += ring->pending_buf;
3158 		ring->skb = NULL;
3159 		ring->pending_buf = 0;
3160 	}
3161 
3162 out:
3163 	/* Make all data has been write before submit */
3164 	if (unused_count > 0)
3165 		hns3_nic_alloc_rx_buffers(ring, unused_count);
3166 
3167 	return recv_pkts;
3168 }
3169 
3170 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3171 {
3172 #define HNS3_RX_LOW_BYTE_RATE 10000
3173 #define HNS3_RX_MID_BYTE_RATE 20000
3174 #define HNS3_RX_ULTRA_PACKET_RATE 40
3175 
3176 	enum hns3_flow_level_range new_flow_level;
3177 	struct hns3_enet_tqp_vector *tqp_vector;
3178 	int packets_per_msecs, bytes_per_msecs;
3179 	u32 time_passed_ms;
3180 
3181 	tqp_vector = ring_group->ring->tqp_vector;
3182 	time_passed_ms =
3183 		jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3184 	if (!time_passed_ms)
3185 		return false;
3186 
3187 	do_div(ring_group->total_packets, time_passed_ms);
3188 	packets_per_msecs = ring_group->total_packets;
3189 
3190 	do_div(ring_group->total_bytes, time_passed_ms);
3191 	bytes_per_msecs = ring_group->total_bytes;
3192 
3193 	new_flow_level = ring_group->coal.flow_level;
3194 
3195 	/* Simple throttlerate management
3196 	 * 0-10MB/s   lower     (50000 ints/s)
3197 	 * 10-20MB/s   middle    (20000 ints/s)
3198 	 * 20-1249MB/s high      (18000 ints/s)
3199 	 * > 40000pps  ultra     (8000 ints/s)
3200 	 */
3201 	switch (new_flow_level) {
3202 	case HNS3_FLOW_LOW:
3203 		if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3204 			new_flow_level = HNS3_FLOW_MID;
3205 		break;
3206 	case HNS3_FLOW_MID:
3207 		if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3208 			new_flow_level = HNS3_FLOW_HIGH;
3209 		else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3210 			new_flow_level = HNS3_FLOW_LOW;
3211 		break;
3212 	case HNS3_FLOW_HIGH:
3213 	case HNS3_FLOW_ULTRA:
3214 	default:
3215 		if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3216 			new_flow_level = HNS3_FLOW_MID;
3217 		break;
3218 	}
3219 
3220 	if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3221 	    &tqp_vector->rx_group == ring_group)
3222 		new_flow_level = HNS3_FLOW_ULTRA;
3223 
3224 	ring_group->total_bytes = 0;
3225 	ring_group->total_packets = 0;
3226 	ring_group->coal.flow_level = new_flow_level;
3227 
3228 	return true;
3229 }
3230 
3231 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3232 {
3233 	struct hns3_enet_tqp_vector *tqp_vector;
3234 	u16 new_int_gl;
3235 
3236 	if (!ring_group->ring)
3237 		return false;
3238 
3239 	tqp_vector = ring_group->ring->tqp_vector;
3240 	if (!tqp_vector->last_jiffies)
3241 		return false;
3242 
3243 	if (ring_group->total_packets == 0) {
3244 		ring_group->coal.int_gl = HNS3_INT_GL_50K;
3245 		ring_group->coal.flow_level = HNS3_FLOW_LOW;
3246 		return true;
3247 	}
3248 
3249 	if (!hns3_get_new_flow_lvl(ring_group))
3250 		return false;
3251 
3252 	new_int_gl = ring_group->coal.int_gl;
3253 	switch (ring_group->coal.flow_level) {
3254 	case HNS3_FLOW_LOW:
3255 		new_int_gl = HNS3_INT_GL_50K;
3256 		break;
3257 	case HNS3_FLOW_MID:
3258 		new_int_gl = HNS3_INT_GL_20K;
3259 		break;
3260 	case HNS3_FLOW_HIGH:
3261 		new_int_gl = HNS3_INT_GL_18K;
3262 		break;
3263 	case HNS3_FLOW_ULTRA:
3264 		new_int_gl = HNS3_INT_GL_8K;
3265 		break;
3266 	default:
3267 		break;
3268 	}
3269 
3270 	if (new_int_gl != ring_group->coal.int_gl) {
3271 		ring_group->coal.int_gl = new_int_gl;
3272 		return true;
3273 	}
3274 	return false;
3275 }
3276 
3277 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3278 {
3279 	struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3280 	struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3281 	bool rx_update, tx_update;
3282 
3283 	/* update param every 1000ms */
3284 	if (time_before(jiffies,
3285 			tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3286 		return;
3287 
3288 	if (rx_group->coal.gl_adapt_enable) {
3289 		rx_update = hns3_get_new_int_gl(rx_group);
3290 		if (rx_update)
3291 			hns3_set_vector_coalesce_rx_gl(tqp_vector,
3292 						       rx_group->coal.int_gl);
3293 	}
3294 
3295 	if (tx_group->coal.gl_adapt_enable) {
3296 		tx_update = hns3_get_new_int_gl(tx_group);
3297 		if (tx_update)
3298 			hns3_set_vector_coalesce_tx_gl(tqp_vector,
3299 						       tx_group->coal.int_gl);
3300 	}
3301 
3302 	tqp_vector->last_jiffies = jiffies;
3303 }
3304 
3305 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3306 {
3307 	struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3308 	struct hns3_enet_ring *ring;
3309 	int rx_pkt_total = 0;
3310 
3311 	struct hns3_enet_tqp_vector *tqp_vector =
3312 		container_of(napi, struct hns3_enet_tqp_vector, napi);
3313 	bool clean_complete = true;
3314 	int rx_budget = budget;
3315 
3316 	if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3317 		napi_complete(napi);
3318 		return 0;
3319 	}
3320 
3321 	/* Since the actual Tx work is minimal, we can give the Tx a larger
3322 	 * budget and be more aggressive about cleaning up the Tx descriptors.
3323 	 */
3324 	hns3_for_each_ring(ring, tqp_vector->tx_group)
3325 		hns3_clean_tx_ring(ring);
3326 
3327 	/* make sure rx ring budget not smaller than 1 */
3328 	if (tqp_vector->num_tqps > 1)
3329 		rx_budget = max(budget / tqp_vector->num_tqps, 1);
3330 
3331 	hns3_for_each_ring(ring, tqp_vector->rx_group) {
3332 		int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3333 						    hns3_rx_skb);
3334 
3335 		if (rx_cleaned >= rx_budget)
3336 			clean_complete = false;
3337 
3338 		rx_pkt_total += rx_cleaned;
3339 	}
3340 
3341 	tqp_vector->rx_group.total_packets += rx_pkt_total;
3342 
3343 	if (!clean_complete)
3344 		return budget;
3345 
3346 	if (napi_complete(napi) &&
3347 	    likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3348 		hns3_update_new_int_gl(tqp_vector);
3349 		hns3_mask_vector_irq(tqp_vector, 1);
3350 	}
3351 
3352 	return rx_pkt_total;
3353 }
3354 
3355 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3356 				      struct hnae3_ring_chain_node *head)
3357 {
3358 	struct pci_dev *pdev = tqp_vector->handle->pdev;
3359 	struct hnae3_ring_chain_node *cur_chain = head;
3360 	struct hnae3_ring_chain_node *chain;
3361 	struct hns3_enet_ring *tx_ring;
3362 	struct hns3_enet_ring *rx_ring;
3363 
3364 	tx_ring = tqp_vector->tx_group.ring;
3365 	if (tx_ring) {
3366 		cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3367 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3368 			      HNAE3_RING_TYPE_TX);
3369 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3370 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3371 
3372 		cur_chain->next = NULL;
3373 
3374 		while (tx_ring->next) {
3375 			tx_ring = tx_ring->next;
3376 
3377 			chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3378 					     GFP_KERNEL);
3379 			if (!chain)
3380 				goto err_free_chain;
3381 
3382 			cur_chain->next = chain;
3383 			chain->tqp_index = tx_ring->tqp->tqp_index;
3384 			hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3385 				      HNAE3_RING_TYPE_TX);
3386 			hnae3_set_field(chain->int_gl_idx,
3387 					HNAE3_RING_GL_IDX_M,
3388 					HNAE3_RING_GL_IDX_S,
3389 					HNAE3_RING_GL_TX);
3390 
3391 			cur_chain = chain;
3392 		}
3393 	}
3394 
3395 	rx_ring = tqp_vector->rx_group.ring;
3396 	if (!tx_ring && rx_ring) {
3397 		cur_chain->next = NULL;
3398 		cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3399 		hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3400 			      HNAE3_RING_TYPE_RX);
3401 		hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3402 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3403 
3404 		rx_ring = rx_ring->next;
3405 	}
3406 
3407 	while (rx_ring) {
3408 		chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3409 		if (!chain)
3410 			goto err_free_chain;
3411 
3412 		cur_chain->next = chain;
3413 		chain->tqp_index = rx_ring->tqp->tqp_index;
3414 		hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3415 			      HNAE3_RING_TYPE_RX);
3416 		hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3417 				HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3418 
3419 		cur_chain = chain;
3420 
3421 		rx_ring = rx_ring->next;
3422 	}
3423 
3424 	return 0;
3425 
3426 err_free_chain:
3427 	cur_chain = head->next;
3428 	while (cur_chain) {
3429 		chain = cur_chain->next;
3430 		devm_kfree(&pdev->dev, cur_chain);
3431 		cur_chain = chain;
3432 	}
3433 	head->next = NULL;
3434 
3435 	return -ENOMEM;
3436 }
3437 
3438 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3439 					struct hnae3_ring_chain_node *head)
3440 {
3441 	struct pci_dev *pdev = tqp_vector->handle->pdev;
3442 	struct hnae3_ring_chain_node *chain_tmp, *chain;
3443 
3444 	chain = head->next;
3445 
3446 	while (chain) {
3447 		chain_tmp = chain->next;
3448 		devm_kfree(&pdev->dev, chain);
3449 		chain = chain_tmp;
3450 	}
3451 }
3452 
3453 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3454 				   struct hns3_enet_ring *ring)
3455 {
3456 	ring->next = group->ring;
3457 	group->ring = ring;
3458 
3459 	group->count++;
3460 }
3461 
3462 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3463 {
3464 	struct pci_dev *pdev = priv->ae_handle->pdev;
3465 	struct hns3_enet_tqp_vector *tqp_vector;
3466 	int num_vectors = priv->vector_num;
3467 	int numa_node;
3468 	int vector_i;
3469 
3470 	numa_node = dev_to_node(&pdev->dev);
3471 
3472 	for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3473 		tqp_vector = &priv->tqp_vector[vector_i];
3474 		cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3475 				&tqp_vector->affinity_mask);
3476 	}
3477 }
3478 
3479 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3480 {
3481 	struct hnae3_ring_chain_node vector_ring_chain;
3482 	struct hnae3_handle *h = priv->ae_handle;
3483 	struct hns3_enet_tqp_vector *tqp_vector;
3484 	int ret = 0;
3485 	int i;
3486 
3487 	hns3_nic_set_cpumask(priv);
3488 
3489 	for (i = 0; i < priv->vector_num; i++) {
3490 		tqp_vector = &priv->tqp_vector[i];
3491 		hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3492 		tqp_vector->num_tqps = 0;
3493 	}
3494 
3495 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3496 		u16 vector_i = i % priv->vector_num;
3497 		u16 tqp_num = h->kinfo.num_tqps;
3498 
3499 		tqp_vector = &priv->tqp_vector[vector_i];
3500 
3501 		hns3_add_ring_to_group(&tqp_vector->tx_group,
3502 				       &priv->ring[i]);
3503 
3504 		hns3_add_ring_to_group(&tqp_vector->rx_group,
3505 				       &priv->ring[i + tqp_num]);
3506 
3507 		priv->ring[i].tqp_vector = tqp_vector;
3508 		priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3509 		tqp_vector->num_tqps++;
3510 	}
3511 
3512 	for (i = 0; i < priv->vector_num; i++) {
3513 		tqp_vector = &priv->tqp_vector[i];
3514 
3515 		tqp_vector->rx_group.total_bytes = 0;
3516 		tqp_vector->rx_group.total_packets = 0;
3517 		tqp_vector->tx_group.total_bytes = 0;
3518 		tqp_vector->tx_group.total_packets = 0;
3519 		tqp_vector->handle = h;
3520 
3521 		ret = hns3_get_vector_ring_chain(tqp_vector,
3522 						 &vector_ring_chain);
3523 		if (ret)
3524 			goto map_ring_fail;
3525 
3526 		ret = h->ae_algo->ops->map_ring_to_vector(h,
3527 			tqp_vector->vector_irq, &vector_ring_chain);
3528 
3529 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3530 
3531 		if (ret)
3532 			goto map_ring_fail;
3533 
3534 		netif_napi_add(priv->netdev, &tqp_vector->napi,
3535 			       hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3536 	}
3537 
3538 	return 0;
3539 
3540 map_ring_fail:
3541 	while (i--)
3542 		netif_napi_del(&priv->tqp_vector[i].napi);
3543 
3544 	return ret;
3545 }
3546 
3547 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3548 {
3549 #define HNS3_VECTOR_PF_MAX_NUM		64
3550 
3551 	struct hnae3_handle *h = priv->ae_handle;
3552 	struct hns3_enet_tqp_vector *tqp_vector;
3553 	struct hnae3_vector_info *vector;
3554 	struct pci_dev *pdev = h->pdev;
3555 	u16 tqp_num = h->kinfo.num_tqps;
3556 	u16 vector_num;
3557 	int ret = 0;
3558 	u16 i;
3559 
3560 	/* RSS size, cpu online and vector_num should be the same */
3561 	/* Should consider 2p/4p later */
3562 	vector_num = min_t(u16, num_online_cpus(), tqp_num);
3563 	vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3564 
3565 	vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3566 			      GFP_KERNEL);
3567 	if (!vector)
3568 		return -ENOMEM;
3569 
3570 	/* save the actual available vector number */
3571 	vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3572 
3573 	priv->vector_num = vector_num;
3574 	priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3575 		devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3576 			     GFP_KERNEL);
3577 	if (!priv->tqp_vector) {
3578 		ret = -ENOMEM;
3579 		goto out;
3580 	}
3581 
3582 	for (i = 0; i < priv->vector_num; i++) {
3583 		tqp_vector = &priv->tqp_vector[i];
3584 		tqp_vector->idx = i;
3585 		tqp_vector->mask_addr = vector[i].io_addr;
3586 		tqp_vector->vector_irq = vector[i].vector;
3587 		hns3_vector_gl_rl_init(tqp_vector, priv);
3588 	}
3589 
3590 out:
3591 	devm_kfree(&pdev->dev, vector);
3592 	return ret;
3593 }
3594 
3595 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3596 {
3597 	group->ring = NULL;
3598 	group->count = 0;
3599 }
3600 
3601 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3602 {
3603 	struct hnae3_ring_chain_node vector_ring_chain;
3604 	struct hnae3_handle *h = priv->ae_handle;
3605 	struct hns3_enet_tqp_vector *tqp_vector;
3606 	int i;
3607 
3608 	for (i = 0; i < priv->vector_num; i++) {
3609 		tqp_vector = &priv->tqp_vector[i];
3610 
3611 		if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3612 			continue;
3613 
3614 		/* Since the mapping can be overwritten, when fail to get the
3615 		 * chain between vector and ring, we should go on to deal with
3616 		 * the remaining options.
3617 		 */
3618 		if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain))
3619 			dev_warn(priv->dev, "failed to get ring chain\n");
3620 
3621 		h->ae_algo->ops->unmap_ring_from_vector(h,
3622 			tqp_vector->vector_irq, &vector_ring_chain);
3623 
3624 		hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3625 
3626 		hns3_clear_ring_group(&tqp_vector->rx_group);
3627 		hns3_clear_ring_group(&tqp_vector->tx_group);
3628 		netif_napi_del(&priv->tqp_vector[i].napi);
3629 	}
3630 }
3631 
3632 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3633 {
3634 	struct hnae3_handle *h = priv->ae_handle;
3635 	struct pci_dev *pdev = h->pdev;
3636 	int i, ret;
3637 
3638 	for (i = 0; i < priv->vector_num; i++) {
3639 		struct hns3_enet_tqp_vector *tqp_vector;
3640 
3641 		tqp_vector = &priv->tqp_vector[i];
3642 		ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3643 		if (ret)
3644 			return;
3645 	}
3646 
3647 	devm_kfree(&pdev->dev, priv->tqp_vector);
3648 }
3649 
3650 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3651 			      unsigned int ring_type)
3652 {
3653 	int queue_num = priv->ae_handle->kinfo.num_tqps;
3654 	struct hns3_enet_ring *ring;
3655 	int desc_num;
3656 
3657 	if (ring_type == HNAE3_RING_TYPE_TX) {
3658 		ring = &priv->ring[q->tqp_index];
3659 		desc_num = priv->ae_handle->kinfo.num_tx_desc;
3660 		ring->queue_index = q->tqp_index;
3661 		ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3662 	} else {
3663 		ring = &priv->ring[q->tqp_index + queue_num];
3664 		desc_num = priv->ae_handle->kinfo.num_rx_desc;
3665 		ring->queue_index = q->tqp_index;
3666 		ring->io_base = q->io_base;
3667 	}
3668 
3669 	hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3670 
3671 	ring->tqp = q;
3672 	ring->desc = NULL;
3673 	ring->desc_cb = NULL;
3674 	ring->dev = priv->dev;
3675 	ring->desc_dma_addr = 0;
3676 	ring->buf_size = q->buf_size;
3677 	ring->desc_num = desc_num;
3678 	ring->next_to_use = 0;
3679 	ring->next_to_clean = 0;
3680 }
3681 
3682 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3683 			       struct hns3_nic_priv *priv)
3684 {
3685 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3686 	hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3687 }
3688 
3689 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3690 {
3691 	struct hnae3_handle *h = priv->ae_handle;
3692 	struct pci_dev *pdev = h->pdev;
3693 	int i;
3694 
3695 	priv->ring = devm_kzalloc(&pdev->dev,
3696 				  array3_size(h->kinfo.num_tqps,
3697 					      sizeof(*priv->ring), 2),
3698 				  GFP_KERNEL);
3699 	if (!priv->ring)
3700 		return -ENOMEM;
3701 
3702 	for (i = 0; i < h->kinfo.num_tqps; i++)
3703 		hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3704 
3705 	return 0;
3706 }
3707 
3708 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3709 {
3710 	if (!priv->ring)
3711 		return;
3712 
3713 	devm_kfree(priv->dev, priv->ring);
3714 	priv->ring = NULL;
3715 }
3716 
3717 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3718 {
3719 	int ret;
3720 
3721 	if (ring->desc_num <= 0 || ring->buf_size <= 0)
3722 		return -EINVAL;
3723 
3724 	ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3725 				     sizeof(ring->desc_cb[0]), GFP_KERNEL);
3726 	if (!ring->desc_cb) {
3727 		ret = -ENOMEM;
3728 		goto out;
3729 	}
3730 
3731 	ret = hns3_alloc_desc(ring);
3732 	if (ret)
3733 		goto out_with_desc_cb;
3734 
3735 	if (!HNAE3_IS_TX_RING(ring)) {
3736 		ret = hns3_alloc_ring_buffers(ring);
3737 		if (ret)
3738 			goto out_with_desc;
3739 	}
3740 
3741 	return 0;
3742 
3743 out_with_desc:
3744 	hns3_free_desc(ring);
3745 out_with_desc_cb:
3746 	devm_kfree(ring_to_dev(ring), ring->desc_cb);
3747 	ring->desc_cb = NULL;
3748 out:
3749 	return ret;
3750 }
3751 
3752 void hns3_fini_ring(struct hns3_enet_ring *ring)
3753 {
3754 	hns3_free_desc(ring);
3755 	devm_kfree(ring_to_dev(ring), ring->desc_cb);
3756 	ring->desc_cb = NULL;
3757 	ring->next_to_clean = 0;
3758 	ring->next_to_use = 0;
3759 	ring->pending_buf = 0;
3760 	if (ring->skb) {
3761 		dev_kfree_skb_any(ring->skb);
3762 		ring->skb = NULL;
3763 	}
3764 }
3765 
3766 static int hns3_buf_size2type(u32 buf_size)
3767 {
3768 	int bd_size_type;
3769 
3770 	switch (buf_size) {
3771 	case 512:
3772 		bd_size_type = HNS3_BD_SIZE_512_TYPE;
3773 		break;
3774 	case 1024:
3775 		bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3776 		break;
3777 	case 2048:
3778 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3779 		break;
3780 	case 4096:
3781 		bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3782 		break;
3783 	default:
3784 		bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3785 	}
3786 
3787 	return bd_size_type;
3788 }
3789 
3790 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3791 {
3792 	dma_addr_t dma = ring->desc_dma_addr;
3793 	struct hnae3_queue *q = ring->tqp;
3794 
3795 	if (!HNAE3_IS_TX_RING(ring)) {
3796 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3797 		hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3798 			       (u32)((dma >> 31) >> 1));
3799 
3800 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3801 			       hns3_buf_size2type(ring->buf_size));
3802 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3803 			       ring->desc_num / 8 - 1);
3804 
3805 	} else {
3806 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3807 			       (u32)dma);
3808 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3809 			       (u32)((dma >> 31) >> 1));
3810 
3811 		hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3812 			       ring->desc_num / 8 - 1);
3813 	}
3814 }
3815 
3816 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3817 {
3818 	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3819 	int i;
3820 
3821 	for (i = 0; i < HNAE3_MAX_TC; i++) {
3822 		struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3823 		int j;
3824 
3825 		if (!tc_info->enable)
3826 			continue;
3827 
3828 		for (j = 0; j < tc_info->tqp_count; j++) {
3829 			struct hnae3_queue *q;
3830 
3831 			q = priv->ring[tc_info->tqp_offset + j].tqp;
3832 			hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3833 				       tc_info->tc);
3834 		}
3835 	}
3836 }
3837 
3838 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3839 {
3840 	struct hnae3_handle *h = priv->ae_handle;
3841 	int ring_num = h->kinfo.num_tqps * 2;
3842 	int i, j;
3843 	int ret;
3844 
3845 	for (i = 0; i < ring_num; i++) {
3846 		ret = hns3_alloc_ring_memory(&priv->ring[i]);
3847 		if (ret) {
3848 			dev_err(priv->dev,
3849 				"Alloc ring memory fail! ret=%d\n", ret);
3850 			goto out_when_alloc_ring_memory;
3851 		}
3852 
3853 		u64_stats_init(&priv->ring[i].syncp);
3854 	}
3855 
3856 	return 0;
3857 
3858 out_when_alloc_ring_memory:
3859 	for (j = i - 1; j >= 0; j--)
3860 		hns3_fini_ring(&priv->ring[j]);
3861 
3862 	return -ENOMEM;
3863 }
3864 
3865 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3866 {
3867 	struct hnae3_handle *h = priv->ae_handle;
3868 	int i;
3869 
3870 	for (i = 0; i < h->kinfo.num_tqps; i++) {
3871 		hns3_fini_ring(&priv->ring[i]);
3872 		hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3873 	}
3874 	return 0;
3875 }
3876 
3877 /* Set mac addr if it is configured. or leave it to the AE driver */
3878 static int hns3_init_mac_addr(struct net_device *netdev)
3879 {
3880 	struct hns3_nic_priv *priv = netdev_priv(netdev);
3881 	struct hnae3_handle *h = priv->ae_handle;
3882 	u8 mac_addr_temp[ETH_ALEN];
3883 	int ret = 0;
3884 
3885 	if (h->ae_algo->ops->get_mac_addr)
3886 		h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3887 
3888 	/* Check if the MAC address is valid, if not get a random one */
3889 	if (!is_valid_ether_addr(mac_addr_temp)) {
3890 		eth_hw_addr_random(netdev);
3891 		dev_warn(priv->dev, "using random MAC address %pM\n",
3892 			 netdev->dev_addr);
3893 	} else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
3894 		ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3895 		ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3896 	} else {
3897 		return 0;
3898 	}
3899 
3900 	if (h->ae_algo->ops->set_mac_addr)
3901 		ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3902 
3903 	return ret;
3904 }
3905 
3906 static int hns3_init_phy(struct net_device *netdev)
3907 {
3908 	struct hnae3_handle *h = hns3_get_handle(netdev);
3909 	int ret = 0;
3910 
3911 	if (h->ae_algo->ops->mac_connect_phy)
3912 		ret = h->ae_algo->ops->mac_connect_phy(h);
3913 
3914 	return ret;
3915 }
3916 
3917 static void hns3_uninit_phy(struct net_device *netdev)
3918 {
3919 	struct hnae3_handle *h = hns3_get_handle(netdev);
3920 
3921 	if (h->ae_algo->ops->mac_disconnect_phy)
3922 		h->ae_algo->ops->mac_disconnect_phy(h);
3923 }
3924 
3925 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3926 {
3927 	struct hnae3_handle *h = hns3_get_handle(netdev);
3928 
3929 	if (h->ae_algo->ops->del_all_fd_entries)
3930 		h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3931 }
3932 
3933 static int hns3_client_start(struct hnae3_handle *handle)
3934 {
3935 	if (!handle->ae_algo->ops->client_start)
3936 		return 0;
3937 
3938 	return handle->ae_algo->ops->client_start(handle);
3939 }
3940 
3941 static void hns3_client_stop(struct hnae3_handle *handle)
3942 {
3943 	if (!handle->ae_algo->ops->client_stop)
3944 		return;
3945 
3946 	handle->ae_algo->ops->client_stop(handle);
3947 }
3948 
3949 static void hns3_info_show(struct hns3_nic_priv *priv)
3950 {
3951 	struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3952 
3953 	dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3954 	dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
3955 	dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
3956 	dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
3957 	dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
3958 	dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
3959 	dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
3960 	dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
3961 	dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
3962 }
3963 
3964 static int hns3_client_init(struct hnae3_handle *handle)
3965 {
3966 	struct pci_dev *pdev = handle->pdev;
3967 	u16 alloc_tqps, max_rss_size;
3968 	struct hns3_nic_priv *priv;
3969 	struct net_device *netdev;
3970 	int ret;
3971 
3972 	handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3973 						    &max_rss_size);
3974 	netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3975 	if (!netdev)
3976 		return -ENOMEM;
3977 
3978 	priv = netdev_priv(netdev);
3979 	priv->dev = &pdev->dev;
3980 	priv->netdev = netdev;
3981 	priv->ae_handle = handle;
3982 	priv->tx_timeout_count = 0;
3983 	set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3984 
3985 	handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3986 
3987 	handle->kinfo.netdev = netdev;
3988 	handle->priv = (void *)priv;
3989 
3990 	hns3_init_mac_addr(netdev);
3991 
3992 	hns3_set_default_feature(netdev);
3993 
3994 	netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3995 	netdev->priv_flags |= IFF_UNICAST_FLT;
3996 	netdev->netdev_ops = &hns3_nic_netdev_ops;
3997 	SET_NETDEV_DEV(netdev, &pdev->dev);
3998 	hns3_ethtool_set_ops(netdev);
3999 
4000 	/* Carrier off reporting is important to ethtool even BEFORE open */
4001 	netif_carrier_off(netdev);
4002 
4003 	ret = hns3_get_ring_config(priv);
4004 	if (ret) {
4005 		ret = -ENOMEM;
4006 		goto out_get_ring_cfg;
4007 	}
4008 
4009 	ret = hns3_nic_alloc_vector_data(priv);
4010 	if (ret) {
4011 		ret = -ENOMEM;
4012 		goto out_alloc_vector_data;
4013 	}
4014 
4015 	ret = hns3_nic_init_vector_data(priv);
4016 	if (ret) {
4017 		ret = -ENOMEM;
4018 		goto out_init_vector_data;
4019 	}
4020 
4021 	ret = hns3_init_all_ring(priv);
4022 	if (ret) {
4023 		ret = -ENOMEM;
4024 		goto out_init_ring;
4025 	}
4026 
4027 	ret = hns3_init_phy(netdev);
4028 	if (ret)
4029 		goto out_init_phy;
4030 
4031 	ret = register_netdev(netdev);
4032 	if (ret) {
4033 		dev_err(priv->dev, "probe register netdev fail!\n");
4034 		goto out_reg_netdev_fail;
4035 	}
4036 
4037 	/* the device can work without cpu rmap, only aRFS needs it */
4038 	ret = hns3_set_rx_cpu_rmap(netdev);
4039 	if (ret)
4040 		dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4041 
4042 	ret = hns3_nic_init_irq(priv);
4043 	if (ret) {
4044 		dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4045 		hns3_free_rx_cpu_rmap(netdev);
4046 		goto out_init_irq_fail;
4047 	}
4048 
4049 	ret = hns3_client_start(handle);
4050 	if (ret) {
4051 		dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4052 		goto out_client_start;
4053 	}
4054 
4055 	hns3_dcbnl_setup(handle);
4056 
4057 	hns3_dbg_init(handle);
4058 
4059 	/* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4060 	netdev->max_mtu = HNS3_MAX_MTU;
4061 
4062 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4063 
4064 	if (netif_msg_drv(handle))
4065 		hns3_info_show(priv);
4066 
4067 	return ret;
4068 
4069 out_client_start:
4070 	hns3_free_rx_cpu_rmap(netdev);
4071 	hns3_nic_uninit_irq(priv);
4072 out_init_irq_fail:
4073 	unregister_netdev(netdev);
4074 out_reg_netdev_fail:
4075 	hns3_uninit_phy(netdev);
4076 out_init_phy:
4077 	hns3_uninit_all_ring(priv);
4078 out_init_ring:
4079 	hns3_nic_uninit_vector_data(priv);
4080 out_init_vector_data:
4081 	hns3_nic_dealloc_vector_data(priv);
4082 out_alloc_vector_data:
4083 	priv->ring = NULL;
4084 out_get_ring_cfg:
4085 	priv->ae_handle = NULL;
4086 	free_netdev(netdev);
4087 	return ret;
4088 }
4089 
4090 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4091 {
4092 	struct net_device *netdev = handle->kinfo.netdev;
4093 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4094 	int ret;
4095 
4096 	if (netdev->reg_state != NETREG_UNINITIALIZED)
4097 		unregister_netdev(netdev);
4098 
4099 	hns3_client_stop(handle);
4100 
4101 	hns3_uninit_phy(netdev);
4102 
4103 	if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4104 		netdev_warn(netdev, "already uninitialized\n");
4105 		goto out_netdev_free;
4106 	}
4107 
4108 	hns3_free_rx_cpu_rmap(netdev);
4109 
4110 	hns3_nic_uninit_irq(priv);
4111 
4112 	hns3_del_all_fd_rules(netdev, true);
4113 
4114 	hns3_clear_all_ring(handle, true);
4115 
4116 	hns3_nic_uninit_vector_data(priv);
4117 
4118 	hns3_nic_dealloc_vector_data(priv);
4119 
4120 	ret = hns3_uninit_all_ring(priv);
4121 	if (ret)
4122 		netdev_err(netdev, "uninit ring error\n");
4123 
4124 	hns3_put_ring_config(priv);
4125 
4126 out_netdev_free:
4127 	hns3_dbg_uninit(handle);
4128 	free_netdev(netdev);
4129 }
4130 
4131 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4132 {
4133 	struct net_device *netdev = handle->kinfo.netdev;
4134 
4135 	if (!netdev)
4136 		return;
4137 
4138 	if (linkup) {
4139 		netif_tx_wake_all_queues(netdev);
4140 		netif_carrier_on(netdev);
4141 		if (netif_msg_link(handle))
4142 			netdev_info(netdev, "link up\n");
4143 	} else {
4144 		netif_carrier_off(netdev);
4145 		netif_tx_stop_all_queues(netdev);
4146 		if (netif_msg_link(handle))
4147 			netdev_info(netdev, "link down\n");
4148 	}
4149 }
4150 
4151 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4152 {
4153 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4154 	struct net_device *ndev = kinfo->netdev;
4155 
4156 	if (tc > HNAE3_MAX_TC)
4157 		return -EINVAL;
4158 
4159 	if (!ndev)
4160 		return -ENODEV;
4161 
4162 	return hns3_nic_set_real_num_queue(ndev);
4163 }
4164 
4165 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4166 {
4167 	while (ring->next_to_clean != ring->next_to_use) {
4168 		ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4169 		hns3_free_buffer_detach(ring, ring->next_to_clean);
4170 		ring_ptr_move_fw(ring, next_to_clean);
4171 	}
4172 }
4173 
4174 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4175 {
4176 	struct hns3_desc_cb res_cbs;
4177 	int ret;
4178 
4179 	while (ring->next_to_use != ring->next_to_clean) {
4180 		/* When a buffer is not reused, it's memory has been
4181 		 * freed in hns3_handle_rx_bd or will be freed by
4182 		 * stack, so we need to replace the buffer here.
4183 		 */
4184 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4185 			ret = hns3_reserve_buffer_map(ring, &res_cbs);
4186 			if (ret) {
4187 				u64_stats_update_begin(&ring->syncp);
4188 				ring->stats.sw_err_cnt++;
4189 				u64_stats_update_end(&ring->syncp);
4190 				/* if alloc new buffer fail, exit directly
4191 				 * and reclear in up flow.
4192 				 */
4193 				netdev_warn(ring_to_netdev(ring),
4194 					    "reserve buffer map failed, ret = %d\n",
4195 					    ret);
4196 				return ret;
4197 			}
4198 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4199 		}
4200 		ring_ptr_move_fw(ring, next_to_use);
4201 	}
4202 
4203 	/* Free the pending skb in rx ring */
4204 	if (ring->skb) {
4205 		dev_kfree_skb_any(ring->skb);
4206 		ring->skb = NULL;
4207 		ring->pending_buf = 0;
4208 	}
4209 
4210 	return 0;
4211 }
4212 
4213 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4214 {
4215 	while (ring->next_to_use != ring->next_to_clean) {
4216 		/* When a buffer is not reused, it's memory has been
4217 		 * freed in hns3_handle_rx_bd or will be freed by
4218 		 * stack, so only need to unmap the buffer here.
4219 		 */
4220 		if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4221 			hns3_unmap_buffer(ring,
4222 					  &ring->desc_cb[ring->next_to_use]);
4223 			ring->desc_cb[ring->next_to_use].dma = 0;
4224 		}
4225 
4226 		ring_ptr_move_fw(ring, next_to_use);
4227 	}
4228 }
4229 
4230 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4231 {
4232 	struct net_device *ndev = h->kinfo.netdev;
4233 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4234 	u32 i;
4235 
4236 	for (i = 0; i < h->kinfo.num_tqps; i++) {
4237 		struct hns3_enet_ring *ring;
4238 
4239 		ring = &priv->ring[i];
4240 		hns3_clear_tx_ring(ring);
4241 
4242 		ring = &priv->ring[i + h->kinfo.num_tqps];
4243 		/* Continue to clear other rings even if clearing some
4244 		 * rings failed.
4245 		 */
4246 		if (force)
4247 			hns3_force_clear_rx_ring(ring);
4248 		else
4249 			hns3_clear_rx_ring(ring);
4250 	}
4251 }
4252 
4253 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4254 {
4255 	struct net_device *ndev = h->kinfo.netdev;
4256 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4257 	struct hns3_enet_ring *rx_ring;
4258 	int i, j;
4259 	int ret;
4260 
4261 	for (i = 0; i < h->kinfo.num_tqps; i++) {
4262 		ret = h->ae_algo->ops->reset_queue(h, i);
4263 		if (ret)
4264 			return ret;
4265 
4266 		hns3_init_ring_hw(&priv->ring[i]);
4267 
4268 		/* We need to clear tx ring here because self test will
4269 		 * use the ring and will not run down before up
4270 		 */
4271 		hns3_clear_tx_ring(&priv->ring[i]);
4272 		priv->ring[i].next_to_clean = 0;
4273 		priv->ring[i].next_to_use = 0;
4274 
4275 		rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4276 		hns3_init_ring_hw(rx_ring);
4277 		ret = hns3_clear_rx_ring(rx_ring);
4278 		if (ret)
4279 			return ret;
4280 
4281 		/* We can not know the hardware head and tail when this
4282 		 * function is called in reset flow, so we reuse all desc.
4283 		 */
4284 		for (j = 0; j < rx_ring->desc_num; j++)
4285 			hns3_reuse_buffer(rx_ring, j);
4286 
4287 		rx_ring->next_to_clean = 0;
4288 		rx_ring->next_to_use = 0;
4289 	}
4290 
4291 	hns3_init_tx_ring_tc(priv);
4292 
4293 	return 0;
4294 }
4295 
4296 static void hns3_store_coal(struct hns3_nic_priv *priv)
4297 {
4298 	/* ethtool only support setting and querying one coal
4299 	 * configuration for now, so save the vector 0' coal
4300 	 * configuration here in order to restore it.
4301 	 */
4302 	memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4303 	       sizeof(struct hns3_enet_coalesce));
4304 	memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4305 	       sizeof(struct hns3_enet_coalesce));
4306 }
4307 
4308 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4309 {
4310 	u16 vector_num = priv->vector_num;
4311 	int i;
4312 
4313 	for (i = 0; i < vector_num; i++) {
4314 		memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4315 		       sizeof(struct hns3_enet_coalesce));
4316 		memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4317 		       sizeof(struct hns3_enet_coalesce));
4318 	}
4319 }
4320 
4321 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4322 {
4323 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4324 	struct net_device *ndev = kinfo->netdev;
4325 	struct hns3_nic_priv *priv = netdev_priv(ndev);
4326 
4327 	if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4328 		return 0;
4329 
4330 	if (!netif_running(ndev))
4331 		return 0;
4332 
4333 	return hns3_nic_net_stop(ndev);
4334 }
4335 
4336 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4337 {
4338 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4339 	struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4340 	int ret = 0;
4341 
4342 	clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4343 
4344 	if (netif_running(kinfo->netdev)) {
4345 		ret = hns3_nic_net_open(kinfo->netdev);
4346 		if (ret) {
4347 			set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4348 			netdev_err(kinfo->netdev,
4349 				   "net up fail, ret=%d!\n", ret);
4350 			return ret;
4351 		}
4352 	}
4353 
4354 	return ret;
4355 }
4356 
4357 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4358 {
4359 	struct net_device *netdev = handle->kinfo.netdev;
4360 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4361 	int ret;
4362 
4363 	/* Carrier off reporting is important to ethtool even BEFORE open */
4364 	netif_carrier_off(netdev);
4365 
4366 	ret = hns3_get_ring_config(priv);
4367 	if (ret)
4368 		return ret;
4369 
4370 	ret = hns3_nic_alloc_vector_data(priv);
4371 	if (ret)
4372 		goto err_put_ring;
4373 
4374 	hns3_restore_coal(priv);
4375 
4376 	ret = hns3_nic_init_vector_data(priv);
4377 	if (ret)
4378 		goto err_dealloc_vector;
4379 
4380 	ret = hns3_init_all_ring(priv);
4381 	if (ret)
4382 		goto err_uninit_vector;
4383 
4384 	/* the device can work without cpu rmap, only aRFS needs it */
4385 	ret = hns3_set_rx_cpu_rmap(netdev);
4386 	if (ret)
4387 		dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
4388 
4389 	ret = hns3_nic_init_irq(priv);
4390 	if (ret) {
4391 		dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
4392 		hns3_free_rx_cpu_rmap(netdev);
4393 		goto err_init_irq_fail;
4394 	}
4395 
4396 	if (!hns3_is_phys_func(handle->pdev))
4397 		hns3_init_mac_addr(netdev);
4398 
4399 	ret = hns3_client_start(handle);
4400 	if (ret) {
4401 		dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4402 		goto err_client_start_fail;
4403 	}
4404 
4405 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4406 
4407 	return ret;
4408 
4409 err_client_start_fail:
4410 	hns3_free_rx_cpu_rmap(netdev);
4411 	hns3_nic_uninit_irq(priv);
4412 err_init_irq_fail:
4413 	hns3_uninit_all_ring(priv);
4414 err_uninit_vector:
4415 	hns3_nic_uninit_vector_data(priv);
4416 err_dealloc_vector:
4417 	hns3_nic_dealloc_vector_data(priv);
4418 err_put_ring:
4419 	hns3_put_ring_config(priv);
4420 
4421 	return ret;
4422 }
4423 
4424 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4425 {
4426 	struct net_device *netdev = handle->kinfo.netdev;
4427 	struct hns3_nic_priv *priv = netdev_priv(netdev);
4428 	int ret;
4429 
4430 	if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4431 		netdev_warn(netdev, "already uninitialized\n");
4432 		return 0;
4433 	}
4434 
4435 	hns3_free_rx_cpu_rmap(netdev);
4436 	hns3_nic_uninit_irq(priv);
4437 	hns3_clear_all_ring(handle, true);
4438 	hns3_reset_tx_queue(priv->ae_handle);
4439 
4440 	hns3_nic_uninit_vector_data(priv);
4441 
4442 	hns3_store_coal(priv);
4443 
4444 	hns3_nic_dealloc_vector_data(priv);
4445 
4446 	ret = hns3_uninit_all_ring(priv);
4447 	if (ret)
4448 		netdev_err(netdev, "uninit ring error\n");
4449 
4450 	hns3_put_ring_config(priv);
4451 
4452 	return ret;
4453 }
4454 
4455 static int hns3_reset_notify(struct hnae3_handle *handle,
4456 			     enum hnae3_reset_notify_type type)
4457 {
4458 	int ret = 0;
4459 
4460 	switch (type) {
4461 	case HNAE3_UP_CLIENT:
4462 		ret = hns3_reset_notify_up_enet(handle);
4463 		break;
4464 	case HNAE3_DOWN_CLIENT:
4465 		ret = hns3_reset_notify_down_enet(handle);
4466 		break;
4467 	case HNAE3_INIT_CLIENT:
4468 		ret = hns3_reset_notify_init_enet(handle);
4469 		break;
4470 	case HNAE3_UNINIT_CLIENT:
4471 		ret = hns3_reset_notify_uninit_enet(handle);
4472 		break;
4473 	default:
4474 		break;
4475 	}
4476 
4477 	return ret;
4478 }
4479 
4480 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4481 				bool rxfh_configured)
4482 {
4483 	int ret;
4484 
4485 	ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4486 						 rxfh_configured);
4487 	if (ret) {
4488 		dev_err(&handle->pdev->dev,
4489 			"Change tqp num(%u) fail.\n", new_tqp_num);
4490 		return ret;
4491 	}
4492 
4493 	ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4494 	if (ret)
4495 		return ret;
4496 
4497 	ret =  hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4498 	if (ret)
4499 		hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4500 
4501 	return ret;
4502 }
4503 
4504 int hns3_set_channels(struct net_device *netdev,
4505 		      struct ethtool_channels *ch)
4506 {
4507 	struct hnae3_handle *h = hns3_get_handle(netdev);
4508 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
4509 	bool rxfh_configured = netif_is_rxfh_configured(netdev);
4510 	u32 new_tqp_num = ch->combined_count;
4511 	u16 org_tqp_num;
4512 	int ret;
4513 
4514 	if (hns3_nic_resetting(netdev))
4515 		return -EBUSY;
4516 
4517 	if (ch->rx_count || ch->tx_count)
4518 		return -EINVAL;
4519 
4520 	if (new_tqp_num > hns3_get_max_available_channels(h) ||
4521 	    new_tqp_num < 1) {
4522 		dev_err(&netdev->dev,
4523 			"Change tqps fail, the tqp range is from 1 to %u",
4524 			hns3_get_max_available_channels(h));
4525 		return -EINVAL;
4526 	}
4527 
4528 	if (kinfo->rss_size == new_tqp_num)
4529 		return 0;
4530 
4531 	netif_dbg(h, drv, netdev,
4532 		  "set channels: tqp_num=%u, rxfh=%d\n",
4533 		  new_tqp_num, rxfh_configured);
4534 
4535 	ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4536 	if (ret)
4537 		return ret;
4538 
4539 	ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4540 	if (ret)
4541 		return ret;
4542 
4543 	org_tqp_num = h->kinfo.num_tqps;
4544 	ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4545 	if (ret) {
4546 		int ret1;
4547 
4548 		netdev_warn(netdev,
4549 			    "Change channels fail, revert to old value\n");
4550 		ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4551 		if (ret1) {
4552 			netdev_err(netdev,
4553 				   "revert to old channel fail\n");
4554 			return ret1;
4555 		}
4556 
4557 		return ret;
4558 	}
4559 
4560 	return 0;
4561 }
4562 
4563 static const struct hns3_hw_error_info hns3_hw_err[] = {
4564 	{ .type = HNAE3_PPU_POISON_ERROR,
4565 	  .msg = "PPU poison" },
4566 	{ .type = HNAE3_CMDQ_ECC_ERROR,
4567 	  .msg = "IMP CMDQ error" },
4568 	{ .type = HNAE3_IMP_RD_POISON_ERROR,
4569 	  .msg = "IMP RD poison" },
4570 };
4571 
4572 static void hns3_process_hw_error(struct hnae3_handle *handle,
4573 				  enum hnae3_hw_error_type type)
4574 {
4575 	int i;
4576 
4577 	for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4578 		if (hns3_hw_err[i].type == type) {
4579 			dev_err(&handle->pdev->dev, "Detected %s!\n",
4580 				hns3_hw_err[i].msg);
4581 			break;
4582 		}
4583 	}
4584 }
4585 
4586 static const struct hnae3_client_ops client_ops = {
4587 	.init_instance = hns3_client_init,
4588 	.uninit_instance = hns3_client_uninit,
4589 	.link_status_change = hns3_link_status_change,
4590 	.setup_tc = hns3_client_setup_tc,
4591 	.reset_notify = hns3_reset_notify,
4592 	.process_hw_error = hns3_process_hw_error,
4593 };
4594 
4595 /* hns3_init_module - Driver registration routine
4596  * hns3_init_module is the first routine called when the driver is
4597  * loaded. All it does is register with the PCI subsystem.
4598  */
4599 static int __init hns3_init_module(void)
4600 {
4601 	int ret;
4602 
4603 	pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4604 	pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4605 
4606 	client.type = HNAE3_CLIENT_KNIC;
4607 	snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
4608 		 hns3_driver_name);
4609 
4610 	client.ops = &client_ops;
4611 
4612 	INIT_LIST_HEAD(&client.node);
4613 
4614 	hns3_dbg_register_debugfs(hns3_driver_name);
4615 
4616 	ret = hnae3_register_client(&client);
4617 	if (ret)
4618 		goto err_reg_client;
4619 
4620 	ret = pci_register_driver(&hns3_driver);
4621 	if (ret)
4622 		goto err_reg_driver;
4623 
4624 	return ret;
4625 
4626 err_reg_driver:
4627 	hnae3_unregister_client(&client);
4628 err_reg_client:
4629 	hns3_dbg_unregister_debugfs();
4630 	return ret;
4631 }
4632 module_init(hns3_init_module);
4633 
4634 /* hns3_exit_module - Driver exit cleanup routine
4635  * hns3_exit_module is called just before the driver is removed
4636  * from memory.
4637  */
4638 static void __exit hns3_exit_module(void)
4639 {
4640 	pci_unregister_driver(&hns3_driver);
4641 	hnae3_unregister_client(&client);
4642 	hns3_dbg_unregister_debugfs();
4643 }
4644 module_exit(hns3_exit_module);
4645 
4646 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4647 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4648 MODULE_LICENSE("GPL");
4649 MODULE_ALIAS("pci:hns-nic");
4650