1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <linux/vermagic.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 30 31 #define hns3_rl_err(fmt, ...) \ 32 do { \ 33 if (net_ratelimit()) \ 34 netdev_err(fmt, ##__VA_ARGS__); \ 35 } while (0) 36 37 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 38 static void hns3_remove_hw_addr(struct net_device *netdev); 39 40 static const char hns3_driver_name[] = "hns3"; 41 const char hns3_driver_version[] = VERMAGIC_STRING; 42 static const char hns3_driver_string[] = 43 "Hisilicon Ethernet Network Driver for Hip08 Family"; 44 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 45 static struct hnae3_client client; 46 47 static int debug = -1; 48 module_param(debug, int, 0); 49 MODULE_PARM_DESC(debug, " Network interface message level setting"); 50 51 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 53 54 #define HNS3_INNER_VLAN_TAG 1 55 #define HNS3_OUTER_VLAN_TAG 2 56 57 #define HNS3_MIN_TX_LEN 33U 58 59 /* hns3_pci_tbl - PCI Device ID Table 60 * 61 * Last entry must be all 0s 62 * 63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 64 * Class, Class Mask, private data (not used) } 65 */ 66 static const struct pci_device_id hns3_pci_tbl[] = { 67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 68 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 78 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 /* required last entry */ 83 {0, } 84 }; 85 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 86 87 static irqreturn_t hns3_irq_handle(int irq, void *vector) 88 { 89 struct hns3_enet_tqp_vector *tqp_vector = vector; 90 91 napi_schedule_irqoff(&tqp_vector->napi); 92 93 return IRQ_HANDLED; 94 } 95 96 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 97 { 98 struct hns3_enet_tqp_vector *tqp_vectors; 99 unsigned int i; 100 101 for (i = 0; i < priv->vector_num; i++) { 102 tqp_vectors = &priv->tqp_vector[i]; 103 104 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 105 continue; 106 107 /* clear the affinity mask */ 108 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 109 110 /* release the irq resource */ 111 free_irq(tqp_vectors->vector_irq, tqp_vectors); 112 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 113 } 114 } 115 116 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 117 { 118 struct hns3_enet_tqp_vector *tqp_vectors; 119 int txrx_int_idx = 0; 120 int rx_int_idx = 0; 121 int tx_int_idx = 0; 122 unsigned int i; 123 int ret; 124 125 for (i = 0; i < priv->vector_num; i++) { 126 tqp_vectors = &priv->tqp_vector[i]; 127 128 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 129 continue; 130 131 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 132 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 133 "%s-%s-%d", priv->netdev->name, "TxRx", 134 txrx_int_idx++); 135 txrx_int_idx++; 136 } else if (tqp_vectors->rx_group.ring) { 137 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 138 "%s-%s-%d", priv->netdev->name, "Rx", 139 rx_int_idx++); 140 } else if (tqp_vectors->tx_group.ring) { 141 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 142 "%s-%s-%d", priv->netdev->name, "Tx", 143 tx_int_idx++); 144 } else { 145 /* Skip this unused q_vector */ 146 continue; 147 } 148 149 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 150 151 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 152 tqp_vectors->name, tqp_vectors); 153 if (ret) { 154 netdev_err(priv->netdev, "request irq(%d) fail\n", 155 tqp_vectors->vector_irq); 156 hns3_nic_uninit_irq(priv); 157 return ret; 158 } 159 160 irq_set_affinity_hint(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_mask); 162 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 164 } 165 166 return 0; 167 } 168 169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 170 u32 mask_en) 171 { 172 writel(mask_en, tqp_vector->mask_addr); 173 } 174 175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 176 { 177 napi_enable(&tqp_vector->napi); 178 179 /* enable vector */ 180 hns3_mask_vector_irq(tqp_vector, 1); 181 } 182 183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 /* disable vector */ 186 hns3_mask_vector_irq(tqp_vector, 0); 187 188 disable_irq(tqp_vector->vector_irq); 189 napi_disable(&tqp_vector->napi); 190 } 191 192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 rl_value) 194 { 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 196 197 /* this defines the configuration for RL (Interrupt Rate Limiter). 198 * Rl defines rate of interrupts i.e. number of interrupts-per-second 199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 200 */ 201 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 203 !tqp_vector->rx_group.coal.gl_adapt_enable) 204 /* According to the hardware, the range of rl_reg is 205 * 0-59 and the unit is 4. 206 */ 207 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 208 209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 210 } 211 212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 213 u32 gl_value) 214 { 215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 216 217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 218 } 219 220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 221 u32 gl_value) 222 { 223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 224 225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 226 } 227 228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 229 struct hns3_nic_priv *priv) 230 { 231 /* initialize the configuration for interrupt coalescing. 232 * 1. GL (Interrupt Gap Limiter) 233 * 2. RL (Interrupt Rate Limiter) 234 * 235 * Default: enable interrupt coalescing self-adaptive and GL 236 */ 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 238 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 239 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 242 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 245 } 246 247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 248 struct hns3_nic_priv *priv) 249 { 250 struct hnae3_handle *h = priv->ae_handle; 251 252 hns3_set_vector_coalesce_tx_gl(tqp_vector, 253 tqp_vector->tx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rx_gl(tqp_vector, 255 tqp_vector->rx_group.coal.int_gl); 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 257 } 258 259 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 260 { 261 struct hnae3_handle *h = hns3_get_handle(netdev); 262 struct hnae3_knic_private_info *kinfo = &h->kinfo; 263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 264 int i, ret; 265 266 if (kinfo->num_tc <= 1) { 267 netdev_reset_tc(netdev); 268 } else { 269 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 270 if (ret) { 271 netdev_err(netdev, 272 "netdev_set_num_tc fail, ret=%d!\n", ret); 273 return ret; 274 } 275 276 for (i = 0; i < HNAE3_MAX_TC; i++) { 277 if (!kinfo->tc_info[i].enable) 278 continue; 279 280 netdev_set_tc_queue(netdev, 281 kinfo->tc_info[i].tc, 282 kinfo->tc_info[i].tqp_count, 283 kinfo->tc_info[i].tqp_offset); 284 } 285 } 286 287 ret = netif_set_real_num_tx_queues(netdev, queue_size); 288 if (ret) { 289 netdev_err(netdev, 290 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 291 return ret; 292 } 293 294 ret = netif_set_real_num_rx_queues(netdev, queue_size); 295 if (ret) { 296 netdev_err(netdev, 297 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 298 return ret; 299 } 300 301 return 0; 302 } 303 304 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 305 { 306 u16 alloc_tqps, max_rss_size, rss_size; 307 308 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 309 rss_size = alloc_tqps / h->kinfo.num_tc; 310 311 return min_t(u16, rss_size, max_rss_size); 312 } 313 314 static void hns3_tqp_enable(struct hnae3_queue *tqp) 315 { 316 u32 rcb_reg; 317 318 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 319 rcb_reg |= BIT(HNS3_RING_EN_B); 320 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 321 } 322 323 static void hns3_tqp_disable(struct hnae3_queue *tqp) 324 { 325 u32 rcb_reg; 326 327 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 328 rcb_reg &= ~BIT(HNS3_RING_EN_B); 329 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 330 } 331 332 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 333 { 334 #ifdef CONFIG_RFS_ACCEL 335 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 336 netdev->rx_cpu_rmap = NULL; 337 #endif 338 } 339 340 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 341 { 342 #ifdef CONFIG_RFS_ACCEL 343 struct hns3_nic_priv *priv = netdev_priv(netdev); 344 struct hns3_enet_tqp_vector *tqp_vector; 345 int i, ret; 346 347 if (!netdev->rx_cpu_rmap) { 348 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 349 if (!netdev->rx_cpu_rmap) 350 return -ENOMEM; 351 } 352 353 for (i = 0; i < priv->vector_num; i++) { 354 tqp_vector = &priv->tqp_vector[i]; 355 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 356 tqp_vector->vector_irq); 357 if (ret) { 358 hns3_free_rx_cpu_rmap(netdev); 359 return ret; 360 } 361 } 362 #endif 363 return 0; 364 } 365 366 static int hns3_nic_net_up(struct net_device *netdev) 367 { 368 struct hns3_nic_priv *priv = netdev_priv(netdev); 369 struct hnae3_handle *h = priv->ae_handle; 370 int i, j; 371 int ret; 372 373 ret = hns3_nic_reset_all_ring(h); 374 if (ret) 375 return ret; 376 377 /* the device can work without cpu rmap, only aRFS needs it */ 378 ret = hns3_set_rx_cpu_rmap(netdev); 379 if (ret) 380 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret); 381 382 /* get irq resource for all vectors */ 383 ret = hns3_nic_init_irq(priv); 384 if (ret) { 385 netdev_err(netdev, "init irq failed! ret=%d\n", ret); 386 goto free_rmap; 387 } 388 389 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 390 391 /* enable the vectors */ 392 for (i = 0; i < priv->vector_num; i++) 393 hns3_vector_enable(&priv->tqp_vector[i]); 394 395 /* enable rcb */ 396 for (j = 0; j < h->kinfo.num_tqps; j++) 397 hns3_tqp_enable(h->kinfo.tqp[j]); 398 399 /* start the ae_dev */ 400 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 401 if (ret) 402 goto out_start_err; 403 404 return 0; 405 406 out_start_err: 407 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 408 while (j--) 409 hns3_tqp_disable(h->kinfo.tqp[j]); 410 411 for (j = i - 1; j >= 0; j--) 412 hns3_vector_disable(&priv->tqp_vector[j]); 413 414 hns3_nic_uninit_irq(priv); 415 free_rmap: 416 hns3_free_rx_cpu_rmap(netdev); 417 return ret; 418 } 419 420 static void hns3_config_xps(struct hns3_nic_priv *priv) 421 { 422 int i; 423 424 for (i = 0; i < priv->vector_num; i++) { 425 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 426 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 427 428 while (ring) { 429 int ret; 430 431 ret = netif_set_xps_queue(priv->netdev, 432 &tqp_vector->affinity_mask, 433 ring->tqp->tqp_index); 434 if (ret) 435 netdev_warn(priv->netdev, 436 "set xps queue failed: %d", ret); 437 438 ring = ring->next; 439 } 440 } 441 } 442 443 static int hns3_nic_net_open(struct net_device *netdev) 444 { 445 struct hns3_nic_priv *priv = netdev_priv(netdev); 446 struct hnae3_handle *h = hns3_get_handle(netdev); 447 struct hnae3_knic_private_info *kinfo; 448 int i, ret; 449 450 if (hns3_nic_resetting(netdev)) 451 return -EBUSY; 452 453 netif_carrier_off(netdev); 454 455 ret = hns3_nic_set_real_num_queue(netdev); 456 if (ret) 457 return ret; 458 459 ret = hns3_nic_net_up(netdev); 460 if (ret) { 461 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 462 return ret; 463 } 464 465 kinfo = &h->kinfo; 466 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 467 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 468 469 if (h->ae_algo->ops->set_timer_task) 470 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 471 472 hns3_config_xps(priv); 473 474 netif_dbg(h, drv, netdev, "net open\n"); 475 476 return 0; 477 } 478 479 static void hns3_reset_tx_queue(struct hnae3_handle *h) 480 { 481 struct net_device *ndev = h->kinfo.netdev; 482 struct hns3_nic_priv *priv = netdev_priv(ndev); 483 struct netdev_queue *dev_queue; 484 u32 i; 485 486 for (i = 0; i < h->kinfo.num_tqps; i++) { 487 dev_queue = netdev_get_tx_queue(ndev, 488 priv->ring[i].queue_index); 489 netdev_tx_reset_queue(dev_queue); 490 } 491 } 492 493 static void hns3_nic_net_down(struct net_device *netdev) 494 { 495 struct hns3_nic_priv *priv = netdev_priv(netdev); 496 struct hnae3_handle *h = hns3_get_handle(netdev); 497 const struct hnae3_ae_ops *ops; 498 int i; 499 500 /* disable vectors */ 501 for (i = 0; i < priv->vector_num; i++) 502 hns3_vector_disable(&priv->tqp_vector[i]); 503 504 /* disable rcb */ 505 for (i = 0; i < h->kinfo.num_tqps; i++) 506 hns3_tqp_disable(h->kinfo.tqp[i]); 507 508 /* stop ae_dev */ 509 ops = priv->ae_handle->ae_algo->ops; 510 if (ops->stop) 511 ops->stop(priv->ae_handle); 512 513 hns3_free_rx_cpu_rmap(netdev); 514 515 /* free irq resources */ 516 hns3_nic_uninit_irq(priv); 517 518 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 519 * during reset process, because driver may not be able 520 * to disable the ring through firmware when downing the netdev. 521 */ 522 if (!hns3_nic_resetting(netdev)) 523 hns3_clear_all_ring(priv->ae_handle, false); 524 525 hns3_reset_tx_queue(priv->ae_handle); 526 } 527 528 static int hns3_nic_net_stop(struct net_device *netdev) 529 { 530 struct hns3_nic_priv *priv = netdev_priv(netdev); 531 struct hnae3_handle *h = hns3_get_handle(netdev); 532 533 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 534 return 0; 535 536 netif_dbg(h, drv, netdev, "net stop\n"); 537 538 if (h->ae_algo->ops->set_timer_task) 539 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 540 541 netif_tx_stop_all_queues(netdev); 542 netif_carrier_off(netdev); 543 544 hns3_nic_net_down(netdev); 545 546 return 0; 547 } 548 549 static int hns3_nic_uc_sync(struct net_device *netdev, 550 const unsigned char *addr) 551 { 552 struct hnae3_handle *h = hns3_get_handle(netdev); 553 554 if (h->ae_algo->ops->add_uc_addr) 555 return h->ae_algo->ops->add_uc_addr(h, addr); 556 557 return 0; 558 } 559 560 static int hns3_nic_uc_unsync(struct net_device *netdev, 561 const unsigned char *addr) 562 { 563 struct hnae3_handle *h = hns3_get_handle(netdev); 564 565 if (h->ae_algo->ops->rm_uc_addr) 566 return h->ae_algo->ops->rm_uc_addr(h, addr); 567 568 return 0; 569 } 570 571 static int hns3_nic_mc_sync(struct net_device *netdev, 572 const unsigned char *addr) 573 { 574 struct hnae3_handle *h = hns3_get_handle(netdev); 575 576 if (h->ae_algo->ops->add_mc_addr) 577 return h->ae_algo->ops->add_mc_addr(h, addr); 578 579 return 0; 580 } 581 582 static int hns3_nic_mc_unsync(struct net_device *netdev, 583 const unsigned char *addr) 584 { 585 struct hnae3_handle *h = hns3_get_handle(netdev); 586 587 if (h->ae_algo->ops->rm_mc_addr) 588 return h->ae_algo->ops->rm_mc_addr(h, addr); 589 590 return 0; 591 } 592 593 static u8 hns3_get_netdev_flags(struct net_device *netdev) 594 { 595 u8 flags = 0; 596 597 if (netdev->flags & IFF_PROMISC) { 598 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 599 } else { 600 flags |= HNAE3_VLAN_FLTR; 601 if (netdev->flags & IFF_ALLMULTI) 602 flags |= HNAE3_USER_MPE; 603 } 604 605 return flags; 606 } 607 608 static void hns3_nic_set_rx_mode(struct net_device *netdev) 609 { 610 struct hnae3_handle *h = hns3_get_handle(netdev); 611 u8 new_flags; 612 int ret; 613 614 new_flags = hns3_get_netdev_flags(netdev); 615 616 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 617 if (ret) { 618 netdev_err(netdev, "sync uc address fail\n"); 619 if (ret == -ENOSPC) 620 new_flags |= HNAE3_OVERFLOW_UPE; 621 } 622 623 if (netdev->flags & IFF_MULTICAST) { 624 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 625 hns3_nic_mc_unsync); 626 if (ret) { 627 netdev_err(netdev, "sync mc address fail\n"); 628 if (ret == -ENOSPC) 629 new_flags |= HNAE3_OVERFLOW_MPE; 630 } 631 } 632 633 /* User mode Promisc mode enable and vlan filtering is disabled to 634 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 635 * vlan fitering is enabled 636 */ 637 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 638 h->netdev_flags = new_flags; 639 hns3_update_promisc_mode(netdev, new_flags); 640 } 641 642 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 643 { 644 struct hns3_nic_priv *priv = netdev_priv(netdev); 645 struct hnae3_handle *h = priv->ae_handle; 646 647 if (h->ae_algo->ops->set_promisc_mode) { 648 return h->ae_algo->ops->set_promisc_mode(h, 649 promisc_flags & HNAE3_UPE, 650 promisc_flags & HNAE3_MPE); 651 } 652 653 return 0; 654 } 655 656 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 657 { 658 struct hns3_nic_priv *priv = netdev_priv(netdev); 659 struct hnae3_handle *h = priv->ae_handle; 660 bool last_state; 661 662 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 663 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 664 if (enable != last_state) { 665 netdev_info(netdev, 666 "%s vlan filter\n", 667 enable ? "enable" : "disable"); 668 h->ae_algo->ops->enable_vlan_filter(h, enable); 669 } 670 } 671 } 672 673 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 674 u16 *mss, u32 *type_cs_vlan_tso) 675 { 676 u32 l4_offset, hdr_len; 677 union l3_hdr_info l3; 678 union l4_hdr_info l4; 679 u32 l4_paylen; 680 int ret; 681 682 if (!skb_is_gso(skb)) 683 return 0; 684 685 ret = skb_cow_head(skb, 0); 686 if (unlikely(ret < 0)) 687 return ret; 688 689 l3.hdr = skb_network_header(skb); 690 l4.hdr = skb_transport_header(skb); 691 692 /* Software should clear the IPv4's checksum field when tso is 693 * needed. 694 */ 695 if (l3.v4->version == 4) 696 l3.v4->check = 0; 697 698 /* tunnel packet */ 699 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 700 SKB_GSO_GRE_CSUM | 701 SKB_GSO_UDP_TUNNEL | 702 SKB_GSO_UDP_TUNNEL_CSUM)) { 703 if ((!(skb_shinfo(skb)->gso_type & 704 SKB_GSO_PARTIAL)) && 705 (skb_shinfo(skb)->gso_type & 706 SKB_GSO_UDP_TUNNEL_CSUM)) { 707 /* Software should clear the udp's checksum 708 * field when tso is needed. 709 */ 710 l4.udp->check = 0; 711 } 712 /* reset l3&l4 pointers from outer to inner headers */ 713 l3.hdr = skb_inner_network_header(skb); 714 l4.hdr = skb_inner_transport_header(skb); 715 716 /* Software should clear the IPv4's checksum field when 717 * tso is needed. 718 */ 719 if (l3.v4->version == 4) 720 l3.v4->check = 0; 721 } 722 723 /* normal or tunnel packet */ 724 l4_offset = l4.hdr - skb->data; 725 hdr_len = (l4.tcp->doff << 2) + l4_offset; 726 727 /* remove payload length from inner pseudo checksum when tso */ 728 l4_paylen = skb->len - l4_offset; 729 csum_replace_by_diff(&l4.tcp->check, 730 (__force __wsum)htonl(l4_paylen)); 731 732 /* find the txbd field values */ 733 *paylen = skb->len - hdr_len; 734 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 735 736 /* get MSS for TSO */ 737 *mss = skb_shinfo(skb)->gso_size; 738 739 return 0; 740 } 741 742 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 743 u8 *il4_proto) 744 { 745 union l3_hdr_info l3; 746 unsigned char *l4_hdr; 747 unsigned char *exthdr; 748 u8 l4_proto_tmp; 749 __be16 frag_off; 750 751 /* find outer header point */ 752 l3.hdr = skb_network_header(skb); 753 l4_hdr = skb_transport_header(skb); 754 755 if (skb->protocol == htons(ETH_P_IPV6)) { 756 exthdr = l3.hdr + sizeof(*l3.v6); 757 l4_proto_tmp = l3.v6->nexthdr; 758 if (l4_hdr != exthdr) 759 ipv6_skip_exthdr(skb, exthdr - skb->data, 760 &l4_proto_tmp, &frag_off); 761 } else if (skb->protocol == htons(ETH_P_IP)) { 762 l4_proto_tmp = l3.v4->protocol; 763 } else { 764 return -EINVAL; 765 } 766 767 *ol4_proto = l4_proto_tmp; 768 769 /* tunnel packet */ 770 if (!skb->encapsulation) { 771 *il4_proto = 0; 772 return 0; 773 } 774 775 /* find inner header point */ 776 l3.hdr = skb_inner_network_header(skb); 777 l4_hdr = skb_inner_transport_header(skb); 778 779 if (l3.v6->version == 6) { 780 exthdr = l3.hdr + sizeof(*l3.v6); 781 l4_proto_tmp = l3.v6->nexthdr; 782 if (l4_hdr != exthdr) 783 ipv6_skip_exthdr(skb, exthdr - skb->data, 784 &l4_proto_tmp, &frag_off); 785 } else if (l3.v4->version == 4) { 786 l4_proto_tmp = l3.v4->protocol; 787 } 788 789 *il4_proto = l4_proto_tmp; 790 791 return 0; 792 } 793 794 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 795 * and it is udp packet, which has a dest port as the IANA assigned. 796 * the hardware is expected to do the checksum offload, but the 797 * hardware will not do the checksum offload when udp dest port is 798 * 4789. 799 */ 800 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 801 { 802 union l4_hdr_info l4; 803 804 l4.hdr = skb_transport_header(skb); 805 806 if (!(!skb->encapsulation && 807 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 808 return false; 809 810 skb_checksum_help(skb); 811 812 return true; 813 } 814 815 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 816 u32 *ol_type_vlan_len_msec) 817 { 818 u32 l2_len, l3_len, l4_len; 819 unsigned char *il2_hdr; 820 union l3_hdr_info l3; 821 union l4_hdr_info l4; 822 823 l3.hdr = skb_network_header(skb); 824 l4.hdr = skb_transport_header(skb); 825 826 /* compute OL2 header size, defined in 2 Bytes */ 827 l2_len = l3.hdr - skb->data; 828 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 829 830 /* compute OL3 header size, defined in 4 Bytes */ 831 l3_len = l4.hdr - l3.hdr; 832 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 833 834 il2_hdr = skb_inner_mac_header(skb); 835 /* compute OL4 header size, defined in 4 Bytes */ 836 l4_len = il2_hdr - l4.hdr; 837 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 838 839 /* define outer network header type */ 840 if (skb->protocol == htons(ETH_P_IP)) { 841 if (skb_is_gso(skb)) 842 hns3_set_field(*ol_type_vlan_len_msec, 843 HNS3_TXD_OL3T_S, 844 HNS3_OL3T_IPV4_CSUM); 845 else 846 hns3_set_field(*ol_type_vlan_len_msec, 847 HNS3_TXD_OL3T_S, 848 HNS3_OL3T_IPV4_NO_CSUM); 849 850 } else if (skb->protocol == htons(ETH_P_IPV6)) { 851 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 852 HNS3_OL3T_IPV6); 853 } 854 855 if (ol4_proto == IPPROTO_UDP) 856 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 857 HNS3_TUN_MAC_IN_UDP); 858 else if (ol4_proto == IPPROTO_GRE) 859 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 860 HNS3_TUN_NVGRE); 861 } 862 863 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 864 u8 il4_proto, u32 *type_cs_vlan_tso, 865 u32 *ol_type_vlan_len_msec) 866 { 867 unsigned char *l2_hdr = skb->data; 868 u32 l4_proto = ol4_proto; 869 union l4_hdr_info l4; 870 union l3_hdr_info l3; 871 u32 l2_len, l3_len; 872 873 l4.hdr = skb_transport_header(skb); 874 l3.hdr = skb_network_header(skb); 875 876 /* handle encapsulation skb */ 877 if (skb->encapsulation) { 878 /* If this is a not UDP/GRE encapsulation skb */ 879 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 880 /* drop the skb tunnel packet if hardware don't support, 881 * because hardware can't calculate csum when TSO. 882 */ 883 if (skb_is_gso(skb)) 884 return -EDOM; 885 886 /* the stack computes the IP header already, 887 * driver calculate l4 checksum when not TSO. 888 */ 889 skb_checksum_help(skb); 890 return 0; 891 } 892 893 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 894 895 /* switch to inner header */ 896 l2_hdr = skb_inner_mac_header(skb); 897 l3.hdr = skb_inner_network_header(skb); 898 l4.hdr = skb_inner_transport_header(skb); 899 l4_proto = il4_proto; 900 } 901 902 if (l3.v4->version == 4) { 903 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 904 HNS3_L3T_IPV4); 905 906 /* the stack computes the IP header already, the only time we 907 * need the hardware to recompute it is in the case of TSO. 908 */ 909 if (skb_is_gso(skb)) 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 911 } else if (l3.v6->version == 6) { 912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 913 HNS3_L3T_IPV6); 914 } 915 916 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 917 l2_len = l3.hdr - l2_hdr; 918 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 919 920 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 921 l3_len = l4.hdr - l3.hdr; 922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 923 924 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 925 switch (l4_proto) { 926 case IPPROTO_TCP: 927 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 929 HNS3_L4T_TCP); 930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 931 l4.tcp->doff); 932 break; 933 case IPPROTO_UDP: 934 if (hns3_tunnel_csum_bug(skb)) 935 break; 936 937 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 939 HNS3_L4T_UDP); 940 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 941 (sizeof(struct udphdr) >> 2)); 942 break; 943 case IPPROTO_SCTP: 944 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 946 HNS3_L4T_SCTP); 947 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 948 (sizeof(struct sctphdr) >> 2)); 949 break; 950 default: 951 /* drop the skb tunnel packet if hardware don't support, 952 * because hardware can't calculate csum when TSO. 953 */ 954 if (skb_is_gso(skb)) 955 return -EDOM; 956 957 /* the stack computes the IP header already, 958 * driver calculate l4 checksum when not TSO. 959 */ 960 skb_checksum_help(skb); 961 return 0; 962 } 963 964 return 0; 965 } 966 967 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 968 struct sk_buff *skb) 969 { 970 struct hnae3_handle *handle = tx_ring->tqp->handle; 971 struct vlan_ethhdr *vhdr; 972 int rc; 973 974 if (!(skb->protocol == htons(ETH_P_8021Q) || 975 skb_vlan_tag_present(skb))) 976 return 0; 977 978 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 979 * header is allowed in skb, otherwise it will cause RAS error. 980 */ 981 if (unlikely(skb_vlan_tagged_multi(skb) && 982 handle->port_base_vlan_state == 983 HNAE3_PORT_BASE_VLAN_ENABLE)) 984 return -EINVAL; 985 986 if (skb->protocol == htons(ETH_P_8021Q) && 987 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 988 /* When HW VLAN acceleration is turned off, and the stack 989 * sets the protocol to 802.1q, the driver just need to 990 * set the protocol to the encapsulated ethertype. 991 */ 992 skb->protocol = vlan_get_protocol(skb); 993 return 0; 994 } 995 996 if (skb_vlan_tag_present(skb)) { 997 /* Based on hw strategy, use out_vtag in two layer tag case, 998 * and use inner_vtag in one tag case. 999 */ 1000 if (skb->protocol == htons(ETH_P_8021Q) && 1001 handle->port_base_vlan_state == 1002 HNAE3_PORT_BASE_VLAN_DISABLE) 1003 rc = HNS3_OUTER_VLAN_TAG; 1004 else 1005 rc = HNS3_INNER_VLAN_TAG; 1006 1007 skb->protocol = vlan_get_protocol(skb); 1008 return rc; 1009 } 1010 1011 rc = skb_cow_head(skb, 0); 1012 if (unlikely(rc < 0)) 1013 return rc; 1014 1015 vhdr = (struct vlan_ethhdr *)skb->data; 1016 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1017 & VLAN_PRIO_MASK); 1018 1019 skb->protocol = vlan_get_protocol(skb); 1020 return 0; 1021 } 1022 1023 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1024 struct sk_buff *skb, struct hns3_desc *desc) 1025 { 1026 u32 ol_type_vlan_len_msec = 0; 1027 u32 type_cs_vlan_tso = 0; 1028 u32 paylen = skb->len; 1029 u16 inner_vtag = 0; 1030 u16 out_vtag = 0; 1031 u16 mss = 0; 1032 int ret; 1033 1034 ret = hns3_handle_vtags(ring, skb); 1035 if (unlikely(ret < 0)) { 1036 u64_stats_update_begin(&ring->syncp); 1037 ring->stats.tx_vlan_err++; 1038 u64_stats_update_end(&ring->syncp); 1039 return ret; 1040 } else if (ret == HNS3_INNER_VLAN_TAG) { 1041 inner_vtag = skb_vlan_tag_get(skb); 1042 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1043 VLAN_PRIO_MASK; 1044 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1045 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1046 out_vtag = skb_vlan_tag_get(skb); 1047 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1048 VLAN_PRIO_MASK; 1049 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1050 1); 1051 } 1052 1053 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1054 u8 ol4_proto, il4_proto; 1055 1056 skb_reset_mac_len(skb); 1057 1058 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1059 if (unlikely(ret < 0)) { 1060 u64_stats_update_begin(&ring->syncp); 1061 ring->stats.tx_l4_proto_err++; 1062 u64_stats_update_end(&ring->syncp); 1063 return ret; 1064 } 1065 1066 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1067 &type_cs_vlan_tso, 1068 &ol_type_vlan_len_msec); 1069 if (unlikely(ret < 0)) { 1070 u64_stats_update_begin(&ring->syncp); 1071 ring->stats.tx_l2l3l4_err++; 1072 u64_stats_update_end(&ring->syncp); 1073 return ret; 1074 } 1075 1076 ret = hns3_set_tso(skb, &paylen, &mss, 1077 &type_cs_vlan_tso); 1078 if (unlikely(ret < 0)) { 1079 u64_stats_update_begin(&ring->syncp); 1080 ring->stats.tx_tso_err++; 1081 u64_stats_update_end(&ring->syncp); 1082 return ret; 1083 } 1084 } 1085 1086 /* Set txbd */ 1087 desc->tx.ol_type_vlan_len_msec = 1088 cpu_to_le32(ol_type_vlan_len_msec); 1089 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1090 desc->tx.paylen = cpu_to_le32(paylen); 1091 desc->tx.mss = cpu_to_le16(mss); 1092 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1093 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1094 1095 return 0; 1096 } 1097 1098 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1099 unsigned int size, enum hns_desc_type type) 1100 { 1101 #define HNS3_LIKELY_BD_NUM 1 1102 1103 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1104 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1105 struct device *dev = ring_to_dev(ring); 1106 skb_frag_t *frag; 1107 unsigned int frag_buf_num; 1108 int k, sizeoflast; 1109 dma_addr_t dma; 1110 1111 if (type == DESC_TYPE_SKB) { 1112 struct sk_buff *skb = (struct sk_buff *)priv; 1113 int ret; 1114 1115 ret = hns3_fill_skb_desc(ring, skb, desc); 1116 if (unlikely(ret < 0)) 1117 return ret; 1118 1119 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1120 } else { 1121 frag = (skb_frag_t *)priv; 1122 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1123 } 1124 1125 if (unlikely(dma_mapping_error(dev, dma))) { 1126 u64_stats_update_begin(&ring->syncp); 1127 ring->stats.sw_err_cnt++; 1128 u64_stats_update_end(&ring->syncp); 1129 return -ENOMEM; 1130 } 1131 1132 desc_cb->length = size; 1133 1134 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1135 desc_cb->priv = priv; 1136 desc_cb->dma = dma; 1137 desc_cb->type = type; 1138 desc->addr = cpu_to_le64(dma); 1139 desc->tx.send_size = cpu_to_le16(size); 1140 desc->tx.bdtp_fe_sc_vld_ra_ri = 1141 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1142 1143 ring_ptr_move_fw(ring, next_to_use); 1144 return HNS3_LIKELY_BD_NUM; 1145 } 1146 1147 frag_buf_num = hns3_tx_bd_count(size); 1148 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1149 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1150 1151 /* When frag size is bigger than hardware limit, split this frag */ 1152 for (k = 0; k < frag_buf_num; k++) { 1153 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1154 desc_cb->priv = priv; 1155 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1156 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1157 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1158 1159 /* now, fill the descriptor */ 1160 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1161 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1162 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1163 desc->tx.bdtp_fe_sc_vld_ra_ri = 1164 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1165 1166 /* move ring pointer to next */ 1167 ring_ptr_move_fw(ring, next_to_use); 1168 1169 desc_cb = &ring->desc_cb[ring->next_to_use]; 1170 desc = &ring->desc[ring->next_to_use]; 1171 } 1172 1173 return frag_buf_num; 1174 } 1175 1176 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1177 unsigned int bd_num) 1178 { 1179 unsigned int size; 1180 int i; 1181 1182 size = skb_headlen(skb); 1183 while (size > HNS3_MAX_BD_SIZE) { 1184 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1185 size -= HNS3_MAX_BD_SIZE; 1186 1187 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1188 return bd_num; 1189 } 1190 1191 if (size) { 1192 bd_size[bd_num++] = size; 1193 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1194 return bd_num; 1195 } 1196 1197 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1198 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1199 size = skb_frag_size(frag); 1200 if (!size) 1201 continue; 1202 1203 while (size > HNS3_MAX_BD_SIZE) { 1204 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1205 size -= HNS3_MAX_BD_SIZE; 1206 1207 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1208 return bd_num; 1209 } 1210 1211 bd_size[bd_num++] = size; 1212 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1213 return bd_num; 1214 } 1215 1216 return bd_num; 1217 } 1218 1219 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size) 1220 { 1221 struct sk_buff *frag_skb; 1222 unsigned int bd_num = 0; 1223 1224 /* If the total len is within the max bd limit */ 1225 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1226 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM)) 1227 return skb_shinfo(skb)->nr_frags + 1U; 1228 1229 /* The below case will always be linearized, return 1230 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1231 */ 1232 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1233 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE))) 1234 return HNS3_MAX_TSO_BD_NUM + 1U; 1235 1236 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1237 1238 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1239 return bd_num; 1240 1241 skb_walk_frags(skb, frag_skb) { 1242 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1243 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1244 return bd_num; 1245 } 1246 1247 return bd_num; 1248 } 1249 1250 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1251 { 1252 if (!skb->encapsulation) 1253 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1254 1255 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1256 } 1257 1258 /* HW need every continuous 8 buffer data to be larger than MSS, 1259 * we simplify it by ensuring skb_headlen + the first continuous 1260 * 7 frags to to be larger than gso header len + mss, and the remaining 1261 * continuous 7 frags to be larger than MSS except the last 7 frags. 1262 */ 1263 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1264 unsigned int bd_num) 1265 { 1266 unsigned int tot_len = 0; 1267 int i; 1268 1269 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++) 1270 tot_len += bd_size[i]; 1271 1272 /* ensure the first 8 frags is greater than mss + header */ 1273 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] < 1274 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1275 return true; 1276 1277 /* ensure every continuous 7 buffer is greater than mss 1278 * except the last one. 1279 */ 1280 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) { 1281 tot_len -= bd_size[i]; 1282 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U]; 1283 1284 if (tot_len < skb_shinfo(skb)->gso_size) 1285 return true; 1286 } 1287 1288 return false; 1289 } 1290 1291 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1292 struct net_device *netdev, 1293 struct sk_buff *skb) 1294 { 1295 struct hns3_nic_priv *priv = netdev_priv(netdev); 1296 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1297 unsigned int bd_num; 1298 1299 bd_num = hns3_tx_bd_num(skb, bd_size); 1300 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1301 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1302 !hns3_skb_need_linearized(skb, bd_size, bd_num)) 1303 goto out; 1304 1305 if (__skb_linearize(skb)) 1306 return -ENOMEM; 1307 1308 bd_num = hns3_tx_bd_count(skb->len); 1309 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1310 (!skb_is_gso(skb) && 1311 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) 1312 return -ENOMEM; 1313 1314 u64_stats_update_begin(&ring->syncp); 1315 ring->stats.tx_copy++; 1316 u64_stats_update_end(&ring->syncp); 1317 } 1318 1319 out: 1320 if (likely(ring_space(ring) >= bd_num)) 1321 return bd_num; 1322 1323 netif_stop_subqueue(netdev, ring->queue_index); 1324 smp_mb(); /* Memory barrier before checking ring_space */ 1325 1326 /* Start queue in case hns3_clean_tx_ring has just made room 1327 * available and has not seen the queue stopped state performed 1328 * by netif_stop_subqueue above. 1329 */ 1330 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1331 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1332 netif_start_subqueue(netdev, ring->queue_index); 1333 return bd_num; 1334 } 1335 1336 return -EBUSY; 1337 } 1338 1339 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1340 { 1341 struct device *dev = ring_to_dev(ring); 1342 unsigned int i; 1343 1344 for (i = 0; i < ring->desc_num; i++) { 1345 /* check if this is where we started */ 1346 if (ring->next_to_use == next_to_use_orig) 1347 break; 1348 1349 /* rollback one */ 1350 ring_ptr_move_bw(ring, next_to_use); 1351 1352 /* unmap the descriptor dma address */ 1353 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1354 dma_unmap_single(dev, 1355 ring->desc_cb[ring->next_to_use].dma, 1356 ring->desc_cb[ring->next_to_use].length, 1357 DMA_TO_DEVICE); 1358 else if (ring->desc_cb[ring->next_to_use].length) 1359 dma_unmap_page(dev, 1360 ring->desc_cb[ring->next_to_use].dma, 1361 ring->desc_cb[ring->next_to_use].length, 1362 DMA_TO_DEVICE); 1363 1364 ring->desc_cb[ring->next_to_use].length = 0; 1365 ring->desc_cb[ring->next_to_use].dma = 0; 1366 } 1367 } 1368 1369 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1370 struct sk_buff *skb, enum hns_desc_type type) 1371 { 1372 unsigned int size = skb_headlen(skb); 1373 int i, ret, bd_num = 0; 1374 1375 if (size) { 1376 ret = hns3_fill_desc(ring, skb, size, type); 1377 if (unlikely(ret < 0)) 1378 return ret; 1379 1380 bd_num += ret; 1381 } 1382 1383 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1384 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1385 1386 size = skb_frag_size(frag); 1387 if (!size) 1388 continue; 1389 1390 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1391 if (unlikely(ret < 0)) 1392 return ret; 1393 1394 bd_num += ret; 1395 } 1396 1397 return bd_num; 1398 } 1399 1400 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1401 { 1402 struct hns3_nic_priv *priv = netdev_priv(netdev); 1403 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1404 struct netdev_queue *dev_queue; 1405 int pre_ntu, next_to_use_head; 1406 struct sk_buff *frag_skb; 1407 int bd_num = 0; 1408 int ret; 1409 1410 /* Hardware can only handle short frames above 32 bytes */ 1411 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) 1412 return NETDEV_TX_OK; 1413 1414 /* Prefetch the data used later */ 1415 prefetch(skb->data); 1416 1417 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1418 if (unlikely(ret <= 0)) { 1419 if (ret == -EBUSY) { 1420 u64_stats_update_begin(&ring->syncp); 1421 ring->stats.tx_busy++; 1422 u64_stats_update_end(&ring->syncp); 1423 return NETDEV_TX_BUSY; 1424 } else if (ret == -ENOMEM) { 1425 u64_stats_update_begin(&ring->syncp); 1426 ring->stats.sw_err_cnt++; 1427 u64_stats_update_end(&ring->syncp); 1428 } 1429 1430 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1431 goto out_err_tx_ok; 1432 } 1433 1434 next_to_use_head = ring->next_to_use; 1435 1436 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1437 if (unlikely(ret < 0)) 1438 goto fill_err; 1439 1440 bd_num += ret; 1441 1442 if (!skb_has_frag_list(skb)) 1443 goto out; 1444 1445 skb_walk_frags(skb, frag_skb) { 1446 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE); 1447 if (unlikely(ret < 0)) 1448 goto fill_err; 1449 1450 bd_num += ret; 1451 } 1452 out: 1453 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1454 (ring->desc_num - 1); 1455 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1456 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1457 1458 /* Complete translate all packets */ 1459 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1460 netdev_tx_sent_queue(dev_queue, skb->len); 1461 1462 wmb(); /* Commit all data before submit */ 1463 1464 hnae3_queue_xmit(ring->tqp, bd_num); 1465 1466 return NETDEV_TX_OK; 1467 1468 fill_err: 1469 hns3_clear_desc(ring, next_to_use_head); 1470 1471 out_err_tx_ok: 1472 dev_kfree_skb_any(skb); 1473 return NETDEV_TX_OK; 1474 } 1475 1476 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1477 { 1478 struct hnae3_handle *h = hns3_get_handle(netdev); 1479 struct sockaddr *mac_addr = p; 1480 int ret; 1481 1482 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1483 return -EADDRNOTAVAIL; 1484 1485 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1486 netdev_info(netdev, "already using mac address %pM\n", 1487 mac_addr->sa_data); 1488 return 0; 1489 } 1490 1491 /* For VF device, if there is a perm_addr, then the user will not 1492 * be allowed to change the address. 1493 */ 1494 if (!hns3_is_phys_func(h->pdev) && 1495 !is_zero_ether_addr(netdev->perm_addr)) { 1496 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1497 netdev->perm_addr, mac_addr->sa_data); 1498 return -EPERM; 1499 } 1500 1501 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1502 if (ret) { 1503 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1504 return ret; 1505 } 1506 1507 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1508 1509 return 0; 1510 } 1511 1512 static int hns3_nic_do_ioctl(struct net_device *netdev, 1513 struct ifreq *ifr, int cmd) 1514 { 1515 struct hnae3_handle *h = hns3_get_handle(netdev); 1516 1517 if (!netif_running(netdev)) 1518 return -EINVAL; 1519 1520 if (!h->ae_algo->ops->do_ioctl) 1521 return -EOPNOTSUPP; 1522 1523 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1524 } 1525 1526 static int hns3_nic_set_features(struct net_device *netdev, 1527 netdev_features_t features) 1528 { 1529 netdev_features_t changed = netdev->features ^ features; 1530 struct hns3_nic_priv *priv = netdev_priv(netdev); 1531 struct hnae3_handle *h = priv->ae_handle; 1532 bool enable; 1533 int ret; 1534 1535 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1536 enable = !!(features & NETIF_F_GRO_HW); 1537 ret = h->ae_algo->ops->set_gro_en(h, enable); 1538 if (ret) 1539 return ret; 1540 } 1541 1542 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1543 h->ae_algo->ops->enable_vlan_filter) { 1544 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1545 h->ae_algo->ops->enable_vlan_filter(h, enable); 1546 } 1547 1548 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1549 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1550 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1551 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1552 if (ret) 1553 return ret; 1554 } 1555 1556 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1557 enable = !!(features & NETIF_F_NTUPLE); 1558 h->ae_algo->ops->enable_fd(h, enable); 1559 } 1560 1561 netdev->features = features; 1562 return 0; 1563 } 1564 1565 static void hns3_nic_get_stats64(struct net_device *netdev, 1566 struct rtnl_link_stats64 *stats) 1567 { 1568 struct hns3_nic_priv *priv = netdev_priv(netdev); 1569 int queue_num = priv->ae_handle->kinfo.num_tqps; 1570 struct hnae3_handle *handle = priv->ae_handle; 1571 struct hns3_enet_ring *ring; 1572 u64 rx_length_errors = 0; 1573 u64 rx_crc_errors = 0; 1574 u64 rx_multicast = 0; 1575 unsigned int start; 1576 u64 tx_errors = 0; 1577 u64 rx_errors = 0; 1578 unsigned int idx; 1579 u64 tx_bytes = 0; 1580 u64 rx_bytes = 0; 1581 u64 tx_pkts = 0; 1582 u64 rx_pkts = 0; 1583 u64 tx_drop = 0; 1584 u64 rx_drop = 0; 1585 1586 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1587 return; 1588 1589 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1590 1591 for (idx = 0; idx < queue_num; idx++) { 1592 /* fetch the tx stats */ 1593 ring = &priv->ring[idx]; 1594 do { 1595 start = u64_stats_fetch_begin_irq(&ring->syncp); 1596 tx_bytes += ring->stats.tx_bytes; 1597 tx_pkts += ring->stats.tx_pkts; 1598 tx_drop += ring->stats.sw_err_cnt; 1599 tx_drop += ring->stats.tx_vlan_err; 1600 tx_drop += ring->stats.tx_l4_proto_err; 1601 tx_drop += ring->stats.tx_l2l3l4_err; 1602 tx_drop += ring->stats.tx_tso_err; 1603 tx_errors += ring->stats.sw_err_cnt; 1604 tx_errors += ring->stats.tx_vlan_err; 1605 tx_errors += ring->stats.tx_l4_proto_err; 1606 tx_errors += ring->stats.tx_l2l3l4_err; 1607 tx_errors += ring->stats.tx_tso_err; 1608 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1609 1610 /* fetch the rx stats */ 1611 ring = &priv->ring[idx + queue_num]; 1612 do { 1613 start = u64_stats_fetch_begin_irq(&ring->syncp); 1614 rx_bytes += ring->stats.rx_bytes; 1615 rx_pkts += ring->stats.rx_pkts; 1616 rx_drop += ring->stats.l2_err; 1617 rx_errors += ring->stats.l2_err; 1618 rx_errors += ring->stats.l3l4_csum_err; 1619 rx_crc_errors += ring->stats.l2_err; 1620 rx_multicast += ring->stats.rx_multicast; 1621 rx_length_errors += ring->stats.err_pkt_len; 1622 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1623 } 1624 1625 stats->tx_bytes = tx_bytes; 1626 stats->tx_packets = tx_pkts; 1627 stats->rx_bytes = rx_bytes; 1628 stats->rx_packets = rx_pkts; 1629 1630 stats->rx_errors = rx_errors; 1631 stats->multicast = rx_multicast; 1632 stats->rx_length_errors = rx_length_errors; 1633 stats->rx_crc_errors = rx_crc_errors; 1634 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1635 1636 stats->tx_errors = tx_errors; 1637 stats->rx_dropped = rx_drop; 1638 stats->tx_dropped = tx_drop; 1639 stats->collisions = netdev->stats.collisions; 1640 stats->rx_over_errors = netdev->stats.rx_over_errors; 1641 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1642 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1643 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1644 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1645 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1646 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1647 stats->tx_window_errors = netdev->stats.tx_window_errors; 1648 stats->rx_compressed = netdev->stats.rx_compressed; 1649 stats->tx_compressed = netdev->stats.tx_compressed; 1650 } 1651 1652 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1653 { 1654 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1655 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1656 struct hnae3_knic_private_info *kinfo; 1657 u8 tc = mqprio_qopt->qopt.num_tc; 1658 u16 mode = mqprio_qopt->mode; 1659 u8 hw = mqprio_qopt->qopt.hw; 1660 struct hnae3_handle *h; 1661 1662 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1663 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1664 return -EOPNOTSUPP; 1665 1666 if (tc > HNAE3_MAX_TC) 1667 return -EINVAL; 1668 1669 if (!netdev) 1670 return -EINVAL; 1671 1672 h = hns3_get_handle(netdev); 1673 kinfo = &h->kinfo; 1674 1675 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1676 1677 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1678 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1679 } 1680 1681 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1682 void *type_data) 1683 { 1684 if (type != TC_SETUP_QDISC_MQPRIO) 1685 return -EOPNOTSUPP; 1686 1687 return hns3_setup_tc(dev, type_data); 1688 } 1689 1690 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1691 __be16 proto, u16 vid) 1692 { 1693 struct hnae3_handle *h = hns3_get_handle(netdev); 1694 int ret = -EIO; 1695 1696 if (h->ae_algo->ops->set_vlan_filter) 1697 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1698 1699 return ret; 1700 } 1701 1702 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1703 __be16 proto, u16 vid) 1704 { 1705 struct hnae3_handle *h = hns3_get_handle(netdev); 1706 int ret = -EIO; 1707 1708 if (h->ae_algo->ops->set_vlan_filter) 1709 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1710 1711 return ret; 1712 } 1713 1714 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1715 u8 qos, __be16 vlan_proto) 1716 { 1717 struct hnae3_handle *h = hns3_get_handle(netdev); 1718 int ret = -EIO; 1719 1720 netif_dbg(h, drv, netdev, 1721 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1722 vf, vlan, qos, ntohs(vlan_proto)); 1723 1724 if (h->ae_algo->ops->set_vf_vlan_filter) 1725 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1726 qos, vlan_proto); 1727 1728 return ret; 1729 } 1730 1731 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1732 { 1733 struct hnae3_handle *handle = hns3_get_handle(netdev); 1734 1735 if (hns3_nic_resetting(netdev)) 1736 return -EBUSY; 1737 1738 if (!handle->ae_algo->ops->set_vf_spoofchk) 1739 return -EOPNOTSUPP; 1740 1741 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1742 } 1743 1744 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1745 { 1746 struct hnae3_handle *handle = hns3_get_handle(netdev); 1747 1748 if (!handle->ae_algo->ops->set_vf_trust) 1749 return -EOPNOTSUPP; 1750 1751 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1752 } 1753 1754 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1755 { 1756 struct hnae3_handle *h = hns3_get_handle(netdev); 1757 int ret; 1758 1759 if (hns3_nic_resetting(netdev)) 1760 return -EBUSY; 1761 1762 if (!h->ae_algo->ops->set_mtu) 1763 return -EOPNOTSUPP; 1764 1765 netif_dbg(h, drv, netdev, 1766 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1767 1768 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1769 if (ret) 1770 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1771 ret); 1772 else 1773 netdev->mtu = new_mtu; 1774 1775 return ret; 1776 } 1777 1778 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1779 { 1780 struct hns3_nic_priv *priv = netdev_priv(ndev); 1781 struct hnae3_handle *h = hns3_get_handle(ndev); 1782 struct hns3_enet_ring *tx_ring; 1783 struct napi_struct *napi; 1784 int timeout_queue = 0; 1785 int hw_head, hw_tail; 1786 int fbd_num, fbd_oft; 1787 int ebd_num, ebd_oft; 1788 int bd_num, bd_err; 1789 int ring_en, tc; 1790 int i; 1791 1792 /* Find the stopped queue the same way the stack does */ 1793 for (i = 0; i < ndev->num_tx_queues; i++) { 1794 struct netdev_queue *q; 1795 unsigned long trans_start; 1796 1797 q = netdev_get_tx_queue(ndev, i); 1798 trans_start = q->trans_start; 1799 if (netif_xmit_stopped(q) && 1800 time_after(jiffies, 1801 (trans_start + ndev->watchdog_timeo))) { 1802 timeout_queue = i; 1803 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1804 q->state, 1805 jiffies_to_msecs(jiffies - trans_start)); 1806 break; 1807 } 1808 } 1809 1810 if (i == ndev->num_tx_queues) { 1811 netdev_info(ndev, 1812 "no netdev TX timeout queue found, timeout count: %llu\n", 1813 priv->tx_timeout_count); 1814 return false; 1815 } 1816 1817 priv->tx_timeout_count++; 1818 1819 tx_ring = &priv->ring[timeout_queue]; 1820 napi = &tx_ring->tqp_vector->napi; 1821 1822 netdev_info(ndev, 1823 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1824 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1825 tx_ring->next_to_clean, napi->state); 1826 1827 netdev_info(ndev, 1828 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1829 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1830 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1831 1832 netdev_info(ndev, 1833 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1834 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1835 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1836 1837 /* When mac received many pause frames continuous, it's unable to send 1838 * packets, which may cause tx timeout 1839 */ 1840 if (h->ae_algo->ops->get_mac_stats) { 1841 struct hns3_mac_stats mac_stats; 1842 1843 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1844 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1845 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1846 } 1847 1848 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1849 HNS3_RING_TX_RING_HEAD_REG); 1850 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1851 HNS3_RING_TX_RING_TAIL_REG); 1852 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1853 HNS3_RING_TX_RING_FBDNUM_REG); 1854 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1855 HNS3_RING_TX_RING_OFFSET_REG); 1856 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1857 HNS3_RING_TX_RING_EBDNUM_REG); 1858 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1859 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1860 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1861 HNS3_RING_TX_RING_BD_NUM_REG); 1862 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1863 HNS3_RING_TX_RING_BD_ERR_REG); 1864 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1865 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1866 1867 netdev_info(ndev, 1868 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1869 bd_num, hw_head, hw_tail, bd_err, 1870 readl(tx_ring->tqp_vector->mask_addr)); 1871 netdev_info(ndev, 1872 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1873 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1874 1875 return true; 1876 } 1877 1878 static void hns3_nic_net_timeout(struct net_device *ndev) 1879 { 1880 struct hns3_nic_priv *priv = netdev_priv(ndev); 1881 struct hnae3_handle *h = priv->ae_handle; 1882 1883 if (!hns3_get_tx_timeo_queue_info(ndev)) 1884 return; 1885 1886 /* request the reset, and let the hclge to determine 1887 * which reset level should be done 1888 */ 1889 if (h->ae_algo->ops->reset_event) 1890 h->ae_algo->ops->reset_event(h->pdev, h); 1891 } 1892 1893 #ifdef CONFIG_RFS_ACCEL 1894 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1895 u16 rxq_index, u32 flow_id) 1896 { 1897 struct hnae3_handle *h = hns3_get_handle(dev); 1898 struct flow_keys fkeys; 1899 1900 if (!h->ae_algo->ops->add_arfs_entry) 1901 return -EOPNOTSUPP; 1902 1903 if (skb->encapsulation) 1904 return -EPROTONOSUPPORT; 1905 1906 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1907 return -EPROTONOSUPPORT; 1908 1909 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1910 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1911 (fkeys.basic.ip_proto != IPPROTO_TCP && 1912 fkeys.basic.ip_proto != IPPROTO_UDP)) 1913 return -EPROTONOSUPPORT; 1914 1915 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1916 } 1917 #endif 1918 1919 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 1920 struct ifla_vf_info *ivf) 1921 { 1922 struct hnae3_handle *h = hns3_get_handle(ndev); 1923 1924 if (!h->ae_algo->ops->get_vf_config) 1925 return -EOPNOTSUPP; 1926 1927 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 1928 } 1929 1930 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 1931 int link_state) 1932 { 1933 struct hnae3_handle *h = hns3_get_handle(ndev); 1934 1935 if (!h->ae_algo->ops->set_vf_link_state) 1936 return -EOPNOTSUPP; 1937 1938 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 1939 } 1940 1941 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 1942 int min_tx_rate, int max_tx_rate) 1943 { 1944 struct hnae3_handle *h = hns3_get_handle(ndev); 1945 1946 if (!h->ae_algo->ops->set_vf_rate) 1947 return -EOPNOTSUPP; 1948 1949 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 1950 false); 1951 } 1952 1953 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 1954 { 1955 struct hnae3_handle *h = hns3_get_handle(netdev); 1956 1957 if (!h->ae_algo->ops->set_vf_mac) 1958 return -EOPNOTSUPP; 1959 1960 if (is_multicast_ether_addr(mac)) { 1961 netdev_err(netdev, 1962 "Invalid MAC:%pM specified. Could not set MAC\n", 1963 mac); 1964 return -EINVAL; 1965 } 1966 1967 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 1968 } 1969 1970 static const struct net_device_ops hns3_nic_netdev_ops = { 1971 .ndo_open = hns3_nic_net_open, 1972 .ndo_stop = hns3_nic_net_stop, 1973 .ndo_start_xmit = hns3_nic_net_xmit, 1974 .ndo_tx_timeout = hns3_nic_net_timeout, 1975 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1976 .ndo_do_ioctl = hns3_nic_do_ioctl, 1977 .ndo_change_mtu = hns3_nic_change_mtu, 1978 .ndo_set_features = hns3_nic_set_features, 1979 .ndo_get_stats64 = hns3_nic_get_stats64, 1980 .ndo_setup_tc = hns3_nic_setup_tc, 1981 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1982 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1983 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1984 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1985 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 1986 .ndo_set_vf_trust = hns3_set_vf_trust, 1987 #ifdef CONFIG_RFS_ACCEL 1988 .ndo_rx_flow_steer = hns3_rx_flow_steer, 1989 #endif 1990 .ndo_get_vf_config = hns3_nic_get_vf_config, 1991 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 1992 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 1993 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 1994 }; 1995 1996 bool hns3_is_phys_func(struct pci_dev *pdev) 1997 { 1998 u32 dev_id = pdev->device; 1999 2000 switch (dev_id) { 2001 case HNAE3_DEV_ID_GE: 2002 case HNAE3_DEV_ID_25GE: 2003 case HNAE3_DEV_ID_25GE_RDMA: 2004 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2005 case HNAE3_DEV_ID_50GE_RDMA: 2006 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2007 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2008 return true; 2009 case HNAE3_DEV_ID_100G_VF: 2010 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 2011 return false; 2012 default: 2013 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2014 dev_id); 2015 } 2016 2017 return false; 2018 } 2019 2020 static void hns3_disable_sriov(struct pci_dev *pdev) 2021 { 2022 /* If our VFs are assigned we cannot shut down SR-IOV 2023 * without causing issues, so just leave the hardware 2024 * available but disabled 2025 */ 2026 if (pci_vfs_assigned(pdev)) { 2027 dev_warn(&pdev->dev, 2028 "disabling driver while VFs are assigned\n"); 2029 return; 2030 } 2031 2032 pci_disable_sriov(pdev); 2033 } 2034 2035 static void hns3_get_dev_capability(struct pci_dev *pdev, 2036 struct hnae3_ae_dev *ae_dev) 2037 { 2038 if (pdev->revision >= 0x21) { 2039 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 2040 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 2041 } 2042 } 2043 2044 /* hns3_probe - Device initialization routine 2045 * @pdev: PCI device information struct 2046 * @ent: entry in hns3_pci_tbl 2047 * 2048 * hns3_probe initializes a PF identified by a pci_dev structure. 2049 * The OS initialization, configuring of the PF private structure, 2050 * and a hardware reset occur. 2051 * 2052 * Returns 0 on success, negative on failure 2053 */ 2054 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2055 { 2056 struct hnae3_ae_dev *ae_dev; 2057 int ret; 2058 2059 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2060 if (!ae_dev) { 2061 ret = -ENOMEM; 2062 return ret; 2063 } 2064 2065 ae_dev->pdev = pdev; 2066 ae_dev->flag = ent->driver_data; 2067 ae_dev->reset_type = HNAE3_NONE_RESET; 2068 hns3_get_dev_capability(pdev, ae_dev); 2069 pci_set_drvdata(pdev, ae_dev); 2070 2071 ret = hnae3_register_ae_dev(ae_dev); 2072 if (ret) { 2073 devm_kfree(&pdev->dev, ae_dev); 2074 pci_set_drvdata(pdev, NULL); 2075 } 2076 2077 return ret; 2078 } 2079 2080 /* hns3_remove - Device removal routine 2081 * @pdev: PCI device information struct 2082 */ 2083 static void hns3_remove(struct pci_dev *pdev) 2084 { 2085 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2086 2087 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2088 hns3_disable_sriov(pdev); 2089 2090 hnae3_unregister_ae_dev(ae_dev); 2091 pci_set_drvdata(pdev, NULL); 2092 } 2093 2094 /** 2095 * hns3_pci_sriov_configure 2096 * @pdev: pointer to a pci_dev structure 2097 * @num_vfs: number of VFs to allocate 2098 * 2099 * Enable or change the number of VFs. Called when the user updates the number 2100 * of VFs in sysfs. 2101 **/ 2102 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2103 { 2104 int ret; 2105 2106 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2107 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2108 return -EINVAL; 2109 } 2110 2111 if (num_vfs) { 2112 ret = pci_enable_sriov(pdev, num_vfs); 2113 if (ret) 2114 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2115 else 2116 return num_vfs; 2117 } else if (!pci_vfs_assigned(pdev)) { 2118 pci_disable_sriov(pdev); 2119 } else { 2120 dev_warn(&pdev->dev, 2121 "Unable to free VFs because some are assigned to VMs.\n"); 2122 } 2123 2124 return 0; 2125 } 2126 2127 static void hns3_shutdown(struct pci_dev *pdev) 2128 { 2129 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2130 2131 hnae3_unregister_ae_dev(ae_dev); 2132 devm_kfree(&pdev->dev, ae_dev); 2133 pci_set_drvdata(pdev, NULL); 2134 2135 if (system_state == SYSTEM_POWER_OFF) 2136 pci_set_power_state(pdev, PCI_D3hot); 2137 } 2138 2139 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2140 pci_channel_state_t state) 2141 { 2142 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2143 pci_ers_result_t ret; 2144 2145 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2146 2147 if (state == pci_channel_io_perm_failure) 2148 return PCI_ERS_RESULT_DISCONNECT; 2149 2150 if (!ae_dev || !ae_dev->ops) { 2151 dev_err(&pdev->dev, 2152 "Can't recover - error happened before device initialized\n"); 2153 return PCI_ERS_RESULT_NONE; 2154 } 2155 2156 if (ae_dev->ops->handle_hw_ras_error) 2157 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2158 else 2159 return PCI_ERS_RESULT_NONE; 2160 2161 return ret; 2162 } 2163 2164 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2165 { 2166 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2167 const struct hnae3_ae_ops *ops; 2168 enum hnae3_reset_type reset_type; 2169 struct device *dev = &pdev->dev; 2170 2171 if (!ae_dev || !ae_dev->ops) 2172 return PCI_ERS_RESULT_NONE; 2173 2174 ops = ae_dev->ops; 2175 /* request the reset */ 2176 if (ops->reset_event && ops->get_reset_level && 2177 ops->set_default_reset_request) { 2178 if (ae_dev->hw_err_reset_req) { 2179 reset_type = ops->get_reset_level(ae_dev, 2180 &ae_dev->hw_err_reset_req); 2181 ops->set_default_reset_request(ae_dev, reset_type); 2182 dev_info(dev, "requesting reset due to PCI error\n"); 2183 ops->reset_event(pdev, NULL); 2184 } 2185 2186 return PCI_ERS_RESULT_RECOVERED; 2187 } 2188 2189 return PCI_ERS_RESULT_DISCONNECT; 2190 } 2191 2192 static void hns3_reset_prepare(struct pci_dev *pdev) 2193 { 2194 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2195 2196 dev_info(&pdev->dev, "hns3 flr prepare\n"); 2197 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2198 ae_dev->ops->flr_prepare(ae_dev); 2199 } 2200 2201 static void hns3_reset_done(struct pci_dev *pdev) 2202 { 2203 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2204 2205 dev_info(&pdev->dev, "hns3 flr done\n"); 2206 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2207 ae_dev->ops->flr_done(ae_dev); 2208 } 2209 2210 static const struct pci_error_handlers hns3_err_handler = { 2211 .error_detected = hns3_error_detected, 2212 .slot_reset = hns3_slot_reset, 2213 .reset_prepare = hns3_reset_prepare, 2214 .reset_done = hns3_reset_done, 2215 }; 2216 2217 static struct pci_driver hns3_driver = { 2218 .name = hns3_driver_name, 2219 .id_table = hns3_pci_tbl, 2220 .probe = hns3_probe, 2221 .remove = hns3_remove, 2222 .shutdown = hns3_shutdown, 2223 .sriov_configure = hns3_pci_sriov_configure, 2224 .err_handler = &hns3_err_handler, 2225 }; 2226 2227 /* set default feature to hns3 */ 2228 static void hns3_set_default_feature(struct net_device *netdev) 2229 { 2230 struct hnae3_handle *h = hns3_get_handle(netdev); 2231 struct pci_dev *pdev = h->pdev; 2232 2233 netdev->priv_flags |= IFF_UNICAST_FLT; 2234 2235 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2236 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2237 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2238 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2239 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2240 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2241 2242 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2243 2244 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2245 NETIF_F_HW_VLAN_CTAG_FILTER | 2246 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2247 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2248 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2249 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2250 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2251 NETIF_F_FRAGLIST; 2252 2253 netdev->vlan_features |= 2254 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2255 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2256 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2257 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2258 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2259 NETIF_F_FRAGLIST; 2260 2261 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2262 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2263 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2264 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2265 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2266 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2267 NETIF_F_FRAGLIST; 2268 2269 if (pdev->revision >= 0x21) { 2270 netdev->hw_features |= NETIF_F_GRO_HW; 2271 netdev->features |= NETIF_F_GRO_HW; 2272 2273 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2274 netdev->hw_features |= NETIF_F_NTUPLE; 2275 netdev->features |= NETIF_F_NTUPLE; 2276 } 2277 } 2278 } 2279 2280 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2281 struct hns3_desc_cb *cb) 2282 { 2283 unsigned int order = hns3_page_order(ring); 2284 struct page *p; 2285 2286 p = dev_alloc_pages(order); 2287 if (!p) 2288 return -ENOMEM; 2289 2290 cb->priv = p; 2291 cb->page_offset = 0; 2292 cb->reuse_flag = 0; 2293 cb->buf = page_address(p); 2294 cb->length = hns3_page_size(ring); 2295 cb->type = DESC_TYPE_PAGE; 2296 2297 return 0; 2298 } 2299 2300 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2301 struct hns3_desc_cb *cb) 2302 { 2303 if (cb->type == DESC_TYPE_SKB) 2304 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2305 else if (!HNAE3_IS_TX_RING(ring)) 2306 put_page((struct page *)cb->priv); 2307 memset(cb, 0, sizeof(*cb)); 2308 } 2309 2310 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2311 { 2312 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2313 cb->length, ring_to_dma_dir(ring)); 2314 2315 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2316 return -EIO; 2317 2318 return 0; 2319 } 2320 2321 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2322 struct hns3_desc_cb *cb) 2323 { 2324 if (cb->type == DESC_TYPE_SKB) 2325 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2326 ring_to_dma_dir(ring)); 2327 else if (cb->length) 2328 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2329 ring_to_dma_dir(ring)); 2330 } 2331 2332 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2333 { 2334 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2335 ring->desc[i].addr = 0; 2336 } 2337 2338 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2339 { 2340 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2341 2342 if (!ring->desc_cb[i].dma) 2343 return; 2344 2345 hns3_buffer_detach(ring, i); 2346 hns3_free_buffer(ring, cb); 2347 } 2348 2349 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2350 { 2351 int i; 2352 2353 for (i = 0; i < ring->desc_num; i++) 2354 hns3_free_buffer_detach(ring, i); 2355 } 2356 2357 /* free desc along with its attached buffer */ 2358 static void hns3_free_desc(struct hns3_enet_ring *ring) 2359 { 2360 int size = ring->desc_num * sizeof(ring->desc[0]); 2361 2362 hns3_free_buffers(ring); 2363 2364 if (ring->desc) { 2365 dma_free_coherent(ring_to_dev(ring), size, 2366 ring->desc, ring->desc_dma_addr); 2367 ring->desc = NULL; 2368 } 2369 } 2370 2371 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2372 { 2373 int size = ring->desc_num * sizeof(ring->desc[0]); 2374 2375 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2376 &ring->desc_dma_addr, GFP_KERNEL); 2377 if (!ring->desc) 2378 return -ENOMEM; 2379 2380 return 0; 2381 } 2382 2383 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2384 struct hns3_desc_cb *cb) 2385 { 2386 int ret; 2387 2388 ret = hns3_alloc_buffer(ring, cb); 2389 if (ret) 2390 goto out; 2391 2392 ret = hns3_map_buffer(ring, cb); 2393 if (ret) 2394 goto out_with_buf; 2395 2396 return 0; 2397 2398 out_with_buf: 2399 hns3_free_buffer(ring, cb); 2400 out: 2401 return ret; 2402 } 2403 2404 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2405 { 2406 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2407 2408 if (ret) 2409 return ret; 2410 2411 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2412 2413 return 0; 2414 } 2415 2416 /* Allocate memory for raw pkg, and map with dma */ 2417 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2418 { 2419 int i, j, ret; 2420 2421 for (i = 0; i < ring->desc_num; i++) { 2422 ret = hns3_alloc_buffer_attach(ring, i); 2423 if (ret) 2424 goto out_buffer_fail; 2425 } 2426 2427 return 0; 2428 2429 out_buffer_fail: 2430 for (j = i - 1; j >= 0; j--) 2431 hns3_free_buffer_detach(ring, j); 2432 return ret; 2433 } 2434 2435 /* detach a in-used buffer and replace with a reserved one */ 2436 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2437 struct hns3_desc_cb *res_cb) 2438 { 2439 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2440 ring->desc_cb[i] = *res_cb; 2441 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2442 ring->desc[i].rx.bd_base_info = 0; 2443 } 2444 2445 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2446 { 2447 ring->desc_cb[i].reuse_flag = 0; 2448 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2449 ring->desc_cb[i].page_offset); 2450 ring->desc[i].rx.bd_base_info = 0; 2451 } 2452 2453 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2454 int *bytes, int *pkts) 2455 { 2456 int ntc = ring->next_to_clean; 2457 struct hns3_desc_cb *desc_cb; 2458 2459 while (head != ntc) { 2460 desc_cb = &ring->desc_cb[ntc]; 2461 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2462 (*bytes) += desc_cb->length; 2463 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2464 hns3_free_buffer_detach(ring, ntc); 2465 2466 if (++ntc == ring->desc_num) 2467 ntc = 0; 2468 2469 /* Issue prefetch for next Tx descriptor */ 2470 prefetch(&ring->desc_cb[ntc]); 2471 } 2472 2473 /* This smp_store_release() pairs with smp_load_acquire() in 2474 * ring_space called by hns3_nic_net_xmit. 2475 */ 2476 smp_store_release(&ring->next_to_clean, ntc); 2477 } 2478 2479 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2480 { 2481 int u = ring->next_to_use; 2482 int c = ring->next_to_clean; 2483 2484 if (unlikely(h > ring->desc_num)) 2485 return 0; 2486 2487 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2488 } 2489 2490 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2491 { 2492 struct net_device *netdev = ring_to_netdev(ring); 2493 struct hns3_nic_priv *priv = netdev_priv(netdev); 2494 struct netdev_queue *dev_queue; 2495 int bytes, pkts; 2496 int head; 2497 2498 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2499 2500 if (is_ring_empty(ring) || head == ring->next_to_clean) 2501 return; /* no data to poll */ 2502 2503 rmb(); /* Make sure head is ready before touch any data */ 2504 2505 if (unlikely(!is_valid_clean_head(ring, head))) { 2506 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2507 ring->next_to_use, ring->next_to_clean); 2508 2509 u64_stats_update_begin(&ring->syncp); 2510 ring->stats.io_err_cnt++; 2511 u64_stats_update_end(&ring->syncp); 2512 return; 2513 } 2514 2515 bytes = 0; 2516 pkts = 0; 2517 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2518 2519 ring->tqp_vector->tx_group.total_bytes += bytes; 2520 ring->tqp_vector->tx_group.total_packets += pkts; 2521 2522 u64_stats_update_begin(&ring->syncp); 2523 ring->stats.tx_bytes += bytes; 2524 ring->stats.tx_pkts += pkts; 2525 u64_stats_update_end(&ring->syncp); 2526 2527 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2528 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2529 2530 if (unlikely(netif_carrier_ok(netdev) && 2531 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2532 /* Make sure that anybody stopping the queue after this 2533 * sees the new next_to_clean. 2534 */ 2535 smp_mb(); 2536 if (netif_tx_queue_stopped(dev_queue) && 2537 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2538 netif_tx_wake_queue(dev_queue); 2539 ring->stats.restart_queue++; 2540 } 2541 } 2542 } 2543 2544 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2545 { 2546 int ntc = ring->next_to_clean; 2547 int ntu = ring->next_to_use; 2548 2549 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2550 } 2551 2552 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2553 int cleand_count) 2554 { 2555 struct hns3_desc_cb *desc_cb; 2556 struct hns3_desc_cb res_cbs; 2557 int i, ret; 2558 2559 for (i = 0; i < cleand_count; i++) { 2560 desc_cb = &ring->desc_cb[ring->next_to_use]; 2561 if (desc_cb->reuse_flag) { 2562 u64_stats_update_begin(&ring->syncp); 2563 ring->stats.reuse_pg_cnt++; 2564 u64_stats_update_end(&ring->syncp); 2565 2566 hns3_reuse_buffer(ring, ring->next_to_use); 2567 } else { 2568 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2569 if (ret) { 2570 u64_stats_update_begin(&ring->syncp); 2571 ring->stats.sw_err_cnt++; 2572 u64_stats_update_end(&ring->syncp); 2573 2574 hns3_rl_err(ring_to_netdev(ring), 2575 "alloc rx buffer failed: %d\n", 2576 ret); 2577 break; 2578 } 2579 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2580 2581 u64_stats_update_begin(&ring->syncp); 2582 ring->stats.non_reuse_pg++; 2583 u64_stats_update_end(&ring->syncp); 2584 } 2585 2586 ring_ptr_move_fw(ring, next_to_use); 2587 } 2588 2589 wmb(); /* Make all data has been write before submit */ 2590 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2591 } 2592 2593 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2594 struct hns3_enet_ring *ring, int pull_len, 2595 struct hns3_desc_cb *desc_cb) 2596 { 2597 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2598 int size = le16_to_cpu(desc->rx.size); 2599 u32 truesize = hns3_buf_size(ring); 2600 2601 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2602 size - pull_len, truesize); 2603 2604 /* Avoid re-using remote pages, or the stack is still using the page 2605 * when page_offset rollback to zero, flag default unreuse 2606 */ 2607 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) || 2608 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2609 return; 2610 2611 /* Move offset up to the next cache line */ 2612 desc_cb->page_offset += truesize; 2613 2614 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2615 desc_cb->reuse_flag = 1; 2616 /* Bump ref count on page before it is given */ 2617 get_page(desc_cb->priv); 2618 } else if (page_count(desc_cb->priv) == 1) { 2619 desc_cb->reuse_flag = 1; 2620 desc_cb->page_offset = 0; 2621 get_page(desc_cb->priv); 2622 } 2623 } 2624 2625 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2626 { 2627 __be16 type = skb->protocol; 2628 struct tcphdr *th; 2629 int depth = 0; 2630 2631 while (eth_type_vlan(type)) { 2632 struct vlan_hdr *vh; 2633 2634 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2635 return -EFAULT; 2636 2637 vh = (struct vlan_hdr *)(skb->data + depth); 2638 type = vh->h_vlan_encapsulated_proto; 2639 depth += VLAN_HLEN; 2640 } 2641 2642 skb_set_network_header(skb, depth); 2643 2644 if (type == htons(ETH_P_IP)) { 2645 const struct iphdr *iph = ip_hdr(skb); 2646 2647 depth += sizeof(struct iphdr); 2648 skb_set_transport_header(skb, depth); 2649 th = tcp_hdr(skb); 2650 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2651 iph->daddr, 0); 2652 } else if (type == htons(ETH_P_IPV6)) { 2653 const struct ipv6hdr *iph = ipv6_hdr(skb); 2654 2655 depth += sizeof(struct ipv6hdr); 2656 skb_set_transport_header(skb, depth); 2657 th = tcp_hdr(skb); 2658 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2659 &iph->daddr, 0); 2660 } else { 2661 hns3_rl_err(skb->dev, 2662 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2663 be16_to_cpu(type), depth); 2664 return -EFAULT; 2665 } 2666 2667 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2668 if (th->cwr) 2669 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2670 2671 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2672 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2673 2674 skb->csum_start = (unsigned char *)th - skb->head; 2675 skb->csum_offset = offsetof(struct tcphdr, check); 2676 skb->ip_summed = CHECKSUM_PARTIAL; 2677 return 0; 2678 } 2679 2680 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2681 u32 l234info, u32 bd_base_info, u32 ol_info) 2682 { 2683 struct net_device *netdev = ring_to_netdev(ring); 2684 int l3_type, l4_type; 2685 int ol4_type; 2686 2687 skb->ip_summed = CHECKSUM_NONE; 2688 2689 skb_checksum_none_assert(skb); 2690 2691 if (!(netdev->features & NETIF_F_RXCSUM)) 2692 return; 2693 2694 /* check if hardware has done checksum */ 2695 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2696 return; 2697 2698 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2699 BIT(HNS3_RXD_OL3E_B) | 2700 BIT(HNS3_RXD_OL4E_B)))) { 2701 u64_stats_update_begin(&ring->syncp); 2702 ring->stats.l3l4_csum_err++; 2703 u64_stats_update_end(&ring->syncp); 2704 2705 return; 2706 } 2707 2708 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2709 HNS3_RXD_OL4ID_S); 2710 switch (ol4_type) { 2711 case HNS3_OL4_TYPE_MAC_IN_UDP: 2712 case HNS3_OL4_TYPE_NVGRE: 2713 skb->csum_level = 1; 2714 /* fall through */ 2715 case HNS3_OL4_TYPE_NO_TUN: 2716 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2717 HNS3_RXD_L3ID_S); 2718 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2719 HNS3_RXD_L4ID_S); 2720 2721 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2722 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2723 l3_type == HNS3_L3_TYPE_IPV6) && 2724 (l4_type == HNS3_L4_TYPE_UDP || 2725 l4_type == HNS3_L4_TYPE_TCP || 2726 l4_type == HNS3_L4_TYPE_SCTP)) 2727 skb->ip_summed = CHECKSUM_UNNECESSARY; 2728 break; 2729 default: 2730 break; 2731 } 2732 } 2733 2734 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2735 { 2736 if (skb_has_frag_list(skb)) 2737 napi_gro_flush(&ring->tqp_vector->napi, false); 2738 2739 napi_gro_receive(&ring->tqp_vector->napi, skb); 2740 } 2741 2742 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2743 struct hns3_desc *desc, u32 l234info, 2744 u16 *vlan_tag) 2745 { 2746 struct hnae3_handle *handle = ring->tqp->handle; 2747 struct pci_dev *pdev = ring->tqp->handle->pdev; 2748 2749 if (pdev->revision == 0x20) { 2750 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2751 if (!(*vlan_tag & VLAN_VID_MASK)) 2752 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2753 2754 return (*vlan_tag != 0); 2755 } 2756 2757 #define HNS3_STRP_OUTER_VLAN 0x1 2758 #define HNS3_STRP_INNER_VLAN 0x2 2759 #define HNS3_STRP_BOTH 0x3 2760 2761 /* Hardware always insert VLAN tag into RX descriptor when 2762 * remove the tag from packet, driver needs to determine 2763 * reporting which tag to stack. 2764 */ 2765 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2766 HNS3_RXD_STRP_TAGP_S)) { 2767 case HNS3_STRP_OUTER_VLAN: 2768 if (handle->port_base_vlan_state != 2769 HNAE3_PORT_BASE_VLAN_DISABLE) 2770 return false; 2771 2772 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2773 return true; 2774 case HNS3_STRP_INNER_VLAN: 2775 if (handle->port_base_vlan_state != 2776 HNAE3_PORT_BASE_VLAN_DISABLE) 2777 return false; 2778 2779 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2780 return true; 2781 case HNS3_STRP_BOTH: 2782 if (handle->port_base_vlan_state == 2783 HNAE3_PORT_BASE_VLAN_DISABLE) 2784 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2785 else 2786 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2787 2788 return true; 2789 default: 2790 return false; 2791 } 2792 } 2793 2794 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2795 unsigned char *va) 2796 { 2797 #define HNS3_NEED_ADD_FRAG 1 2798 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2799 struct net_device *netdev = ring_to_netdev(ring); 2800 struct sk_buff *skb; 2801 2802 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2803 skb = ring->skb; 2804 if (unlikely(!skb)) { 2805 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2806 2807 u64_stats_update_begin(&ring->syncp); 2808 ring->stats.sw_err_cnt++; 2809 u64_stats_update_end(&ring->syncp); 2810 2811 return -ENOMEM; 2812 } 2813 2814 prefetchw(skb->data); 2815 2816 ring->pending_buf = 1; 2817 ring->frag_num = 0; 2818 ring->tail_skb = NULL; 2819 if (length <= HNS3_RX_HEAD_SIZE) { 2820 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2821 2822 /* We can reuse buffer as-is, just make sure it is local */ 2823 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id())) 2824 desc_cb->reuse_flag = 1; 2825 else /* This page cannot be reused so discard it */ 2826 put_page(desc_cb->priv); 2827 2828 ring_ptr_move_fw(ring, next_to_clean); 2829 return 0; 2830 } 2831 u64_stats_update_begin(&ring->syncp); 2832 ring->stats.seg_pkt_cnt++; 2833 u64_stats_update_end(&ring->syncp); 2834 2835 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2836 __skb_put(skb, ring->pull_len); 2837 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2838 desc_cb); 2839 ring_ptr_move_fw(ring, next_to_clean); 2840 2841 return HNS3_NEED_ADD_FRAG; 2842 } 2843 2844 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2845 bool pending) 2846 { 2847 struct sk_buff *skb = ring->skb; 2848 struct sk_buff *head_skb = skb; 2849 struct sk_buff *new_skb; 2850 struct hns3_desc_cb *desc_cb; 2851 struct hns3_desc *pre_desc; 2852 u32 bd_base_info; 2853 int pre_bd; 2854 2855 /* if there is pending bd, the SW param next_to_clean has moved 2856 * to next and the next is NULL 2857 */ 2858 if (pending) { 2859 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2860 ring->desc_num; 2861 pre_desc = &ring->desc[pre_bd]; 2862 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2863 } else { 2864 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2865 } 2866 2867 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2868 desc = &ring->desc[ring->next_to_clean]; 2869 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2870 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2871 /* make sure HW write desc complete */ 2872 dma_rmb(); 2873 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2874 return -ENXIO; 2875 2876 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2877 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2878 if (unlikely(!new_skb)) { 2879 hns3_rl_err(ring_to_netdev(ring), 2880 "alloc rx fraglist skb fail\n"); 2881 return -ENXIO; 2882 } 2883 ring->frag_num = 0; 2884 2885 if (ring->tail_skb) { 2886 ring->tail_skb->next = new_skb; 2887 ring->tail_skb = new_skb; 2888 } else { 2889 skb_shinfo(skb)->frag_list = new_skb; 2890 ring->tail_skb = new_skb; 2891 } 2892 } 2893 2894 if (ring->tail_skb) { 2895 head_skb->truesize += hns3_buf_size(ring); 2896 head_skb->data_len += le16_to_cpu(desc->rx.size); 2897 head_skb->len += le16_to_cpu(desc->rx.size); 2898 skb = ring->tail_skb; 2899 } 2900 2901 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2902 ring_ptr_move_fw(ring, next_to_clean); 2903 ring->pending_buf++; 2904 } 2905 2906 return 0; 2907 } 2908 2909 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2910 struct sk_buff *skb, u32 l234info, 2911 u32 bd_base_info, u32 ol_info) 2912 { 2913 u32 l3_type; 2914 2915 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2916 HNS3_RXD_GRO_SIZE_M, 2917 HNS3_RXD_GRO_SIZE_S); 2918 /* if there is no HW GRO, do not set gro params */ 2919 if (!skb_shinfo(skb)->gso_size) { 2920 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2921 return 0; 2922 } 2923 2924 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2925 HNS3_RXD_GRO_COUNT_M, 2926 HNS3_RXD_GRO_COUNT_S); 2927 2928 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2929 if (l3_type == HNS3_L3_TYPE_IPV4) 2930 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2931 else if (l3_type == HNS3_L3_TYPE_IPV6) 2932 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2933 else 2934 return -EFAULT; 2935 2936 return hns3_gro_complete(skb, l234info); 2937 } 2938 2939 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2940 struct sk_buff *skb, u32 rss_hash) 2941 { 2942 struct hnae3_handle *handle = ring->tqp->handle; 2943 enum pkt_hash_types rss_type; 2944 2945 if (rss_hash) 2946 rss_type = handle->kinfo.rss_type; 2947 else 2948 rss_type = PKT_HASH_TYPE_NONE; 2949 2950 skb_set_hash(skb, rss_hash, rss_type); 2951 } 2952 2953 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2954 { 2955 struct net_device *netdev = ring_to_netdev(ring); 2956 enum hns3_pkt_l2t_type l2_frame_type; 2957 u32 bd_base_info, l234info, ol_info; 2958 struct hns3_desc *desc; 2959 unsigned int len; 2960 int pre_ntc, ret; 2961 2962 /* bdinfo handled below is only valid on the last BD of the 2963 * current packet, and ring->next_to_clean indicates the first 2964 * descriptor of next packet, so need - 1 below. 2965 */ 2966 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 2967 (ring->desc_num - 1); 2968 desc = &ring->desc[pre_ntc]; 2969 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2970 l234info = le32_to_cpu(desc->rx.l234_info); 2971 ol_info = le32_to_cpu(desc->rx.ol_info); 2972 2973 /* Based on hw strategy, the tag offloaded will be stored at 2974 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2975 * in one layer tag case. 2976 */ 2977 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2978 u16 vlan_tag; 2979 2980 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2981 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2982 vlan_tag); 2983 } 2984 2985 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2986 BIT(HNS3_RXD_L2E_B))))) { 2987 u64_stats_update_begin(&ring->syncp); 2988 if (l234info & BIT(HNS3_RXD_L2E_B)) 2989 ring->stats.l2_err++; 2990 else 2991 ring->stats.err_pkt_len++; 2992 u64_stats_update_end(&ring->syncp); 2993 2994 return -EFAULT; 2995 } 2996 2997 len = skb->len; 2998 2999 /* Do update ip stack process */ 3000 skb->protocol = eth_type_trans(skb, netdev); 3001 3002 /* This is needed in order to enable forwarding support */ 3003 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3004 bd_base_info, ol_info); 3005 if (unlikely(ret)) { 3006 u64_stats_update_begin(&ring->syncp); 3007 ring->stats.rx_err_cnt++; 3008 u64_stats_update_end(&ring->syncp); 3009 return ret; 3010 } 3011 3012 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3013 HNS3_RXD_DMAC_S); 3014 3015 u64_stats_update_begin(&ring->syncp); 3016 ring->stats.rx_pkts++; 3017 ring->stats.rx_bytes += len; 3018 3019 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3020 ring->stats.rx_multicast++; 3021 3022 u64_stats_update_end(&ring->syncp); 3023 3024 ring->tqp_vector->rx_group.total_bytes += len; 3025 3026 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3027 return 0; 3028 } 3029 3030 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3031 { 3032 struct sk_buff *skb = ring->skb; 3033 struct hns3_desc_cb *desc_cb; 3034 struct hns3_desc *desc; 3035 unsigned int length; 3036 u32 bd_base_info; 3037 int ret; 3038 3039 desc = &ring->desc[ring->next_to_clean]; 3040 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3041 3042 prefetch(desc); 3043 3044 length = le16_to_cpu(desc->rx.size); 3045 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3046 3047 /* Check valid BD */ 3048 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3049 return -ENXIO; 3050 3051 if (!skb) 3052 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 3053 3054 /* Prefetch first cache line of first page 3055 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 3056 * line size is 64B so need to prefetch twice to make it 128B. But in 3057 * actual we can have greater size of caches with 128B Level 1 cache 3058 * lines. In such a case, single fetch would suffice to cache in the 3059 * relevant part of the header. 3060 */ 3061 prefetch(ring->va); 3062 #if L1_CACHE_BYTES < 128 3063 prefetch(ring->va + L1_CACHE_BYTES); 3064 #endif 3065 3066 if (!skb) { 3067 ret = hns3_alloc_skb(ring, length, ring->va); 3068 skb = ring->skb; 3069 3070 if (ret < 0) /* alloc buffer fail */ 3071 return ret; 3072 if (ret > 0) { /* need add frag */ 3073 ret = hns3_add_frag(ring, desc, false); 3074 if (ret) 3075 return ret; 3076 3077 /* As the head data may be changed when GRO enable, copy 3078 * the head data in after other data rx completed 3079 */ 3080 memcpy(skb->data, ring->va, 3081 ALIGN(ring->pull_len, sizeof(long))); 3082 } 3083 } else { 3084 ret = hns3_add_frag(ring, desc, true); 3085 if (ret) 3086 return ret; 3087 3088 /* As the head data may be changed when GRO enable, copy 3089 * the head data in after other data rx completed 3090 */ 3091 memcpy(skb->data, ring->va, 3092 ALIGN(ring->pull_len, sizeof(long))); 3093 } 3094 3095 ret = hns3_handle_bdinfo(ring, skb); 3096 if (unlikely(ret)) { 3097 dev_kfree_skb_any(skb); 3098 return ret; 3099 } 3100 3101 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3102 return 0; 3103 } 3104 3105 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3106 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3107 { 3108 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3109 int unused_count = hns3_desc_unused(ring); 3110 int recv_pkts = 0; 3111 int recv_bds = 0; 3112 int err, num; 3113 3114 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 3115 num -= unused_count; 3116 unused_count -= ring->pending_buf; 3117 3118 if (num <= 0) 3119 goto out; 3120 3121 rmb(); /* Make sure num taken effect before the other data is touched */ 3122 3123 while (recv_pkts < budget && recv_bds < num) { 3124 /* Reuse or realloc buffers */ 3125 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3126 hns3_nic_alloc_rx_buffers(ring, unused_count); 3127 unused_count = hns3_desc_unused(ring) - 3128 ring->pending_buf; 3129 } 3130 3131 /* Poll one pkt */ 3132 err = hns3_handle_rx_bd(ring); 3133 /* Do not get FE for the packet or failed to alloc skb */ 3134 if (unlikely(!ring->skb || err == -ENXIO)) { 3135 goto out; 3136 } else if (likely(!err)) { 3137 rx_fn(ring, ring->skb); 3138 recv_pkts++; 3139 } 3140 3141 recv_bds += ring->pending_buf; 3142 unused_count += ring->pending_buf; 3143 ring->skb = NULL; 3144 ring->pending_buf = 0; 3145 } 3146 3147 out: 3148 /* Make all data has been write before submit */ 3149 if (unused_count > 0) 3150 hns3_nic_alloc_rx_buffers(ring, unused_count); 3151 3152 return recv_pkts; 3153 } 3154 3155 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3156 { 3157 #define HNS3_RX_LOW_BYTE_RATE 10000 3158 #define HNS3_RX_MID_BYTE_RATE 20000 3159 #define HNS3_RX_ULTRA_PACKET_RATE 40 3160 3161 enum hns3_flow_level_range new_flow_level; 3162 struct hns3_enet_tqp_vector *tqp_vector; 3163 int packets_per_msecs, bytes_per_msecs; 3164 u32 time_passed_ms; 3165 3166 tqp_vector = ring_group->ring->tqp_vector; 3167 time_passed_ms = 3168 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3169 if (!time_passed_ms) 3170 return false; 3171 3172 do_div(ring_group->total_packets, time_passed_ms); 3173 packets_per_msecs = ring_group->total_packets; 3174 3175 do_div(ring_group->total_bytes, time_passed_ms); 3176 bytes_per_msecs = ring_group->total_bytes; 3177 3178 new_flow_level = ring_group->coal.flow_level; 3179 3180 /* Simple throttlerate management 3181 * 0-10MB/s lower (50000 ints/s) 3182 * 10-20MB/s middle (20000 ints/s) 3183 * 20-1249MB/s high (18000 ints/s) 3184 * > 40000pps ultra (8000 ints/s) 3185 */ 3186 switch (new_flow_level) { 3187 case HNS3_FLOW_LOW: 3188 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3189 new_flow_level = HNS3_FLOW_MID; 3190 break; 3191 case HNS3_FLOW_MID: 3192 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3193 new_flow_level = HNS3_FLOW_HIGH; 3194 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3195 new_flow_level = HNS3_FLOW_LOW; 3196 break; 3197 case HNS3_FLOW_HIGH: 3198 case HNS3_FLOW_ULTRA: 3199 default: 3200 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3201 new_flow_level = HNS3_FLOW_MID; 3202 break; 3203 } 3204 3205 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3206 &tqp_vector->rx_group == ring_group) 3207 new_flow_level = HNS3_FLOW_ULTRA; 3208 3209 ring_group->total_bytes = 0; 3210 ring_group->total_packets = 0; 3211 ring_group->coal.flow_level = new_flow_level; 3212 3213 return true; 3214 } 3215 3216 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3217 { 3218 struct hns3_enet_tqp_vector *tqp_vector; 3219 u16 new_int_gl; 3220 3221 if (!ring_group->ring) 3222 return false; 3223 3224 tqp_vector = ring_group->ring->tqp_vector; 3225 if (!tqp_vector->last_jiffies) 3226 return false; 3227 3228 if (ring_group->total_packets == 0) { 3229 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3230 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3231 return true; 3232 } 3233 3234 if (!hns3_get_new_flow_lvl(ring_group)) 3235 return false; 3236 3237 new_int_gl = ring_group->coal.int_gl; 3238 switch (ring_group->coal.flow_level) { 3239 case HNS3_FLOW_LOW: 3240 new_int_gl = HNS3_INT_GL_50K; 3241 break; 3242 case HNS3_FLOW_MID: 3243 new_int_gl = HNS3_INT_GL_20K; 3244 break; 3245 case HNS3_FLOW_HIGH: 3246 new_int_gl = HNS3_INT_GL_18K; 3247 break; 3248 case HNS3_FLOW_ULTRA: 3249 new_int_gl = HNS3_INT_GL_8K; 3250 break; 3251 default: 3252 break; 3253 } 3254 3255 if (new_int_gl != ring_group->coal.int_gl) { 3256 ring_group->coal.int_gl = new_int_gl; 3257 return true; 3258 } 3259 return false; 3260 } 3261 3262 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3263 { 3264 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3265 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3266 bool rx_update, tx_update; 3267 3268 /* update param every 1000ms */ 3269 if (time_before(jiffies, 3270 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3271 return; 3272 3273 if (rx_group->coal.gl_adapt_enable) { 3274 rx_update = hns3_get_new_int_gl(rx_group); 3275 if (rx_update) 3276 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3277 rx_group->coal.int_gl); 3278 } 3279 3280 if (tx_group->coal.gl_adapt_enable) { 3281 tx_update = hns3_get_new_int_gl(tx_group); 3282 if (tx_update) 3283 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3284 tx_group->coal.int_gl); 3285 } 3286 3287 tqp_vector->last_jiffies = jiffies; 3288 } 3289 3290 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3291 { 3292 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3293 struct hns3_enet_ring *ring; 3294 int rx_pkt_total = 0; 3295 3296 struct hns3_enet_tqp_vector *tqp_vector = 3297 container_of(napi, struct hns3_enet_tqp_vector, napi); 3298 bool clean_complete = true; 3299 int rx_budget = budget; 3300 3301 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3302 napi_complete(napi); 3303 return 0; 3304 } 3305 3306 /* Since the actual Tx work is minimal, we can give the Tx a larger 3307 * budget and be more aggressive about cleaning up the Tx descriptors. 3308 */ 3309 hns3_for_each_ring(ring, tqp_vector->tx_group) 3310 hns3_clean_tx_ring(ring); 3311 3312 /* make sure rx ring budget not smaller than 1 */ 3313 if (tqp_vector->num_tqps > 1) 3314 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3315 3316 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3317 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3318 hns3_rx_skb); 3319 3320 if (rx_cleaned >= rx_budget) 3321 clean_complete = false; 3322 3323 rx_pkt_total += rx_cleaned; 3324 } 3325 3326 tqp_vector->rx_group.total_packets += rx_pkt_total; 3327 3328 if (!clean_complete) 3329 return budget; 3330 3331 if (napi_complete(napi) && 3332 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3333 hns3_update_new_int_gl(tqp_vector); 3334 hns3_mask_vector_irq(tqp_vector, 1); 3335 } 3336 3337 return rx_pkt_total; 3338 } 3339 3340 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3341 struct hnae3_ring_chain_node *head) 3342 { 3343 struct pci_dev *pdev = tqp_vector->handle->pdev; 3344 struct hnae3_ring_chain_node *cur_chain = head; 3345 struct hnae3_ring_chain_node *chain; 3346 struct hns3_enet_ring *tx_ring; 3347 struct hns3_enet_ring *rx_ring; 3348 3349 tx_ring = tqp_vector->tx_group.ring; 3350 if (tx_ring) { 3351 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3352 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3353 HNAE3_RING_TYPE_TX); 3354 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3355 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3356 3357 cur_chain->next = NULL; 3358 3359 while (tx_ring->next) { 3360 tx_ring = tx_ring->next; 3361 3362 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3363 GFP_KERNEL); 3364 if (!chain) 3365 goto err_free_chain; 3366 3367 cur_chain->next = chain; 3368 chain->tqp_index = tx_ring->tqp->tqp_index; 3369 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3370 HNAE3_RING_TYPE_TX); 3371 hnae3_set_field(chain->int_gl_idx, 3372 HNAE3_RING_GL_IDX_M, 3373 HNAE3_RING_GL_IDX_S, 3374 HNAE3_RING_GL_TX); 3375 3376 cur_chain = chain; 3377 } 3378 } 3379 3380 rx_ring = tqp_vector->rx_group.ring; 3381 if (!tx_ring && rx_ring) { 3382 cur_chain->next = NULL; 3383 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3384 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3385 HNAE3_RING_TYPE_RX); 3386 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3387 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3388 3389 rx_ring = rx_ring->next; 3390 } 3391 3392 while (rx_ring) { 3393 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3394 if (!chain) 3395 goto err_free_chain; 3396 3397 cur_chain->next = chain; 3398 chain->tqp_index = rx_ring->tqp->tqp_index; 3399 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3400 HNAE3_RING_TYPE_RX); 3401 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3402 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3403 3404 cur_chain = chain; 3405 3406 rx_ring = rx_ring->next; 3407 } 3408 3409 return 0; 3410 3411 err_free_chain: 3412 cur_chain = head->next; 3413 while (cur_chain) { 3414 chain = cur_chain->next; 3415 devm_kfree(&pdev->dev, cur_chain); 3416 cur_chain = chain; 3417 } 3418 head->next = NULL; 3419 3420 return -ENOMEM; 3421 } 3422 3423 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3424 struct hnae3_ring_chain_node *head) 3425 { 3426 struct pci_dev *pdev = tqp_vector->handle->pdev; 3427 struct hnae3_ring_chain_node *chain_tmp, *chain; 3428 3429 chain = head->next; 3430 3431 while (chain) { 3432 chain_tmp = chain->next; 3433 devm_kfree(&pdev->dev, chain); 3434 chain = chain_tmp; 3435 } 3436 } 3437 3438 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3439 struct hns3_enet_ring *ring) 3440 { 3441 ring->next = group->ring; 3442 group->ring = ring; 3443 3444 group->count++; 3445 } 3446 3447 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3448 { 3449 struct pci_dev *pdev = priv->ae_handle->pdev; 3450 struct hns3_enet_tqp_vector *tqp_vector; 3451 int num_vectors = priv->vector_num; 3452 int numa_node; 3453 int vector_i; 3454 3455 numa_node = dev_to_node(&pdev->dev); 3456 3457 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3458 tqp_vector = &priv->tqp_vector[vector_i]; 3459 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3460 &tqp_vector->affinity_mask); 3461 } 3462 } 3463 3464 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3465 { 3466 struct hnae3_ring_chain_node vector_ring_chain; 3467 struct hnae3_handle *h = priv->ae_handle; 3468 struct hns3_enet_tqp_vector *tqp_vector; 3469 int ret = 0; 3470 int i; 3471 3472 hns3_nic_set_cpumask(priv); 3473 3474 for (i = 0; i < priv->vector_num; i++) { 3475 tqp_vector = &priv->tqp_vector[i]; 3476 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3477 tqp_vector->num_tqps = 0; 3478 } 3479 3480 for (i = 0; i < h->kinfo.num_tqps; i++) { 3481 u16 vector_i = i % priv->vector_num; 3482 u16 tqp_num = h->kinfo.num_tqps; 3483 3484 tqp_vector = &priv->tqp_vector[vector_i]; 3485 3486 hns3_add_ring_to_group(&tqp_vector->tx_group, 3487 &priv->ring[i]); 3488 3489 hns3_add_ring_to_group(&tqp_vector->rx_group, 3490 &priv->ring[i + tqp_num]); 3491 3492 priv->ring[i].tqp_vector = tqp_vector; 3493 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3494 tqp_vector->num_tqps++; 3495 } 3496 3497 for (i = 0; i < priv->vector_num; i++) { 3498 tqp_vector = &priv->tqp_vector[i]; 3499 3500 tqp_vector->rx_group.total_bytes = 0; 3501 tqp_vector->rx_group.total_packets = 0; 3502 tqp_vector->tx_group.total_bytes = 0; 3503 tqp_vector->tx_group.total_packets = 0; 3504 tqp_vector->handle = h; 3505 3506 ret = hns3_get_vector_ring_chain(tqp_vector, 3507 &vector_ring_chain); 3508 if (ret) 3509 goto map_ring_fail; 3510 3511 ret = h->ae_algo->ops->map_ring_to_vector(h, 3512 tqp_vector->vector_irq, &vector_ring_chain); 3513 3514 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3515 3516 if (ret) 3517 goto map_ring_fail; 3518 3519 netif_napi_add(priv->netdev, &tqp_vector->napi, 3520 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3521 } 3522 3523 return 0; 3524 3525 map_ring_fail: 3526 while (i--) 3527 netif_napi_del(&priv->tqp_vector[i].napi); 3528 3529 return ret; 3530 } 3531 3532 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3533 { 3534 #define HNS3_VECTOR_PF_MAX_NUM 64 3535 3536 struct hnae3_handle *h = priv->ae_handle; 3537 struct hns3_enet_tqp_vector *tqp_vector; 3538 struct hnae3_vector_info *vector; 3539 struct pci_dev *pdev = h->pdev; 3540 u16 tqp_num = h->kinfo.num_tqps; 3541 u16 vector_num; 3542 int ret = 0; 3543 u16 i; 3544 3545 /* RSS size, cpu online and vector_num should be the same */ 3546 /* Should consider 2p/4p later */ 3547 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3548 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3549 3550 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3551 GFP_KERNEL); 3552 if (!vector) 3553 return -ENOMEM; 3554 3555 /* save the actual available vector number */ 3556 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3557 3558 priv->vector_num = vector_num; 3559 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3560 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3561 GFP_KERNEL); 3562 if (!priv->tqp_vector) { 3563 ret = -ENOMEM; 3564 goto out; 3565 } 3566 3567 for (i = 0; i < priv->vector_num; i++) { 3568 tqp_vector = &priv->tqp_vector[i]; 3569 tqp_vector->idx = i; 3570 tqp_vector->mask_addr = vector[i].io_addr; 3571 tqp_vector->vector_irq = vector[i].vector; 3572 hns3_vector_gl_rl_init(tqp_vector, priv); 3573 } 3574 3575 out: 3576 devm_kfree(&pdev->dev, vector); 3577 return ret; 3578 } 3579 3580 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3581 { 3582 group->ring = NULL; 3583 group->count = 0; 3584 } 3585 3586 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3587 { 3588 struct hnae3_ring_chain_node vector_ring_chain; 3589 struct hnae3_handle *h = priv->ae_handle; 3590 struct hns3_enet_tqp_vector *tqp_vector; 3591 int i; 3592 3593 for (i = 0; i < priv->vector_num; i++) { 3594 tqp_vector = &priv->tqp_vector[i]; 3595 3596 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3597 continue; 3598 3599 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3600 3601 h->ae_algo->ops->unmap_ring_from_vector(h, 3602 tqp_vector->vector_irq, &vector_ring_chain); 3603 3604 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3605 3606 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3607 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3608 free_irq(tqp_vector->vector_irq, tqp_vector); 3609 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3610 } 3611 3612 hns3_clear_ring_group(&tqp_vector->rx_group); 3613 hns3_clear_ring_group(&tqp_vector->tx_group); 3614 netif_napi_del(&priv->tqp_vector[i].napi); 3615 } 3616 } 3617 3618 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3619 { 3620 struct hnae3_handle *h = priv->ae_handle; 3621 struct pci_dev *pdev = h->pdev; 3622 int i, ret; 3623 3624 for (i = 0; i < priv->vector_num; i++) { 3625 struct hns3_enet_tqp_vector *tqp_vector; 3626 3627 tqp_vector = &priv->tqp_vector[i]; 3628 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3629 if (ret) 3630 return ret; 3631 } 3632 3633 devm_kfree(&pdev->dev, priv->tqp_vector); 3634 return 0; 3635 } 3636 3637 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3638 unsigned int ring_type) 3639 { 3640 int queue_num = priv->ae_handle->kinfo.num_tqps; 3641 struct hns3_enet_ring *ring; 3642 int desc_num; 3643 3644 if (ring_type == HNAE3_RING_TYPE_TX) { 3645 ring = &priv->ring[q->tqp_index]; 3646 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3647 ring->queue_index = q->tqp_index; 3648 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3649 } else { 3650 ring = &priv->ring[q->tqp_index + queue_num]; 3651 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3652 ring->queue_index = q->tqp_index; 3653 ring->io_base = q->io_base; 3654 } 3655 3656 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3657 3658 ring->tqp = q; 3659 ring->desc = NULL; 3660 ring->desc_cb = NULL; 3661 ring->dev = priv->dev; 3662 ring->desc_dma_addr = 0; 3663 ring->buf_size = q->buf_size; 3664 ring->desc_num = desc_num; 3665 ring->next_to_use = 0; 3666 ring->next_to_clean = 0; 3667 } 3668 3669 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3670 struct hns3_nic_priv *priv) 3671 { 3672 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3673 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3674 } 3675 3676 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3677 { 3678 struct hnae3_handle *h = priv->ae_handle; 3679 struct pci_dev *pdev = h->pdev; 3680 int i; 3681 3682 priv->ring = devm_kzalloc(&pdev->dev, 3683 array3_size(h->kinfo.num_tqps, 3684 sizeof(*priv->ring), 2), 3685 GFP_KERNEL); 3686 if (!priv->ring) 3687 return -ENOMEM; 3688 3689 for (i = 0; i < h->kinfo.num_tqps; i++) 3690 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3691 3692 return 0; 3693 } 3694 3695 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3696 { 3697 if (!priv->ring) 3698 return; 3699 3700 devm_kfree(priv->dev, priv->ring); 3701 priv->ring = NULL; 3702 } 3703 3704 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3705 { 3706 int ret; 3707 3708 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3709 return -EINVAL; 3710 3711 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3712 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3713 if (!ring->desc_cb) { 3714 ret = -ENOMEM; 3715 goto out; 3716 } 3717 3718 ret = hns3_alloc_desc(ring); 3719 if (ret) 3720 goto out_with_desc_cb; 3721 3722 if (!HNAE3_IS_TX_RING(ring)) { 3723 ret = hns3_alloc_ring_buffers(ring); 3724 if (ret) 3725 goto out_with_desc; 3726 } 3727 3728 return 0; 3729 3730 out_with_desc: 3731 hns3_free_desc(ring); 3732 out_with_desc_cb: 3733 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3734 ring->desc_cb = NULL; 3735 out: 3736 return ret; 3737 } 3738 3739 void hns3_fini_ring(struct hns3_enet_ring *ring) 3740 { 3741 hns3_free_desc(ring); 3742 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3743 ring->desc_cb = NULL; 3744 ring->next_to_clean = 0; 3745 ring->next_to_use = 0; 3746 ring->pending_buf = 0; 3747 if (ring->skb) { 3748 dev_kfree_skb_any(ring->skb); 3749 ring->skb = NULL; 3750 } 3751 } 3752 3753 static int hns3_buf_size2type(u32 buf_size) 3754 { 3755 int bd_size_type; 3756 3757 switch (buf_size) { 3758 case 512: 3759 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3760 break; 3761 case 1024: 3762 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3763 break; 3764 case 2048: 3765 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3766 break; 3767 case 4096: 3768 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3769 break; 3770 default: 3771 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3772 } 3773 3774 return bd_size_type; 3775 } 3776 3777 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3778 { 3779 dma_addr_t dma = ring->desc_dma_addr; 3780 struct hnae3_queue *q = ring->tqp; 3781 3782 if (!HNAE3_IS_TX_RING(ring)) { 3783 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3784 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3785 (u32)((dma >> 31) >> 1)); 3786 3787 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3788 hns3_buf_size2type(ring->buf_size)); 3789 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3790 ring->desc_num / 8 - 1); 3791 3792 } else { 3793 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3794 (u32)dma); 3795 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3796 (u32)((dma >> 31) >> 1)); 3797 3798 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3799 ring->desc_num / 8 - 1); 3800 } 3801 } 3802 3803 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3804 { 3805 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3806 int i; 3807 3808 for (i = 0; i < HNAE3_MAX_TC; i++) { 3809 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3810 int j; 3811 3812 if (!tc_info->enable) 3813 continue; 3814 3815 for (j = 0; j < tc_info->tqp_count; j++) { 3816 struct hnae3_queue *q; 3817 3818 q = priv->ring[tc_info->tqp_offset + j].tqp; 3819 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3820 tc_info->tc); 3821 } 3822 } 3823 } 3824 3825 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3826 { 3827 struct hnae3_handle *h = priv->ae_handle; 3828 int ring_num = h->kinfo.num_tqps * 2; 3829 int i, j; 3830 int ret; 3831 3832 for (i = 0; i < ring_num; i++) { 3833 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3834 if (ret) { 3835 dev_err(priv->dev, 3836 "Alloc ring memory fail! ret=%d\n", ret); 3837 goto out_when_alloc_ring_memory; 3838 } 3839 3840 u64_stats_init(&priv->ring[i].syncp); 3841 } 3842 3843 return 0; 3844 3845 out_when_alloc_ring_memory: 3846 for (j = i - 1; j >= 0; j--) 3847 hns3_fini_ring(&priv->ring[j]); 3848 3849 return -ENOMEM; 3850 } 3851 3852 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3853 { 3854 struct hnae3_handle *h = priv->ae_handle; 3855 int i; 3856 3857 for (i = 0; i < h->kinfo.num_tqps; i++) { 3858 hns3_fini_ring(&priv->ring[i]); 3859 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3860 } 3861 return 0; 3862 } 3863 3864 /* Set mac addr if it is configured. or leave it to the AE driver */ 3865 static int hns3_init_mac_addr(struct net_device *netdev) 3866 { 3867 struct hns3_nic_priv *priv = netdev_priv(netdev); 3868 struct hnae3_handle *h = priv->ae_handle; 3869 u8 mac_addr_temp[ETH_ALEN]; 3870 int ret = 0; 3871 3872 if (h->ae_algo->ops->get_mac_addr) 3873 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3874 3875 /* Check if the MAC address is valid, if not get a random one */ 3876 if (!is_valid_ether_addr(mac_addr_temp)) { 3877 eth_hw_addr_random(netdev); 3878 dev_warn(priv->dev, "using random MAC address %pM\n", 3879 netdev->dev_addr); 3880 } else { 3881 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3882 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3883 } 3884 3885 if (h->ae_algo->ops->set_mac_addr) 3886 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3887 3888 return ret; 3889 } 3890 3891 static int hns3_init_phy(struct net_device *netdev) 3892 { 3893 struct hnae3_handle *h = hns3_get_handle(netdev); 3894 int ret = 0; 3895 3896 if (h->ae_algo->ops->mac_connect_phy) 3897 ret = h->ae_algo->ops->mac_connect_phy(h); 3898 3899 return ret; 3900 } 3901 3902 static void hns3_uninit_phy(struct net_device *netdev) 3903 { 3904 struct hnae3_handle *h = hns3_get_handle(netdev); 3905 3906 if (h->ae_algo->ops->mac_disconnect_phy) 3907 h->ae_algo->ops->mac_disconnect_phy(h); 3908 } 3909 3910 static int hns3_restore_fd_rules(struct net_device *netdev) 3911 { 3912 struct hnae3_handle *h = hns3_get_handle(netdev); 3913 int ret = 0; 3914 3915 if (h->ae_algo->ops->restore_fd_rules) 3916 ret = h->ae_algo->ops->restore_fd_rules(h); 3917 3918 return ret; 3919 } 3920 3921 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3922 { 3923 struct hnae3_handle *h = hns3_get_handle(netdev); 3924 3925 if (h->ae_algo->ops->del_all_fd_entries) 3926 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3927 } 3928 3929 static int hns3_client_start(struct hnae3_handle *handle) 3930 { 3931 if (!handle->ae_algo->ops->client_start) 3932 return 0; 3933 3934 return handle->ae_algo->ops->client_start(handle); 3935 } 3936 3937 static void hns3_client_stop(struct hnae3_handle *handle) 3938 { 3939 if (!handle->ae_algo->ops->client_stop) 3940 return; 3941 3942 handle->ae_algo->ops->client_stop(handle); 3943 } 3944 3945 static void hns3_info_show(struct hns3_nic_priv *priv) 3946 { 3947 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3948 3949 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3950 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 3951 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 3952 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 3953 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 3954 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 3955 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 3956 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 3957 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 3958 } 3959 3960 static int hns3_client_init(struct hnae3_handle *handle) 3961 { 3962 struct pci_dev *pdev = handle->pdev; 3963 u16 alloc_tqps, max_rss_size; 3964 struct hns3_nic_priv *priv; 3965 struct net_device *netdev; 3966 int ret; 3967 3968 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3969 &max_rss_size); 3970 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3971 if (!netdev) 3972 return -ENOMEM; 3973 3974 priv = netdev_priv(netdev); 3975 priv->dev = &pdev->dev; 3976 priv->netdev = netdev; 3977 priv->ae_handle = handle; 3978 priv->tx_timeout_count = 0; 3979 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3980 3981 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 3982 3983 handle->kinfo.netdev = netdev; 3984 handle->priv = (void *)priv; 3985 3986 hns3_init_mac_addr(netdev); 3987 3988 hns3_set_default_feature(netdev); 3989 3990 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3991 netdev->priv_flags |= IFF_UNICAST_FLT; 3992 netdev->netdev_ops = &hns3_nic_netdev_ops; 3993 SET_NETDEV_DEV(netdev, &pdev->dev); 3994 hns3_ethtool_set_ops(netdev); 3995 3996 /* Carrier off reporting is important to ethtool even BEFORE open */ 3997 netif_carrier_off(netdev); 3998 3999 ret = hns3_get_ring_config(priv); 4000 if (ret) { 4001 ret = -ENOMEM; 4002 goto out_get_ring_cfg; 4003 } 4004 4005 ret = hns3_nic_alloc_vector_data(priv); 4006 if (ret) { 4007 ret = -ENOMEM; 4008 goto out_alloc_vector_data; 4009 } 4010 4011 ret = hns3_nic_init_vector_data(priv); 4012 if (ret) { 4013 ret = -ENOMEM; 4014 goto out_init_vector_data; 4015 } 4016 4017 ret = hns3_init_all_ring(priv); 4018 if (ret) { 4019 ret = -ENOMEM; 4020 goto out_init_ring; 4021 } 4022 4023 ret = hns3_init_phy(netdev); 4024 if (ret) 4025 goto out_init_phy; 4026 4027 ret = register_netdev(netdev); 4028 if (ret) { 4029 dev_err(priv->dev, "probe register netdev fail!\n"); 4030 goto out_reg_netdev_fail; 4031 } 4032 4033 ret = hns3_client_start(handle); 4034 if (ret) { 4035 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4036 goto out_client_start; 4037 } 4038 4039 hns3_dcbnl_setup(handle); 4040 4041 hns3_dbg_init(handle); 4042 4043 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4044 netdev->max_mtu = HNS3_MAX_MTU; 4045 4046 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4047 4048 if (netif_msg_drv(handle)) 4049 hns3_info_show(priv); 4050 4051 return ret; 4052 4053 out_client_start: 4054 unregister_netdev(netdev); 4055 out_reg_netdev_fail: 4056 hns3_uninit_phy(netdev); 4057 out_init_phy: 4058 hns3_uninit_all_ring(priv); 4059 out_init_ring: 4060 hns3_nic_uninit_vector_data(priv); 4061 out_init_vector_data: 4062 hns3_nic_dealloc_vector_data(priv); 4063 out_alloc_vector_data: 4064 priv->ring = NULL; 4065 out_get_ring_cfg: 4066 priv->ae_handle = NULL; 4067 free_netdev(netdev); 4068 return ret; 4069 } 4070 4071 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4072 { 4073 struct net_device *netdev = handle->kinfo.netdev; 4074 struct hns3_nic_priv *priv = netdev_priv(netdev); 4075 int ret; 4076 4077 hns3_remove_hw_addr(netdev); 4078 4079 if (netdev->reg_state != NETREG_UNINITIALIZED) 4080 unregister_netdev(netdev); 4081 4082 hns3_client_stop(handle); 4083 4084 hns3_uninit_phy(netdev); 4085 4086 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4087 netdev_warn(netdev, "already uninitialized\n"); 4088 goto out_netdev_free; 4089 } 4090 4091 hns3_del_all_fd_rules(netdev, true); 4092 4093 hns3_clear_all_ring(handle, true); 4094 4095 hns3_nic_uninit_vector_data(priv); 4096 4097 ret = hns3_nic_dealloc_vector_data(priv); 4098 if (ret) 4099 netdev_err(netdev, "dealloc vector error\n"); 4100 4101 ret = hns3_uninit_all_ring(priv); 4102 if (ret) 4103 netdev_err(netdev, "uninit ring error\n"); 4104 4105 hns3_put_ring_config(priv); 4106 4107 hns3_dbg_uninit(handle); 4108 4109 out_netdev_free: 4110 free_netdev(netdev); 4111 } 4112 4113 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4114 { 4115 struct net_device *netdev = handle->kinfo.netdev; 4116 4117 if (!netdev) 4118 return; 4119 4120 if (linkup) { 4121 netif_carrier_on(netdev); 4122 netif_tx_wake_all_queues(netdev); 4123 if (netif_msg_link(handle)) 4124 netdev_info(netdev, "link up\n"); 4125 } else { 4126 netif_carrier_off(netdev); 4127 netif_tx_stop_all_queues(netdev); 4128 if (netif_msg_link(handle)) 4129 netdev_info(netdev, "link down\n"); 4130 } 4131 } 4132 4133 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4134 { 4135 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4136 struct net_device *ndev = kinfo->netdev; 4137 4138 if (tc > HNAE3_MAX_TC) 4139 return -EINVAL; 4140 4141 if (!ndev) 4142 return -ENODEV; 4143 4144 return hns3_nic_set_real_num_queue(ndev); 4145 } 4146 4147 static int hns3_recover_hw_addr(struct net_device *ndev) 4148 { 4149 struct netdev_hw_addr_list *list; 4150 struct netdev_hw_addr *ha, *tmp; 4151 int ret = 0; 4152 4153 netif_addr_lock_bh(ndev); 4154 /* go through and sync uc_addr entries to the device */ 4155 list = &ndev->uc; 4156 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4157 ret = hns3_nic_uc_sync(ndev, ha->addr); 4158 if (ret) 4159 goto out; 4160 } 4161 4162 /* go through and sync mc_addr entries to the device */ 4163 list = &ndev->mc; 4164 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4165 ret = hns3_nic_mc_sync(ndev, ha->addr); 4166 if (ret) 4167 goto out; 4168 } 4169 4170 out: 4171 netif_addr_unlock_bh(ndev); 4172 return ret; 4173 } 4174 4175 static void hns3_remove_hw_addr(struct net_device *netdev) 4176 { 4177 struct netdev_hw_addr_list *list; 4178 struct netdev_hw_addr *ha, *tmp; 4179 4180 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 4181 4182 netif_addr_lock_bh(netdev); 4183 /* go through and unsync uc_addr entries to the device */ 4184 list = &netdev->uc; 4185 list_for_each_entry_safe(ha, tmp, &list->list, list) 4186 hns3_nic_uc_unsync(netdev, ha->addr); 4187 4188 /* go through and unsync mc_addr entries to the device */ 4189 list = &netdev->mc; 4190 list_for_each_entry_safe(ha, tmp, &list->list, list) 4191 if (ha->refcount > 1) 4192 hns3_nic_mc_unsync(netdev, ha->addr); 4193 4194 netif_addr_unlock_bh(netdev); 4195 } 4196 4197 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4198 { 4199 while (ring->next_to_clean != ring->next_to_use) { 4200 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4201 hns3_free_buffer_detach(ring, ring->next_to_clean); 4202 ring_ptr_move_fw(ring, next_to_clean); 4203 } 4204 } 4205 4206 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4207 { 4208 struct hns3_desc_cb res_cbs; 4209 int ret; 4210 4211 while (ring->next_to_use != ring->next_to_clean) { 4212 /* When a buffer is not reused, it's memory has been 4213 * freed in hns3_handle_rx_bd or will be freed by 4214 * stack, so we need to replace the buffer here. 4215 */ 4216 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4217 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4218 if (ret) { 4219 u64_stats_update_begin(&ring->syncp); 4220 ring->stats.sw_err_cnt++; 4221 u64_stats_update_end(&ring->syncp); 4222 /* if alloc new buffer fail, exit directly 4223 * and reclear in up flow. 4224 */ 4225 netdev_warn(ring_to_netdev(ring), 4226 "reserve buffer map failed, ret = %d\n", 4227 ret); 4228 return ret; 4229 } 4230 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4231 } 4232 ring_ptr_move_fw(ring, next_to_use); 4233 } 4234 4235 /* Free the pending skb in rx ring */ 4236 if (ring->skb) { 4237 dev_kfree_skb_any(ring->skb); 4238 ring->skb = NULL; 4239 ring->pending_buf = 0; 4240 } 4241 4242 return 0; 4243 } 4244 4245 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4246 { 4247 while (ring->next_to_use != ring->next_to_clean) { 4248 /* When a buffer is not reused, it's memory has been 4249 * freed in hns3_handle_rx_bd or will be freed by 4250 * stack, so only need to unmap the buffer here. 4251 */ 4252 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4253 hns3_unmap_buffer(ring, 4254 &ring->desc_cb[ring->next_to_use]); 4255 ring->desc_cb[ring->next_to_use].dma = 0; 4256 } 4257 4258 ring_ptr_move_fw(ring, next_to_use); 4259 } 4260 } 4261 4262 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4263 { 4264 struct net_device *ndev = h->kinfo.netdev; 4265 struct hns3_nic_priv *priv = netdev_priv(ndev); 4266 u32 i; 4267 4268 for (i = 0; i < h->kinfo.num_tqps; i++) { 4269 struct hns3_enet_ring *ring; 4270 4271 ring = &priv->ring[i]; 4272 hns3_clear_tx_ring(ring); 4273 4274 ring = &priv->ring[i + h->kinfo.num_tqps]; 4275 /* Continue to clear other rings even if clearing some 4276 * rings failed. 4277 */ 4278 if (force) 4279 hns3_force_clear_rx_ring(ring); 4280 else 4281 hns3_clear_rx_ring(ring); 4282 } 4283 } 4284 4285 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4286 { 4287 struct net_device *ndev = h->kinfo.netdev; 4288 struct hns3_nic_priv *priv = netdev_priv(ndev); 4289 struct hns3_enet_ring *rx_ring; 4290 int i, j; 4291 int ret; 4292 4293 for (i = 0; i < h->kinfo.num_tqps; i++) { 4294 ret = h->ae_algo->ops->reset_queue(h, i); 4295 if (ret) 4296 return ret; 4297 4298 hns3_init_ring_hw(&priv->ring[i]); 4299 4300 /* We need to clear tx ring here because self test will 4301 * use the ring and will not run down before up 4302 */ 4303 hns3_clear_tx_ring(&priv->ring[i]); 4304 priv->ring[i].next_to_clean = 0; 4305 priv->ring[i].next_to_use = 0; 4306 4307 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4308 hns3_init_ring_hw(rx_ring); 4309 ret = hns3_clear_rx_ring(rx_ring); 4310 if (ret) 4311 return ret; 4312 4313 /* We can not know the hardware head and tail when this 4314 * function is called in reset flow, so we reuse all desc. 4315 */ 4316 for (j = 0; j < rx_ring->desc_num; j++) 4317 hns3_reuse_buffer(rx_ring, j); 4318 4319 rx_ring->next_to_clean = 0; 4320 rx_ring->next_to_use = 0; 4321 } 4322 4323 hns3_init_tx_ring_tc(priv); 4324 4325 return 0; 4326 } 4327 4328 static void hns3_store_coal(struct hns3_nic_priv *priv) 4329 { 4330 /* ethtool only support setting and querying one coal 4331 * configuration for now, so save the vector 0' coal 4332 * configuration here in order to restore it. 4333 */ 4334 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4335 sizeof(struct hns3_enet_coalesce)); 4336 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4337 sizeof(struct hns3_enet_coalesce)); 4338 } 4339 4340 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4341 { 4342 u16 vector_num = priv->vector_num; 4343 int i; 4344 4345 for (i = 0; i < vector_num; i++) { 4346 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4347 sizeof(struct hns3_enet_coalesce)); 4348 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4349 sizeof(struct hns3_enet_coalesce)); 4350 } 4351 } 4352 4353 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4354 { 4355 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4356 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4357 struct net_device *ndev = kinfo->netdev; 4358 struct hns3_nic_priv *priv = netdev_priv(ndev); 4359 4360 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4361 return 0; 4362 4363 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4364 * from table space. Hence, for function reset software intervention is 4365 * required to delete the entries 4366 */ 4367 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4368 hns3_remove_hw_addr(ndev); 4369 hns3_del_all_fd_rules(ndev, false); 4370 } 4371 4372 if (!netif_running(ndev)) 4373 return 0; 4374 4375 return hns3_nic_net_stop(ndev); 4376 } 4377 4378 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4379 { 4380 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4381 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4382 int ret = 0; 4383 4384 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4385 4386 if (netif_running(kinfo->netdev)) { 4387 ret = hns3_nic_net_open(kinfo->netdev); 4388 if (ret) { 4389 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4390 netdev_err(kinfo->netdev, 4391 "net up fail, ret=%d!\n", ret); 4392 return ret; 4393 } 4394 } 4395 4396 return ret; 4397 } 4398 4399 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4400 { 4401 struct net_device *netdev = handle->kinfo.netdev; 4402 struct hns3_nic_priv *priv = netdev_priv(netdev); 4403 int ret; 4404 4405 /* Carrier off reporting is important to ethtool even BEFORE open */ 4406 netif_carrier_off(netdev); 4407 4408 ret = hns3_get_ring_config(priv); 4409 if (ret) 4410 return ret; 4411 4412 ret = hns3_nic_alloc_vector_data(priv); 4413 if (ret) 4414 goto err_put_ring; 4415 4416 hns3_restore_coal(priv); 4417 4418 ret = hns3_nic_init_vector_data(priv); 4419 if (ret) 4420 goto err_dealloc_vector; 4421 4422 ret = hns3_init_all_ring(priv); 4423 if (ret) 4424 goto err_uninit_vector; 4425 4426 ret = hns3_client_start(handle); 4427 if (ret) { 4428 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4429 goto err_uninit_ring; 4430 } 4431 4432 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4433 4434 return ret; 4435 4436 err_uninit_ring: 4437 hns3_uninit_all_ring(priv); 4438 err_uninit_vector: 4439 hns3_nic_uninit_vector_data(priv); 4440 err_dealloc_vector: 4441 hns3_nic_dealloc_vector_data(priv); 4442 err_put_ring: 4443 hns3_put_ring_config(priv); 4444 4445 return ret; 4446 } 4447 4448 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4449 { 4450 struct net_device *netdev = handle->kinfo.netdev; 4451 bool vlan_filter_enable; 4452 int ret; 4453 4454 ret = hns3_init_mac_addr(netdev); 4455 if (ret) 4456 return ret; 4457 4458 ret = hns3_recover_hw_addr(netdev); 4459 if (ret) 4460 return ret; 4461 4462 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4463 if (ret) 4464 return ret; 4465 4466 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4467 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4468 4469 if (handle->ae_algo->ops->restore_vlan_table) 4470 handle->ae_algo->ops->restore_vlan_table(handle); 4471 4472 return hns3_restore_fd_rules(netdev); 4473 } 4474 4475 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4476 { 4477 struct net_device *netdev = handle->kinfo.netdev; 4478 struct hns3_nic_priv *priv = netdev_priv(netdev); 4479 int ret; 4480 4481 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4482 netdev_warn(netdev, "already uninitialized\n"); 4483 return 0; 4484 } 4485 4486 hns3_clear_all_ring(handle, true); 4487 hns3_reset_tx_queue(priv->ae_handle); 4488 4489 hns3_nic_uninit_vector_data(priv); 4490 4491 hns3_store_coal(priv); 4492 4493 ret = hns3_nic_dealloc_vector_data(priv); 4494 if (ret) 4495 netdev_err(netdev, "dealloc vector error\n"); 4496 4497 ret = hns3_uninit_all_ring(priv); 4498 if (ret) 4499 netdev_err(netdev, "uninit ring error\n"); 4500 4501 hns3_put_ring_config(priv); 4502 4503 return ret; 4504 } 4505 4506 static int hns3_reset_notify(struct hnae3_handle *handle, 4507 enum hnae3_reset_notify_type type) 4508 { 4509 int ret = 0; 4510 4511 switch (type) { 4512 case HNAE3_UP_CLIENT: 4513 ret = hns3_reset_notify_up_enet(handle); 4514 break; 4515 case HNAE3_DOWN_CLIENT: 4516 ret = hns3_reset_notify_down_enet(handle); 4517 break; 4518 case HNAE3_INIT_CLIENT: 4519 ret = hns3_reset_notify_init_enet(handle); 4520 break; 4521 case HNAE3_UNINIT_CLIENT: 4522 ret = hns3_reset_notify_uninit_enet(handle); 4523 break; 4524 case HNAE3_RESTORE_CLIENT: 4525 ret = hns3_reset_notify_restore_enet(handle); 4526 break; 4527 default: 4528 break; 4529 } 4530 4531 return ret; 4532 } 4533 4534 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4535 bool rxfh_configured) 4536 { 4537 int ret; 4538 4539 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4540 rxfh_configured); 4541 if (ret) { 4542 dev_err(&handle->pdev->dev, 4543 "Change tqp num(%u) fail.\n", new_tqp_num); 4544 return ret; 4545 } 4546 4547 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4548 if (ret) 4549 return ret; 4550 4551 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4552 if (ret) 4553 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4554 4555 return ret; 4556 } 4557 4558 int hns3_set_channels(struct net_device *netdev, 4559 struct ethtool_channels *ch) 4560 { 4561 struct hnae3_handle *h = hns3_get_handle(netdev); 4562 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4563 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4564 u32 new_tqp_num = ch->combined_count; 4565 u16 org_tqp_num; 4566 int ret; 4567 4568 if (hns3_nic_resetting(netdev)) 4569 return -EBUSY; 4570 4571 if (ch->rx_count || ch->tx_count) 4572 return -EINVAL; 4573 4574 if (new_tqp_num > hns3_get_max_available_channels(h) || 4575 new_tqp_num < 1) { 4576 dev_err(&netdev->dev, 4577 "Change tqps fail, the tqp range is from 1 to %u", 4578 hns3_get_max_available_channels(h)); 4579 return -EINVAL; 4580 } 4581 4582 if (kinfo->rss_size == new_tqp_num) 4583 return 0; 4584 4585 netif_dbg(h, drv, netdev, 4586 "set channels: tqp_num=%u, rxfh=%d\n", 4587 new_tqp_num, rxfh_configured); 4588 4589 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4590 if (ret) 4591 return ret; 4592 4593 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4594 if (ret) 4595 return ret; 4596 4597 org_tqp_num = h->kinfo.num_tqps; 4598 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4599 if (ret) { 4600 int ret1; 4601 4602 netdev_warn(netdev, 4603 "Change channels fail, revert to old value\n"); 4604 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4605 if (ret1) { 4606 netdev_err(netdev, 4607 "revert to old channel fail\n"); 4608 return ret1; 4609 } 4610 4611 return ret; 4612 } 4613 4614 return 0; 4615 } 4616 4617 static const struct hns3_hw_error_info hns3_hw_err[] = { 4618 { .type = HNAE3_PPU_POISON_ERROR, 4619 .msg = "PPU poison" }, 4620 { .type = HNAE3_CMDQ_ECC_ERROR, 4621 .msg = "IMP CMDQ error" }, 4622 { .type = HNAE3_IMP_RD_POISON_ERROR, 4623 .msg = "IMP RD poison" }, 4624 }; 4625 4626 static void hns3_process_hw_error(struct hnae3_handle *handle, 4627 enum hnae3_hw_error_type type) 4628 { 4629 int i; 4630 4631 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4632 if (hns3_hw_err[i].type == type) { 4633 dev_err(&handle->pdev->dev, "Detected %s!\n", 4634 hns3_hw_err[i].msg); 4635 break; 4636 } 4637 } 4638 } 4639 4640 static const struct hnae3_client_ops client_ops = { 4641 .init_instance = hns3_client_init, 4642 .uninit_instance = hns3_client_uninit, 4643 .link_status_change = hns3_link_status_change, 4644 .setup_tc = hns3_client_setup_tc, 4645 .reset_notify = hns3_reset_notify, 4646 .process_hw_error = hns3_process_hw_error, 4647 }; 4648 4649 /* hns3_init_module - Driver registration routine 4650 * hns3_init_module is the first routine called when the driver is 4651 * loaded. All it does is register with the PCI subsystem. 4652 */ 4653 static int __init hns3_init_module(void) 4654 { 4655 int ret; 4656 4657 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4658 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4659 4660 client.type = HNAE3_CLIENT_KNIC; 4661 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4662 hns3_driver_name); 4663 4664 client.ops = &client_ops; 4665 4666 INIT_LIST_HEAD(&client.node); 4667 4668 hns3_dbg_register_debugfs(hns3_driver_name); 4669 4670 ret = hnae3_register_client(&client); 4671 if (ret) 4672 goto err_reg_client; 4673 4674 ret = pci_register_driver(&hns3_driver); 4675 if (ret) 4676 goto err_reg_driver; 4677 4678 return ret; 4679 4680 err_reg_driver: 4681 hnae3_unregister_client(&client); 4682 err_reg_client: 4683 hns3_dbg_unregister_debugfs(); 4684 return ret; 4685 } 4686 module_init(hns3_init_module); 4687 4688 /* hns3_exit_module - Driver exit cleanup routine 4689 * hns3_exit_module is called just before the driver is removed 4690 * from memory. 4691 */ 4692 static void __exit hns3_exit_module(void) 4693 { 4694 pci_unregister_driver(&hns3_driver); 4695 hnae3_unregister_client(&client); 4696 hns3_dbg_unregister_debugfs(); 4697 } 4698 module_exit(hns3_exit_module); 4699 4700 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4701 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4702 MODULE_LICENSE("GPL"); 4703 MODULE_ALIAS("pci:hns-nic"); 4704 MODULE_VERSION(HNS3_MOD_VERSION); 4705