1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 static void hns3_clear_all_ring(struct hnae3_handle *h); 25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 26 static void hns3_remove_hw_addr(struct net_device *netdev); 27 28 static const char hns3_driver_name[] = "hns3"; 29 const char hns3_driver_version[] = VERMAGIC_STRING; 30 static const char hns3_driver_string[] = 31 "Hisilicon Ethernet Network Driver for Hip08 Family"; 32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 33 static struct hnae3_client client; 34 35 /* hns3_pci_tbl - PCI Device ID Table 36 * 37 * Last entry must be all 0s 38 * 39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 40 * Class, Class Mask, private data (not used) } 41 */ 42 static const struct pci_device_id hns3_pci_tbl[] = { 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 /* required last entry */ 59 {0, } 60 }; 61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 62 63 static irqreturn_t hns3_irq_handle(int irq, void *vector) 64 { 65 struct hns3_enet_tqp_vector *tqp_vector = vector; 66 67 napi_schedule(&tqp_vector->napi); 68 69 return IRQ_HANDLED; 70 } 71 72 /* This callback function is used to set affinity changes to the irq affinity 73 * masks when the irq_set_affinity_notifier function is used. 74 */ 75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 76 const cpumask_t *mask) 77 { 78 struct hns3_enet_tqp_vector *tqp_vectors = 79 container_of(notify, struct hns3_enet_tqp_vector, 80 affinity_notify); 81 82 tqp_vectors->affinity_mask = *mask; 83 } 84 85 static void hns3_nic_irq_affinity_release(struct kref *ref) 86 { 87 } 88 89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 90 { 91 struct hns3_enet_tqp_vector *tqp_vectors; 92 unsigned int i; 93 94 for (i = 0; i < priv->vector_num; i++) { 95 tqp_vectors = &priv->tqp_vector[i]; 96 97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 98 continue; 99 100 /* clear the affinity notifier and affinity mask */ 101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 103 104 /* release the irq resource */ 105 free_irq(tqp_vectors->vector_irq, tqp_vectors); 106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 107 } 108 } 109 110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 111 { 112 struct hns3_enet_tqp_vector *tqp_vectors; 113 int txrx_int_idx = 0; 114 int rx_int_idx = 0; 115 int tx_int_idx = 0; 116 unsigned int i; 117 int ret; 118 119 for (i = 0; i < priv->vector_num; i++) { 120 tqp_vectors = &priv->tqp_vector[i]; 121 122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 123 continue; 124 125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 127 "%s-%s-%d", priv->netdev->name, "TxRx", 128 txrx_int_idx++); 129 txrx_int_idx++; 130 } else if (tqp_vectors->rx_group.ring) { 131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 132 "%s-%s-%d", priv->netdev->name, "Rx", 133 rx_int_idx++); 134 } else if (tqp_vectors->tx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Tx", 137 tx_int_idx++); 138 } else { 139 /* Skip this unused q_vector */ 140 continue; 141 } 142 143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 144 145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 146 tqp_vectors->name, 147 tqp_vectors); 148 if (ret) { 149 netdev_err(priv->netdev, "request irq(%d) fail\n", 150 tqp_vectors->vector_irq); 151 return ret; 152 } 153 154 tqp_vectors->affinity_notify.notify = 155 hns3_nic_irq_affinity_notify; 156 tqp_vectors->affinity_notify.release = 157 hns3_nic_irq_affinity_release; 158 irq_set_affinity_notifier(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_notify); 160 irq_set_affinity_hint(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_mask); 162 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 164 } 165 166 return 0; 167 } 168 169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 170 u32 mask_en) 171 { 172 writel(mask_en, tqp_vector->mask_addr); 173 } 174 175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 176 { 177 napi_enable(&tqp_vector->napi); 178 179 /* enable vector */ 180 hns3_mask_vector_irq(tqp_vector, 1); 181 } 182 183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 /* disable vector */ 186 hns3_mask_vector_irq(tqp_vector, 0); 187 188 disable_irq(tqp_vector->vector_irq); 189 napi_disable(&tqp_vector->napi); 190 } 191 192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 rl_value) 194 { 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 196 197 /* this defines the configuration for RL (Interrupt Rate Limiter). 198 * Rl defines rate of interrupts i.e. number of interrupts-per-second 199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 200 */ 201 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 203 !tqp_vector->rx_group.coal.gl_adapt_enable) 204 /* According to the hardware, the range of rl_reg is 205 * 0-59 and the unit is 4. 206 */ 207 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 208 209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 210 } 211 212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 213 u32 gl_value) 214 { 215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 216 217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 218 } 219 220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 221 u32 gl_value) 222 { 223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 224 225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 226 } 227 228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 229 struct hns3_nic_priv *priv) 230 { 231 /* initialize the configuration for interrupt coalescing. 232 * 1. GL (Interrupt Gap Limiter) 233 * 2. RL (Interrupt Rate Limiter) 234 */ 235 236 /* Default: enable interrupt coalescing self-adaptive and GL */ 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 238 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 239 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 242 243 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 244 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 245 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 246 } 247 248 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 249 struct hns3_nic_priv *priv) 250 { 251 struct hnae3_handle *h = priv->ae_handle; 252 253 hns3_set_vector_coalesce_tx_gl(tqp_vector, 254 tqp_vector->tx_group.coal.int_gl); 255 hns3_set_vector_coalesce_rx_gl(tqp_vector, 256 tqp_vector->rx_group.coal.int_gl); 257 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 258 } 259 260 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 261 { 262 struct hnae3_handle *h = hns3_get_handle(netdev); 263 struct hnae3_knic_private_info *kinfo = &h->kinfo; 264 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 265 int i, ret; 266 267 if (kinfo->num_tc <= 1) { 268 netdev_reset_tc(netdev); 269 } else { 270 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 271 if (ret) { 272 netdev_err(netdev, 273 "netdev_set_num_tc fail, ret=%d!\n", ret); 274 return ret; 275 } 276 277 for (i = 0; i < HNAE3_MAX_TC; i++) { 278 if (!kinfo->tc_info[i].enable) 279 continue; 280 281 netdev_set_tc_queue(netdev, 282 kinfo->tc_info[i].tc, 283 kinfo->tc_info[i].tqp_count, 284 kinfo->tc_info[i].tqp_offset); 285 } 286 } 287 288 ret = netif_set_real_num_tx_queues(netdev, queue_size); 289 if (ret) { 290 netdev_err(netdev, 291 "netif_set_real_num_tx_queues fail, ret=%d!\n", 292 ret); 293 return ret; 294 } 295 296 ret = netif_set_real_num_rx_queues(netdev, queue_size); 297 if (ret) { 298 netdev_err(netdev, 299 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 300 return ret; 301 } 302 303 return 0; 304 } 305 306 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 307 { 308 u16 alloc_tqps, max_rss_size, rss_size; 309 310 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 311 rss_size = alloc_tqps / h->kinfo.num_tc; 312 313 return min_t(u16, rss_size, max_rss_size); 314 } 315 316 static void hns3_tqp_enable(struct hnae3_queue *tqp) 317 { 318 u32 rcb_reg; 319 320 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 321 rcb_reg |= BIT(HNS3_RING_EN_B); 322 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 323 } 324 325 static void hns3_tqp_disable(struct hnae3_queue *tqp) 326 { 327 u32 rcb_reg; 328 329 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 330 rcb_reg &= ~BIT(HNS3_RING_EN_B); 331 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 332 } 333 334 static int hns3_nic_net_up(struct net_device *netdev) 335 { 336 struct hns3_nic_priv *priv = netdev_priv(netdev); 337 struct hnae3_handle *h = priv->ae_handle; 338 int i, j; 339 int ret; 340 341 ret = hns3_nic_reset_all_ring(h); 342 if (ret) 343 return ret; 344 345 /* get irq resource for all vectors */ 346 ret = hns3_nic_init_irq(priv); 347 if (ret) { 348 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 349 return ret; 350 } 351 352 /* enable the vectors */ 353 for (i = 0; i < priv->vector_num; i++) 354 hns3_vector_enable(&priv->tqp_vector[i]); 355 356 /* enable rcb */ 357 for (j = 0; j < h->kinfo.num_tqps; j++) 358 hns3_tqp_enable(h->kinfo.tqp[j]); 359 360 /* start the ae_dev */ 361 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 362 if (ret) 363 goto out_start_err; 364 365 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 366 367 return 0; 368 369 out_start_err: 370 while (j--) 371 hns3_tqp_disable(h->kinfo.tqp[j]); 372 373 for (j = i - 1; j >= 0; j--) 374 hns3_vector_disable(&priv->tqp_vector[j]); 375 376 hns3_nic_uninit_irq(priv); 377 378 return ret; 379 } 380 381 static int hns3_nic_net_open(struct net_device *netdev) 382 { 383 struct hnae3_handle *h = hns3_get_handle(netdev); 384 struct hnae3_knic_private_info *kinfo; 385 int i, ret; 386 387 if (hns3_nic_resetting(netdev)) 388 return -EBUSY; 389 390 netif_carrier_off(netdev); 391 392 ret = hns3_nic_set_real_num_queue(netdev); 393 if (ret) 394 return ret; 395 396 ret = hns3_nic_net_up(netdev); 397 if (ret) { 398 netdev_err(netdev, 399 "hns net up fail, ret=%d!\n", ret); 400 return ret; 401 } 402 403 kinfo = &h->kinfo; 404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 405 netdev_set_prio_tc_map(netdev, i, 406 kinfo->prio_tc[i]); 407 } 408 409 return 0; 410 } 411 412 static void hns3_nic_net_down(struct net_device *netdev) 413 { 414 struct hns3_nic_priv *priv = netdev_priv(netdev); 415 struct hnae3_handle *h = hns3_get_handle(netdev); 416 const struct hnae3_ae_ops *ops; 417 int i; 418 419 /* disable vectors */ 420 for (i = 0; i < priv->vector_num; i++) 421 hns3_vector_disable(&priv->tqp_vector[i]); 422 423 /* disable rcb */ 424 for (i = 0; i < h->kinfo.num_tqps; i++) 425 hns3_tqp_disable(h->kinfo.tqp[i]); 426 427 /* stop ae_dev */ 428 ops = priv->ae_handle->ae_algo->ops; 429 if (ops->stop) 430 ops->stop(priv->ae_handle); 431 432 /* free irq resources */ 433 hns3_nic_uninit_irq(priv); 434 435 hns3_clear_all_ring(priv->ae_handle); 436 } 437 438 static int hns3_nic_net_stop(struct net_device *netdev) 439 { 440 struct hns3_nic_priv *priv = netdev_priv(netdev); 441 442 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 443 return 0; 444 445 netif_tx_stop_all_queues(netdev); 446 netif_carrier_off(netdev); 447 448 hns3_nic_net_down(netdev); 449 450 return 0; 451 } 452 453 static int hns3_nic_uc_sync(struct net_device *netdev, 454 const unsigned char *addr) 455 { 456 struct hnae3_handle *h = hns3_get_handle(netdev); 457 458 if (h->ae_algo->ops->add_uc_addr) 459 return h->ae_algo->ops->add_uc_addr(h, addr); 460 461 return 0; 462 } 463 464 static int hns3_nic_uc_unsync(struct net_device *netdev, 465 const unsigned char *addr) 466 { 467 struct hnae3_handle *h = hns3_get_handle(netdev); 468 469 if (h->ae_algo->ops->rm_uc_addr) 470 return h->ae_algo->ops->rm_uc_addr(h, addr); 471 472 return 0; 473 } 474 475 static int hns3_nic_mc_sync(struct net_device *netdev, 476 const unsigned char *addr) 477 { 478 struct hnae3_handle *h = hns3_get_handle(netdev); 479 480 if (h->ae_algo->ops->add_mc_addr) 481 return h->ae_algo->ops->add_mc_addr(h, addr); 482 483 return 0; 484 } 485 486 static int hns3_nic_mc_unsync(struct net_device *netdev, 487 const unsigned char *addr) 488 { 489 struct hnae3_handle *h = hns3_get_handle(netdev); 490 491 if (h->ae_algo->ops->rm_mc_addr) 492 return h->ae_algo->ops->rm_mc_addr(h, addr); 493 494 return 0; 495 } 496 497 static u8 hns3_get_netdev_flags(struct net_device *netdev) 498 { 499 u8 flags = 0; 500 501 if (netdev->flags & IFF_PROMISC) { 502 flags = HNAE3_USER_UPE | HNAE3_USER_MPE; 503 } else { 504 flags |= HNAE3_VLAN_FLTR; 505 if (netdev->flags & IFF_ALLMULTI) 506 flags |= HNAE3_USER_MPE; 507 } 508 509 return flags; 510 } 511 512 static void hns3_nic_set_rx_mode(struct net_device *netdev) 513 { 514 struct hnae3_handle *h = hns3_get_handle(netdev); 515 u8 new_flags; 516 int ret; 517 518 new_flags = hns3_get_netdev_flags(netdev); 519 520 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 521 if (ret) { 522 netdev_err(netdev, "sync uc address fail\n"); 523 if (ret == -ENOSPC) 524 new_flags |= HNAE3_OVERFLOW_UPE; 525 } 526 527 if (netdev->flags & IFF_MULTICAST) { 528 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 529 hns3_nic_mc_unsync); 530 if (ret) { 531 netdev_err(netdev, "sync mc address fail\n"); 532 if (ret == -ENOSPC) 533 new_flags |= HNAE3_OVERFLOW_MPE; 534 } 535 } 536 537 hns3_update_promisc_mode(netdev, new_flags); 538 /* User mode Promisc mode enable and vlan filtering is disabled to 539 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 540 * vlan fitering is enabled 541 */ 542 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 543 h->netdev_flags = new_flags; 544 } 545 546 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 547 { 548 struct hns3_nic_priv *priv = netdev_priv(netdev); 549 struct hnae3_handle *h = priv->ae_handle; 550 551 if (h->ae_algo->ops->set_promisc_mode) { 552 return h->ae_algo->ops->set_promisc_mode(h, 553 promisc_flags & HNAE3_UPE, 554 promisc_flags & HNAE3_MPE); 555 } 556 557 return 0; 558 } 559 560 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 561 { 562 struct hns3_nic_priv *priv = netdev_priv(netdev); 563 struct hnae3_handle *h = priv->ae_handle; 564 bool last_state; 565 566 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 567 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 568 if (enable != last_state) { 569 netdev_info(netdev, 570 "%s vlan filter\n", 571 enable ? "enable" : "disable"); 572 h->ae_algo->ops->enable_vlan_filter(h, enable); 573 } 574 } 575 } 576 577 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 578 u16 *mss, u32 *type_cs_vlan_tso) 579 { 580 u32 l4_offset, hdr_len; 581 union l3_hdr_info l3; 582 union l4_hdr_info l4; 583 u32 l4_paylen; 584 int ret; 585 586 if (!skb_is_gso(skb)) 587 return 0; 588 589 ret = skb_cow_head(skb, 0); 590 if (ret) 591 return ret; 592 593 l3.hdr = skb_network_header(skb); 594 l4.hdr = skb_transport_header(skb); 595 596 /* Software should clear the IPv4's checksum field when tso is 597 * needed. 598 */ 599 if (l3.v4->version == 4) 600 l3.v4->check = 0; 601 602 /* tunnel packet.*/ 603 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 604 SKB_GSO_GRE_CSUM | 605 SKB_GSO_UDP_TUNNEL | 606 SKB_GSO_UDP_TUNNEL_CSUM)) { 607 if ((!(skb_shinfo(skb)->gso_type & 608 SKB_GSO_PARTIAL)) && 609 (skb_shinfo(skb)->gso_type & 610 SKB_GSO_UDP_TUNNEL_CSUM)) { 611 /* Software should clear the udp's checksum 612 * field when tso is needed. 613 */ 614 l4.udp->check = 0; 615 } 616 /* reset l3&l4 pointers from outer to inner headers */ 617 l3.hdr = skb_inner_network_header(skb); 618 l4.hdr = skb_inner_transport_header(skb); 619 620 /* Software should clear the IPv4's checksum field when 621 * tso is needed. 622 */ 623 if (l3.v4->version == 4) 624 l3.v4->check = 0; 625 } 626 627 /* normal or tunnel packet*/ 628 l4_offset = l4.hdr - skb->data; 629 hdr_len = (l4.tcp->doff * 4) + l4_offset; 630 631 /* remove payload length from inner pseudo checksum when tso*/ 632 l4_paylen = skb->len - l4_offset; 633 csum_replace_by_diff(&l4.tcp->check, 634 (__force __wsum)htonl(l4_paylen)); 635 636 /* find the txbd field values */ 637 *paylen = skb->len - hdr_len; 638 hnae3_set_bit(*type_cs_vlan_tso, 639 HNS3_TXD_TSO_B, 1); 640 641 /* get MSS for TSO */ 642 *mss = skb_shinfo(skb)->gso_size; 643 644 return 0; 645 } 646 647 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 648 u8 *il4_proto) 649 { 650 union { 651 struct iphdr *v4; 652 struct ipv6hdr *v6; 653 unsigned char *hdr; 654 } l3; 655 unsigned char *l4_hdr; 656 unsigned char *exthdr; 657 u8 l4_proto_tmp; 658 __be16 frag_off; 659 660 /* find outer header point */ 661 l3.hdr = skb_network_header(skb); 662 l4_hdr = skb_transport_header(skb); 663 664 if (skb->protocol == htons(ETH_P_IPV6)) { 665 exthdr = l3.hdr + sizeof(*l3.v6); 666 l4_proto_tmp = l3.v6->nexthdr; 667 if (l4_hdr != exthdr) 668 ipv6_skip_exthdr(skb, exthdr - skb->data, 669 &l4_proto_tmp, &frag_off); 670 } else if (skb->protocol == htons(ETH_P_IP)) { 671 l4_proto_tmp = l3.v4->protocol; 672 } else { 673 return -EINVAL; 674 } 675 676 *ol4_proto = l4_proto_tmp; 677 678 /* tunnel packet */ 679 if (!skb->encapsulation) { 680 *il4_proto = 0; 681 return 0; 682 } 683 684 /* find inner header point */ 685 l3.hdr = skb_inner_network_header(skb); 686 l4_hdr = skb_inner_transport_header(skb); 687 688 if (l3.v6->version == 6) { 689 exthdr = l3.hdr + sizeof(*l3.v6); 690 l4_proto_tmp = l3.v6->nexthdr; 691 if (l4_hdr != exthdr) 692 ipv6_skip_exthdr(skb, exthdr - skb->data, 693 &l4_proto_tmp, &frag_off); 694 } else if (l3.v4->version == 4) { 695 l4_proto_tmp = l3.v4->protocol; 696 } 697 698 *il4_proto = l4_proto_tmp; 699 700 return 0; 701 } 702 703 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 704 u8 il4_proto, u32 *type_cs_vlan_tso, 705 u32 *ol_type_vlan_len_msec) 706 { 707 union { 708 struct iphdr *v4; 709 struct ipv6hdr *v6; 710 unsigned char *hdr; 711 } l3; 712 union { 713 struct tcphdr *tcp; 714 struct udphdr *udp; 715 struct gre_base_hdr *gre; 716 unsigned char *hdr; 717 } l4; 718 unsigned char *l2_hdr; 719 u8 l4_proto = ol4_proto; 720 u32 ol2_len; 721 u32 ol3_len; 722 u32 ol4_len; 723 u32 l2_len; 724 u32 l3_len; 725 726 l3.hdr = skb_network_header(skb); 727 l4.hdr = skb_transport_header(skb); 728 729 /* compute L2 header size for normal packet, defined in 2 Bytes */ 730 l2_len = l3.hdr - skb->data; 731 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 732 HNS3_TXD_L2LEN_S, l2_len >> 1); 733 734 /* tunnel packet*/ 735 if (skb->encapsulation) { 736 /* compute OL2 header size, defined in 2 Bytes */ 737 ol2_len = l2_len; 738 hnae3_set_field(*ol_type_vlan_len_msec, 739 HNS3_TXD_L2LEN_M, 740 HNS3_TXD_L2LEN_S, ol2_len >> 1); 741 742 /* compute OL3 header size, defined in 4 Bytes */ 743 ol3_len = l4.hdr - l3.hdr; 744 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 745 HNS3_TXD_L3LEN_S, ol3_len >> 2); 746 747 /* MAC in UDP, MAC in GRE (0x6558)*/ 748 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 749 /* switch MAC header ptr from outer to inner header.*/ 750 l2_hdr = skb_inner_mac_header(skb); 751 752 /* compute OL4 header size, defined in 4 Bytes. */ 753 ol4_len = l2_hdr - l4.hdr; 754 hnae3_set_field(*ol_type_vlan_len_msec, 755 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 756 ol4_len >> 2); 757 758 /* switch IP header ptr from outer to inner header */ 759 l3.hdr = skb_inner_network_header(skb); 760 761 /* compute inner l2 header size, defined in 2 Bytes. */ 762 l2_len = l3.hdr - l2_hdr; 763 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 764 HNS3_TXD_L2LEN_S, l2_len >> 1); 765 } else { 766 /* skb packet types not supported by hardware, 767 * txbd len fild doesn't be filled. 768 */ 769 return; 770 } 771 772 /* switch L4 header pointer from outer to inner */ 773 l4.hdr = skb_inner_transport_header(skb); 774 775 l4_proto = il4_proto; 776 } 777 778 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 779 l3_len = l4.hdr - l3.hdr; 780 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 781 HNS3_TXD_L3LEN_S, l3_len >> 2); 782 783 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 784 switch (l4_proto) { 785 case IPPROTO_TCP: 786 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 787 HNS3_TXD_L4LEN_S, l4.tcp->doff); 788 break; 789 case IPPROTO_SCTP: 790 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 791 HNS3_TXD_L4LEN_S, 792 (sizeof(struct sctphdr) >> 2)); 793 break; 794 case IPPROTO_UDP: 795 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 796 HNS3_TXD_L4LEN_S, 797 (sizeof(struct udphdr) >> 2)); 798 break; 799 default: 800 /* skb packet types not supported by hardware, 801 * txbd len fild doesn't be filled. 802 */ 803 return; 804 } 805 } 806 807 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 808 * and it is udp packet, which has a dest port as the IANA assigned. 809 * the hardware is expected to do the checksum offload, but the 810 * hardware will not do the checksum offload when udp dest port is 811 * 4789. 812 */ 813 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 814 { 815 #define IANA_VXLAN_PORT 4789 816 union { 817 struct tcphdr *tcp; 818 struct udphdr *udp; 819 struct gre_base_hdr *gre; 820 unsigned char *hdr; 821 } l4; 822 823 l4.hdr = skb_transport_header(skb); 824 825 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 826 return false; 827 828 skb_checksum_help(skb); 829 830 return true; 831 } 832 833 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 834 u8 il4_proto, u32 *type_cs_vlan_tso, 835 u32 *ol_type_vlan_len_msec) 836 { 837 union { 838 struct iphdr *v4; 839 struct ipv6hdr *v6; 840 unsigned char *hdr; 841 } l3; 842 u32 l4_proto = ol4_proto; 843 844 l3.hdr = skb_network_header(skb); 845 846 /* define OL3 type and tunnel type(OL4).*/ 847 if (skb->encapsulation) { 848 /* define outer network header type.*/ 849 if (skb->protocol == htons(ETH_P_IP)) { 850 if (skb_is_gso(skb)) 851 hnae3_set_field(*ol_type_vlan_len_msec, 852 HNS3_TXD_OL3T_M, 853 HNS3_TXD_OL3T_S, 854 HNS3_OL3T_IPV4_CSUM); 855 else 856 hnae3_set_field(*ol_type_vlan_len_msec, 857 HNS3_TXD_OL3T_M, 858 HNS3_TXD_OL3T_S, 859 HNS3_OL3T_IPV4_NO_CSUM); 860 861 } else if (skb->protocol == htons(ETH_P_IPV6)) { 862 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 863 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 864 } 865 866 /* define tunnel type(OL4).*/ 867 switch (l4_proto) { 868 case IPPROTO_UDP: 869 hnae3_set_field(*ol_type_vlan_len_msec, 870 HNS3_TXD_TUNTYPE_M, 871 HNS3_TXD_TUNTYPE_S, 872 HNS3_TUN_MAC_IN_UDP); 873 break; 874 case IPPROTO_GRE: 875 hnae3_set_field(*ol_type_vlan_len_msec, 876 HNS3_TXD_TUNTYPE_M, 877 HNS3_TXD_TUNTYPE_S, 878 HNS3_TUN_NVGRE); 879 break; 880 default: 881 /* drop the skb tunnel packet if hardware don't support, 882 * because hardware can't calculate csum when TSO. 883 */ 884 if (skb_is_gso(skb)) 885 return -EDOM; 886 887 /* the stack computes the IP header already, 888 * driver calculate l4 checksum when not TSO. 889 */ 890 skb_checksum_help(skb); 891 return 0; 892 } 893 894 l3.hdr = skb_inner_network_header(skb); 895 l4_proto = il4_proto; 896 } 897 898 if (l3.v4->version == 4) { 899 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 900 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 901 902 /* the stack computes the IP header already, the only time we 903 * need the hardware to recompute it is in the case of TSO. 904 */ 905 if (skb_is_gso(skb)) 906 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 907 } else if (l3.v6->version == 6) { 908 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 909 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 910 } 911 912 switch (l4_proto) { 913 case IPPROTO_TCP: 914 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 915 hnae3_set_field(*type_cs_vlan_tso, 916 HNS3_TXD_L4T_M, 917 HNS3_TXD_L4T_S, 918 HNS3_L4T_TCP); 919 break; 920 case IPPROTO_UDP: 921 if (hns3_tunnel_csum_bug(skb)) 922 break; 923 924 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 925 hnae3_set_field(*type_cs_vlan_tso, 926 HNS3_TXD_L4T_M, 927 HNS3_TXD_L4T_S, 928 HNS3_L4T_UDP); 929 break; 930 case IPPROTO_SCTP: 931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 932 hnae3_set_field(*type_cs_vlan_tso, 933 HNS3_TXD_L4T_M, 934 HNS3_TXD_L4T_S, 935 HNS3_L4T_SCTP); 936 break; 937 default: 938 /* drop the skb tunnel packet if hardware don't support, 939 * because hardware can't calculate csum when TSO. 940 */ 941 if (skb_is_gso(skb)) 942 return -EDOM; 943 944 /* the stack computes the IP header already, 945 * driver calculate l4 checksum when not TSO. 946 */ 947 skb_checksum_help(skb); 948 return 0; 949 } 950 951 return 0; 952 } 953 954 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 955 { 956 /* Config bd buffer end */ 957 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 958 HNS3_TXD_BDTYPE_S, 0); 959 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 960 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 961 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 962 } 963 964 static int hns3_fill_desc_vtags(struct sk_buff *skb, 965 struct hns3_enet_ring *tx_ring, 966 u32 *inner_vlan_flag, 967 u32 *out_vlan_flag, 968 u16 *inner_vtag, 969 u16 *out_vtag) 970 { 971 #define HNS3_TX_VLAN_PRIO_SHIFT 13 972 973 if (skb->protocol == htons(ETH_P_8021Q) && 974 !(tx_ring->tqp->handle->kinfo.netdev->features & 975 NETIF_F_HW_VLAN_CTAG_TX)) { 976 /* When HW VLAN acceleration is turned off, and the stack 977 * sets the protocol to 802.1q, the driver just need to 978 * set the protocol to the encapsulated ethertype. 979 */ 980 skb->protocol = vlan_get_protocol(skb); 981 return 0; 982 } 983 984 if (skb_vlan_tag_present(skb)) { 985 u16 vlan_tag; 986 987 vlan_tag = skb_vlan_tag_get(skb); 988 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 989 990 /* Based on hw strategy, use out_vtag in two layer tag case, 991 * and use inner_vtag in one tag case. 992 */ 993 if (skb->protocol == htons(ETH_P_8021Q)) { 994 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 995 *out_vtag = vlan_tag; 996 } else { 997 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 998 *inner_vtag = vlan_tag; 999 } 1000 } else if (skb->protocol == htons(ETH_P_8021Q)) { 1001 struct vlan_ethhdr *vhdr; 1002 int rc; 1003 1004 rc = skb_cow_head(skb, 0); 1005 if (rc < 0) 1006 return rc; 1007 vhdr = (struct vlan_ethhdr *)skb->data; 1008 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1009 << HNS3_TX_VLAN_PRIO_SHIFT); 1010 } 1011 1012 skb->protocol = vlan_get_protocol(skb); 1013 return 0; 1014 } 1015 1016 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1017 int size, int frag_end, enum hns_desc_type type) 1018 { 1019 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1020 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1021 struct device *dev = ring_to_dev(ring); 1022 u32 ol_type_vlan_len_msec = 0; 1023 u16 bdtp_fe_sc_vld_ra_ri = 0; 1024 struct skb_frag_struct *frag; 1025 unsigned int frag_buf_num; 1026 u32 type_cs_vlan_tso = 0; 1027 struct sk_buff *skb; 1028 u16 inner_vtag = 0; 1029 u16 out_vtag = 0; 1030 unsigned int k; 1031 int sizeoflast; 1032 u32 paylen = 0; 1033 dma_addr_t dma; 1034 u16 mss = 0; 1035 u8 ol4_proto; 1036 u8 il4_proto; 1037 int ret; 1038 1039 if (type == DESC_TYPE_SKB) { 1040 skb = (struct sk_buff *)priv; 1041 paylen = skb->len; 1042 1043 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1044 &ol_type_vlan_len_msec, 1045 &inner_vtag, &out_vtag); 1046 if (unlikely(ret)) 1047 return ret; 1048 1049 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1050 skb_reset_mac_len(skb); 1051 1052 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1053 if (ret) 1054 return ret; 1055 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1056 &type_cs_vlan_tso, 1057 &ol_type_vlan_len_msec); 1058 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1059 &type_cs_vlan_tso, 1060 &ol_type_vlan_len_msec); 1061 if (ret) 1062 return ret; 1063 1064 ret = hns3_set_tso(skb, &paylen, &mss, 1065 &type_cs_vlan_tso); 1066 if (ret) 1067 return ret; 1068 } 1069 1070 /* Set txbd */ 1071 desc->tx.ol_type_vlan_len_msec = 1072 cpu_to_le32(ol_type_vlan_len_msec); 1073 desc->tx.type_cs_vlan_tso_len = 1074 cpu_to_le32(type_cs_vlan_tso); 1075 desc->tx.paylen = cpu_to_le32(paylen); 1076 desc->tx.mss = cpu_to_le16(mss); 1077 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1078 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1079 1080 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1081 } else { 1082 frag = (struct skb_frag_struct *)priv; 1083 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1084 } 1085 1086 if (dma_mapping_error(ring->dev, dma)) { 1087 ring->stats.sw_err_cnt++; 1088 return -ENOMEM; 1089 } 1090 1091 desc_cb->length = size; 1092 1093 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1094 sizeoflast = size % HNS3_MAX_BD_SIZE; 1095 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1096 1097 /* When frag size is bigger than hardware limit, split this frag */ 1098 for (k = 0; k < frag_buf_num; k++) { 1099 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1100 desc_cb->priv = priv; 1101 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1102 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1103 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1104 1105 /* now, fill the descriptor */ 1106 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1107 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1108 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1109 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1110 frag_end && (k == frag_buf_num - 1) ? 1111 1 : 0); 1112 desc->tx.bdtp_fe_sc_vld_ra_ri = 1113 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1114 1115 /* move ring pointer to next.*/ 1116 ring_ptr_move_fw(ring, next_to_use); 1117 1118 desc_cb = &ring->desc_cb[ring->next_to_use]; 1119 desc = &ring->desc[ring->next_to_use]; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1126 struct hns3_enet_ring *ring) 1127 { 1128 struct sk_buff *skb = *out_skb; 1129 struct skb_frag_struct *frag; 1130 int bdnum_for_frag; 1131 int frag_num; 1132 int buf_num; 1133 int size; 1134 int i; 1135 1136 size = skb_headlen(skb); 1137 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1138 1139 frag_num = skb_shinfo(skb)->nr_frags; 1140 for (i = 0; i < frag_num; i++) { 1141 frag = &skb_shinfo(skb)->frags[i]; 1142 size = skb_frag_size(frag); 1143 bdnum_for_frag = 1144 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1145 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1146 return -ENOMEM; 1147 1148 buf_num += bdnum_for_frag; 1149 } 1150 1151 if (buf_num > ring_space(ring)) 1152 return -EBUSY; 1153 1154 *bnum = buf_num; 1155 return 0; 1156 } 1157 1158 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1159 struct hns3_enet_ring *ring) 1160 { 1161 struct sk_buff *skb = *out_skb; 1162 int buf_num; 1163 1164 /* No. of segments (plus a header) */ 1165 buf_num = skb_shinfo(skb)->nr_frags + 1; 1166 1167 if (unlikely(ring_space(ring) < buf_num)) 1168 return -EBUSY; 1169 1170 *bnum = buf_num; 1171 1172 return 0; 1173 } 1174 1175 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1176 { 1177 struct device *dev = ring_to_dev(ring); 1178 unsigned int i; 1179 1180 for (i = 0; i < ring->desc_num; i++) { 1181 /* check if this is where we started */ 1182 if (ring->next_to_use == next_to_use_orig) 1183 break; 1184 1185 /* unmap the descriptor dma address */ 1186 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1187 dma_unmap_single(dev, 1188 ring->desc_cb[ring->next_to_use].dma, 1189 ring->desc_cb[ring->next_to_use].length, 1190 DMA_TO_DEVICE); 1191 else if (ring->desc_cb[ring->next_to_use].length) 1192 dma_unmap_page(dev, 1193 ring->desc_cb[ring->next_to_use].dma, 1194 ring->desc_cb[ring->next_to_use].length, 1195 DMA_TO_DEVICE); 1196 1197 ring->desc_cb[ring->next_to_use].length = 0; 1198 1199 /* rollback one */ 1200 ring_ptr_move_bw(ring, next_to_use); 1201 } 1202 } 1203 1204 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1205 { 1206 struct hns3_nic_priv *priv = netdev_priv(netdev); 1207 struct hns3_nic_ring_data *ring_data = 1208 &tx_ring_data(priv, skb->queue_mapping); 1209 struct hns3_enet_ring *ring = ring_data->ring; 1210 struct netdev_queue *dev_queue; 1211 struct skb_frag_struct *frag; 1212 int next_to_use_head; 1213 int next_to_use_frag; 1214 int buf_num; 1215 int seg_num; 1216 int size; 1217 int ret; 1218 int i; 1219 1220 /* Prefetch the data used later */ 1221 prefetch(skb->data); 1222 1223 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1224 case -EBUSY: 1225 u64_stats_update_begin(&ring->syncp); 1226 ring->stats.tx_busy++; 1227 u64_stats_update_end(&ring->syncp); 1228 1229 goto out_net_tx_busy; 1230 case -ENOMEM: 1231 u64_stats_update_begin(&ring->syncp); 1232 ring->stats.sw_err_cnt++; 1233 u64_stats_update_end(&ring->syncp); 1234 netdev_err(netdev, "no memory to xmit!\n"); 1235 1236 goto out_err_tx_ok; 1237 default: 1238 break; 1239 } 1240 1241 /* No. of segments (plus a header) */ 1242 seg_num = skb_shinfo(skb)->nr_frags + 1; 1243 /* Fill the first part */ 1244 size = skb_headlen(skb); 1245 1246 next_to_use_head = ring->next_to_use; 1247 1248 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1249 DESC_TYPE_SKB); 1250 if (ret) 1251 goto head_fill_err; 1252 1253 next_to_use_frag = ring->next_to_use; 1254 /* Fill the fragments */ 1255 for (i = 1; i < seg_num; i++) { 1256 frag = &skb_shinfo(skb)->frags[i - 1]; 1257 size = skb_frag_size(frag); 1258 1259 ret = priv->ops.fill_desc(ring, frag, size, 1260 seg_num - 1 == i ? 1 : 0, 1261 DESC_TYPE_PAGE); 1262 1263 if (ret) 1264 goto frag_fill_err; 1265 } 1266 1267 /* Complete translate all packets */ 1268 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1269 netdev_tx_sent_queue(dev_queue, skb->len); 1270 1271 wmb(); /* Commit all data before submit */ 1272 1273 hnae3_queue_xmit(ring->tqp, buf_num); 1274 1275 return NETDEV_TX_OK; 1276 1277 frag_fill_err: 1278 hns3_clear_desc(ring, next_to_use_frag); 1279 1280 head_fill_err: 1281 hns3_clear_desc(ring, next_to_use_head); 1282 1283 out_err_tx_ok: 1284 dev_kfree_skb_any(skb); 1285 return NETDEV_TX_OK; 1286 1287 out_net_tx_busy: 1288 netif_stop_subqueue(netdev, ring_data->queue_index); 1289 smp_mb(); /* Commit all data before submit */ 1290 1291 return NETDEV_TX_BUSY; 1292 } 1293 1294 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1295 { 1296 struct hnae3_handle *h = hns3_get_handle(netdev); 1297 struct sockaddr *mac_addr = p; 1298 int ret; 1299 1300 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1301 return -EADDRNOTAVAIL; 1302 1303 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1304 netdev_info(netdev, "already using mac address %pM\n", 1305 mac_addr->sa_data); 1306 return 0; 1307 } 1308 1309 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1310 if (ret) { 1311 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1312 return ret; 1313 } 1314 1315 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1316 1317 return 0; 1318 } 1319 1320 static int hns3_nic_do_ioctl(struct net_device *netdev, 1321 struct ifreq *ifr, int cmd) 1322 { 1323 struct hnae3_handle *h = hns3_get_handle(netdev); 1324 1325 if (!netif_running(netdev)) 1326 return -EINVAL; 1327 1328 if (!h->ae_algo->ops->do_ioctl) 1329 return -EOPNOTSUPP; 1330 1331 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1332 } 1333 1334 static int hns3_nic_set_features(struct net_device *netdev, 1335 netdev_features_t features) 1336 { 1337 netdev_features_t changed = netdev->features ^ features; 1338 struct hns3_nic_priv *priv = netdev_priv(netdev); 1339 struct hnae3_handle *h = priv->ae_handle; 1340 int ret; 1341 1342 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1343 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1344 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1345 else 1346 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1347 } 1348 1349 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1350 if (features & NETIF_F_GRO_HW) 1351 ret = h->ae_algo->ops->set_gro_en(h, true); 1352 else 1353 ret = h->ae_algo->ops->set_gro_en(h, false); 1354 if (ret) 1355 return ret; 1356 } 1357 1358 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1359 h->ae_algo->ops->enable_vlan_filter) { 1360 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1361 h->ae_algo->ops->enable_vlan_filter(h, true); 1362 else 1363 h->ae_algo->ops->enable_vlan_filter(h, false); 1364 } 1365 1366 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1367 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1368 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1369 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1370 else 1371 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1372 1373 if (ret) 1374 return ret; 1375 } 1376 1377 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1378 if (features & NETIF_F_NTUPLE) 1379 h->ae_algo->ops->enable_fd(h, true); 1380 else 1381 h->ae_algo->ops->enable_fd(h, false); 1382 } 1383 1384 netdev->features = features; 1385 return 0; 1386 } 1387 1388 static void hns3_nic_get_stats64(struct net_device *netdev, 1389 struct rtnl_link_stats64 *stats) 1390 { 1391 struct hns3_nic_priv *priv = netdev_priv(netdev); 1392 int queue_num = priv->ae_handle->kinfo.num_tqps; 1393 struct hnae3_handle *handle = priv->ae_handle; 1394 struct hns3_enet_ring *ring; 1395 unsigned int start; 1396 unsigned int idx; 1397 u64 tx_bytes = 0; 1398 u64 rx_bytes = 0; 1399 u64 tx_pkts = 0; 1400 u64 rx_pkts = 0; 1401 u64 tx_drop = 0; 1402 u64 rx_drop = 0; 1403 1404 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1405 return; 1406 1407 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1408 1409 for (idx = 0; idx < queue_num; idx++) { 1410 /* fetch the tx stats */ 1411 ring = priv->ring_data[idx].ring; 1412 do { 1413 start = u64_stats_fetch_begin_irq(&ring->syncp); 1414 tx_bytes += ring->stats.tx_bytes; 1415 tx_pkts += ring->stats.tx_pkts; 1416 tx_drop += ring->stats.tx_busy; 1417 tx_drop += ring->stats.sw_err_cnt; 1418 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1419 1420 /* fetch the rx stats */ 1421 ring = priv->ring_data[idx + queue_num].ring; 1422 do { 1423 start = u64_stats_fetch_begin_irq(&ring->syncp); 1424 rx_bytes += ring->stats.rx_bytes; 1425 rx_pkts += ring->stats.rx_pkts; 1426 rx_drop += ring->stats.non_vld_descs; 1427 rx_drop += ring->stats.err_pkt_len; 1428 rx_drop += ring->stats.l2_err; 1429 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1430 } 1431 1432 stats->tx_bytes = tx_bytes; 1433 stats->tx_packets = tx_pkts; 1434 stats->rx_bytes = rx_bytes; 1435 stats->rx_packets = rx_pkts; 1436 1437 stats->rx_errors = netdev->stats.rx_errors; 1438 stats->multicast = netdev->stats.multicast; 1439 stats->rx_length_errors = netdev->stats.rx_length_errors; 1440 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1441 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1442 1443 stats->tx_errors = netdev->stats.tx_errors; 1444 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1445 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1446 stats->collisions = netdev->stats.collisions; 1447 stats->rx_over_errors = netdev->stats.rx_over_errors; 1448 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1449 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1450 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1451 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1452 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1453 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1454 stats->tx_window_errors = netdev->stats.tx_window_errors; 1455 stats->rx_compressed = netdev->stats.rx_compressed; 1456 stats->tx_compressed = netdev->stats.tx_compressed; 1457 } 1458 1459 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1460 { 1461 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1462 struct hnae3_handle *h = hns3_get_handle(netdev); 1463 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1464 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1465 u8 tc = mqprio_qopt->qopt.num_tc; 1466 u16 mode = mqprio_qopt->mode; 1467 u8 hw = mqprio_qopt->qopt.hw; 1468 bool if_running; 1469 int ret; 1470 1471 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1472 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1473 return -EOPNOTSUPP; 1474 1475 if (tc > HNAE3_MAX_TC) 1476 return -EINVAL; 1477 1478 if (!netdev) 1479 return -EINVAL; 1480 1481 if_running = netif_running(netdev); 1482 if (if_running) { 1483 hns3_nic_net_stop(netdev); 1484 msleep(100); 1485 } 1486 1487 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1488 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1489 if (ret) 1490 goto out; 1491 1492 ret = hns3_nic_set_real_num_queue(netdev); 1493 1494 out: 1495 if (if_running) 1496 hns3_nic_net_open(netdev); 1497 1498 return ret; 1499 } 1500 1501 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1502 void *type_data) 1503 { 1504 if (type != TC_SETUP_QDISC_MQPRIO) 1505 return -EOPNOTSUPP; 1506 1507 return hns3_setup_tc(dev, type_data); 1508 } 1509 1510 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1511 __be16 proto, u16 vid) 1512 { 1513 struct hnae3_handle *h = hns3_get_handle(netdev); 1514 struct hns3_nic_priv *priv = netdev_priv(netdev); 1515 int ret = -EIO; 1516 1517 if (h->ae_algo->ops->set_vlan_filter) 1518 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1519 1520 if (!ret) 1521 set_bit(vid, priv->active_vlans); 1522 1523 return ret; 1524 } 1525 1526 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1527 __be16 proto, u16 vid) 1528 { 1529 struct hnae3_handle *h = hns3_get_handle(netdev); 1530 struct hns3_nic_priv *priv = netdev_priv(netdev); 1531 int ret = -EIO; 1532 1533 if (h->ae_algo->ops->set_vlan_filter) 1534 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1535 1536 if (!ret) 1537 clear_bit(vid, priv->active_vlans); 1538 1539 return ret; 1540 } 1541 1542 static int hns3_restore_vlan(struct net_device *netdev) 1543 { 1544 struct hns3_nic_priv *priv = netdev_priv(netdev); 1545 int ret = 0; 1546 u16 vid; 1547 1548 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1549 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1550 if (ret) { 1551 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1552 vid, ret); 1553 return ret; 1554 } 1555 } 1556 1557 return ret; 1558 } 1559 1560 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1561 u8 qos, __be16 vlan_proto) 1562 { 1563 struct hnae3_handle *h = hns3_get_handle(netdev); 1564 int ret = -EIO; 1565 1566 if (h->ae_algo->ops->set_vf_vlan_filter) 1567 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1568 qos, vlan_proto); 1569 1570 return ret; 1571 } 1572 1573 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1574 { 1575 struct hnae3_handle *h = hns3_get_handle(netdev); 1576 int ret; 1577 1578 if (!h->ae_algo->ops->set_mtu) 1579 return -EOPNOTSUPP; 1580 1581 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1582 if (ret) 1583 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1584 ret); 1585 else 1586 netdev->mtu = new_mtu; 1587 1588 return ret; 1589 } 1590 1591 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1592 { 1593 struct hns3_nic_priv *priv = netdev_priv(ndev); 1594 struct hns3_enet_ring *tx_ring = NULL; 1595 int timeout_queue = 0; 1596 int hw_head, hw_tail; 1597 int i; 1598 1599 /* Find the stopped queue the same way the stack does */ 1600 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1601 struct netdev_queue *q; 1602 unsigned long trans_start; 1603 1604 q = netdev_get_tx_queue(ndev, i); 1605 trans_start = q->trans_start; 1606 if (netif_xmit_stopped(q) && 1607 time_after(jiffies, 1608 (trans_start + ndev->watchdog_timeo))) { 1609 timeout_queue = i; 1610 break; 1611 } 1612 } 1613 1614 if (i == ndev->num_tx_queues) { 1615 netdev_info(ndev, 1616 "no netdev TX timeout queue found, timeout count: %llu\n", 1617 priv->tx_timeout_count); 1618 return false; 1619 } 1620 1621 tx_ring = priv->ring_data[timeout_queue].ring; 1622 1623 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1624 HNS3_RING_TX_RING_HEAD_REG); 1625 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1626 HNS3_RING_TX_RING_TAIL_REG); 1627 netdev_info(ndev, 1628 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1629 priv->tx_timeout_count, 1630 timeout_queue, 1631 tx_ring->next_to_use, 1632 tx_ring->next_to_clean, 1633 hw_head, 1634 hw_tail, 1635 readl(tx_ring->tqp_vector->mask_addr)); 1636 1637 return true; 1638 } 1639 1640 static void hns3_nic_net_timeout(struct net_device *ndev) 1641 { 1642 struct hns3_nic_priv *priv = netdev_priv(ndev); 1643 struct hnae3_handle *h = priv->ae_handle; 1644 1645 if (!hns3_get_tx_timeo_queue_info(ndev)) 1646 return; 1647 1648 priv->tx_timeout_count++; 1649 1650 /* request the reset, and let the hclge to determine 1651 * which reset level should be done 1652 */ 1653 if (h->ae_algo->ops->reset_event) 1654 h->ae_algo->ops->reset_event(h->pdev, h); 1655 } 1656 1657 static const struct net_device_ops hns3_nic_netdev_ops = { 1658 .ndo_open = hns3_nic_net_open, 1659 .ndo_stop = hns3_nic_net_stop, 1660 .ndo_start_xmit = hns3_nic_net_xmit, 1661 .ndo_tx_timeout = hns3_nic_net_timeout, 1662 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1663 .ndo_do_ioctl = hns3_nic_do_ioctl, 1664 .ndo_change_mtu = hns3_nic_change_mtu, 1665 .ndo_set_features = hns3_nic_set_features, 1666 .ndo_get_stats64 = hns3_nic_get_stats64, 1667 .ndo_setup_tc = hns3_nic_setup_tc, 1668 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1669 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1670 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1671 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1672 }; 1673 1674 static bool hns3_is_phys_func(struct pci_dev *pdev) 1675 { 1676 u32 dev_id = pdev->device; 1677 1678 switch (dev_id) { 1679 case HNAE3_DEV_ID_GE: 1680 case HNAE3_DEV_ID_25GE: 1681 case HNAE3_DEV_ID_25GE_RDMA: 1682 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1683 case HNAE3_DEV_ID_50GE_RDMA: 1684 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1685 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1686 return true; 1687 case HNAE3_DEV_ID_100G_VF: 1688 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1689 return false; 1690 default: 1691 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1692 dev_id); 1693 } 1694 1695 return false; 1696 } 1697 1698 static void hns3_disable_sriov(struct pci_dev *pdev) 1699 { 1700 /* If our VFs are assigned we cannot shut down SR-IOV 1701 * without causing issues, so just leave the hardware 1702 * available but disabled 1703 */ 1704 if (pci_vfs_assigned(pdev)) { 1705 dev_warn(&pdev->dev, 1706 "disabling driver while VFs are assigned\n"); 1707 return; 1708 } 1709 1710 pci_disable_sriov(pdev); 1711 } 1712 1713 static void hns3_get_dev_capability(struct pci_dev *pdev, 1714 struct hnae3_ae_dev *ae_dev) 1715 { 1716 if (pdev->revision >= 0x21) { 1717 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1718 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1719 } 1720 } 1721 1722 /* hns3_probe - Device initialization routine 1723 * @pdev: PCI device information struct 1724 * @ent: entry in hns3_pci_tbl 1725 * 1726 * hns3_probe initializes a PF identified by a pci_dev structure. 1727 * The OS initialization, configuring of the PF private structure, 1728 * and a hardware reset occur. 1729 * 1730 * Returns 0 on success, negative on failure 1731 */ 1732 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1733 { 1734 struct hnae3_ae_dev *ae_dev; 1735 int ret; 1736 1737 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1738 GFP_KERNEL); 1739 if (!ae_dev) { 1740 ret = -ENOMEM; 1741 return ret; 1742 } 1743 1744 ae_dev->pdev = pdev; 1745 ae_dev->flag = ent->driver_data; 1746 ae_dev->dev_type = HNAE3_DEV_KNIC; 1747 ae_dev->reset_type = HNAE3_NONE_RESET; 1748 hns3_get_dev_capability(pdev, ae_dev); 1749 pci_set_drvdata(pdev, ae_dev); 1750 1751 hnae3_register_ae_dev(ae_dev); 1752 1753 return 0; 1754 } 1755 1756 /* hns3_remove - Device removal routine 1757 * @pdev: PCI device information struct 1758 */ 1759 static void hns3_remove(struct pci_dev *pdev) 1760 { 1761 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1762 1763 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1764 hns3_disable_sriov(pdev); 1765 1766 hnae3_unregister_ae_dev(ae_dev); 1767 } 1768 1769 /** 1770 * hns3_pci_sriov_configure 1771 * @pdev: pointer to a pci_dev structure 1772 * @num_vfs: number of VFs to allocate 1773 * 1774 * Enable or change the number of VFs. Called when the user updates the number 1775 * of VFs in sysfs. 1776 **/ 1777 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1778 { 1779 int ret; 1780 1781 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1782 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1783 return -EINVAL; 1784 } 1785 1786 if (num_vfs) { 1787 ret = pci_enable_sriov(pdev, num_vfs); 1788 if (ret) 1789 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1790 else 1791 return num_vfs; 1792 } else if (!pci_vfs_assigned(pdev)) { 1793 pci_disable_sriov(pdev); 1794 } else { 1795 dev_warn(&pdev->dev, 1796 "Unable to free VFs because some are assigned to VMs.\n"); 1797 } 1798 1799 return 0; 1800 } 1801 1802 static void hns3_shutdown(struct pci_dev *pdev) 1803 { 1804 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1805 1806 hnae3_unregister_ae_dev(ae_dev); 1807 devm_kfree(&pdev->dev, ae_dev); 1808 pci_set_drvdata(pdev, NULL); 1809 1810 if (system_state == SYSTEM_POWER_OFF) 1811 pci_set_power_state(pdev, PCI_D3hot); 1812 } 1813 1814 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1815 pci_channel_state_t state) 1816 { 1817 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1818 pci_ers_result_t ret; 1819 1820 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1821 1822 if (state == pci_channel_io_perm_failure) 1823 return PCI_ERS_RESULT_DISCONNECT; 1824 1825 if (!ae_dev) { 1826 dev_err(&pdev->dev, 1827 "Can't recover - error happened during device init\n"); 1828 return PCI_ERS_RESULT_NONE; 1829 } 1830 1831 if (ae_dev->ops->process_hw_error) 1832 ret = ae_dev->ops->process_hw_error(ae_dev); 1833 else 1834 return PCI_ERS_RESULT_NONE; 1835 1836 return ret; 1837 } 1838 1839 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1840 { 1841 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1842 struct device *dev = &pdev->dev; 1843 1844 dev_info(dev, "requesting reset due to PCI error\n"); 1845 1846 /* request the reset */ 1847 if (ae_dev->ops->reset_event) { 1848 ae_dev->ops->reset_event(pdev, NULL); 1849 return PCI_ERS_RESULT_RECOVERED; 1850 } 1851 1852 return PCI_ERS_RESULT_DISCONNECT; 1853 } 1854 1855 static void hns3_reset_prepare(struct pci_dev *pdev) 1856 { 1857 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1858 1859 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1860 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1861 ae_dev->ops->flr_prepare(ae_dev); 1862 } 1863 1864 static void hns3_reset_done(struct pci_dev *pdev) 1865 { 1866 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1867 1868 dev_info(&pdev->dev, "hns3 flr done\n"); 1869 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1870 ae_dev->ops->flr_done(ae_dev); 1871 } 1872 1873 static const struct pci_error_handlers hns3_err_handler = { 1874 .error_detected = hns3_error_detected, 1875 .slot_reset = hns3_slot_reset, 1876 .reset_prepare = hns3_reset_prepare, 1877 .reset_done = hns3_reset_done, 1878 }; 1879 1880 static struct pci_driver hns3_driver = { 1881 .name = hns3_driver_name, 1882 .id_table = hns3_pci_tbl, 1883 .probe = hns3_probe, 1884 .remove = hns3_remove, 1885 .shutdown = hns3_shutdown, 1886 .sriov_configure = hns3_pci_sriov_configure, 1887 .err_handler = &hns3_err_handler, 1888 }; 1889 1890 /* set default feature to hns3 */ 1891 static void hns3_set_default_feature(struct net_device *netdev) 1892 { 1893 struct hnae3_handle *h = hns3_get_handle(netdev); 1894 struct pci_dev *pdev = h->pdev; 1895 1896 netdev->priv_flags |= IFF_UNICAST_FLT; 1897 1898 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1899 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1900 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1901 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1902 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1903 1904 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1905 1906 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1907 1908 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1909 NETIF_F_HW_VLAN_CTAG_FILTER | 1910 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1911 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1912 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1913 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1914 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1915 1916 netdev->vlan_features |= 1917 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1918 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1919 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1920 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1921 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1922 1923 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1924 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1925 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1926 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1927 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1928 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1929 1930 if (pdev->revision >= 0x21) { 1931 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | 1932 NETIF_F_GRO_HW; 1933 netdev->features |= NETIF_F_GRO_HW; 1934 1935 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1936 netdev->hw_features |= NETIF_F_NTUPLE; 1937 netdev->features |= NETIF_F_NTUPLE; 1938 } 1939 } 1940 } 1941 1942 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1943 struct hns3_desc_cb *cb) 1944 { 1945 unsigned int order = hnae3_page_order(ring); 1946 struct page *p; 1947 1948 p = dev_alloc_pages(order); 1949 if (!p) 1950 return -ENOMEM; 1951 1952 cb->priv = p; 1953 cb->page_offset = 0; 1954 cb->reuse_flag = 0; 1955 cb->buf = page_address(p); 1956 cb->length = hnae3_page_size(ring); 1957 cb->type = DESC_TYPE_PAGE; 1958 1959 return 0; 1960 } 1961 1962 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1963 struct hns3_desc_cb *cb) 1964 { 1965 if (cb->type == DESC_TYPE_SKB) 1966 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1967 else if (!HNAE3_IS_TX_RING(ring)) 1968 put_page((struct page *)cb->priv); 1969 memset(cb, 0, sizeof(*cb)); 1970 } 1971 1972 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1973 { 1974 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1975 cb->length, ring_to_dma_dir(ring)); 1976 1977 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 1978 return -EIO; 1979 1980 return 0; 1981 } 1982 1983 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1984 struct hns3_desc_cb *cb) 1985 { 1986 if (cb->type == DESC_TYPE_SKB) 1987 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1988 ring_to_dma_dir(ring)); 1989 else if (cb->length) 1990 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1991 ring_to_dma_dir(ring)); 1992 } 1993 1994 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1995 { 1996 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1997 ring->desc[i].addr = 0; 1998 } 1999 2000 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2001 { 2002 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2003 2004 if (!ring->desc_cb[i].dma) 2005 return; 2006 2007 hns3_buffer_detach(ring, i); 2008 hns3_free_buffer(ring, cb); 2009 } 2010 2011 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2012 { 2013 int i; 2014 2015 for (i = 0; i < ring->desc_num; i++) 2016 hns3_free_buffer_detach(ring, i); 2017 } 2018 2019 /* free desc along with its attached buffer */ 2020 static void hns3_free_desc(struct hns3_enet_ring *ring) 2021 { 2022 int size = ring->desc_num * sizeof(ring->desc[0]); 2023 2024 hns3_free_buffers(ring); 2025 2026 if (ring->desc) { 2027 dma_free_coherent(ring_to_dev(ring), size, 2028 ring->desc, ring->desc_dma_addr); 2029 ring->desc = NULL; 2030 } 2031 } 2032 2033 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2034 { 2035 int size = ring->desc_num * sizeof(ring->desc[0]); 2036 2037 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 2038 &ring->desc_dma_addr, 2039 GFP_KERNEL); 2040 if (!ring->desc) 2041 return -ENOMEM; 2042 2043 return 0; 2044 } 2045 2046 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2047 struct hns3_desc_cb *cb) 2048 { 2049 int ret; 2050 2051 ret = hns3_alloc_buffer(ring, cb); 2052 if (ret) 2053 goto out; 2054 2055 ret = hns3_map_buffer(ring, cb); 2056 if (ret) 2057 goto out_with_buf; 2058 2059 return 0; 2060 2061 out_with_buf: 2062 hns3_free_buffer(ring, cb); 2063 out: 2064 return ret; 2065 } 2066 2067 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2068 { 2069 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2070 2071 if (ret) 2072 return ret; 2073 2074 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2075 2076 return 0; 2077 } 2078 2079 /* Allocate memory for raw pkg, and map with dma */ 2080 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2081 { 2082 int i, j, ret; 2083 2084 for (i = 0; i < ring->desc_num; i++) { 2085 ret = hns3_alloc_buffer_attach(ring, i); 2086 if (ret) 2087 goto out_buffer_fail; 2088 } 2089 2090 return 0; 2091 2092 out_buffer_fail: 2093 for (j = i - 1; j >= 0; j--) 2094 hns3_free_buffer_detach(ring, j); 2095 return ret; 2096 } 2097 2098 /* detach a in-used buffer and replace with a reserved one */ 2099 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2100 struct hns3_desc_cb *res_cb) 2101 { 2102 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2103 ring->desc_cb[i] = *res_cb; 2104 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2105 ring->desc[i].rx.bd_base_info = 0; 2106 } 2107 2108 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2109 { 2110 ring->desc_cb[i].reuse_flag = 0; 2111 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2112 + ring->desc_cb[i].page_offset); 2113 ring->desc[i].rx.bd_base_info = 0; 2114 } 2115 2116 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2117 int *pkts) 2118 { 2119 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2120 2121 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2122 (*bytes) += desc_cb->length; 2123 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2124 hns3_free_buffer_detach(ring, ring->next_to_clean); 2125 2126 ring_ptr_move_fw(ring, next_to_clean); 2127 } 2128 2129 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2130 { 2131 int u = ring->next_to_use; 2132 int c = ring->next_to_clean; 2133 2134 if (unlikely(h > ring->desc_num)) 2135 return 0; 2136 2137 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2138 } 2139 2140 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2141 { 2142 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2143 struct hns3_nic_priv *priv = netdev_priv(netdev); 2144 struct netdev_queue *dev_queue; 2145 int bytes, pkts; 2146 int head; 2147 2148 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2149 rmb(); /* Make sure head is ready before touch any data */ 2150 2151 if (is_ring_empty(ring) || head == ring->next_to_clean) 2152 return; /* no data to poll */ 2153 2154 if (unlikely(!is_valid_clean_head(ring, head))) { 2155 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2156 ring->next_to_use, ring->next_to_clean); 2157 2158 u64_stats_update_begin(&ring->syncp); 2159 ring->stats.io_err_cnt++; 2160 u64_stats_update_end(&ring->syncp); 2161 return; 2162 } 2163 2164 bytes = 0; 2165 pkts = 0; 2166 while (head != ring->next_to_clean) { 2167 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2168 /* Issue prefetch for next Tx descriptor */ 2169 prefetch(&ring->desc_cb[ring->next_to_clean]); 2170 } 2171 2172 ring->tqp_vector->tx_group.total_bytes += bytes; 2173 ring->tqp_vector->tx_group.total_packets += pkts; 2174 2175 u64_stats_update_begin(&ring->syncp); 2176 ring->stats.tx_bytes += bytes; 2177 ring->stats.tx_pkts += pkts; 2178 u64_stats_update_end(&ring->syncp); 2179 2180 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2181 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2182 2183 if (unlikely(pkts && netif_carrier_ok(netdev) && 2184 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2185 /* Make sure that anybody stopping the queue after this 2186 * sees the new next_to_clean. 2187 */ 2188 smp_mb(); 2189 if (netif_tx_queue_stopped(dev_queue) && 2190 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2191 netif_tx_wake_queue(dev_queue); 2192 ring->stats.restart_queue++; 2193 } 2194 } 2195 } 2196 2197 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2198 { 2199 int ntc = ring->next_to_clean; 2200 int ntu = ring->next_to_use; 2201 2202 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2203 } 2204 2205 static void 2206 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2207 { 2208 struct hns3_desc_cb *desc_cb; 2209 struct hns3_desc_cb res_cbs; 2210 int i, ret; 2211 2212 for (i = 0; i < cleand_count; i++) { 2213 desc_cb = &ring->desc_cb[ring->next_to_use]; 2214 if (desc_cb->reuse_flag) { 2215 u64_stats_update_begin(&ring->syncp); 2216 ring->stats.reuse_pg_cnt++; 2217 u64_stats_update_end(&ring->syncp); 2218 2219 hns3_reuse_buffer(ring, ring->next_to_use); 2220 } else { 2221 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2222 if (ret) { 2223 u64_stats_update_begin(&ring->syncp); 2224 ring->stats.sw_err_cnt++; 2225 u64_stats_update_end(&ring->syncp); 2226 2227 netdev_err(ring->tqp->handle->kinfo.netdev, 2228 "hnae reserve buffer map failed.\n"); 2229 break; 2230 } 2231 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2232 } 2233 2234 ring_ptr_move_fw(ring, next_to_use); 2235 } 2236 2237 wmb(); /* Make all data has been write before submit */ 2238 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2239 } 2240 2241 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2242 struct hns3_enet_ring *ring, int pull_len, 2243 struct hns3_desc_cb *desc_cb) 2244 { 2245 struct hns3_desc *desc; 2246 u32 truesize; 2247 int size; 2248 int last_offset; 2249 bool twobufs; 2250 2251 twobufs = ((PAGE_SIZE < 8192) && 2252 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2253 2254 desc = &ring->desc[ring->next_to_clean]; 2255 size = le16_to_cpu(desc->rx.size); 2256 2257 truesize = hnae3_buf_size(ring); 2258 2259 if (!twobufs) 2260 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2261 2262 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2263 size - pull_len, truesize); 2264 2265 /* Avoid re-using remote pages,flag default unreuse */ 2266 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2267 return; 2268 2269 if (twobufs) { 2270 /* If we are only owner of page we can reuse it */ 2271 if (likely(page_count(desc_cb->priv) == 1)) { 2272 /* Flip page offset to other buffer */ 2273 desc_cb->page_offset ^= truesize; 2274 2275 desc_cb->reuse_flag = 1; 2276 /* bump ref count on page before it is given*/ 2277 get_page(desc_cb->priv); 2278 } 2279 return; 2280 } 2281 2282 /* Move offset up to the next cache line */ 2283 desc_cb->page_offset += truesize; 2284 2285 if (desc_cb->page_offset <= last_offset) { 2286 desc_cb->reuse_flag = 1; 2287 /* Bump ref count on page before it is given*/ 2288 get_page(desc_cb->priv); 2289 } 2290 } 2291 2292 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2293 struct hns3_desc *desc) 2294 { 2295 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2296 int l3_type, l4_type; 2297 u32 bd_base_info; 2298 int ol4_type; 2299 u32 l234info; 2300 2301 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2302 l234info = le32_to_cpu(desc->rx.l234_info); 2303 2304 skb->ip_summed = CHECKSUM_NONE; 2305 2306 skb_checksum_none_assert(skb); 2307 2308 if (!(netdev->features & NETIF_F_RXCSUM)) 2309 return; 2310 2311 /* We MUST enable hardware checksum before enabling hardware GRO */ 2312 if (skb_shinfo(skb)->gso_size) { 2313 skb->ip_summed = CHECKSUM_UNNECESSARY; 2314 return; 2315 } 2316 2317 /* check if hardware has done checksum */ 2318 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2319 return; 2320 2321 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2322 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2323 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2324 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2325 u64_stats_update_begin(&ring->syncp); 2326 ring->stats.l3l4_csum_err++; 2327 u64_stats_update_end(&ring->syncp); 2328 2329 return; 2330 } 2331 2332 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2333 HNS3_RXD_L3ID_S); 2334 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2335 HNS3_RXD_L4ID_S); 2336 2337 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2338 HNS3_RXD_OL4ID_S); 2339 switch (ol4_type) { 2340 case HNS3_OL4_TYPE_MAC_IN_UDP: 2341 case HNS3_OL4_TYPE_NVGRE: 2342 skb->csum_level = 1; 2343 /* fall through */ 2344 case HNS3_OL4_TYPE_NO_TUN: 2345 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2346 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2347 l3_type == HNS3_L3_TYPE_IPV6) && 2348 (l4_type == HNS3_L4_TYPE_UDP || 2349 l4_type == HNS3_L4_TYPE_TCP || 2350 l4_type == HNS3_L4_TYPE_SCTP)) 2351 skb->ip_summed = CHECKSUM_UNNECESSARY; 2352 break; 2353 default: 2354 break; 2355 } 2356 } 2357 2358 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2359 { 2360 if (skb_has_frag_list(skb)) 2361 napi_gro_flush(&ring->tqp_vector->napi, false); 2362 2363 napi_gro_receive(&ring->tqp_vector->napi, skb); 2364 } 2365 2366 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2367 struct hns3_desc *desc, u32 l234info, 2368 u16 *vlan_tag) 2369 { 2370 struct pci_dev *pdev = ring->tqp->handle->pdev; 2371 2372 if (pdev->revision == 0x20) { 2373 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2374 if (!(*vlan_tag & VLAN_VID_MASK)) 2375 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2376 2377 return (*vlan_tag != 0); 2378 } 2379 2380 #define HNS3_STRP_OUTER_VLAN 0x1 2381 #define HNS3_STRP_INNER_VLAN 0x2 2382 2383 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2384 HNS3_RXD_STRP_TAGP_S)) { 2385 case HNS3_STRP_OUTER_VLAN: 2386 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2387 return true; 2388 case HNS3_STRP_INNER_VLAN: 2389 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2390 return true; 2391 default: 2392 return false; 2393 } 2394 } 2395 2396 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2397 unsigned char *va) 2398 { 2399 #define HNS3_NEED_ADD_FRAG 1 2400 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2401 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2402 struct sk_buff *skb; 2403 2404 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2405 skb = ring->skb; 2406 if (unlikely(!skb)) { 2407 netdev_err(netdev, "alloc rx skb fail\n"); 2408 2409 u64_stats_update_begin(&ring->syncp); 2410 ring->stats.sw_err_cnt++; 2411 u64_stats_update_end(&ring->syncp); 2412 2413 return -ENOMEM; 2414 } 2415 2416 prefetchw(skb->data); 2417 2418 ring->pending_buf = 1; 2419 ring->frag_num = 0; 2420 ring->tail_skb = NULL; 2421 if (length <= HNS3_RX_HEAD_SIZE) { 2422 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2423 2424 /* We can reuse buffer as-is, just make sure it is local */ 2425 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2426 desc_cb->reuse_flag = 1; 2427 else /* This page cannot be reused so discard it */ 2428 put_page(desc_cb->priv); 2429 2430 ring_ptr_move_fw(ring, next_to_clean); 2431 return 0; 2432 } 2433 u64_stats_update_begin(&ring->syncp); 2434 ring->stats.seg_pkt_cnt++; 2435 u64_stats_update_end(&ring->syncp); 2436 2437 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2438 __skb_put(skb, ring->pull_len); 2439 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2440 desc_cb); 2441 ring_ptr_move_fw(ring, next_to_clean); 2442 2443 return HNS3_NEED_ADD_FRAG; 2444 } 2445 2446 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2447 struct sk_buff **out_skb, bool pending) 2448 { 2449 struct sk_buff *skb = *out_skb; 2450 struct sk_buff *head_skb = *out_skb; 2451 struct sk_buff *new_skb; 2452 struct hns3_desc_cb *desc_cb; 2453 struct hns3_desc *pre_desc; 2454 u32 bd_base_info; 2455 int pre_bd; 2456 2457 /* if there is pending bd, the SW param next_to_clean has moved 2458 * to next and the next is NULL 2459 */ 2460 if (pending) { 2461 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2462 ring->desc_num; 2463 pre_desc = &ring->desc[pre_bd]; 2464 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2465 } else { 2466 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2467 } 2468 2469 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2470 desc = &ring->desc[ring->next_to_clean]; 2471 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2472 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2473 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)) 2474 return -ENXIO; 2475 2476 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2477 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2478 HNS3_RX_HEAD_SIZE); 2479 if (unlikely(!new_skb)) { 2480 netdev_err(ring->tqp->handle->kinfo.netdev, 2481 "alloc rx skb frag fail\n"); 2482 return -ENXIO; 2483 } 2484 ring->frag_num = 0; 2485 2486 if (ring->tail_skb) { 2487 ring->tail_skb->next = new_skb; 2488 ring->tail_skb = new_skb; 2489 } else { 2490 skb_shinfo(skb)->frag_list = new_skb; 2491 ring->tail_skb = new_skb; 2492 } 2493 } 2494 2495 if (ring->tail_skb) { 2496 head_skb->truesize += hnae3_buf_size(ring); 2497 head_skb->data_len += le16_to_cpu(desc->rx.size); 2498 head_skb->len += le16_to_cpu(desc->rx.size); 2499 skb = ring->tail_skb; 2500 } 2501 2502 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2503 ring_ptr_move_fw(ring, next_to_clean); 2504 ring->pending_buf++; 2505 } 2506 2507 return 0; 2508 } 2509 2510 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info, 2511 u32 bd_base_info) 2512 { 2513 u16 gro_count; 2514 u32 l3_type; 2515 2516 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2517 HNS3_RXD_GRO_COUNT_S); 2518 /* if there is no HW GRO, do not set gro params */ 2519 if (!gro_count) 2520 return; 2521 2522 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count 2523 * to skb_shinfo(skb)->gso_segs 2524 */ 2525 NAPI_GRO_CB(skb)->count = gro_count; 2526 2527 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2528 HNS3_RXD_L3ID_S); 2529 if (l3_type == HNS3_L3_TYPE_IPV4) 2530 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2531 else if (l3_type == HNS3_L3_TYPE_IPV6) 2532 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2533 else 2534 return; 2535 2536 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2537 HNS3_RXD_GRO_SIZE_M, 2538 HNS3_RXD_GRO_SIZE_S); 2539 if (skb_shinfo(skb)->gso_size) 2540 tcp_gro_complete(skb); 2541 } 2542 2543 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2544 struct sk_buff *skb) 2545 { 2546 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2547 struct hnae3_handle *handle = ring->tqp->handle; 2548 enum pkt_hash_types rss_type; 2549 2550 if (le32_to_cpu(desc->rx.rss_hash)) 2551 rss_type = handle->kinfo.rss_type; 2552 else 2553 rss_type = PKT_HASH_TYPE_NONE; 2554 2555 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2556 } 2557 2558 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2559 struct sk_buff **out_skb) 2560 { 2561 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2562 struct sk_buff *skb = ring->skb; 2563 struct hns3_desc_cb *desc_cb; 2564 struct hns3_desc *desc; 2565 u32 bd_base_info; 2566 u32 l234info; 2567 int length; 2568 int ret; 2569 2570 desc = &ring->desc[ring->next_to_clean]; 2571 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2572 2573 prefetch(desc); 2574 2575 length = le16_to_cpu(desc->rx.size); 2576 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2577 2578 /* Check valid BD */ 2579 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2580 return -ENXIO; 2581 2582 if (!skb) 2583 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2584 2585 /* Prefetch first cache line of first page 2586 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2587 * line size is 64B so need to prefetch twice to make it 128B. But in 2588 * actual we can have greater size of caches with 128B Level 1 cache 2589 * lines. In such a case, single fetch would suffice to cache in the 2590 * relevant part of the header. 2591 */ 2592 prefetch(ring->va); 2593 #if L1_CACHE_BYTES < 128 2594 prefetch(ring->va + L1_CACHE_BYTES); 2595 #endif 2596 2597 if (!skb) { 2598 ret = hns3_alloc_skb(ring, length, ring->va); 2599 *out_skb = skb = ring->skb; 2600 2601 if (ret < 0) /* alloc buffer fail */ 2602 return ret; 2603 if (ret > 0) { /* need add frag */ 2604 ret = hns3_add_frag(ring, desc, &skb, false); 2605 if (ret) 2606 return ret; 2607 2608 /* As the head data may be changed when GRO enable, copy 2609 * the head data in after other data rx completed 2610 */ 2611 memcpy(skb->data, ring->va, 2612 ALIGN(ring->pull_len, sizeof(long))); 2613 } 2614 } else { 2615 ret = hns3_add_frag(ring, desc, &skb, true); 2616 if (ret) 2617 return ret; 2618 2619 /* As the head data may be changed when GRO enable, copy 2620 * the head data in after other data rx completed 2621 */ 2622 memcpy(skb->data, ring->va, 2623 ALIGN(ring->pull_len, sizeof(long))); 2624 } 2625 2626 l234info = le32_to_cpu(desc->rx.l234_info); 2627 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2628 2629 /* Based on hw strategy, the tag offloaded will be stored at 2630 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2631 * in one layer tag case. 2632 */ 2633 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2634 u16 vlan_tag; 2635 2636 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2637 __vlan_hwaccel_put_tag(skb, 2638 htons(ETH_P_8021Q), 2639 vlan_tag); 2640 } 2641 2642 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2643 u64_stats_update_begin(&ring->syncp); 2644 ring->stats.non_vld_descs++; 2645 u64_stats_update_end(&ring->syncp); 2646 2647 dev_kfree_skb_any(skb); 2648 return -EINVAL; 2649 } 2650 2651 if (unlikely((!desc->rx.pkt_len) || 2652 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2653 u64_stats_update_begin(&ring->syncp); 2654 ring->stats.err_pkt_len++; 2655 u64_stats_update_end(&ring->syncp); 2656 2657 dev_kfree_skb_any(skb); 2658 return -EFAULT; 2659 } 2660 2661 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2662 u64_stats_update_begin(&ring->syncp); 2663 ring->stats.l2_err++; 2664 u64_stats_update_end(&ring->syncp); 2665 2666 dev_kfree_skb_any(skb); 2667 return -EFAULT; 2668 } 2669 2670 u64_stats_update_begin(&ring->syncp); 2671 ring->stats.rx_pkts++; 2672 ring->stats.rx_bytes += skb->len; 2673 u64_stats_update_end(&ring->syncp); 2674 2675 ring->tqp_vector->rx_group.total_bytes += skb->len; 2676 2677 /* This is needed in order to enable forwarding support */ 2678 hns3_set_gro_param(skb, l234info, bd_base_info); 2679 2680 hns3_rx_checksum(ring, skb, desc); 2681 *out_skb = skb; 2682 hns3_set_rx_skb_rss_type(ring, skb); 2683 2684 return 0; 2685 } 2686 2687 int hns3_clean_rx_ring( 2688 struct hns3_enet_ring *ring, int budget, 2689 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2690 { 2691 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2692 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2693 int recv_pkts, recv_bds, clean_count, err; 2694 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2695 struct sk_buff *skb = ring->skb; 2696 int num; 2697 2698 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2699 rmb(); /* Make sure num taken effect before the other data is touched */ 2700 2701 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2702 num -= unused_count; 2703 2704 while (recv_pkts < budget && recv_bds < num) { 2705 /* Reuse or realloc buffers */ 2706 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2707 hns3_nic_alloc_rx_buffers(ring, 2708 clean_count + unused_count); 2709 clean_count = 0; 2710 unused_count = hns3_desc_unused(ring) - 2711 ring->pending_buf; 2712 } 2713 2714 /* Poll one pkt */ 2715 err = hns3_handle_rx_bd(ring, &skb); 2716 if (unlikely(!skb)) /* This fault cannot be repaired */ 2717 goto out; 2718 2719 if (err == -ENXIO) { /* Do not get FE for the packet */ 2720 goto out; 2721 } else if (unlikely(err)) { /* Do jump the err */ 2722 recv_bds += ring->pending_buf; 2723 clean_count += ring->pending_buf; 2724 ring->skb = NULL; 2725 ring->pending_buf = 0; 2726 continue; 2727 } 2728 2729 /* Do update ip stack process */ 2730 skb->protocol = eth_type_trans(skb, netdev); 2731 rx_fn(ring, skb); 2732 recv_bds += ring->pending_buf; 2733 clean_count += ring->pending_buf; 2734 ring->skb = NULL; 2735 ring->pending_buf = 0; 2736 2737 recv_pkts++; 2738 } 2739 2740 out: 2741 /* Make all data has been write before submit */ 2742 if (clean_count + unused_count > 0) 2743 hns3_nic_alloc_rx_buffers(ring, 2744 clean_count + unused_count); 2745 2746 return recv_pkts; 2747 } 2748 2749 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2750 { 2751 struct hns3_enet_tqp_vector *tqp_vector = 2752 ring_group->ring->tqp_vector; 2753 enum hns3_flow_level_range new_flow_level; 2754 int packets_per_msecs; 2755 int bytes_per_msecs; 2756 u32 time_passed_ms; 2757 u16 new_int_gl; 2758 2759 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2760 return false; 2761 2762 if (ring_group->total_packets == 0) { 2763 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2764 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2765 return true; 2766 } 2767 2768 /* Simple throttlerate management 2769 * 0-10MB/s lower (50000 ints/s) 2770 * 10-20MB/s middle (20000 ints/s) 2771 * 20-1249MB/s high (18000 ints/s) 2772 * > 40000pps ultra (8000 ints/s) 2773 */ 2774 new_flow_level = ring_group->coal.flow_level; 2775 new_int_gl = ring_group->coal.int_gl; 2776 time_passed_ms = 2777 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2778 2779 if (!time_passed_ms) 2780 return false; 2781 2782 do_div(ring_group->total_packets, time_passed_ms); 2783 packets_per_msecs = ring_group->total_packets; 2784 2785 do_div(ring_group->total_bytes, time_passed_ms); 2786 bytes_per_msecs = ring_group->total_bytes; 2787 2788 #define HNS3_RX_LOW_BYTE_RATE 10000 2789 #define HNS3_RX_MID_BYTE_RATE 20000 2790 2791 switch (new_flow_level) { 2792 case HNS3_FLOW_LOW: 2793 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2794 new_flow_level = HNS3_FLOW_MID; 2795 break; 2796 case HNS3_FLOW_MID: 2797 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2798 new_flow_level = HNS3_FLOW_HIGH; 2799 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2800 new_flow_level = HNS3_FLOW_LOW; 2801 break; 2802 case HNS3_FLOW_HIGH: 2803 case HNS3_FLOW_ULTRA: 2804 default: 2805 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2806 new_flow_level = HNS3_FLOW_MID; 2807 break; 2808 } 2809 2810 #define HNS3_RX_ULTRA_PACKET_RATE 40 2811 2812 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2813 &tqp_vector->rx_group == ring_group) 2814 new_flow_level = HNS3_FLOW_ULTRA; 2815 2816 switch (new_flow_level) { 2817 case HNS3_FLOW_LOW: 2818 new_int_gl = HNS3_INT_GL_50K; 2819 break; 2820 case HNS3_FLOW_MID: 2821 new_int_gl = HNS3_INT_GL_20K; 2822 break; 2823 case HNS3_FLOW_HIGH: 2824 new_int_gl = HNS3_INT_GL_18K; 2825 break; 2826 case HNS3_FLOW_ULTRA: 2827 new_int_gl = HNS3_INT_GL_8K; 2828 break; 2829 default: 2830 break; 2831 } 2832 2833 ring_group->total_bytes = 0; 2834 ring_group->total_packets = 0; 2835 ring_group->coal.flow_level = new_flow_level; 2836 if (new_int_gl != ring_group->coal.int_gl) { 2837 ring_group->coal.int_gl = new_int_gl; 2838 return true; 2839 } 2840 return false; 2841 } 2842 2843 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2844 { 2845 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2846 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2847 bool rx_update, tx_update; 2848 2849 if (tqp_vector->int_adapt_down > 0) { 2850 tqp_vector->int_adapt_down--; 2851 return; 2852 } 2853 2854 if (rx_group->coal.gl_adapt_enable) { 2855 rx_update = hns3_get_new_int_gl(rx_group); 2856 if (rx_update) 2857 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2858 rx_group->coal.int_gl); 2859 } 2860 2861 if (tx_group->coal.gl_adapt_enable) { 2862 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2863 if (tx_update) 2864 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2865 tx_group->coal.int_gl); 2866 } 2867 2868 tqp_vector->last_jiffies = jiffies; 2869 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 2870 } 2871 2872 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2873 { 2874 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2875 struct hns3_enet_ring *ring; 2876 int rx_pkt_total = 0; 2877 2878 struct hns3_enet_tqp_vector *tqp_vector = 2879 container_of(napi, struct hns3_enet_tqp_vector, napi); 2880 bool clean_complete = true; 2881 int rx_budget; 2882 2883 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2884 napi_complete(napi); 2885 return 0; 2886 } 2887 2888 /* Since the actual Tx work is minimal, we can give the Tx a larger 2889 * budget and be more aggressive about cleaning up the Tx descriptors. 2890 */ 2891 hns3_for_each_ring(ring, tqp_vector->tx_group) 2892 hns3_clean_tx_ring(ring); 2893 2894 /* make sure rx ring budget not smaller than 1 */ 2895 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2896 2897 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2898 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2899 hns3_rx_skb); 2900 2901 if (rx_cleaned >= rx_budget) 2902 clean_complete = false; 2903 2904 rx_pkt_total += rx_cleaned; 2905 } 2906 2907 tqp_vector->rx_group.total_packets += rx_pkt_total; 2908 2909 if (!clean_complete) 2910 return budget; 2911 2912 if (likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) && 2913 napi_complete(napi)) { 2914 hns3_update_new_int_gl(tqp_vector); 2915 hns3_mask_vector_irq(tqp_vector, 1); 2916 } 2917 2918 return rx_pkt_total; 2919 } 2920 2921 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2922 struct hnae3_ring_chain_node *head) 2923 { 2924 struct pci_dev *pdev = tqp_vector->handle->pdev; 2925 struct hnae3_ring_chain_node *cur_chain = head; 2926 struct hnae3_ring_chain_node *chain; 2927 struct hns3_enet_ring *tx_ring; 2928 struct hns3_enet_ring *rx_ring; 2929 2930 tx_ring = tqp_vector->tx_group.ring; 2931 if (tx_ring) { 2932 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2933 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2934 HNAE3_RING_TYPE_TX); 2935 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2936 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2937 2938 cur_chain->next = NULL; 2939 2940 while (tx_ring->next) { 2941 tx_ring = tx_ring->next; 2942 2943 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2944 GFP_KERNEL); 2945 if (!chain) 2946 goto err_free_chain; 2947 2948 cur_chain->next = chain; 2949 chain->tqp_index = tx_ring->tqp->tqp_index; 2950 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2951 HNAE3_RING_TYPE_TX); 2952 hnae3_set_field(chain->int_gl_idx, 2953 HNAE3_RING_GL_IDX_M, 2954 HNAE3_RING_GL_IDX_S, 2955 HNAE3_RING_GL_TX); 2956 2957 cur_chain = chain; 2958 } 2959 } 2960 2961 rx_ring = tqp_vector->rx_group.ring; 2962 if (!tx_ring && rx_ring) { 2963 cur_chain->next = NULL; 2964 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2965 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2966 HNAE3_RING_TYPE_RX); 2967 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2968 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2969 2970 rx_ring = rx_ring->next; 2971 } 2972 2973 while (rx_ring) { 2974 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2975 if (!chain) 2976 goto err_free_chain; 2977 2978 cur_chain->next = chain; 2979 chain->tqp_index = rx_ring->tqp->tqp_index; 2980 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2981 HNAE3_RING_TYPE_RX); 2982 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2983 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2984 2985 cur_chain = chain; 2986 2987 rx_ring = rx_ring->next; 2988 } 2989 2990 return 0; 2991 2992 err_free_chain: 2993 cur_chain = head->next; 2994 while (cur_chain) { 2995 chain = cur_chain->next; 2996 devm_kfree(&pdev->dev, chain); 2997 cur_chain = chain; 2998 } 2999 3000 return -ENOMEM; 3001 } 3002 3003 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3004 struct hnae3_ring_chain_node *head) 3005 { 3006 struct pci_dev *pdev = tqp_vector->handle->pdev; 3007 struct hnae3_ring_chain_node *chain_tmp, *chain; 3008 3009 chain = head->next; 3010 3011 while (chain) { 3012 chain_tmp = chain->next; 3013 devm_kfree(&pdev->dev, chain); 3014 chain = chain_tmp; 3015 } 3016 } 3017 3018 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3019 struct hns3_enet_ring *ring) 3020 { 3021 ring->next = group->ring; 3022 group->ring = ring; 3023 3024 group->count++; 3025 } 3026 3027 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3028 { 3029 struct pci_dev *pdev = priv->ae_handle->pdev; 3030 struct hns3_enet_tqp_vector *tqp_vector; 3031 int num_vectors = priv->vector_num; 3032 int numa_node; 3033 int vector_i; 3034 3035 numa_node = dev_to_node(&pdev->dev); 3036 3037 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3038 tqp_vector = &priv->tqp_vector[vector_i]; 3039 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3040 &tqp_vector->affinity_mask); 3041 } 3042 } 3043 3044 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3045 { 3046 struct hnae3_ring_chain_node vector_ring_chain; 3047 struct hnae3_handle *h = priv->ae_handle; 3048 struct hns3_enet_tqp_vector *tqp_vector; 3049 int ret = 0; 3050 int i; 3051 3052 hns3_nic_set_cpumask(priv); 3053 3054 for (i = 0; i < priv->vector_num; i++) { 3055 tqp_vector = &priv->tqp_vector[i]; 3056 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3057 tqp_vector->num_tqps = 0; 3058 } 3059 3060 for (i = 0; i < h->kinfo.num_tqps; i++) { 3061 u16 vector_i = i % priv->vector_num; 3062 u16 tqp_num = h->kinfo.num_tqps; 3063 3064 tqp_vector = &priv->tqp_vector[vector_i]; 3065 3066 hns3_add_ring_to_group(&tqp_vector->tx_group, 3067 priv->ring_data[i].ring); 3068 3069 hns3_add_ring_to_group(&tqp_vector->rx_group, 3070 priv->ring_data[i + tqp_num].ring); 3071 3072 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3073 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3074 tqp_vector->num_tqps++; 3075 } 3076 3077 for (i = 0; i < priv->vector_num; i++) { 3078 tqp_vector = &priv->tqp_vector[i]; 3079 3080 tqp_vector->rx_group.total_bytes = 0; 3081 tqp_vector->rx_group.total_packets = 0; 3082 tqp_vector->tx_group.total_bytes = 0; 3083 tqp_vector->tx_group.total_packets = 0; 3084 tqp_vector->handle = h; 3085 3086 ret = hns3_get_vector_ring_chain(tqp_vector, 3087 &vector_ring_chain); 3088 if (ret) 3089 return ret; 3090 3091 ret = h->ae_algo->ops->map_ring_to_vector(h, 3092 tqp_vector->vector_irq, &vector_ring_chain); 3093 3094 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3095 3096 if (ret) 3097 goto map_ring_fail; 3098 3099 netif_napi_add(priv->netdev, &tqp_vector->napi, 3100 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3101 } 3102 3103 return 0; 3104 3105 map_ring_fail: 3106 while (i--) 3107 netif_napi_del(&priv->tqp_vector[i].napi); 3108 3109 return ret; 3110 } 3111 3112 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3113 { 3114 struct hnae3_handle *h = priv->ae_handle; 3115 struct hns3_enet_tqp_vector *tqp_vector; 3116 struct hnae3_vector_info *vector; 3117 struct pci_dev *pdev = h->pdev; 3118 u16 tqp_num = h->kinfo.num_tqps; 3119 u16 vector_num; 3120 int ret = 0; 3121 u16 i; 3122 3123 /* RSS size, cpu online and vector_num should be the same */ 3124 /* Should consider 2p/4p later */ 3125 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3126 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3127 GFP_KERNEL); 3128 if (!vector) 3129 return -ENOMEM; 3130 3131 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3132 3133 priv->vector_num = vector_num; 3134 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3135 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3136 GFP_KERNEL); 3137 if (!priv->tqp_vector) { 3138 ret = -ENOMEM; 3139 goto out; 3140 } 3141 3142 for (i = 0; i < priv->vector_num; i++) { 3143 tqp_vector = &priv->tqp_vector[i]; 3144 tqp_vector->idx = i; 3145 tqp_vector->mask_addr = vector[i].io_addr; 3146 tqp_vector->vector_irq = vector[i].vector; 3147 hns3_vector_gl_rl_init(tqp_vector, priv); 3148 } 3149 3150 out: 3151 devm_kfree(&pdev->dev, vector); 3152 return ret; 3153 } 3154 3155 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3156 { 3157 group->ring = NULL; 3158 group->count = 0; 3159 } 3160 3161 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3162 { 3163 struct hnae3_ring_chain_node vector_ring_chain; 3164 struct hnae3_handle *h = priv->ae_handle; 3165 struct hns3_enet_tqp_vector *tqp_vector; 3166 int i, ret; 3167 3168 for (i = 0; i < priv->vector_num; i++) { 3169 tqp_vector = &priv->tqp_vector[i]; 3170 3171 ret = hns3_get_vector_ring_chain(tqp_vector, 3172 &vector_ring_chain); 3173 if (ret) 3174 return ret; 3175 3176 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 3177 tqp_vector->vector_irq, &vector_ring_chain); 3178 if (ret) 3179 return ret; 3180 3181 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3182 3183 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) { 3184 (void)irq_set_affinity_hint( 3185 priv->tqp_vector[i].vector_irq, 3186 NULL); 3187 free_irq(priv->tqp_vector[i].vector_irq, 3188 &priv->tqp_vector[i]); 3189 } 3190 3191 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3192 hns3_clear_ring_group(&tqp_vector->rx_group); 3193 hns3_clear_ring_group(&tqp_vector->tx_group); 3194 netif_napi_del(&priv->tqp_vector[i].napi); 3195 } 3196 3197 return 0; 3198 } 3199 3200 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3201 { 3202 struct hnae3_handle *h = priv->ae_handle; 3203 struct pci_dev *pdev = h->pdev; 3204 int i, ret; 3205 3206 for (i = 0; i < priv->vector_num; i++) { 3207 struct hns3_enet_tqp_vector *tqp_vector; 3208 3209 tqp_vector = &priv->tqp_vector[i]; 3210 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3211 if (ret) 3212 return ret; 3213 } 3214 3215 devm_kfree(&pdev->dev, priv->tqp_vector); 3216 return 0; 3217 } 3218 3219 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3220 int ring_type) 3221 { 3222 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3223 int queue_num = priv->ae_handle->kinfo.num_tqps; 3224 struct pci_dev *pdev = priv->ae_handle->pdev; 3225 struct hns3_enet_ring *ring; 3226 3227 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3228 if (!ring) 3229 return -ENOMEM; 3230 3231 if (ring_type == HNAE3_RING_TYPE_TX) { 3232 ring_data[q->tqp_index].ring = ring; 3233 ring_data[q->tqp_index].queue_index = q->tqp_index; 3234 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3235 } else { 3236 ring_data[q->tqp_index + queue_num].ring = ring; 3237 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3238 ring->io_base = q->io_base; 3239 } 3240 3241 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3242 3243 ring->tqp = q; 3244 ring->desc = NULL; 3245 ring->desc_cb = NULL; 3246 ring->dev = priv->dev; 3247 ring->desc_dma_addr = 0; 3248 ring->buf_size = q->buf_size; 3249 ring->desc_num = q->desc_num; 3250 ring->next_to_use = 0; 3251 ring->next_to_clean = 0; 3252 3253 return 0; 3254 } 3255 3256 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3257 struct hns3_nic_priv *priv) 3258 { 3259 int ret; 3260 3261 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3262 if (ret) 3263 return ret; 3264 3265 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3266 if (ret) { 3267 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3268 return ret; 3269 } 3270 3271 return 0; 3272 } 3273 3274 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3275 { 3276 struct hnae3_handle *h = priv->ae_handle; 3277 struct pci_dev *pdev = h->pdev; 3278 int i, ret; 3279 3280 priv->ring_data = devm_kzalloc(&pdev->dev, 3281 array3_size(h->kinfo.num_tqps, 3282 sizeof(*priv->ring_data), 3283 2), 3284 GFP_KERNEL); 3285 if (!priv->ring_data) 3286 return -ENOMEM; 3287 3288 for (i = 0; i < h->kinfo.num_tqps; i++) { 3289 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3290 if (ret) 3291 goto err; 3292 } 3293 3294 return 0; 3295 err: 3296 while (i--) { 3297 devm_kfree(priv->dev, priv->ring_data[i].ring); 3298 devm_kfree(priv->dev, 3299 priv->ring_data[i + h->kinfo.num_tqps].ring); 3300 } 3301 3302 devm_kfree(&pdev->dev, priv->ring_data); 3303 return ret; 3304 } 3305 3306 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3307 { 3308 struct hnae3_handle *h = priv->ae_handle; 3309 int i; 3310 3311 for (i = 0; i < h->kinfo.num_tqps; i++) { 3312 devm_kfree(priv->dev, priv->ring_data[i].ring); 3313 devm_kfree(priv->dev, 3314 priv->ring_data[i + h->kinfo.num_tqps].ring); 3315 } 3316 devm_kfree(priv->dev, priv->ring_data); 3317 } 3318 3319 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3320 { 3321 int ret; 3322 3323 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3324 return -EINVAL; 3325 3326 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3327 GFP_KERNEL); 3328 if (!ring->desc_cb) { 3329 ret = -ENOMEM; 3330 goto out; 3331 } 3332 3333 ret = hns3_alloc_desc(ring); 3334 if (ret) 3335 goto out_with_desc_cb; 3336 3337 if (!HNAE3_IS_TX_RING(ring)) { 3338 ret = hns3_alloc_ring_buffers(ring); 3339 if (ret) 3340 goto out_with_desc; 3341 } 3342 3343 return 0; 3344 3345 out_with_desc: 3346 hns3_free_desc(ring); 3347 out_with_desc_cb: 3348 kfree(ring->desc_cb); 3349 ring->desc_cb = NULL; 3350 out: 3351 return ret; 3352 } 3353 3354 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3355 { 3356 hns3_free_desc(ring); 3357 kfree(ring->desc_cb); 3358 ring->desc_cb = NULL; 3359 ring->next_to_clean = 0; 3360 ring->next_to_use = 0; 3361 } 3362 3363 static int hns3_buf_size2type(u32 buf_size) 3364 { 3365 int bd_size_type; 3366 3367 switch (buf_size) { 3368 case 512: 3369 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3370 break; 3371 case 1024: 3372 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3373 break; 3374 case 2048: 3375 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3376 break; 3377 case 4096: 3378 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3379 break; 3380 default: 3381 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3382 } 3383 3384 return bd_size_type; 3385 } 3386 3387 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3388 { 3389 dma_addr_t dma = ring->desc_dma_addr; 3390 struct hnae3_queue *q = ring->tqp; 3391 3392 if (!HNAE3_IS_TX_RING(ring)) { 3393 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3394 (u32)dma); 3395 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3396 (u32)((dma >> 31) >> 1)); 3397 3398 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3399 hns3_buf_size2type(ring->buf_size)); 3400 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3401 ring->desc_num / 8 - 1); 3402 3403 } else { 3404 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3405 (u32)dma); 3406 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3407 (u32)((dma >> 31) >> 1)); 3408 3409 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3410 ring->desc_num / 8 - 1); 3411 } 3412 } 3413 3414 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3415 { 3416 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3417 int i; 3418 3419 for (i = 0; i < HNAE3_MAX_TC; i++) { 3420 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3421 int j; 3422 3423 if (!tc_info->enable) 3424 continue; 3425 3426 for (j = 0; j < tc_info->tqp_count; j++) { 3427 struct hnae3_queue *q; 3428 3429 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3430 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3431 tc_info->tc); 3432 } 3433 } 3434 } 3435 3436 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3437 { 3438 struct hnae3_handle *h = priv->ae_handle; 3439 int ring_num = h->kinfo.num_tqps * 2; 3440 int i, j; 3441 int ret; 3442 3443 for (i = 0; i < ring_num; i++) { 3444 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3445 if (ret) { 3446 dev_err(priv->dev, 3447 "Alloc ring memory fail! ret=%d\n", ret); 3448 goto out_when_alloc_ring_memory; 3449 } 3450 3451 u64_stats_init(&priv->ring_data[i].ring->syncp); 3452 } 3453 3454 return 0; 3455 3456 out_when_alloc_ring_memory: 3457 for (j = i - 1; j >= 0; j--) 3458 hns3_fini_ring(priv->ring_data[j].ring); 3459 3460 return -ENOMEM; 3461 } 3462 3463 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3464 { 3465 struct hnae3_handle *h = priv->ae_handle; 3466 int i; 3467 3468 for (i = 0; i < h->kinfo.num_tqps; i++) { 3469 hns3_fini_ring(priv->ring_data[i].ring); 3470 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3471 } 3472 return 0; 3473 } 3474 3475 /* Set mac addr if it is configured. or leave it to the AE driver */ 3476 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3477 { 3478 struct hns3_nic_priv *priv = netdev_priv(netdev); 3479 struct hnae3_handle *h = priv->ae_handle; 3480 u8 mac_addr_temp[ETH_ALEN]; 3481 int ret = 0; 3482 3483 if (h->ae_algo->ops->get_mac_addr && init) { 3484 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3485 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3486 } 3487 3488 /* Check if the MAC address is valid, if not get a random one */ 3489 if (!is_valid_ether_addr(netdev->dev_addr)) { 3490 eth_hw_addr_random(netdev); 3491 dev_warn(priv->dev, "using random MAC address %pM\n", 3492 netdev->dev_addr); 3493 } 3494 3495 if (h->ae_algo->ops->set_mac_addr) 3496 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3497 3498 return ret; 3499 } 3500 3501 static int hns3_restore_fd_rules(struct net_device *netdev) 3502 { 3503 struct hnae3_handle *h = hns3_get_handle(netdev); 3504 int ret = 0; 3505 3506 if (h->ae_algo->ops->restore_fd_rules) 3507 ret = h->ae_algo->ops->restore_fd_rules(h); 3508 3509 return ret; 3510 } 3511 3512 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3513 { 3514 struct hnae3_handle *h = hns3_get_handle(netdev); 3515 3516 if (h->ae_algo->ops->del_all_fd_entries) 3517 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3518 } 3519 3520 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3521 { 3522 struct hns3_nic_priv *priv = netdev_priv(netdev); 3523 3524 priv->ops.fill_desc = hns3_fill_desc; 3525 if ((netdev->features & NETIF_F_TSO) || 3526 (netdev->features & NETIF_F_TSO6)) 3527 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3528 else 3529 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3530 } 3531 3532 static int hns3_client_start(struct hnae3_handle *handle) 3533 { 3534 if (!handle->ae_algo->ops->client_start) 3535 return 0; 3536 3537 return handle->ae_algo->ops->client_start(handle); 3538 } 3539 3540 static void hns3_client_stop(struct hnae3_handle *handle) 3541 { 3542 if (!handle->ae_algo->ops->client_stop) 3543 return; 3544 3545 handle->ae_algo->ops->client_stop(handle); 3546 } 3547 3548 static int hns3_client_init(struct hnae3_handle *handle) 3549 { 3550 struct pci_dev *pdev = handle->pdev; 3551 u16 alloc_tqps, max_rss_size; 3552 struct hns3_nic_priv *priv; 3553 struct net_device *netdev; 3554 int ret; 3555 3556 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3557 &max_rss_size); 3558 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3559 if (!netdev) 3560 return -ENOMEM; 3561 3562 priv = netdev_priv(netdev); 3563 priv->dev = &pdev->dev; 3564 priv->netdev = netdev; 3565 priv->ae_handle = handle; 3566 priv->tx_timeout_count = 0; 3567 3568 handle->kinfo.netdev = netdev; 3569 handle->priv = (void *)priv; 3570 3571 hns3_init_mac_addr(netdev, true); 3572 3573 hns3_set_default_feature(netdev); 3574 3575 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3576 netdev->priv_flags |= IFF_UNICAST_FLT; 3577 netdev->netdev_ops = &hns3_nic_netdev_ops; 3578 SET_NETDEV_DEV(netdev, &pdev->dev); 3579 hns3_ethtool_set_ops(netdev); 3580 hns3_nic_set_priv_ops(netdev); 3581 3582 /* Carrier off reporting is important to ethtool even BEFORE open */ 3583 netif_carrier_off(netdev); 3584 3585 ret = hns3_get_ring_config(priv); 3586 if (ret) { 3587 ret = -ENOMEM; 3588 goto out_get_ring_cfg; 3589 } 3590 3591 ret = hns3_nic_alloc_vector_data(priv); 3592 if (ret) { 3593 ret = -ENOMEM; 3594 goto out_alloc_vector_data; 3595 } 3596 3597 ret = hns3_nic_init_vector_data(priv); 3598 if (ret) { 3599 ret = -ENOMEM; 3600 goto out_init_vector_data; 3601 } 3602 3603 ret = hns3_init_all_ring(priv); 3604 if (ret) { 3605 ret = -ENOMEM; 3606 goto out_init_ring_data; 3607 } 3608 3609 ret = register_netdev(netdev); 3610 if (ret) { 3611 dev_err(priv->dev, "probe register netdev fail!\n"); 3612 goto out_reg_netdev_fail; 3613 } 3614 3615 ret = hns3_client_start(handle); 3616 if (ret) { 3617 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3618 goto out_reg_netdev_fail; 3619 } 3620 3621 hns3_dcbnl_setup(handle); 3622 3623 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3624 netdev->max_mtu = HNS3_MAX_MTU; 3625 3626 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3627 3628 return ret; 3629 3630 out_reg_netdev_fail: 3631 out_init_ring_data: 3632 (void)hns3_nic_uninit_vector_data(priv); 3633 out_init_vector_data: 3634 hns3_nic_dealloc_vector_data(priv); 3635 out_alloc_vector_data: 3636 priv->ring_data = NULL; 3637 out_get_ring_cfg: 3638 priv->ae_handle = NULL; 3639 free_netdev(netdev); 3640 return ret; 3641 } 3642 3643 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3644 { 3645 struct net_device *netdev = handle->kinfo.netdev; 3646 struct hns3_nic_priv *priv = netdev_priv(netdev); 3647 int ret; 3648 3649 hns3_client_stop(handle); 3650 3651 hns3_remove_hw_addr(netdev); 3652 3653 if (netdev->reg_state != NETREG_UNINITIALIZED) 3654 unregister_netdev(netdev); 3655 3656 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3657 netdev_warn(netdev, "already uninitialized\n"); 3658 goto out_netdev_free; 3659 } 3660 3661 hns3_del_all_fd_rules(netdev, true); 3662 3663 hns3_force_clear_all_rx_ring(handle); 3664 3665 ret = hns3_nic_uninit_vector_data(priv); 3666 if (ret) 3667 netdev_err(netdev, "uninit vector error\n"); 3668 3669 ret = hns3_nic_dealloc_vector_data(priv); 3670 if (ret) 3671 netdev_err(netdev, "dealloc vector error\n"); 3672 3673 ret = hns3_uninit_all_ring(priv); 3674 if (ret) 3675 netdev_err(netdev, "uninit ring error\n"); 3676 3677 hns3_put_ring_config(priv); 3678 3679 priv->ring_data = NULL; 3680 3681 out_netdev_free: 3682 free_netdev(netdev); 3683 } 3684 3685 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3686 { 3687 struct net_device *netdev = handle->kinfo.netdev; 3688 3689 if (!netdev) 3690 return; 3691 3692 if (linkup) { 3693 netif_carrier_on(netdev); 3694 netif_tx_wake_all_queues(netdev); 3695 netdev_info(netdev, "link up\n"); 3696 } else { 3697 netif_carrier_off(netdev); 3698 netif_tx_stop_all_queues(netdev); 3699 netdev_info(netdev, "link down\n"); 3700 } 3701 } 3702 3703 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3704 { 3705 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3706 struct net_device *ndev = kinfo->netdev; 3707 bool if_running; 3708 int ret; 3709 3710 if (tc > HNAE3_MAX_TC) 3711 return -EINVAL; 3712 3713 if (!ndev) 3714 return -ENODEV; 3715 3716 if_running = netif_running(ndev); 3717 3718 if (if_running) { 3719 (void)hns3_nic_net_stop(ndev); 3720 msleep(100); 3721 } 3722 3723 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3724 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3725 if (ret) 3726 goto err_out; 3727 3728 ret = hns3_nic_set_real_num_queue(ndev); 3729 3730 err_out: 3731 if (if_running) 3732 (void)hns3_nic_net_open(ndev); 3733 3734 return ret; 3735 } 3736 3737 static int hns3_recover_hw_addr(struct net_device *ndev) 3738 { 3739 struct netdev_hw_addr_list *list; 3740 struct netdev_hw_addr *ha, *tmp; 3741 int ret = 0; 3742 3743 /* go through and sync uc_addr entries to the device */ 3744 list = &ndev->uc; 3745 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3746 ret = hns3_nic_uc_sync(ndev, ha->addr); 3747 if (ret) 3748 return ret; 3749 } 3750 3751 /* go through and sync mc_addr entries to the device */ 3752 list = &ndev->mc; 3753 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3754 ret = hns3_nic_mc_sync(ndev, ha->addr); 3755 if (ret) 3756 return ret; 3757 } 3758 3759 return ret; 3760 } 3761 3762 static void hns3_remove_hw_addr(struct net_device *netdev) 3763 { 3764 struct netdev_hw_addr_list *list; 3765 struct netdev_hw_addr *ha, *tmp; 3766 3767 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3768 3769 /* go through and unsync uc_addr entries to the device */ 3770 list = &netdev->uc; 3771 list_for_each_entry_safe(ha, tmp, &list->list, list) 3772 hns3_nic_uc_unsync(netdev, ha->addr); 3773 3774 /* go through and unsync mc_addr entries to the device */ 3775 list = &netdev->mc; 3776 list_for_each_entry_safe(ha, tmp, &list->list, list) 3777 if (ha->refcount > 1) 3778 hns3_nic_mc_unsync(netdev, ha->addr); 3779 } 3780 3781 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3782 { 3783 while (ring->next_to_clean != ring->next_to_use) { 3784 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3785 hns3_free_buffer_detach(ring, ring->next_to_clean); 3786 ring_ptr_move_fw(ring, next_to_clean); 3787 } 3788 } 3789 3790 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3791 { 3792 struct hns3_desc_cb res_cbs; 3793 int ret; 3794 3795 while (ring->next_to_use != ring->next_to_clean) { 3796 /* When a buffer is not reused, it's memory has been 3797 * freed in hns3_handle_rx_bd or will be freed by 3798 * stack, so we need to replace the buffer here. 3799 */ 3800 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3801 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3802 if (ret) { 3803 u64_stats_update_begin(&ring->syncp); 3804 ring->stats.sw_err_cnt++; 3805 u64_stats_update_end(&ring->syncp); 3806 /* if alloc new buffer fail, exit directly 3807 * and reclear in up flow. 3808 */ 3809 netdev_warn(ring->tqp->handle->kinfo.netdev, 3810 "reserve buffer map failed, ret = %d\n", 3811 ret); 3812 return ret; 3813 } 3814 hns3_replace_buffer(ring, ring->next_to_use, 3815 &res_cbs); 3816 } 3817 ring_ptr_move_fw(ring, next_to_use); 3818 } 3819 3820 return 0; 3821 } 3822 3823 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3824 { 3825 while (ring->next_to_use != ring->next_to_clean) { 3826 /* When a buffer is not reused, it's memory has been 3827 * freed in hns3_handle_rx_bd or will be freed by 3828 * stack, so only need to unmap the buffer here. 3829 */ 3830 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3831 hns3_unmap_buffer(ring, 3832 &ring->desc_cb[ring->next_to_use]); 3833 ring->desc_cb[ring->next_to_use].dma = 0; 3834 } 3835 3836 ring_ptr_move_fw(ring, next_to_use); 3837 } 3838 } 3839 3840 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3841 { 3842 struct net_device *ndev = h->kinfo.netdev; 3843 struct hns3_nic_priv *priv = netdev_priv(ndev); 3844 struct hns3_enet_ring *ring; 3845 u32 i; 3846 3847 for (i = 0; i < h->kinfo.num_tqps; i++) { 3848 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3849 hns3_force_clear_rx_ring(ring); 3850 } 3851 } 3852 3853 static void hns3_clear_all_ring(struct hnae3_handle *h) 3854 { 3855 struct net_device *ndev = h->kinfo.netdev; 3856 struct hns3_nic_priv *priv = netdev_priv(ndev); 3857 u32 i; 3858 3859 for (i = 0; i < h->kinfo.num_tqps; i++) { 3860 struct netdev_queue *dev_queue; 3861 struct hns3_enet_ring *ring; 3862 3863 ring = priv->ring_data[i].ring; 3864 hns3_clear_tx_ring(ring); 3865 dev_queue = netdev_get_tx_queue(ndev, 3866 priv->ring_data[i].queue_index); 3867 netdev_tx_reset_queue(dev_queue); 3868 3869 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3870 /* Continue to clear other rings even if clearing some 3871 * rings failed. 3872 */ 3873 hns3_clear_rx_ring(ring); 3874 } 3875 } 3876 3877 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3878 { 3879 struct net_device *ndev = h->kinfo.netdev; 3880 struct hns3_nic_priv *priv = netdev_priv(ndev); 3881 struct hns3_enet_ring *rx_ring; 3882 int i, j; 3883 int ret; 3884 3885 for (i = 0; i < h->kinfo.num_tqps; i++) { 3886 ret = h->ae_algo->ops->reset_queue(h, i); 3887 if (ret) 3888 return ret; 3889 3890 hns3_init_ring_hw(priv->ring_data[i].ring); 3891 3892 /* We need to clear tx ring here because self test will 3893 * use the ring and will not run down before up 3894 */ 3895 hns3_clear_tx_ring(priv->ring_data[i].ring); 3896 priv->ring_data[i].ring->next_to_clean = 0; 3897 priv->ring_data[i].ring->next_to_use = 0; 3898 3899 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3900 hns3_init_ring_hw(rx_ring); 3901 ret = hns3_clear_rx_ring(rx_ring); 3902 if (ret) 3903 return ret; 3904 3905 /* We can not know the hardware head and tail when this 3906 * function is called in reset flow, so we reuse all desc. 3907 */ 3908 for (j = 0; j < rx_ring->desc_num; j++) 3909 hns3_reuse_buffer(rx_ring, j); 3910 3911 rx_ring->next_to_clean = 0; 3912 rx_ring->next_to_use = 0; 3913 } 3914 3915 hns3_init_tx_ring_tc(priv); 3916 3917 return 0; 3918 } 3919 3920 static void hns3_store_coal(struct hns3_nic_priv *priv) 3921 { 3922 /* ethtool only support setting and querying one coal 3923 * configuation for now, so save the vector 0' coal 3924 * configuation here in order to restore it. 3925 */ 3926 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 3927 sizeof(struct hns3_enet_coalesce)); 3928 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 3929 sizeof(struct hns3_enet_coalesce)); 3930 } 3931 3932 static void hns3_restore_coal(struct hns3_nic_priv *priv) 3933 { 3934 u16 vector_num = priv->vector_num; 3935 int i; 3936 3937 for (i = 0; i < vector_num; i++) { 3938 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 3939 sizeof(struct hns3_enet_coalesce)); 3940 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 3941 sizeof(struct hns3_enet_coalesce)); 3942 } 3943 } 3944 3945 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3946 { 3947 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 3948 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3949 struct net_device *ndev = kinfo->netdev; 3950 struct hns3_nic_priv *priv = netdev_priv(ndev); 3951 3952 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 3953 return 0; 3954 3955 /* it is cumbersome for hardware to pick-and-choose entries for deletion 3956 * from table space. Hence, for function reset software intervention is 3957 * required to delete the entries 3958 */ 3959 if (hns3_dev_ongoing_func_reset(ae_dev)) { 3960 hns3_remove_hw_addr(ndev); 3961 hns3_del_all_fd_rules(ndev, false); 3962 } 3963 3964 if (!netif_running(ndev)) 3965 return 0; 3966 3967 return hns3_nic_net_stop(ndev); 3968 } 3969 3970 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3971 { 3972 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3973 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 3974 int ret = 0; 3975 3976 if (netif_running(kinfo->netdev)) { 3977 ret = hns3_nic_net_up(kinfo->netdev); 3978 if (ret) { 3979 netdev_err(kinfo->netdev, 3980 "hns net up fail, ret=%d!\n", ret); 3981 return ret; 3982 } 3983 } 3984 3985 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 3986 3987 return ret; 3988 } 3989 3990 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 3991 { 3992 struct net_device *netdev = handle->kinfo.netdev; 3993 struct hns3_nic_priv *priv = netdev_priv(netdev); 3994 bool vlan_filter_enable; 3995 int ret; 3996 3997 ret = hns3_init_mac_addr(netdev, false); 3998 if (ret) 3999 return ret; 4000 4001 ret = hns3_recover_hw_addr(netdev); 4002 if (ret) 4003 return ret; 4004 4005 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4006 if (ret) 4007 return ret; 4008 4009 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4010 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4011 4012 /* Hardware table is only clear when pf resets */ 4013 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4014 ret = hns3_restore_vlan(netdev); 4015 if (ret) 4016 return ret; 4017 } 4018 4019 ret = hns3_restore_fd_rules(netdev); 4020 if (ret) 4021 return ret; 4022 4023 /* Carrier off reporting is important to ethtool even BEFORE open */ 4024 netif_carrier_off(netdev); 4025 4026 ret = hns3_nic_alloc_vector_data(priv); 4027 if (ret) 4028 return ret; 4029 4030 hns3_restore_coal(priv); 4031 4032 ret = hns3_nic_init_vector_data(priv); 4033 if (ret) 4034 goto err_dealloc_vector; 4035 4036 ret = hns3_init_all_ring(priv); 4037 if (ret) 4038 goto err_uninit_vector; 4039 4040 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4041 4042 return ret; 4043 4044 err_uninit_vector: 4045 hns3_nic_uninit_vector_data(priv); 4046 priv->ring_data = NULL; 4047 err_dealloc_vector: 4048 hns3_nic_dealloc_vector_data(priv); 4049 4050 return ret; 4051 } 4052 4053 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4054 { 4055 struct net_device *netdev = handle->kinfo.netdev; 4056 struct hns3_nic_priv *priv = netdev_priv(netdev); 4057 int ret; 4058 4059 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4060 netdev_warn(netdev, "already uninitialized\n"); 4061 return 0; 4062 } 4063 4064 hns3_force_clear_all_rx_ring(handle); 4065 4066 ret = hns3_nic_uninit_vector_data(priv); 4067 if (ret) { 4068 netdev_err(netdev, "uninit vector error\n"); 4069 return ret; 4070 } 4071 4072 hns3_store_coal(priv); 4073 4074 ret = hns3_nic_dealloc_vector_data(priv); 4075 if (ret) 4076 netdev_err(netdev, "dealloc vector error\n"); 4077 4078 ret = hns3_uninit_all_ring(priv); 4079 if (ret) 4080 netdev_err(netdev, "uninit ring error\n"); 4081 4082 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 4083 4084 return ret; 4085 } 4086 4087 static int hns3_reset_notify(struct hnae3_handle *handle, 4088 enum hnae3_reset_notify_type type) 4089 { 4090 int ret = 0; 4091 4092 switch (type) { 4093 case HNAE3_UP_CLIENT: 4094 ret = hns3_reset_notify_up_enet(handle); 4095 break; 4096 case HNAE3_DOWN_CLIENT: 4097 ret = hns3_reset_notify_down_enet(handle); 4098 break; 4099 case HNAE3_INIT_CLIENT: 4100 ret = hns3_reset_notify_init_enet(handle); 4101 break; 4102 case HNAE3_UNINIT_CLIENT: 4103 ret = hns3_reset_notify_uninit_enet(handle); 4104 break; 4105 default: 4106 break; 4107 } 4108 4109 return ret; 4110 } 4111 4112 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num) 4113 { 4114 struct hns3_nic_priv *priv = netdev_priv(netdev); 4115 struct hnae3_handle *h = hns3_get_handle(netdev); 4116 int ret; 4117 4118 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 4119 if (ret) 4120 return ret; 4121 4122 ret = hns3_get_ring_config(priv); 4123 if (ret) 4124 return ret; 4125 4126 ret = hns3_nic_alloc_vector_data(priv); 4127 if (ret) 4128 goto err_alloc_vector; 4129 4130 hns3_restore_coal(priv); 4131 4132 ret = hns3_nic_init_vector_data(priv); 4133 if (ret) 4134 goto err_uninit_vector; 4135 4136 ret = hns3_init_all_ring(priv); 4137 if (ret) 4138 goto err_put_ring; 4139 4140 return 0; 4141 4142 err_put_ring: 4143 hns3_put_ring_config(priv); 4144 err_uninit_vector: 4145 hns3_nic_uninit_vector_data(priv); 4146 err_alloc_vector: 4147 hns3_nic_dealloc_vector_data(priv); 4148 return ret; 4149 } 4150 4151 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 4152 { 4153 return (new_tqp_num / num_tc) * num_tc; 4154 } 4155 4156 int hns3_set_channels(struct net_device *netdev, 4157 struct ethtool_channels *ch) 4158 { 4159 struct hns3_nic_priv *priv = netdev_priv(netdev); 4160 struct hnae3_handle *h = hns3_get_handle(netdev); 4161 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4162 bool if_running = netif_running(netdev); 4163 u32 new_tqp_num = ch->combined_count; 4164 u16 org_tqp_num; 4165 int ret; 4166 4167 if (ch->rx_count || ch->tx_count) 4168 return -EINVAL; 4169 4170 if (new_tqp_num > hns3_get_max_available_channels(h) || 4171 new_tqp_num < kinfo->num_tc) { 4172 dev_err(&netdev->dev, 4173 "Change tqps fail, the tqp range is from %d to %d", 4174 kinfo->num_tc, 4175 hns3_get_max_available_channels(h)); 4176 return -EINVAL; 4177 } 4178 4179 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 4180 if (kinfo->num_tqps == new_tqp_num) 4181 return 0; 4182 4183 if (if_running) 4184 hns3_nic_net_stop(netdev); 4185 4186 ret = hns3_nic_uninit_vector_data(priv); 4187 if (ret) { 4188 dev_err(&netdev->dev, 4189 "Unbind vector with tqp fail, nothing is changed"); 4190 goto open_netdev; 4191 } 4192 4193 hns3_store_coal(priv); 4194 4195 hns3_nic_dealloc_vector_data(priv); 4196 4197 hns3_uninit_all_ring(priv); 4198 hns3_put_ring_config(priv); 4199 4200 org_tqp_num = h->kinfo.num_tqps; 4201 ret = hns3_modify_tqp_num(netdev, new_tqp_num); 4202 if (ret) { 4203 ret = hns3_modify_tqp_num(netdev, org_tqp_num); 4204 if (ret) { 4205 /* If revert to old tqp failed, fatal error occurred */ 4206 dev_err(&netdev->dev, 4207 "Revert to old tqp num fail, ret=%d", ret); 4208 return ret; 4209 } 4210 dev_info(&netdev->dev, 4211 "Change tqp num fail, Revert to old tqp num"); 4212 } 4213 4214 open_netdev: 4215 if (if_running) 4216 hns3_nic_net_open(netdev); 4217 4218 return ret; 4219 } 4220 4221 static const struct hnae3_client_ops client_ops = { 4222 .init_instance = hns3_client_init, 4223 .uninit_instance = hns3_client_uninit, 4224 .link_status_change = hns3_link_status_change, 4225 .setup_tc = hns3_client_setup_tc, 4226 .reset_notify = hns3_reset_notify, 4227 }; 4228 4229 /* hns3_init_module - Driver registration routine 4230 * hns3_init_module is the first routine called when the driver is 4231 * loaded. All it does is register with the PCI subsystem. 4232 */ 4233 static int __init hns3_init_module(void) 4234 { 4235 int ret; 4236 4237 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4238 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4239 4240 client.type = HNAE3_CLIENT_KNIC; 4241 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4242 hns3_driver_name); 4243 4244 client.ops = &client_ops; 4245 4246 INIT_LIST_HEAD(&client.node); 4247 4248 ret = hnae3_register_client(&client); 4249 if (ret) 4250 return ret; 4251 4252 ret = pci_register_driver(&hns3_driver); 4253 if (ret) 4254 hnae3_unregister_client(&client); 4255 4256 return ret; 4257 } 4258 module_init(hns3_init_module); 4259 4260 /* hns3_exit_module - Driver exit cleanup routine 4261 * hns3_exit_module is called just before the driver is removed 4262 * from memory. 4263 */ 4264 static void __exit hns3_exit_module(void) 4265 { 4266 pci_unregister_driver(&hns3_driver); 4267 hnae3_unregister_client(&client); 4268 } 4269 module_exit(hns3_exit_module); 4270 4271 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4272 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4273 MODULE_LICENSE("GPL"); 4274 MODULE_ALIAS("pci:hns-nic"); 4275 MODULE_VERSION(HNS3_MOD_VERSION); 4276