1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 static irqreturn_t hns3_irq_handle(int irq, void *vector) 95 { 96 struct hns3_enet_tqp_vector *tqp_vector = vector; 97 98 napi_schedule_irqoff(&tqp_vector->napi); 99 100 return IRQ_HANDLED; 101 } 102 103 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 104 { 105 struct hns3_enet_tqp_vector *tqp_vectors; 106 unsigned int i; 107 108 for (i = 0; i < priv->vector_num; i++) { 109 tqp_vectors = &priv->tqp_vector[i]; 110 111 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 112 continue; 113 114 /* clear the affinity mask */ 115 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 116 117 /* release the irq resource */ 118 free_irq(tqp_vectors->vector_irq, tqp_vectors); 119 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 120 } 121 } 122 123 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 124 { 125 struct hns3_enet_tqp_vector *tqp_vectors; 126 int txrx_int_idx = 0; 127 int rx_int_idx = 0; 128 int tx_int_idx = 0; 129 unsigned int i; 130 int ret; 131 132 for (i = 0; i < priv->vector_num; i++) { 133 tqp_vectors = &priv->tqp_vector[i]; 134 135 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 136 continue; 137 138 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 140 "%s-%s-%s-%d", hns3_driver_name, 141 pci_name(priv->ae_handle->pdev), 142 "TxRx", txrx_int_idx++); 143 txrx_int_idx++; 144 } else if (tqp_vectors->rx_group.ring) { 145 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 146 "%s-%s-%s-%d", hns3_driver_name, 147 pci_name(priv->ae_handle->pdev), 148 "Rx", rx_int_idx++); 149 } else if (tqp_vectors->tx_group.ring) { 150 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 151 "%s-%s-%s-%d", hns3_driver_name, 152 pci_name(priv->ae_handle->pdev), 153 "Tx", tx_int_idx++); 154 } else { 155 /* Skip this unused q_vector */ 156 continue; 157 } 158 159 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 160 161 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 162 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 163 tqp_vectors->name, tqp_vectors); 164 if (ret) { 165 netdev_err(priv->netdev, "request irq(%d) fail\n", 166 tqp_vectors->vector_irq); 167 hns3_nic_uninit_irq(priv); 168 return ret; 169 } 170 171 irq_set_affinity_hint(tqp_vectors->vector_irq, 172 &tqp_vectors->affinity_mask); 173 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 175 } 176 177 return 0; 178 } 179 180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 181 u32 mask_en) 182 { 183 writel(mask_en, tqp_vector->mask_addr); 184 } 185 186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 napi_enable(&tqp_vector->napi); 189 enable_irq(tqp_vector->vector_irq); 190 191 /* enable vector */ 192 hns3_mask_vector_irq(tqp_vector, 1); 193 } 194 195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 196 { 197 /* disable vector */ 198 hns3_mask_vector_irq(tqp_vector, 0); 199 200 disable_irq(tqp_vector->vector_irq); 201 napi_disable(&tqp_vector->napi); 202 } 203 204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 205 u32 rl_value) 206 { 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 208 209 /* this defines the configuration for RL (Interrupt Rate Limiter). 210 * Rl defines rate of interrupts i.e. number of interrupts-per-second 211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 212 */ 213 214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 215 !tqp_vector->rx_group.coal.gl_adapt_enable) 216 /* According to the hardware, the range of rl_reg is 217 * 0-59 and the unit is 4. 218 */ 219 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 220 221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 222 } 223 224 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 225 u32 gl_value) 226 { 227 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 228 229 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 230 } 231 232 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 233 u32 gl_value) 234 { 235 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 236 237 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 238 } 239 240 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 241 struct hns3_nic_priv *priv) 242 { 243 /* initialize the configuration for interrupt coalescing. 244 * 1. GL (Interrupt Gap Limiter) 245 * 2. RL (Interrupt Rate Limiter) 246 * 247 * Default: enable interrupt coalescing self-adaptive and GL 248 */ 249 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 250 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 251 252 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 253 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 254 255 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 256 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 257 } 258 259 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 260 struct hns3_nic_priv *priv) 261 { 262 struct hnae3_handle *h = priv->ae_handle; 263 264 hns3_set_vector_coalesce_tx_gl(tqp_vector, 265 tqp_vector->tx_group.coal.int_gl); 266 hns3_set_vector_coalesce_rx_gl(tqp_vector, 267 tqp_vector->rx_group.coal.int_gl); 268 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 269 } 270 271 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 272 { 273 struct hnae3_handle *h = hns3_get_handle(netdev); 274 struct hnae3_knic_private_info *kinfo = &h->kinfo; 275 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 276 int i, ret; 277 278 if (kinfo->num_tc <= 1) { 279 netdev_reset_tc(netdev); 280 } else { 281 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 282 if (ret) { 283 netdev_err(netdev, 284 "netdev_set_num_tc fail, ret=%d!\n", ret); 285 return ret; 286 } 287 288 for (i = 0; i < HNAE3_MAX_TC; i++) { 289 if (!kinfo->tc_info[i].enable) 290 continue; 291 292 netdev_set_tc_queue(netdev, 293 kinfo->tc_info[i].tc, 294 kinfo->tc_info[i].tqp_count, 295 kinfo->tc_info[i].tqp_offset); 296 } 297 } 298 299 ret = netif_set_real_num_tx_queues(netdev, queue_size); 300 if (ret) { 301 netdev_err(netdev, 302 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 303 return ret; 304 } 305 306 ret = netif_set_real_num_rx_queues(netdev, queue_size); 307 if (ret) { 308 netdev_err(netdev, 309 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 310 return ret; 311 } 312 313 return 0; 314 } 315 316 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 317 { 318 u16 alloc_tqps, max_rss_size, rss_size; 319 320 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 321 rss_size = alloc_tqps / h->kinfo.num_tc; 322 323 return min_t(u16, rss_size, max_rss_size); 324 } 325 326 static void hns3_tqp_enable(struct hnae3_queue *tqp) 327 { 328 u32 rcb_reg; 329 330 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 331 rcb_reg |= BIT(HNS3_RING_EN_B); 332 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 333 } 334 335 static void hns3_tqp_disable(struct hnae3_queue *tqp) 336 { 337 u32 rcb_reg; 338 339 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 340 rcb_reg &= ~BIT(HNS3_RING_EN_B); 341 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 342 } 343 344 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 345 { 346 #ifdef CONFIG_RFS_ACCEL 347 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 348 netdev->rx_cpu_rmap = NULL; 349 #endif 350 } 351 352 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 353 { 354 #ifdef CONFIG_RFS_ACCEL 355 struct hns3_nic_priv *priv = netdev_priv(netdev); 356 struct hns3_enet_tqp_vector *tqp_vector; 357 int i, ret; 358 359 if (!netdev->rx_cpu_rmap) { 360 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 361 if (!netdev->rx_cpu_rmap) 362 return -ENOMEM; 363 } 364 365 for (i = 0; i < priv->vector_num; i++) { 366 tqp_vector = &priv->tqp_vector[i]; 367 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 368 tqp_vector->vector_irq); 369 if (ret) { 370 hns3_free_rx_cpu_rmap(netdev); 371 return ret; 372 } 373 } 374 #endif 375 return 0; 376 } 377 378 static int hns3_nic_net_up(struct net_device *netdev) 379 { 380 struct hns3_nic_priv *priv = netdev_priv(netdev); 381 struct hnae3_handle *h = priv->ae_handle; 382 int i, j; 383 int ret; 384 385 ret = hns3_nic_reset_all_ring(h); 386 if (ret) 387 return ret; 388 389 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 390 391 /* enable the vectors */ 392 for (i = 0; i < priv->vector_num; i++) 393 hns3_vector_enable(&priv->tqp_vector[i]); 394 395 /* enable rcb */ 396 for (j = 0; j < h->kinfo.num_tqps; j++) 397 hns3_tqp_enable(h->kinfo.tqp[j]); 398 399 /* start the ae_dev */ 400 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 401 if (ret) { 402 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 403 while (j--) 404 hns3_tqp_disable(h->kinfo.tqp[j]); 405 406 for (j = i - 1; j >= 0; j--) 407 hns3_vector_disable(&priv->tqp_vector[j]); 408 } 409 410 return ret; 411 } 412 413 static void hns3_config_xps(struct hns3_nic_priv *priv) 414 { 415 int i; 416 417 for (i = 0; i < priv->vector_num; i++) { 418 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 419 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 420 421 while (ring) { 422 int ret; 423 424 ret = netif_set_xps_queue(priv->netdev, 425 &tqp_vector->affinity_mask, 426 ring->tqp->tqp_index); 427 if (ret) 428 netdev_warn(priv->netdev, 429 "set xps queue failed: %d", ret); 430 431 ring = ring->next; 432 } 433 } 434 } 435 436 static int hns3_nic_net_open(struct net_device *netdev) 437 { 438 struct hns3_nic_priv *priv = netdev_priv(netdev); 439 struct hnae3_handle *h = hns3_get_handle(netdev); 440 struct hnae3_knic_private_info *kinfo; 441 int i, ret; 442 443 if (hns3_nic_resetting(netdev)) 444 return -EBUSY; 445 446 netif_carrier_off(netdev); 447 448 ret = hns3_nic_set_real_num_queue(netdev); 449 if (ret) 450 return ret; 451 452 ret = hns3_nic_net_up(netdev); 453 if (ret) { 454 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 455 return ret; 456 } 457 458 kinfo = &h->kinfo; 459 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 460 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 461 462 if (h->ae_algo->ops->set_timer_task) 463 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 464 465 hns3_config_xps(priv); 466 467 netif_dbg(h, drv, netdev, "net open\n"); 468 469 return 0; 470 } 471 472 static void hns3_reset_tx_queue(struct hnae3_handle *h) 473 { 474 struct net_device *ndev = h->kinfo.netdev; 475 struct hns3_nic_priv *priv = netdev_priv(ndev); 476 struct netdev_queue *dev_queue; 477 u32 i; 478 479 for (i = 0; i < h->kinfo.num_tqps; i++) { 480 dev_queue = netdev_get_tx_queue(ndev, 481 priv->ring[i].queue_index); 482 netdev_tx_reset_queue(dev_queue); 483 } 484 } 485 486 static void hns3_nic_net_down(struct net_device *netdev) 487 { 488 struct hns3_nic_priv *priv = netdev_priv(netdev); 489 struct hnae3_handle *h = hns3_get_handle(netdev); 490 const struct hnae3_ae_ops *ops; 491 int i; 492 493 /* disable vectors */ 494 for (i = 0; i < priv->vector_num; i++) 495 hns3_vector_disable(&priv->tqp_vector[i]); 496 497 /* disable rcb */ 498 for (i = 0; i < h->kinfo.num_tqps; i++) 499 hns3_tqp_disable(h->kinfo.tqp[i]); 500 501 /* stop ae_dev */ 502 ops = priv->ae_handle->ae_algo->ops; 503 if (ops->stop) 504 ops->stop(priv->ae_handle); 505 506 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 507 * during reset process, because driver may not be able 508 * to disable the ring through firmware when downing the netdev. 509 */ 510 if (!hns3_nic_resetting(netdev)) 511 hns3_clear_all_ring(priv->ae_handle, false); 512 513 hns3_reset_tx_queue(priv->ae_handle); 514 } 515 516 static int hns3_nic_net_stop(struct net_device *netdev) 517 { 518 struct hns3_nic_priv *priv = netdev_priv(netdev); 519 struct hnae3_handle *h = hns3_get_handle(netdev); 520 521 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 522 return 0; 523 524 netif_dbg(h, drv, netdev, "net stop\n"); 525 526 if (h->ae_algo->ops->set_timer_task) 527 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 528 529 netif_tx_stop_all_queues(netdev); 530 netif_carrier_off(netdev); 531 532 hns3_nic_net_down(netdev); 533 534 return 0; 535 } 536 537 static int hns3_nic_uc_sync(struct net_device *netdev, 538 const unsigned char *addr) 539 { 540 struct hnae3_handle *h = hns3_get_handle(netdev); 541 542 if (h->ae_algo->ops->add_uc_addr) 543 return h->ae_algo->ops->add_uc_addr(h, addr); 544 545 return 0; 546 } 547 548 static int hns3_nic_uc_unsync(struct net_device *netdev, 549 const unsigned char *addr) 550 { 551 struct hnae3_handle *h = hns3_get_handle(netdev); 552 553 /* need ignore the request of removing device address, because 554 * we store the device address and other addresses of uc list 555 * in the function's mac filter list. 556 */ 557 if (ether_addr_equal(addr, netdev->dev_addr)) 558 return 0; 559 560 if (h->ae_algo->ops->rm_uc_addr) 561 return h->ae_algo->ops->rm_uc_addr(h, addr); 562 563 return 0; 564 } 565 566 static int hns3_nic_mc_sync(struct net_device *netdev, 567 const unsigned char *addr) 568 { 569 struct hnae3_handle *h = hns3_get_handle(netdev); 570 571 if (h->ae_algo->ops->add_mc_addr) 572 return h->ae_algo->ops->add_mc_addr(h, addr); 573 574 return 0; 575 } 576 577 static int hns3_nic_mc_unsync(struct net_device *netdev, 578 const unsigned char *addr) 579 { 580 struct hnae3_handle *h = hns3_get_handle(netdev); 581 582 if (h->ae_algo->ops->rm_mc_addr) 583 return h->ae_algo->ops->rm_mc_addr(h, addr); 584 585 return 0; 586 } 587 588 static u8 hns3_get_netdev_flags(struct net_device *netdev) 589 { 590 u8 flags = 0; 591 592 if (netdev->flags & IFF_PROMISC) { 593 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 594 } else { 595 flags |= HNAE3_VLAN_FLTR; 596 if (netdev->flags & IFF_ALLMULTI) 597 flags |= HNAE3_USER_MPE; 598 } 599 600 return flags; 601 } 602 603 static void hns3_nic_set_rx_mode(struct net_device *netdev) 604 { 605 struct hnae3_handle *h = hns3_get_handle(netdev); 606 u8 new_flags; 607 608 new_flags = hns3_get_netdev_flags(netdev); 609 610 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 611 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 612 613 /* User mode Promisc mode enable and vlan filtering is disabled to 614 * let all packets in. 615 */ 616 h->netdev_flags = new_flags; 617 hns3_request_update_promisc_mode(h); 618 } 619 620 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 621 { 622 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 623 624 if (ops->request_update_promisc_mode) 625 ops->request_update_promisc_mode(handle); 626 } 627 628 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 629 { 630 struct hns3_nic_priv *priv = netdev_priv(netdev); 631 struct hnae3_handle *h = priv->ae_handle; 632 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 633 bool last_state; 634 635 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 && 636 h->ae_algo->ops->enable_vlan_filter) { 637 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 638 if (enable != last_state) { 639 netdev_info(netdev, 640 "%s vlan filter\n", 641 enable ? "enable" : "disable"); 642 h->ae_algo->ops->enable_vlan_filter(h, enable); 643 } 644 } 645 } 646 647 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 648 u16 *mss, u32 *type_cs_vlan_tso) 649 { 650 u32 l4_offset, hdr_len; 651 union l3_hdr_info l3; 652 union l4_hdr_info l4; 653 u32 l4_paylen; 654 int ret; 655 656 if (!skb_is_gso(skb)) 657 return 0; 658 659 ret = skb_cow_head(skb, 0); 660 if (unlikely(ret < 0)) 661 return ret; 662 663 l3.hdr = skb_network_header(skb); 664 l4.hdr = skb_transport_header(skb); 665 666 /* Software should clear the IPv4's checksum field when tso is 667 * needed. 668 */ 669 if (l3.v4->version == 4) 670 l3.v4->check = 0; 671 672 /* tunnel packet */ 673 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 674 SKB_GSO_GRE_CSUM | 675 SKB_GSO_UDP_TUNNEL | 676 SKB_GSO_UDP_TUNNEL_CSUM)) { 677 if ((!(skb_shinfo(skb)->gso_type & 678 SKB_GSO_PARTIAL)) && 679 (skb_shinfo(skb)->gso_type & 680 SKB_GSO_UDP_TUNNEL_CSUM)) { 681 /* Software should clear the udp's checksum 682 * field when tso is needed. 683 */ 684 l4.udp->check = 0; 685 } 686 /* reset l3&l4 pointers from outer to inner headers */ 687 l3.hdr = skb_inner_network_header(skb); 688 l4.hdr = skb_inner_transport_header(skb); 689 690 /* Software should clear the IPv4's checksum field when 691 * tso is needed. 692 */ 693 if (l3.v4->version == 4) 694 l3.v4->check = 0; 695 } 696 697 /* normal or tunnel packet */ 698 l4_offset = l4.hdr - skb->data; 699 700 /* remove payload length from inner pseudo checksum when tso */ 701 l4_paylen = skb->len - l4_offset; 702 703 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 704 hdr_len = sizeof(*l4.udp) + l4_offset; 705 csum_replace_by_diff(&l4.udp->check, 706 (__force __wsum)htonl(l4_paylen)); 707 } else { 708 hdr_len = (l4.tcp->doff << 2) + l4_offset; 709 csum_replace_by_diff(&l4.tcp->check, 710 (__force __wsum)htonl(l4_paylen)); 711 } 712 713 /* find the txbd field values */ 714 *paylen = skb->len - hdr_len; 715 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 716 717 /* get MSS for TSO */ 718 *mss = skb_shinfo(skb)->gso_size; 719 720 trace_hns3_tso(skb); 721 722 return 0; 723 } 724 725 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 726 u8 *il4_proto) 727 { 728 union l3_hdr_info l3; 729 unsigned char *l4_hdr; 730 unsigned char *exthdr; 731 u8 l4_proto_tmp; 732 __be16 frag_off; 733 734 /* find outer header point */ 735 l3.hdr = skb_network_header(skb); 736 l4_hdr = skb_transport_header(skb); 737 738 if (skb->protocol == htons(ETH_P_IPV6)) { 739 exthdr = l3.hdr + sizeof(*l3.v6); 740 l4_proto_tmp = l3.v6->nexthdr; 741 if (l4_hdr != exthdr) 742 ipv6_skip_exthdr(skb, exthdr - skb->data, 743 &l4_proto_tmp, &frag_off); 744 } else if (skb->protocol == htons(ETH_P_IP)) { 745 l4_proto_tmp = l3.v4->protocol; 746 } else { 747 return -EINVAL; 748 } 749 750 *ol4_proto = l4_proto_tmp; 751 752 /* tunnel packet */ 753 if (!skb->encapsulation) { 754 *il4_proto = 0; 755 return 0; 756 } 757 758 /* find inner header point */ 759 l3.hdr = skb_inner_network_header(skb); 760 l4_hdr = skb_inner_transport_header(skb); 761 762 if (l3.v6->version == 6) { 763 exthdr = l3.hdr + sizeof(*l3.v6); 764 l4_proto_tmp = l3.v6->nexthdr; 765 if (l4_hdr != exthdr) 766 ipv6_skip_exthdr(skb, exthdr - skb->data, 767 &l4_proto_tmp, &frag_off); 768 } else if (l3.v4->version == 4) { 769 l4_proto_tmp = l3.v4->protocol; 770 } 771 772 *il4_proto = l4_proto_tmp; 773 774 return 0; 775 } 776 777 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 778 * and it is udp packet, which has a dest port as the IANA assigned. 779 * the hardware is expected to do the checksum offload, but the 780 * hardware will not do the checksum offload when udp dest port is 781 * 4789 or 6081. 782 */ 783 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 784 { 785 union l4_hdr_info l4; 786 787 l4.hdr = skb_transport_header(skb); 788 789 if (!(!skb->encapsulation && 790 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 791 l4.udp->dest == htons(GENEVE_UDP_PORT)))) 792 return false; 793 794 skb_checksum_help(skb); 795 796 return true; 797 } 798 799 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 800 u32 *ol_type_vlan_len_msec) 801 { 802 u32 l2_len, l3_len, l4_len; 803 unsigned char *il2_hdr; 804 union l3_hdr_info l3; 805 union l4_hdr_info l4; 806 807 l3.hdr = skb_network_header(skb); 808 l4.hdr = skb_transport_header(skb); 809 810 /* compute OL2 header size, defined in 2 Bytes */ 811 l2_len = l3.hdr - skb->data; 812 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 813 814 /* compute OL3 header size, defined in 4 Bytes */ 815 l3_len = l4.hdr - l3.hdr; 816 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 817 818 il2_hdr = skb_inner_mac_header(skb); 819 /* compute OL4 header size, defined in 4 Bytes */ 820 l4_len = il2_hdr - l4.hdr; 821 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 822 823 /* define outer network header type */ 824 if (skb->protocol == htons(ETH_P_IP)) { 825 if (skb_is_gso(skb)) 826 hns3_set_field(*ol_type_vlan_len_msec, 827 HNS3_TXD_OL3T_S, 828 HNS3_OL3T_IPV4_CSUM); 829 else 830 hns3_set_field(*ol_type_vlan_len_msec, 831 HNS3_TXD_OL3T_S, 832 HNS3_OL3T_IPV4_NO_CSUM); 833 834 } else if (skb->protocol == htons(ETH_P_IPV6)) { 835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 836 HNS3_OL3T_IPV6); 837 } 838 839 if (ol4_proto == IPPROTO_UDP) 840 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 841 HNS3_TUN_MAC_IN_UDP); 842 else if (ol4_proto == IPPROTO_GRE) 843 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 844 HNS3_TUN_NVGRE); 845 } 846 847 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 848 u8 il4_proto, u32 *type_cs_vlan_tso, 849 u32 *ol_type_vlan_len_msec) 850 { 851 unsigned char *l2_hdr = skb->data; 852 u32 l4_proto = ol4_proto; 853 union l4_hdr_info l4; 854 union l3_hdr_info l3; 855 u32 l2_len, l3_len; 856 857 l4.hdr = skb_transport_header(skb); 858 l3.hdr = skb_network_header(skb); 859 860 /* handle encapsulation skb */ 861 if (skb->encapsulation) { 862 /* If this is a not UDP/GRE encapsulation skb */ 863 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 864 /* drop the skb tunnel packet if hardware don't support, 865 * because hardware can't calculate csum when TSO. 866 */ 867 if (skb_is_gso(skb)) 868 return -EDOM; 869 870 /* the stack computes the IP header already, 871 * driver calculate l4 checksum when not TSO. 872 */ 873 skb_checksum_help(skb); 874 return 0; 875 } 876 877 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 878 879 /* switch to inner header */ 880 l2_hdr = skb_inner_mac_header(skb); 881 l3.hdr = skb_inner_network_header(skb); 882 l4.hdr = skb_inner_transport_header(skb); 883 l4_proto = il4_proto; 884 } 885 886 if (l3.v4->version == 4) { 887 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 888 HNS3_L3T_IPV4); 889 890 /* the stack computes the IP header already, the only time we 891 * need the hardware to recompute it is in the case of TSO. 892 */ 893 if (skb_is_gso(skb)) 894 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 895 } else if (l3.v6->version == 6) { 896 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 897 HNS3_L3T_IPV6); 898 } 899 900 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 901 l2_len = l3.hdr - l2_hdr; 902 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 903 904 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 905 l3_len = l4.hdr - l3.hdr; 906 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 907 908 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 909 switch (l4_proto) { 910 case IPPROTO_TCP: 911 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 913 HNS3_L4T_TCP); 914 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 915 l4.tcp->doff); 916 break; 917 case IPPROTO_UDP: 918 if (hns3_tunnel_csum_bug(skb)) 919 break; 920 921 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 922 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 923 HNS3_L4T_UDP); 924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 925 (sizeof(struct udphdr) >> 2)); 926 break; 927 case IPPROTO_SCTP: 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 930 HNS3_L4T_SCTP); 931 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 932 (sizeof(struct sctphdr) >> 2)); 933 break; 934 default: 935 /* drop the skb tunnel packet if hardware don't support, 936 * because hardware can't calculate csum when TSO. 937 */ 938 if (skb_is_gso(skb)) 939 return -EDOM; 940 941 /* the stack computes the IP header already, 942 * driver calculate l4 checksum when not TSO. 943 */ 944 skb_checksum_help(skb); 945 return 0; 946 } 947 948 return 0; 949 } 950 951 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 952 struct sk_buff *skb) 953 { 954 struct hnae3_handle *handle = tx_ring->tqp->handle; 955 struct vlan_ethhdr *vhdr; 956 int rc; 957 958 if (!(skb->protocol == htons(ETH_P_8021Q) || 959 skb_vlan_tag_present(skb))) 960 return 0; 961 962 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 963 * header is allowed in skb, otherwise it will cause RAS error. 964 */ 965 if (unlikely(skb_vlan_tagged_multi(skb) && 966 handle->port_base_vlan_state == 967 HNAE3_PORT_BASE_VLAN_ENABLE)) 968 return -EINVAL; 969 970 if (skb->protocol == htons(ETH_P_8021Q) && 971 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 972 /* When HW VLAN acceleration is turned off, and the stack 973 * sets the protocol to 802.1q, the driver just need to 974 * set the protocol to the encapsulated ethertype. 975 */ 976 skb->protocol = vlan_get_protocol(skb); 977 return 0; 978 } 979 980 if (skb_vlan_tag_present(skb)) { 981 /* Based on hw strategy, use out_vtag in two layer tag case, 982 * and use inner_vtag in one tag case. 983 */ 984 if (skb->protocol == htons(ETH_P_8021Q) && 985 handle->port_base_vlan_state == 986 HNAE3_PORT_BASE_VLAN_DISABLE) 987 rc = HNS3_OUTER_VLAN_TAG; 988 else 989 rc = HNS3_INNER_VLAN_TAG; 990 991 skb->protocol = vlan_get_protocol(skb); 992 return rc; 993 } 994 995 rc = skb_cow_head(skb, 0); 996 if (unlikely(rc < 0)) 997 return rc; 998 999 vhdr = (struct vlan_ethhdr *)skb->data; 1000 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1001 & VLAN_PRIO_MASK); 1002 1003 skb->protocol = vlan_get_protocol(skb); 1004 return 0; 1005 } 1006 1007 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1008 struct sk_buff *skb, struct hns3_desc *desc) 1009 { 1010 u32 ol_type_vlan_len_msec = 0; 1011 u32 type_cs_vlan_tso = 0; 1012 u32 paylen = skb->len; 1013 u16 inner_vtag = 0; 1014 u16 out_vtag = 0; 1015 u16 mss = 0; 1016 int ret; 1017 1018 ret = hns3_handle_vtags(ring, skb); 1019 if (unlikely(ret < 0)) { 1020 u64_stats_update_begin(&ring->syncp); 1021 ring->stats.tx_vlan_err++; 1022 u64_stats_update_end(&ring->syncp); 1023 return ret; 1024 } else if (ret == HNS3_INNER_VLAN_TAG) { 1025 inner_vtag = skb_vlan_tag_get(skb); 1026 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1027 VLAN_PRIO_MASK; 1028 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1029 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1030 out_vtag = skb_vlan_tag_get(skb); 1031 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1032 VLAN_PRIO_MASK; 1033 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1034 1); 1035 } 1036 1037 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1038 u8 ol4_proto, il4_proto; 1039 1040 skb_reset_mac_len(skb); 1041 1042 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1043 if (unlikely(ret < 0)) { 1044 u64_stats_update_begin(&ring->syncp); 1045 ring->stats.tx_l4_proto_err++; 1046 u64_stats_update_end(&ring->syncp); 1047 return ret; 1048 } 1049 1050 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1051 &type_cs_vlan_tso, 1052 &ol_type_vlan_len_msec); 1053 if (unlikely(ret < 0)) { 1054 u64_stats_update_begin(&ring->syncp); 1055 ring->stats.tx_l2l3l4_err++; 1056 u64_stats_update_end(&ring->syncp); 1057 return ret; 1058 } 1059 1060 ret = hns3_set_tso(skb, &paylen, &mss, 1061 &type_cs_vlan_tso); 1062 if (unlikely(ret < 0)) { 1063 u64_stats_update_begin(&ring->syncp); 1064 ring->stats.tx_tso_err++; 1065 u64_stats_update_end(&ring->syncp); 1066 return ret; 1067 } 1068 } 1069 1070 /* Set txbd */ 1071 desc->tx.ol_type_vlan_len_msec = 1072 cpu_to_le32(ol_type_vlan_len_msec); 1073 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1074 desc->tx.paylen = cpu_to_le32(paylen); 1075 desc->tx.mss = cpu_to_le16(mss); 1076 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1077 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1078 1079 return 0; 1080 } 1081 1082 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1083 unsigned int size, enum hns_desc_type type) 1084 { 1085 #define HNS3_LIKELY_BD_NUM 1 1086 1087 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1088 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1089 struct device *dev = ring_to_dev(ring); 1090 skb_frag_t *frag; 1091 unsigned int frag_buf_num; 1092 int k, sizeoflast; 1093 dma_addr_t dma; 1094 1095 if (type == DESC_TYPE_FRAGLIST_SKB || 1096 type == DESC_TYPE_SKB) { 1097 struct sk_buff *skb = (struct sk_buff *)priv; 1098 1099 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1100 } else { 1101 frag = (skb_frag_t *)priv; 1102 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1103 } 1104 1105 if (unlikely(dma_mapping_error(dev, dma))) { 1106 u64_stats_update_begin(&ring->syncp); 1107 ring->stats.sw_err_cnt++; 1108 u64_stats_update_end(&ring->syncp); 1109 return -ENOMEM; 1110 } 1111 1112 desc_cb->priv = priv; 1113 desc_cb->length = size; 1114 desc_cb->dma = dma; 1115 desc_cb->type = type; 1116 1117 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1118 desc->addr = cpu_to_le64(dma); 1119 desc->tx.send_size = cpu_to_le16(size); 1120 desc->tx.bdtp_fe_sc_vld_ra_ri = 1121 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1122 1123 trace_hns3_tx_desc(ring, ring->next_to_use); 1124 ring_ptr_move_fw(ring, next_to_use); 1125 return HNS3_LIKELY_BD_NUM; 1126 } 1127 1128 frag_buf_num = hns3_tx_bd_count(size); 1129 sizeoflast = size % HNS3_MAX_BD_SIZE; 1130 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1131 1132 /* When frag size is bigger than hardware limit, split this frag */ 1133 for (k = 0; k < frag_buf_num; k++) { 1134 /* now, fill the descriptor */ 1135 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1136 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1137 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1138 desc->tx.bdtp_fe_sc_vld_ra_ri = 1139 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1140 1141 trace_hns3_tx_desc(ring, ring->next_to_use); 1142 /* move ring pointer to next */ 1143 ring_ptr_move_fw(ring, next_to_use); 1144 1145 desc = &ring->desc[ring->next_to_use]; 1146 } 1147 1148 return frag_buf_num; 1149 } 1150 1151 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1152 unsigned int bd_num) 1153 { 1154 unsigned int size; 1155 int i; 1156 1157 size = skb_headlen(skb); 1158 while (size > HNS3_MAX_BD_SIZE) { 1159 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1160 size -= HNS3_MAX_BD_SIZE; 1161 1162 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1163 return bd_num; 1164 } 1165 1166 if (size) { 1167 bd_size[bd_num++] = size; 1168 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1169 return bd_num; 1170 } 1171 1172 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1173 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1174 size = skb_frag_size(frag); 1175 if (!size) 1176 continue; 1177 1178 while (size > HNS3_MAX_BD_SIZE) { 1179 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1180 size -= HNS3_MAX_BD_SIZE; 1181 1182 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1183 return bd_num; 1184 } 1185 1186 bd_size[bd_num++] = size; 1187 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1188 return bd_num; 1189 } 1190 1191 return bd_num; 1192 } 1193 1194 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1195 u8 max_non_tso_bd_num) 1196 { 1197 struct sk_buff *frag_skb; 1198 unsigned int bd_num = 0; 1199 1200 /* If the total len is within the max bd limit */ 1201 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1202 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1203 return skb_shinfo(skb)->nr_frags + 1U; 1204 1205 /* The below case will always be linearized, return 1206 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1207 */ 1208 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1209 (!skb_is_gso(skb) && skb->len > 1210 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num)))) 1211 return HNS3_MAX_TSO_BD_NUM + 1U; 1212 1213 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1214 1215 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1216 return bd_num; 1217 1218 skb_walk_frags(skb, frag_skb) { 1219 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1220 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1221 return bd_num; 1222 } 1223 1224 return bd_num; 1225 } 1226 1227 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1228 { 1229 if (!skb->encapsulation) 1230 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1231 1232 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1233 } 1234 1235 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1236 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1237 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1238 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1239 * than MSS except the last max_non_tso_bd_num - 1 frags. 1240 */ 1241 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1242 unsigned int bd_num, u8 max_non_tso_bd_num) 1243 { 1244 unsigned int tot_len = 0; 1245 int i; 1246 1247 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1248 tot_len += bd_size[i]; 1249 1250 /* ensure the first max_non_tso_bd_num frags is greater than 1251 * mss + header 1252 */ 1253 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1254 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1255 return true; 1256 1257 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1258 * than mss except the last one. 1259 */ 1260 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1261 tot_len -= bd_size[i]; 1262 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1263 1264 if (tot_len < skb_shinfo(skb)->gso_size) 1265 return true; 1266 } 1267 1268 return false; 1269 } 1270 1271 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1272 { 1273 int i; 1274 1275 for (i = 0; i < MAX_SKB_FRAGS; i++) 1276 size[i] = skb_frag_size(&shinfo->frags[i]); 1277 } 1278 1279 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1280 struct net_device *netdev, 1281 struct sk_buff *skb) 1282 { 1283 struct hns3_nic_priv *priv = netdev_priv(netdev); 1284 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1285 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1286 unsigned int bd_num; 1287 1288 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num); 1289 if (unlikely(bd_num > max_non_tso_bd_num)) { 1290 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1291 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1292 max_non_tso_bd_num)) { 1293 trace_hns3_over_max_bd(skb); 1294 goto out; 1295 } 1296 1297 if (__skb_linearize(skb)) 1298 return -ENOMEM; 1299 1300 bd_num = hns3_tx_bd_count(skb->len); 1301 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1302 (!skb_is_gso(skb) && 1303 bd_num > max_non_tso_bd_num)) { 1304 trace_hns3_over_max_bd(skb); 1305 return -ENOMEM; 1306 } 1307 1308 u64_stats_update_begin(&ring->syncp); 1309 ring->stats.tx_copy++; 1310 u64_stats_update_end(&ring->syncp); 1311 } 1312 1313 out: 1314 if (likely(ring_space(ring) >= bd_num)) 1315 return bd_num; 1316 1317 netif_stop_subqueue(netdev, ring->queue_index); 1318 smp_mb(); /* Memory barrier before checking ring_space */ 1319 1320 /* Start queue in case hns3_clean_tx_ring has just made room 1321 * available and has not seen the queue stopped state performed 1322 * by netif_stop_subqueue above. 1323 */ 1324 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1325 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1326 netif_start_subqueue(netdev, ring->queue_index); 1327 return bd_num; 1328 } 1329 1330 return -EBUSY; 1331 } 1332 1333 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1334 { 1335 struct device *dev = ring_to_dev(ring); 1336 unsigned int i; 1337 1338 for (i = 0; i < ring->desc_num; i++) { 1339 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1340 1341 memset(desc, 0, sizeof(*desc)); 1342 1343 /* check if this is where we started */ 1344 if (ring->next_to_use == next_to_use_orig) 1345 break; 1346 1347 /* rollback one */ 1348 ring_ptr_move_bw(ring, next_to_use); 1349 1350 if (!ring->desc_cb[ring->next_to_use].dma) 1351 continue; 1352 1353 /* unmap the descriptor dma address */ 1354 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1355 ring->desc_cb[ring->next_to_use].type == 1356 DESC_TYPE_FRAGLIST_SKB) 1357 dma_unmap_single(dev, 1358 ring->desc_cb[ring->next_to_use].dma, 1359 ring->desc_cb[ring->next_to_use].length, 1360 DMA_TO_DEVICE); 1361 else if (ring->desc_cb[ring->next_to_use].length) 1362 dma_unmap_page(dev, 1363 ring->desc_cb[ring->next_to_use].dma, 1364 ring->desc_cb[ring->next_to_use].length, 1365 DMA_TO_DEVICE); 1366 1367 ring->desc_cb[ring->next_to_use].length = 0; 1368 ring->desc_cb[ring->next_to_use].dma = 0; 1369 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1370 } 1371 } 1372 1373 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1374 struct sk_buff *skb, enum hns_desc_type type) 1375 { 1376 unsigned int size = skb_headlen(skb); 1377 int i, ret, bd_num = 0; 1378 1379 if (size) { 1380 ret = hns3_fill_desc(ring, skb, size, type); 1381 if (unlikely(ret < 0)) 1382 return ret; 1383 1384 bd_num += ret; 1385 } 1386 1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1388 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1389 1390 size = skb_frag_size(frag); 1391 if (!size) 1392 continue; 1393 1394 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1395 if (unlikely(ret < 0)) 1396 return ret; 1397 1398 bd_num += ret; 1399 } 1400 1401 return bd_num; 1402 } 1403 1404 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1405 bool doorbell) 1406 { 1407 ring->pending_buf += num; 1408 1409 if (!doorbell) { 1410 u64_stats_update_begin(&ring->syncp); 1411 ring->stats.tx_more++; 1412 u64_stats_update_end(&ring->syncp); 1413 return; 1414 } 1415 1416 if (!ring->pending_buf) 1417 return; 1418 1419 writel(ring->pending_buf, 1420 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1421 ring->pending_buf = 0; 1422 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1423 } 1424 1425 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1426 { 1427 struct hns3_nic_priv *priv = netdev_priv(netdev); 1428 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1429 struct netdev_queue *dev_queue; 1430 int pre_ntu, next_to_use_head; 1431 struct sk_buff *frag_skb; 1432 int bd_num = 0; 1433 bool doorbell; 1434 int ret; 1435 1436 /* Hardware can only handle short frames above 32 bytes */ 1437 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1438 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1439 return NETDEV_TX_OK; 1440 } 1441 1442 /* Prefetch the data used later */ 1443 prefetch(skb->data); 1444 1445 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1446 if (unlikely(ret <= 0)) { 1447 if (ret == -EBUSY) { 1448 u64_stats_update_begin(&ring->syncp); 1449 ring->stats.tx_busy++; 1450 u64_stats_update_end(&ring->syncp); 1451 hns3_tx_doorbell(ring, 0, true); 1452 return NETDEV_TX_BUSY; 1453 } else if (ret == -ENOMEM) { 1454 u64_stats_update_begin(&ring->syncp); 1455 ring->stats.sw_err_cnt++; 1456 u64_stats_update_end(&ring->syncp); 1457 } 1458 1459 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1460 goto out_err_tx_ok; 1461 } 1462 1463 next_to_use_head = ring->next_to_use; 1464 1465 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use]); 1466 if (unlikely(ret < 0)) 1467 goto fill_err; 1468 1469 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1470 if (unlikely(ret < 0)) 1471 goto fill_err; 1472 1473 bd_num += ret; 1474 1475 skb_walk_frags(skb, frag_skb) { 1476 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1477 DESC_TYPE_FRAGLIST_SKB); 1478 if (unlikely(ret < 0)) 1479 goto fill_err; 1480 1481 bd_num += ret; 1482 } 1483 1484 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1485 (ring->desc_num - 1); 1486 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1487 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1488 trace_hns3_tx_desc(ring, pre_ntu); 1489 1490 /* Complete translate all packets */ 1491 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1492 doorbell = __netdev_tx_sent_queue(dev_queue, skb->len, 1493 netdev_xmit_more()); 1494 hns3_tx_doorbell(ring, bd_num, doorbell); 1495 1496 return NETDEV_TX_OK; 1497 1498 fill_err: 1499 hns3_clear_desc(ring, next_to_use_head); 1500 1501 out_err_tx_ok: 1502 dev_kfree_skb_any(skb); 1503 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1504 return NETDEV_TX_OK; 1505 } 1506 1507 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1508 { 1509 struct hnae3_handle *h = hns3_get_handle(netdev); 1510 struct sockaddr *mac_addr = p; 1511 int ret; 1512 1513 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1514 return -EADDRNOTAVAIL; 1515 1516 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1517 netdev_info(netdev, "already using mac address %pM\n", 1518 mac_addr->sa_data); 1519 return 0; 1520 } 1521 1522 /* For VF device, if there is a perm_addr, then the user will not 1523 * be allowed to change the address. 1524 */ 1525 if (!hns3_is_phys_func(h->pdev) && 1526 !is_zero_ether_addr(netdev->perm_addr)) { 1527 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1528 netdev->perm_addr, mac_addr->sa_data); 1529 return -EPERM; 1530 } 1531 1532 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1533 if (ret) { 1534 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1535 return ret; 1536 } 1537 1538 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1539 1540 return 0; 1541 } 1542 1543 static int hns3_nic_do_ioctl(struct net_device *netdev, 1544 struct ifreq *ifr, int cmd) 1545 { 1546 struct hnae3_handle *h = hns3_get_handle(netdev); 1547 1548 if (!netif_running(netdev)) 1549 return -EINVAL; 1550 1551 if (!h->ae_algo->ops->do_ioctl) 1552 return -EOPNOTSUPP; 1553 1554 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1555 } 1556 1557 static int hns3_nic_set_features(struct net_device *netdev, 1558 netdev_features_t features) 1559 { 1560 netdev_features_t changed = netdev->features ^ features; 1561 struct hns3_nic_priv *priv = netdev_priv(netdev); 1562 struct hnae3_handle *h = priv->ae_handle; 1563 bool enable; 1564 int ret; 1565 1566 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1567 enable = !!(features & NETIF_F_GRO_HW); 1568 ret = h->ae_algo->ops->set_gro_en(h, enable); 1569 if (ret) 1570 return ret; 1571 } 1572 1573 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1574 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1575 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1576 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1577 if (ret) 1578 return ret; 1579 } 1580 1581 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1582 enable = !!(features & NETIF_F_NTUPLE); 1583 h->ae_algo->ops->enable_fd(h, enable); 1584 } 1585 1586 netdev->features = features; 1587 return 0; 1588 } 1589 1590 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1591 struct net_device *dev, 1592 netdev_features_t features) 1593 { 1594 #define HNS3_MAX_HDR_LEN 480U 1595 #define HNS3_MAX_L4_HDR_LEN 60U 1596 1597 size_t len; 1598 1599 if (skb->ip_summed != CHECKSUM_PARTIAL) 1600 return features; 1601 1602 if (skb->encapsulation) 1603 len = skb_inner_transport_header(skb) - skb->data; 1604 else 1605 len = skb_transport_header(skb) - skb->data; 1606 1607 /* Assume L4 is 60 byte as TCP is the only protocol with a 1608 * a flexible value, and it's max len is 60 bytes. 1609 */ 1610 len += HNS3_MAX_L4_HDR_LEN; 1611 1612 /* Hardware only supports checksum on the skb with a max header 1613 * len of 480 bytes. 1614 */ 1615 if (len > HNS3_MAX_HDR_LEN) 1616 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1617 1618 return features; 1619 } 1620 1621 static void hns3_nic_get_stats64(struct net_device *netdev, 1622 struct rtnl_link_stats64 *stats) 1623 { 1624 struct hns3_nic_priv *priv = netdev_priv(netdev); 1625 int queue_num = priv->ae_handle->kinfo.num_tqps; 1626 struct hnae3_handle *handle = priv->ae_handle; 1627 struct hns3_enet_ring *ring; 1628 u64 rx_length_errors = 0; 1629 u64 rx_crc_errors = 0; 1630 u64 rx_multicast = 0; 1631 unsigned int start; 1632 u64 tx_errors = 0; 1633 u64 rx_errors = 0; 1634 unsigned int idx; 1635 u64 tx_bytes = 0; 1636 u64 rx_bytes = 0; 1637 u64 tx_pkts = 0; 1638 u64 rx_pkts = 0; 1639 u64 tx_drop = 0; 1640 u64 rx_drop = 0; 1641 1642 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1643 return; 1644 1645 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1646 1647 for (idx = 0; idx < queue_num; idx++) { 1648 /* fetch the tx stats */ 1649 ring = &priv->ring[idx]; 1650 do { 1651 start = u64_stats_fetch_begin_irq(&ring->syncp); 1652 tx_bytes += ring->stats.tx_bytes; 1653 tx_pkts += ring->stats.tx_pkts; 1654 tx_drop += ring->stats.sw_err_cnt; 1655 tx_drop += ring->stats.tx_vlan_err; 1656 tx_drop += ring->stats.tx_l4_proto_err; 1657 tx_drop += ring->stats.tx_l2l3l4_err; 1658 tx_drop += ring->stats.tx_tso_err; 1659 tx_errors += ring->stats.sw_err_cnt; 1660 tx_errors += ring->stats.tx_vlan_err; 1661 tx_errors += ring->stats.tx_l4_proto_err; 1662 tx_errors += ring->stats.tx_l2l3l4_err; 1663 tx_errors += ring->stats.tx_tso_err; 1664 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1665 1666 /* fetch the rx stats */ 1667 ring = &priv->ring[idx + queue_num]; 1668 do { 1669 start = u64_stats_fetch_begin_irq(&ring->syncp); 1670 rx_bytes += ring->stats.rx_bytes; 1671 rx_pkts += ring->stats.rx_pkts; 1672 rx_drop += ring->stats.l2_err; 1673 rx_errors += ring->stats.l2_err; 1674 rx_errors += ring->stats.l3l4_csum_err; 1675 rx_crc_errors += ring->stats.l2_err; 1676 rx_multicast += ring->stats.rx_multicast; 1677 rx_length_errors += ring->stats.err_pkt_len; 1678 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1679 } 1680 1681 stats->tx_bytes = tx_bytes; 1682 stats->tx_packets = tx_pkts; 1683 stats->rx_bytes = rx_bytes; 1684 stats->rx_packets = rx_pkts; 1685 1686 stats->rx_errors = rx_errors; 1687 stats->multicast = rx_multicast; 1688 stats->rx_length_errors = rx_length_errors; 1689 stats->rx_crc_errors = rx_crc_errors; 1690 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1691 1692 stats->tx_errors = tx_errors; 1693 stats->rx_dropped = rx_drop; 1694 stats->tx_dropped = tx_drop; 1695 stats->collisions = netdev->stats.collisions; 1696 stats->rx_over_errors = netdev->stats.rx_over_errors; 1697 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1698 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1699 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1700 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1701 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1702 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1703 stats->tx_window_errors = netdev->stats.tx_window_errors; 1704 stats->rx_compressed = netdev->stats.rx_compressed; 1705 stats->tx_compressed = netdev->stats.tx_compressed; 1706 } 1707 1708 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1709 { 1710 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1711 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1712 struct hnae3_knic_private_info *kinfo; 1713 u8 tc = mqprio_qopt->qopt.num_tc; 1714 u16 mode = mqprio_qopt->mode; 1715 u8 hw = mqprio_qopt->qopt.hw; 1716 struct hnae3_handle *h; 1717 1718 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1719 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1720 return -EOPNOTSUPP; 1721 1722 if (tc > HNAE3_MAX_TC) 1723 return -EINVAL; 1724 1725 if (!netdev) 1726 return -EINVAL; 1727 1728 h = hns3_get_handle(netdev); 1729 kinfo = &h->kinfo; 1730 1731 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1732 1733 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1734 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP; 1735 } 1736 1737 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1738 void *type_data) 1739 { 1740 if (type != TC_SETUP_QDISC_MQPRIO) 1741 return -EOPNOTSUPP; 1742 1743 return hns3_setup_tc(dev, type_data); 1744 } 1745 1746 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1747 __be16 proto, u16 vid) 1748 { 1749 struct hnae3_handle *h = hns3_get_handle(netdev); 1750 int ret = -EIO; 1751 1752 if (h->ae_algo->ops->set_vlan_filter) 1753 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1754 1755 return ret; 1756 } 1757 1758 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1759 __be16 proto, u16 vid) 1760 { 1761 struct hnae3_handle *h = hns3_get_handle(netdev); 1762 int ret = -EIO; 1763 1764 if (h->ae_algo->ops->set_vlan_filter) 1765 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1766 1767 return ret; 1768 } 1769 1770 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1771 u8 qos, __be16 vlan_proto) 1772 { 1773 struct hnae3_handle *h = hns3_get_handle(netdev); 1774 int ret = -EIO; 1775 1776 netif_dbg(h, drv, netdev, 1777 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1778 vf, vlan, qos, ntohs(vlan_proto)); 1779 1780 if (h->ae_algo->ops->set_vf_vlan_filter) 1781 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1782 qos, vlan_proto); 1783 1784 return ret; 1785 } 1786 1787 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1788 { 1789 struct hnae3_handle *handle = hns3_get_handle(netdev); 1790 1791 if (hns3_nic_resetting(netdev)) 1792 return -EBUSY; 1793 1794 if (!handle->ae_algo->ops->set_vf_spoofchk) 1795 return -EOPNOTSUPP; 1796 1797 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1798 } 1799 1800 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1801 { 1802 struct hnae3_handle *handle = hns3_get_handle(netdev); 1803 1804 if (!handle->ae_algo->ops->set_vf_trust) 1805 return -EOPNOTSUPP; 1806 1807 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1808 } 1809 1810 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1811 { 1812 struct hnae3_handle *h = hns3_get_handle(netdev); 1813 int ret; 1814 1815 if (hns3_nic_resetting(netdev)) 1816 return -EBUSY; 1817 1818 if (!h->ae_algo->ops->set_mtu) 1819 return -EOPNOTSUPP; 1820 1821 netif_dbg(h, drv, netdev, 1822 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1823 1824 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1825 if (ret) 1826 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1827 ret); 1828 else 1829 netdev->mtu = new_mtu; 1830 1831 return ret; 1832 } 1833 1834 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1835 { 1836 struct hns3_nic_priv *priv = netdev_priv(ndev); 1837 struct hnae3_handle *h = hns3_get_handle(ndev); 1838 struct hns3_enet_ring *tx_ring; 1839 struct napi_struct *napi; 1840 int timeout_queue = 0; 1841 int hw_head, hw_tail; 1842 int fbd_num, fbd_oft; 1843 int ebd_num, ebd_oft; 1844 int bd_num, bd_err; 1845 int ring_en, tc; 1846 int i; 1847 1848 /* Find the stopped queue the same way the stack does */ 1849 for (i = 0; i < ndev->num_tx_queues; i++) { 1850 struct netdev_queue *q; 1851 unsigned long trans_start; 1852 1853 q = netdev_get_tx_queue(ndev, i); 1854 trans_start = q->trans_start; 1855 if (netif_xmit_stopped(q) && 1856 time_after(jiffies, 1857 (trans_start + ndev->watchdog_timeo))) { 1858 timeout_queue = i; 1859 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1860 q->state, 1861 jiffies_to_msecs(jiffies - trans_start)); 1862 break; 1863 } 1864 } 1865 1866 if (i == ndev->num_tx_queues) { 1867 netdev_info(ndev, 1868 "no netdev TX timeout queue found, timeout count: %llu\n", 1869 priv->tx_timeout_count); 1870 return false; 1871 } 1872 1873 priv->tx_timeout_count++; 1874 1875 tx_ring = &priv->ring[timeout_queue]; 1876 napi = &tx_ring->tqp_vector->napi; 1877 1878 netdev_info(ndev, 1879 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1880 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1881 tx_ring->next_to_clean, napi->state); 1882 1883 netdev_info(ndev, 1884 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 1885 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1886 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 1887 1888 netdev_info(ndev, 1889 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 1890 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 1891 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1892 1893 /* When mac received many pause frames continuous, it's unable to send 1894 * packets, which may cause tx timeout 1895 */ 1896 if (h->ae_algo->ops->get_mac_stats) { 1897 struct hns3_mac_stats mac_stats; 1898 1899 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1900 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1901 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1902 } 1903 1904 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1905 HNS3_RING_TX_RING_HEAD_REG); 1906 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1907 HNS3_RING_TX_RING_TAIL_REG); 1908 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1909 HNS3_RING_TX_RING_FBDNUM_REG); 1910 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1911 HNS3_RING_TX_RING_OFFSET_REG); 1912 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1913 HNS3_RING_TX_RING_EBDNUM_REG); 1914 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1915 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1916 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1917 HNS3_RING_TX_RING_BD_NUM_REG); 1918 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1919 HNS3_RING_TX_RING_BD_ERR_REG); 1920 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1921 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1922 1923 netdev_info(ndev, 1924 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1925 bd_num, hw_head, hw_tail, bd_err, 1926 readl(tx_ring->tqp_vector->mask_addr)); 1927 netdev_info(ndev, 1928 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1929 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1930 1931 return true; 1932 } 1933 1934 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 1935 { 1936 struct hns3_nic_priv *priv = netdev_priv(ndev); 1937 struct hnae3_handle *h = priv->ae_handle; 1938 1939 if (!hns3_get_tx_timeo_queue_info(ndev)) 1940 return; 1941 1942 /* request the reset, and let the hclge to determine 1943 * which reset level should be done 1944 */ 1945 if (h->ae_algo->ops->reset_event) 1946 h->ae_algo->ops->reset_event(h->pdev, h); 1947 } 1948 1949 #ifdef CONFIG_RFS_ACCEL 1950 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1951 u16 rxq_index, u32 flow_id) 1952 { 1953 struct hnae3_handle *h = hns3_get_handle(dev); 1954 struct flow_keys fkeys; 1955 1956 if (!h->ae_algo->ops->add_arfs_entry) 1957 return -EOPNOTSUPP; 1958 1959 if (skb->encapsulation) 1960 return -EPROTONOSUPPORT; 1961 1962 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1963 return -EPROTONOSUPPORT; 1964 1965 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1966 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1967 (fkeys.basic.ip_proto != IPPROTO_TCP && 1968 fkeys.basic.ip_proto != IPPROTO_UDP)) 1969 return -EPROTONOSUPPORT; 1970 1971 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1972 } 1973 #endif 1974 1975 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 1976 struct ifla_vf_info *ivf) 1977 { 1978 struct hnae3_handle *h = hns3_get_handle(ndev); 1979 1980 if (!h->ae_algo->ops->get_vf_config) 1981 return -EOPNOTSUPP; 1982 1983 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 1984 } 1985 1986 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 1987 int link_state) 1988 { 1989 struct hnae3_handle *h = hns3_get_handle(ndev); 1990 1991 if (!h->ae_algo->ops->set_vf_link_state) 1992 return -EOPNOTSUPP; 1993 1994 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 1995 } 1996 1997 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 1998 int min_tx_rate, int max_tx_rate) 1999 { 2000 struct hnae3_handle *h = hns3_get_handle(ndev); 2001 2002 if (!h->ae_algo->ops->set_vf_rate) 2003 return -EOPNOTSUPP; 2004 2005 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2006 false); 2007 } 2008 2009 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2010 { 2011 struct hnae3_handle *h = hns3_get_handle(netdev); 2012 2013 if (!h->ae_algo->ops->set_vf_mac) 2014 return -EOPNOTSUPP; 2015 2016 if (is_multicast_ether_addr(mac)) { 2017 netdev_err(netdev, 2018 "Invalid MAC:%pM specified. Could not set MAC\n", 2019 mac); 2020 return -EINVAL; 2021 } 2022 2023 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2024 } 2025 2026 static const struct net_device_ops hns3_nic_netdev_ops = { 2027 .ndo_open = hns3_nic_net_open, 2028 .ndo_stop = hns3_nic_net_stop, 2029 .ndo_start_xmit = hns3_nic_net_xmit, 2030 .ndo_tx_timeout = hns3_nic_net_timeout, 2031 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2032 .ndo_do_ioctl = hns3_nic_do_ioctl, 2033 .ndo_change_mtu = hns3_nic_change_mtu, 2034 .ndo_set_features = hns3_nic_set_features, 2035 .ndo_features_check = hns3_features_check, 2036 .ndo_get_stats64 = hns3_nic_get_stats64, 2037 .ndo_setup_tc = hns3_nic_setup_tc, 2038 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2039 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2040 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2041 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2042 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2043 .ndo_set_vf_trust = hns3_set_vf_trust, 2044 #ifdef CONFIG_RFS_ACCEL 2045 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2046 #endif 2047 .ndo_get_vf_config = hns3_nic_get_vf_config, 2048 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2049 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2050 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2051 }; 2052 2053 bool hns3_is_phys_func(struct pci_dev *pdev) 2054 { 2055 u32 dev_id = pdev->device; 2056 2057 switch (dev_id) { 2058 case HNAE3_DEV_ID_GE: 2059 case HNAE3_DEV_ID_25GE: 2060 case HNAE3_DEV_ID_25GE_RDMA: 2061 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2062 case HNAE3_DEV_ID_50GE_RDMA: 2063 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2064 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2065 case HNAE3_DEV_ID_200G_RDMA: 2066 return true; 2067 case HNAE3_DEV_ID_VF: 2068 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2069 return false; 2070 default: 2071 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2072 dev_id); 2073 } 2074 2075 return false; 2076 } 2077 2078 static void hns3_disable_sriov(struct pci_dev *pdev) 2079 { 2080 /* If our VFs are assigned we cannot shut down SR-IOV 2081 * without causing issues, so just leave the hardware 2082 * available but disabled 2083 */ 2084 if (pci_vfs_assigned(pdev)) { 2085 dev_warn(&pdev->dev, 2086 "disabling driver while VFs are assigned\n"); 2087 return; 2088 } 2089 2090 pci_disable_sriov(pdev); 2091 } 2092 2093 /* hns3_probe - Device initialization routine 2094 * @pdev: PCI device information struct 2095 * @ent: entry in hns3_pci_tbl 2096 * 2097 * hns3_probe initializes a PF identified by a pci_dev structure. 2098 * The OS initialization, configuring of the PF private structure, 2099 * and a hardware reset occur. 2100 * 2101 * Returns 0 on success, negative on failure 2102 */ 2103 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2104 { 2105 struct hnae3_ae_dev *ae_dev; 2106 int ret; 2107 2108 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2109 if (!ae_dev) 2110 return -ENOMEM; 2111 2112 ae_dev->pdev = pdev; 2113 ae_dev->flag = ent->driver_data; 2114 pci_set_drvdata(pdev, ae_dev); 2115 2116 ret = hnae3_register_ae_dev(ae_dev); 2117 if (ret) 2118 pci_set_drvdata(pdev, NULL); 2119 2120 return ret; 2121 } 2122 2123 /* hns3_remove - Device removal routine 2124 * @pdev: PCI device information struct 2125 */ 2126 static void hns3_remove(struct pci_dev *pdev) 2127 { 2128 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2129 2130 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2131 hns3_disable_sriov(pdev); 2132 2133 hnae3_unregister_ae_dev(ae_dev); 2134 pci_set_drvdata(pdev, NULL); 2135 } 2136 2137 /** 2138 * hns3_pci_sriov_configure 2139 * @pdev: pointer to a pci_dev structure 2140 * @num_vfs: number of VFs to allocate 2141 * 2142 * Enable or change the number of VFs. Called when the user updates the number 2143 * of VFs in sysfs. 2144 **/ 2145 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2146 { 2147 int ret; 2148 2149 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2150 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2151 return -EINVAL; 2152 } 2153 2154 if (num_vfs) { 2155 ret = pci_enable_sriov(pdev, num_vfs); 2156 if (ret) 2157 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2158 else 2159 return num_vfs; 2160 } else if (!pci_vfs_assigned(pdev)) { 2161 pci_disable_sriov(pdev); 2162 } else { 2163 dev_warn(&pdev->dev, 2164 "Unable to free VFs because some are assigned to VMs.\n"); 2165 } 2166 2167 return 0; 2168 } 2169 2170 static void hns3_shutdown(struct pci_dev *pdev) 2171 { 2172 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2173 2174 hnae3_unregister_ae_dev(ae_dev); 2175 pci_set_drvdata(pdev, NULL); 2176 2177 if (system_state == SYSTEM_POWER_OFF) 2178 pci_set_power_state(pdev, PCI_D3hot); 2179 } 2180 2181 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2182 pci_channel_state_t state) 2183 { 2184 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2185 pci_ers_result_t ret; 2186 2187 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2188 2189 if (state == pci_channel_io_perm_failure) 2190 return PCI_ERS_RESULT_DISCONNECT; 2191 2192 if (!ae_dev || !ae_dev->ops) { 2193 dev_err(&pdev->dev, 2194 "Can't recover - error happened before device initialized\n"); 2195 return PCI_ERS_RESULT_NONE; 2196 } 2197 2198 if (ae_dev->ops->handle_hw_ras_error) 2199 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2200 else 2201 return PCI_ERS_RESULT_NONE; 2202 2203 return ret; 2204 } 2205 2206 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2207 { 2208 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2209 const struct hnae3_ae_ops *ops; 2210 enum hnae3_reset_type reset_type; 2211 struct device *dev = &pdev->dev; 2212 2213 if (!ae_dev || !ae_dev->ops) 2214 return PCI_ERS_RESULT_NONE; 2215 2216 ops = ae_dev->ops; 2217 /* request the reset */ 2218 if (ops->reset_event && ops->get_reset_level && 2219 ops->set_default_reset_request) { 2220 if (ae_dev->hw_err_reset_req) { 2221 reset_type = ops->get_reset_level(ae_dev, 2222 &ae_dev->hw_err_reset_req); 2223 ops->set_default_reset_request(ae_dev, reset_type); 2224 dev_info(dev, "requesting reset due to PCI error\n"); 2225 ops->reset_event(pdev, NULL); 2226 } 2227 2228 return PCI_ERS_RESULT_RECOVERED; 2229 } 2230 2231 return PCI_ERS_RESULT_DISCONNECT; 2232 } 2233 2234 static void hns3_reset_prepare(struct pci_dev *pdev) 2235 { 2236 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2237 2238 dev_info(&pdev->dev, "FLR prepare\n"); 2239 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2240 ae_dev->ops->flr_prepare(ae_dev); 2241 } 2242 2243 static void hns3_reset_done(struct pci_dev *pdev) 2244 { 2245 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2246 2247 dev_info(&pdev->dev, "FLR done\n"); 2248 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2249 ae_dev->ops->flr_done(ae_dev); 2250 } 2251 2252 static const struct pci_error_handlers hns3_err_handler = { 2253 .error_detected = hns3_error_detected, 2254 .slot_reset = hns3_slot_reset, 2255 .reset_prepare = hns3_reset_prepare, 2256 .reset_done = hns3_reset_done, 2257 }; 2258 2259 static struct pci_driver hns3_driver = { 2260 .name = hns3_driver_name, 2261 .id_table = hns3_pci_tbl, 2262 .probe = hns3_probe, 2263 .remove = hns3_remove, 2264 .shutdown = hns3_shutdown, 2265 .sriov_configure = hns3_pci_sriov_configure, 2266 .err_handler = &hns3_err_handler, 2267 }; 2268 2269 /* set default feature to hns3 */ 2270 static void hns3_set_default_feature(struct net_device *netdev) 2271 { 2272 struct hnae3_handle *h = hns3_get_handle(netdev); 2273 struct pci_dev *pdev = h->pdev; 2274 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2275 2276 netdev->priv_flags |= IFF_UNICAST_FLT; 2277 2278 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2279 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2280 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2281 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2282 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2283 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2284 2285 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2286 2287 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2288 NETIF_F_HW_VLAN_CTAG_FILTER | 2289 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2290 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2291 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2292 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2293 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2294 NETIF_F_FRAGLIST; 2295 2296 netdev->vlan_features |= 2297 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2298 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2299 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2300 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2301 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2302 NETIF_F_FRAGLIST; 2303 2304 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2305 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2306 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2307 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2308 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2309 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2310 NETIF_F_FRAGLIST; 2311 2312 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2313 netdev->hw_features |= NETIF_F_GRO_HW; 2314 netdev->features |= NETIF_F_GRO_HW; 2315 2316 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2317 netdev->hw_features |= NETIF_F_NTUPLE; 2318 netdev->features |= NETIF_F_NTUPLE; 2319 } 2320 } 2321 2322 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2323 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2324 netdev->features |= NETIF_F_GSO_UDP_L4; 2325 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2326 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2327 } 2328 } 2329 2330 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2331 struct hns3_desc_cb *cb) 2332 { 2333 unsigned int order = hns3_page_order(ring); 2334 struct page *p; 2335 2336 p = dev_alloc_pages(order); 2337 if (!p) 2338 return -ENOMEM; 2339 2340 cb->priv = p; 2341 cb->page_offset = 0; 2342 cb->reuse_flag = 0; 2343 cb->buf = page_address(p); 2344 cb->length = hns3_page_size(ring); 2345 cb->type = DESC_TYPE_PAGE; 2346 page_ref_add(p, USHRT_MAX - 1); 2347 cb->pagecnt_bias = USHRT_MAX; 2348 2349 return 0; 2350 } 2351 2352 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2353 struct hns3_desc_cb *cb, int budget) 2354 { 2355 if (cb->type == DESC_TYPE_SKB) 2356 napi_consume_skb(cb->priv, budget); 2357 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2358 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2359 memset(cb, 0, sizeof(*cb)); 2360 } 2361 2362 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2363 { 2364 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2365 cb->length, ring_to_dma_dir(ring)); 2366 2367 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2368 return -EIO; 2369 2370 return 0; 2371 } 2372 2373 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2374 struct hns3_desc_cb *cb) 2375 { 2376 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2377 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2378 ring_to_dma_dir(ring)); 2379 else if (cb->length) 2380 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2381 ring_to_dma_dir(ring)); 2382 } 2383 2384 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2385 { 2386 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2387 ring->desc[i].addr = 0; 2388 } 2389 2390 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2391 int budget) 2392 { 2393 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2394 2395 if (!ring->desc_cb[i].dma) 2396 return; 2397 2398 hns3_buffer_detach(ring, i); 2399 hns3_free_buffer(ring, cb, budget); 2400 } 2401 2402 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2403 { 2404 int i; 2405 2406 for (i = 0; i < ring->desc_num; i++) 2407 hns3_free_buffer_detach(ring, i, 0); 2408 } 2409 2410 /* free desc along with its attached buffer */ 2411 static void hns3_free_desc(struct hns3_enet_ring *ring) 2412 { 2413 int size = ring->desc_num * sizeof(ring->desc[0]); 2414 2415 hns3_free_buffers(ring); 2416 2417 if (ring->desc) { 2418 dma_free_coherent(ring_to_dev(ring), size, 2419 ring->desc, ring->desc_dma_addr); 2420 ring->desc = NULL; 2421 } 2422 } 2423 2424 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2425 { 2426 int size = ring->desc_num * sizeof(ring->desc[0]); 2427 2428 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2429 &ring->desc_dma_addr, GFP_KERNEL); 2430 if (!ring->desc) 2431 return -ENOMEM; 2432 2433 return 0; 2434 } 2435 2436 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2437 struct hns3_desc_cb *cb) 2438 { 2439 int ret; 2440 2441 ret = hns3_alloc_buffer(ring, cb); 2442 if (ret) 2443 goto out; 2444 2445 ret = hns3_map_buffer(ring, cb); 2446 if (ret) 2447 goto out_with_buf; 2448 2449 return 0; 2450 2451 out_with_buf: 2452 hns3_free_buffer(ring, cb, 0); 2453 out: 2454 return ret; 2455 } 2456 2457 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2458 { 2459 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2460 2461 if (ret) 2462 return ret; 2463 2464 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2465 2466 return 0; 2467 } 2468 2469 /* Allocate memory for raw pkg, and map with dma */ 2470 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2471 { 2472 int i, j, ret; 2473 2474 for (i = 0; i < ring->desc_num; i++) { 2475 ret = hns3_alloc_and_attach_buffer(ring, i); 2476 if (ret) 2477 goto out_buffer_fail; 2478 } 2479 2480 return 0; 2481 2482 out_buffer_fail: 2483 for (j = i - 1; j >= 0; j--) 2484 hns3_free_buffer_detach(ring, j, 0); 2485 return ret; 2486 } 2487 2488 /* detach a in-used buffer and replace with a reserved one */ 2489 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2490 struct hns3_desc_cb *res_cb) 2491 { 2492 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2493 ring->desc_cb[i] = *res_cb; 2494 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2495 ring->desc[i].rx.bd_base_info = 0; 2496 } 2497 2498 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2499 { 2500 ring->desc_cb[i].reuse_flag = 0; 2501 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2502 ring->desc_cb[i].page_offset); 2503 ring->desc[i].rx.bd_base_info = 0; 2504 2505 dma_sync_single_for_device(ring_to_dev(ring), 2506 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 2507 hns3_buf_size(ring), 2508 DMA_FROM_DEVICE); 2509 } 2510 2511 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 2512 int *bytes, int *pkts, int budget) 2513 { 2514 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 2515 * smp_store_release() is not used in hns3_tx_doorbell() because 2516 * the doorbell operation already have the needed barrier operation. 2517 */ 2518 int ltu = smp_load_acquire(&ring->last_to_use); 2519 int ntc = ring->next_to_clean; 2520 struct hns3_desc_cb *desc_cb; 2521 bool reclaimed = false; 2522 struct hns3_desc *desc; 2523 2524 while (ltu != ntc) { 2525 desc = &ring->desc[ntc]; 2526 2527 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 2528 BIT(HNS3_TXD_VLD_B)) 2529 break; 2530 2531 desc_cb = &ring->desc_cb[ntc]; 2532 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2533 (*bytes) += desc_cb->length; 2534 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2535 hns3_free_buffer_detach(ring, ntc, budget); 2536 2537 if (++ntc == ring->desc_num) 2538 ntc = 0; 2539 2540 /* Issue prefetch for next Tx descriptor */ 2541 prefetch(&ring->desc_cb[ntc]); 2542 reclaimed = true; 2543 } 2544 2545 if (unlikely(!reclaimed)) 2546 return false; 2547 2548 /* This smp_store_release() pairs with smp_load_acquire() in 2549 * ring_space called by hns3_nic_net_xmit. 2550 */ 2551 smp_store_release(&ring->next_to_clean, ntc); 2552 return true; 2553 } 2554 2555 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 2556 { 2557 struct net_device *netdev = ring_to_netdev(ring); 2558 struct hns3_nic_priv *priv = netdev_priv(netdev); 2559 struct netdev_queue *dev_queue; 2560 int bytes, pkts; 2561 2562 bytes = 0; 2563 pkts = 0; 2564 2565 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 2566 return; 2567 2568 ring->tqp_vector->tx_group.total_bytes += bytes; 2569 ring->tqp_vector->tx_group.total_packets += pkts; 2570 2571 u64_stats_update_begin(&ring->syncp); 2572 ring->stats.tx_bytes += bytes; 2573 ring->stats.tx_pkts += pkts; 2574 u64_stats_update_end(&ring->syncp); 2575 2576 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2577 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2578 2579 if (unlikely(netif_carrier_ok(netdev) && 2580 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2581 /* Make sure that anybody stopping the queue after this 2582 * sees the new next_to_clean. 2583 */ 2584 smp_mb(); 2585 if (netif_tx_queue_stopped(dev_queue) && 2586 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2587 netif_tx_wake_queue(dev_queue); 2588 ring->stats.restart_queue++; 2589 } 2590 } 2591 } 2592 2593 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2594 { 2595 int ntc = ring->next_to_clean; 2596 int ntu = ring->next_to_use; 2597 2598 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2599 } 2600 2601 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2602 int cleand_count) 2603 { 2604 struct hns3_desc_cb *desc_cb; 2605 struct hns3_desc_cb res_cbs; 2606 int i, ret; 2607 2608 for (i = 0; i < cleand_count; i++) { 2609 desc_cb = &ring->desc_cb[ring->next_to_use]; 2610 if (desc_cb->reuse_flag) { 2611 u64_stats_update_begin(&ring->syncp); 2612 ring->stats.reuse_pg_cnt++; 2613 u64_stats_update_end(&ring->syncp); 2614 2615 hns3_reuse_buffer(ring, ring->next_to_use); 2616 } else { 2617 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 2618 if (ret) { 2619 u64_stats_update_begin(&ring->syncp); 2620 ring->stats.sw_err_cnt++; 2621 u64_stats_update_end(&ring->syncp); 2622 2623 hns3_rl_err(ring_to_netdev(ring), 2624 "alloc rx buffer failed: %d\n", 2625 ret); 2626 break; 2627 } 2628 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2629 2630 u64_stats_update_begin(&ring->syncp); 2631 ring->stats.non_reuse_pg++; 2632 u64_stats_update_end(&ring->syncp); 2633 } 2634 2635 ring_ptr_move_fw(ring, next_to_use); 2636 } 2637 2638 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2639 } 2640 2641 static bool hns3_page_is_reusable(struct page *page) 2642 { 2643 return page_to_nid(page) == numa_mem_id() && 2644 !page_is_pfmemalloc(page); 2645 } 2646 2647 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 2648 { 2649 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 2650 } 2651 2652 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2653 struct hns3_enet_ring *ring, int pull_len, 2654 struct hns3_desc_cb *desc_cb) 2655 { 2656 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2657 int size = le16_to_cpu(desc->rx.size); 2658 u32 truesize = hns3_buf_size(ring); 2659 2660 desc_cb->pagecnt_bias--; 2661 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2662 size - pull_len, truesize); 2663 2664 /* Avoid re-using remote pages, or the stack is still using the page 2665 * when page_offset rollback to zero, flag default unreuse 2666 */ 2667 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) || 2668 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 2669 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2670 return; 2671 } 2672 2673 /* Move offset up to the next cache line */ 2674 desc_cb->page_offset += truesize; 2675 2676 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2677 desc_cb->reuse_flag = 1; 2678 } else if (hns3_can_reuse_page(desc_cb)) { 2679 desc_cb->reuse_flag = 1; 2680 desc_cb->page_offset = 0; 2681 } else if (desc_cb->pagecnt_bias) { 2682 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 2683 return; 2684 } 2685 2686 if (unlikely(!desc_cb->pagecnt_bias)) { 2687 page_ref_add(desc_cb->priv, USHRT_MAX); 2688 desc_cb->pagecnt_bias = USHRT_MAX; 2689 } 2690 } 2691 2692 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2693 { 2694 __be16 type = skb->protocol; 2695 struct tcphdr *th; 2696 int depth = 0; 2697 2698 while (eth_type_vlan(type)) { 2699 struct vlan_hdr *vh; 2700 2701 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2702 return -EFAULT; 2703 2704 vh = (struct vlan_hdr *)(skb->data + depth); 2705 type = vh->h_vlan_encapsulated_proto; 2706 depth += VLAN_HLEN; 2707 } 2708 2709 skb_set_network_header(skb, depth); 2710 2711 if (type == htons(ETH_P_IP)) { 2712 const struct iphdr *iph = ip_hdr(skb); 2713 2714 depth += sizeof(struct iphdr); 2715 skb_set_transport_header(skb, depth); 2716 th = tcp_hdr(skb); 2717 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2718 iph->daddr, 0); 2719 } else if (type == htons(ETH_P_IPV6)) { 2720 const struct ipv6hdr *iph = ipv6_hdr(skb); 2721 2722 depth += sizeof(struct ipv6hdr); 2723 skb_set_transport_header(skb, depth); 2724 th = tcp_hdr(skb); 2725 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2726 &iph->daddr, 0); 2727 } else { 2728 hns3_rl_err(skb->dev, 2729 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2730 be16_to_cpu(type), depth); 2731 return -EFAULT; 2732 } 2733 2734 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2735 if (th->cwr) 2736 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2737 2738 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2739 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2740 2741 skb->csum_start = (unsigned char *)th - skb->head; 2742 skb->csum_offset = offsetof(struct tcphdr, check); 2743 skb->ip_summed = CHECKSUM_PARTIAL; 2744 2745 trace_hns3_gro(skb); 2746 2747 return 0; 2748 } 2749 2750 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2751 u32 l234info, u32 bd_base_info, u32 ol_info) 2752 { 2753 struct net_device *netdev = ring_to_netdev(ring); 2754 int l3_type, l4_type; 2755 int ol4_type; 2756 2757 skb->ip_summed = CHECKSUM_NONE; 2758 2759 skb_checksum_none_assert(skb); 2760 2761 if (!(netdev->features & NETIF_F_RXCSUM)) 2762 return; 2763 2764 /* check if hardware has done checksum */ 2765 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2766 return; 2767 2768 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2769 BIT(HNS3_RXD_OL3E_B) | 2770 BIT(HNS3_RXD_OL4E_B)))) { 2771 u64_stats_update_begin(&ring->syncp); 2772 ring->stats.l3l4_csum_err++; 2773 u64_stats_update_end(&ring->syncp); 2774 2775 return; 2776 } 2777 2778 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2779 HNS3_RXD_OL4ID_S); 2780 switch (ol4_type) { 2781 case HNS3_OL4_TYPE_MAC_IN_UDP: 2782 case HNS3_OL4_TYPE_NVGRE: 2783 skb->csum_level = 1; 2784 fallthrough; 2785 case HNS3_OL4_TYPE_NO_TUN: 2786 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2787 HNS3_RXD_L3ID_S); 2788 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2789 HNS3_RXD_L4ID_S); 2790 2791 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2792 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2793 l3_type == HNS3_L3_TYPE_IPV6) && 2794 (l4_type == HNS3_L4_TYPE_UDP || 2795 l4_type == HNS3_L4_TYPE_TCP || 2796 l4_type == HNS3_L4_TYPE_SCTP)) 2797 skb->ip_summed = CHECKSUM_UNNECESSARY; 2798 break; 2799 default: 2800 break; 2801 } 2802 } 2803 2804 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2805 { 2806 if (skb_has_frag_list(skb)) 2807 napi_gro_flush(&ring->tqp_vector->napi, false); 2808 2809 napi_gro_receive(&ring->tqp_vector->napi, skb); 2810 } 2811 2812 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2813 struct hns3_desc *desc, u32 l234info, 2814 u16 *vlan_tag) 2815 { 2816 struct hnae3_handle *handle = ring->tqp->handle; 2817 struct pci_dev *pdev = ring->tqp->handle->pdev; 2818 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2819 2820 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 2821 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2822 if (!(*vlan_tag & VLAN_VID_MASK)) 2823 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2824 2825 return (*vlan_tag != 0); 2826 } 2827 2828 #define HNS3_STRP_OUTER_VLAN 0x1 2829 #define HNS3_STRP_INNER_VLAN 0x2 2830 #define HNS3_STRP_BOTH 0x3 2831 2832 /* Hardware always insert VLAN tag into RX descriptor when 2833 * remove the tag from packet, driver needs to determine 2834 * reporting which tag to stack. 2835 */ 2836 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2837 HNS3_RXD_STRP_TAGP_S)) { 2838 case HNS3_STRP_OUTER_VLAN: 2839 if (handle->port_base_vlan_state != 2840 HNAE3_PORT_BASE_VLAN_DISABLE) 2841 return false; 2842 2843 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2844 return true; 2845 case HNS3_STRP_INNER_VLAN: 2846 if (handle->port_base_vlan_state != 2847 HNAE3_PORT_BASE_VLAN_DISABLE) 2848 return false; 2849 2850 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2851 return true; 2852 case HNS3_STRP_BOTH: 2853 if (handle->port_base_vlan_state == 2854 HNAE3_PORT_BASE_VLAN_DISABLE) 2855 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2856 else 2857 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2858 2859 return true; 2860 default: 2861 return false; 2862 } 2863 } 2864 2865 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 2866 { 2867 ring->desc[ring->next_to_clean].rx.bd_base_info &= 2868 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 2869 ring->next_to_clean += 1; 2870 2871 if (unlikely(ring->next_to_clean == ring->desc_num)) 2872 ring->next_to_clean = 0; 2873 } 2874 2875 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2876 unsigned char *va) 2877 { 2878 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2879 struct net_device *netdev = ring_to_netdev(ring); 2880 struct sk_buff *skb; 2881 2882 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2883 skb = ring->skb; 2884 if (unlikely(!skb)) { 2885 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2886 2887 u64_stats_update_begin(&ring->syncp); 2888 ring->stats.sw_err_cnt++; 2889 u64_stats_update_end(&ring->syncp); 2890 2891 return -ENOMEM; 2892 } 2893 2894 trace_hns3_rx_desc(ring); 2895 prefetchw(skb->data); 2896 2897 ring->pending_buf = 1; 2898 ring->frag_num = 0; 2899 ring->tail_skb = NULL; 2900 if (length <= HNS3_RX_HEAD_SIZE) { 2901 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2902 2903 /* We can reuse buffer as-is, just make sure it is local */ 2904 if (likely(hns3_page_is_reusable(desc_cb->priv))) 2905 desc_cb->reuse_flag = 1; 2906 else /* This page cannot be reused so discard it */ 2907 __page_frag_cache_drain(desc_cb->priv, 2908 desc_cb->pagecnt_bias); 2909 2910 hns3_rx_ring_move_fw(ring); 2911 return 0; 2912 } 2913 u64_stats_update_begin(&ring->syncp); 2914 ring->stats.seg_pkt_cnt++; 2915 u64_stats_update_end(&ring->syncp); 2916 2917 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2918 __skb_put(skb, ring->pull_len); 2919 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2920 desc_cb); 2921 hns3_rx_ring_move_fw(ring); 2922 2923 return 0; 2924 } 2925 2926 static int hns3_add_frag(struct hns3_enet_ring *ring) 2927 { 2928 struct sk_buff *skb = ring->skb; 2929 struct sk_buff *head_skb = skb; 2930 struct sk_buff *new_skb; 2931 struct hns3_desc_cb *desc_cb; 2932 struct hns3_desc *desc; 2933 u32 bd_base_info; 2934 2935 do { 2936 desc = &ring->desc[ring->next_to_clean]; 2937 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2938 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2939 /* make sure HW write desc complete */ 2940 dma_rmb(); 2941 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2942 return -ENXIO; 2943 2944 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2945 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2946 if (unlikely(!new_skb)) { 2947 hns3_rl_err(ring_to_netdev(ring), 2948 "alloc rx fraglist skb fail\n"); 2949 return -ENXIO; 2950 } 2951 ring->frag_num = 0; 2952 2953 if (ring->tail_skb) { 2954 ring->tail_skb->next = new_skb; 2955 ring->tail_skb = new_skb; 2956 } else { 2957 skb_shinfo(skb)->frag_list = new_skb; 2958 ring->tail_skb = new_skb; 2959 } 2960 } 2961 2962 if (ring->tail_skb) { 2963 head_skb->truesize += hns3_buf_size(ring); 2964 head_skb->data_len += le16_to_cpu(desc->rx.size); 2965 head_skb->len += le16_to_cpu(desc->rx.size); 2966 skb = ring->tail_skb; 2967 } 2968 2969 dma_sync_single_for_cpu(ring_to_dev(ring), 2970 desc_cb->dma + desc_cb->page_offset, 2971 hns3_buf_size(ring), 2972 DMA_FROM_DEVICE); 2973 2974 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2975 trace_hns3_rx_desc(ring); 2976 hns3_rx_ring_move_fw(ring); 2977 ring->pending_buf++; 2978 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 2979 2980 return 0; 2981 } 2982 2983 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2984 struct sk_buff *skb, u32 l234info, 2985 u32 bd_base_info, u32 ol_info) 2986 { 2987 u32 l3_type; 2988 2989 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2990 HNS3_RXD_GRO_SIZE_M, 2991 HNS3_RXD_GRO_SIZE_S); 2992 /* if there is no HW GRO, do not set gro params */ 2993 if (!skb_shinfo(skb)->gso_size) { 2994 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2995 return 0; 2996 } 2997 2998 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2999 HNS3_RXD_GRO_COUNT_M, 3000 HNS3_RXD_GRO_COUNT_S); 3001 3002 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 3003 if (l3_type == HNS3_L3_TYPE_IPV4) 3004 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3005 else if (l3_type == HNS3_L3_TYPE_IPV6) 3006 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3007 else 3008 return -EFAULT; 3009 3010 return hns3_gro_complete(skb, l234info); 3011 } 3012 3013 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3014 struct sk_buff *skb, u32 rss_hash) 3015 { 3016 struct hnae3_handle *handle = ring->tqp->handle; 3017 enum pkt_hash_types rss_type; 3018 3019 if (rss_hash) 3020 rss_type = handle->kinfo.rss_type; 3021 else 3022 rss_type = PKT_HASH_TYPE_NONE; 3023 3024 skb_set_hash(skb, rss_hash, rss_type); 3025 } 3026 3027 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3028 { 3029 struct net_device *netdev = ring_to_netdev(ring); 3030 enum hns3_pkt_l2t_type l2_frame_type; 3031 u32 bd_base_info, l234info, ol_info; 3032 struct hns3_desc *desc; 3033 unsigned int len; 3034 int pre_ntc, ret; 3035 3036 /* bdinfo handled below is only valid on the last BD of the 3037 * current packet, and ring->next_to_clean indicates the first 3038 * descriptor of next packet, so need - 1 below. 3039 */ 3040 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3041 (ring->desc_num - 1); 3042 desc = &ring->desc[pre_ntc]; 3043 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3044 l234info = le32_to_cpu(desc->rx.l234_info); 3045 ol_info = le32_to_cpu(desc->rx.ol_info); 3046 3047 /* Based on hw strategy, the tag offloaded will be stored at 3048 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3049 * in one layer tag case. 3050 */ 3051 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3052 u16 vlan_tag; 3053 3054 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3055 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3056 vlan_tag); 3057 } 3058 3059 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3060 BIT(HNS3_RXD_L2E_B))))) { 3061 u64_stats_update_begin(&ring->syncp); 3062 if (l234info & BIT(HNS3_RXD_L2E_B)) 3063 ring->stats.l2_err++; 3064 else 3065 ring->stats.err_pkt_len++; 3066 u64_stats_update_end(&ring->syncp); 3067 3068 return -EFAULT; 3069 } 3070 3071 len = skb->len; 3072 3073 /* Do update ip stack process */ 3074 skb->protocol = eth_type_trans(skb, netdev); 3075 3076 /* This is needed in order to enable forwarding support */ 3077 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3078 bd_base_info, ol_info); 3079 if (unlikely(ret)) { 3080 u64_stats_update_begin(&ring->syncp); 3081 ring->stats.rx_err_cnt++; 3082 u64_stats_update_end(&ring->syncp); 3083 return ret; 3084 } 3085 3086 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3087 HNS3_RXD_DMAC_S); 3088 3089 u64_stats_update_begin(&ring->syncp); 3090 ring->stats.rx_pkts++; 3091 ring->stats.rx_bytes += len; 3092 3093 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3094 ring->stats.rx_multicast++; 3095 3096 u64_stats_update_end(&ring->syncp); 3097 3098 ring->tqp_vector->rx_group.total_bytes += len; 3099 3100 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3101 return 0; 3102 } 3103 3104 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3105 { 3106 struct sk_buff *skb = ring->skb; 3107 struct hns3_desc_cb *desc_cb; 3108 struct hns3_desc *desc; 3109 unsigned int length; 3110 u32 bd_base_info; 3111 int ret; 3112 3113 desc = &ring->desc[ring->next_to_clean]; 3114 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3115 3116 prefetch(desc); 3117 3118 if (!skb) { 3119 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3120 3121 /* Check valid BD */ 3122 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3123 return -ENXIO; 3124 3125 dma_rmb(); 3126 length = le16_to_cpu(desc->rx.size); 3127 3128 ring->va = desc_cb->buf + desc_cb->page_offset; 3129 3130 dma_sync_single_for_cpu(ring_to_dev(ring), 3131 desc_cb->dma + desc_cb->page_offset, 3132 hns3_buf_size(ring), 3133 DMA_FROM_DEVICE); 3134 3135 /* Prefetch first cache line of first page. 3136 * Idea is to cache few bytes of the header of the packet. 3137 * Our L1 Cache line size is 64B so need to prefetch twice to make 3138 * it 128B. But in actual we can have greater size of caches with 3139 * 128B Level 1 cache lines. In such a case, single fetch would 3140 * suffice to cache in the relevant part of the header. 3141 */ 3142 net_prefetch(ring->va); 3143 3144 ret = hns3_alloc_skb(ring, length, ring->va); 3145 skb = ring->skb; 3146 3147 if (ret < 0) /* alloc buffer fail */ 3148 return ret; 3149 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3150 ret = hns3_add_frag(ring); 3151 if (ret) 3152 return ret; 3153 } 3154 } else { 3155 ret = hns3_add_frag(ring); 3156 if (ret) 3157 return ret; 3158 } 3159 3160 /* As the head data may be changed when GRO enable, copy 3161 * the head data in after other data rx completed 3162 */ 3163 if (skb->len > HNS3_RX_HEAD_SIZE) 3164 memcpy(skb->data, ring->va, 3165 ALIGN(ring->pull_len, sizeof(long))); 3166 3167 ret = hns3_handle_bdinfo(ring, skb); 3168 if (unlikely(ret)) { 3169 dev_kfree_skb_any(skb); 3170 return ret; 3171 } 3172 3173 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3174 return 0; 3175 } 3176 3177 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3178 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3179 { 3180 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3181 int unused_count = hns3_desc_unused(ring); 3182 int recv_pkts = 0; 3183 int err; 3184 3185 unused_count -= ring->pending_buf; 3186 3187 while (recv_pkts < budget) { 3188 /* Reuse or realloc buffers */ 3189 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3190 hns3_nic_alloc_rx_buffers(ring, unused_count); 3191 unused_count = hns3_desc_unused(ring) - 3192 ring->pending_buf; 3193 } 3194 3195 /* Poll one pkt */ 3196 err = hns3_handle_rx_bd(ring); 3197 /* Do not get FE for the packet or failed to alloc skb */ 3198 if (unlikely(!ring->skb || err == -ENXIO)) { 3199 goto out; 3200 } else if (likely(!err)) { 3201 rx_fn(ring, ring->skb); 3202 recv_pkts++; 3203 } 3204 3205 unused_count += ring->pending_buf; 3206 ring->skb = NULL; 3207 ring->pending_buf = 0; 3208 } 3209 3210 out: 3211 /* Make all data has been write before submit */ 3212 if (unused_count > 0) 3213 hns3_nic_alloc_rx_buffers(ring, unused_count); 3214 3215 return recv_pkts; 3216 } 3217 3218 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3219 { 3220 #define HNS3_RX_LOW_BYTE_RATE 10000 3221 #define HNS3_RX_MID_BYTE_RATE 20000 3222 #define HNS3_RX_ULTRA_PACKET_RATE 40 3223 3224 enum hns3_flow_level_range new_flow_level; 3225 struct hns3_enet_tqp_vector *tqp_vector; 3226 int packets_per_msecs, bytes_per_msecs; 3227 u32 time_passed_ms; 3228 3229 tqp_vector = ring_group->ring->tqp_vector; 3230 time_passed_ms = 3231 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3232 if (!time_passed_ms) 3233 return false; 3234 3235 do_div(ring_group->total_packets, time_passed_ms); 3236 packets_per_msecs = ring_group->total_packets; 3237 3238 do_div(ring_group->total_bytes, time_passed_ms); 3239 bytes_per_msecs = ring_group->total_bytes; 3240 3241 new_flow_level = ring_group->coal.flow_level; 3242 3243 /* Simple throttlerate management 3244 * 0-10MB/s lower (50000 ints/s) 3245 * 10-20MB/s middle (20000 ints/s) 3246 * 20-1249MB/s high (18000 ints/s) 3247 * > 40000pps ultra (8000 ints/s) 3248 */ 3249 switch (new_flow_level) { 3250 case HNS3_FLOW_LOW: 3251 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3252 new_flow_level = HNS3_FLOW_MID; 3253 break; 3254 case HNS3_FLOW_MID: 3255 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3256 new_flow_level = HNS3_FLOW_HIGH; 3257 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3258 new_flow_level = HNS3_FLOW_LOW; 3259 break; 3260 case HNS3_FLOW_HIGH: 3261 case HNS3_FLOW_ULTRA: 3262 default: 3263 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3264 new_flow_level = HNS3_FLOW_MID; 3265 break; 3266 } 3267 3268 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3269 &tqp_vector->rx_group == ring_group) 3270 new_flow_level = HNS3_FLOW_ULTRA; 3271 3272 ring_group->total_bytes = 0; 3273 ring_group->total_packets = 0; 3274 ring_group->coal.flow_level = new_flow_level; 3275 3276 return true; 3277 } 3278 3279 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3280 { 3281 struct hns3_enet_tqp_vector *tqp_vector; 3282 u16 new_int_gl; 3283 3284 if (!ring_group->ring) 3285 return false; 3286 3287 tqp_vector = ring_group->ring->tqp_vector; 3288 if (!tqp_vector->last_jiffies) 3289 return false; 3290 3291 if (ring_group->total_packets == 0) { 3292 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3293 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3294 return true; 3295 } 3296 3297 if (!hns3_get_new_flow_lvl(ring_group)) 3298 return false; 3299 3300 new_int_gl = ring_group->coal.int_gl; 3301 switch (ring_group->coal.flow_level) { 3302 case HNS3_FLOW_LOW: 3303 new_int_gl = HNS3_INT_GL_50K; 3304 break; 3305 case HNS3_FLOW_MID: 3306 new_int_gl = HNS3_INT_GL_20K; 3307 break; 3308 case HNS3_FLOW_HIGH: 3309 new_int_gl = HNS3_INT_GL_18K; 3310 break; 3311 case HNS3_FLOW_ULTRA: 3312 new_int_gl = HNS3_INT_GL_8K; 3313 break; 3314 default: 3315 break; 3316 } 3317 3318 if (new_int_gl != ring_group->coal.int_gl) { 3319 ring_group->coal.int_gl = new_int_gl; 3320 return true; 3321 } 3322 return false; 3323 } 3324 3325 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3326 { 3327 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3328 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3329 bool rx_update, tx_update; 3330 3331 /* update param every 1000ms */ 3332 if (time_before(jiffies, 3333 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3334 return; 3335 3336 if (rx_group->coal.gl_adapt_enable) { 3337 rx_update = hns3_get_new_int_gl(rx_group); 3338 if (rx_update) 3339 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3340 rx_group->coal.int_gl); 3341 } 3342 3343 if (tx_group->coal.gl_adapt_enable) { 3344 tx_update = hns3_get_new_int_gl(tx_group); 3345 if (tx_update) 3346 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3347 tx_group->coal.int_gl); 3348 } 3349 3350 tqp_vector->last_jiffies = jiffies; 3351 } 3352 3353 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3354 { 3355 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3356 struct hns3_enet_ring *ring; 3357 int rx_pkt_total = 0; 3358 3359 struct hns3_enet_tqp_vector *tqp_vector = 3360 container_of(napi, struct hns3_enet_tqp_vector, napi); 3361 bool clean_complete = true; 3362 int rx_budget = budget; 3363 3364 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3365 napi_complete(napi); 3366 return 0; 3367 } 3368 3369 /* Since the actual Tx work is minimal, we can give the Tx a larger 3370 * budget and be more aggressive about cleaning up the Tx descriptors. 3371 */ 3372 hns3_for_each_ring(ring, tqp_vector->tx_group) 3373 hns3_clean_tx_ring(ring, budget); 3374 3375 /* make sure rx ring budget not smaller than 1 */ 3376 if (tqp_vector->num_tqps > 1) 3377 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3378 3379 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3380 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3381 hns3_rx_skb); 3382 3383 if (rx_cleaned >= rx_budget) 3384 clean_complete = false; 3385 3386 rx_pkt_total += rx_cleaned; 3387 } 3388 3389 tqp_vector->rx_group.total_packets += rx_pkt_total; 3390 3391 if (!clean_complete) 3392 return budget; 3393 3394 if (napi_complete(napi) && 3395 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3396 hns3_update_new_int_gl(tqp_vector); 3397 hns3_mask_vector_irq(tqp_vector, 1); 3398 } 3399 3400 return rx_pkt_total; 3401 } 3402 3403 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3404 struct hnae3_ring_chain_node *head) 3405 { 3406 struct pci_dev *pdev = tqp_vector->handle->pdev; 3407 struct hnae3_ring_chain_node *cur_chain = head; 3408 struct hnae3_ring_chain_node *chain; 3409 struct hns3_enet_ring *tx_ring; 3410 struct hns3_enet_ring *rx_ring; 3411 3412 tx_ring = tqp_vector->tx_group.ring; 3413 if (tx_ring) { 3414 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3415 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3416 HNAE3_RING_TYPE_TX); 3417 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3418 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3419 3420 cur_chain->next = NULL; 3421 3422 while (tx_ring->next) { 3423 tx_ring = tx_ring->next; 3424 3425 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3426 GFP_KERNEL); 3427 if (!chain) 3428 goto err_free_chain; 3429 3430 cur_chain->next = chain; 3431 chain->tqp_index = tx_ring->tqp->tqp_index; 3432 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3433 HNAE3_RING_TYPE_TX); 3434 hnae3_set_field(chain->int_gl_idx, 3435 HNAE3_RING_GL_IDX_M, 3436 HNAE3_RING_GL_IDX_S, 3437 HNAE3_RING_GL_TX); 3438 3439 cur_chain = chain; 3440 } 3441 } 3442 3443 rx_ring = tqp_vector->rx_group.ring; 3444 if (!tx_ring && rx_ring) { 3445 cur_chain->next = NULL; 3446 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3447 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3448 HNAE3_RING_TYPE_RX); 3449 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3450 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3451 3452 rx_ring = rx_ring->next; 3453 } 3454 3455 while (rx_ring) { 3456 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3457 if (!chain) 3458 goto err_free_chain; 3459 3460 cur_chain->next = chain; 3461 chain->tqp_index = rx_ring->tqp->tqp_index; 3462 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3463 HNAE3_RING_TYPE_RX); 3464 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3465 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3466 3467 cur_chain = chain; 3468 3469 rx_ring = rx_ring->next; 3470 } 3471 3472 return 0; 3473 3474 err_free_chain: 3475 cur_chain = head->next; 3476 while (cur_chain) { 3477 chain = cur_chain->next; 3478 devm_kfree(&pdev->dev, cur_chain); 3479 cur_chain = chain; 3480 } 3481 head->next = NULL; 3482 3483 return -ENOMEM; 3484 } 3485 3486 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3487 struct hnae3_ring_chain_node *head) 3488 { 3489 struct pci_dev *pdev = tqp_vector->handle->pdev; 3490 struct hnae3_ring_chain_node *chain_tmp, *chain; 3491 3492 chain = head->next; 3493 3494 while (chain) { 3495 chain_tmp = chain->next; 3496 devm_kfree(&pdev->dev, chain); 3497 chain = chain_tmp; 3498 } 3499 } 3500 3501 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3502 struct hns3_enet_ring *ring) 3503 { 3504 ring->next = group->ring; 3505 group->ring = ring; 3506 3507 group->count++; 3508 } 3509 3510 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3511 { 3512 struct pci_dev *pdev = priv->ae_handle->pdev; 3513 struct hns3_enet_tqp_vector *tqp_vector; 3514 int num_vectors = priv->vector_num; 3515 int numa_node; 3516 int vector_i; 3517 3518 numa_node = dev_to_node(&pdev->dev); 3519 3520 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3521 tqp_vector = &priv->tqp_vector[vector_i]; 3522 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3523 &tqp_vector->affinity_mask); 3524 } 3525 } 3526 3527 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3528 { 3529 struct hnae3_ring_chain_node vector_ring_chain; 3530 struct hnae3_handle *h = priv->ae_handle; 3531 struct hns3_enet_tqp_vector *tqp_vector; 3532 int ret; 3533 int i; 3534 3535 hns3_nic_set_cpumask(priv); 3536 3537 for (i = 0; i < priv->vector_num; i++) { 3538 tqp_vector = &priv->tqp_vector[i]; 3539 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3540 tqp_vector->num_tqps = 0; 3541 } 3542 3543 for (i = 0; i < h->kinfo.num_tqps; i++) { 3544 u16 vector_i = i % priv->vector_num; 3545 u16 tqp_num = h->kinfo.num_tqps; 3546 3547 tqp_vector = &priv->tqp_vector[vector_i]; 3548 3549 hns3_add_ring_to_group(&tqp_vector->tx_group, 3550 &priv->ring[i]); 3551 3552 hns3_add_ring_to_group(&tqp_vector->rx_group, 3553 &priv->ring[i + tqp_num]); 3554 3555 priv->ring[i].tqp_vector = tqp_vector; 3556 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3557 tqp_vector->num_tqps++; 3558 } 3559 3560 for (i = 0; i < priv->vector_num; i++) { 3561 tqp_vector = &priv->tqp_vector[i]; 3562 3563 tqp_vector->rx_group.total_bytes = 0; 3564 tqp_vector->rx_group.total_packets = 0; 3565 tqp_vector->tx_group.total_bytes = 0; 3566 tqp_vector->tx_group.total_packets = 0; 3567 tqp_vector->handle = h; 3568 3569 ret = hns3_get_vector_ring_chain(tqp_vector, 3570 &vector_ring_chain); 3571 if (ret) 3572 goto map_ring_fail; 3573 3574 ret = h->ae_algo->ops->map_ring_to_vector(h, 3575 tqp_vector->vector_irq, &vector_ring_chain); 3576 3577 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3578 3579 if (ret) 3580 goto map_ring_fail; 3581 3582 netif_napi_add(priv->netdev, &tqp_vector->napi, 3583 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3584 } 3585 3586 return 0; 3587 3588 map_ring_fail: 3589 while (i--) 3590 netif_napi_del(&priv->tqp_vector[i].napi); 3591 3592 return ret; 3593 } 3594 3595 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3596 { 3597 #define HNS3_VECTOR_PF_MAX_NUM 64 3598 3599 struct hnae3_handle *h = priv->ae_handle; 3600 struct hns3_enet_tqp_vector *tqp_vector; 3601 struct hnae3_vector_info *vector; 3602 struct pci_dev *pdev = h->pdev; 3603 u16 tqp_num = h->kinfo.num_tqps; 3604 u16 vector_num; 3605 int ret = 0; 3606 u16 i; 3607 3608 /* RSS size, cpu online and vector_num should be the same */ 3609 /* Should consider 2p/4p later */ 3610 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3611 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3612 3613 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3614 GFP_KERNEL); 3615 if (!vector) 3616 return -ENOMEM; 3617 3618 /* save the actual available vector number */ 3619 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3620 3621 priv->vector_num = vector_num; 3622 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3623 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3624 GFP_KERNEL); 3625 if (!priv->tqp_vector) { 3626 ret = -ENOMEM; 3627 goto out; 3628 } 3629 3630 for (i = 0; i < priv->vector_num; i++) { 3631 tqp_vector = &priv->tqp_vector[i]; 3632 tqp_vector->idx = i; 3633 tqp_vector->mask_addr = vector[i].io_addr; 3634 tqp_vector->vector_irq = vector[i].vector; 3635 hns3_vector_gl_rl_init(tqp_vector, priv); 3636 } 3637 3638 out: 3639 devm_kfree(&pdev->dev, vector); 3640 return ret; 3641 } 3642 3643 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3644 { 3645 group->ring = NULL; 3646 group->count = 0; 3647 } 3648 3649 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3650 { 3651 struct hnae3_ring_chain_node vector_ring_chain; 3652 struct hnae3_handle *h = priv->ae_handle; 3653 struct hns3_enet_tqp_vector *tqp_vector; 3654 int i; 3655 3656 for (i = 0; i < priv->vector_num; i++) { 3657 tqp_vector = &priv->tqp_vector[i]; 3658 3659 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3660 continue; 3661 3662 /* Since the mapping can be overwritten, when fail to get the 3663 * chain between vector and ring, we should go on to deal with 3664 * the remaining options. 3665 */ 3666 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3667 dev_warn(priv->dev, "failed to get ring chain\n"); 3668 3669 h->ae_algo->ops->unmap_ring_from_vector(h, 3670 tqp_vector->vector_irq, &vector_ring_chain); 3671 3672 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3673 3674 hns3_clear_ring_group(&tqp_vector->rx_group); 3675 hns3_clear_ring_group(&tqp_vector->tx_group); 3676 netif_napi_del(&priv->tqp_vector[i].napi); 3677 } 3678 } 3679 3680 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3681 { 3682 struct hnae3_handle *h = priv->ae_handle; 3683 struct pci_dev *pdev = h->pdev; 3684 int i, ret; 3685 3686 for (i = 0; i < priv->vector_num; i++) { 3687 struct hns3_enet_tqp_vector *tqp_vector; 3688 3689 tqp_vector = &priv->tqp_vector[i]; 3690 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3691 if (ret) 3692 return; 3693 } 3694 3695 devm_kfree(&pdev->dev, priv->tqp_vector); 3696 } 3697 3698 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3699 unsigned int ring_type) 3700 { 3701 int queue_num = priv->ae_handle->kinfo.num_tqps; 3702 struct hns3_enet_ring *ring; 3703 int desc_num; 3704 3705 if (ring_type == HNAE3_RING_TYPE_TX) { 3706 ring = &priv->ring[q->tqp_index]; 3707 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3708 ring->queue_index = q->tqp_index; 3709 } else { 3710 ring = &priv->ring[q->tqp_index + queue_num]; 3711 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3712 ring->queue_index = q->tqp_index; 3713 } 3714 3715 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3716 3717 ring->tqp = q; 3718 ring->desc = NULL; 3719 ring->desc_cb = NULL; 3720 ring->dev = priv->dev; 3721 ring->desc_dma_addr = 0; 3722 ring->buf_size = q->buf_size; 3723 ring->desc_num = desc_num; 3724 ring->next_to_use = 0; 3725 ring->next_to_clean = 0; 3726 ring->last_to_use = 0; 3727 } 3728 3729 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3730 struct hns3_nic_priv *priv) 3731 { 3732 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3733 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3734 } 3735 3736 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3737 { 3738 struct hnae3_handle *h = priv->ae_handle; 3739 struct pci_dev *pdev = h->pdev; 3740 int i; 3741 3742 priv->ring = devm_kzalloc(&pdev->dev, 3743 array3_size(h->kinfo.num_tqps, 3744 sizeof(*priv->ring), 2), 3745 GFP_KERNEL); 3746 if (!priv->ring) 3747 return -ENOMEM; 3748 3749 for (i = 0; i < h->kinfo.num_tqps; i++) 3750 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3751 3752 return 0; 3753 } 3754 3755 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3756 { 3757 if (!priv->ring) 3758 return; 3759 3760 devm_kfree(priv->dev, priv->ring); 3761 priv->ring = NULL; 3762 } 3763 3764 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3765 { 3766 int ret; 3767 3768 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3769 return -EINVAL; 3770 3771 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3772 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3773 if (!ring->desc_cb) { 3774 ret = -ENOMEM; 3775 goto out; 3776 } 3777 3778 ret = hns3_alloc_desc(ring); 3779 if (ret) 3780 goto out_with_desc_cb; 3781 3782 if (!HNAE3_IS_TX_RING(ring)) { 3783 ret = hns3_alloc_ring_buffers(ring); 3784 if (ret) 3785 goto out_with_desc; 3786 } 3787 3788 return 0; 3789 3790 out_with_desc: 3791 hns3_free_desc(ring); 3792 out_with_desc_cb: 3793 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3794 ring->desc_cb = NULL; 3795 out: 3796 return ret; 3797 } 3798 3799 void hns3_fini_ring(struct hns3_enet_ring *ring) 3800 { 3801 hns3_free_desc(ring); 3802 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3803 ring->desc_cb = NULL; 3804 ring->next_to_clean = 0; 3805 ring->next_to_use = 0; 3806 ring->last_to_use = 0; 3807 ring->pending_buf = 0; 3808 if (ring->skb) { 3809 dev_kfree_skb_any(ring->skb); 3810 ring->skb = NULL; 3811 } 3812 } 3813 3814 static int hns3_buf_size2type(u32 buf_size) 3815 { 3816 int bd_size_type; 3817 3818 switch (buf_size) { 3819 case 512: 3820 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3821 break; 3822 case 1024: 3823 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3824 break; 3825 case 2048: 3826 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3827 break; 3828 case 4096: 3829 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3830 break; 3831 default: 3832 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3833 } 3834 3835 return bd_size_type; 3836 } 3837 3838 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3839 { 3840 dma_addr_t dma = ring->desc_dma_addr; 3841 struct hnae3_queue *q = ring->tqp; 3842 3843 if (!HNAE3_IS_TX_RING(ring)) { 3844 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3845 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3846 (u32)((dma >> 31) >> 1)); 3847 3848 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3849 hns3_buf_size2type(ring->buf_size)); 3850 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3851 ring->desc_num / 8 - 1); 3852 3853 } else { 3854 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3855 (u32)dma); 3856 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3857 (u32)((dma >> 31) >> 1)); 3858 3859 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3860 ring->desc_num / 8 - 1); 3861 } 3862 } 3863 3864 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3865 { 3866 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3867 int i; 3868 3869 for (i = 0; i < HNAE3_MAX_TC; i++) { 3870 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3871 int j; 3872 3873 if (!tc_info->enable) 3874 continue; 3875 3876 for (j = 0; j < tc_info->tqp_count; j++) { 3877 struct hnae3_queue *q; 3878 3879 q = priv->ring[tc_info->tqp_offset + j].tqp; 3880 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3881 tc_info->tc); 3882 } 3883 } 3884 } 3885 3886 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3887 { 3888 struct hnae3_handle *h = priv->ae_handle; 3889 int ring_num = h->kinfo.num_tqps * 2; 3890 int i, j; 3891 int ret; 3892 3893 for (i = 0; i < ring_num; i++) { 3894 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3895 if (ret) { 3896 dev_err(priv->dev, 3897 "Alloc ring memory fail! ret=%d\n", ret); 3898 goto out_when_alloc_ring_memory; 3899 } 3900 3901 u64_stats_init(&priv->ring[i].syncp); 3902 } 3903 3904 return 0; 3905 3906 out_when_alloc_ring_memory: 3907 for (j = i - 1; j >= 0; j--) 3908 hns3_fini_ring(&priv->ring[j]); 3909 3910 return -ENOMEM; 3911 } 3912 3913 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3914 { 3915 struct hnae3_handle *h = priv->ae_handle; 3916 int i; 3917 3918 for (i = 0; i < h->kinfo.num_tqps; i++) { 3919 hns3_fini_ring(&priv->ring[i]); 3920 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3921 } 3922 return 0; 3923 } 3924 3925 /* Set mac addr if it is configured. or leave it to the AE driver */ 3926 static int hns3_init_mac_addr(struct net_device *netdev) 3927 { 3928 struct hns3_nic_priv *priv = netdev_priv(netdev); 3929 struct hnae3_handle *h = priv->ae_handle; 3930 u8 mac_addr_temp[ETH_ALEN]; 3931 int ret = 0; 3932 3933 if (h->ae_algo->ops->get_mac_addr) 3934 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3935 3936 /* Check if the MAC address is valid, if not get a random one */ 3937 if (!is_valid_ether_addr(mac_addr_temp)) { 3938 eth_hw_addr_random(netdev); 3939 dev_warn(priv->dev, "using random MAC address %pM\n", 3940 netdev->dev_addr); 3941 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 3942 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3943 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3944 } else { 3945 return 0; 3946 } 3947 3948 if (h->ae_algo->ops->set_mac_addr) 3949 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3950 3951 return ret; 3952 } 3953 3954 static int hns3_init_phy(struct net_device *netdev) 3955 { 3956 struct hnae3_handle *h = hns3_get_handle(netdev); 3957 int ret = 0; 3958 3959 if (h->ae_algo->ops->mac_connect_phy) 3960 ret = h->ae_algo->ops->mac_connect_phy(h); 3961 3962 return ret; 3963 } 3964 3965 static void hns3_uninit_phy(struct net_device *netdev) 3966 { 3967 struct hnae3_handle *h = hns3_get_handle(netdev); 3968 3969 if (h->ae_algo->ops->mac_disconnect_phy) 3970 h->ae_algo->ops->mac_disconnect_phy(h); 3971 } 3972 3973 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3974 { 3975 struct hnae3_handle *h = hns3_get_handle(netdev); 3976 3977 if (h->ae_algo->ops->del_all_fd_entries) 3978 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3979 } 3980 3981 static int hns3_client_start(struct hnae3_handle *handle) 3982 { 3983 if (!handle->ae_algo->ops->client_start) 3984 return 0; 3985 3986 return handle->ae_algo->ops->client_start(handle); 3987 } 3988 3989 static void hns3_client_stop(struct hnae3_handle *handle) 3990 { 3991 if (!handle->ae_algo->ops->client_stop) 3992 return; 3993 3994 handle->ae_algo->ops->client_stop(handle); 3995 } 3996 3997 static void hns3_info_show(struct hns3_nic_priv *priv) 3998 { 3999 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4000 4001 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4002 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4003 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4004 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4005 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4006 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4007 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4008 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 4009 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4010 } 4011 4012 static int hns3_client_init(struct hnae3_handle *handle) 4013 { 4014 struct pci_dev *pdev = handle->pdev; 4015 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4016 u16 alloc_tqps, max_rss_size; 4017 struct hns3_nic_priv *priv; 4018 struct net_device *netdev; 4019 int ret; 4020 4021 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4022 &max_rss_size); 4023 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4024 if (!netdev) 4025 return -ENOMEM; 4026 4027 priv = netdev_priv(netdev); 4028 priv->dev = &pdev->dev; 4029 priv->netdev = netdev; 4030 priv->ae_handle = handle; 4031 priv->tx_timeout_count = 0; 4032 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4033 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4034 4035 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4036 4037 handle->kinfo.netdev = netdev; 4038 handle->priv = (void *)priv; 4039 4040 hns3_init_mac_addr(netdev); 4041 4042 hns3_set_default_feature(netdev); 4043 4044 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4045 netdev->priv_flags |= IFF_UNICAST_FLT; 4046 netdev->netdev_ops = &hns3_nic_netdev_ops; 4047 SET_NETDEV_DEV(netdev, &pdev->dev); 4048 hns3_ethtool_set_ops(netdev); 4049 4050 /* Carrier off reporting is important to ethtool even BEFORE open */ 4051 netif_carrier_off(netdev); 4052 4053 ret = hns3_get_ring_config(priv); 4054 if (ret) { 4055 ret = -ENOMEM; 4056 goto out_get_ring_cfg; 4057 } 4058 4059 ret = hns3_nic_alloc_vector_data(priv); 4060 if (ret) { 4061 ret = -ENOMEM; 4062 goto out_alloc_vector_data; 4063 } 4064 4065 ret = hns3_nic_init_vector_data(priv); 4066 if (ret) { 4067 ret = -ENOMEM; 4068 goto out_init_vector_data; 4069 } 4070 4071 ret = hns3_init_all_ring(priv); 4072 if (ret) { 4073 ret = -ENOMEM; 4074 goto out_init_ring; 4075 } 4076 4077 ret = hns3_init_phy(netdev); 4078 if (ret) 4079 goto out_init_phy; 4080 4081 ret = register_netdev(netdev); 4082 if (ret) { 4083 dev_err(priv->dev, "probe register netdev fail!\n"); 4084 goto out_reg_netdev_fail; 4085 } 4086 4087 /* the device can work without cpu rmap, only aRFS needs it */ 4088 ret = hns3_set_rx_cpu_rmap(netdev); 4089 if (ret) 4090 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4091 4092 ret = hns3_nic_init_irq(priv); 4093 if (ret) { 4094 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4095 hns3_free_rx_cpu_rmap(netdev); 4096 goto out_init_irq_fail; 4097 } 4098 4099 ret = hns3_client_start(handle); 4100 if (ret) { 4101 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4102 goto out_client_start; 4103 } 4104 4105 hns3_dcbnl_setup(handle); 4106 4107 hns3_dbg_init(handle); 4108 4109 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4110 netdev->max_mtu = HNS3_MAX_MTU; 4111 4112 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4113 4114 if (netif_msg_drv(handle)) 4115 hns3_info_show(priv); 4116 4117 return ret; 4118 4119 out_client_start: 4120 hns3_free_rx_cpu_rmap(netdev); 4121 hns3_nic_uninit_irq(priv); 4122 out_init_irq_fail: 4123 unregister_netdev(netdev); 4124 out_reg_netdev_fail: 4125 hns3_uninit_phy(netdev); 4126 out_init_phy: 4127 hns3_uninit_all_ring(priv); 4128 out_init_ring: 4129 hns3_nic_uninit_vector_data(priv); 4130 out_init_vector_data: 4131 hns3_nic_dealloc_vector_data(priv); 4132 out_alloc_vector_data: 4133 priv->ring = NULL; 4134 out_get_ring_cfg: 4135 priv->ae_handle = NULL; 4136 free_netdev(netdev); 4137 return ret; 4138 } 4139 4140 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4141 { 4142 struct net_device *netdev = handle->kinfo.netdev; 4143 struct hns3_nic_priv *priv = netdev_priv(netdev); 4144 int ret; 4145 4146 if (netdev->reg_state != NETREG_UNINITIALIZED) 4147 unregister_netdev(netdev); 4148 4149 hns3_client_stop(handle); 4150 4151 hns3_uninit_phy(netdev); 4152 4153 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4154 netdev_warn(netdev, "already uninitialized\n"); 4155 goto out_netdev_free; 4156 } 4157 4158 hns3_free_rx_cpu_rmap(netdev); 4159 4160 hns3_nic_uninit_irq(priv); 4161 4162 hns3_del_all_fd_rules(netdev, true); 4163 4164 hns3_clear_all_ring(handle, true); 4165 4166 hns3_nic_uninit_vector_data(priv); 4167 4168 hns3_nic_dealloc_vector_data(priv); 4169 4170 ret = hns3_uninit_all_ring(priv); 4171 if (ret) 4172 netdev_err(netdev, "uninit ring error\n"); 4173 4174 hns3_put_ring_config(priv); 4175 4176 out_netdev_free: 4177 hns3_dbg_uninit(handle); 4178 free_netdev(netdev); 4179 } 4180 4181 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4182 { 4183 struct net_device *netdev = handle->kinfo.netdev; 4184 4185 if (!netdev) 4186 return; 4187 4188 if (linkup) { 4189 netif_tx_wake_all_queues(netdev); 4190 netif_carrier_on(netdev); 4191 if (netif_msg_link(handle)) 4192 netdev_info(netdev, "link up\n"); 4193 } else { 4194 netif_carrier_off(netdev); 4195 netif_tx_stop_all_queues(netdev); 4196 if (netif_msg_link(handle)) 4197 netdev_info(netdev, "link down\n"); 4198 } 4199 } 4200 4201 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4202 { 4203 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4204 struct net_device *ndev = kinfo->netdev; 4205 4206 if (tc > HNAE3_MAX_TC) 4207 return -EINVAL; 4208 4209 if (!ndev) 4210 return -ENODEV; 4211 4212 return hns3_nic_set_real_num_queue(ndev); 4213 } 4214 4215 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4216 { 4217 while (ring->next_to_clean != ring->next_to_use) { 4218 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4219 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4220 ring_ptr_move_fw(ring, next_to_clean); 4221 } 4222 4223 ring->pending_buf = 0; 4224 } 4225 4226 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4227 { 4228 struct hns3_desc_cb res_cbs; 4229 int ret; 4230 4231 while (ring->next_to_use != ring->next_to_clean) { 4232 /* When a buffer is not reused, it's memory has been 4233 * freed in hns3_handle_rx_bd or will be freed by 4234 * stack, so we need to replace the buffer here. 4235 */ 4236 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4237 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4238 if (ret) { 4239 u64_stats_update_begin(&ring->syncp); 4240 ring->stats.sw_err_cnt++; 4241 u64_stats_update_end(&ring->syncp); 4242 /* if alloc new buffer fail, exit directly 4243 * and reclear in up flow. 4244 */ 4245 netdev_warn(ring_to_netdev(ring), 4246 "reserve buffer map failed, ret = %d\n", 4247 ret); 4248 return ret; 4249 } 4250 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4251 } 4252 ring_ptr_move_fw(ring, next_to_use); 4253 } 4254 4255 /* Free the pending skb in rx ring */ 4256 if (ring->skb) { 4257 dev_kfree_skb_any(ring->skb); 4258 ring->skb = NULL; 4259 ring->pending_buf = 0; 4260 } 4261 4262 return 0; 4263 } 4264 4265 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4266 { 4267 while (ring->next_to_use != ring->next_to_clean) { 4268 /* When a buffer is not reused, it's memory has been 4269 * freed in hns3_handle_rx_bd or will be freed by 4270 * stack, so only need to unmap the buffer here. 4271 */ 4272 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4273 hns3_unmap_buffer(ring, 4274 &ring->desc_cb[ring->next_to_use]); 4275 ring->desc_cb[ring->next_to_use].dma = 0; 4276 } 4277 4278 ring_ptr_move_fw(ring, next_to_use); 4279 } 4280 } 4281 4282 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4283 { 4284 struct net_device *ndev = h->kinfo.netdev; 4285 struct hns3_nic_priv *priv = netdev_priv(ndev); 4286 u32 i; 4287 4288 for (i = 0; i < h->kinfo.num_tqps; i++) { 4289 struct hns3_enet_ring *ring; 4290 4291 ring = &priv->ring[i]; 4292 hns3_clear_tx_ring(ring); 4293 4294 ring = &priv->ring[i + h->kinfo.num_tqps]; 4295 /* Continue to clear other rings even if clearing some 4296 * rings failed. 4297 */ 4298 if (force) 4299 hns3_force_clear_rx_ring(ring); 4300 else 4301 hns3_clear_rx_ring(ring); 4302 } 4303 } 4304 4305 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4306 { 4307 struct net_device *ndev = h->kinfo.netdev; 4308 struct hns3_nic_priv *priv = netdev_priv(ndev); 4309 struct hns3_enet_ring *rx_ring; 4310 int i, j; 4311 int ret; 4312 4313 for (i = 0; i < h->kinfo.num_tqps; i++) { 4314 ret = h->ae_algo->ops->reset_queue(h, i); 4315 if (ret) 4316 return ret; 4317 4318 hns3_init_ring_hw(&priv->ring[i]); 4319 4320 /* We need to clear tx ring here because self test will 4321 * use the ring and will not run down before up 4322 */ 4323 hns3_clear_tx_ring(&priv->ring[i]); 4324 priv->ring[i].next_to_clean = 0; 4325 priv->ring[i].next_to_use = 0; 4326 priv->ring[i].last_to_use = 0; 4327 4328 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4329 hns3_init_ring_hw(rx_ring); 4330 ret = hns3_clear_rx_ring(rx_ring); 4331 if (ret) 4332 return ret; 4333 4334 /* We can not know the hardware head and tail when this 4335 * function is called in reset flow, so we reuse all desc. 4336 */ 4337 for (j = 0; j < rx_ring->desc_num; j++) 4338 hns3_reuse_buffer(rx_ring, j); 4339 4340 rx_ring->next_to_clean = 0; 4341 rx_ring->next_to_use = 0; 4342 } 4343 4344 hns3_init_tx_ring_tc(priv); 4345 4346 return 0; 4347 } 4348 4349 static void hns3_store_coal(struct hns3_nic_priv *priv) 4350 { 4351 /* ethtool only support setting and querying one coal 4352 * configuration for now, so save the vector 0' coal 4353 * configuration here in order to restore it. 4354 */ 4355 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4356 sizeof(struct hns3_enet_coalesce)); 4357 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4358 sizeof(struct hns3_enet_coalesce)); 4359 } 4360 4361 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4362 { 4363 u16 vector_num = priv->vector_num; 4364 int i; 4365 4366 for (i = 0; i < vector_num; i++) { 4367 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4368 sizeof(struct hns3_enet_coalesce)); 4369 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4370 sizeof(struct hns3_enet_coalesce)); 4371 } 4372 } 4373 4374 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4375 { 4376 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4377 struct net_device *ndev = kinfo->netdev; 4378 struct hns3_nic_priv *priv = netdev_priv(ndev); 4379 4380 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4381 return 0; 4382 4383 if (!netif_running(ndev)) 4384 return 0; 4385 4386 return hns3_nic_net_stop(ndev); 4387 } 4388 4389 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4390 { 4391 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4392 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4393 int ret = 0; 4394 4395 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4396 4397 if (netif_running(kinfo->netdev)) { 4398 ret = hns3_nic_net_open(kinfo->netdev); 4399 if (ret) { 4400 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4401 netdev_err(kinfo->netdev, 4402 "net up fail, ret=%d!\n", ret); 4403 return ret; 4404 } 4405 } 4406 4407 return ret; 4408 } 4409 4410 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4411 { 4412 struct net_device *netdev = handle->kinfo.netdev; 4413 struct hns3_nic_priv *priv = netdev_priv(netdev); 4414 int ret; 4415 4416 /* Carrier off reporting is important to ethtool even BEFORE open */ 4417 netif_carrier_off(netdev); 4418 4419 ret = hns3_get_ring_config(priv); 4420 if (ret) 4421 return ret; 4422 4423 ret = hns3_nic_alloc_vector_data(priv); 4424 if (ret) 4425 goto err_put_ring; 4426 4427 hns3_restore_coal(priv); 4428 4429 ret = hns3_nic_init_vector_data(priv); 4430 if (ret) 4431 goto err_dealloc_vector; 4432 4433 ret = hns3_init_all_ring(priv); 4434 if (ret) 4435 goto err_uninit_vector; 4436 4437 /* the device can work without cpu rmap, only aRFS needs it */ 4438 ret = hns3_set_rx_cpu_rmap(netdev); 4439 if (ret) 4440 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4441 4442 ret = hns3_nic_init_irq(priv); 4443 if (ret) { 4444 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4445 hns3_free_rx_cpu_rmap(netdev); 4446 goto err_init_irq_fail; 4447 } 4448 4449 if (!hns3_is_phys_func(handle->pdev)) 4450 hns3_init_mac_addr(netdev); 4451 4452 ret = hns3_client_start(handle); 4453 if (ret) { 4454 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4455 goto err_client_start_fail; 4456 } 4457 4458 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4459 4460 return ret; 4461 4462 err_client_start_fail: 4463 hns3_free_rx_cpu_rmap(netdev); 4464 hns3_nic_uninit_irq(priv); 4465 err_init_irq_fail: 4466 hns3_uninit_all_ring(priv); 4467 err_uninit_vector: 4468 hns3_nic_uninit_vector_data(priv); 4469 err_dealloc_vector: 4470 hns3_nic_dealloc_vector_data(priv); 4471 err_put_ring: 4472 hns3_put_ring_config(priv); 4473 4474 return ret; 4475 } 4476 4477 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4478 { 4479 struct net_device *netdev = handle->kinfo.netdev; 4480 struct hns3_nic_priv *priv = netdev_priv(netdev); 4481 int ret; 4482 4483 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4484 netdev_warn(netdev, "already uninitialized\n"); 4485 return 0; 4486 } 4487 4488 hns3_free_rx_cpu_rmap(netdev); 4489 hns3_nic_uninit_irq(priv); 4490 hns3_clear_all_ring(handle, true); 4491 hns3_reset_tx_queue(priv->ae_handle); 4492 4493 hns3_nic_uninit_vector_data(priv); 4494 4495 hns3_store_coal(priv); 4496 4497 hns3_nic_dealloc_vector_data(priv); 4498 4499 ret = hns3_uninit_all_ring(priv); 4500 if (ret) 4501 netdev_err(netdev, "uninit ring error\n"); 4502 4503 hns3_put_ring_config(priv); 4504 4505 return ret; 4506 } 4507 4508 static int hns3_reset_notify(struct hnae3_handle *handle, 4509 enum hnae3_reset_notify_type type) 4510 { 4511 int ret = 0; 4512 4513 switch (type) { 4514 case HNAE3_UP_CLIENT: 4515 ret = hns3_reset_notify_up_enet(handle); 4516 break; 4517 case HNAE3_DOWN_CLIENT: 4518 ret = hns3_reset_notify_down_enet(handle); 4519 break; 4520 case HNAE3_INIT_CLIENT: 4521 ret = hns3_reset_notify_init_enet(handle); 4522 break; 4523 case HNAE3_UNINIT_CLIENT: 4524 ret = hns3_reset_notify_uninit_enet(handle); 4525 break; 4526 default: 4527 break; 4528 } 4529 4530 return ret; 4531 } 4532 4533 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4534 bool rxfh_configured) 4535 { 4536 int ret; 4537 4538 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4539 rxfh_configured); 4540 if (ret) { 4541 dev_err(&handle->pdev->dev, 4542 "Change tqp num(%u) fail.\n", new_tqp_num); 4543 return ret; 4544 } 4545 4546 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4547 if (ret) 4548 return ret; 4549 4550 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4551 if (ret) 4552 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4553 4554 return ret; 4555 } 4556 4557 int hns3_set_channels(struct net_device *netdev, 4558 struct ethtool_channels *ch) 4559 { 4560 struct hnae3_handle *h = hns3_get_handle(netdev); 4561 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4562 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4563 u32 new_tqp_num = ch->combined_count; 4564 u16 org_tqp_num; 4565 int ret; 4566 4567 if (hns3_nic_resetting(netdev)) 4568 return -EBUSY; 4569 4570 if (ch->rx_count || ch->tx_count) 4571 return -EINVAL; 4572 4573 if (new_tqp_num > hns3_get_max_available_channels(h) || 4574 new_tqp_num < 1) { 4575 dev_err(&netdev->dev, 4576 "Change tqps fail, the tqp range is from 1 to %u", 4577 hns3_get_max_available_channels(h)); 4578 return -EINVAL; 4579 } 4580 4581 if (kinfo->rss_size == new_tqp_num) 4582 return 0; 4583 4584 netif_dbg(h, drv, netdev, 4585 "set channels: tqp_num=%u, rxfh=%d\n", 4586 new_tqp_num, rxfh_configured); 4587 4588 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4589 if (ret) 4590 return ret; 4591 4592 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4593 if (ret) 4594 return ret; 4595 4596 org_tqp_num = h->kinfo.num_tqps; 4597 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4598 if (ret) { 4599 int ret1; 4600 4601 netdev_warn(netdev, 4602 "Change channels fail, revert to old value\n"); 4603 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4604 if (ret1) { 4605 netdev_err(netdev, 4606 "revert to old channel fail\n"); 4607 return ret1; 4608 } 4609 4610 return ret; 4611 } 4612 4613 return 0; 4614 } 4615 4616 static const struct hns3_hw_error_info hns3_hw_err[] = { 4617 { .type = HNAE3_PPU_POISON_ERROR, 4618 .msg = "PPU poison" }, 4619 { .type = HNAE3_CMDQ_ECC_ERROR, 4620 .msg = "IMP CMDQ error" }, 4621 { .type = HNAE3_IMP_RD_POISON_ERROR, 4622 .msg = "IMP RD poison" }, 4623 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 4624 .msg = "ROCEE AXI RESP error" }, 4625 }; 4626 4627 static void hns3_process_hw_error(struct hnae3_handle *handle, 4628 enum hnae3_hw_error_type type) 4629 { 4630 int i; 4631 4632 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4633 if (hns3_hw_err[i].type == type) { 4634 dev_err(&handle->pdev->dev, "Detected %s!\n", 4635 hns3_hw_err[i].msg); 4636 break; 4637 } 4638 } 4639 } 4640 4641 static const struct hnae3_client_ops client_ops = { 4642 .init_instance = hns3_client_init, 4643 .uninit_instance = hns3_client_uninit, 4644 .link_status_change = hns3_link_status_change, 4645 .setup_tc = hns3_client_setup_tc, 4646 .reset_notify = hns3_reset_notify, 4647 .process_hw_error = hns3_process_hw_error, 4648 }; 4649 4650 /* hns3_init_module - Driver registration routine 4651 * hns3_init_module is the first routine called when the driver is 4652 * loaded. All it does is register with the PCI subsystem. 4653 */ 4654 static int __init hns3_init_module(void) 4655 { 4656 int ret; 4657 4658 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4659 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4660 4661 client.type = HNAE3_CLIENT_KNIC; 4662 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4663 hns3_driver_name); 4664 4665 client.ops = &client_ops; 4666 4667 INIT_LIST_HEAD(&client.node); 4668 4669 hns3_dbg_register_debugfs(hns3_driver_name); 4670 4671 ret = hnae3_register_client(&client); 4672 if (ret) 4673 goto err_reg_client; 4674 4675 ret = pci_register_driver(&hns3_driver); 4676 if (ret) 4677 goto err_reg_driver; 4678 4679 return ret; 4680 4681 err_reg_driver: 4682 hnae3_unregister_client(&client); 4683 err_reg_client: 4684 hns3_dbg_unregister_debugfs(); 4685 return ret; 4686 } 4687 module_init(hns3_init_module); 4688 4689 /* hns3_exit_module - Driver exit cleanup routine 4690 * hns3_exit_module is called just before the driver is removed 4691 * from memory. 4692 */ 4693 static void __exit hns3_exit_module(void) 4694 { 4695 pci_unregister_driver(&hns3_driver); 4696 hnae3_unregister_client(&client); 4697 hns3_dbg_unregister_debugfs(); 4698 } 4699 module_exit(hns3_exit_module); 4700 4701 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4702 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4703 MODULE_LICENSE("GPL"); 4704 MODULE_ALIAS("pci:hns-nic"); 4705