1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 25 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 26 27 static void hns3_clear_all_ring(struct hnae3_handle *h); 28 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 29 static void hns3_remove_hw_addr(struct net_device *netdev); 30 31 static const char hns3_driver_name[] = "hns3"; 32 const char hns3_driver_version[] = VERMAGIC_STRING; 33 static const char hns3_driver_string[] = 34 "Hisilicon Ethernet Network Driver for Hip08 Family"; 35 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 36 static struct hnae3_client client; 37 38 /* hns3_pci_tbl - PCI Device ID Table 39 * 40 * Last entry must be all 0s 41 * 42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 43 * Class, Class Mask, private data (not used) } 44 */ 45 static const struct pci_device_id hns3_pci_tbl[] = { 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 53 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 54 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 55 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 59 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 60 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 61 /* required last entry */ 62 {0, } 63 }; 64 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 65 66 static irqreturn_t hns3_irq_handle(int irq, void *vector) 67 { 68 struct hns3_enet_tqp_vector *tqp_vector = vector; 69 70 napi_schedule(&tqp_vector->napi); 71 72 return IRQ_HANDLED; 73 } 74 75 /* This callback function is used to set affinity changes to the irq affinity 76 * masks when the irq_set_affinity_notifier function is used. 77 */ 78 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 79 const cpumask_t *mask) 80 { 81 struct hns3_enet_tqp_vector *tqp_vectors = 82 container_of(notify, struct hns3_enet_tqp_vector, 83 affinity_notify); 84 85 tqp_vectors->affinity_mask = *mask; 86 } 87 88 static void hns3_nic_irq_affinity_release(struct kref *ref) 89 { 90 } 91 92 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 93 { 94 struct hns3_enet_tqp_vector *tqp_vectors; 95 unsigned int i; 96 97 for (i = 0; i < priv->vector_num; i++) { 98 tqp_vectors = &priv->tqp_vector[i]; 99 100 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 101 continue; 102 103 /* clear the affinity notifier and affinity mask */ 104 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 105 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 106 107 /* release the irq resource */ 108 free_irq(tqp_vectors->vector_irq, tqp_vectors); 109 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 110 } 111 } 112 113 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 114 { 115 struct hns3_enet_tqp_vector *tqp_vectors; 116 int txrx_int_idx = 0; 117 int rx_int_idx = 0; 118 int tx_int_idx = 0; 119 unsigned int i; 120 int ret; 121 122 for (i = 0; i < priv->vector_num; i++) { 123 tqp_vectors = &priv->tqp_vector[i]; 124 125 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 126 continue; 127 128 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 129 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 130 "%s-%s-%d", priv->netdev->name, "TxRx", 131 txrx_int_idx++); 132 txrx_int_idx++; 133 } else if (tqp_vectors->rx_group.ring) { 134 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 135 "%s-%s-%d", priv->netdev->name, "Rx", 136 rx_int_idx++); 137 } else if (tqp_vectors->tx_group.ring) { 138 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 139 "%s-%s-%d", priv->netdev->name, "Tx", 140 tx_int_idx++); 141 } else { 142 /* Skip this unused q_vector */ 143 continue; 144 } 145 146 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 147 148 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 149 tqp_vectors->name, 150 tqp_vectors); 151 if (ret) { 152 netdev_err(priv->netdev, "request irq(%d) fail\n", 153 tqp_vectors->vector_irq); 154 return ret; 155 } 156 157 tqp_vectors->affinity_notify.notify = 158 hns3_nic_irq_affinity_notify; 159 tqp_vectors->affinity_notify.release = 160 hns3_nic_irq_affinity_release; 161 irq_set_affinity_notifier(tqp_vectors->vector_irq, 162 &tqp_vectors->affinity_notify); 163 irq_set_affinity_hint(tqp_vectors->vector_irq, 164 &tqp_vectors->affinity_mask); 165 166 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 167 } 168 169 return 0; 170 } 171 172 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 173 u32 mask_en) 174 { 175 writel(mask_en, tqp_vector->mask_addr); 176 } 177 178 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 179 { 180 napi_enable(&tqp_vector->napi); 181 182 /* enable vector */ 183 hns3_mask_vector_irq(tqp_vector, 1); 184 } 185 186 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 /* disable vector */ 189 hns3_mask_vector_irq(tqp_vector, 0); 190 191 disable_irq(tqp_vector->vector_irq); 192 napi_disable(&tqp_vector->napi); 193 } 194 195 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 196 u32 rl_value) 197 { 198 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 199 200 /* this defines the configuration for RL (Interrupt Rate Limiter). 201 * Rl defines rate of interrupts i.e. number of interrupts-per-second 202 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 203 */ 204 205 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 206 !tqp_vector->rx_group.coal.gl_adapt_enable) 207 /* According to the hardware, the range of rl_reg is 208 * 0-59 and the unit is 4. 209 */ 210 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 211 212 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 213 } 214 215 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 216 u32 gl_value) 217 { 218 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 219 220 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 221 } 222 223 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 224 u32 gl_value) 225 { 226 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 227 228 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 229 } 230 231 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 232 struct hns3_nic_priv *priv) 233 { 234 /* initialize the configuration for interrupt coalescing. 235 * 1. GL (Interrupt Gap Limiter) 236 * 2. RL (Interrupt Rate Limiter) 237 */ 238 239 /* Default: enable interrupt coalescing self-adaptive and GL */ 240 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 241 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 242 243 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 244 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 245 246 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 247 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 248 } 249 250 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 251 struct hns3_nic_priv *priv) 252 { 253 struct hnae3_handle *h = priv->ae_handle; 254 255 hns3_set_vector_coalesce_tx_gl(tqp_vector, 256 tqp_vector->tx_group.coal.int_gl); 257 hns3_set_vector_coalesce_rx_gl(tqp_vector, 258 tqp_vector->rx_group.coal.int_gl); 259 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 260 } 261 262 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 263 { 264 struct hnae3_handle *h = hns3_get_handle(netdev); 265 struct hnae3_knic_private_info *kinfo = &h->kinfo; 266 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 267 int i, ret; 268 269 if (kinfo->num_tc <= 1) { 270 netdev_reset_tc(netdev); 271 } else { 272 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 273 if (ret) { 274 netdev_err(netdev, 275 "netdev_set_num_tc fail, ret=%d!\n", ret); 276 return ret; 277 } 278 279 for (i = 0; i < HNAE3_MAX_TC; i++) { 280 if (!kinfo->tc_info[i].enable) 281 continue; 282 283 netdev_set_tc_queue(netdev, 284 kinfo->tc_info[i].tc, 285 kinfo->tc_info[i].tqp_count, 286 kinfo->tc_info[i].tqp_offset); 287 } 288 } 289 290 ret = netif_set_real_num_tx_queues(netdev, queue_size); 291 if (ret) { 292 netdev_err(netdev, 293 "netif_set_real_num_tx_queues fail, ret=%d!\n", 294 ret); 295 return ret; 296 } 297 298 ret = netif_set_real_num_rx_queues(netdev, queue_size); 299 if (ret) { 300 netdev_err(netdev, 301 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 302 return ret; 303 } 304 305 return 0; 306 } 307 308 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 309 { 310 u16 alloc_tqps, max_rss_size, rss_size; 311 312 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 313 rss_size = alloc_tqps / h->kinfo.num_tc; 314 315 return min_t(u16, rss_size, max_rss_size); 316 } 317 318 static void hns3_tqp_enable(struct hnae3_queue *tqp) 319 { 320 u32 rcb_reg; 321 322 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 323 rcb_reg |= BIT(HNS3_RING_EN_B); 324 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 325 } 326 327 static void hns3_tqp_disable(struct hnae3_queue *tqp) 328 { 329 u32 rcb_reg; 330 331 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 332 rcb_reg &= ~BIT(HNS3_RING_EN_B); 333 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 334 } 335 336 static int hns3_nic_net_up(struct net_device *netdev) 337 { 338 struct hns3_nic_priv *priv = netdev_priv(netdev); 339 struct hnae3_handle *h = priv->ae_handle; 340 int i, j; 341 int ret; 342 343 ret = hns3_nic_reset_all_ring(h); 344 if (ret) 345 return ret; 346 347 /* get irq resource for all vectors */ 348 ret = hns3_nic_init_irq(priv); 349 if (ret) { 350 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 351 return ret; 352 } 353 354 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 355 356 /* enable the vectors */ 357 for (i = 0; i < priv->vector_num; i++) 358 hns3_vector_enable(&priv->tqp_vector[i]); 359 360 /* enable rcb */ 361 for (j = 0; j < h->kinfo.num_tqps; j++) 362 hns3_tqp_enable(h->kinfo.tqp[j]); 363 364 /* start the ae_dev */ 365 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 366 if (ret) 367 goto out_start_err; 368 369 return 0; 370 371 out_start_err: 372 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 373 while (j--) 374 hns3_tqp_disable(h->kinfo.tqp[j]); 375 376 for (j = i - 1; j >= 0; j--) 377 hns3_vector_disable(&priv->tqp_vector[j]); 378 379 hns3_nic_uninit_irq(priv); 380 381 return ret; 382 } 383 384 static void hns3_config_xps(struct hns3_nic_priv *priv) 385 { 386 int i; 387 388 for (i = 0; i < priv->vector_num; i++) { 389 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 390 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 391 392 while (ring) { 393 int ret; 394 395 ret = netif_set_xps_queue(priv->netdev, 396 &tqp_vector->affinity_mask, 397 ring->tqp->tqp_index); 398 if (ret) 399 netdev_warn(priv->netdev, 400 "set xps queue failed: %d", ret); 401 402 ring = ring->next; 403 } 404 } 405 } 406 407 static int hns3_nic_net_open(struct net_device *netdev) 408 { 409 struct hns3_nic_priv *priv = netdev_priv(netdev); 410 struct hnae3_handle *h = hns3_get_handle(netdev); 411 struct hnae3_knic_private_info *kinfo; 412 int i, ret; 413 414 if (hns3_nic_resetting(netdev)) 415 return -EBUSY; 416 417 netif_carrier_off(netdev); 418 419 ret = hns3_nic_set_real_num_queue(netdev); 420 if (ret) 421 return ret; 422 423 ret = hns3_nic_net_up(netdev); 424 if (ret) { 425 netdev_err(netdev, 426 "hns net up fail, ret=%d!\n", ret); 427 return ret; 428 } 429 430 kinfo = &h->kinfo; 431 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 432 netdev_set_prio_tc_map(netdev, i, 433 kinfo->prio_tc[i]); 434 } 435 436 if (h->ae_algo->ops->set_timer_task) 437 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 438 439 hns3_config_xps(priv); 440 return 0; 441 } 442 443 static void hns3_nic_net_down(struct net_device *netdev) 444 { 445 struct hns3_nic_priv *priv = netdev_priv(netdev); 446 struct hnae3_handle *h = hns3_get_handle(netdev); 447 const struct hnae3_ae_ops *ops; 448 int i; 449 450 /* disable vectors */ 451 for (i = 0; i < priv->vector_num; i++) 452 hns3_vector_disable(&priv->tqp_vector[i]); 453 454 /* disable rcb */ 455 for (i = 0; i < h->kinfo.num_tqps; i++) 456 hns3_tqp_disable(h->kinfo.tqp[i]); 457 458 /* stop ae_dev */ 459 ops = priv->ae_handle->ae_algo->ops; 460 if (ops->stop) 461 ops->stop(priv->ae_handle); 462 463 /* free irq resources */ 464 hns3_nic_uninit_irq(priv); 465 466 hns3_clear_all_ring(priv->ae_handle); 467 } 468 469 static int hns3_nic_net_stop(struct net_device *netdev) 470 { 471 struct hns3_nic_priv *priv = netdev_priv(netdev); 472 struct hnae3_handle *h = hns3_get_handle(netdev); 473 474 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 475 return 0; 476 477 if (h->ae_algo->ops->set_timer_task) 478 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 479 480 netif_tx_stop_all_queues(netdev); 481 netif_carrier_off(netdev); 482 483 hns3_nic_net_down(netdev); 484 485 return 0; 486 } 487 488 static int hns3_nic_uc_sync(struct net_device *netdev, 489 const unsigned char *addr) 490 { 491 struct hnae3_handle *h = hns3_get_handle(netdev); 492 493 if (h->ae_algo->ops->add_uc_addr) 494 return h->ae_algo->ops->add_uc_addr(h, addr); 495 496 return 0; 497 } 498 499 static int hns3_nic_uc_unsync(struct net_device *netdev, 500 const unsigned char *addr) 501 { 502 struct hnae3_handle *h = hns3_get_handle(netdev); 503 504 if (h->ae_algo->ops->rm_uc_addr) 505 return h->ae_algo->ops->rm_uc_addr(h, addr); 506 507 return 0; 508 } 509 510 static int hns3_nic_mc_sync(struct net_device *netdev, 511 const unsigned char *addr) 512 { 513 struct hnae3_handle *h = hns3_get_handle(netdev); 514 515 if (h->ae_algo->ops->add_mc_addr) 516 return h->ae_algo->ops->add_mc_addr(h, addr); 517 518 return 0; 519 } 520 521 static int hns3_nic_mc_unsync(struct net_device *netdev, 522 const unsigned char *addr) 523 { 524 struct hnae3_handle *h = hns3_get_handle(netdev); 525 526 if (h->ae_algo->ops->rm_mc_addr) 527 return h->ae_algo->ops->rm_mc_addr(h, addr); 528 529 return 0; 530 } 531 532 static u8 hns3_get_netdev_flags(struct net_device *netdev) 533 { 534 u8 flags = 0; 535 536 if (netdev->flags & IFF_PROMISC) { 537 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 538 } else { 539 flags |= HNAE3_VLAN_FLTR; 540 if (netdev->flags & IFF_ALLMULTI) 541 flags |= HNAE3_USER_MPE; 542 } 543 544 return flags; 545 } 546 547 static void hns3_nic_set_rx_mode(struct net_device *netdev) 548 { 549 struct hnae3_handle *h = hns3_get_handle(netdev); 550 u8 new_flags; 551 int ret; 552 553 new_flags = hns3_get_netdev_flags(netdev); 554 555 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 556 if (ret) { 557 netdev_err(netdev, "sync uc address fail\n"); 558 if (ret == -ENOSPC) 559 new_flags |= HNAE3_OVERFLOW_UPE; 560 } 561 562 if (netdev->flags & IFF_MULTICAST) { 563 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 564 hns3_nic_mc_unsync); 565 if (ret) { 566 netdev_err(netdev, "sync mc address fail\n"); 567 if (ret == -ENOSPC) 568 new_flags |= HNAE3_OVERFLOW_MPE; 569 } 570 } 571 572 /* User mode Promisc mode enable and vlan filtering is disabled to 573 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 574 * vlan fitering is enabled 575 */ 576 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 577 h->netdev_flags = new_flags; 578 hns3_update_promisc_mode(netdev, new_flags); 579 } 580 581 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 582 { 583 struct hns3_nic_priv *priv = netdev_priv(netdev); 584 struct hnae3_handle *h = priv->ae_handle; 585 586 if (h->ae_algo->ops->set_promisc_mode) { 587 return h->ae_algo->ops->set_promisc_mode(h, 588 promisc_flags & HNAE3_UPE, 589 promisc_flags & HNAE3_MPE); 590 } 591 592 return 0; 593 } 594 595 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 596 { 597 struct hns3_nic_priv *priv = netdev_priv(netdev); 598 struct hnae3_handle *h = priv->ae_handle; 599 bool last_state; 600 601 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 602 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 603 if (enable != last_state) { 604 netdev_info(netdev, 605 "%s vlan filter\n", 606 enable ? "enable" : "disable"); 607 h->ae_algo->ops->enable_vlan_filter(h, enable); 608 } 609 } 610 } 611 612 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 613 u16 *mss, u32 *type_cs_vlan_tso) 614 { 615 u32 l4_offset, hdr_len; 616 union l3_hdr_info l3; 617 union l4_hdr_info l4; 618 u32 l4_paylen; 619 int ret; 620 621 if (!skb_is_gso(skb)) 622 return 0; 623 624 ret = skb_cow_head(skb, 0); 625 if (unlikely(ret)) 626 return ret; 627 628 l3.hdr = skb_network_header(skb); 629 l4.hdr = skb_transport_header(skb); 630 631 /* Software should clear the IPv4's checksum field when tso is 632 * needed. 633 */ 634 if (l3.v4->version == 4) 635 l3.v4->check = 0; 636 637 /* tunnel packet.*/ 638 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 639 SKB_GSO_GRE_CSUM | 640 SKB_GSO_UDP_TUNNEL | 641 SKB_GSO_UDP_TUNNEL_CSUM)) { 642 if ((!(skb_shinfo(skb)->gso_type & 643 SKB_GSO_PARTIAL)) && 644 (skb_shinfo(skb)->gso_type & 645 SKB_GSO_UDP_TUNNEL_CSUM)) { 646 /* Software should clear the udp's checksum 647 * field when tso is needed. 648 */ 649 l4.udp->check = 0; 650 } 651 /* reset l3&l4 pointers from outer to inner headers */ 652 l3.hdr = skb_inner_network_header(skb); 653 l4.hdr = skb_inner_transport_header(skb); 654 655 /* Software should clear the IPv4's checksum field when 656 * tso is needed. 657 */ 658 if (l3.v4->version == 4) 659 l3.v4->check = 0; 660 } 661 662 /* normal or tunnel packet*/ 663 l4_offset = l4.hdr - skb->data; 664 hdr_len = (l4.tcp->doff << 2) + l4_offset; 665 666 /* remove payload length from inner pseudo checksum when tso*/ 667 l4_paylen = skb->len - l4_offset; 668 csum_replace_by_diff(&l4.tcp->check, 669 (__force __wsum)htonl(l4_paylen)); 670 671 /* find the txbd field values */ 672 *paylen = skb->len - hdr_len; 673 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 674 675 /* get MSS for TSO */ 676 *mss = skb_shinfo(skb)->gso_size; 677 678 return 0; 679 } 680 681 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 682 u8 *il4_proto) 683 { 684 union l3_hdr_info l3; 685 unsigned char *l4_hdr; 686 unsigned char *exthdr; 687 u8 l4_proto_tmp; 688 __be16 frag_off; 689 690 /* find outer header point */ 691 l3.hdr = skb_network_header(skb); 692 l4_hdr = skb_transport_header(skb); 693 694 if (skb->protocol == htons(ETH_P_IPV6)) { 695 exthdr = l3.hdr + sizeof(*l3.v6); 696 l4_proto_tmp = l3.v6->nexthdr; 697 if (l4_hdr != exthdr) 698 ipv6_skip_exthdr(skb, exthdr - skb->data, 699 &l4_proto_tmp, &frag_off); 700 } else if (skb->protocol == htons(ETH_P_IP)) { 701 l4_proto_tmp = l3.v4->protocol; 702 } else { 703 return -EINVAL; 704 } 705 706 *ol4_proto = l4_proto_tmp; 707 708 /* tunnel packet */ 709 if (!skb->encapsulation) { 710 *il4_proto = 0; 711 return 0; 712 } 713 714 /* find inner header point */ 715 l3.hdr = skb_inner_network_header(skb); 716 l4_hdr = skb_inner_transport_header(skb); 717 718 if (l3.v6->version == 6) { 719 exthdr = l3.hdr + sizeof(*l3.v6); 720 l4_proto_tmp = l3.v6->nexthdr; 721 if (l4_hdr != exthdr) 722 ipv6_skip_exthdr(skb, exthdr - skb->data, 723 &l4_proto_tmp, &frag_off); 724 } else if (l3.v4->version == 4) { 725 l4_proto_tmp = l3.v4->protocol; 726 } 727 728 *il4_proto = l4_proto_tmp; 729 730 return 0; 731 } 732 733 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 734 u8 il4_proto, u32 *type_cs_vlan_tso, 735 u32 *ol_type_vlan_len_msec) 736 { 737 union l3_hdr_info l3; 738 union l4_hdr_info l4; 739 unsigned char *l2_hdr; 740 u8 l4_proto = ol4_proto; 741 u32 ol2_len; 742 u32 ol3_len; 743 u32 ol4_len; 744 u32 l2_len; 745 u32 l3_len; 746 747 l3.hdr = skb_network_header(skb); 748 l4.hdr = skb_transport_header(skb); 749 750 /* compute L2 header size for normal packet, defined in 2 Bytes */ 751 l2_len = l3.hdr - skb->data; 752 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 753 754 /* tunnel packet*/ 755 if (skb->encapsulation) { 756 /* compute OL2 header size, defined in 2 Bytes */ 757 ol2_len = l2_len; 758 hns3_set_field(*ol_type_vlan_len_msec, 759 HNS3_TXD_L2LEN_S, ol2_len >> 1); 760 761 /* compute OL3 header size, defined in 4 Bytes */ 762 ol3_len = l4.hdr - l3.hdr; 763 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, 764 ol3_len >> 2); 765 766 /* MAC in UDP, MAC in GRE (0x6558)*/ 767 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 768 /* switch MAC header ptr from outer to inner header.*/ 769 l2_hdr = skb_inner_mac_header(skb); 770 771 /* compute OL4 header size, defined in 4 Bytes. */ 772 ol4_len = l2_hdr - l4.hdr; 773 hns3_set_field(*ol_type_vlan_len_msec, 774 HNS3_TXD_L4LEN_S, ol4_len >> 2); 775 776 /* switch IP header ptr from outer to inner header */ 777 l3.hdr = skb_inner_network_header(skb); 778 779 /* compute inner l2 header size, defined in 2 Bytes. */ 780 l2_len = l3.hdr - l2_hdr; 781 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, 782 l2_len >> 1); 783 } else { 784 /* skb packet types not supported by hardware, 785 * txbd len fild doesn't be filled. 786 */ 787 return; 788 } 789 790 /* switch L4 header pointer from outer to inner */ 791 l4.hdr = skb_inner_transport_header(skb); 792 793 l4_proto = il4_proto; 794 } 795 796 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 797 l3_len = l4.hdr - l3.hdr; 798 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 799 800 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 801 switch (l4_proto) { 802 case IPPROTO_TCP: 803 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 804 l4.tcp->doff); 805 break; 806 case IPPROTO_SCTP: 807 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 808 (sizeof(struct sctphdr) >> 2)); 809 break; 810 case IPPROTO_UDP: 811 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 812 (sizeof(struct udphdr) >> 2)); 813 break; 814 default: 815 /* skb packet types not supported by hardware, 816 * txbd len fild doesn't be filled. 817 */ 818 return; 819 } 820 } 821 822 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 823 * and it is udp packet, which has a dest port as the IANA assigned. 824 * the hardware is expected to do the checksum offload, but the 825 * hardware will not do the checksum offload when udp dest port is 826 * 4789. 827 */ 828 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 829 { 830 union l4_hdr_info l4; 831 832 l4.hdr = skb_transport_header(skb); 833 834 if (!(!skb->encapsulation && 835 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 836 return false; 837 838 skb_checksum_help(skb); 839 840 return true; 841 } 842 843 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 844 u8 il4_proto, u32 *type_cs_vlan_tso, 845 u32 *ol_type_vlan_len_msec) 846 { 847 union l3_hdr_info l3; 848 u32 l4_proto = ol4_proto; 849 850 l3.hdr = skb_network_header(skb); 851 852 /* define OL3 type and tunnel type(OL4).*/ 853 if (skb->encapsulation) { 854 /* define outer network header type.*/ 855 if (skb->protocol == htons(ETH_P_IP)) { 856 if (skb_is_gso(skb)) 857 hns3_set_field(*ol_type_vlan_len_msec, 858 HNS3_TXD_OL3T_S, 859 HNS3_OL3T_IPV4_CSUM); 860 else 861 hns3_set_field(*ol_type_vlan_len_msec, 862 HNS3_TXD_OL3T_S, 863 HNS3_OL3T_IPV4_NO_CSUM); 864 865 } else if (skb->protocol == htons(ETH_P_IPV6)) { 866 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 867 HNS3_OL3T_IPV6); 868 } 869 870 /* define tunnel type(OL4).*/ 871 switch (l4_proto) { 872 case IPPROTO_UDP: 873 hns3_set_field(*ol_type_vlan_len_msec, 874 HNS3_TXD_TUNTYPE_S, 875 HNS3_TUN_MAC_IN_UDP); 876 break; 877 case IPPROTO_GRE: 878 hns3_set_field(*ol_type_vlan_len_msec, 879 HNS3_TXD_TUNTYPE_S, 880 HNS3_TUN_NVGRE); 881 break; 882 default: 883 /* drop the skb tunnel packet if hardware don't support, 884 * because hardware can't calculate csum when TSO. 885 */ 886 if (skb_is_gso(skb)) 887 return -EDOM; 888 889 /* the stack computes the IP header already, 890 * driver calculate l4 checksum when not TSO. 891 */ 892 skb_checksum_help(skb); 893 return 0; 894 } 895 896 l3.hdr = skb_inner_network_header(skb); 897 l4_proto = il4_proto; 898 } 899 900 if (l3.v4->version == 4) { 901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 902 HNS3_L3T_IPV4); 903 904 /* the stack computes the IP header already, the only time we 905 * need the hardware to recompute it is in the case of TSO. 906 */ 907 if (skb_is_gso(skb)) 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 909 } else if (l3.v6->version == 6) { 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 911 HNS3_L3T_IPV6); 912 } 913 914 switch (l4_proto) { 915 case IPPROTO_TCP: 916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 918 HNS3_L4T_TCP); 919 break; 920 case IPPROTO_UDP: 921 if (hns3_tunnel_csum_bug(skb)) 922 break; 923 924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 926 HNS3_L4T_UDP); 927 break; 928 case IPPROTO_SCTP: 929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 931 HNS3_L4T_SCTP); 932 break; 933 default: 934 /* drop the skb tunnel packet if hardware don't support, 935 * because hardware can't calculate csum when TSO. 936 */ 937 if (skb_is_gso(skb)) 938 return -EDOM; 939 940 /* the stack computes the IP header already, 941 * driver calculate l4 checksum when not TSO. 942 */ 943 skb_checksum_help(skb); 944 return 0; 945 } 946 947 return 0; 948 } 949 950 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 951 { 952 /* Config bd buffer end */ 953 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 954 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 955 } 956 957 static int hns3_fill_desc_vtags(struct sk_buff *skb, 958 struct hns3_enet_ring *tx_ring, 959 u32 *inner_vlan_flag, 960 u32 *out_vlan_flag, 961 u16 *inner_vtag, 962 u16 *out_vtag) 963 { 964 #define HNS3_TX_VLAN_PRIO_SHIFT 13 965 966 struct hnae3_handle *handle = tx_ring->tqp->handle; 967 968 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 969 * header is allowed in skb, otherwise it will cause RAS error. 970 */ 971 if (unlikely(skb_vlan_tagged_multi(skb) && 972 handle->port_base_vlan_state == 973 HNAE3_PORT_BASE_VLAN_ENABLE)) 974 return -EINVAL; 975 976 if (skb->protocol == htons(ETH_P_8021Q) && 977 !(tx_ring->tqp->handle->kinfo.netdev->features & 978 NETIF_F_HW_VLAN_CTAG_TX)) { 979 /* When HW VLAN acceleration is turned off, and the stack 980 * sets the protocol to 802.1q, the driver just need to 981 * set the protocol to the encapsulated ethertype. 982 */ 983 skb->protocol = vlan_get_protocol(skb); 984 return 0; 985 } 986 987 if (skb_vlan_tag_present(skb)) { 988 u16 vlan_tag; 989 990 vlan_tag = skb_vlan_tag_get(skb); 991 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 992 993 /* Based on hw strategy, use out_vtag in two layer tag case, 994 * and use inner_vtag in one tag case. 995 */ 996 if (skb->protocol == htons(ETH_P_8021Q)) { 997 if (handle->port_base_vlan_state == 998 HNAE3_PORT_BASE_VLAN_DISABLE){ 999 hns3_set_field(*out_vlan_flag, 1000 HNS3_TXD_OVLAN_B, 1); 1001 *out_vtag = vlan_tag; 1002 } else { 1003 hns3_set_field(*inner_vlan_flag, 1004 HNS3_TXD_VLAN_B, 1); 1005 *inner_vtag = vlan_tag; 1006 } 1007 } else { 1008 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 1009 *inner_vtag = vlan_tag; 1010 } 1011 } else if (skb->protocol == htons(ETH_P_8021Q)) { 1012 struct vlan_ethhdr *vhdr; 1013 int rc; 1014 1015 rc = skb_cow_head(skb, 0); 1016 if (unlikely(rc < 0)) 1017 return rc; 1018 vhdr = (struct vlan_ethhdr *)skb->data; 1019 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1020 << HNS3_TX_VLAN_PRIO_SHIFT); 1021 } 1022 1023 skb->protocol = vlan_get_protocol(skb); 1024 return 0; 1025 } 1026 1027 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1028 int size, int frag_end, enum hns_desc_type type) 1029 { 1030 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1031 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1032 struct device *dev = ring_to_dev(ring); 1033 struct skb_frag_struct *frag; 1034 unsigned int frag_buf_num; 1035 int k, sizeoflast; 1036 dma_addr_t dma; 1037 1038 if (type == DESC_TYPE_SKB) { 1039 struct sk_buff *skb = (struct sk_buff *)priv; 1040 u32 ol_type_vlan_len_msec = 0; 1041 u32 type_cs_vlan_tso = 0; 1042 u32 paylen = skb->len; 1043 u16 inner_vtag = 0; 1044 u16 out_vtag = 0; 1045 u16 mss = 0; 1046 int ret; 1047 1048 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1049 &ol_type_vlan_len_msec, 1050 &inner_vtag, &out_vtag); 1051 if (unlikely(ret)) 1052 return ret; 1053 1054 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1055 u8 ol4_proto, il4_proto; 1056 1057 skb_reset_mac_len(skb); 1058 1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1060 if (unlikely(ret)) 1061 return ret; 1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1063 &type_cs_vlan_tso, 1064 &ol_type_vlan_len_msec); 1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1066 &type_cs_vlan_tso, 1067 &ol_type_vlan_len_msec); 1068 if (unlikely(ret)) 1069 return ret; 1070 1071 ret = hns3_set_tso(skb, &paylen, &mss, 1072 &type_cs_vlan_tso); 1073 if (unlikely(ret)) 1074 return ret; 1075 } 1076 1077 /* Set txbd */ 1078 desc->tx.ol_type_vlan_len_msec = 1079 cpu_to_le32(ol_type_vlan_len_msec); 1080 desc->tx.type_cs_vlan_tso_len = 1081 cpu_to_le32(type_cs_vlan_tso); 1082 desc->tx.paylen = cpu_to_le32(paylen); 1083 desc->tx.mss = cpu_to_le16(mss); 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1086 1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1088 } else { 1089 frag = (struct skb_frag_struct *)priv; 1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1091 } 1092 1093 if (unlikely(dma_mapping_error(ring->dev, dma))) { 1094 ring->stats.sw_err_cnt++; 1095 return -ENOMEM; 1096 } 1097 1098 desc_cb->length = size; 1099 1100 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1101 u16 bdtp_fe_sc_vld_ra_ri = 0; 1102 1103 desc_cb->priv = priv; 1104 desc_cb->dma = dma; 1105 desc_cb->type = type; 1106 desc->addr = cpu_to_le64(dma); 1107 desc->tx.send_size = cpu_to_le16(size); 1108 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 1109 desc->tx.bdtp_fe_sc_vld_ra_ri = 1110 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1111 1112 ring_ptr_move_fw(ring, next_to_use); 1113 return 0; 1114 } 1115 1116 frag_buf_num = hns3_tx_bd_count(size); 1117 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1118 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1119 1120 /* When frag size is bigger than hardware limit, split this frag */ 1121 for (k = 0; k < frag_buf_num; k++) { 1122 u16 bdtp_fe_sc_vld_ra_ri = 0; 1123 1124 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1125 desc_cb->priv = priv; 1126 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1127 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1128 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1129 1130 /* now, fill the descriptor */ 1131 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1132 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1133 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1134 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1135 frag_end && (k == frag_buf_num - 1) ? 1136 1 : 0); 1137 desc->tx.bdtp_fe_sc_vld_ra_ri = 1138 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1139 1140 /* move ring pointer to next.*/ 1141 ring_ptr_move_fw(ring, next_to_use); 1142 1143 desc_cb = &ring->desc_cb[ring->next_to_use]; 1144 desc = &ring->desc[ring->next_to_use]; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1151 struct hns3_enet_ring *ring) 1152 { 1153 struct sk_buff *skb = *out_skb; 1154 struct sk_buff *new_skb = NULL; 1155 struct skb_frag_struct *frag; 1156 int bdnum_for_frag; 1157 int frag_num; 1158 int buf_num; 1159 int size; 1160 int i; 1161 1162 size = skb_headlen(skb); 1163 buf_num = hns3_tx_bd_count(size); 1164 1165 frag_num = skb_shinfo(skb)->nr_frags; 1166 for (i = 0; i < frag_num; i++) { 1167 frag = &skb_shinfo(skb)->frags[i]; 1168 size = skb_frag_size(frag); 1169 bdnum_for_frag = hns3_tx_bd_count(size); 1170 if (unlikely(bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)) 1171 return -ENOMEM; 1172 1173 buf_num += bdnum_for_frag; 1174 } 1175 1176 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1177 buf_num = hns3_tx_bd_count(skb->len); 1178 if (ring_space(ring) < buf_num) 1179 return -EBUSY; 1180 /* manual split the send packet */ 1181 new_skb = skb_copy(skb, GFP_ATOMIC); 1182 if (!new_skb) 1183 return -ENOMEM; 1184 dev_kfree_skb_any(skb); 1185 *out_skb = new_skb; 1186 } 1187 1188 if (unlikely(ring_space(ring) < buf_num)) 1189 return -EBUSY; 1190 1191 *bnum = buf_num; 1192 return 0; 1193 } 1194 1195 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1196 struct hns3_enet_ring *ring) 1197 { 1198 struct sk_buff *skb = *out_skb; 1199 struct sk_buff *new_skb = NULL; 1200 int buf_num; 1201 1202 /* No. of segments (plus a header) */ 1203 buf_num = skb_shinfo(skb)->nr_frags + 1; 1204 1205 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1206 buf_num = hns3_tx_bd_count(skb->len); 1207 if (ring_space(ring) < buf_num) 1208 return -EBUSY; 1209 /* manual split the send packet */ 1210 new_skb = skb_copy(skb, GFP_ATOMIC); 1211 if (!new_skb) 1212 return -ENOMEM; 1213 dev_kfree_skb_any(skb); 1214 *out_skb = new_skb; 1215 } 1216 1217 if (unlikely(ring_space(ring) < buf_num)) 1218 return -EBUSY; 1219 1220 *bnum = buf_num; 1221 1222 return 0; 1223 } 1224 1225 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1226 { 1227 struct device *dev = ring_to_dev(ring); 1228 unsigned int i; 1229 1230 for (i = 0; i < ring->desc_num; i++) { 1231 /* check if this is where we started */ 1232 if (ring->next_to_use == next_to_use_orig) 1233 break; 1234 1235 /* unmap the descriptor dma address */ 1236 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1237 dma_unmap_single(dev, 1238 ring->desc_cb[ring->next_to_use].dma, 1239 ring->desc_cb[ring->next_to_use].length, 1240 DMA_TO_DEVICE); 1241 else if (ring->desc_cb[ring->next_to_use].length) 1242 dma_unmap_page(dev, 1243 ring->desc_cb[ring->next_to_use].dma, 1244 ring->desc_cb[ring->next_to_use].length, 1245 DMA_TO_DEVICE); 1246 1247 ring->desc_cb[ring->next_to_use].length = 0; 1248 1249 /* rollback one */ 1250 ring_ptr_move_bw(ring, next_to_use); 1251 } 1252 } 1253 1254 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1255 { 1256 struct hns3_nic_priv *priv = netdev_priv(netdev); 1257 struct hns3_nic_ring_data *ring_data = 1258 &tx_ring_data(priv, skb->queue_mapping); 1259 struct hns3_enet_ring *ring = ring_data->ring; 1260 struct netdev_queue *dev_queue; 1261 struct skb_frag_struct *frag; 1262 int next_to_use_head; 1263 int next_to_use_frag; 1264 int buf_num; 1265 int seg_num; 1266 int size; 1267 int ret; 1268 int i; 1269 1270 /* Prefetch the data used later */ 1271 prefetch(skb->data); 1272 1273 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1274 case -EBUSY: 1275 u64_stats_update_begin(&ring->syncp); 1276 ring->stats.tx_busy++; 1277 u64_stats_update_end(&ring->syncp); 1278 1279 goto out_net_tx_busy; 1280 case -ENOMEM: 1281 u64_stats_update_begin(&ring->syncp); 1282 ring->stats.sw_err_cnt++; 1283 u64_stats_update_end(&ring->syncp); 1284 netdev_err(netdev, "no memory to xmit!\n"); 1285 1286 goto out_err_tx_ok; 1287 default: 1288 break; 1289 } 1290 1291 /* No. of segments (plus a header) */ 1292 seg_num = skb_shinfo(skb)->nr_frags + 1; 1293 /* Fill the first part */ 1294 size = skb_headlen(skb); 1295 1296 next_to_use_head = ring->next_to_use; 1297 1298 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1299 DESC_TYPE_SKB); 1300 if (unlikely(ret)) 1301 goto head_fill_err; 1302 1303 next_to_use_frag = ring->next_to_use; 1304 /* Fill the fragments */ 1305 for (i = 1; i < seg_num; i++) { 1306 frag = &skb_shinfo(skb)->frags[i - 1]; 1307 size = skb_frag_size(frag); 1308 1309 ret = hns3_fill_desc(ring, frag, size, 1310 seg_num - 1 == i ? 1 : 0, 1311 DESC_TYPE_PAGE); 1312 1313 if (unlikely(ret)) 1314 goto frag_fill_err; 1315 } 1316 1317 /* Complete translate all packets */ 1318 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1319 netdev_tx_sent_queue(dev_queue, skb->len); 1320 1321 wmb(); /* Commit all data before submit */ 1322 1323 hnae3_queue_xmit(ring->tqp, buf_num); 1324 1325 return NETDEV_TX_OK; 1326 1327 frag_fill_err: 1328 hns3_clear_desc(ring, next_to_use_frag); 1329 1330 head_fill_err: 1331 hns3_clear_desc(ring, next_to_use_head); 1332 1333 out_err_tx_ok: 1334 dev_kfree_skb_any(skb); 1335 return NETDEV_TX_OK; 1336 1337 out_net_tx_busy: 1338 netif_stop_subqueue(netdev, ring_data->queue_index); 1339 smp_mb(); /* Commit all data before submit */ 1340 1341 return NETDEV_TX_BUSY; 1342 } 1343 1344 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1345 { 1346 struct hnae3_handle *h = hns3_get_handle(netdev); 1347 struct sockaddr *mac_addr = p; 1348 int ret; 1349 1350 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1351 return -EADDRNOTAVAIL; 1352 1353 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1354 netdev_info(netdev, "already using mac address %pM\n", 1355 mac_addr->sa_data); 1356 return 0; 1357 } 1358 1359 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1360 if (ret) { 1361 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1362 return ret; 1363 } 1364 1365 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1366 1367 return 0; 1368 } 1369 1370 static int hns3_nic_do_ioctl(struct net_device *netdev, 1371 struct ifreq *ifr, int cmd) 1372 { 1373 struct hnae3_handle *h = hns3_get_handle(netdev); 1374 1375 if (!netif_running(netdev)) 1376 return -EINVAL; 1377 1378 if (!h->ae_algo->ops->do_ioctl) 1379 return -EOPNOTSUPP; 1380 1381 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1382 } 1383 1384 static int hns3_nic_set_features(struct net_device *netdev, 1385 netdev_features_t features) 1386 { 1387 netdev_features_t changed = netdev->features ^ features; 1388 struct hns3_nic_priv *priv = netdev_priv(netdev); 1389 struct hnae3_handle *h = priv->ae_handle; 1390 bool enable; 1391 int ret; 1392 1393 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1394 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1395 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1396 else 1397 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1398 } 1399 1400 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1401 enable = !!(features & NETIF_F_GRO_HW); 1402 ret = h->ae_algo->ops->set_gro_en(h, enable); 1403 if (ret) 1404 return ret; 1405 } 1406 1407 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1408 h->ae_algo->ops->enable_vlan_filter) { 1409 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1410 h->ae_algo->ops->enable_vlan_filter(h, enable); 1411 } 1412 1413 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1414 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1415 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1416 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1417 if (ret) 1418 return ret; 1419 } 1420 1421 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1422 enable = !!(features & NETIF_F_NTUPLE); 1423 h->ae_algo->ops->enable_fd(h, enable); 1424 } 1425 1426 netdev->features = features; 1427 return 0; 1428 } 1429 1430 static void hns3_nic_get_stats64(struct net_device *netdev, 1431 struct rtnl_link_stats64 *stats) 1432 { 1433 struct hns3_nic_priv *priv = netdev_priv(netdev); 1434 int queue_num = priv->ae_handle->kinfo.num_tqps; 1435 struct hnae3_handle *handle = priv->ae_handle; 1436 struct hns3_enet_ring *ring; 1437 u64 rx_length_errors = 0; 1438 u64 rx_crc_errors = 0; 1439 u64 rx_multicast = 0; 1440 unsigned int start; 1441 u64 tx_errors = 0; 1442 u64 rx_errors = 0; 1443 unsigned int idx; 1444 u64 tx_bytes = 0; 1445 u64 rx_bytes = 0; 1446 u64 tx_pkts = 0; 1447 u64 rx_pkts = 0; 1448 u64 tx_drop = 0; 1449 u64 rx_drop = 0; 1450 1451 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1452 return; 1453 1454 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1455 1456 for (idx = 0; idx < queue_num; idx++) { 1457 /* fetch the tx stats */ 1458 ring = priv->ring_data[idx].ring; 1459 do { 1460 start = u64_stats_fetch_begin_irq(&ring->syncp); 1461 tx_bytes += ring->stats.tx_bytes; 1462 tx_pkts += ring->stats.tx_pkts; 1463 tx_drop += ring->stats.sw_err_cnt; 1464 tx_errors += ring->stats.sw_err_cnt; 1465 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1466 1467 /* fetch the rx stats */ 1468 ring = priv->ring_data[idx + queue_num].ring; 1469 do { 1470 start = u64_stats_fetch_begin_irq(&ring->syncp); 1471 rx_bytes += ring->stats.rx_bytes; 1472 rx_pkts += ring->stats.rx_pkts; 1473 rx_drop += ring->stats.non_vld_descs; 1474 rx_drop += ring->stats.l2_err; 1475 rx_errors += ring->stats.non_vld_descs; 1476 rx_errors += ring->stats.l2_err; 1477 rx_crc_errors += ring->stats.l2_err; 1478 rx_crc_errors += ring->stats.l3l4_csum_err; 1479 rx_multicast += ring->stats.rx_multicast; 1480 rx_length_errors += ring->stats.err_pkt_len; 1481 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1482 } 1483 1484 stats->tx_bytes = tx_bytes; 1485 stats->tx_packets = tx_pkts; 1486 stats->rx_bytes = rx_bytes; 1487 stats->rx_packets = rx_pkts; 1488 1489 stats->rx_errors = rx_errors; 1490 stats->multicast = rx_multicast; 1491 stats->rx_length_errors = rx_length_errors; 1492 stats->rx_crc_errors = rx_crc_errors; 1493 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1494 1495 stats->tx_errors = tx_errors; 1496 stats->rx_dropped = rx_drop; 1497 stats->tx_dropped = tx_drop; 1498 stats->collisions = netdev->stats.collisions; 1499 stats->rx_over_errors = netdev->stats.rx_over_errors; 1500 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1501 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1502 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1503 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1504 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1505 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1506 stats->tx_window_errors = netdev->stats.tx_window_errors; 1507 stats->rx_compressed = netdev->stats.rx_compressed; 1508 stats->tx_compressed = netdev->stats.tx_compressed; 1509 } 1510 1511 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1512 { 1513 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1514 struct hnae3_handle *h = hns3_get_handle(netdev); 1515 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1516 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1517 u8 tc = mqprio_qopt->qopt.num_tc; 1518 u16 mode = mqprio_qopt->mode; 1519 u8 hw = mqprio_qopt->qopt.hw; 1520 1521 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1522 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1523 return -EOPNOTSUPP; 1524 1525 if (tc > HNAE3_MAX_TC) 1526 return -EINVAL; 1527 1528 if (!netdev) 1529 return -EINVAL; 1530 1531 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1532 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1533 } 1534 1535 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1536 void *type_data) 1537 { 1538 if (type != TC_SETUP_QDISC_MQPRIO) 1539 return -EOPNOTSUPP; 1540 1541 return hns3_setup_tc(dev, type_data); 1542 } 1543 1544 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1545 __be16 proto, u16 vid) 1546 { 1547 struct hnae3_handle *h = hns3_get_handle(netdev); 1548 struct hns3_nic_priv *priv = netdev_priv(netdev); 1549 int ret = -EIO; 1550 1551 if (h->ae_algo->ops->set_vlan_filter) 1552 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1553 1554 if (!ret) 1555 set_bit(vid, priv->active_vlans); 1556 1557 return ret; 1558 } 1559 1560 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1561 __be16 proto, u16 vid) 1562 { 1563 struct hnae3_handle *h = hns3_get_handle(netdev); 1564 struct hns3_nic_priv *priv = netdev_priv(netdev); 1565 int ret = -EIO; 1566 1567 if (h->ae_algo->ops->set_vlan_filter) 1568 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1569 1570 if (!ret) 1571 clear_bit(vid, priv->active_vlans); 1572 1573 return ret; 1574 } 1575 1576 static int hns3_restore_vlan(struct net_device *netdev) 1577 { 1578 struct hns3_nic_priv *priv = netdev_priv(netdev); 1579 int ret = 0; 1580 u16 vid; 1581 1582 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1583 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1584 if (ret) { 1585 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1586 vid, ret); 1587 return ret; 1588 } 1589 } 1590 1591 return ret; 1592 } 1593 1594 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1595 u8 qos, __be16 vlan_proto) 1596 { 1597 struct hnae3_handle *h = hns3_get_handle(netdev); 1598 int ret = -EIO; 1599 1600 if (h->ae_algo->ops->set_vf_vlan_filter) 1601 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1602 qos, vlan_proto); 1603 1604 return ret; 1605 } 1606 1607 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1608 { 1609 struct hnae3_handle *h = hns3_get_handle(netdev); 1610 int ret; 1611 1612 if (hns3_nic_resetting(netdev)) 1613 return -EBUSY; 1614 1615 if (!h->ae_algo->ops->set_mtu) 1616 return -EOPNOTSUPP; 1617 1618 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1619 if (ret) 1620 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1621 ret); 1622 else 1623 netdev->mtu = new_mtu; 1624 1625 return ret; 1626 } 1627 1628 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1629 { 1630 struct hns3_nic_priv *priv = netdev_priv(ndev); 1631 struct hns3_enet_ring *tx_ring = NULL; 1632 int timeout_queue = 0; 1633 int hw_head, hw_tail; 1634 int i; 1635 1636 /* Find the stopped queue the same way the stack does */ 1637 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1638 struct netdev_queue *q; 1639 unsigned long trans_start; 1640 1641 q = netdev_get_tx_queue(ndev, i); 1642 trans_start = q->trans_start; 1643 if (netif_xmit_stopped(q) && 1644 time_after(jiffies, 1645 (trans_start + ndev->watchdog_timeo))) { 1646 timeout_queue = i; 1647 break; 1648 } 1649 } 1650 1651 if (i == ndev->num_tx_queues) { 1652 netdev_info(ndev, 1653 "no netdev TX timeout queue found, timeout count: %llu\n", 1654 priv->tx_timeout_count); 1655 return false; 1656 } 1657 1658 tx_ring = priv->ring_data[timeout_queue].ring; 1659 1660 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1661 HNS3_RING_TX_RING_HEAD_REG); 1662 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1663 HNS3_RING_TX_RING_TAIL_REG); 1664 netdev_info(ndev, 1665 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1666 priv->tx_timeout_count, 1667 timeout_queue, 1668 tx_ring->next_to_use, 1669 tx_ring->next_to_clean, 1670 hw_head, 1671 hw_tail, 1672 readl(tx_ring->tqp_vector->mask_addr)); 1673 1674 return true; 1675 } 1676 1677 static void hns3_nic_net_timeout(struct net_device *ndev) 1678 { 1679 struct hns3_nic_priv *priv = netdev_priv(ndev); 1680 struct hnae3_handle *h = priv->ae_handle; 1681 1682 if (!hns3_get_tx_timeo_queue_info(ndev)) 1683 return; 1684 1685 priv->tx_timeout_count++; 1686 1687 /* request the reset, and let the hclge to determine 1688 * which reset level should be done 1689 */ 1690 if (h->ae_algo->ops->reset_event) 1691 h->ae_algo->ops->reset_event(h->pdev, h); 1692 } 1693 1694 static const struct net_device_ops hns3_nic_netdev_ops = { 1695 .ndo_open = hns3_nic_net_open, 1696 .ndo_stop = hns3_nic_net_stop, 1697 .ndo_start_xmit = hns3_nic_net_xmit, 1698 .ndo_tx_timeout = hns3_nic_net_timeout, 1699 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1700 .ndo_do_ioctl = hns3_nic_do_ioctl, 1701 .ndo_change_mtu = hns3_nic_change_mtu, 1702 .ndo_set_features = hns3_nic_set_features, 1703 .ndo_get_stats64 = hns3_nic_get_stats64, 1704 .ndo_setup_tc = hns3_nic_setup_tc, 1705 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1706 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1707 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1708 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1709 }; 1710 1711 static bool hns3_is_phys_func(struct pci_dev *pdev) 1712 { 1713 u32 dev_id = pdev->device; 1714 1715 switch (dev_id) { 1716 case HNAE3_DEV_ID_GE: 1717 case HNAE3_DEV_ID_25GE: 1718 case HNAE3_DEV_ID_25GE_RDMA: 1719 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1720 case HNAE3_DEV_ID_50GE_RDMA: 1721 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1722 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1723 return true; 1724 case HNAE3_DEV_ID_100G_VF: 1725 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1726 return false; 1727 default: 1728 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1729 dev_id); 1730 } 1731 1732 return false; 1733 } 1734 1735 static void hns3_disable_sriov(struct pci_dev *pdev) 1736 { 1737 /* If our VFs are assigned we cannot shut down SR-IOV 1738 * without causing issues, so just leave the hardware 1739 * available but disabled 1740 */ 1741 if (pci_vfs_assigned(pdev)) { 1742 dev_warn(&pdev->dev, 1743 "disabling driver while VFs are assigned\n"); 1744 return; 1745 } 1746 1747 pci_disable_sriov(pdev); 1748 } 1749 1750 static void hns3_get_dev_capability(struct pci_dev *pdev, 1751 struct hnae3_ae_dev *ae_dev) 1752 { 1753 if (pdev->revision >= 0x21) { 1754 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1755 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1756 } 1757 } 1758 1759 /* hns3_probe - Device initialization routine 1760 * @pdev: PCI device information struct 1761 * @ent: entry in hns3_pci_tbl 1762 * 1763 * hns3_probe initializes a PF identified by a pci_dev structure. 1764 * The OS initialization, configuring of the PF private structure, 1765 * and a hardware reset occur. 1766 * 1767 * Returns 0 on success, negative on failure 1768 */ 1769 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1770 { 1771 struct hnae3_ae_dev *ae_dev; 1772 int ret; 1773 1774 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1775 GFP_KERNEL); 1776 if (!ae_dev) { 1777 ret = -ENOMEM; 1778 return ret; 1779 } 1780 1781 ae_dev->pdev = pdev; 1782 ae_dev->flag = ent->driver_data; 1783 ae_dev->dev_type = HNAE3_DEV_KNIC; 1784 ae_dev->reset_type = HNAE3_NONE_RESET; 1785 hns3_get_dev_capability(pdev, ae_dev); 1786 pci_set_drvdata(pdev, ae_dev); 1787 1788 ret = hnae3_register_ae_dev(ae_dev); 1789 if (ret) { 1790 devm_kfree(&pdev->dev, ae_dev); 1791 pci_set_drvdata(pdev, NULL); 1792 } 1793 1794 return ret; 1795 } 1796 1797 /* hns3_remove - Device removal routine 1798 * @pdev: PCI device information struct 1799 */ 1800 static void hns3_remove(struct pci_dev *pdev) 1801 { 1802 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1803 1804 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1805 hns3_disable_sriov(pdev); 1806 1807 hnae3_unregister_ae_dev(ae_dev); 1808 pci_set_drvdata(pdev, NULL); 1809 } 1810 1811 /** 1812 * hns3_pci_sriov_configure 1813 * @pdev: pointer to a pci_dev structure 1814 * @num_vfs: number of VFs to allocate 1815 * 1816 * Enable or change the number of VFs. Called when the user updates the number 1817 * of VFs in sysfs. 1818 **/ 1819 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1820 { 1821 int ret; 1822 1823 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1824 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1825 return -EINVAL; 1826 } 1827 1828 if (num_vfs) { 1829 ret = pci_enable_sriov(pdev, num_vfs); 1830 if (ret) 1831 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1832 else 1833 return num_vfs; 1834 } else if (!pci_vfs_assigned(pdev)) { 1835 pci_disable_sriov(pdev); 1836 } else { 1837 dev_warn(&pdev->dev, 1838 "Unable to free VFs because some are assigned to VMs.\n"); 1839 } 1840 1841 return 0; 1842 } 1843 1844 static void hns3_shutdown(struct pci_dev *pdev) 1845 { 1846 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1847 1848 hnae3_unregister_ae_dev(ae_dev); 1849 devm_kfree(&pdev->dev, ae_dev); 1850 pci_set_drvdata(pdev, NULL); 1851 1852 if (system_state == SYSTEM_POWER_OFF) 1853 pci_set_power_state(pdev, PCI_D3hot); 1854 } 1855 1856 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1857 pci_channel_state_t state) 1858 { 1859 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1860 pci_ers_result_t ret; 1861 1862 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1863 1864 if (state == pci_channel_io_perm_failure) 1865 return PCI_ERS_RESULT_DISCONNECT; 1866 1867 if (!ae_dev) { 1868 dev_err(&pdev->dev, 1869 "Can't recover - error happened during device init\n"); 1870 return PCI_ERS_RESULT_NONE; 1871 } 1872 1873 if (ae_dev->ops->handle_hw_ras_error) 1874 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1875 else 1876 return PCI_ERS_RESULT_NONE; 1877 1878 return ret; 1879 } 1880 1881 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1882 { 1883 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1884 struct device *dev = &pdev->dev; 1885 1886 dev_info(dev, "requesting reset due to PCI error\n"); 1887 1888 /* request the reset */ 1889 if (ae_dev->ops->reset_event) { 1890 if (!ae_dev->override_pci_need_reset) 1891 ae_dev->ops->reset_event(pdev, NULL); 1892 1893 return PCI_ERS_RESULT_RECOVERED; 1894 } 1895 1896 return PCI_ERS_RESULT_DISCONNECT; 1897 } 1898 1899 static void hns3_reset_prepare(struct pci_dev *pdev) 1900 { 1901 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1902 1903 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1904 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1905 ae_dev->ops->flr_prepare(ae_dev); 1906 } 1907 1908 static void hns3_reset_done(struct pci_dev *pdev) 1909 { 1910 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1911 1912 dev_info(&pdev->dev, "hns3 flr done\n"); 1913 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1914 ae_dev->ops->flr_done(ae_dev); 1915 } 1916 1917 static const struct pci_error_handlers hns3_err_handler = { 1918 .error_detected = hns3_error_detected, 1919 .slot_reset = hns3_slot_reset, 1920 .reset_prepare = hns3_reset_prepare, 1921 .reset_done = hns3_reset_done, 1922 }; 1923 1924 static struct pci_driver hns3_driver = { 1925 .name = hns3_driver_name, 1926 .id_table = hns3_pci_tbl, 1927 .probe = hns3_probe, 1928 .remove = hns3_remove, 1929 .shutdown = hns3_shutdown, 1930 .sriov_configure = hns3_pci_sriov_configure, 1931 .err_handler = &hns3_err_handler, 1932 }; 1933 1934 /* set default feature to hns3 */ 1935 static void hns3_set_default_feature(struct net_device *netdev) 1936 { 1937 struct hnae3_handle *h = hns3_get_handle(netdev); 1938 struct pci_dev *pdev = h->pdev; 1939 1940 netdev->priv_flags |= IFF_UNICAST_FLT; 1941 1942 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1943 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1944 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1945 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1946 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1947 1948 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1949 1950 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1951 1952 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1953 NETIF_F_HW_VLAN_CTAG_FILTER | 1954 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1955 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1956 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1957 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1958 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1959 1960 netdev->vlan_features |= 1961 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1962 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1963 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1964 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1965 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1966 1967 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1968 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1969 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1970 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1971 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1972 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1973 1974 if (pdev->revision >= 0x21) { 1975 netdev->hw_features |= NETIF_F_GRO_HW; 1976 netdev->features |= NETIF_F_GRO_HW; 1977 1978 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1979 netdev->hw_features |= NETIF_F_NTUPLE; 1980 netdev->features |= NETIF_F_NTUPLE; 1981 } 1982 } 1983 } 1984 1985 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1986 struct hns3_desc_cb *cb) 1987 { 1988 unsigned int order = hnae3_page_order(ring); 1989 struct page *p; 1990 1991 p = dev_alloc_pages(order); 1992 if (!p) 1993 return -ENOMEM; 1994 1995 cb->priv = p; 1996 cb->page_offset = 0; 1997 cb->reuse_flag = 0; 1998 cb->buf = page_address(p); 1999 cb->length = hnae3_page_size(ring); 2000 cb->type = DESC_TYPE_PAGE; 2001 2002 return 0; 2003 } 2004 2005 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2006 struct hns3_desc_cb *cb) 2007 { 2008 if (cb->type == DESC_TYPE_SKB) 2009 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2010 else if (!HNAE3_IS_TX_RING(ring)) 2011 put_page((struct page *)cb->priv); 2012 memset(cb, 0, sizeof(*cb)); 2013 } 2014 2015 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2016 { 2017 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2018 cb->length, ring_to_dma_dir(ring)); 2019 2020 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2021 return -EIO; 2022 2023 return 0; 2024 } 2025 2026 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2027 struct hns3_desc_cb *cb) 2028 { 2029 if (cb->type == DESC_TYPE_SKB) 2030 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2031 ring_to_dma_dir(ring)); 2032 else if (cb->length) 2033 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2034 ring_to_dma_dir(ring)); 2035 } 2036 2037 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2038 { 2039 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2040 ring->desc[i].addr = 0; 2041 } 2042 2043 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2044 { 2045 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2046 2047 if (!ring->desc_cb[i].dma) 2048 return; 2049 2050 hns3_buffer_detach(ring, i); 2051 hns3_free_buffer(ring, cb); 2052 } 2053 2054 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2055 { 2056 int i; 2057 2058 for (i = 0; i < ring->desc_num; i++) 2059 hns3_free_buffer_detach(ring, i); 2060 } 2061 2062 /* free desc along with its attached buffer */ 2063 static void hns3_free_desc(struct hns3_enet_ring *ring) 2064 { 2065 int size = ring->desc_num * sizeof(ring->desc[0]); 2066 2067 hns3_free_buffers(ring); 2068 2069 if (ring->desc) { 2070 dma_free_coherent(ring_to_dev(ring), size, 2071 ring->desc, ring->desc_dma_addr); 2072 ring->desc = NULL; 2073 } 2074 } 2075 2076 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2077 { 2078 int size = ring->desc_num * sizeof(ring->desc[0]); 2079 2080 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2081 &ring->desc_dma_addr, GFP_KERNEL); 2082 if (!ring->desc) 2083 return -ENOMEM; 2084 2085 return 0; 2086 } 2087 2088 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2089 struct hns3_desc_cb *cb) 2090 { 2091 int ret; 2092 2093 ret = hns3_alloc_buffer(ring, cb); 2094 if (ret) 2095 goto out; 2096 2097 ret = hns3_map_buffer(ring, cb); 2098 if (ret) 2099 goto out_with_buf; 2100 2101 return 0; 2102 2103 out_with_buf: 2104 hns3_free_buffer(ring, cb); 2105 out: 2106 return ret; 2107 } 2108 2109 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2110 { 2111 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2112 2113 if (ret) 2114 return ret; 2115 2116 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2117 2118 return 0; 2119 } 2120 2121 /* Allocate memory for raw pkg, and map with dma */ 2122 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2123 { 2124 int i, j, ret; 2125 2126 for (i = 0; i < ring->desc_num; i++) { 2127 ret = hns3_alloc_buffer_attach(ring, i); 2128 if (ret) 2129 goto out_buffer_fail; 2130 } 2131 2132 return 0; 2133 2134 out_buffer_fail: 2135 for (j = i - 1; j >= 0; j--) 2136 hns3_free_buffer_detach(ring, j); 2137 return ret; 2138 } 2139 2140 /* detach a in-used buffer and replace with a reserved one */ 2141 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2142 struct hns3_desc_cb *res_cb) 2143 { 2144 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2145 ring->desc_cb[i] = *res_cb; 2146 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2147 ring->desc[i].rx.bd_base_info = 0; 2148 } 2149 2150 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2151 { 2152 ring->desc_cb[i].reuse_flag = 0; 2153 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2154 + ring->desc_cb[i].page_offset); 2155 ring->desc[i].rx.bd_base_info = 0; 2156 } 2157 2158 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2159 int *pkts) 2160 { 2161 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2162 2163 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2164 (*bytes) += desc_cb->length; 2165 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2166 hns3_free_buffer_detach(ring, ring->next_to_clean); 2167 2168 ring_ptr_move_fw(ring, next_to_clean); 2169 } 2170 2171 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2172 { 2173 int u = ring->next_to_use; 2174 int c = ring->next_to_clean; 2175 2176 if (unlikely(h > ring->desc_num)) 2177 return 0; 2178 2179 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2180 } 2181 2182 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2183 { 2184 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2185 struct hns3_nic_priv *priv = netdev_priv(netdev); 2186 struct netdev_queue *dev_queue; 2187 int bytes, pkts; 2188 int head; 2189 2190 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2191 rmb(); /* Make sure head is ready before touch any data */ 2192 2193 if (is_ring_empty(ring) || head == ring->next_to_clean) 2194 return; /* no data to poll */ 2195 2196 if (unlikely(!is_valid_clean_head(ring, head))) { 2197 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2198 ring->next_to_use, ring->next_to_clean); 2199 2200 u64_stats_update_begin(&ring->syncp); 2201 ring->stats.io_err_cnt++; 2202 u64_stats_update_end(&ring->syncp); 2203 return; 2204 } 2205 2206 bytes = 0; 2207 pkts = 0; 2208 while (head != ring->next_to_clean) { 2209 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2210 /* Issue prefetch for next Tx descriptor */ 2211 prefetch(&ring->desc_cb[ring->next_to_clean]); 2212 } 2213 2214 ring->tqp_vector->tx_group.total_bytes += bytes; 2215 ring->tqp_vector->tx_group.total_packets += pkts; 2216 2217 u64_stats_update_begin(&ring->syncp); 2218 ring->stats.tx_bytes += bytes; 2219 ring->stats.tx_pkts += pkts; 2220 u64_stats_update_end(&ring->syncp); 2221 2222 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2223 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2224 2225 if (unlikely(pkts && netif_carrier_ok(netdev) && 2226 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2227 /* Make sure that anybody stopping the queue after this 2228 * sees the new next_to_clean. 2229 */ 2230 smp_mb(); 2231 if (netif_tx_queue_stopped(dev_queue) && 2232 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2233 netif_tx_wake_queue(dev_queue); 2234 ring->stats.restart_queue++; 2235 } 2236 } 2237 } 2238 2239 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2240 { 2241 int ntc = ring->next_to_clean; 2242 int ntu = ring->next_to_use; 2243 2244 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2245 } 2246 2247 static void 2248 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2249 { 2250 struct hns3_desc_cb *desc_cb; 2251 struct hns3_desc_cb res_cbs; 2252 int i, ret; 2253 2254 for (i = 0; i < cleand_count; i++) { 2255 desc_cb = &ring->desc_cb[ring->next_to_use]; 2256 if (desc_cb->reuse_flag) { 2257 u64_stats_update_begin(&ring->syncp); 2258 ring->stats.reuse_pg_cnt++; 2259 u64_stats_update_end(&ring->syncp); 2260 2261 hns3_reuse_buffer(ring, ring->next_to_use); 2262 } else { 2263 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2264 if (ret) { 2265 u64_stats_update_begin(&ring->syncp); 2266 ring->stats.sw_err_cnt++; 2267 u64_stats_update_end(&ring->syncp); 2268 2269 netdev_err(ring->tqp->handle->kinfo.netdev, 2270 "hnae reserve buffer map failed.\n"); 2271 break; 2272 } 2273 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2274 } 2275 2276 ring_ptr_move_fw(ring, next_to_use); 2277 } 2278 2279 wmb(); /* Make all data has been write before submit */ 2280 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2281 } 2282 2283 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2284 struct hns3_enet_ring *ring, int pull_len, 2285 struct hns3_desc_cb *desc_cb) 2286 { 2287 struct hns3_desc *desc; 2288 u32 truesize; 2289 int size; 2290 int last_offset; 2291 bool twobufs; 2292 2293 twobufs = ((PAGE_SIZE < 8192) && 2294 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2295 2296 desc = &ring->desc[ring->next_to_clean]; 2297 size = le16_to_cpu(desc->rx.size); 2298 2299 truesize = hnae3_buf_size(ring); 2300 2301 if (!twobufs) 2302 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2303 2304 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2305 size - pull_len, truesize); 2306 2307 /* Avoid re-using remote pages,flag default unreuse */ 2308 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2309 return; 2310 2311 if (twobufs) { 2312 /* If we are only owner of page we can reuse it */ 2313 if (likely(page_count(desc_cb->priv) == 1)) { 2314 /* Flip page offset to other buffer */ 2315 desc_cb->page_offset ^= truesize; 2316 2317 desc_cb->reuse_flag = 1; 2318 /* bump ref count on page before it is given*/ 2319 get_page(desc_cb->priv); 2320 } 2321 return; 2322 } 2323 2324 /* Move offset up to the next cache line */ 2325 desc_cb->page_offset += truesize; 2326 2327 if (desc_cb->page_offset <= last_offset) { 2328 desc_cb->reuse_flag = 1; 2329 /* Bump ref count on page before it is given*/ 2330 get_page(desc_cb->priv); 2331 } 2332 } 2333 2334 static int hns3_gro_complete(struct sk_buff *skb) 2335 { 2336 __be16 type = skb->protocol; 2337 struct tcphdr *th; 2338 int depth = 0; 2339 2340 while (type == htons(ETH_P_8021Q)) { 2341 struct vlan_hdr *vh; 2342 2343 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2344 return -EFAULT; 2345 2346 vh = (struct vlan_hdr *)(skb->data + depth); 2347 type = vh->h_vlan_encapsulated_proto; 2348 depth += VLAN_HLEN; 2349 } 2350 2351 if (type == htons(ETH_P_IP)) { 2352 depth += sizeof(struct iphdr); 2353 } else if (type == htons(ETH_P_IPV6)) { 2354 depth += sizeof(struct ipv6hdr); 2355 } else { 2356 netdev_err(skb->dev, 2357 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2358 be16_to_cpu(type), depth); 2359 return -EFAULT; 2360 } 2361 2362 th = (struct tcphdr *)(skb->data + depth); 2363 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2364 if (th->cwr) 2365 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2366 2367 skb->ip_summed = CHECKSUM_UNNECESSARY; 2368 2369 return 0; 2370 } 2371 2372 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2373 u32 l234info, u32 bd_base_info) 2374 { 2375 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2376 int l3_type, l4_type; 2377 int ol4_type; 2378 2379 skb->ip_summed = CHECKSUM_NONE; 2380 2381 skb_checksum_none_assert(skb); 2382 2383 if (!(netdev->features & NETIF_F_RXCSUM)) 2384 return; 2385 2386 /* check if hardware has done checksum */ 2387 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2388 return; 2389 2390 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2391 BIT(HNS3_RXD_OL3E_B) | 2392 BIT(HNS3_RXD_OL4E_B)))) { 2393 u64_stats_update_begin(&ring->syncp); 2394 ring->stats.l3l4_csum_err++; 2395 u64_stats_update_end(&ring->syncp); 2396 2397 return; 2398 } 2399 2400 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2401 HNS3_RXD_OL4ID_S); 2402 switch (ol4_type) { 2403 case HNS3_OL4_TYPE_MAC_IN_UDP: 2404 case HNS3_OL4_TYPE_NVGRE: 2405 skb->csum_level = 1; 2406 /* fall through */ 2407 case HNS3_OL4_TYPE_NO_TUN: 2408 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2409 HNS3_RXD_L3ID_S); 2410 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2411 HNS3_RXD_L4ID_S); 2412 2413 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2414 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2415 l3_type == HNS3_L3_TYPE_IPV6) && 2416 (l4_type == HNS3_L4_TYPE_UDP || 2417 l4_type == HNS3_L4_TYPE_TCP || 2418 l4_type == HNS3_L4_TYPE_SCTP)) 2419 skb->ip_summed = CHECKSUM_UNNECESSARY; 2420 break; 2421 default: 2422 break; 2423 } 2424 } 2425 2426 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2427 { 2428 if (skb_has_frag_list(skb)) 2429 napi_gro_flush(&ring->tqp_vector->napi, false); 2430 2431 napi_gro_receive(&ring->tqp_vector->napi, skb); 2432 } 2433 2434 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2435 struct hns3_desc *desc, u32 l234info, 2436 u16 *vlan_tag) 2437 { 2438 struct hnae3_handle *handle = ring->tqp->handle; 2439 struct pci_dev *pdev = ring->tqp->handle->pdev; 2440 2441 if (pdev->revision == 0x20) { 2442 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2443 if (!(*vlan_tag & VLAN_VID_MASK)) 2444 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2445 2446 return (*vlan_tag != 0); 2447 } 2448 2449 #define HNS3_STRP_OUTER_VLAN 0x1 2450 #define HNS3_STRP_INNER_VLAN 0x2 2451 #define HNS3_STRP_BOTH 0x3 2452 2453 /* Hardware always insert VLAN tag into RX descriptor when 2454 * remove the tag from packet, driver needs to determine 2455 * reporting which tag to stack. 2456 */ 2457 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2458 HNS3_RXD_STRP_TAGP_S)) { 2459 case HNS3_STRP_OUTER_VLAN: 2460 if (handle->port_base_vlan_state != 2461 HNAE3_PORT_BASE_VLAN_DISABLE) 2462 return false; 2463 2464 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2465 return true; 2466 case HNS3_STRP_INNER_VLAN: 2467 if (handle->port_base_vlan_state != 2468 HNAE3_PORT_BASE_VLAN_DISABLE) 2469 return false; 2470 2471 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2472 return true; 2473 case HNS3_STRP_BOTH: 2474 if (handle->port_base_vlan_state == 2475 HNAE3_PORT_BASE_VLAN_DISABLE) 2476 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2477 else 2478 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2479 2480 return true; 2481 default: 2482 return false; 2483 } 2484 } 2485 2486 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2487 unsigned char *va) 2488 { 2489 #define HNS3_NEED_ADD_FRAG 1 2490 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2491 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2492 struct sk_buff *skb; 2493 2494 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2495 skb = ring->skb; 2496 if (unlikely(!skb)) { 2497 netdev_err(netdev, "alloc rx skb fail\n"); 2498 2499 u64_stats_update_begin(&ring->syncp); 2500 ring->stats.sw_err_cnt++; 2501 u64_stats_update_end(&ring->syncp); 2502 2503 return -ENOMEM; 2504 } 2505 2506 prefetchw(skb->data); 2507 2508 ring->pending_buf = 1; 2509 ring->frag_num = 0; 2510 ring->tail_skb = NULL; 2511 if (length <= HNS3_RX_HEAD_SIZE) { 2512 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2513 2514 /* We can reuse buffer as-is, just make sure it is local */ 2515 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2516 desc_cb->reuse_flag = 1; 2517 else /* This page cannot be reused so discard it */ 2518 put_page(desc_cb->priv); 2519 2520 ring_ptr_move_fw(ring, next_to_clean); 2521 return 0; 2522 } 2523 u64_stats_update_begin(&ring->syncp); 2524 ring->stats.seg_pkt_cnt++; 2525 u64_stats_update_end(&ring->syncp); 2526 2527 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2528 __skb_put(skb, ring->pull_len); 2529 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2530 desc_cb); 2531 ring_ptr_move_fw(ring, next_to_clean); 2532 2533 return HNS3_NEED_ADD_FRAG; 2534 } 2535 2536 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2537 struct sk_buff **out_skb, bool pending) 2538 { 2539 struct sk_buff *skb = *out_skb; 2540 struct sk_buff *head_skb = *out_skb; 2541 struct sk_buff *new_skb; 2542 struct hns3_desc_cb *desc_cb; 2543 struct hns3_desc *pre_desc; 2544 u32 bd_base_info; 2545 int pre_bd; 2546 2547 /* if there is pending bd, the SW param next_to_clean has moved 2548 * to next and the next is NULL 2549 */ 2550 if (pending) { 2551 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2552 ring->desc_num; 2553 pre_desc = &ring->desc[pre_bd]; 2554 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2555 } else { 2556 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2557 } 2558 2559 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2560 desc = &ring->desc[ring->next_to_clean]; 2561 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2562 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2563 /* make sure HW write desc complete */ 2564 dma_rmb(); 2565 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2566 return -ENXIO; 2567 2568 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2569 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2570 HNS3_RX_HEAD_SIZE); 2571 if (unlikely(!new_skb)) { 2572 netdev_err(ring->tqp->handle->kinfo.netdev, 2573 "alloc rx skb frag fail\n"); 2574 return -ENXIO; 2575 } 2576 ring->frag_num = 0; 2577 2578 if (ring->tail_skb) { 2579 ring->tail_skb->next = new_skb; 2580 ring->tail_skb = new_skb; 2581 } else { 2582 skb_shinfo(skb)->frag_list = new_skb; 2583 ring->tail_skb = new_skb; 2584 } 2585 } 2586 2587 if (ring->tail_skb) { 2588 head_skb->truesize += hnae3_buf_size(ring); 2589 head_skb->data_len += le16_to_cpu(desc->rx.size); 2590 head_skb->len += le16_to_cpu(desc->rx.size); 2591 skb = ring->tail_skb; 2592 } 2593 2594 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2595 ring_ptr_move_fw(ring, next_to_clean); 2596 ring->pending_buf++; 2597 } 2598 2599 return 0; 2600 } 2601 2602 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2603 struct sk_buff *skb, u32 l234info, 2604 u32 bd_base_info) 2605 { 2606 u16 gro_count; 2607 u32 l3_type; 2608 2609 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2610 HNS3_RXD_GRO_COUNT_S); 2611 /* if there is no HW GRO, do not set gro params */ 2612 if (!gro_count) { 2613 hns3_rx_checksum(ring, skb, l234info, bd_base_info); 2614 return 0; 2615 } 2616 2617 NAPI_GRO_CB(skb)->count = gro_count; 2618 2619 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2620 HNS3_RXD_L3ID_S); 2621 if (l3_type == HNS3_L3_TYPE_IPV4) 2622 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2623 else if (l3_type == HNS3_L3_TYPE_IPV6) 2624 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2625 else 2626 return -EFAULT; 2627 2628 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2629 HNS3_RXD_GRO_SIZE_M, 2630 HNS3_RXD_GRO_SIZE_S); 2631 2632 return hns3_gro_complete(skb); 2633 } 2634 2635 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2636 struct sk_buff *skb) 2637 { 2638 struct hnae3_handle *handle = ring->tqp->handle; 2639 enum pkt_hash_types rss_type; 2640 struct hns3_desc *desc; 2641 int last_bd; 2642 2643 /* When driver handle the rss type, ring->next_to_clean indicates the 2644 * first descriptor of next packet, need -1 here. 2645 */ 2646 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num; 2647 desc = &ring->desc[last_bd]; 2648 2649 if (le32_to_cpu(desc->rx.rss_hash)) 2650 rss_type = handle->kinfo.rss_type; 2651 else 2652 rss_type = PKT_HASH_TYPE_NONE; 2653 2654 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2655 } 2656 2657 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb, 2658 struct hns3_desc *desc) 2659 { 2660 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2661 u32 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2662 u32 l234info = le32_to_cpu(desc->rx.l234_info); 2663 enum hns3_pkt_l2t_type l2_frame_type; 2664 unsigned int len; 2665 int ret; 2666 2667 /* Based on hw strategy, the tag offloaded will be stored at 2668 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2669 * in one layer tag case. 2670 */ 2671 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2672 u16 vlan_tag; 2673 2674 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2675 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2676 vlan_tag); 2677 } 2678 2679 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) { 2680 u64_stats_update_begin(&ring->syncp); 2681 ring->stats.non_vld_descs++; 2682 u64_stats_update_end(&ring->syncp); 2683 2684 return -EINVAL; 2685 } 2686 2687 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2688 BIT(HNS3_RXD_L2E_B))))) { 2689 u64_stats_update_begin(&ring->syncp); 2690 if (l234info & BIT(HNS3_RXD_L2E_B)) 2691 ring->stats.l2_err++; 2692 else 2693 ring->stats.err_pkt_len++; 2694 u64_stats_update_end(&ring->syncp); 2695 2696 return -EFAULT; 2697 } 2698 2699 len = skb->len; 2700 2701 /* Do update ip stack process */ 2702 skb->protocol = eth_type_trans(skb, netdev); 2703 2704 /* This is needed in order to enable forwarding support */ 2705 ret = hns3_set_gro_and_checksum(ring, skb, l234info, bd_base_info); 2706 if (unlikely(ret)) { 2707 u64_stats_update_begin(&ring->syncp); 2708 ring->stats.rx_err_cnt++; 2709 u64_stats_update_end(&ring->syncp); 2710 return ret; 2711 } 2712 2713 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2714 HNS3_RXD_DMAC_S); 2715 2716 u64_stats_update_begin(&ring->syncp); 2717 ring->stats.rx_pkts++; 2718 ring->stats.rx_bytes += len; 2719 2720 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2721 ring->stats.rx_multicast++; 2722 2723 u64_stats_update_end(&ring->syncp); 2724 2725 ring->tqp_vector->rx_group.total_bytes += len; 2726 return 0; 2727 } 2728 2729 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2730 struct sk_buff **out_skb) 2731 { 2732 struct sk_buff *skb = ring->skb; 2733 struct hns3_desc_cb *desc_cb; 2734 struct hns3_desc *desc; 2735 u32 bd_base_info; 2736 int length; 2737 int ret; 2738 2739 desc = &ring->desc[ring->next_to_clean]; 2740 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2741 2742 prefetch(desc); 2743 2744 length = le16_to_cpu(desc->rx.size); 2745 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2746 2747 /* Check valid BD */ 2748 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2749 return -ENXIO; 2750 2751 if (!skb) 2752 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2753 2754 /* Prefetch first cache line of first page 2755 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2756 * line size is 64B so need to prefetch twice to make it 128B. But in 2757 * actual we can have greater size of caches with 128B Level 1 cache 2758 * lines. In such a case, single fetch would suffice to cache in the 2759 * relevant part of the header. 2760 */ 2761 prefetch(ring->va); 2762 #if L1_CACHE_BYTES < 128 2763 prefetch(ring->va + L1_CACHE_BYTES); 2764 #endif 2765 2766 if (!skb) { 2767 ret = hns3_alloc_skb(ring, length, ring->va); 2768 *out_skb = skb = ring->skb; 2769 2770 if (ret < 0) /* alloc buffer fail */ 2771 return ret; 2772 if (ret > 0) { /* need add frag */ 2773 ret = hns3_add_frag(ring, desc, &skb, false); 2774 if (ret) 2775 return ret; 2776 2777 /* As the head data may be changed when GRO enable, copy 2778 * the head data in after other data rx completed 2779 */ 2780 memcpy(skb->data, ring->va, 2781 ALIGN(ring->pull_len, sizeof(long))); 2782 } 2783 } else { 2784 ret = hns3_add_frag(ring, desc, &skb, true); 2785 if (ret) 2786 return ret; 2787 2788 /* As the head data may be changed when GRO enable, copy 2789 * the head data in after other data rx completed 2790 */ 2791 memcpy(skb->data, ring->va, 2792 ALIGN(ring->pull_len, sizeof(long))); 2793 } 2794 2795 ret = hns3_handle_bdinfo(ring, skb, desc); 2796 if (unlikely(ret)) { 2797 dev_kfree_skb_any(skb); 2798 return ret; 2799 } 2800 2801 *out_skb = skb; 2802 hns3_set_rx_skb_rss_type(ring, skb); 2803 2804 return 0; 2805 } 2806 2807 int hns3_clean_rx_ring( 2808 struct hns3_enet_ring *ring, int budget, 2809 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2810 { 2811 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2812 int recv_pkts, recv_bds, clean_count, err; 2813 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2814 struct sk_buff *skb = ring->skb; 2815 int num; 2816 2817 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2818 rmb(); /* Make sure num taken effect before the other data is touched */ 2819 2820 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2821 num -= unused_count; 2822 2823 while (recv_pkts < budget && recv_bds < num) { 2824 /* Reuse or realloc buffers */ 2825 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2826 hns3_nic_alloc_rx_buffers(ring, 2827 clean_count + unused_count); 2828 clean_count = 0; 2829 unused_count = hns3_desc_unused(ring) - 2830 ring->pending_buf; 2831 } 2832 2833 /* Poll one pkt */ 2834 err = hns3_handle_rx_bd(ring, &skb); 2835 if (unlikely(!skb)) /* This fault cannot be repaired */ 2836 goto out; 2837 2838 if (err == -ENXIO) { /* Do not get FE for the packet */ 2839 goto out; 2840 } else if (unlikely(err)) { /* Do jump the err */ 2841 recv_bds += ring->pending_buf; 2842 clean_count += ring->pending_buf; 2843 ring->skb = NULL; 2844 ring->pending_buf = 0; 2845 continue; 2846 } 2847 2848 rx_fn(ring, skb); 2849 recv_bds += ring->pending_buf; 2850 clean_count += ring->pending_buf; 2851 ring->skb = NULL; 2852 ring->pending_buf = 0; 2853 2854 recv_pkts++; 2855 } 2856 2857 out: 2858 /* Make all data has been write before submit */ 2859 if (clean_count + unused_count > 0) 2860 hns3_nic_alloc_rx_buffers(ring, 2861 clean_count + unused_count); 2862 2863 return recv_pkts; 2864 } 2865 2866 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2867 { 2868 struct hns3_enet_tqp_vector *tqp_vector = 2869 ring_group->ring->tqp_vector; 2870 enum hns3_flow_level_range new_flow_level; 2871 int packets_per_msecs; 2872 int bytes_per_msecs; 2873 u32 time_passed_ms; 2874 u16 new_int_gl; 2875 2876 if (!tqp_vector->last_jiffies) 2877 return false; 2878 2879 if (ring_group->total_packets == 0) { 2880 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2881 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2882 return true; 2883 } 2884 2885 /* Simple throttlerate management 2886 * 0-10MB/s lower (50000 ints/s) 2887 * 10-20MB/s middle (20000 ints/s) 2888 * 20-1249MB/s high (18000 ints/s) 2889 * > 40000pps ultra (8000 ints/s) 2890 */ 2891 new_flow_level = ring_group->coal.flow_level; 2892 new_int_gl = ring_group->coal.int_gl; 2893 time_passed_ms = 2894 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2895 2896 if (!time_passed_ms) 2897 return false; 2898 2899 do_div(ring_group->total_packets, time_passed_ms); 2900 packets_per_msecs = ring_group->total_packets; 2901 2902 do_div(ring_group->total_bytes, time_passed_ms); 2903 bytes_per_msecs = ring_group->total_bytes; 2904 2905 #define HNS3_RX_LOW_BYTE_RATE 10000 2906 #define HNS3_RX_MID_BYTE_RATE 20000 2907 2908 switch (new_flow_level) { 2909 case HNS3_FLOW_LOW: 2910 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2911 new_flow_level = HNS3_FLOW_MID; 2912 break; 2913 case HNS3_FLOW_MID: 2914 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2915 new_flow_level = HNS3_FLOW_HIGH; 2916 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2917 new_flow_level = HNS3_FLOW_LOW; 2918 break; 2919 case HNS3_FLOW_HIGH: 2920 case HNS3_FLOW_ULTRA: 2921 default: 2922 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2923 new_flow_level = HNS3_FLOW_MID; 2924 break; 2925 } 2926 2927 #define HNS3_RX_ULTRA_PACKET_RATE 40 2928 2929 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2930 &tqp_vector->rx_group == ring_group) 2931 new_flow_level = HNS3_FLOW_ULTRA; 2932 2933 switch (new_flow_level) { 2934 case HNS3_FLOW_LOW: 2935 new_int_gl = HNS3_INT_GL_50K; 2936 break; 2937 case HNS3_FLOW_MID: 2938 new_int_gl = HNS3_INT_GL_20K; 2939 break; 2940 case HNS3_FLOW_HIGH: 2941 new_int_gl = HNS3_INT_GL_18K; 2942 break; 2943 case HNS3_FLOW_ULTRA: 2944 new_int_gl = HNS3_INT_GL_8K; 2945 break; 2946 default: 2947 break; 2948 } 2949 2950 ring_group->total_bytes = 0; 2951 ring_group->total_packets = 0; 2952 ring_group->coal.flow_level = new_flow_level; 2953 if (new_int_gl != ring_group->coal.int_gl) { 2954 ring_group->coal.int_gl = new_int_gl; 2955 return true; 2956 } 2957 return false; 2958 } 2959 2960 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2961 { 2962 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2963 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2964 bool rx_update, tx_update; 2965 2966 /* update param every 1000ms */ 2967 if (time_before(jiffies, 2968 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 2969 return; 2970 2971 if (rx_group->coal.gl_adapt_enable) { 2972 rx_update = hns3_get_new_int_gl(rx_group); 2973 if (rx_update) 2974 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2975 rx_group->coal.int_gl); 2976 } 2977 2978 if (tx_group->coal.gl_adapt_enable) { 2979 tx_update = hns3_get_new_int_gl(tx_group); 2980 if (tx_update) 2981 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2982 tx_group->coal.int_gl); 2983 } 2984 2985 tqp_vector->last_jiffies = jiffies; 2986 } 2987 2988 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2989 { 2990 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2991 struct hns3_enet_ring *ring; 2992 int rx_pkt_total = 0; 2993 2994 struct hns3_enet_tqp_vector *tqp_vector = 2995 container_of(napi, struct hns3_enet_tqp_vector, napi); 2996 bool clean_complete = true; 2997 int rx_budget = budget; 2998 2999 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3000 napi_complete(napi); 3001 return 0; 3002 } 3003 3004 /* Since the actual Tx work is minimal, we can give the Tx a larger 3005 * budget and be more aggressive about cleaning up the Tx descriptors. 3006 */ 3007 hns3_for_each_ring(ring, tqp_vector->tx_group) 3008 hns3_clean_tx_ring(ring); 3009 3010 /* make sure rx ring budget not smaller than 1 */ 3011 if (tqp_vector->num_tqps > 1) 3012 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3013 3014 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3015 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3016 hns3_rx_skb); 3017 3018 if (rx_cleaned >= rx_budget) 3019 clean_complete = false; 3020 3021 rx_pkt_total += rx_cleaned; 3022 } 3023 3024 tqp_vector->rx_group.total_packets += rx_pkt_total; 3025 3026 if (!clean_complete) 3027 return budget; 3028 3029 if (napi_complete(napi) && 3030 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3031 hns3_update_new_int_gl(tqp_vector); 3032 hns3_mask_vector_irq(tqp_vector, 1); 3033 } 3034 3035 return rx_pkt_total; 3036 } 3037 3038 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3039 struct hnae3_ring_chain_node *head) 3040 { 3041 struct pci_dev *pdev = tqp_vector->handle->pdev; 3042 struct hnae3_ring_chain_node *cur_chain = head; 3043 struct hnae3_ring_chain_node *chain; 3044 struct hns3_enet_ring *tx_ring; 3045 struct hns3_enet_ring *rx_ring; 3046 3047 tx_ring = tqp_vector->tx_group.ring; 3048 if (tx_ring) { 3049 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3050 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3051 HNAE3_RING_TYPE_TX); 3052 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3053 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3054 3055 cur_chain->next = NULL; 3056 3057 while (tx_ring->next) { 3058 tx_ring = tx_ring->next; 3059 3060 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3061 GFP_KERNEL); 3062 if (!chain) 3063 goto err_free_chain; 3064 3065 cur_chain->next = chain; 3066 chain->tqp_index = tx_ring->tqp->tqp_index; 3067 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3068 HNAE3_RING_TYPE_TX); 3069 hnae3_set_field(chain->int_gl_idx, 3070 HNAE3_RING_GL_IDX_M, 3071 HNAE3_RING_GL_IDX_S, 3072 HNAE3_RING_GL_TX); 3073 3074 cur_chain = chain; 3075 } 3076 } 3077 3078 rx_ring = tqp_vector->rx_group.ring; 3079 if (!tx_ring && rx_ring) { 3080 cur_chain->next = NULL; 3081 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3082 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3083 HNAE3_RING_TYPE_RX); 3084 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3085 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3086 3087 rx_ring = rx_ring->next; 3088 } 3089 3090 while (rx_ring) { 3091 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3092 if (!chain) 3093 goto err_free_chain; 3094 3095 cur_chain->next = chain; 3096 chain->tqp_index = rx_ring->tqp->tqp_index; 3097 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3098 HNAE3_RING_TYPE_RX); 3099 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3100 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3101 3102 cur_chain = chain; 3103 3104 rx_ring = rx_ring->next; 3105 } 3106 3107 return 0; 3108 3109 err_free_chain: 3110 cur_chain = head->next; 3111 while (cur_chain) { 3112 chain = cur_chain->next; 3113 devm_kfree(&pdev->dev, cur_chain); 3114 cur_chain = chain; 3115 } 3116 head->next = NULL; 3117 3118 return -ENOMEM; 3119 } 3120 3121 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3122 struct hnae3_ring_chain_node *head) 3123 { 3124 struct pci_dev *pdev = tqp_vector->handle->pdev; 3125 struct hnae3_ring_chain_node *chain_tmp, *chain; 3126 3127 chain = head->next; 3128 3129 while (chain) { 3130 chain_tmp = chain->next; 3131 devm_kfree(&pdev->dev, chain); 3132 chain = chain_tmp; 3133 } 3134 } 3135 3136 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3137 struct hns3_enet_ring *ring) 3138 { 3139 ring->next = group->ring; 3140 group->ring = ring; 3141 3142 group->count++; 3143 } 3144 3145 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3146 { 3147 struct pci_dev *pdev = priv->ae_handle->pdev; 3148 struct hns3_enet_tqp_vector *tqp_vector; 3149 int num_vectors = priv->vector_num; 3150 int numa_node; 3151 int vector_i; 3152 3153 numa_node = dev_to_node(&pdev->dev); 3154 3155 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3156 tqp_vector = &priv->tqp_vector[vector_i]; 3157 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3158 &tqp_vector->affinity_mask); 3159 } 3160 } 3161 3162 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3163 { 3164 struct hnae3_ring_chain_node vector_ring_chain; 3165 struct hnae3_handle *h = priv->ae_handle; 3166 struct hns3_enet_tqp_vector *tqp_vector; 3167 int ret = 0; 3168 int i; 3169 3170 hns3_nic_set_cpumask(priv); 3171 3172 for (i = 0; i < priv->vector_num; i++) { 3173 tqp_vector = &priv->tqp_vector[i]; 3174 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3175 tqp_vector->num_tqps = 0; 3176 } 3177 3178 for (i = 0; i < h->kinfo.num_tqps; i++) { 3179 u16 vector_i = i % priv->vector_num; 3180 u16 tqp_num = h->kinfo.num_tqps; 3181 3182 tqp_vector = &priv->tqp_vector[vector_i]; 3183 3184 hns3_add_ring_to_group(&tqp_vector->tx_group, 3185 priv->ring_data[i].ring); 3186 3187 hns3_add_ring_to_group(&tqp_vector->rx_group, 3188 priv->ring_data[i + tqp_num].ring); 3189 3190 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3191 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3192 tqp_vector->num_tqps++; 3193 } 3194 3195 for (i = 0; i < priv->vector_num; i++) { 3196 tqp_vector = &priv->tqp_vector[i]; 3197 3198 tqp_vector->rx_group.total_bytes = 0; 3199 tqp_vector->rx_group.total_packets = 0; 3200 tqp_vector->tx_group.total_bytes = 0; 3201 tqp_vector->tx_group.total_packets = 0; 3202 tqp_vector->handle = h; 3203 3204 ret = hns3_get_vector_ring_chain(tqp_vector, 3205 &vector_ring_chain); 3206 if (ret) 3207 goto map_ring_fail; 3208 3209 ret = h->ae_algo->ops->map_ring_to_vector(h, 3210 tqp_vector->vector_irq, &vector_ring_chain); 3211 3212 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3213 3214 if (ret) 3215 goto map_ring_fail; 3216 3217 netif_napi_add(priv->netdev, &tqp_vector->napi, 3218 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3219 } 3220 3221 return 0; 3222 3223 map_ring_fail: 3224 while (i--) 3225 netif_napi_del(&priv->tqp_vector[i].napi); 3226 3227 return ret; 3228 } 3229 3230 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3231 { 3232 #define HNS3_VECTOR_PF_MAX_NUM 64 3233 3234 struct hnae3_handle *h = priv->ae_handle; 3235 struct hns3_enet_tqp_vector *tqp_vector; 3236 struct hnae3_vector_info *vector; 3237 struct pci_dev *pdev = h->pdev; 3238 u16 tqp_num = h->kinfo.num_tqps; 3239 u16 vector_num; 3240 int ret = 0; 3241 u16 i; 3242 3243 /* RSS size, cpu online and vector_num should be the same */ 3244 /* Should consider 2p/4p later */ 3245 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3246 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3247 3248 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3249 GFP_KERNEL); 3250 if (!vector) 3251 return -ENOMEM; 3252 3253 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3254 3255 priv->vector_num = vector_num; 3256 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3257 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3258 GFP_KERNEL); 3259 if (!priv->tqp_vector) { 3260 ret = -ENOMEM; 3261 goto out; 3262 } 3263 3264 for (i = 0; i < priv->vector_num; i++) { 3265 tqp_vector = &priv->tqp_vector[i]; 3266 tqp_vector->idx = i; 3267 tqp_vector->mask_addr = vector[i].io_addr; 3268 tqp_vector->vector_irq = vector[i].vector; 3269 hns3_vector_gl_rl_init(tqp_vector, priv); 3270 } 3271 3272 out: 3273 devm_kfree(&pdev->dev, vector); 3274 return ret; 3275 } 3276 3277 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3278 { 3279 group->ring = NULL; 3280 group->count = 0; 3281 } 3282 3283 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3284 { 3285 struct hnae3_ring_chain_node vector_ring_chain; 3286 struct hnae3_handle *h = priv->ae_handle; 3287 struct hns3_enet_tqp_vector *tqp_vector; 3288 int i; 3289 3290 for (i = 0; i < priv->vector_num; i++) { 3291 tqp_vector = &priv->tqp_vector[i]; 3292 3293 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3294 continue; 3295 3296 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3297 3298 h->ae_algo->ops->unmap_ring_from_vector(h, 3299 tqp_vector->vector_irq, &vector_ring_chain); 3300 3301 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3302 3303 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3304 irq_set_affinity_notifier(tqp_vector->vector_irq, 3305 NULL); 3306 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3307 free_irq(tqp_vector->vector_irq, tqp_vector); 3308 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3309 } 3310 3311 hns3_clear_ring_group(&tqp_vector->rx_group); 3312 hns3_clear_ring_group(&tqp_vector->tx_group); 3313 netif_napi_del(&priv->tqp_vector[i].napi); 3314 } 3315 } 3316 3317 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3318 { 3319 struct hnae3_handle *h = priv->ae_handle; 3320 struct pci_dev *pdev = h->pdev; 3321 int i, ret; 3322 3323 for (i = 0; i < priv->vector_num; i++) { 3324 struct hns3_enet_tqp_vector *tqp_vector; 3325 3326 tqp_vector = &priv->tqp_vector[i]; 3327 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3328 if (ret) 3329 return ret; 3330 } 3331 3332 devm_kfree(&pdev->dev, priv->tqp_vector); 3333 return 0; 3334 } 3335 3336 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3337 int ring_type) 3338 { 3339 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3340 int queue_num = priv->ae_handle->kinfo.num_tqps; 3341 struct pci_dev *pdev = priv->ae_handle->pdev; 3342 struct hns3_enet_ring *ring; 3343 int desc_num; 3344 3345 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3346 if (!ring) 3347 return -ENOMEM; 3348 3349 if (ring_type == HNAE3_RING_TYPE_TX) { 3350 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3351 ring_data[q->tqp_index].ring = ring; 3352 ring_data[q->tqp_index].queue_index = q->tqp_index; 3353 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3354 } else { 3355 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3356 ring_data[q->tqp_index + queue_num].ring = ring; 3357 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3358 ring->io_base = q->io_base; 3359 } 3360 3361 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3362 3363 ring->tqp = q; 3364 ring->desc = NULL; 3365 ring->desc_cb = NULL; 3366 ring->dev = priv->dev; 3367 ring->desc_dma_addr = 0; 3368 ring->buf_size = q->buf_size; 3369 ring->desc_num = desc_num; 3370 ring->next_to_use = 0; 3371 ring->next_to_clean = 0; 3372 3373 return 0; 3374 } 3375 3376 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3377 struct hns3_nic_priv *priv) 3378 { 3379 int ret; 3380 3381 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3382 if (ret) 3383 return ret; 3384 3385 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3386 if (ret) { 3387 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3388 return ret; 3389 } 3390 3391 return 0; 3392 } 3393 3394 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3395 { 3396 struct hnae3_handle *h = priv->ae_handle; 3397 struct pci_dev *pdev = h->pdev; 3398 int i, ret; 3399 3400 priv->ring_data = devm_kzalloc(&pdev->dev, 3401 array3_size(h->kinfo.num_tqps, 3402 sizeof(*priv->ring_data), 3403 2), 3404 GFP_KERNEL); 3405 if (!priv->ring_data) 3406 return -ENOMEM; 3407 3408 for (i = 0; i < h->kinfo.num_tqps; i++) { 3409 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3410 if (ret) 3411 goto err; 3412 } 3413 3414 return 0; 3415 err: 3416 while (i--) { 3417 devm_kfree(priv->dev, priv->ring_data[i].ring); 3418 devm_kfree(priv->dev, 3419 priv->ring_data[i + h->kinfo.num_tqps].ring); 3420 } 3421 3422 devm_kfree(&pdev->dev, priv->ring_data); 3423 return ret; 3424 } 3425 3426 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3427 { 3428 struct hnae3_handle *h = priv->ae_handle; 3429 int i; 3430 3431 for (i = 0; i < h->kinfo.num_tqps; i++) { 3432 devm_kfree(priv->dev, priv->ring_data[i].ring); 3433 devm_kfree(priv->dev, 3434 priv->ring_data[i + h->kinfo.num_tqps].ring); 3435 } 3436 devm_kfree(priv->dev, priv->ring_data); 3437 } 3438 3439 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3440 { 3441 int ret; 3442 3443 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3444 return -EINVAL; 3445 3446 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3447 GFP_KERNEL); 3448 if (!ring->desc_cb) { 3449 ret = -ENOMEM; 3450 goto out; 3451 } 3452 3453 ret = hns3_alloc_desc(ring); 3454 if (ret) 3455 goto out_with_desc_cb; 3456 3457 if (!HNAE3_IS_TX_RING(ring)) { 3458 ret = hns3_alloc_ring_buffers(ring); 3459 if (ret) 3460 goto out_with_desc; 3461 } 3462 3463 return 0; 3464 3465 out_with_desc: 3466 hns3_free_desc(ring); 3467 out_with_desc_cb: 3468 kfree(ring->desc_cb); 3469 ring->desc_cb = NULL; 3470 out: 3471 return ret; 3472 } 3473 3474 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3475 { 3476 hns3_free_desc(ring); 3477 kfree(ring->desc_cb); 3478 ring->desc_cb = NULL; 3479 ring->next_to_clean = 0; 3480 ring->next_to_use = 0; 3481 ring->pending_buf = 0; 3482 if (ring->skb) { 3483 dev_kfree_skb_any(ring->skb); 3484 ring->skb = NULL; 3485 } 3486 } 3487 3488 static int hns3_buf_size2type(u32 buf_size) 3489 { 3490 int bd_size_type; 3491 3492 switch (buf_size) { 3493 case 512: 3494 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3495 break; 3496 case 1024: 3497 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3498 break; 3499 case 2048: 3500 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3501 break; 3502 case 4096: 3503 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3504 break; 3505 default: 3506 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3507 } 3508 3509 return bd_size_type; 3510 } 3511 3512 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3513 { 3514 dma_addr_t dma = ring->desc_dma_addr; 3515 struct hnae3_queue *q = ring->tqp; 3516 3517 if (!HNAE3_IS_TX_RING(ring)) { 3518 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3519 (u32)dma); 3520 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3521 (u32)((dma >> 31) >> 1)); 3522 3523 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3524 hns3_buf_size2type(ring->buf_size)); 3525 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3526 ring->desc_num / 8 - 1); 3527 3528 } else { 3529 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3530 (u32)dma); 3531 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3532 (u32)((dma >> 31) >> 1)); 3533 3534 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3535 ring->desc_num / 8 - 1); 3536 } 3537 } 3538 3539 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3540 { 3541 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3542 int i; 3543 3544 for (i = 0; i < HNAE3_MAX_TC; i++) { 3545 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3546 int j; 3547 3548 if (!tc_info->enable) 3549 continue; 3550 3551 for (j = 0; j < tc_info->tqp_count; j++) { 3552 struct hnae3_queue *q; 3553 3554 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3555 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3556 tc_info->tc); 3557 } 3558 } 3559 } 3560 3561 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3562 { 3563 struct hnae3_handle *h = priv->ae_handle; 3564 int ring_num = h->kinfo.num_tqps * 2; 3565 int i, j; 3566 int ret; 3567 3568 for (i = 0; i < ring_num; i++) { 3569 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3570 if (ret) { 3571 dev_err(priv->dev, 3572 "Alloc ring memory fail! ret=%d\n", ret); 3573 goto out_when_alloc_ring_memory; 3574 } 3575 3576 u64_stats_init(&priv->ring_data[i].ring->syncp); 3577 } 3578 3579 return 0; 3580 3581 out_when_alloc_ring_memory: 3582 for (j = i - 1; j >= 0; j--) 3583 hns3_fini_ring(priv->ring_data[j].ring); 3584 3585 return -ENOMEM; 3586 } 3587 3588 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3589 { 3590 struct hnae3_handle *h = priv->ae_handle; 3591 int i; 3592 3593 for (i = 0; i < h->kinfo.num_tqps; i++) { 3594 hns3_fini_ring(priv->ring_data[i].ring); 3595 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3596 } 3597 return 0; 3598 } 3599 3600 /* Set mac addr if it is configured. or leave it to the AE driver */ 3601 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3602 { 3603 struct hns3_nic_priv *priv = netdev_priv(netdev); 3604 struct hnae3_handle *h = priv->ae_handle; 3605 u8 mac_addr_temp[ETH_ALEN]; 3606 int ret = 0; 3607 3608 if (h->ae_algo->ops->get_mac_addr && init) { 3609 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3610 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3611 } 3612 3613 /* Check if the MAC address is valid, if not get a random one */ 3614 if (!is_valid_ether_addr(netdev->dev_addr)) { 3615 eth_hw_addr_random(netdev); 3616 dev_warn(priv->dev, "using random MAC address %pM\n", 3617 netdev->dev_addr); 3618 } 3619 3620 if (h->ae_algo->ops->set_mac_addr) 3621 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3622 3623 return ret; 3624 } 3625 3626 static int hns3_init_phy(struct net_device *netdev) 3627 { 3628 struct hnae3_handle *h = hns3_get_handle(netdev); 3629 int ret = 0; 3630 3631 if (h->ae_algo->ops->mac_connect_phy) 3632 ret = h->ae_algo->ops->mac_connect_phy(h); 3633 3634 return ret; 3635 } 3636 3637 static void hns3_uninit_phy(struct net_device *netdev) 3638 { 3639 struct hnae3_handle *h = hns3_get_handle(netdev); 3640 3641 if (h->ae_algo->ops->mac_disconnect_phy) 3642 h->ae_algo->ops->mac_disconnect_phy(h); 3643 } 3644 3645 static int hns3_restore_fd_rules(struct net_device *netdev) 3646 { 3647 struct hnae3_handle *h = hns3_get_handle(netdev); 3648 int ret = 0; 3649 3650 if (h->ae_algo->ops->restore_fd_rules) 3651 ret = h->ae_algo->ops->restore_fd_rules(h); 3652 3653 return ret; 3654 } 3655 3656 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3657 { 3658 struct hnae3_handle *h = hns3_get_handle(netdev); 3659 3660 if (h->ae_algo->ops->del_all_fd_entries) 3661 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3662 } 3663 3664 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3665 { 3666 struct hns3_nic_priv *priv = netdev_priv(netdev); 3667 3668 if ((netdev->features & NETIF_F_TSO) || 3669 (netdev->features & NETIF_F_TSO6)) 3670 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3671 else 3672 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3673 } 3674 3675 static int hns3_client_start(struct hnae3_handle *handle) 3676 { 3677 if (!handle->ae_algo->ops->client_start) 3678 return 0; 3679 3680 return handle->ae_algo->ops->client_start(handle); 3681 } 3682 3683 static void hns3_client_stop(struct hnae3_handle *handle) 3684 { 3685 if (!handle->ae_algo->ops->client_stop) 3686 return; 3687 3688 handle->ae_algo->ops->client_stop(handle); 3689 } 3690 3691 static int hns3_client_init(struct hnae3_handle *handle) 3692 { 3693 struct pci_dev *pdev = handle->pdev; 3694 u16 alloc_tqps, max_rss_size; 3695 struct hns3_nic_priv *priv; 3696 struct net_device *netdev; 3697 int ret; 3698 3699 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3700 &max_rss_size); 3701 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3702 if (!netdev) 3703 return -ENOMEM; 3704 3705 priv = netdev_priv(netdev); 3706 priv->dev = &pdev->dev; 3707 priv->netdev = netdev; 3708 priv->ae_handle = handle; 3709 priv->tx_timeout_count = 0; 3710 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3711 3712 handle->kinfo.netdev = netdev; 3713 handle->priv = (void *)priv; 3714 3715 hns3_init_mac_addr(netdev, true); 3716 3717 hns3_set_default_feature(netdev); 3718 3719 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3720 netdev->priv_flags |= IFF_UNICAST_FLT; 3721 netdev->netdev_ops = &hns3_nic_netdev_ops; 3722 SET_NETDEV_DEV(netdev, &pdev->dev); 3723 hns3_ethtool_set_ops(netdev); 3724 hns3_nic_set_priv_ops(netdev); 3725 3726 /* Carrier off reporting is important to ethtool even BEFORE open */ 3727 netif_carrier_off(netdev); 3728 3729 ret = hns3_get_ring_config(priv); 3730 if (ret) { 3731 ret = -ENOMEM; 3732 goto out_get_ring_cfg; 3733 } 3734 3735 ret = hns3_nic_alloc_vector_data(priv); 3736 if (ret) { 3737 ret = -ENOMEM; 3738 goto out_alloc_vector_data; 3739 } 3740 3741 ret = hns3_nic_init_vector_data(priv); 3742 if (ret) { 3743 ret = -ENOMEM; 3744 goto out_init_vector_data; 3745 } 3746 3747 ret = hns3_init_all_ring(priv); 3748 if (ret) { 3749 ret = -ENOMEM; 3750 goto out_init_ring_data; 3751 } 3752 3753 ret = hns3_init_phy(netdev); 3754 if (ret) 3755 goto out_init_phy; 3756 3757 ret = register_netdev(netdev); 3758 if (ret) { 3759 dev_err(priv->dev, "probe register netdev fail!\n"); 3760 goto out_reg_netdev_fail; 3761 } 3762 3763 ret = hns3_client_start(handle); 3764 if (ret) { 3765 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3766 goto out_client_start; 3767 } 3768 3769 hns3_dcbnl_setup(handle); 3770 3771 hns3_dbg_init(handle); 3772 3773 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3774 netdev->max_mtu = HNS3_MAX_MTU; 3775 3776 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3777 3778 return ret; 3779 3780 out_client_start: 3781 unregister_netdev(netdev); 3782 out_reg_netdev_fail: 3783 hns3_uninit_phy(netdev); 3784 out_init_phy: 3785 hns3_uninit_all_ring(priv); 3786 out_init_ring_data: 3787 hns3_nic_uninit_vector_data(priv); 3788 out_init_vector_data: 3789 hns3_nic_dealloc_vector_data(priv); 3790 out_alloc_vector_data: 3791 priv->ring_data = NULL; 3792 out_get_ring_cfg: 3793 priv->ae_handle = NULL; 3794 free_netdev(netdev); 3795 return ret; 3796 } 3797 3798 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3799 { 3800 struct net_device *netdev = handle->kinfo.netdev; 3801 struct hns3_nic_priv *priv = netdev_priv(netdev); 3802 int ret; 3803 3804 hns3_remove_hw_addr(netdev); 3805 3806 if (netdev->reg_state != NETREG_UNINITIALIZED) 3807 unregister_netdev(netdev); 3808 3809 hns3_client_stop(handle); 3810 3811 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3812 netdev_warn(netdev, "already uninitialized\n"); 3813 goto out_netdev_free; 3814 } 3815 3816 hns3_del_all_fd_rules(netdev, true); 3817 3818 hns3_force_clear_all_rx_ring(handle); 3819 3820 hns3_uninit_phy(netdev); 3821 3822 hns3_nic_uninit_vector_data(priv); 3823 3824 ret = hns3_nic_dealloc_vector_data(priv); 3825 if (ret) 3826 netdev_err(netdev, "dealloc vector error\n"); 3827 3828 ret = hns3_uninit_all_ring(priv); 3829 if (ret) 3830 netdev_err(netdev, "uninit ring error\n"); 3831 3832 hns3_put_ring_config(priv); 3833 3834 hns3_dbg_uninit(handle); 3835 3836 priv->ring_data = NULL; 3837 3838 out_netdev_free: 3839 free_netdev(netdev); 3840 } 3841 3842 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3843 { 3844 struct net_device *netdev = handle->kinfo.netdev; 3845 3846 if (!netdev) 3847 return; 3848 3849 if (linkup) { 3850 netif_carrier_on(netdev); 3851 netif_tx_wake_all_queues(netdev); 3852 netdev_info(netdev, "link up\n"); 3853 } else { 3854 netif_carrier_off(netdev); 3855 netif_tx_stop_all_queues(netdev); 3856 netdev_info(netdev, "link down\n"); 3857 } 3858 } 3859 3860 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3861 { 3862 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3863 struct net_device *ndev = kinfo->netdev; 3864 3865 if (tc > HNAE3_MAX_TC) 3866 return -EINVAL; 3867 3868 if (!ndev) 3869 return -ENODEV; 3870 3871 return hns3_nic_set_real_num_queue(ndev); 3872 } 3873 3874 static int hns3_recover_hw_addr(struct net_device *ndev) 3875 { 3876 struct netdev_hw_addr_list *list; 3877 struct netdev_hw_addr *ha, *tmp; 3878 int ret = 0; 3879 3880 netif_addr_lock_bh(ndev); 3881 /* go through and sync uc_addr entries to the device */ 3882 list = &ndev->uc; 3883 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3884 ret = hns3_nic_uc_sync(ndev, ha->addr); 3885 if (ret) 3886 goto out; 3887 } 3888 3889 /* go through and sync mc_addr entries to the device */ 3890 list = &ndev->mc; 3891 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3892 ret = hns3_nic_mc_sync(ndev, ha->addr); 3893 if (ret) 3894 goto out; 3895 } 3896 3897 out: 3898 netif_addr_unlock_bh(ndev); 3899 return ret; 3900 } 3901 3902 static void hns3_remove_hw_addr(struct net_device *netdev) 3903 { 3904 struct netdev_hw_addr_list *list; 3905 struct netdev_hw_addr *ha, *tmp; 3906 3907 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3908 3909 netif_addr_lock_bh(netdev); 3910 /* go through and unsync uc_addr entries to the device */ 3911 list = &netdev->uc; 3912 list_for_each_entry_safe(ha, tmp, &list->list, list) 3913 hns3_nic_uc_unsync(netdev, ha->addr); 3914 3915 /* go through and unsync mc_addr entries to the device */ 3916 list = &netdev->mc; 3917 list_for_each_entry_safe(ha, tmp, &list->list, list) 3918 if (ha->refcount > 1) 3919 hns3_nic_mc_unsync(netdev, ha->addr); 3920 3921 netif_addr_unlock_bh(netdev); 3922 } 3923 3924 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3925 { 3926 while (ring->next_to_clean != ring->next_to_use) { 3927 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3928 hns3_free_buffer_detach(ring, ring->next_to_clean); 3929 ring_ptr_move_fw(ring, next_to_clean); 3930 } 3931 } 3932 3933 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3934 { 3935 struct hns3_desc_cb res_cbs; 3936 int ret; 3937 3938 while (ring->next_to_use != ring->next_to_clean) { 3939 /* When a buffer is not reused, it's memory has been 3940 * freed in hns3_handle_rx_bd or will be freed by 3941 * stack, so we need to replace the buffer here. 3942 */ 3943 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3944 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3945 if (ret) { 3946 u64_stats_update_begin(&ring->syncp); 3947 ring->stats.sw_err_cnt++; 3948 u64_stats_update_end(&ring->syncp); 3949 /* if alloc new buffer fail, exit directly 3950 * and reclear in up flow. 3951 */ 3952 netdev_warn(ring->tqp->handle->kinfo.netdev, 3953 "reserve buffer map failed, ret = %d\n", 3954 ret); 3955 return ret; 3956 } 3957 hns3_replace_buffer(ring, ring->next_to_use, 3958 &res_cbs); 3959 } 3960 ring_ptr_move_fw(ring, next_to_use); 3961 } 3962 3963 /* Free the pending skb in rx ring */ 3964 if (ring->skb) { 3965 dev_kfree_skb_any(ring->skb); 3966 ring->skb = NULL; 3967 ring->pending_buf = 0; 3968 } 3969 3970 return 0; 3971 } 3972 3973 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3974 { 3975 while (ring->next_to_use != ring->next_to_clean) { 3976 /* When a buffer is not reused, it's memory has been 3977 * freed in hns3_handle_rx_bd or will be freed by 3978 * stack, so only need to unmap the buffer here. 3979 */ 3980 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3981 hns3_unmap_buffer(ring, 3982 &ring->desc_cb[ring->next_to_use]); 3983 ring->desc_cb[ring->next_to_use].dma = 0; 3984 } 3985 3986 ring_ptr_move_fw(ring, next_to_use); 3987 } 3988 } 3989 3990 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3991 { 3992 struct net_device *ndev = h->kinfo.netdev; 3993 struct hns3_nic_priv *priv = netdev_priv(ndev); 3994 struct hns3_enet_ring *ring; 3995 u32 i; 3996 3997 for (i = 0; i < h->kinfo.num_tqps; i++) { 3998 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3999 hns3_force_clear_rx_ring(ring); 4000 } 4001 } 4002 4003 static void hns3_clear_all_ring(struct hnae3_handle *h) 4004 { 4005 struct net_device *ndev = h->kinfo.netdev; 4006 struct hns3_nic_priv *priv = netdev_priv(ndev); 4007 u32 i; 4008 4009 for (i = 0; i < h->kinfo.num_tqps; i++) { 4010 struct netdev_queue *dev_queue; 4011 struct hns3_enet_ring *ring; 4012 4013 ring = priv->ring_data[i].ring; 4014 hns3_clear_tx_ring(ring); 4015 dev_queue = netdev_get_tx_queue(ndev, 4016 priv->ring_data[i].queue_index); 4017 netdev_tx_reset_queue(dev_queue); 4018 4019 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4020 /* Continue to clear other rings even if clearing some 4021 * rings failed. 4022 */ 4023 hns3_clear_rx_ring(ring); 4024 } 4025 } 4026 4027 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4028 { 4029 struct net_device *ndev = h->kinfo.netdev; 4030 struct hns3_nic_priv *priv = netdev_priv(ndev); 4031 struct hns3_enet_ring *rx_ring; 4032 int i, j; 4033 int ret; 4034 4035 for (i = 0; i < h->kinfo.num_tqps; i++) { 4036 ret = h->ae_algo->ops->reset_queue(h, i); 4037 if (ret) 4038 return ret; 4039 4040 hns3_init_ring_hw(priv->ring_data[i].ring); 4041 4042 /* We need to clear tx ring here because self test will 4043 * use the ring and will not run down before up 4044 */ 4045 hns3_clear_tx_ring(priv->ring_data[i].ring); 4046 priv->ring_data[i].ring->next_to_clean = 0; 4047 priv->ring_data[i].ring->next_to_use = 0; 4048 4049 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 4050 hns3_init_ring_hw(rx_ring); 4051 ret = hns3_clear_rx_ring(rx_ring); 4052 if (ret) 4053 return ret; 4054 4055 /* We can not know the hardware head and tail when this 4056 * function is called in reset flow, so we reuse all desc. 4057 */ 4058 for (j = 0; j < rx_ring->desc_num; j++) 4059 hns3_reuse_buffer(rx_ring, j); 4060 4061 rx_ring->next_to_clean = 0; 4062 rx_ring->next_to_use = 0; 4063 } 4064 4065 hns3_init_tx_ring_tc(priv); 4066 4067 return 0; 4068 } 4069 4070 static void hns3_store_coal(struct hns3_nic_priv *priv) 4071 { 4072 /* ethtool only support setting and querying one coal 4073 * configuation for now, so save the vector 0' coal 4074 * configuation here in order to restore it. 4075 */ 4076 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4077 sizeof(struct hns3_enet_coalesce)); 4078 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4079 sizeof(struct hns3_enet_coalesce)); 4080 } 4081 4082 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4083 { 4084 u16 vector_num = priv->vector_num; 4085 int i; 4086 4087 for (i = 0; i < vector_num; i++) { 4088 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4089 sizeof(struct hns3_enet_coalesce)); 4090 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4091 sizeof(struct hns3_enet_coalesce)); 4092 } 4093 } 4094 4095 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4096 { 4097 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4098 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4099 struct net_device *ndev = kinfo->netdev; 4100 struct hns3_nic_priv *priv = netdev_priv(ndev); 4101 4102 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4103 return 0; 4104 4105 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4106 * from table space. Hence, for function reset software intervention is 4107 * required to delete the entries 4108 */ 4109 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4110 hns3_remove_hw_addr(ndev); 4111 hns3_del_all_fd_rules(ndev, false); 4112 } 4113 4114 if (!netif_running(ndev)) 4115 return 0; 4116 4117 return hns3_nic_net_stop(ndev); 4118 } 4119 4120 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4121 { 4122 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4123 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4124 int ret = 0; 4125 4126 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4127 4128 if (netif_running(kinfo->netdev)) { 4129 ret = hns3_nic_net_open(kinfo->netdev); 4130 if (ret) { 4131 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4132 netdev_err(kinfo->netdev, 4133 "hns net up fail, ret=%d!\n", ret); 4134 return ret; 4135 } 4136 } 4137 4138 return ret; 4139 } 4140 4141 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4142 { 4143 struct net_device *netdev = handle->kinfo.netdev; 4144 struct hns3_nic_priv *priv = netdev_priv(netdev); 4145 int ret; 4146 4147 /* Carrier off reporting is important to ethtool even BEFORE open */ 4148 netif_carrier_off(netdev); 4149 4150 ret = hns3_get_ring_config(priv); 4151 if (ret) 4152 return ret; 4153 4154 ret = hns3_nic_alloc_vector_data(priv); 4155 if (ret) 4156 goto err_put_ring; 4157 4158 hns3_restore_coal(priv); 4159 4160 ret = hns3_nic_init_vector_data(priv); 4161 if (ret) 4162 goto err_dealloc_vector; 4163 4164 ret = hns3_init_all_ring(priv); 4165 if (ret) 4166 goto err_uninit_vector; 4167 4168 ret = hns3_client_start(handle); 4169 if (ret) { 4170 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4171 goto err_uninit_ring; 4172 } 4173 4174 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4175 4176 return ret; 4177 4178 err_uninit_ring: 4179 hns3_uninit_all_ring(priv); 4180 err_uninit_vector: 4181 hns3_nic_uninit_vector_data(priv); 4182 priv->ring_data = NULL; 4183 err_dealloc_vector: 4184 hns3_nic_dealloc_vector_data(priv); 4185 err_put_ring: 4186 hns3_put_ring_config(priv); 4187 priv->ring_data = NULL; 4188 4189 return ret; 4190 } 4191 4192 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4193 { 4194 struct net_device *netdev = handle->kinfo.netdev; 4195 bool vlan_filter_enable; 4196 int ret; 4197 4198 ret = hns3_init_mac_addr(netdev, false); 4199 if (ret) 4200 return ret; 4201 4202 ret = hns3_recover_hw_addr(netdev); 4203 if (ret) 4204 return ret; 4205 4206 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4207 if (ret) 4208 return ret; 4209 4210 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4211 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4212 4213 /* Hardware table is only clear when pf resets */ 4214 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4215 ret = hns3_restore_vlan(netdev); 4216 if (ret) 4217 return ret; 4218 } 4219 4220 return hns3_restore_fd_rules(netdev); 4221 } 4222 4223 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4224 { 4225 struct net_device *netdev = handle->kinfo.netdev; 4226 struct hns3_nic_priv *priv = netdev_priv(netdev); 4227 int ret; 4228 4229 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4230 netdev_warn(netdev, "already uninitialized\n"); 4231 return 0; 4232 } 4233 4234 hns3_force_clear_all_rx_ring(handle); 4235 4236 hns3_nic_uninit_vector_data(priv); 4237 4238 hns3_store_coal(priv); 4239 4240 ret = hns3_nic_dealloc_vector_data(priv); 4241 if (ret) 4242 netdev_err(netdev, "dealloc vector error\n"); 4243 4244 ret = hns3_uninit_all_ring(priv); 4245 if (ret) 4246 netdev_err(netdev, "uninit ring error\n"); 4247 4248 hns3_put_ring_config(priv); 4249 priv->ring_data = NULL; 4250 4251 return ret; 4252 } 4253 4254 static int hns3_reset_notify(struct hnae3_handle *handle, 4255 enum hnae3_reset_notify_type type) 4256 { 4257 int ret = 0; 4258 4259 switch (type) { 4260 case HNAE3_UP_CLIENT: 4261 ret = hns3_reset_notify_up_enet(handle); 4262 break; 4263 case HNAE3_DOWN_CLIENT: 4264 ret = hns3_reset_notify_down_enet(handle); 4265 break; 4266 case HNAE3_INIT_CLIENT: 4267 ret = hns3_reset_notify_init_enet(handle); 4268 break; 4269 case HNAE3_UNINIT_CLIENT: 4270 ret = hns3_reset_notify_uninit_enet(handle); 4271 break; 4272 case HNAE3_RESTORE_CLIENT: 4273 ret = hns3_reset_notify_restore_enet(handle); 4274 break; 4275 default: 4276 break; 4277 } 4278 4279 return ret; 4280 } 4281 4282 int hns3_set_channels(struct net_device *netdev, 4283 struct ethtool_channels *ch) 4284 { 4285 struct hnae3_handle *h = hns3_get_handle(netdev); 4286 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4287 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4288 u32 new_tqp_num = ch->combined_count; 4289 u16 org_tqp_num; 4290 int ret; 4291 4292 if (ch->rx_count || ch->tx_count) 4293 return -EINVAL; 4294 4295 if (new_tqp_num > hns3_get_max_available_channels(h) || 4296 new_tqp_num < 1) { 4297 dev_err(&netdev->dev, 4298 "Change tqps fail, the tqp range is from 1 to %d", 4299 hns3_get_max_available_channels(h)); 4300 return -EINVAL; 4301 } 4302 4303 if (kinfo->rss_size == new_tqp_num) 4304 return 0; 4305 4306 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4307 if (ret) 4308 return ret; 4309 4310 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4311 if (ret) 4312 return ret; 4313 4314 org_tqp_num = h->kinfo.num_tqps; 4315 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4316 if (ret) { 4317 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4318 rxfh_configured); 4319 if (ret) { 4320 /* If revert to old tqp failed, fatal error occurred */ 4321 dev_err(&netdev->dev, 4322 "Revert to old tqp num fail, ret=%d", ret); 4323 return ret; 4324 } 4325 dev_info(&netdev->dev, 4326 "Change tqp num fail, Revert to old tqp num"); 4327 } 4328 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4329 if (ret) 4330 return ret; 4331 4332 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4333 } 4334 4335 static const struct hnae3_client_ops client_ops = { 4336 .init_instance = hns3_client_init, 4337 .uninit_instance = hns3_client_uninit, 4338 .link_status_change = hns3_link_status_change, 4339 .setup_tc = hns3_client_setup_tc, 4340 .reset_notify = hns3_reset_notify, 4341 }; 4342 4343 /* hns3_init_module - Driver registration routine 4344 * hns3_init_module is the first routine called when the driver is 4345 * loaded. All it does is register with the PCI subsystem. 4346 */ 4347 static int __init hns3_init_module(void) 4348 { 4349 int ret; 4350 4351 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4352 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4353 4354 client.type = HNAE3_CLIENT_KNIC; 4355 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4356 hns3_driver_name); 4357 4358 client.ops = &client_ops; 4359 4360 INIT_LIST_HEAD(&client.node); 4361 4362 hns3_dbg_register_debugfs(hns3_driver_name); 4363 4364 ret = hnae3_register_client(&client); 4365 if (ret) 4366 goto err_reg_client; 4367 4368 ret = pci_register_driver(&hns3_driver); 4369 if (ret) 4370 goto err_reg_driver; 4371 4372 return ret; 4373 4374 err_reg_driver: 4375 hnae3_unregister_client(&client); 4376 err_reg_client: 4377 hns3_dbg_unregister_debugfs(); 4378 return ret; 4379 } 4380 module_init(hns3_init_module); 4381 4382 /* hns3_exit_module - Driver exit cleanup routine 4383 * hns3_exit_module is called just before the driver is removed 4384 * from memory. 4385 */ 4386 static void __exit hns3_exit_module(void) 4387 { 4388 pci_unregister_driver(&hns3_driver); 4389 hnae3_unregister_client(&client); 4390 hns3_dbg_unregister_debugfs(); 4391 } 4392 module_exit(hns3_exit_module); 4393 4394 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4395 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4396 MODULE_LICENSE("GPL"); 4397 MODULE_ALIAS("pci:hns-nic"); 4398 MODULE_VERSION(HNS3_MOD_VERSION); 4399