1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 static void hns3_clear_all_ring(struct hnae3_handle *h); 25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 26 static void hns3_remove_hw_addr(struct net_device *netdev); 27 28 static const char hns3_driver_name[] = "hns3"; 29 const char hns3_driver_version[] = VERMAGIC_STRING; 30 static const char hns3_driver_string[] = 31 "Hisilicon Ethernet Network Driver for Hip08 Family"; 32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 33 static struct hnae3_client client; 34 35 /* hns3_pci_tbl - PCI Device ID Table 36 * 37 * Last entry must be all 0s 38 * 39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 40 * Class, Class Mask, private data (not used) } 41 */ 42 static const struct pci_device_id hns3_pci_tbl[] = { 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 58 /* required last entry */ 59 {0, } 60 }; 61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 62 63 static irqreturn_t hns3_irq_handle(int irq, void *vector) 64 { 65 struct hns3_enet_tqp_vector *tqp_vector = vector; 66 67 napi_schedule(&tqp_vector->napi); 68 69 return IRQ_HANDLED; 70 } 71 72 /* This callback function is used to set affinity changes to the irq affinity 73 * masks when the irq_set_affinity_notifier function is used. 74 */ 75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 76 const cpumask_t *mask) 77 { 78 struct hns3_enet_tqp_vector *tqp_vectors = 79 container_of(notify, struct hns3_enet_tqp_vector, 80 affinity_notify); 81 82 tqp_vectors->affinity_mask = *mask; 83 } 84 85 static void hns3_nic_irq_affinity_release(struct kref *ref) 86 { 87 } 88 89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 90 { 91 struct hns3_enet_tqp_vector *tqp_vectors; 92 unsigned int i; 93 94 for (i = 0; i < priv->vector_num; i++) { 95 tqp_vectors = &priv->tqp_vector[i]; 96 97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 98 continue; 99 100 /* clear the affinity notifier and affinity mask */ 101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 103 104 /* release the irq resource */ 105 free_irq(tqp_vectors->vector_irq, tqp_vectors); 106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 107 } 108 } 109 110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 111 { 112 struct hns3_enet_tqp_vector *tqp_vectors; 113 int txrx_int_idx = 0; 114 int rx_int_idx = 0; 115 int tx_int_idx = 0; 116 unsigned int i; 117 int ret; 118 119 for (i = 0; i < priv->vector_num; i++) { 120 tqp_vectors = &priv->tqp_vector[i]; 121 122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 123 continue; 124 125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 127 "%s-%s-%d", priv->netdev->name, "TxRx", 128 txrx_int_idx++); 129 txrx_int_idx++; 130 } else if (tqp_vectors->rx_group.ring) { 131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 132 "%s-%s-%d", priv->netdev->name, "Rx", 133 rx_int_idx++); 134 } else if (tqp_vectors->tx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Tx", 137 tx_int_idx++); 138 } else { 139 /* Skip this unused q_vector */ 140 continue; 141 } 142 143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 144 145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 146 tqp_vectors->name, 147 tqp_vectors); 148 if (ret) { 149 netdev_err(priv->netdev, "request irq(%d) fail\n", 150 tqp_vectors->vector_irq); 151 return ret; 152 } 153 154 tqp_vectors->affinity_notify.notify = 155 hns3_nic_irq_affinity_notify; 156 tqp_vectors->affinity_notify.release = 157 hns3_nic_irq_affinity_release; 158 irq_set_affinity_notifier(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_notify); 160 irq_set_affinity_hint(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_mask); 162 163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 164 } 165 166 return 0; 167 } 168 169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 170 u32 mask_en) 171 { 172 writel(mask_en, tqp_vector->mask_addr); 173 } 174 175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 176 { 177 napi_enable(&tqp_vector->napi); 178 179 /* enable vector */ 180 hns3_mask_vector_irq(tqp_vector, 1); 181 } 182 183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 184 { 185 /* disable vector */ 186 hns3_mask_vector_irq(tqp_vector, 0); 187 188 disable_irq(tqp_vector->vector_irq); 189 napi_disable(&tqp_vector->napi); 190 } 191 192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 193 u32 rl_value) 194 { 195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 196 197 /* this defines the configuration for RL (Interrupt Rate Limiter). 198 * Rl defines rate of interrupts i.e. number of interrupts-per-second 199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 200 */ 201 202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 203 !tqp_vector->rx_group.coal.gl_adapt_enable) 204 /* According to the hardware, the range of rl_reg is 205 * 0-59 and the unit is 4. 206 */ 207 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 208 209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 210 } 211 212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 213 u32 gl_value) 214 { 215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 216 217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 218 } 219 220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 221 u32 gl_value) 222 { 223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 224 225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 226 } 227 228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 229 struct hns3_nic_priv *priv) 230 { 231 /* initialize the configuration for interrupt coalescing. 232 * 1. GL (Interrupt Gap Limiter) 233 * 2. RL (Interrupt Rate Limiter) 234 */ 235 236 /* Default: enable interrupt coalescing self-adaptive and GL */ 237 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 238 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 239 240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 242 243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 245 } 246 247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 248 struct hns3_nic_priv *priv) 249 { 250 struct hnae3_handle *h = priv->ae_handle; 251 252 hns3_set_vector_coalesce_tx_gl(tqp_vector, 253 tqp_vector->tx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rx_gl(tqp_vector, 255 tqp_vector->rx_group.coal.int_gl); 256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 257 } 258 259 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 260 { 261 struct hnae3_handle *h = hns3_get_handle(netdev); 262 struct hnae3_knic_private_info *kinfo = &h->kinfo; 263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 264 int i, ret; 265 266 if (kinfo->num_tc <= 1) { 267 netdev_reset_tc(netdev); 268 } else { 269 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 270 if (ret) { 271 netdev_err(netdev, 272 "netdev_set_num_tc fail, ret=%d!\n", ret); 273 return ret; 274 } 275 276 for (i = 0; i < HNAE3_MAX_TC; i++) { 277 if (!kinfo->tc_info[i].enable) 278 continue; 279 280 netdev_set_tc_queue(netdev, 281 kinfo->tc_info[i].tc, 282 kinfo->tc_info[i].tqp_count, 283 kinfo->tc_info[i].tqp_offset); 284 } 285 } 286 287 ret = netif_set_real_num_tx_queues(netdev, queue_size); 288 if (ret) { 289 netdev_err(netdev, 290 "netif_set_real_num_tx_queues fail, ret=%d!\n", 291 ret); 292 return ret; 293 } 294 295 ret = netif_set_real_num_rx_queues(netdev, queue_size); 296 if (ret) { 297 netdev_err(netdev, 298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 299 return ret; 300 } 301 302 return 0; 303 } 304 305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 306 { 307 u16 alloc_tqps, max_rss_size, rss_size; 308 309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 310 rss_size = alloc_tqps / h->kinfo.num_tc; 311 312 return min_t(u16, rss_size, max_rss_size); 313 } 314 315 static void hns3_tqp_enable(struct hnae3_queue *tqp) 316 { 317 u32 rcb_reg; 318 319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 320 rcb_reg |= BIT(HNS3_RING_EN_B); 321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 322 } 323 324 static void hns3_tqp_disable(struct hnae3_queue *tqp) 325 { 326 u32 rcb_reg; 327 328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 329 rcb_reg &= ~BIT(HNS3_RING_EN_B); 330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 331 } 332 333 static int hns3_nic_net_up(struct net_device *netdev) 334 { 335 struct hns3_nic_priv *priv = netdev_priv(netdev); 336 struct hnae3_handle *h = priv->ae_handle; 337 int i, j; 338 int ret; 339 340 ret = hns3_nic_reset_all_ring(h); 341 if (ret) 342 return ret; 343 344 /* get irq resource for all vectors */ 345 ret = hns3_nic_init_irq(priv); 346 if (ret) { 347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 348 return ret; 349 } 350 351 /* enable the vectors */ 352 for (i = 0; i < priv->vector_num; i++) 353 hns3_vector_enable(&priv->tqp_vector[i]); 354 355 /* enable rcb */ 356 for (j = 0; j < h->kinfo.num_tqps; j++) 357 hns3_tqp_enable(h->kinfo.tqp[j]); 358 359 /* start the ae_dev */ 360 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 361 if (ret) 362 goto out_start_err; 363 364 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 365 366 return 0; 367 368 out_start_err: 369 while (j--) 370 hns3_tqp_disable(h->kinfo.tqp[j]); 371 372 for (j = i - 1; j >= 0; j--) 373 hns3_vector_disable(&priv->tqp_vector[j]); 374 375 hns3_nic_uninit_irq(priv); 376 377 return ret; 378 } 379 380 static int hns3_nic_net_open(struct net_device *netdev) 381 { 382 struct hns3_nic_priv *priv = netdev_priv(netdev); 383 struct hnae3_handle *h = hns3_get_handle(netdev); 384 struct hnae3_knic_private_info *kinfo; 385 int i, ret; 386 387 if (hns3_nic_resetting(netdev)) 388 return -EBUSY; 389 390 netif_carrier_off(netdev); 391 392 ret = hns3_nic_set_real_num_queue(netdev); 393 if (ret) 394 return ret; 395 396 ret = hns3_nic_net_up(netdev); 397 if (ret) { 398 netdev_err(netdev, 399 "hns net up fail, ret=%d!\n", ret); 400 return ret; 401 } 402 403 kinfo = &h->kinfo; 404 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 405 netdev_set_prio_tc_map(netdev, i, 406 kinfo->prio_tc[i]); 407 } 408 409 if (h->ae_algo->ops->set_timer_task) 410 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 411 412 return 0; 413 } 414 415 static void hns3_nic_net_down(struct net_device *netdev) 416 { 417 struct hns3_nic_priv *priv = netdev_priv(netdev); 418 struct hnae3_handle *h = hns3_get_handle(netdev); 419 const struct hnae3_ae_ops *ops; 420 int i; 421 422 /* disable vectors */ 423 for (i = 0; i < priv->vector_num; i++) 424 hns3_vector_disable(&priv->tqp_vector[i]); 425 426 /* disable rcb */ 427 for (i = 0; i < h->kinfo.num_tqps; i++) 428 hns3_tqp_disable(h->kinfo.tqp[i]); 429 430 /* stop ae_dev */ 431 ops = priv->ae_handle->ae_algo->ops; 432 if (ops->stop) 433 ops->stop(priv->ae_handle); 434 435 /* free irq resources */ 436 hns3_nic_uninit_irq(priv); 437 438 hns3_clear_all_ring(priv->ae_handle); 439 } 440 441 static int hns3_nic_net_stop(struct net_device *netdev) 442 { 443 struct hns3_nic_priv *priv = netdev_priv(netdev); 444 struct hnae3_handle *h = hns3_get_handle(netdev); 445 446 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 447 return 0; 448 449 if (h->ae_algo->ops->set_timer_task) 450 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 451 452 netif_tx_stop_all_queues(netdev); 453 netif_carrier_off(netdev); 454 455 hns3_nic_net_down(netdev); 456 457 return 0; 458 } 459 460 static int hns3_nic_uc_sync(struct net_device *netdev, 461 const unsigned char *addr) 462 { 463 struct hnae3_handle *h = hns3_get_handle(netdev); 464 465 if (h->ae_algo->ops->add_uc_addr) 466 return h->ae_algo->ops->add_uc_addr(h, addr); 467 468 return 0; 469 } 470 471 static int hns3_nic_uc_unsync(struct net_device *netdev, 472 const unsigned char *addr) 473 { 474 struct hnae3_handle *h = hns3_get_handle(netdev); 475 476 if (h->ae_algo->ops->rm_uc_addr) 477 return h->ae_algo->ops->rm_uc_addr(h, addr); 478 479 return 0; 480 } 481 482 static int hns3_nic_mc_sync(struct net_device *netdev, 483 const unsigned char *addr) 484 { 485 struct hnae3_handle *h = hns3_get_handle(netdev); 486 487 if (h->ae_algo->ops->add_mc_addr) 488 return h->ae_algo->ops->add_mc_addr(h, addr); 489 490 return 0; 491 } 492 493 static int hns3_nic_mc_unsync(struct net_device *netdev, 494 const unsigned char *addr) 495 { 496 struct hnae3_handle *h = hns3_get_handle(netdev); 497 498 if (h->ae_algo->ops->rm_mc_addr) 499 return h->ae_algo->ops->rm_mc_addr(h, addr); 500 501 return 0; 502 } 503 504 static u8 hns3_get_netdev_flags(struct net_device *netdev) 505 { 506 u8 flags = 0; 507 508 if (netdev->flags & IFF_PROMISC) { 509 flags = HNAE3_USER_UPE | HNAE3_USER_MPE; 510 } else { 511 flags |= HNAE3_VLAN_FLTR; 512 if (netdev->flags & IFF_ALLMULTI) 513 flags |= HNAE3_USER_MPE; 514 } 515 516 return flags; 517 } 518 519 static void hns3_nic_set_rx_mode(struct net_device *netdev) 520 { 521 struct hnae3_handle *h = hns3_get_handle(netdev); 522 u8 new_flags; 523 int ret; 524 525 new_flags = hns3_get_netdev_flags(netdev); 526 527 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 528 if (ret) { 529 netdev_err(netdev, "sync uc address fail\n"); 530 if (ret == -ENOSPC) 531 new_flags |= HNAE3_OVERFLOW_UPE; 532 } 533 534 if (netdev->flags & IFF_MULTICAST) { 535 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 536 hns3_nic_mc_unsync); 537 if (ret) { 538 netdev_err(netdev, "sync mc address fail\n"); 539 if (ret == -ENOSPC) 540 new_flags |= HNAE3_OVERFLOW_MPE; 541 } 542 } 543 544 hns3_update_promisc_mode(netdev, new_flags); 545 /* User mode Promisc mode enable and vlan filtering is disabled to 546 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 547 * vlan fitering is enabled 548 */ 549 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 550 h->netdev_flags = new_flags; 551 } 552 553 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 554 { 555 struct hns3_nic_priv *priv = netdev_priv(netdev); 556 struct hnae3_handle *h = priv->ae_handle; 557 558 if (h->ae_algo->ops->set_promisc_mode) { 559 return h->ae_algo->ops->set_promisc_mode(h, 560 promisc_flags & HNAE3_UPE, 561 promisc_flags & HNAE3_MPE); 562 } 563 564 return 0; 565 } 566 567 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 568 { 569 struct hns3_nic_priv *priv = netdev_priv(netdev); 570 struct hnae3_handle *h = priv->ae_handle; 571 bool last_state; 572 573 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 574 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 575 if (enable != last_state) { 576 netdev_info(netdev, 577 "%s vlan filter\n", 578 enable ? "enable" : "disable"); 579 h->ae_algo->ops->enable_vlan_filter(h, enable); 580 } 581 } 582 } 583 584 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 585 u16 *mss, u32 *type_cs_vlan_tso) 586 { 587 u32 l4_offset, hdr_len; 588 union l3_hdr_info l3; 589 union l4_hdr_info l4; 590 u32 l4_paylen; 591 int ret; 592 593 if (!skb_is_gso(skb)) 594 return 0; 595 596 ret = skb_cow_head(skb, 0); 597 if (ret) 598 return ret; 599 600 l3.hdr = skb_network_header(skb); 601 l4.hdr = skb_transport_header(skb); 602 603 /* Software should clear the IPv4's checksum field when tso is 604 * needed. 605 */ 606 if (l3.v4->version == 4) 607 l3.v4->check = 0; 608 609 /* tunnel packet.*/ 610 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 611 SKB_GSO_GRE_CSUM | 612 SKB_GSO_UDP_TUNNEL | 613 SKB_GSO_UDP_TUNNEL_CSUM)) { 614 if ((!(skb_shinfo(skb)->gso_type & 615 SKB_GSO_PARTIAL)) && 616 (skb_shinfo(skb)->gso_type & 617 SKB_GSO_UDP_TUNNEL_CSUM)) { 618 /* Software should clear the udp's checksum 619 * field when tso is needed. 620 */ 621 l4.udp->check = 0; 622 } 623 /* reset l3&l4 pointers from outer to inner headers */ 624 l3.hdr = skb_inner_network_header(skb); 625 l4.hdr = skb_inner_transport_header(skb); 626 627 /* Software should clear the IPv4's checksum field when 628 * tso is needed. 629 */ 630 if (l3.v4->version == 4) 631 l3.v4->check = 0; 632 } 633 634 /* normal or tunnel packet*/ 635 l4_offset = l4.hdr - skb->data; 636 hdr_len = (l4.tcp->doff * 4) + l4_offset; 637 638 /* remove payload length from inner pseudo checksum when tso*/ 639 l4_paylen = skb->len - l4_offset; 640 csum_replace_by_diff(&l4.tcp->check, 641 (__force __wsum)htonl(l4_paylen)); 642 643 /* find the txbd field values */ 644 *paylen = skb->len - hdr_len; 645 hnae3_set_bit(*type_cs_vlan_tso, 646 HNS3_TXD_TSO_B, 1); 647 648 /* get MSS for TSO */ 649 *mss = skb_shinfo(skb)->gso_size; 650 651 return 0; 652 } 653 654 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 655 u8 *il4_proto) 656 { 657 union { 658 struct iphdr *v4; 659 struct ipv6hdr *v6; 660 unsigned char *hdr; 661 } l3; 662 unsigned char *l4_hdr; 663 unsigned char *exthdr; 664 u8 l4_proto_tmp; 665 __be16 frag_off; 666 667 /* find outer header point */ 668 l3.hdr = skb_network_header(skb); 669 l4_hdr = skb_transport_header(skb); 670 671 if (skb->protocol == htons(ETH_P_IPV6)) { 672 exthdr = l3.hdr + sizeof(*l3.v6); 673 l4_proto_tmp = l3.v6->nexthdr; 674 if (l4_hdr != exthdr) 675 ipv6_skip_exthdr(skb, exthdr - skb->data, 676 &l4_proto_tmp, &frag_off); 677 } else if (skb->protocol == htons(ETH_P_IP)) { 678 l4_proto_tmp = l3.v4->protocol; 679 } else { 680 return -EINVAL; 681 } 682 683 *ol4_proto = l4_proto_tmp; 684 685 /* tunnel packet */ 686 if (!skb->encapsulation) { 687 *il4_proto = 0; 688 return 0; 689 } 690 691 /* find inner header point */ 692 l3.hdr = skb_inner_network_header(skb); 693 l4_hdr = skb_inner_transport_header(skb); 694 695 if (l3.v6->version == 6) { 696 exthdr = l3.hdr + sizeof(*l3.v6); 697 l4_proto_tmp = l3.v6->nexthdr; 698 if (l4_hdr != exthdr) 699 ipv6_skip_exthdr(skb, exthdr - skb->data, 700 &l4_proto_tmp, &frag_off); 701 } else if (l3.v4->version == 4) { 702 l4_proto_tmp = l3.v4->protocol; 703 } 704 705 *il4_proto = l4_proto_tmp; 706 707 return 0; 708 } 709 710 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 711 u8 il4_proto, u32 *type_cs_vlan_tso, 712 u32 *ol_type_vlan_len_msec) 713 { 714 union { 715 struct iphdr *v4; 716 struct ipv6hdr *v6; 717 unsigned char *hdr; 718 } l3; 719 union { 720 struct tcphdr *tcp; 721 struct udphdr *udp; 722 struct gre_base_hdr *gre; 723 unsigned char *hdr; 724 } l4; 725 unsigned char *l2_hdr; 726 u8 l4_proto = ol4_proto; 727 u32 ol2_len; 728 u32 ol3_len; 729 u32 ol4_len; 730 u32 l2_len; 731 u32 l3_len; 732 733 l3.hdr = skb_network_header(skb); 734 l4.hdr = skb_transport_header(skb); 735 736 /* compute L2 header size for normal packet, defined in 2 Bytes */ 737 l2_len = l3.hdr - skb->data; 738 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 739 HNS3_TXD_L2LEN_S, l2_len >> 1); 740 741 /* tunnel packet*/ 742 if (skb->encapsulation) { 743 /* compute OL2 header size, defined in 2 Bytes */ 744 ol2_len = l2_len; 745 hnae3_set_field(*ol_type_vlan_len_msec, 746 HNS3_TXD_L2LEN_M, 747 HNS3_TXD_L2LEN_S, ol2_len >> 1); 748 749 /* compute OL3 header size, defined in 4 Bytes */ 750 ol3_len = l4.hdr - l3.hdr; 751 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 752 HNS3_TXD_L3LEN_S, ol3_len >> 2); 753 754 /* MAC in UDP, MAC in GRE (0x6558)*/ 755 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 756 /* switch MAC header ptr from outer to inner header.*/ 757 l2_hdr = skb_inner_mac_header(skb); 758 759 /* compute OL4 header size, defined in 4 Bytes. */ 760 ol4_len = l2_hdr - l4.hdr; 761 hnae3_set_field(*ol_type_vlan_len_msec, 762 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 763 ol4_len >> 2); 764 765 /* switch IP header ptr from outer to inner header */ 766 l3.hdr = skb_inner_network_header(skb); 767 768 /* compute inner l2 header size, defined in 2 Bytes. */ 769 l2_len = l3.hdr - l2_hdr; 770 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 771 HNS3_TXD_L2LEN_S, l2_len >> 1); 772 } else { 773 /* skb packet types not supported by hardware, 774 * txbd len fild doesn't be filled. 775 */ 776 return; 777 } 778 779 /* switch L4 header pointer from outer to inner */ 780 l4.hdr = skb_inner_transport_header(skb); 781 782 l4_proto = il4_proto; 783 } 784 785 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 786 l3_len = l4.hdr - l3.hdr; 787 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 788 HNS3_TXD_L3LEN_S, l3_len >> 2); 789 790 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 791 switch (l4_proto) { 792 case IPPROTO_TCP: 793 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 794 HNS3_TXD_L4LEN_S, l4.tcp->doff); 795 break; 796 case IPPROTO_SCTP: 797 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 798 HNS3_TXD_L4LEN_S, 799 (sizeof(struct sctphdr) >> 2)); 800 break; 801 case IPPROTO_UDP: 802 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 803 HNS3_TXD_L4LEN_S, 804 (sizeof(struct udphdr) >> 2)); 805 break; 806 default: 807 /* skb packet types not supported by hardware, 808 * txbd len fild doesn't be filled. 809 */ 810 return; 811 } 812 } 813 814 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 815 * and it is udp packet, which has a dest port as the IANA assigned. 816 * the hardware is expected to do the checksum offload, but the 817 * hardware will not do the checksum offload when udp dest port is 818 * 4789. 819 */ 820 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 821 { 822 #define IANA_VXLAN_PORT 4789 823 union { 824 struct tcphdr *tcp; 825 struct udphdr *udp; 826 struct gre_base_hdr *gre; 827 unsigned char *hdr; 828 } l4; 829 830 l4.hdr = skb_transport_header(skb); 831 832 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 833 return false; 834 835 skb_checksum_help(skb); 836 837 return true; 838 } 839 840 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 841 u8 il4_proto, u32 *type_cs_vlan_tso, 842 u32 *ol_type_vlan_len_msec) 843 { 844 union { 845 struct iphdr *v4; 846 struct ipv6hdr *v6; 847 unsigned char *hdr; 848 } l3; 849 u32 l4_proto = ol4_proto; 850 851 l3.hdr = skb_network_header(skb); 852 853 /* define OL3 type and tunnel type(OL4).*/ 854 if (skb->encapsulation) { 855 /* define outer network header type.*/ 856 if (skb->protocol == htons(ETH_P_IP)) { 857 if (skb_is_gso(skb)) 858 hnae3_set_field(*ol_type_vlan_len_msec, 859 HNS3_TXD_OL3T_M, 860 HNS3_TXD_OL3T_S, 861 HNS3_OL3T_IPV4_CSUM); 862 else 863 hnae3_set_field(*ol_type_vlan_len_msec, 864 HNS3_TXD_OL3T_M, 865 HNS3_TXD_OL3T_S, 866 HNS3_OL3T_IPV4_NO_CSUM); 867 868 } else if (skb->protocol == htons(ETH_P_IPV6)) { 869 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 870 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 871 } 872 873 /* define tunnel type(OL4).*/ 874 switch (l4_proto) { 875 case IPPROTO_UDP: 876 hnae3_set_field(*ol_type_vlan_len_msec, 877 HNS3_TXD_TUNTYPE_M, 878 HNS3_TXD_TUNTYPE_S, 879 HNS3_TUN_MAC_IN_UDP); 880 break; 881 case IPPROTO_GRE: 882 hnae3_set_field(*ol_type_vlan_len_msec, 883 HNS3_TXD_TUNTYPE_M, 884 HNS3_TXD_TUNTYPE_S, 885 HNS3_TUN_NVGRE); 886 break; 887 default: 888 /* drop the skb tunnel packet if hardware don't support, 889 * because hardware can't calculate csum when TSO. 890 */ 891 if (skb_is_gso(skb)) 892 return -EDOM; 893 894 /* the stack computes the IP header already, 895 * driver calculate l4 checksum when not TSO. 896 */ 897 skb_checksum_help(skb); 898 return 0; 899 } 900 901 l3.hdr = skb_inner_network_header(skb); 902 l4_proto = il4_proto; 903 } 904 905 if (l3.v4->version == 4) { 906 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 907 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 908 909 /* the stack computes the IP header already, the only time we 910 * need the hardware to recompute it is in the case of TSO. 911 */ 912 if (skb_is_gso(skb)) 913 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 914 } else if (l3.v6->version == 6) { 915 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 916 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 917 } 918 919 switch (l4_proto) { 920 case IPPROTO_TCP: 921 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 922 hnae3_set_field(*type_cs_vlan_tso, 923 HNS3_TXD_L4T_M, 924 HNS3_TXD_L4T_S, 925 HNS3_L4T_TCP); 926 break; 927 case IPPROTO_UDP: 928 if (hns3_tunnel_csum_bug(skb)) 929 break; 930 931 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 932 hnae3_set_field(*type_cs_vlan_tso, 933 HNS3_TXD_L4T_M, 934 HNS3_TXD_L4T_S, 935 HNS3_L4T_UDP); 936 break; 937 case IPPROTO_SCTP: 938 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 939 hnae3_set_field(*type_cs_vlan_tso, 940 HNS3_TXD_L4T_M, 941 HNS3_TXD_L4T_S, 942 HNS3_L4T_SCTP); 943 break; 944 default: 945 /* drop the skb tunnel packet if hardware don't support, 946 * because hardware can't calculate csum when TSO. 947 */ 948 if (skb_is_gso(skb)) 949 return -EDOM; 950 951 /* the stack computes the IP header already, 952 * driver calculate l4 checksum when not TSO. 953 */ 954 skb_checksum_help(skb); 955 return 0; 956 } 957 958 return 0; 959 } 960 961 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 962 { 963 /* Config bd buffer end */ 964 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 965 HNS3_TXD_BDTYPE_S, 0); 966 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 967 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 968 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 969 } 970 971 static int hns3_fill_desc_vtags(struct sk_buff *skb, 972 struct hns3_enet_ring *tx_ring, 973 u32 *inner_vlan_flag, 974 u32 *out_vlan_flag, 975 u16 *inner_vtag, 976 u16 *out_vtag) 977 { 978 #define HNS3_TX_VLAN_PRIO_SHIFT 13 979 980 if (skb->protocol == htons(ETH_P_8021Q) && 981 !(tx_ring->tqp->handle->kinfo.netdev->features & 982 NETIF_F_HW_VLAN_CTAG_TX)) { 983 /* When HW VLAN acceleration is turned off, and the stack 984 * sets the protocol to 802.1q, the driver just need to 985 * set the protocol to the encapsulated ethertype. 986 */ 987 skb->protocol = vlan_get_protocol(skb); 988 return 0; 989 } 990 991 if (skb_vlan_tag_present(skb)) { 992 u16 vlan_tag; 993 994 vlan_tag = skb_vlan_tag_get(skb); 995 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 996 997 /* Based on hw strategy, use out_vtag in two layer tag case, 998 * and use inner_vtag in one tag case. 999 */ 1000 if (skb->protocol == htons(ETH_P_8021Q)) { 1001 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 1002 *out_vtag = vlan_tag; 1003 } else { 1004 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 1005 *inner_vtag = vlan_tag; 1006 } 1007 } else if (skb->protocol == htons(ETH_P_8021Q)) { 1008 struct vlan_ethhdr *vhdr; 1009 int rc; 1010 1011 rc = skb_cow_head(skb, 0); 1012 if (rc < 0) 1013 return rc; 1014 vhdr = (struct vlan_ethhdr *)skb->data; 1015 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1016 << HNS3_TX_VLAN_PRIO_SHIFT); 1017 } 1018 1019 skb->protocol = vlan_get_protocol(skb); 1020 return 0; 1021 } 1022 1023 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1024 int size, int frag_end, enum hns_desc_type type) 1025 { 1026 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1027 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1028 struct device *dev = ring_to_dev(ring); 1029 u32 ol_type_vlan_len_msec = 0; 1030 u16 bdtp_fe_sc_vld_ra_ri = 0; 1031 struct skb_frag_struct *frag; 1032 unsigned int frag_buf_num; 1033 u32 type_cs_vlan_tso = 0; 1034 struct sk_buff *skb; 1035 u16 inner_vtag = 0; 1036 u16 out_vtag = 0; 1037 unsigned int k; 1038 int sizeoflast; 1039 u32 paylen = 0; 1040 dma_addr_t dma; 1041 u16 mss = 0; 1042 u8 ol4_proto; 1043 u8 il4_proto; 1044 int ret; 1045 1046 if (type == DESC_TYPE_SKB) { 1047 skb = (struct sk_buff *)priv; 1048 paylen = skb->len; 1049 1050 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1051 &ol_type_vlan_len_msec, 1052 &inner_vtag, &out_vtag); 1053 if (unlikely(ret)) 1054 return ret; 1055 1056 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1057 skb_reset_mac_len(skb); 1058 1059 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1060 if (ret) 1061 return ret; 1062 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1063 &type_cs_vlan_tso, 1064 &ol_type_vlan_len_msec); 1065 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1066 &type_cs_vlan_tso, 1067 &ol_type_vlan_len_msec); 1068 if (ret) 1069 return ret; 1070 1071 ret = hns3_set_tso(skb, &paylen, &mss, 1072 &type_cs_vlan_tso); 1073 if (ret) 1074 return ret; 1075 } 1076 1077 /* Set txbd */ 1078 desc->tx.ol_type_vlan_len_msec = 1079 cpu_to_le32(ol_type_vlan_len_msec); 1080 desc->tx.type_cs_vlan_tso_len = 1081 cpu_to_le32(type_cs_vlan_tso); 1082 desc->tx.paylen = cpu_to_le32(paylen); 1083 desc->tx.mss = cpu_to_le16(mss); 1084 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1085 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1086 1087 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1088 } else { 1089 frag = (struct skb_frag_struct *)priv; 1090 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1091 } 1092 1093 if (dma_mapping_error(ring->dev, dma)) { 1094 ring->stats.sw_err_cnt++; 1095 return -ENOMEM; 1096 } 1097 1098 desc_cb->length = size; 1099 1100 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1101 sizeoflast = size % HNS3_MAX_BD_SIZE; 1102 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1103 1104 /* When frag size is bigger than hardware limit, split this frag */ 1105 for (k = 0; k < frag_buf_num; k++) { 1106 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1107 desc_cb->priv = priv; 1108 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1109 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1110 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1111 1112 /* now, fill the descriptor */ 1113 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1114 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1115 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1116 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1117 frag_end && (k == frag_buf_num - 1) ? 1118 1 : 0); 1119 desc->tx.bdtp_fe_sc_vld_ra_ri = 1120 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1121 1122 /* move ring pointer to next.*/ 1123 ring_ptr_move_fw(ring, next_to_use); 1124 1125 desc_cb = &ring->desc_cb[ring->next_to_use]; 1126 desc = &ring->desc[ring->next_to_use]; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1133 struct hns3_enet_ring *ring) 1134 { 1135 struct sk_buff *skb = *out_skb; 1136 struct skb_frag_struct *frag; 1137 int bdnum_for_frag; 1138 int frag_num; 1139 int buf_num; 1140 int size; 1141 int i; 1142 1143 size = skb_headlen(skb); 1144 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1145 1146 frag_num = skb_shinfo(skb)->nr_frags; 1147 for (i = 0; i < frag_num; i++) { 1148 frag = &skb_shinfo(skb)->frags[i]; 1149 size = skb_frag_size(frag); 1150 bdnum_for_frag = 1151 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1152 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1153 return -ENOMEM; 1154 1155 buf_num += bdnum_for_frag; 1156 } 1157 1158 if (buf_num > ring_space(ring)) 1159 return -EBUSY; 1160 1161 *bnum = buf_num; 1162 return 0; 1163 } 1164 1165 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1166 struct hns3_enet_ring *ring) 1167 { 1168 struct sk_buff *skb = *out_skb; 1169 int buf_num; 1170 1171 /* No. of segments (plus a header) */ 1172 buf_num = skb_shinfo(skb)->nr_frags + 1; 1173 1174 if (unlikely(ring_space(ring) < buf_num)) 1175 return -EBUSY; 1176 1177 *bnum = buf_num; 1178 1179 return 0; 1180 } 1181 1182 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1183 { 1184 struct device *dev = ring_to_dev(ring); 1185 unsigned int i; 1186 1187 for (i = 0; i < ring->desc_num; i++) { 1188 /* check if this is where we started */ 1189 if (ring->next_to_use == next_to_use_orig) 1190 break; 1191 1192 /* unmap the descriptor dma address */ 1193 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1194 dma_unmap_single(dev, 1195 ring->desc_cb[ring->next_to_use].dma, 1196 ring->desc_cb[ring->next_to_use].length, 1197 DMA_TO_DEVICE); 1198 else if (ring->desc_cb[ring->next_to_use].length) 1199 dma_unmap_page(dev, 1200 ring->desc_cb[ring->next_to_use].dma, 1201 ring->desc_cb[ring->next_to_use].length, 1202 DMA_TO_DEVICE); 1203 1204 ring->desc_cb[ring->next_to_use].length = 0; 1205 1206 /* rollback one */ 1207 ring_ptr_move_bw(ring, next_to_use); 1208 } 1209 } 1210 1211 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1212 { 1213 struct hns3_nic_priv *priv = netdev_priv(netdev); 1214 struct hns3_nic_ring_data *ring_data = 1215 &tx_ring_data(priv, skb->queue_mapping); 1216 struct hns3_enet_ring *ring = ring_data->ring; 1217 struct netdev_queue *dev_queue; 1218 struct skb_frag_struct *frag; 1219 int next_to_use_head; 1220 int next_to_use_frag; 1221 int buf_num; 1222 int seg_num; 1223 int size; 1224 int ret; 1225 int i; 1226 1227 /* Prefetch the data used later */ 1228 prefetch(skb->data); 1229 1230 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1231 case -EBUSY: 1232 u64_stats_update_begin(&ring->syncp); 1233 ring->stats.tx_busy++; 1234 u64_stats_update_end(&ring->syncp); 1235 1236 goto out_net_tx_busy; 1237 case -ENOMEM: 1238 u64_stats_update_begin(&ring->syncp); 1239 ring->stats.sw_err_cnt++; 1240 u64_stats_update_end(&ring->syncp); 1241 netdev_err(netdev, "no memory to xmit!\n"); 1242 1243 goto out_err_tx_ok; 1244 default: 1245 break; 1246 } 1247 1248 /* No. of segments (plus a header) */ 1249 seg_num = skb_shinfo(skb)->nr_frags + 1; 1250 /* Fill the first part */ 1251 size = skb_headlen(skb); 1252 1253 next_to_use_head = ring->next_to_use; 1254 1255 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1256 DESC_TYPE_SKB); 1257 if (ret) 1258 goto head_fill_err; 1259 1260 next_to_use_frag = ring->next_to_use; 1261 /* Fill the fragments */ 1262 for (i = 1; i < seg_num; i++) { 1263 frag = &skb_shinfo(skb)->frags[i - 1]; 1264 size = skb_frag_size(frag); 1265 1266 ret = priv->ops.fill_desc(ring, frag, size, 1267 seg_num - 1 == i ? 1 : 0, 1268 DESC_TYPE_PAGE); 1269 1270 if (ret) 1271 goto frag_fill_err; 1272 } 1273 1274 /* Complete translate all packets */ 1275 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1276 netdev_tx_sent_queue(dev_queue, skb->len); 1277 1278 wmb(); /* Commit all data before submit */ 1279 1280 hnae3_queue_xmit(ring->tqp, buf_num); 1281 1282 return NETDEV_TX_OK; 1283 1284 frag_fill_err: 1285 hns3_clear_desc(ring, next_to_use_frag); 1286 1287 head_fill_err: 1288 hns3_clear_desc(ring, next_to_use_head); 1289 1290 out_err_tx_ok: 1291 dev_kfree_skb_any(skb); 1292 return NETDEV_TX_OK; 1293 1294 out_net_tx_busy: 1295 netif_stop_subqueue(netdev, ring_data->queue_index); 1296 smp_mb(); /* Commit all data before submit */ 1297 1298 return NETDEV_TX_BUSY; 1299 } 1300 1301 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1302 { 1303 struct hnae3_handle *h = hns3_get_handle(netdev); 1304 struct sockaddr *mac_addr = p; 1305 int ret; 1306 1307 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1308 return -EADDRNOTAVAIL; 1309 1310 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1311 netdev_info(netdev, "already using mac address %pM\n", 1312 mac_addr->sa_data); 1313 return 0; 1314 } 1315 1316 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1317 if (ret) { 1318 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1319 return ret; 1320 } 1321 1322 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1323 1324 return 0; 1325 } 1326 1327 static int hns3_nic_do_ioctl(struct net_device *netdev, 1328 struct ifreq *ifr, int cmd) 1329 { 1330 struct hnae3_handle *h = hns3_get_handle(netdev); 1331 1332 if (!netif_running(netdev)) 1333 return -EINVAL; 1334 1335 if (!h->ae_algo->ops->do_ioctl) 1336 return -EOPNOTSUPP; 1337 1338 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1339 } 1340 1341 static int hns3_nic_set_features(struct net_device *netdev, 1342 netdev_features_t features) 1343 { 1344 netdev_features_t changed = netdev->features ^ features; 1345 struct hns3_nic_priv *priv = netdev_priv(netdev); 1346 struct hnae3_handle *h = priv->ae_handle; 1347 int ret; 1348 1349 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1350 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1351 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1352 else 1353 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1354 } 1355 1356 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1357 if (features & NETIF_F_GRO_HW) 1358 ret = h->ae_algo->ops->set_gro_en(h, true); 1359 else 1360 ret = h->ae_algo->ops->set_gro_en(h, false); 1361 if (ret) 1362 return ret; 1363 } 1364 1365 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1366 h->ae_algo->ops->enable_vlan_filter) { 1367 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1368 h->ae_algo->ops->enable_vlan_filter(h, true); 1369 else 1370 h->ae_algo->ops->enable_vlan_filter(h, false); 1371 } 1372 1373 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1374 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1375 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1376 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1377 else 1378 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1379 1380 if (ret) 1381 return ret; 1382 } 1383 1384 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1385 if (features & NETIF_F_NTUPLE) 1386 h->ae_algo->ops->enable_fd(h, true); 1387 else 1388 h->ae_algo->ops->enable_fd(h, false); 1389 } 1390 1391 netdev->features = features; 1392 return 0; 1393 } 1394 1395 static void hns3_nic_get_stats64(struct net_device *netdev, 1396 struct rtnl_link_stats64 *stats) 1397 { 1398 struct hns3_nic_priv *priv = netdev_priv(netdev); 1399 int queue_num = priv->ae_handle->kinfo.num_tqps; 1400 struct hnae3_handle *handle = priv->ae_handle; 1401 struct hns3_enet_ring *ring; 1402 unsigned int start; 1403 unsigned int idx; 1404 u64 tx_bytes = 0; 1405 u64 rx_bytes = 0; 1406 u64 tx_pkts = 0; 1407 u64 rx_pkts = 0; 1408 u64 tx_drop = 0; 1409 u64 rx_drop = 0; 1410 1411 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1412 return; 1413 1414 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1415 1416 for (idx = 0; idx < queue_num; idx++) { 1417 /* fetch the tx stats */ 1418 ring = priv->ring_data[idx].ring; 1419 do { 1420 start = u64_stats_fetch_begin_irq(&ring->syncp); 1421 tx_bytes += ring->stats.tx_bytes; 1422 tx_pkts += ring->stats.tx_pkts; 1423 tx_drop += ring->stats.tx_busy; 1424 tx_drop += ring->stats.sw_err_cnt; 1425 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1426 1427 /* fetch the rx stats */ 1428 ring = priv->ring_data[idx + queue_num].ring; 1429 do { 1430 start = u64_stats_fetch_begin_irq(&ring->syncp); 1431 rx_bytes += ring->stats.rx_bytes; 1432 rx_pkts += ring->stats.rx_pkts; 1433 rx_drop += ring->stats.non_vld_descs; 1434 rx_drop += ring->stats.err_pkt_len; 1435 rx_drop += ring->stats.l2_err; 1436 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1437 } 1438 1439 stats->tx_bytes = tx_bytes; 1440 stats->tx_packets = tx_pkts; 1441 stats->rx_bytes = rx_bytes; 1442 stats->rx_packets = rx_pkts; 1443 1444 stats->rx_errors = netdev->stats.rx_errors; 1445 stats->multicast = netdev->stats.multicast; 1446 stats->rx_length_errors = netdev->stats.rx_length_errors; 1447 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1448 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1449 1450 stats->tx_errors = netdev->stats.tx_errors; 1451 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1452 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1453 stats->collisions = netdev->stats.collisions; 1454 stats->rx_over_errors = netdev->stats.rx_over_errors; 1455 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1456 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1457 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1458 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1459 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1460 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1461 stats->tx_window_errors = netdev->stats.tx_window_errors; 1462 stats->rx_compressed = netdev->stats.rx_compressed; 1463 stats->tx_compressed = netdev->stats.tx_compressed; 1464 } 1465 1466 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1467 { 1468 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1469 struct hnae3_handle *h = hns3_get_handle(netdev); 1470 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1471 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1472 u8 tc = mqprio_qopt->qopt.num_tc; 1473 u16 mode = mqprio_qopt->mode; 1474 u8 hw = mqprio_qopt->qopt.hw; 1475 bool if_running; 1476 int ret; 1477 1478 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1479 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1480 return -EOPNOTSUPP; 1481 1482 if (tc > HNAE3_MAX_TC) 1483 return -EINVAL; 1484 1485 if (!netdev) 1486 return -EINVAL; 1487 1488 if_running = netif_running(netdev); 1489 if (if_running) { 1490 hns3_nic_net_stop(netdev); 1491 msleep(100); 1492 } 1493 1494 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1495 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1496 if (ret) 1497 goto out; 1498 1499 ret = hns3_nic_set_real_num_queue(netdev); 1500 1501 out: 1502 if (if_running) 1503 hns3_nic_net_open(netdev); 1504 1505 return ret; 1506 } 1507 1508 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1509 void *type_data) 1510 { 1511 if (type != TC_SETUP_QDISC_MQPRIO) 1512 return -EOPNOTSUPP; 1513 1514 return hns3_setup_tc(dev, type_data); 1515 } 1516 1517 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1518 __be16 proto, u16 vid) 1519 { 1520 struct hnae3_handle *h = hns3_get_handle(netdev); 1521 struct hns3_nic_priv *priv = netdev_priv(netdev); 1522 int ret = -EIO; 1523 1524 if (h->ae_algo->ops->set_vlan_filter) 1525 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1526 1527 if (!ret) 1528 set_bit(vid, priv->active_vlans); 1529 1530 return ret; 1531 } 1532 1533 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1534 __be16 proto, u16 vid) 1535 { 1536 struct hnae3_handle *h = hns3_get_handle(netdev); 1537 struct hns3_nic_priv *priv = netdev_priv(netdev); 1538 int ret = -EIO; 1539 1540 if (h->ae_algo->ops->set_vlan_filter) 1541 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1542 1543 if (!ret) 1544 clear_bit(vid, priv->active_vlans); 1545 1546 return ret; 1547 } 1548 1549 static int hns3_restore_vlan(struct net_device *netdev) 1550 { 1551 struct hns3_nic_priv *priv = netdev_priv(netdev); 1552 int ret = 0; 1553 u16 vid; 1554 1555 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1556 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1557 if (ret) { 1558 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1559 vid, ret); 1560 return ret; 1561 } 1562 } 1563 1564 return ret; 1565 } 1566 1567 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1568 u8 qos, __be16 vlan_proto) 1569 { 1570 struct hnae3_handle *h = hns3_get_handle(netdev); 1571 int ret = -EIO; 1572 1573 if (h->ae_algo->ops->set_vf_vlan_filter) 1574 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1575 qos, vlan_proto); 1576 1577 return ret; 1578 } 1579 1580 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1581 { 1582 struct hnae3_handle *h = hns3_get_handle(netdev); 1583 int ret; 1584 1585 if (!h->ae_algo->ops->set_mtu) 1586 return -EOPNOTSUPP; 1587 1588 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1589 if (ret) 1590 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1591 ret); 1592 else 1593 netdev->mtu = new_mtu; 1594 1595 return ret; 1596 } 1597 1598 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1599 { 1600 struct hns3_nic_priv *priv = netdev_priv(ndev); 1601 struct hns3_enet_ring *tx_ring = NULL; 1602 int timeout_queue = 0; 1603 int hw_head, hw_tail; 1604 int i; 1605 1606 /* Find the stopped queue the same way the stack does */ 1607 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1608 struct netdev_queue *q; 1609 unsigned long trans_start; 1610 1611 q = netdev_get_tx_queue(ndev, i); 1612 trans_start = q->trans_start; 1613 if (netif_xmit_stopped(q) && 1614 time_after(jiffies, 1615 (trans_start + ndev->watchdog_timeo))) { 1616 timeout_queue = i; 1617 break; 1618 } 1619 } 1620 1621 if (i == ndev->num_tx_queues) { 1622 netdev_info(ndev, 1623 "no netdev TX timeout queue found, timeout count: %llu\n", 1624 priv->tx_timeout_count); 1625 return false; 1626 } 1627 1628 tx_ring = priv->ring_data[timeout_queue].ring; 1629 1630 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1631 HNS3_RING_TX_RING_HEAD_REG); 1632 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1633 HNS3_RING_TX_RING_TAIL_REG); 1634 netdev_info(ndev, 1635 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1636 priv->tx_timeout_count, 1637 timeout_queue, 1638 tx_ring->next_to_use, 1639 tx_ring->next_to_clean, 1640 hw_head, 1641 hw_tail, 1642 readl(tx_ring->tqp_vector->mask_addr)); 1643 1644 return true; 1645 } 1646 1647 static void hns3_nic_net_timeout(struct net_device *ndev) 1648 { 1649 struct hns3_nic_priv *priv = netdev_priv(ndev); 1650 struct hnae3_handle *h = priv->ae_handle; 1651 1652 if (!hns3_get_tx_timeo_queue_info(ndev)) 1653 return; 1654 1655 priv->tx_timeout_count++; 1656 1657 /* request the reset, and let the hclge to determine 1658 * which reset level should be done 1659 */ 1660 if (h->ae_algo->ops->reset_event) 1661 h->ae_algo->ops->reset_event(h->pdev, h); 1662 } 1663 1664 static const struct net_device_ops hns3_nic_netdev_ops = { 1665 .ndo_open = hns3_nic_net_open, 1666 .ndo_stop = hns3_nic_net_stop, 1667 .ndo_start_xmit = hns3_nic_net_xmit, 1668 .ndo_tx_timeout = hns3_nic_net_timeout, 1669 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1670 .ndo_do_ioctl = hns3_nic_do_ioctl, 1671 .ndo_change_mtu = hns3_nic_change_mtu, 1672 .ndo_set_features = hns3_nic_set_features, 1673 .ndo_get_stats64 = hns3_nic_get_stats64, 1674 .ndo_setup_tc = hns3_nic_setup_tc, 1675 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1676 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1677 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1678 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1679 }; 1680 1681 static bool hns3_is_phys_func(struct pci_dev *pdev) 1682 { 1683 u32 dev_id = pdev->device; 1684 1685 switch (dev_id) { 1686 case HNAE3_DEV_ID_GE: 1687 case HNAE3_DEV_ID_25GE: 1688 case HNAE3_DEV_ID_25GE_RDMA: 1689 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1690 case HNAE3_DEV_ID_50GE_RDMA: 1691 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1692 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1693 return true; 1694 case HNAE3_DEV_ID_100G_VF: 1695 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1696 return false; 1697 default: 1698 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1699 dev_id); 1700 } 1701 1702 return false; 1703 } 1704 1705 static void hns3_disable_sriov(struct pci_dev *pdev) 1706 { 1707 /* If our VFs are assigned we cannot shut down SR-IOV 1708 * without causing issues, so just leave the hardware 1709 * available but disabled 1710 */ 1711 if (pci_vfs_assigned(pdev)) { 1712 dev_warn(&pdev->dev, 1713 "disabling driver while VFs are assigned\n"); 1714 return; 1715 } 1716 1717 pci_disable_sriov(pdev); 1718 } 1719 1720 static void hns3_get_dev_capability(struct pci_dev *pdev, 1721 struct hnae3_ae_dev *ae_dev) 1722 { 1723 if (pdev->revision >= 0x21) { 1724 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1725 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1726 } 1727 } 1728 1729 /* hns3_probe - Device initialization routine 1730 * @pdev: PCI device information struct 1731 * @ent: entry in hns3_pci_tbl 1732 * 1733 * hns3_probe initializes a PF identified by a pci_dev structure. 1734 * The OS initialization, configuring of the PF private structure, 1735 * and a hardware reset occur. 1736 * 1737 * Returns 0 on success, negative on failure 1738 */ 1739 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1740 { 1741 struct hnae3_ae_dev *ae_dev; 1742 int ret; 1743 1744 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1745 GFP_KERNEL); 1746 if (!ae_dev) { 1747 ret = -ENOMEM; 1748 return ret; 1749 } 1750 1751 ae_dev->pdev = pdev; 1752 ae_dev->flag = ent->driver_data; 1753 ae_dev->dev_type = HNAE3_DEV_KNIC; 1754 ae_dev->reset_type = HNAE3_NONE_RESET; 1755 hns3_get_dev_capability(pdev, ae_dev); 1756 pci_set_drvdata(pdev, ae_dev); 1757 1758 hnae3_register_ae_dev(ae_dev); 1759 1760 return 0; 1761 } 1762 1763 /* hns3_remove - Device removal routine 1764 * @pdev: PCI device information struct 1765 */ 1766 static void hns3_remove(struct pci_dev *pdev) 1767 { 1768 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1769 1770 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1771 hns3_disable_sriov(pdev); 1772 1773 hnae3_unregister_ae_dev(ae_dev); 1774 } 1775 1776 /** 1777 * hns3_pci_sriov_configure 1778 * @pdev: pointer to a pci_dev structure 1779 * @num_vfs: number of VFs to allocate 1780 * 1781 * Enable or change the number of VFs. Called when the user updates the number 1782 * of VFs in sysfs. 1783 **/ 1784 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1785 { 1786 int ret; 1787 1788 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1789 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1790 return -EINVAL; 1791 } 1792 1793 if (num_vfs) { 1794 ret = pci_enable_sriov(pdev, num_vfs); 1795 if (ret) 1796 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1797 else 1798 return num_vfs; 1799 } else if (!pci_vfs_assigned(pdev)) { 1800 pci_disable_sriov(pdev); 1801 } else { 1802 dev_warn(&pdev->dev, 1803 "Unable to free VFs because some are assigned to VMs.\n"); 1804 } 1805 1806 return 0; 1807 } 1808 1809 static void hns3_shutdown(struct pci_dev *pdev) 1810 { 1811 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1812 1813 hnae3_unregister_ae_dev(ae_dev); 1814 devm_kfree(&pdev->dev, ae_dev); 1815 pci_set_drvdata(pdev, NULL); 1816 1817 if (system_state == SYSTEM_POWER_OFF) 1818 pci_set_power_state(pdev, PCI_D3hot); 1819 } 1820 1821 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1822 pci_channel_state_t state) 1823 { 1824 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1825 pci_ers_result_t ret; 1826 1827 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1828 1829 if (state == pci_channel_io_perm_failure) 1830 return PCI_ERS_RESULT_DISCONNECT; 1831 1832 if (!ae_dev) { 1833 dev_err(&pdev->dev, 1834 "Can't recover - error happened during device init\n"); 1835 return PCI_ERS_RESULT_NONE; 1836 } 1837 1838 if (ae_dev->ops->handle_hw_ras_error) 1839 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1840 else 1841 return PCI_ERS_RESULT_NONE; 1842 1843 return ret; 1844 } 1845 1846 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1847 { 1848 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1849 struct device *dev = &pdev->dev; 1850 1851 dev_info(dev, "requesting reset due to PCI error\n"); 1852 1853 /* request the reset */ 1854 if (ae_dev->ops->reset_event) { 1855 ae_dev->ops->reset_event(pdev, NULL); 1856 return PCI_ERS_RESULT_RECOVERED; 1857 } 1858 1859 return PCI_ERS_RESULT_DISCONNECT; 1860 } 1861 1862 static void hns3_reset_prepare(struct pci_dev *pdev) 1863 { 1864 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1865 1866 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1867 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1868 ae_dev->ops->flr_prepare(ae_dev); 1869 } 1870 1871 static void hns3_reset_done(struct pci_dev *pdev) 1872 { 1873 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1874 1875 dev_info(&pdev->dev, "hns3 flr done\n"); 1876 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1877 ae_dev->ops->flr_done(ae_dev); 1878 } 1879 1880 static const struct pci_error_handlers hns3_err_handler = { 1881 .error_detected = hns3_error_detected, 1882 .slot_reset = hns3_slot_reset, 1883 .reset_prepare = hns3_reset_prepare, 1884 .reset_done = hns3_reset_done, 1885 }; 1886 1887 static struct pci_driver hns3_driver = { 1888 .name = hns3_driver_name, 1889 .id_table = hns3_pci_tbl, 1890 .probe = hns3_probe, 1891 .remove = hns3_remove, 1892 .shutdown = hns3_shutdown, 1893 .sriov_configure = hns3_pci_sriov_configure, 1894 .err_handler = &hns3_err_handler, 1895 }; 1896 1897 /* set default feature to hns3 */ 1898 static void hns3_set_default_feature(struct net_device *netdev) 1899 { 1900 struct hnae3_handle *h = hns3_get_handle(netdev); 1901 struct pci_dev *pdev = h->pdev; 1902 1903 netdev->priv_flags |= IFF_UNICAST_FLT; 1904 1905 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1906 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1907 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1908 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1909 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1910 1911 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1912 1913 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1914 1915 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1916 NETIF_F_HW_VLAN_CTAG_FILTER | 1917 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1918 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1919 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1920 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1921 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1922 1923 netdev->vlan_features |= 1924 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1925 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1926 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1927 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1928 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1929 1930 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1931 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1932 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1933 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1934 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1935 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1936 1937 if (pdev->revision >= 0x21) { 1938 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | 1939 NETIF_F_GRO_HW; 1940 netdev->features |= NETIF_F_GRO_HW; 1941 1942 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1943 netdev->hw_features |= NETIF_F_NTUPLE; 1944 netdev->features |= NETIF_F_NTUPLE; 1945 } 1946 } 1947 } 1948 1949 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1950 struct hns3_desc_cb *cb) 1951 { 1952 unsigned int order = hnae3_page_order(ring); 1953 struct page *p; 1954 1955 p = dev_alloc_pages(order); 1956 if (!p) 1957 return -ENOMEM; 1958 1959 cb->priv = p; 1960 cb->page_offset = 0; 1961 cb->reuse_flag = 0; 1962 cb->buf = page_address(p); 1963 cb->length = hnae3_page_size(ring); 1964 cb->type = DESC_TYPE_PAGE; 1965 1966 return 0; 1967 } 1968 1969 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1970 struct hns3_desc_cb *cb) 1971 { 1972 if (cb->type == DESC_TYPE_SKB) 1973 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1974 else if (!HNAE3_IS_TX_RING(ring)) 1975 put_page((struct page *)cb->priv); 1976 memset(cb, 0, sizeof(*cb)); 1977 } 1978 1979 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1980 { 1981 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1982 cb->length, ring_to_dma_dir(ring)); 1983 1984 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 1985 return -EIO; 1986 1987 return 0; 1988 } 1989 1990 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1991 struct hns3_desc_cb *cb) 1992 { 1993 if (cb->type == DESC_TYPE_SKB) 1994 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1995 ring_to_dma_dir(ring)); 1996 else if (cb->length) 1997 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1998 ring_to_dma_dir(ring)); 1999 } 2000 2001 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2002 { 2003 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2004 ring->desc[i].addr = 0; 2005 } 2006 2007 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2008 { 2009 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2010 2011 if (!ring->desc_cb[i].dma) 2012 return; 2013 2014 hns3_buffer_detach(ring, i); 2015 hns3_free_buffer(ring, cb); 2016 } 2017 2018 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2019 { 2020 int i; 2021 2022 for (i = 0; i < ring->desc_num; i++) 2023 hns3_free_buffer_detach(ring, i); 2024 } 2025 2026 /* free desc along with its attached buffer */ 2027 static void hns3_free_desc(struct hns3_enet_ring *ring) 2028 { 2029 int size = ring->desc_num * sizeof(ring->desc[0]); 2030 2031 hns3_free_buffers(ring); 2032 2033 if (ring->desc) { 2034 dma_free_coherent(ring_to_dev(ring), size, 2035 ring->desc, ring->desc_dma_addr); 2036 ring->desc = NULL; 2037 } 2038 } 2039 2040 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2041 { 2042 int size = ring->desc_num * sizeof(ring->desc[0]); 2043 2044 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 2045 &ring->desc_dma_addr, 2046 GFP_KERNEL); 2047 if (!ring->desc) 2048 return -ENOMEM; 2049 2050 return 0; 2051 } 2052 2053 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2054 struct hns3_desc_cb *cb) 2055 { 2056 int ret; 2057 2058 ret = hns3_alloc_buffer(ring, cb); 2059 if (ret) 2060 goto out; 2061 2062 ret = hns3_map_buffer(ring, cb); 2063 if (ret) 2064 goto out_with_buf; 2065 2066 return 0; 2067 2068 out_with_buf: 2069 hns3_free_buffer(ring, cb); 2070 out: 2071 return ret; 2072 } 2073 2074 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2075 { 2076 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2077 2078 if (ret) 2079 return ret; 2080 2081 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2082 2083 return 0; 2084 } 2085 2086 /* Allocate memory for raw pkg, and map with dma */ 2087 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2088 { 2089 int i, j, ret; 2090 2091 for (i = 0; i < ring->desc_num; i++) { 2092 ret = hns3_alloc_buffer_attach(ring, i); 2093 if (ret) 2094 goto out_buffer_fail; 2095 } 2096 2097 return 0; 2098 2099 out_buffer_fail: 2100 for (j = i - 1; j >= 0; j--) 2101 hns3_free_buffer_detach(ring, j); 2102 return ret; 2103 } 2104 2105 /* detach a in-used buffer and replace with a reserved one */ 2106 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2107 struct hns3_desc_cb *res_cb) 2108 { 2109 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2110 ring->desc_cb[i] = *res_cb; 2111 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2112 ring->desc[i].rx.bd_base_info = 0; 2113 } 2114 2115 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2116 { 2117 ring->desc_cb[i].reuse_flag = 0; 2118 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2119 + ring->desc_cb[i].page_offset); 2120 ring->desc[i].rx.bd_base_info = 0; 2121 } 2122 2123 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2124 int *pkts) 2125 { 2126 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2127 2128 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2129 (*bytes) += desc_cb->length; 2130 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2131 hns3_free_buffer_detach(ring, ring->next_to_clean); 2132 2133 ring_ptr_move_fw(ring, next_to_clean); 2134 } 2135 2136 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2137 { 2138 int u = ring->next_to_use; 2139 int c = ring->next_to_clean; 2140 2141 if (unlikely(h > ring->desc_num)) 2142 return 0; 2143 2144 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2145 } 2146 2147 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2148 { 2149 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2150 struct hns3_nic_priv *priv = netdev_priv(netdev); 2151 struct netdev_queue *dev_queue; 2152 int bytes, pkts; 2153 int head; 2154 2155 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2156 rmb(); /* Make sure head is ready before touch any data */ 2157 2158 if (is_ring_empty(ring) || head == ring->next_to_clean) 2159 return; /* no data to poll */ 2160 2161 if (unlikely(!is_valid_clean_head(ring, head))) { 2162 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2163 ring->next_to_use, ring->next_to_clean); 2164 2165 u64_stats_update_begin(&ring->syncp); 2166 ring->stats.io_err_cnt++; 2167 u64_stats_update_end(&ring->syncp); 2168 return; 2169 } 2170 2171 bytes = 0; 2172 pkts = 0; 2173 while (head != ring->next_to_clean) { 2174 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2175 /* Issue prefetch for next Tx descriptor */ 2176 prefetch(&ring->desc_cb[ring->next_to_clean]); 2177 } 2178 2179 ring->tqp_vector->tx_group.total_bytes += bytes; 2180 ring->tqp_vector->tx_group.total_packets += pkts; 2181 2182 u64_stats_update_begin(&ring->syncp); 2183 ring->stats.tx_bytes += bytes; 2184 ring->stats.tx_pkts += pkts; 2185 u64_stats_update_end(&ring->syncp); 2186 2187 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2188 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2189 2190 if (unlikely(pkts && netif_carrier_ok(netdev) && 2191 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2192 /* Make sure that anybody stopping the queue after this 2193 * sees the new next_to_clean. 2194 */ 2195 smp_mb(); 2196 if (netif_tx_queue_stopped(dev_queue) && 2197 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2198 netif_tx_wake_queue(dev_queue); 2199 ring->stats.restart_queue++; 2200 } 2201 } 2202 } 2203 2204 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2205 { 2206 int ntc = ring->next_to_clean; 2207 int ntu = ring->next_to_use; 2208 2209 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2210 } 2211 2212 static void 2213 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2214 { 2215 struct hns3_desc_cb *desc_cb; 2216 struct hns3_desc_cb res_cbs; 2217 int i, ret; 2218 2219 for (i = 0; i < cleand_count; i++) { 2220 desc_cb = &ring->desc_cb[ring->next_to_use]; 2221 if (desc_cb->reuse_flag) { 2222 u64_stats_update_begin(&ring->syncp); 2223 ring->stats.reuse_pg_cnt++; 2224 u64_stats_update_end(&ring->syncp); 2225 2226 hns3_reuse_buffer(ring, ring->next_to_use); 2227 } else { 2228 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2229 if (ret) { 2230 u64_stats_update_begin(&ring->syncp); 2231 ring->stats.sw_err_cnt++; 2232 u64_stats_update_end(&ring->syncp); 2233 2234 netdev_err(ring->tqp->handle->kinfo.netdev, 2235 "hnae reserve buffer map failed.\n"); 2236 break; 2237 } 2238 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2239 } 2240 2241 ring_ptr_move_fw(ring, next_to_use); 2242 } 2243 2244 wmb(); /* Make all data has been write before submit */ 2245 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2246 } 2247 2248 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2249 struct hns3_enet_ring *ring, int pull_len, 2250 struct hns3_desc_cb *desc_cb) 2251 { 2252 struct hns3_desc *desc; 2253 u32 truesize; 2254 int size; 2255 int last_offset; 2256 bool twobufs; 2257 2258 twobufs = ((PAGE_SIZE < 8192) && 2259 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2260 2261 desc = &ring->desc[ring->next_to_clean]; 2262 size = le16_to_cpu(desc->rx.size); 2263 2264 truesize = hnae3_buf_size(ring); 2265 2266 if (!twobufs) 2267 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2268 2269 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2270 size - pull_len, truesize); 2271 2272 /* Avoid re-using remote pages,flag default unreuse */ 2273 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2274 return; 2275 2276 if (twobufs) { 2277 /* If we are only owner of page we can reuse it */ 2278 if (likely(page_count(desc_cb->priv) == 1)) { 2279 /* Flip page offset to other buffer */ 2280 desc_cb->page_offset ^= truesize; 2281 2282 desc_cb->reuse_flag = 1; 2283 /* bump ref count on page before it is given*/ 2284 get_page(desc_cb->priv); 2285 } 2286 return; 2287 } 2288 2289 /* Move offset up to the next cache line */ 2290 desc_cb->page_offset += truesize; 2291 2292 if (desc_cb->page_offset <= last_offset) { 2293 desc_cb->reuse_flag = 1; 2294 /* Bump ref count on page before it is given*/ 2295 get_page(desc_cb->priv); 2296 } 2297 } 2298 2299 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2300 struct hns3_desc *desc) 2301 { 2302 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2303 int l3_type, l4_type; 2304 u32 bd_base_info; 2305 int ol4_type; 2306 u32 l234info; 2307 2308 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2309 l234info = le32_to_cpu(desc->rx.l234_info); 2310 2311 skb->ip_summed = CHECKSUM_NONE; 2312 2313 skb_checksum_none_assert(skb); 2314 2315 if (!(netdev->features & NETIF_F_RXCSUM)) 2316 return; 2317 2318 /* We MUST enable hardware checksum before enabling hardware GRO */ 2319 if (skb_shinfo(skb)->gso_size) { 2320 skb->ip_summed = CHECKSUM_UNNECESSARY; 2321 return; 2322 } 2323 2324 /* check if hardware has done checksum */ 2325 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2326 return; 2327 2328 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2329 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2330 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2331 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2332 u64_stats_update_begin(&ring->syncp); 2333 ring->stats.l3l4_csum_err++; 2334 u64_stats_update_end(&ring->syncp); 2335 2336 return; 2337 } 2338 2339 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2340 HNS3_RXD_L3ID_S); 2341 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2342 HNS3_RXD_L4ID_S); 2343 2344 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2345 HNS3_RXD_OL4ID_S); 2346 switch (ol4_type) { 2347 case HNS3_OL4_TYPE_MAC_IN_UDP: 2348 case HNS3_OL4_TYPE_NVGRE: 2349 skb->csum_level = 1; 2350 /* fall through */ 2351 case HNS3_OL4_TYPE_NO_TUN: 2352 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2353 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2354 l3_type == HNS3_L3_TYPE_IPV6) && 2355 (l4_type == HNS3_L4_TYPE_UDP || 2356 l4_type == HNS3_L4_TYPE_TCP || 2357 l4_type == HNS3_L4_TYPE_SCTP)) 2358 skb->ip_summed = CHECKSUM_UNNECESSARY; 2359 break; 2360 default: 2361 break; 2362 } 2363 } 2364 2365 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2366 { 2367 if (skb_has_frag_list(skb)) 2368 napi_gro_flush(&ring->tqp_vector->napi, false); 2369 2370 napi_gro_receive(&ring->tqp_vector->napi, skb); 2371 } 2372 2373 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2374 struct hns3_desc *desc, u32 l234info, 2375 u16 *vlan_tag) 2376 { 2377 struct pci_dev *pdev = ring->tqp->handle->pdev; 2378 2379 if (pdev->revision == 0x20) { 2380 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2381 if (!(*vlan_tag & VLAN_VID_MASK)) 2382 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2383 2384 return (*vlan_tag != 0); 2385 } 2386 2387 #define HNS3_STRP_OUTER_VLAN 0x1 2388 #define HNS3_STRP_INNER_VLAN 0x2 2389 2390 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2391 HNS3_RXD_STRP_TAGP_S)) { 2392 case HNS3_STRP_OUTER_VLAN: 2393 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2394 return true; 2395 case HNS3_STRP_INNER_VLAN: 2396 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2397 return true; 2398 default: 2399 return false; 2400 } 2401 } 2402 2403 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2404 unsigned char *va) 2405 { 2406 #define HNS3_NEED_ADD_FRAG 1 2407 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2408 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2409 struct sk_buff *skb; 2410 2411 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2412 skb = ring->skb; 2413 if (unlikely(!skb)) { 2414 netdev_err(netdev, "alloc rx skb fail\n"); 2415 2416 u64_stats_update_begin(&ring->syncp); 2417 ring->stats.sw_err_cnt++; 2418 u64_stats_update_end(&ring->syncp); 2419 2420 return -ENOMEM; 2421 } 2422 2423 prefetchw(skb->data); 2424 2425 ring->pending_buf = 1; 2426 ring->frag_num = 0; 2427 ring->tail_skb = NULL; 2428 if (length <= HNS3_RX_HEAD_SIZE) { 2429 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2430 2431 /* We can reuse buffer as-is, just make sure it is local */ 2432 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2433 desc_cb->reuse_flag = 1; 2434 else /* This page cannot be reused so discard it */ 2435 put_page(desc_cb->priv); 2436 2437 ring_ptr_move_fw(ring, next_to_clean); 2438 return 0; 2439 } 2440 u64_stats_update_begin(&ring->syncp); 2441 ring->stats.seg_pkt_cnt++; 2442 u64_stats_update_end(&ring->syncp); 2443 2444 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2445 __skb_put(skb, ring->pull_len); 2446 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2447 desc_cb); 2448 ring_ptr_move_fw(ring, next_to_clean); 2449 2450 return HNS3_NEED_ADD_FRAG; 2451 } 2452 2453 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2454 struct sk_buff **out_skb, bool pending) 2455 { 2456 struct sk_buff *skb = *out_skb; 2457 struct sk_buff *head_skb = *out_skb; 2458 struct sk_buff *new_skb; 2459 struct hns3_desc_cb *desc_cb; 2460 struct hns3_desc *pre_desc; 2461 u32 bd_base_info; 2462 int pre_bd; 2463 2464 /* if there is pending bd, the SW param next_to_clean has moved 2465 * to next and the next is NULL 2466 */ 2467 if (pending) { 2468 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2469 ring->desc_num; 2470 pre_desc = &ring->desc[pre_bd]; 2471 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2472 } else { 2473 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2474 } 2475 2476 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2477 desc = &ring->desc[ring->next_to_clean]; 2478 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2479 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2480 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)) 2481 return -ENXIO; 2482 2483 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2484 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2485 HNS3_RX_HEAD_SIZE); 2486 if (unlikely(!new_skb)) { 2487 netdev_err(ring->tqp->handle->kinfo.netdev, 2488 "alloc rx skb frag fail\n"); 2489 return -ENXIO; 2490 } 2491 ring->frag_num = 0; 2492 2493 if (ring->tail_skb) { 2494 ring->tail_skb->next = new_skb; 2495 ring->tail_skb = new_skb; 2496 } else { 2497 skb_shinfo(skb)->frag_list = new_skb; 2498 ring->tail_skb = new_skb; 2499 } 2500 } 2501 2502 if (ring->tail_skb) { 2503 head_skb->truesize += hnae3_buf_size(ring); 2504 head_skb->data_len += le16_to_cpu(desc->rx.size); 2505 head_skb->len += le16_to_cpu(desc->rx.size); 2506 skb = ring->tail_skb; 2507 } 2508 2509 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2510 ring_ptr_move_fw(ring, next_to_clean); 2511 ring->pending_buf++; 2512 } 2513 2514 return 0; 2515 } 2516 2517 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info, 2518 u32 bd_base_info) 2519 { 2520 u16 gro_count; 2521 u32 l3_type; 2522 2523 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2524 HNS3_RXD_GRO_COUNT_S); 2525 /* if there is no HW GRO, do not set gro params */ 2526 if (!gro_count) 2527 return; 2528 2529 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count 2530 * to skb_shinfo(skb)->gso_segs 2531 */ 2532 NAPI_GRO_CB(skb)->count = gro_count; 2533 2534 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2535 HNS3_RXD_L3ID_S); 2536 if (l3_type == HNS3_L3_TYPE_IPV4) 2537 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2538 else if (l3_type == HNS3_L3_TYPE_IPV6) 2539 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2540 else 2541 return; 2542 2543 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2544 HNS3_RXD_GRO_SIZE_M, 2545 HNS3_RXD_GRO_SIZE_S); 2546 if (skb_shinfo(skb)->gso_size) 2547 tcp_gro_complete(skb); 2548 } 2549 2550 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2551 struct sk_buff *skb) 2552 { 2553 struct hnae3_handle *handle = ring->tqp->handle; 2554 enum pkt_hash_types rss_type; 2555 struct hns3_desc *desc; 2556 int last_bd; 2557 2558 /* When driver handle the rss type, ring->next_to_clean indicates the 2559 * first descriptor of next packet, need -1 here. 2560 */ 2561 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num; 2562 desc = &ring->desc[last_bd]; 2563 2564 if (le32_to_cpu(desc->rx.rss_hash)) 2565 rss_type = handle->kinfo.rss_type; 2566 else 2567 rss_type = PKT_HASH_TYPE_NONE; 2568 2569 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2570 } 2571 2572 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2573 struct sk_buff **out_skb) 2574 { 2575 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2576 struct sk_buff *skb = ring->skb; 2577 struct hns3_desc_cb *desc_cb; 2578 struct hns3_desc *desc; 2579 u32 bd_base_info; 2580 u32 l234info; 2581 int length; 2582 int ret; 2583 2584 desc = &ring->desc[ring->next_to_clean]; 2585 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2586 2587 prefetch(desc); 2588 2589 length = le16_to_cpu(desc->rx.size); 2590 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2591 2592 /* Check valid BD */ 2593 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2594 return -ENXIO; 2595 2596 if (!skb) 2597 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2598 2599 /* Prefetch first cache line of first page 2600 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2601 * line size is 64B so need to prefetch twice to make it 128B. But in 2602 * actual we can have greater size of caches with 128B Level 1 cache 2603 * lines. In such a case, single fetch would suffice to cache in the 2604 * relevant part of the header. 2605 */ 2606 prefetch(ring->va); 2607 #if L1_CACHE_BYTES < 128 2608 prefetch(ring->va + L1_CACHE_BYTES); 2609 #endif 2610 2611 if (!skb) { 2612 ret = hns3_alloc_skb(ring, length, ring->va); 2613 *out_skb = skb = ring->skb; 2614 2615 if (ret < 0) /* alloc buffer fail */ 2616 return ret; 2617 if (ret > 0) { /* need add frag */ 2618 ret = hns3_add_frag(ring, desc, &skb, false); 2619 if (ret) 2620 return ret; 2621 2622 /* As the head data may be changed when GRO enable, copy 2623 * the head data in after other data rx completed 2624 */ 2625 memcpy(skb->data, ring->va, 2626 ALIGN(ring->pull_len, sizeof(long))); 2627 } 2628 } else { 2629 ret = hns3_add_frag(ring, desc, &skb, true); 2630 if (ret) 2631 return ret; 2632 2633 /* As the head data may be changed when GRO enable, copy 2634 * the head data in after other data rx completed 2635 */ 2636 memcpy(skb->data, ring->va, 2637 ALIGN(ring->pull_len, sizeof(long))); 2638 } 2639 2640 l234info = le32_to_cpu(desc->rx.l234_info); 2641 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2642 2643 /* Based on hw strategy, the tag offloaded will be stored at 2644 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2645 * in one layer tag case. 2646 */ 2647 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2648 u16 vlan_tag; 2649 2650 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2651 __vlan_hwaccel_put_tag(skb, 2652 htons(ETH_P_8021Q), 2653 vlan_tag); 2654 } 2655 2656 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2657 u64_stats_update_begin(&ring->syncp); 2658 ring->stats.non_vld_descs++; 2659 u64_stats_update_end(&ring->syncp); 2660 2661 dev_kfree_skb_any(skb); 2662 return -EINVAL; 2663 } 2664 2665 if (unlikely((!desc->rx.pkt_len) || 2666 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2667 u64_stats_update_begin(&ring->syncp); 2668 ring->stats.err_pkt_len++; 2669 u64_stats_update_end(&ring->syncp); 2670 2671 dev_kfree_skb_any(skb); 2672 return -EFAULT; 2673 } 2674 2675 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2676 u64_stats_update_begin(&ring->syncp); 2677 ring->stats.l2_err++; 2678 u64_stats_update_end(&ring->syncp); 2679 2680 dev_kfree_skb_any(skb); 2681 return -EFAULT; 2682 } 2683 2684 u64_stats_update_begin(&ring->syncp); 2685 ring->stats.rx_pkts++; 2686 ring->stats.rx_bytes += skb->len; 2687 u64_stats_update_end(&ring->syncp); 2688 2689 ring->tqp_vector->rx_group.total_bytes += skb->len; 2690 2691 /* This is needed in order to enable forwarding support */ 2692 hns3_set_gro_param(skb, l234info, bd_base_info); 2693 2694 hns3_rx_checksum(ring, skb, desc); 2695 *out_skb = skb; 2696 hns3_set_rx_skb_rss_type(ring, skb); 2697 2698 return 0; 2699 } 2700 2701 int hns3_clean_rx_ring( 2702 struct hns3_enet_ring *ring, int budget, 2703 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2704 { 2705 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2706 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2707 int recv_pkts, recv_bds, clean_count, err; 2708 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2709 struct sk_buff *skb = ring->skb; 2710 int num; 2711 2712 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2713 rmb(); /* Make sure num taken effect before the other data is touched */ 2714 2715 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2716 num -= unused_count; 2717 2718 while (recv_pkts < budget && recv_bds < num) { 2719 /* Reuse or realloc buffers */ 2720 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2721 hns3_nic_alloc_rx_buffers(ring, 2722 clean_count + unused_count); 2723 clean_count = 0; 2724 unused_count = hns3_desc_unused(ring) - 2725 ring->pending_buf; 2726 } 2727 2728 /* Poll one pkt */ 2729 err = hns3_handle_rx_bd(ring, &skb); 2730 if (unlikely(!skb)) /* This fault cannot be repaired */ 2731 goto out; 2732 2733 if (err == -ENXIO) { /* Do not get FE for the packet */ 2734 goto out; 2735 } else if (unlikely(err)) { /* Do jump the err */ 2736 recv_bds += ring->pending_buf; 2737 clean_count += ring->pending_buf; 2738 ring->skb = NULL; 2739 ring->pending_buf = 0; 2740 continue; 2741 } 2742 2743 /* Do update ip stack process */ 2744 skb->protocol = eth_type_trans(skb, netdev); 2745 rx_fn(ring, skb); 2746 recv_bds += ring->pending_buf; 2747 clean_count += ring->pending_buf; 2748 ring->skb = NULL; 2749 ring->pending_buf = 0; 2750 2751 recv_pkts++; 2752 } 2753 2754 out: 2755 /* Make all data has been write before submit */ 2756 if (clean_count + unused_count > 0) 2757 hns3_nic_alloc_rx_buffers(ring, 2758 clean_count + unused_count); 2759 2760 return recv_pkts; 2761 } 2762 2763 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2764 { 2765 struct hns3_enet_tqp_vector *tqp_vector = 2766 ring_group->ring->tqp_vector; 2767 enum hns3_flow_level_range new_flow_level; 2768 int packets_per_msecs; 2769 int bytes_per_msecs; 2770 u32 time_passed_ms; 2771 u16 new_int_gl; 2772 2773 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2774 return false; 2775 2776 if (ring_group->total_packets == 0) { 2777 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2778 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2779 return true; 2780 } 2781 2782 /* Simple throttlerate management 2783 * 0-10MB/s lower (50000 ints/s) 2784 * 10-20MB/s middle (20000 ints/s) 2785 * 20-1249MB/s high (18000 ints/s) 2786 * > 40000pps ultra (8000 ints/s) 2787 */ 2788 new_flow_level = ring_group->coal.flow_level; 2789 new_int_gl = ring_group->coal.int_gl; 2790 time_passed_ms = 2791 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2792 2793 if (!time_passed_ms) 2794 return false; 2795 2796 do_div(ring_group->total_packets, time_passed_ms); 2797 packets_per_msecs = ring_group->total_packets; 2798 2799 do_div(ring_group->total_bytes, time_passed_ms); 2800 bytes_per_msecs = ring_group->total_bytes; 2801 2802 #define HNS3_RX_LOW_BYTE_RATE 10000 2803 #define HNS3_RX_MID_BYTE_RATE 20000 2804 2805 switch (new_flow_level) { 2806 case HNS3_FLOW_LOW: 2807 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2808 new_flow_level = HNS3_FLOW_MID; 2809 break; 2810 case HNS3_FLOW_MID: 2811 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2812 new_flow_level = HNS3_FLOW_HIGH; 2813 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2814 new_flow_level = HNS3_FLOW_LOW; 2815 break; 2816 case HNS3_FLOW_HIGH: 2817 case HNS3_FLOW_ULTRA: 2818 default: 2819 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2820 new_flow_level = HNS3_FLOW_MID; 2821 break; 2822 } 2823 2824 #define HNS3_RX_ULTRA_PACKET_RATE 40 2825 2826 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2827 &tqp_vector->rx_group == ring_group) 2828 new_flow_level = HNS3_FLOW_ULTRA; 2829 2830 switch (new_flow_level) { 2831 case HNS3_FLOW_LOW: 2832 new_int_gl = HNS3_INT_GL_50K; 2833 break; 2834 case HNS3_FLOW_MID: 2835 new_int_gl = HNS3_INT_GL_20K; 2836 break; 2837 case HNS3_FLOW_HIGH: 2838 new_int_gl = HNS3_INT_GL_18K; 2839 break; 2840 case HNS3_FLOW_ULTRA: 2841 new_int_gl = HNS3_INT_GL_8K; 2842 break; 2843 default: 2844 break; 2845 } 2846 2847 ring_group->total_bytes = 0; 2848 ring_group->total_packets = 0; 2849 ring_group->coal.flow_level = new_flow_level; 2850 if (new_int_gl != ring_group->coal.int_gl) { 2851 ring_group->coal.int_gl = new_int_gl; 2852 return true; 2853 } 2854 return false; 2855 } 2856 2857 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2858 { 2859 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2860 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2861 bool rx_update, tx_update; 2862 2863 /* update param every 1000ms */ 2864 if (time_before(jiffies, 2865 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 2866 return; 2867 2868 if (rx_group->coal.gl_adapt_enable) { 2869 rx_update = hns3_get_new_int_gl(rx_group); 2870 if (rx_update) 2871 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2872 rx_group->coal.int_gl); 2873 } 2874 2875 if (tx_group->coal.gl_adapt_enable) { 2876 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2877 if (tx_update) 2878 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2879 tx_group->coal.int_gl); 2880 } 2881 2882 tqp_vector->last_jiffies = jiffies; 2883 } 2884 2885 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2886 { 2887 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2888 struct hns3_enet_ring *ring; 2889 int rx_pkt_total = 0; 2890 2891 struct hns3_enet_tqp_vector *tqp_vector = 2892 container_of(napi, struct hns3_enet_tqp_vector, napi); 2893 bool clean_complete = true; 2894 int rx_budget; 2895 2896 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2897 napi_complete(napi); 2898 return 0; 2899 } 2900 2901 /* Since the actual Tx work is minimal, we can give the Tx a larger 2902 * budget and be more aggressive about cleaning up the Tx descriptors. 2903 */ 2904 hns3_for_each_ring(ring, tqp_vector->tx_group) 2905 hns3_clean_tx_ring(ring); 2906 2907 /* make sure rx ring budget not smaller than 1 */ 2908 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2909 2910 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2911 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2912 hns3_rx_skb); 2913 2914 if (rx_cleaned >= rx_budget) 2915 clean_complete = false; 2916 2917 rx_pkt_total += rx_cleaned; 2918 } 2919 2920 tqp_vector->rx_group.total_packets += rx_pkt_total; 2921 2922 if (!clean_complete) 2923 return budget; 2924 2925 if (napi_complete(napi) && 2926 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2927 hns3_update_new_int_gl(tqp_vector); 2928 hns3_mask_vector_irq(tqp_vector, 1); 2929 } 2930 2931 return rx_pkt_total; 2932 } 2933 2934 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2935 struct hnae3_ring_chain_node *head) 2936 { 2937 struct pci_dev *pdev = tqp_vector->handle->pdev; 2938 struct hnae3_ring_chain_node *cur_chain = head; 2939 struct hnae3_ring_chain_node *chain; 2940 struct hns3_enet_ring *tx_ring; 2941 struct hns3_enet_ring *rx_ring; 2942 2943 tx_ring = tqp_vector->tx_group.ring; 2944 if (tx_ring) { 2945 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2946 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2947 HNAE3_RING_TYPE_TX); 2948 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2949 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2950 2951 cur_chain->next = NULL; 2952 2953 while (tx_ring->next) { 2954 tx_ring = tx_ring->next; 2955 2956 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2957 GFP_KERNEL); 2958 if (!chain) 2959 goto err_free_chain; 2960 2961 cur_chain->next = chain; 2962 chain->tqp_index = tx_ring->tqp->tqp_index; 2963 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2964 HNAE3_RING_TYPE_TX); 2965 hnae3_set_field(chain->int_gl_idx, 2966 HNAE3_RING_GL_IDX_M, 2967 HNAE3_RING_GL_IDX_S, 2968 HNAE3_RING_GL_TX); 2969 2970 cur_chain = chain; 2971 } 2972 } 2973 2974 rx_ring = tqp_vector->rx_group.ring; 2975 if (!tx_ring && rx_ring) { 2976 cur_chain->next = NULL; 2977 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2978 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2979 HNAE3_RING_TYPE_RX); 2980 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2981 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2982 2983 rx_ring = rx_ring->next; 2984 } 2985 2986 while (rx_ring) { 2987 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2988 if (!chain) 2989 goto err_free_chain; 2990 2991 cur_chain->next = chain; 2992 chain->tqp_index = rx_ring->tqp->tqp_index; 2993 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2994 HNAE3_RING_TYPE_RX); 2995 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2996 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2997 2998 cur_chain = chain; 2999 3000 rx_ring = rx_ring->next; 3001 } 3002 3003 return 0; 3004 3005 err_free_chain: 3006 cur_chain = head->next; 3007 while (cur_chain) { 3008 chain = cur_chain->next; 3009 devm_kfree(&pdev->dev, cur_chain); 3010 cur_chain = chain; 3011 } 3012 head->next = NULL; 3013 3014 return -ENOMEM; 3015 } 3016 3017 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3018 struct hnae3_ring_chain_node *head) 3019 { 3020 struct pci_dev *pdev = tqp_vector->handle->pdev; 3021 struct hnae3_ring_chain_node *chain_tmp, *chain; 3022 3023 chain = head->next; 3024 3025 while (chain) { 3026 chain_tmp = chain->next; 3027 devm_kfree(&pdev->dev, chain); 3028 chain = chain_tmp; 3029 } 3030 } 3031 3032 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3033 struct hns3_enet_ring *ring) 3034 { 3035 ring->next = group->ring; 3036 group->ring = ring; 3037 3038 group->count++; 3039 } 3040 3041 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3042 { 3043 struct pci_dev *pdev = priv->ae_handle->pdev; 3044 struct hns3_enet_tqp_vector *tqp_vector; 3045 int num_vectors = priv->vector_num; 3046 int numa_node; 3047 int vector_i; 3048 3049 numa_node = dev_to_node(&pdev->dev); 3050 3051 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3052 tqp_vector = &priv->tqp_vector[vector_i]; 3053 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3054 &tqp_vector->affinity_mask); 3055 } 3056 } 3057 3058 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3059 { 3060 struct hnae3_ring_chain_node vector_ring_chain; 3061 struct hnae3_handle *h = priv->ae_handle; 3062 struct hns3_enet_tqp_vector *tqp_vector; 3063 int ret = 0; 3064 int i; 3065 3066 hns3_nic_set_cpumask(priv); 3067 3068 for (i = 0; i < priv->vector_num; i++) { 3069 tqp_vector = &priv->tqp_vector[i]; 3070 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3071 tqp_vector->num_tqps = 0; 3072 } 3073 3074 for (i = 0; i < h->kinfo.num_tqps; i++) { 3075 u16 vector_i = i % priv->vector_num; 3076 u16 tqp_num = h->kinfo.num_tqps; 3077 3078 tqp_vector = &priv->tqp_vector[vector_i]; 3079 3080 hns3_add_ring_to_group(&tqp_vector->tx_group, 3081 priv->ring_data[i].ring); 3082 3083 hns3_add_ring_to_group(&tqp_vector->rx_group, 3084 priv->ring_data[i + tqp_num].ring); 3085 3086 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3087 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3088 tqp_vector->num_tqps++; 3089 } 3090 3091 for (i = 0; i < priv->vector_num; i++) { 3092 tqp_vector = &priv->tqp_vector[i]; 3093 3094 tqp_vector->rx_group.total_bytes = 0; 3095 tqp_vector->rx_group.total_packets = 0; 3096 tqp_vector->tx_group.total_bytes = 0; 3097 tqp_vector->tx_group.total_packets = 0; 3098 tqp_vector->handle = h; 3099 3100 ret = hns3_get_vector_ring_chain(tqp_vector, 3101 &vector_ring_chain); 3102 if (ret) 3103 goto map_ring_fail; 3104 3105 ret = h->ae_algo->ops->map_ring_to_vector(h, 3106 tqp_vector->vector_irq, &vector_ring_chain); 3107 3108 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3109 3110 if (ret) 3111 goto map_ring_fail; 3112 3113 netif_napi_add(priv->netdev, &tqp_vector->napi, 3114 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3115 } 3116 3117 return 0; 3118 3119 map_ring_fail: 3120 while (i--) 3121 netif_napi_del(&priv->tqp_vector[i].napi); 3122 3123 return ret; 3124 } 3125 3126 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3127 { 3128 #define HNS3_VECTOR_PF_MAX_NUM 64 3129 3130 struct hnae3_handle *h = priv->ae_handle; 3131 struct hns3_enet_tqp_vector *tqp_vector; 3132 struct hnae3_vector_info *vector; 3133 struct pci_dev *pdev = h->pdev; 3134 u16 tqp_num = h->kinfo.num_tqps; 3135 u16 vector_num; 3136 int ret = 0; 3137 u16 i; 3138 3139 /* RSS size, cpu online and vector_num should be the same */ 3140 /* Should consider 2p/4p later */ 3141 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3142 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3143 3144 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3145 GFP_KERNEL); 3146 if (!vector) 3147 return -ENOMEM; 3148 3149 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3150 3151 priv->vector_num = vector_num; 3152 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3153 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3154 GFP_KERNEL); 3155 if (!priv->tqp_vector) { 3156 ret = -ENOMEM; 3157 goto out; 3158 } 3159 3160 for (i = 0; i < priv->vector_num; i++) { 3161 tqp_vector = &priv->tqp_vector[i]; 3162 tqp_vector->idx = i; 3163 tqp_vector->mask_addr = vector[i].io_addr; 3164 tqp_vector->vector_irq = vector[i].vector; 3165 hns3_vector_gl_rl_init(tqp_vector, priv); 3166 } 3167 3168 out: 3169 devm_kfree(&pdev->dev, vector); 3170 return ret; 3171 } 3172 3173 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3174 { 3175 group->ring = NULL; 3176 group->count = 0; 3177 } 3178 3179 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3180 { 3181 struct hnae3_ring_chain_node vector_ring_chain; 3182 struct hnae3_handle *h = priv->ae_handle; 3183 struct hns3_enet_tqp_vector *tqp_vector; 3184 int i, ret; 3185 3186 for (i = 0; i < priv->vector_num; i++) { 3187 tqp_vector = &priv->tqp_vector[i]; 3188 3189 ret = hns3_get_vector_ring_chain(tqp_vector, 3190 &vector_ring_chain); 3191 if (ret) 3192 return ret; 3193 3194 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 3195 tqp_vector->vector_irq, &vector_ring_chain); 3196 if (ret) 3197 return ret; 3198 3199 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3200 3201 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3202 irq_set_affinity_notifier(tqp_vector->vector_irq, 3203 NULL); 3204 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3205 free_irq(tqp_vector->vector_irq, tqp_vector); 3206 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3207 } 3208 3209 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3210 hns3_clear_ring_group(&tqp_vector->rx_group); 3211 hns3_clear_ring_group(&tqp_vector->tx_group); 3212 netif_napi_del(&priv->tqp_vector[i].napi); 3213 } 3214 3215 return 0; 3216 } 3217 3218 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3219 { 3220 struct hnae3_handle *h = priv->ae_handle; 3221 struct pci_dev *pdev = h->pdev; 3222 int i, ret; 3223 3224 for (i = 0; i < priv->vector_num; i++) { 3225 struct hns3_enet_tqp_vector *tqp_vector; 3226 3227 tqp_vector = &priv->tqp_vector[i]; 3228 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3229 if (ret) 3230 return ret; 3231 } 3232 3233 devm_kfree(&pdev->dev, priv->tqp_vector); 3234 return 0; 3235 } 3236 3237 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3238 int ring_type) 3239 { 3240 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3241 int queue_num = priv->ae_handle->kinfo.num_tqps; 3242 struct pci_dev *pdev = priv->ae_handle->pdev; 3243 struct hns3_enet_ring *ring; 3244 3245 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3246 if (!ring) 3247 return -ENOMEM; 3248 3249 if (ring_type == HNAE3_RING_TYPE_TX) { 3250 ring_data[q->tqp_index].ring = ring; 3251 ring_data[q->tqp_index].queue_index = q->tqp_index; 3252 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3253 } else { 3254 ring_data[q->tqp_index + queue_num].ring = ring; 3255 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3256 ring->io_base = q->io_base; 3257 } 3258 3259 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3260 3261 ring->tqp = q; 3262 ring->desc = NULL; 3263 ring->desc_cb = NULL; 3264 ring->dev = priv->dev; 3265 ring->desc_dma_addr = 0; 3266 ring->buf_size = q->buf_size; 3267 ring->desc_num = q->desc_num; 3268 ring->next_to_use = 0; 3269 ring->next_to_clean = 0; 3270 3271 return 0; 3272 } 3273 3274 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3275 struct hns3_nic_priv *priv) 3276 { 3277 int ret; 3278 3279 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3280 if (ret) 3281 return ret; 3282 3283 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3284 if (ret) { 3285 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3286 return ret; 3287 } 3288 3289 return 0; 3290 } 3291 3292 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3293 { 3294 struct hnae3_handle *h = priv->ae_handle; 3295 struct pci_dev *pdev = h->pdev; 3296 int i, ret; 3297 3298 priv->ring_data = devm_kzalloc(&pdev->dev, 3299 array3_size(h->kinfo.num_tqps, 3300 sizeof(*priv->ring_data), 3301 2), 3302 GFP_KERNEL); 3303 if (!priv->ring_data) 3304 return -ENOMEM; 3305 3306 for (i = 0; i < h->kinfo.num_tqps; i++) { 3307 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3308 if (ret) 3309 goto err; 3310 } 3311 3312 return 0; 3313 err: 3314 while (i--) { 3315 devm_kfree(priv->dev, priv->ring_data[i].ring); 3316 devm_kfree(priv->dev, 3317 priv->ring_data[i + h->kinfo.num_tqps].ring); 3318 } 3319 3320 devm_kfree(&pdev->dev, priv->ring_data); 3321 return ret; 3322 } 3323 3324 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3325 { 3326 struct hnae3_handle *h = priv->ae_handle; 3327 int i; 3328 3329 for (i = 0; i < h->kinfo.num_tqps; i++) { 3330 devm_kfree(priv->dev, priv->ring_data[i].ring); 3331 devm_kfree(priv->dev, 3332 priv->ring_data[i + h->kinfo.num_tqps].ring); 3333 } 3334 devm_kfree(priv->dev, priv->ring_data); 3335 } 3336 3337 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3338 { 3339 int ret; 3340 3341 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3342 return -EINVAL; 3343 3344 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3345 GFP_KERNEL); 3346 if (!ring->desc_cb) { 3347 ret = -ENOMEM; 3348 goto out; 3349 } 3350 3351 ret = hns3_alloc_desc(ring); 3352 if (ret) 3353 goto out_with_desc_cb; 3354 3355 if (!HNAE3_IS_TX_RING(ring)) { 3356 ret = hns3_alloc_ring_buffers(ring); 3357 if (ret) 3358 goto out_with_desc; 3359 } 3360 3361 return 0; 3362 3363 out_with_desc: 3364 hns3_free_desc(ring); 3365 out_with_desc_cb: 3366 kfree(ring->desc_cb); 3367 ring->desc_cb = NULL; 3368 out: 3369 return ret; 3370 } 3371 3372 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3373 { 3374 hns3_free_desc(ring); 3375 kfree(ring->desc_cb); 3376 ring->desc_cb = NULL; 3377 ring->next_to_clean = 0; 3378 ring->next_to_use = 0; 3379 } 3380 3381 static int hns3_buf_size2type(u32 buf_size) 3382 { 3383 int bd_size_type; 3384 3385 switch (buf_size) { 3386 case 512: 3387 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3388 break; 3389 case 1024: 3390 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3391 break; 3392 case 2048: 3393 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3394 break; 3395 case 4096: 3396 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3397 break; 3398 default: 3399 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3400 } 3401 3402 return bd_size_type; 3403 } 3404 3405 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3406 { 3407 dma_addr_t dma = ring->desc_dma_addr; 3408 struct hnae3_queue *q = ring->tqp; 3409 3410 if (!HNAE3_IS_TX_RING(ring)) { 3411 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3412 (u32)dma); 3413 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3414 (u32)((dma >> 31) >> 1)); 3415 3416 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3417 hns3_buf_size2type(ring->buf_size)); 3418 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3419 ring->desc_num / 8 - 1); 3420 3421 } else { 3422 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3423 (u32)dma); 3424 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3425 (u32)((dma >> 31) >> 1)); 3426 3427 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3428 ring->desc_num / 8 - 1); 3429 } 3430 } 3431 3432 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3433 { 3434 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3435 int i; 3436 3437 for (i = 0; i < HNAE3_MAX_TC; i++) { 3438 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3439 int j; 3440 3441 if (!tc_info->enable) 3442 continue; 3443 3444 for (j = 0; j < tc_info->tqp_count; j++) { 3445 struct hnae3_queue *q; 3446 3447 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3448 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3449 tc_info->tc); 3450 } 3451 } 3452 } 3453 3454 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3455 { 3456 struct hnae3_handle *h = priv->ae_handle; 3457 int ring_num = h->kinfo.num_tqps * 2; 3458 int i, j; 3459 int ret; 3460 3461 for (i = 0; i < ring_num; i++) { 3462 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3463 if (ret) { 3464 dev_err(priv->dev, 3465 "Alloc ring memory fail! ret=%d\n", ret); 3466 goto out_when_alloc_ring_memory; 3467 } 3468 3469 u64_stats_init(&priv->ring_data[i].ring->syncp); 3470 } 3471 3472 return 0; 3473 3474 out_when_alloc_ring_memory: 3475 for (j = i - 1; j >= 0; j--) 3476 hns3_fini_ring(priv->ring_data[j].ring); 3477 3478 return -ENOMEM; 3479 } 3480 3481 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3482 { 3483 struct hnae3_handle *h = priv->ae_handle; 3484 int i; 3485 3486 for (i = 0; i < h->kinfo.num_tqps; i++) { 3487 hns3_fini_ring(priv->ring_data[i].ring); 3488 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3489 } 3490 return 0; 3491 } 3492 3493 /* Set mac addr if it is configured. or leave it to the AE driver */ 3494 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3495 { 3496 struct hns3_nic_priv *priv = netdev_priv(netdev); 3497 struct hnae3_handle *h = priv->ae_handle; 3498 u8 mac_addr_temp[ETH_ALEN]; 3499 int ret = 0; 3500 3501 if (h->ae_algo->ops->get_mac_addr && init) { 3502 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3503 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3504 } 3505 3506 /* Check if the MAC address is valid, if not get a random one */ 3507 if (!is_valid_ether_addr(netdev->dev_addr)) { 3508 eth_hw_addr_random(netdev); 3509 dev_warn(priv->dev, "using random MAC address %pM\n", 3510 netdev->dev_addr); 3511 } 3512 3513 if (h->ae_algo->ops->set_mac_addr) 3514 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3515 3516 return ret; 3517 } 3518 3519 static int hns3_restore_fd_rules(struct net_device *netdev) 3520 { 3521 struct hnae3_handle *h = hns3_get_handle(netdev); 3522 int ret = 0; 3523 3524 if (h->ae_algo->ops->restore_fd_rules) 3525 ret = h->ae_algo->ops->restore_fd_rules(h); 3526 3527 return ret; 3528 } 3529 3530 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3531 { 3532 struct hnae3_handle *h = hns3_get_handle(netdev); 3533 3534 if (h->ae_algo->ops->del_all_fd_entries) 3535 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3536 } 3537 3538 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3539 { 3540 struct hns3_nic_priv *priv = netdev_priv(netdev); 3541 3542 priv->ops.fill_desc = hns3_fill_desc; 3543 if ((netdev->features & NETIF_F_TSO) || 3544 (netdev->features & NETIF_F_TSO6)) 3545 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3546 else 3547 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3548 } 3549 3550 static int hns3_client_start(struct hnae3_handle *handle) 3551 { 3552 if (!handle->ae_algo->ops->client_start) 3553 return 0; 3554 3555 return handle->ae_algo->ops->client_start(handle); 3556 } 3557 3558 static void hns3_client_stop(struct hnae3_handle *handle) 3559 { 3560 if (!handle->ae_algo->ops->client_stop) 3561 return; 3562 3563 handle->ae_algo->ops->client_stop(handle); 3564 } 3565 3566 static int hns3_client_init(struct hnae3_handle *handle) 3567 { 3568 struct pci_dev *pdev = handle->pdev; 3569 u16 alloc_tqps, max_rss_size; 3570 struct hns3_nic_priv *priv; 3571 struct net_device *netdev; 3572 int ret; 3573 3574 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3575 &max_rss_size); 3576 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3577 if (!netdev) 3578 return -ENOMEM; 3579 3580 priv = netdev_priv(netdev); 3581 priv->dev = &pdev->dev; 3582 priv->netdev = netdev; 3583 priv->ae_handle = handle; 3584 priv->tx_timeout_count = 0; 3585 3586 handle->kinfo.netdev = netdev; 3587 handle->priv = (void *)priv; 3588 3589 hns3_init_mac_addr(netdev, true); 3590 3591 hns3_set_default_feature(netdev); 3592 3593 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3594 netdev->priv_flags |= IFF_UNICAST_FLT; 3595 netdev->netdev_ops = &hns3_nic_netdev_ops; 3596 SET_NETDEV_DEV(netdev, &pdev->dev); 3597 hns3_ethtool_set_ops(netdev); 3598 hns3_nic_set_priv_ops(netdev); 3599 3600 /* Carrier off reporting is important to ethtool even BEFORE open */ 3601 netif_carrier_off(netdev); 3602 3603 ret = hns3_get_ring_config(priv); 3604 if (ret) { 3605 ret = -ENOMEM; 3606 goto out_get_ring_cfg; 3607 } 3608 3609 ret = hns3_nic_alloc_vector_data(priv); 3610 if (ret) { 3611 ret = -ENOMEM; 3612 goto out_alloc_vector_data; 3613 } 3614 3615 ret = hns3_nic_init_vector_data(priv); 3616 if (ret) { 3617 ret = -ENOMEM; 3618 goto out_init_vector_data; 3619 } 3620 3621 ret = hns3_init_all_ring(priv); 3622 if (ret) { 3623 ret = -ENOMEM; 3624 goto out_init_ring_data; 3625 } 3626 3627 ret = register_netdev(netdev); 3628 if (ret) { 3629 dev_err(priv->dev, "probe register netdev fail!\n"); 3630 goto out_reg_netdev_fail; 3631 } 3632 3633 ret = hns3_client_start(handle); 3634 if (ret) { 3635 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3636 goto out_reg_netdev_fail; 3637 } 3638 3639 hns3_dcbnl_setup(handle); 3640 3641 hns3_dbg_init(handle); 3642 3643 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3644 netdev->max_mtu = HNS3_MAX_MTU; 3645 3646 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3647 3648 return ret; 3649 3650 out_reg_netdev_fail: 3651 out_init_ring_data: 3652 (void)hns3_nic_uninit_vector_data(priv); 3653 out_init_vector_data: 3654 hns3_nic_dealloc_vector_data(priv); 3655 out_alloc_vector_data: 3656 priv->ring_data = NULL; 3657 out_get_ring_cfg: 3658 priv->ae_handle = NULL; 3659 free_netdev(netdev); 3660 return ret; 3661 } 3662 3663 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3664 { 3665 struct net_device *netdev = handle->kinfo.netdev; 3666 struct hns3_nic_priv *priv = netdev_priv(netdev); 3667 int ret; 3668 3669 hns3_client_stop(handle); 3670 3671 hns3_remove_hw_addr(netdev); 3672 3673 if (netdev->reg_state != NETREG_UNINITIALIZED) 3674 unregister_netdev(netdev); 3675 3676 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3677 netdev_warn(netdev, "already uninitialized\n"); 3678 goto out_netdev_free; 3679 } 3680 3681 hns3_del_all_fd_rules(netdev, true); 3682 3683 hns3_force_clear_all_rx_ring(handle); 3684 3685 ret = hns3_nic_uninit_vector_data(priv); 3686 if (ret) 3687 netdev_err(netdev, "uninit vector error\n"); 3688 3689 ret = hns3_nic_dealloc_vector_data(priv); 3690 if (ret) 3691 netdev_err(netdev, "dealloc vector error\n"); 3692 3693 ret = hns3_uninit_all_ring(priv); 3694 if (ret) 3695 netdev_err(netdev, "uninit ring error\n"); 3696 3697 hns3_put_ring_config(priv); 3698 3699 hns3_dbg_uninit(handle); 3700 3701 priv->ring_data = NULL; 3702 3703 out_netdev_free: 3704 free_netdev(netdev); 3705 } 3706 3707 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3708 { 3709 struct net_device *netdev = handle->kinfo.netdev; 3710 3711 if (!netdev) 3712 return; 3713 3714 if (linkup) { 3715 netif_carrier_on(netdev); 3716 netif_tx_wake_all_queues(netdev); 3717 netdev_info(netdev, "link up\n"); 3718 } else { 3719 netif_carrier_off(netdev); 3720 netif_tx_stop_all_queues(netdev); 3721 netdev_info(netdev, "link down\n"); 3722 } 3723 } 3724 3725 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3726 { 3727 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3728 struct net_device *ndev = kinfo->netdev; 3729 bool if_running; 3730 int ret; 3731 3732 if (tc > HNAE3_MAX_TC) 3733 return -EINVAL; 3734 3735 if (!ndev) 3736 return -ENODEV; 3737 3738 if_running = netif_running(ndev); 3739 3740 if (if_running) { 3741 (void)hns3_nic_net_stop(ndev); 3742 msleep(100); 3743 } 3744 3745 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3746 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3747 if (ret) 3748 goto err_out; 3749 3750 ret = hns3_nic_set_real_num_queue(ndev); 3751 3752 err_out: 3753 if (if_running) 3754 (void)hns3_nic_net_open(ndev); 3755 3756 return ret; 3757 } 3758 3759 static int hns3_recover_hw_addr(struct net_device *ndev) 3760 { 3761 struct netdev_hw_addr_list *list; 3762 struct netdev_hw_addr *ha, *tmp; 3763 int ret = 0; 3764 3765 /* go through and sync uc_addr entries to the device */ 3766 list = &ndev->uc; 3767 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3768 ret = hns3_nic_uc_sync(ndev, ha->addr); 3769 if (ret) 3770 return ret; 3771 } 3772 3773 /* go through and sync mc_addr entries to the device */ 3774 list = &ndev->mc; 3775 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3776 ret = hns3_nic_mc_sync(ndev, ha->addr); 3777 if (ret) 3778 return ret; 3779 } 3780 3781 return ret; 3782 } 3783 3784 static void hns3_remove_hw_addr(struct net_device *netdev) 3785 { 3786 struct netdev_hw_addr_list *list; 3787 struct netdev_hw_addr *ha, *tmp; 3788 3789 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3790 3791 /* go through and unsync uc_addr entries to the device */ 3792 list = &netdev->uc; 3793 list_for_each_entry_safe(ha, tmp, &list->list, list) 3794 hns3_nic_uc_unsync(netdev, ha->addr); 3795 3796 /* go through and unsync mc_addr entries to the device */ 3797 list = &netdev->mc; 3798 list_for_each_entry_safe(ha, tmp, &list->list, list) 3799 if (ha->refcount > 1) 3800 hns3_nic_mc_unsync(netdev, ha->addr); 3801 } 3802 3803 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3804 { 3805 while (ring->next_to_clean != ring->next_to_use) { 3806 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3807 hns3_free_buffer_detach(ring, ring->next_to_clean); 3808 ring_ptr_move_fw(ring, next_to_clean); 3809 } 3810 } 3811 3812 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3813 { 3814 struct hns3_desc_cb res_cbs; 3815 int ret; 3816 3817 while (ring->next_to_use != ring->next_to_clean) { 3818 /* When a buffer is not reused, it's memory has been 3819 * freed in hns3_handle_rx_bd or will be freed by 3820 * stack, so we need to replace the buffer here. 3821 */ 3822 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3823 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3824 if (ret) { 3825 u64_stats_update_begin(&ring->syncp); 3826 ring->stats.sw_err_cnt++; 3827 u64_stats_update_end(&ring->syncp); 3828 /* if alloc new buffer fail, exit directly 3829 * and reclear in up flow. 3830 */ 3831 netdev_warn(ring->tqp->handle->kinfo.netdev, 3832 "reserve buffer map failed, ret = %d\n", 3833 ret); 3834 return ret; 3835 } 3836 hns3_replace_buffer(ring, ring->next_to_use, 3837 &res_cbs); 3838 } 3839 ring_ptr_move_fw(ring, next_to_use); 3840 } 3841 3842 return 0; 3843 } 3844 3845 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3846 { 3847 while (ring->next_to_use != ring->next_to_clean) { 3848 /* When a buffer is not reused, it's memory has been 3849 * freed in hns3_handle_rx_bd or will be freed by 3850 * stack, so only need to unmap the buffer here. 3851 */ 3852 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3853 hns3_unmap_buffer(ring, 3854 &ring->desc_cb[ring->next_to_use]); 3855 ring->desc_cb[ring->next_to_use].dma = 0; 3856 } 3857 3858 ring_ptr_move_fw(ring, next_to_use); 3859 } 3860 } 3861 3862 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3863 { 3864 struct net_device *ndev = h->kinfo.netdev; 3865 struct hns3_nic_priv *priv = netdev_priv(ndev); 3866 struct hns3_enet_ring *ring; 3867 u32 i; 3868 3869 for (i = 0; i < h->kinfo.num_tqps; i++) { 3870 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3871 hns3_force_clear_rx_ring(ring); 3872 } 3873 } 3874 3875 static void hns3_clear_all_ring(struct hnae3_handle *h) 3876 { 3877 struct net_device *ndev = h->kinfo.netdev; 3878 struct hns3_nic_priv *priv = netdev_priv(ndev); 3879 u32 i; 3880 3881 for (i = 0; i < h->kinfo.num_tqps; i++) { 3882 struct netdev_queue *dev_queue; 3883 struct hns3_enet_ring *ring; 3884 3885 ring = priv->ring_data[i].ring; 3886 hns3_clear_tx_ring(ring); 3887 dev_queue = netdev_get_tx_queue(ndev, 3888 priv->ring_data[i].queue_index); 3889 netdev_tx_reset_queue(dev_queue); 3890 3891 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3892 /* Continue to clear other rings even if clearing some 3893 * rings failed. 3894 */ 3895 hns3_clear_rx_ring(ring); 3896 } 3897 } 3898 3899 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3900 { 3901 struct net_device *ndev = h->kinfo.netdev; 3902 struct hns3_nic_priv *priv = netdev_priv(ndev); 3903 struct hns3_enet_ring *rx_ring; 3904 int i, j; 3905 int ret; 3906 3907 for (i = 0; i < h->kinfo.num_tqps; i++) { 3908 ret = h->ae_algo->ops->reset_queue(h, i); 3909 if (ret) 3910 return ret; 3911 3912 hns3_init_ring_hw(priv->ring_data[i].ring); 3913 3914 /* We need to clear tx ring here because self test will 3915 * use the ring and will not run down before up 3916 */ 3917 hns3_clear_tx_ring(priv->ring_data[i].ring); 3918 priv->ring_data[i].ring->next_to_clean = 0; 3919 priv->ring_data[i].ring->next_to_use = 0; 3920 3921 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3922 hns3_init_ring_hw(rx_ring); 3923 ret = hns3_clear_rx_ring(rx_ring); 3924 if (ret) 3925 return ret; 3926 3927 /* We can not know the hardware head and tail when this 3928 * function is called in reset flow, so we reuse all desc. 3929 */ 3930 for (j = 0; j < rx_ring->desc_num; j++) 3931 hns3_reuse_buffer(rx_ring, j); 3932 3933 rx_ring->next_to_clean = 0; 3934 rx_ring->next_to_use = 0; 3935 } 3936 3937 hns3_init_tx_ring_tc(priv); 3938 3939 return 0; 3940 } 3941 3942 static void hns3_store_coal(struct hns3_nic_priv *priv) 3943 { 3944 /* ethtool only support setting and querying one coal 3945 * configuation for now, so save the vector 0' coal 3946 * configuation here in order to restore it. 3947 */ 3948 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 3949 sizeof(struct hns3_enet_coalesce)); 3950 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 3951 sizeof(struct hns3_enet_coalesce)); 3952 } 3953 3954 static void hns3_restore_coal(struct hns3_nic_priv *priv) 3955 { 3956 u16 vector_num = priv->vector_num; 3957 int i; 3958 3959 for (i = 0; i < vector_num; i++) { 3960 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 3961 sizeof(struct hns3_enet_coalesce)); 3962 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 3963 sizeof(struct hns3_enet_coalesce)); 3964 } 3965 } 3966 3967 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3968 { 3969 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 3970 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3971 struct net_device *ndev = kinfo->netdev; 3972 struct hns3_nic_priv *priv = netdev_priv(ndev); 3973 3974 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 3975 return 0; 3976 3977 /* it is cumbersome for hardware to pick-and-choose entries for deletion 3978 * from table space. Hence, for function reset software intervention is 3979 * required to delete the entries 3980 */ 3981 if (hns3_dev_ongoing_func_reset(ae_dev)) { 3982 hns3_remove_hw_addr(ndev); 3983 hns3_del_all_fd_rules(ndev, false); 3984 } 3985 3986 if (!netif_running(ndev)) 3987 return 0; 3988 3989 return hns3_nic_net_stop(ndev); 3990 } 3991 3992 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3993 { 3994 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3995 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 3996 int ret = 0; 3997 3998 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 3999 4000 if (netif_running(kinfo->netdev)) { 4001 ret = hns3_nic_net_open(kinfo->netdev); 4002 if (ret) { 4003 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4004 netdev_err(kinfo->netdev, 4005 "hns net up fail, ret=%d!\n", ret); 4006 return ret; 4007 } 4008 } 4009 4010 return ret; 4011 } 4012 4013 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4014 { 4015 struct net_device *netdev = handle->kinfo.netdev; 4016 struct hns3_nic_priv *priv = netdev_priv(netdev); 4017 bool vlan_filter_enable; 4018 int ret; 4019 4020 ret = hns3_init_mac_addr(netdev, false); 4021 if (ret) 4022 return ret; 4023 4024 ret = hns3_recover_hw_addr(netdev); 4025 if (ret) 4026 return ret; 4027 4028 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4029 if (ret) 4030 return ret; 4031 4032 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4033 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4034 4035 /* Hardware table is only clear when pf resets */ 4036 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4037 ret = hns3_restore_vlan(netdev); 4038 if (ret) 4039 return ret; 4040 } 4041 4042 ret = hns3_restore_fd_rules(netdev); 4043 if (ret) 4044 return ret; 4045 4046 /* Carrier off reporting is important to ethtool even BEFORE open */ 4047 netif_carrier_off(netdev); 4048 4049 ret = hns3_nic_alloc_vector_data(priv); 4050 if (ret) 4051 return ret; 4052 4053 hns3_restore_coal(priv); 4054 4055 ret = hns3_nic_init_vector_data(priv); 4056 if (ret) 4057 goto err_dealloc_vector; 4058 4059 ret = hns3_init_all_ring(priv); 4060 if (ret) 4061 goto err_uninit_vector; 4062 4063 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4064 4065 return ret; 4066 4067 err_uninit_vector: 4068 hns3_nic_uninit_vector_data(priv); 4069 priv->ring_data = NULL; 4070 err_dealloc_vector: 4071 hns3_nic_dealloc_vector_data(priv); 4072 4073 return ret; 4074 } 4075 4076 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4077 { 4078 struct net_device *netdev = handle->kinfo.netdev; 4079 struct hns3_nic_priv *priv = netdev_priv(netdev); 4080 int ret; 4081 4082 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4083 netdev_warn(netdev, "already uninitialized\n"); 4084 return 0; 4085 } 4086 4087 hns3_force_clear_all_rx_ring(handle); 4088 4089 ret = hns3_nic_uninit_vector_data(priv); 4090 if (ret) { 4091 netdev_err(netdev, "uninit vector error\n"); 4092 return ret; 4093 } 4094 4095 hns3_store_coal(priv); 4096 4097 ret = hns3_nic_dealloc_vector_data(priv); 4098 if (ret) 4099 netdev_err(netdev, "dealloc vector error\n"); 4100 4101 ret = hns3_uninit_all_ring(priv); 4102 if (ret) 4103 netdev_err(netdev, "uninit ring error\n"); 4104 4105 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 4106 4107 return ret; 4108 } 4109 4110 static int hns3_reset_notify(struct hnae3_handle *handle, 4111 enum hnae3_reset_notify_type type) 4112 { 4113 int ret = 0; 4114 4115 switch (type) { 4116 case HNAE3_UP_CLIENT: 4117 ret = hns3_reset_notify_up_enet(handle); 4118 break; 4119 case HNAE3_DOWN_CLIENT: 4120 ret = hns3_reset_notify_down_enet(handle); 4121 break; 4122 case HNAE3_INIT_CLIENT: 4123 ret = hns3_reset_notify_init_enet(handle); 4124 break; 4125 case HNAE3_UNINIT_CLIENT: 4126 ret = hns3_reset_notify_uninit_enet(handle); 4127 break; 4128 default: 4129 break; 4130 } 4131 4132 return ret; 4133 } 4134 4135 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num) 4136 { 4137 struct hns3_nic_priv *priv = netdev_priv(netdev); 4138 struct hnae3_handle *h = hns3_get_handle(netdev); 4139 int ret; 4140 4141 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 4142 if (ret) 4143 return ret; 4144 4145 ret = hns3_get_ring_config(priv); 4146 if (ret) 4147 return ret; 4148 4149 ret = hns3_nic_alloc_vector_data(priv); 4150 if (ret) 4151 goto err_alloc_vector; 4152 4153 hns3_restore_coal(priv); 4154 4155 ret = hns3_nic_init_vector_data(priv); 4156 if (ret) 4157 goto err_uninit_vector; 4158 4159 ret = hns3_init_all_ring(priv); 4160 if (ret) 4161 goto err_put_ring; 4162 4163 return 0; 4164 4165 err_put_ring: 4166 hns3_put_ring_config(priv); 4167 err_uninit_vector: 4168 hns3_nic_uninit_vector_data(priv); 4169 err_alloc_vector: 4170 hns3_nic_dealloc_vector_data(priv); 4171 return ret; 4172 } 4173 4174 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 4175 { 4176 return (new_tqp_num / num_tc) * num_tc; 4177 } 4178 4179 int hns3_set_channels(struct net_device *netdev, 4180 struct ethtool_channels *ch) 4181 { 4182 struct hns3_nic_priv *priv = netdev_priv(netdev); 4183 struct hnae3_handle *h = hns3_get_handle(netdev); 4184 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4185 bool if_running = netif_running(netdev); 4186 u32 new_tqp_num = ch->combined_count; 4187 u16 org_tqp_num; 4188 int ret; 4189 4190 if (ch->rx_count || ch->tx_count) 4191 return -EINVAL; 4192 4193 if (new_tqp_num > hns3_get_max_available_channels(h) || 4194 new_tqp_num < kinfo->num_tc) { 4195 dev_err(&netdev->dev, 4196 "Change tqps fail, the tqp range is from %d to %d", 4197 kinfo->num_tc, 4198 hns3_get_max_available_channels(h)); 4199 return -EINVAL; 4200 } 4201 4202 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 4203 if (kinfo->num_tqps == new_tqp_num) 4204 return 0; 4205 4206 if (if_running) 4207 hns3_nic_net_stop(netdev); 4208 4209 ret = hns3_nic_uninit_vector_data(priv); 4210 if (ret) { 4211 dev_err(&netdev->dev, 4212 "Unbind vector with tqp fail, nothing is changed"); 4213 goto open_netdev; 4214 } 4215 4216 hns3_store_coal(priv); 4217 4218 hns3_nic_dealloc_vector_data(priv); 4219 4220 hns3_uninit_all_ring(priv); 4221 hns3_put_ring_config(priv); 4222 4223 org_tqp_num = h->kinfo.num_tqps; 4224 ret = hns3_modify_tqp_num(netdev, new_tqp_num); 4225 if (ret) { 4226 ret = hns3_modify_tqp_num(netdev, org_tqp_num); 4227 if (ret) { 4228 /* If revert to old tqp failed, fatal error occurred */ 4229 dev_err(&netdev->dev, 4230 "Revert to old tqp num fail, ret=%d", ret); 4231 return ret; 4232 } 4233 dev_info(&netdev->dev, 4234 "Change tqp num fail, Revert to old tqp num"); 4235 } 4236 4237 open_netdev: 4238 if (if_running) 4239 hns3_nic_net_open(netdev); 4240 4241 return ret; 4242 } 4243 4244 static const struct hnae3_client_ops client_ops = { 4245 .init_instance = hns3_client_init, 4246 .uninit_instance = hns3_client_uninit, 4247 .link_status_change = hns3_link_status_change, 4248 .setup_tc = hns3_client_setup_tc, 4249 .reset_notify = hns3_reset_notify, 4250 }; 4251 4252 /* hns3_init_module - Driver registration routine 4253 * hns3_init_module is the first routine called when the driver is 4254 * loaded. All it does is register with the PCI subsystem. 4255 */ 4256 static int __init hns3_init_module(void) 4257 { 4258 int ret; 4259 4260 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4261 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4262 4263 client.type = HNAE3_CLIENT_KNIC; 4264 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4265 hns3_driver_name); 4266 4267 client.ops = &client_ops; 4268 4269 INIT_LIST_HEAD(&client.node); 4270 4271 hns3_dbg_register_debugfs(hns3_driver_name); 4272 4273 ret = hnae3_register_client(&client); 4274 if (ret) 4275 goto err_reg_client; 4276 4277 ret = pci_register_driver(&hns3_driver); 4278 if (ret) 4279 goto err_reg_driver; 4280 4281 return ret; 4282 4283 err_reg_driver: 4284 hnae3_unregister_client(&client); 4285 err_reg_client: 4286 hns3_dbg_unregister_debugfs(); 4287 return ret; 4288 } 4289 module_init(hns3_init_module); 4290 4291 /* hns3_exit_module - Driver exit cleanup routine 4292 * hns3_exit_module is called just before the driver is removed 4293 * from memory. 4294 */ 4295 static void __exit hns3_exit_module(void) 4296 { 4297 pci_unregister_driver(&hns3_driver); 4298 hnae3_unregister_client(&client); 4299 hns3_dbg_unregister_debugfs(); 4300 } 4301 module_exit(hns3_exit_module); 4302 4303 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4304 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4305 MODULE_LICENSE("GPL"); 4306 MODULE_ALIAS("pci:hns-nic"); 4307 MODULE_VERSION(HNS3_MOD_VERSION); 4308