1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 7 #include "hnae3.h" 8 #include "hns3_debugfs.h" 9 #include "hns3_enet.h" 10 11 static struct dentry *hns3_dbgfs_root; 12 13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 14 { 15 .name = "tm" 16 }, 17 { 18 .name = "tx_bd_info" 19 }, 20 { 21 .name = "rx_bd_info" 22 }, 23 { 24 .name = "mac_list" 25 }, 26 { 27 .name = "reg" 28 }, 29 { 30 .name = "queue" 31 }, 32 { 33 .name = "fd" 34 }, 35 /* keep common at the bottom and add new directory above */ 36 { 37 .name = "common" 38 }, 39 }; 40 41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd); 42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, 43 unsigned int cmd); 44 45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 46 { 47 .name = "tm_nodes", 48 .cmd = HNAE3_DBG_CMD_TM_NODES, 49 .dentry = HNS3_DBG_DENTRY_TM, 50 .buf_len = HNS3_DBG_READ_LEN, 51 .init = hns3_dbg_common_file_init, 52 }, 53 { 54 .name = "tm_priority", 55 .cmd = HNAE3_DBG_CMD_TM_PRI, 56 .dentry = HNS3_DBG_DENTRY_TM, 57 .buf_len = HNS3_DBG_READ_LEN, 58 .init = hns3_dbg_common_file_init, 59 }, 60 { 61 .name = "tm_qset", 62 .cmd = HNAE3_DBG_CMD_TM_QSET, 63 .dentry = HNS3_DBG_DENTRY_TM, 64 .buf_len = HNS3_DBG_READ_LEN, 65 .init = hns3_dbg_common_file_init, 66 }, 67 { 68 .name = "tm_map", 69 .cmd = HNAE3_DBG_CMD_TM_MAP, 70 .dentry = HNS3_DBG_DENTRY_TM, 71 .buf_len = HNS3_DBG_READ_LEN_1MB, 72 .init = hns3_dbg_common_file_init, 73 }, 74 { 75 .name = "tm_pg", 76 .cmd = HNAE3_DBG_CMD_TM_PG, 77 .dentry = HNS3_DBG_DENTRY_TM, 78 .buf_len = HNS3_DBG_READ_LEN, 79 .init = hns3_dbg_common_file_init, 80 }, 81 { 82 .name = "tm_port", 83 .cmd = HNAE3_DBG_CMD_TM_PORT, 84 .dentry = HNS3_DBG_DENTRY_TM, 85 .buf_len = HNS3_DBG_READ_LEN, 86 .init = hns3_dbg_common_file_init, 87 }, 88 { 89 .name = "tc_sch_info", 90 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 91 .dentry = HNS3_DBG_DENTRY_TM, 92 .buf_len = HNS3_DBG_READ_LEN, 93 .init = hns3_dbg_common_file_init, 94 }, 95 { 96 .name = "qos_pause_cfg", 97 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 98 .dentry = HNS3_DBG_DENTRY_TM, 99 .buf_len = HNS3_DBG_READ_LEN, 100 .init = hns3_dbg_common_file_init, 101 }, 102 { 103 .name = "qos_pri_map", 104 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 105 .dentry = HNS3_DBG_DENTRY_TM, 106 .buf_len = HNS3_DBG_READ_LEN, 107 .init = hns3_dbg_common_file_init, 108 }, 109 { 110 .name = "qos_buf_cfg", 111 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 112 .dentry = HNS3_DBG_DENTRY_TM, 113 .buf_len = HNS3_DBG_READ_LEN, 114 .init = hns3_dbg_common_file_init, 115 }, 116 { 117 .name = "dev_info", 118 .cmd = HNAE3_DBG_CMD_DEV_INFO, 119 .dentry = HNS3_DBG_DENTRY_COMMON, 120 .buf_len = HNS3_DBG_READ_LEN, 121 .init = hns3_dbg_common_file_init, 122 }, 123 { 124 .name = "tx_bd_queue", 125 .cmd = HNAE3_DBG_CMD_TX_BD, 126 .dentry = HNS3_DBG_DENTRY_TX_BD, 127 .buf_len = HNS3_DBG_READ_LEN_4MB, 128 .init = hns3_dbg_bd_file_init, 129 }, 130 { 131 .name = "rx_bd_queue", 132 .cmd = HNAE3_DBG_CMD_RX_BD, 133 .dentry = HNS3_DBG_DENTRY_RX_BD, 134 .buf_len = HNS3_DBG_READ_LEN_4MB, 135 .init = hns3_dbg_bd_file_init, 136 }, 137 { 138 .name = "uc", 139 .cmd = HNAE3_DBG_CMD_MAC_UC, 140 .dentry = HNS3_DBG_DENTRY_MAC, 141 .buf_len = HNS3_DBG_READ_LEN, 142 .init = hns3_dbg_common_file_init, 143 }, 144 { 145 .name = "mc", 146 .cmd = HNAE3_DBG_CMD_MAC_MC, 147 .dentry = HNS3_DBG_DENTRY_MAC, 148 .buf_len = HNS3_DBG_READ_LEN, 149 .init = hns3_dbg_common_file_init, 150 }, 151 { 152 .name = "mng_tbl", 153 .cmd = HNAE3_DBG_CMD_MNG_TBL, 154 .dentry = HNS3_DBG_DENTRY_COMMON, 155 .buf_len = HNS3_DBG_READ_LEN, 156 .init = hns3_dbg_common_file_init, 157 }, 158 { 159 .name = "loopback", 160 .cmd = HNAE3_DBG_CMD_LOOPBACK, 161 .dentry = HNS3_DBG_DENTRY_COMMON, 162 .buf_len = HNS3_DBG_READ_LEN, 163 .init = hns3_dbg_common_file_init, 164 }, 165 { 166 .name = "interrupt_info", 167 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 168 .dentry = HNS3_DBG_DENTRY_COMMON, 169 .buf_len = HNS3_DBG_READ_LEN, 170 .init = hns3_dbg_common_file_init, 171 }, 172 { 173 .name = "reset_info", 174 .cmd = HNAE3_DBG_CMD_RESET_INFO, 175 .dentry = HNS3_DBG_DENTRY_COMMON, 176 .buf_len = HNS3_DBG_READ_LEN, 177 .init = hns3_dbg_common_file_init, 178 }, 179 { 180 .name = "imp_info", 181 .cmd = HNAE3_DBG_CMD_IMP_INFO, 182 .dentry = HNS3_DBG_DENTRY_COMMON, 183 .buf_len = HNS3_DBG_READ_LEN, 184 .init = hns3_dbg_common_file_init, 185 }, 186 { 187 .name = "ncl_config", 188 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 189 .dentry = HNS3_DBG_DENTRY_COMMON, 190 .buf_len = HNS3_DBG_READ_LEN_128KB, 191 .init = hns3_dbg_common_file_init, 192 }, 193 { 194 .name = "mac_tnl_status", 195 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 196 .dentry = HNS3_DBG_DENTRY_COMMON, 197 .buf_len = HNS3_DBG_READ_LEN, 198 .init = hns3_dbg_common_file_init, 199 }, 200 { 201 .name = "bios_common", 202 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 203 .dentry = HNS3_DBG_DENTRY_REG, 204 .buf_len = HNS3_DBG_READ_LEN, 205 .init = hns3_dbg_common_file_init, 206 }, 207 { 208 .name = "ssu", 209 .cmd = HNAE3_DBG_CMD_REG_SSU, 210 .dentry = HNS3_DBG_DENTRY_REG, 211 .buf_len = HNS3_DBG_READ_LEN, 212 .init = hns3_dbg_common_file_init, 213 }, 214 { 215 .name = "igu_egu", 216 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 217 .dentry = HNS3_DBG_DENTRY_REG, 218 .buf_len = HNS3_DBG_READ_LEN, 219 .init = hns3_dbg_common_file_init, 220 }, 221 { 222 .name = "rpu", 223 .cmd = HNAE3_DBG_CMD_REG_RPU, 224 .dentry = HNS3_DBG_DENTRY_REG, 225 .buf_len = HNS3_DBG_READ_LEN, 226 .init = hns3_dbg_common_file_init, 227 }, 228 { 229 .name = "ncsi", 230 .cmd = HNAE3_DBG_CMD_REG_NCSI, 231 .dentry = HNS3_DBG_DENTRY_REG, 232 .buf_len = HNS3_DBG_READ_LEN, 233 .init = hns3_dbg_common_file_init, 234 }, 235 { 236 .name = "rtc", 237 .cmd = HNAE3_DBG_CMD_REG_RTC, 238 .dentry = HNS3_DBG_DENTRY_REG, 239 .buf_len = HNS3_DBG_READ_LEN, 240 .init = hns3_dbg_common_file_init, 241 }, 242 { 243 .name = "ppp", 244 .cmd = HNAE3_DBG_CMD_REG_PPP, 245 .dentry = HNS3_DBG_DENTRY_REG, 246 .buf_len = HNS3_DBG_READ_LEN, 247 .init = hns3_dbg_common_file_init, 248 }, 249 { 250 .name = "rcb", 251 .cmd = HNAE3_DBG_CMD_REG_RCB, 252 .dentry = HNS3_DBG_DENTRY_REG, 253 .buf_len = HNS3_DBG_READ_LEN, 254 .init = hns3_dbg_common_file_init, 255 }, 256 { 257 .name = "tqp", 258 .cmd = HNAE3_DBG_CMD_REG_TQP, 259 .dentry = HNS3_DBG_DENTRY_REG, 260 .buf_len = HNS3_DBG_READ_LEN, 261 .init = hns3_dbg_common_file_init, 262 }, 263 { 264 .name = "mac", 265 .cmd = HNAE3_DBG_CMD_REG_MAC, 266 .dentry = HNS3_DBG_DENTRY_REG, 267 .buf_len = HNS3_DBG_READ_LEN, 268 .init = hns3_dbg_common_file_init, 269 }, 270 { 271 .name = "dcb", 272 .cmd = HNAE3_DBG_CMD_REG_DCB, 273 .dentry = HNS3_DBG_DENTRY_REG, 274 .buf_len = HNS3_DBG_READ_LEN, 275 .init = hns3_dbg_common_file_init, 276 }, 277 { 278 .name = "queue_map", 279 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 280 .dentry = HNS3_DBG_DENTRY_QUEUE, 281 .buf_len = HNS3_DBG_READ_LEN, 282 .init = hns3_dbg_common_file_init, 283 }, 284 { 285 .name = "rx_queue_info", 286 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 287 .dentry = HNS3_DBG_DENTRY_QUEUE, 288 .buf_len = HNS3_DBG_READ_LEN_1MB, 289 .init = hns3_dbg_common_file_init, 290 }, 291 { 292 .name = "tx_queue_info", 293 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 294 .dentry = HNS3_DBG_DENTRY_QUEUE, 295 .buf_len = HNS3_DBG_READ_LEN_1MB, 296 .init = hns3_dbg_common_file_init, 297 }, 298 { 299 .name = "fd_tcam", 300 .cmd = HNAE3_DBG_CMD_FD_TCAM, 301 .dentry = HNS3_DBG_DENTRY_FD, 302 .buf_len = HNS3_DBG_READ_LEN, 303 .init = hns3_dbg_common_file_init, 304 }, 305 { 306 .name = "service_task_info", 307 .cmd = HNAE3_DBG_CMD_SERV_INFO, 308 .dentry = HNS3_DBG_DENTRY_COMMON, 309 .buf_len = HNS3_DBG_READ_LEN, 310 .init = hns3_dbg_common_file_init, 311 }, 312 { 313 .name = "vlan_config", 314 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 315 .dentry = HNS3_DBG_DENTRY_COMMON, 316 .buf_len = HNS3_DBG_READ_LEN, 317 .init = hns3_dbg_common_file_init, 318 }, 319 { 320 .name = "ptp_info", 321 .cmd = HNAE3_DBG_CMD_PTP_INFO, 322 .dentry = HNS3_DBG_DENTRY_COMMON, 323 .buf_len = HNS3_DBG_READ_LEN, 324 .init = hns3_dbg_common_file_init, 325 }, 326 }; 327 328 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 329 { 330 .name = "support FD", 331 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 332 }, { 333 .name = "support GRO", 334 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 335 }, { 336 .name = "support FEC", 337 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 338 }, { 339 .name = "support UDP GSO", 340 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 341 }, { 342 .name = "support PTP", 343 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 344 }, { 345 .name = "support INT QL", 346 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 347 }, { 348 .name = "support HW TX csum", 349 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 350 }, { 351 .name = "support UDP tunnel csum", 352 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 353 }, { 354 .name = "support TX push", 355 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 356 }, { 357 .name = "support imp-controlled PHY", 358 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 359 }, { 360 .name = "support imp-controlled RAS", 361 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B, 362 }, { 363 .name = "support rxd advanced layout", 364 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 365 }, { 366 .name = "support port vlan bypass", 367 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 368 }, { 369 .name = "support modify vlan filter state", 370 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 371 } 372 }; 373 374 static void hns3_dbg_fill_content(char *content, u16 len, 375 const struct hns3_dbg_item *items, 376 const char **result, u16 size) 377 { 378 char *pos = content; 379 u16 i; 380 381 memset(content, ' ', len); 382 for (i = 0; i < size; i++) { 383 if (result) 384 strncpy(pos, result[i], strlen(result[i])); 385 else 386 strncpy(pos, items[i].name, strlen(items[i].name)); 387 388 pos += strlen(items[i].name) + items[i].interval; 389 } 390 391 *pos++ = '\n'; 392 *pos++ = '\0'; 393 } 394 395 static const struct hns3_dbg_item tx_spare_info_items[] = { 396 { "QUEUE_ID", 2 }, 397 { "COPYBREAK", 2 }, 398 { "LEN", 7 }, 399 { "NTU", 4 }, 400 { "NTC", 4 }, 401 { "LTC", 4 }, 402 { "DMA", 17 }, 403 }; 404 405 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf, 406 int len, u32 ring_num, int *pos) 407 { 408 char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN]; 409 struct hns3_tx_spare *tx_spare = ring->tx_spare; 410 char *result[ARRAY_SIZE(tx_spare_info_items)]; 411 char content[HNS3_DBG_INFO_LEN]; 412 u32 i, j; 413 414 if (!tx_spare) { 415 *pos += scnprintf(buf + *pos, len - *pos, 416 "tx spare buffer is not enabled\n"); 417 return; 418 } 419 420 for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++) 421 result[i] = &data_str[i][0]; 422 423 *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n"); 424 hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items, 425 NULL, ARRAY_SIZE(tx_spare_info_items)); 426 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 427 428 for (i = 0; i < ring_num; i++) { 429 j = 0; 430 sprintf(result[j++], "%8u", i); 431 sprintf(result[j++], "%9u", ring->tx_copybreak); 432 sprintf(result[j++], "%3u", tx_spare->len); 433 sprintf(result[j++], "%3u", tx_spare->next_to_use); 434 sprintf(result[j++], "%3u", tx_spare->next_to_clean); 435 sprintf(result[j++], "%3u", tx_spare->last_to_clean); 436 sprintf(result[j++], "%pad", &tx_spare->dma); 437 hns3_dbg_fill_content(content, sizeof(content), 438 tx_spare_info_items, 439 (const char **)result, 440 ARRAY_SIZE(tx_spare_info_items)); 441 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 442 } 443 } 444 445 static const struct hns3_dbg_item rx_queue_info_items[] = { 446 { "QUEUE_ID", 2 }, 447 { "BD_NUM", 2 }, 448 { "BD_LEN", 2 }, 449 { "TAIL", 2 }, 450 { "HEAD", 2 }, 451 { "FBDNUM", 2 }, 452 { "PKTNUM", 2 }, 453 { "COPYBREAK", 2 }, 454 { "RING_EN", 2 }, 455 { "RX_RING_EN", 2 }, 456 { "BASE_ADDR", 10 }, 457 }; 458 459 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 460 struct hnae3_ae_dev *ae_dev, char **result, 461 u32 index) 462 { 463 u32 base_add_l, base_add_h; 464 u32 j = 0; 465 466 sprintf(result[j++], "%8u", index); 467 468 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 469 HNS3_RING_RX_RING_BD_NUM_REG)); 470 471 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 472 HNS3_RING_RX_RING_BD_LEN_REG)); 473 474 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 475 HNS3_RING_RX_RING_TAIL_REG)); 476 477 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 478 HNS3_RING_RX_RING_HEAD_REG)); 479 480 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 481 HNS3_RING_RX_RING_FBDNUM_REG)); 482 483 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 484 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 485 sprintf(result[j++], "%9u", ring->rx_copybreak); 486 487 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 488 HNS3_RING_EN_REG) ? "on" : "off"); 489 490 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 491 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 492 HNS3_RING_RX_EN_REG) ? "on" : "off"); 493 else 494 sprintf(result[j++], "%10s", "NA"); 495 496 base_add_h = readl_relaxed(ring->tqp->io_base + 497 HNS3_RING_RX_RING_BASEADDR_H_REG); 498 base_add_l = readl_relaxed(ring->tqp->io_base + 499 HNS3_RING_RX_RING_BASEADDR_L_REG); 500 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 501 } 502 503 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 504 char *buf, int len) 505 { 506 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 507 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 508 char *result[ARRAY_SIZE(rx_queue_info_items)]; 509 struct hns3_nic_priv *priv = h->priv; 510 char content[HNS3_DBG_INFO_LEN]; 511 struct hns3_enet_ring *ring; 512 int pos = 0; 513 u32 i; 514 515 if (!priv->ring) { 516 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 517 return -EFAULT; 518 } 519 520 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 521 result[i] = &data_str[i][0]; 522 523 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 524 NULL, ARRAY_SIZE(rx_queue_info_items)); 525 pos += scnprintf(buf + pos, len - pos, "%s", content); 526 for (i = 0; i < h->kinfo.num_tqps; i++) { 527 /* Each cycle needs to determine whether the instance is reset, 528 * to prevent reference to invalid memory. And need to ensure 529 * that the following code is executed within 100ms. 530 */ 531 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 532 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 533 return -EPERM; 534 535 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 536 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 537 hns3_dbg_fill_content(content, sizeof(content), 538 rx_queue_info_items, 539 (const char **)result, 540 ARRAY_SIZE(rx_queue_info_items)); 541 pos += scnprintf(buf + pos, len - pos, "%s", content); 542 } 543 544 return 0; 545 } 546 547 static const struct hns3_dbg_item tx_queue_info_items[] = { 548 { "QUEUE_ID", 2 }, 549 { "BD_NUM", 2 }, 550 { "TC", 2 }, 551 { "TAIL", 2 }, 552 { "HEAD", 2 }, 553 { "FBDNUM", 2 }, 554 { "OFFSET", 2 }, 555 { "PKTNUM", 2 }, 556 { "RING_EN", 2 }, 557 { "TX_RING_EN", 2 }, 558 { "BASE_ADDR", 10 }, 559 }; 560 561 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 562 struct hnae3_ae_dev *ae_dev, char **result, 563 u32 index) 564 { 565 u32 base_add_l, base_add_h; 566 u32 j = 0; 567 568 sprintf(result[j++], "%8u", index); 569 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 570 HNS3_RING_TX_RING_BD_NUM_REG)); 571 572 sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base + 573 HNS3_RING_TX_RING_TC_REG)); 574 575 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 576 HNS3_RING_TX_RING_TAIL_REG)); 577 578 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 579 HNS3_RING_TX_RING_HEAD_REG)); 580 581 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 582 HNS3_RING_TX_RING_FBDNUM_REG)); 583 584 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 585 HNS3_RING_TX_RING_OFFSET_REG)); 586 587 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 588 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 589 590 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 591 HNS3_RING_EN_REG) ? "on" : "off"); 592 593 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 594 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 595 HNS3_RING_TX_EN_REG) ? "on" : "off"); 596 else 597 sprintf(result[j++], "%10s", "NA"); 598 599 base_add_h = readl_relaxed(ring->tqp->io_base + 600 HNS3_RING_TX_RING_BASEADDR_H_REG); 601 base_add_l = readl_relaxed(ring->tqp->io_base + 602 HNS3_RING_TX_RING_BASEADDR_L_REG); 603 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 604 } 605 606 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 607 char *buf, int len) 608 { 609 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 610 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 611 char *result[ARRAY_SIZE(tx_queue_info_items)]; 612 struct hns3_nic_priv *priv = h->priv; 613 char content[HNS3_DBG_INFO_LEN]; 614 struct hns3_enet_ring *ring; 615 int pos = 0; 616 u32 i; 617 618 if (!priv->ring) { 619 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 620 return -EFAULT; 621 } 622 623 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 624 result[i] = &data_str[i][0]; 625 626 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 627 NULL, ARRAY_SIZE(tx_queue_info_items)); 628 pos += scnprintf(buf + pos, len - pos, "%s", content); 629 630 for (i = 0; i < h->kinfo.num_tqps; i++) { 631 /* Each cycle needs to determine whether the instance is reset, 632 * to prevent reference to invalid memory. And need to ensure 633 * that the following code is executed within 100ms. 634 */ 635 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 636 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 637 return -EPERM; 638 639 ring = &priv->ring[i]; 640 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 641 hns3_dbg_fill_content(content, sizeof(content), 642 tx_queue_info_items, 643 (const char **)result, 644 ARRAY_SIZE(tx_queue_info_items)); 645 pos += scnprintf(buf + pos, len - pos, "%s", content); 646 } 647 648 hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos); 649 650 return 0; 651 } 652 653 static const struct hns3_dbg_item queue_map_items[] = { 654 { "local_queue_id", 2 }, 655 { "global_queue_id", 2 }, 656 { "vector_id", 2 }, 657 }; 658 659 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 660 { 661 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 662 char *result[ARRAY_SIZE(queue_map_items)]; 663 struct hns3_nic_priv *priv = h->priv; 664 char content[HNS3_DBG_INFO_LEN]; 665 int pos = 0; 666 int j; 667 u32 i; 668 669 if (!h->ae_algo->ops->get_global_queue_id) 670 return -EOPNOTSUPP; 671 672 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 673 result[i] = &data_str[i][0]; 674 675 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 676 NULL, ARRAY_SIZE(queue_map_items)); 677 pos += scnprintf(buf + pos, len - pos, "%s", content); 678 for (i = 0; i < h->kinfo.num_tqps; i++) { 679 if (!priv->ring || !priv->ring[i].tqp_vector) 680 continue; 681 j = 0; 682 sprintf(result[j++], "%u", i); 683 sprintf(result[j++], "%u", 684 h->ae_algo->ops->get_global_queue_id(h, i)); 685 sprintf(result[j++], "%u", 686 priv->ring[i].tqp_vector->vector_irq); 687 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 688 (const char **)result, 689 ARRAY_SIZE(queue_map_items)); 690 pos += scnprintf(buf + pos, len - pos, "%s", content); 691 } 692 693 return 0; 694 } 695 696 static const struct hns3_dbg_item rx_bd_info_items[] = { 697 { "BD_IDX", 3 }, 698 { "L234_INFO", 2 }, 699 { "PKT_LEN", 3 }, 700 { "SIZE", 4 }, 701 { "RSS_HASH", 4 }, 702 { "FD_ID", 2 }, 703 { "VLAN_TAG", 2 }, 704 { "O_DM_VLAN_ID_FB", 2 }, 705 { "OT_VLAN_TAG", 2 }, 706 { "BD_BASE_INFO", 2 }, 707 { "PTYPE", 2 }, 708 { "HW_CSUM", 2 }, 709 }; 710 711 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 712 struct hns3_desc *desc, char **result, int idx) 713 { 714 unsigned int j = 0; 715 716 sprintf(result[j++], "%5d", idx); 717 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 718 sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len)); 719 sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size)); 720 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 721 sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id)); 722 sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag)); 723 sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 724 sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag)); 725 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 726 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 727 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 728 729 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 730 HNS3_RXD_PTYPE_M, 731 HNS3_RXD_PTYPE_S)); 732 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 733 } else { 734 sprintf(result[j++], "NA"); 735 sprintf(result[j++], "NA"); 736 } 737 } 738 739 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 740 { 741 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 742 struct hns3_nic_priv *priv = d->handle->priv; 743 char *result[ARRAY_SIZE(rx_bd_info_items)]; 744 char content[HNS3_DBG_INFO_LEN]; 745 struct hns3_enet_ring *ring; 746 struct hns3_desc *desc; 747 unsigned int i; 748 int pos = 0; 749 750 if (d->qid >= d->handle->kinfo.num_tqps) { 751 dev_err(&d->handle->pdev->dev, 752 "queue%u is not in use\n", d->qid); 753 return -EINVAL; 754 } 755 756 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 757 result[i] = &data_str[i][0]; 758 759 pos += scnprintf(buf + pos, len - pos, 760 "Queue %u rx bd info:\n", d->qid); 761 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 762 NULL, ARRAY_SIZE(rx_bd_info_items)); 763 pos += scnprintf(buf + pos, len - pos, "%s", content); 764 765 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 766 for (i = 0; i < ring->desc_num; i++) { 767 desc = &ring->desc[i]; 768 769 hns3_dump_rx_bd_info(priv, desc, result, i); 770 hns3_dbg_fill_content(content, sizeof(content), 771 rx_bd_info_items, (const char **)result, 772 ARRAY_SIZE(rx_bd_info_items)); 773 pos += scnprintf(buf + pos, len - pos, "%s", content); 774 } 775 776 return 0; 777 } 778 779 static const struct hns3_dbg_item tx_bd_info_items[] = { 780 { "BD_IDX", 5 }, 781 { "ADDRESS", 2 }, 782 { "VLAN_TAG", 2 }, 783 { "SIZE", 2 }, 784 { "T_CS_VLAN_TSO", 2 }, 785 { "OT_VLAN_TAG", 3 }, 786 { "TV", 2 }, 787 { "OLT_VLAN_LEN", 2}, 788 { "PAYLEN_OL4CS", 2}, 789 { "BD_FE_SC_VLD", 2}, 790 { "MSS_HW_CSUM", 0}, 791 }; 792 793 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, 794 struct hns3_desc *desc, char **result, int idx) 795 { 796 unsigned int j = 0; 797 798 sprintf(result[j++], "%6d", idx); 799 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 800 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag)); 801 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size)); 802 sprintf(result[j++], "%#x", 803 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 804 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag)); 805 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv)); 806 sprintf(result[j++], "%10u", 807 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 808 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 809 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 810 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum)); 811 } 812 813 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 814 { 815 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 816 struct hns3_nic_priv *priv = d->handle->priv; 817 char *result[ARRAY_SIZE(tx_bd_info_items)]; 818 char content[HNS3_DBG_INFO_LEN]; 819 struct hns3_enet_ring *ring; 820 struct hns3_desc *desc; 821 unsigned int i; 822 int pos = 0; 823 824 if (d->qid >= d->handle->kinfo.num_tqps) { 825 dev_err(&d->handle->pdev->dev, 826 "queue%u is not in use\n", d->qid); 827 return -EINVAL; 828 } 829 830 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 831 result[i] = &data_str[i][0]; 832 833 pos += scnprintf(buf + pos, len - pos, 834 "Queue %u tx bd info:\n", d->qid); 835 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 836 NULL, ARRAY_SIZE(tx_bd_info_items)); 837 pos += scnprintf(buf + pos, len - pos, "%s", content); 838 839 ring = &priv->ring[d->qid]; 840 for (i = 0; i < ring->desc_num; i++) { 841 desc = &ring->desc[i]; 842 843 hns3_dump_tx_bd_info(priv, desc, result, i); 844 hns3_dbg_fill_content(content, sizeof(content), 845 tx_bd_info_items, (const char **)result, 846 ARRAY_SIZE(tx_bd_info_items)); 847 pos += scnprintf(buf + pos, len - pos, "%s", content); 848 } 849 850 return 0; 851 } 852 853 static void 854 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 855 { 856 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 857 static const char * const str[] = {"no", "yes"}; 858 unsigned long *caps = ae_dev->caps; 859 u32 i, state; 860 861 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 862 863 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 864 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 865 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 866 hns3_dbg_cap[i].name, str[state]); 867 } 868 869 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 870 } 871 872 static void 873 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 874 { 875 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 876 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 877 struct hnae3_knic_private_info *kinfo = &h->kinfo; 878 879 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 880 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 881 dev_specs->mac_entry_num); 882 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 883 dev_specs->mng_entry_num); 884 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 885 dev_specs->max_non_tso_bd_num); 886 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 887 dev_specs->rss_ind_tbl_size); 888 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 889 dev_specs->rss_key_size); 890 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 891 kinfo->rss_size); 892 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 893 kinfo->req_rss_size); 894 *pos += scnprintf(buf + *pos, len - *pos, 895 "Task queue pairs numbers: %u\n", 896 kinfo->num_tqps); 897 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 898 kinfo->rx_buf_len); 899 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 900 kinfo->num_tx_desc); 901 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 902 kinfo->num_rx_desc); 903 *pos += scnprintf(buf + *pos, len - *pos, 904 "Total number of enabled TCs: %u\n", 905 kinfo->tc_info.num_tc); 906 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 907 dev_specs->int_ql_max); 908 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 909 dev_specs->max_int_gl); 910 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 911 dev_specs->max_tm_rate); 912 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 913 dev_specs->max_qset_num); 914 } 915 916 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 917 { 918 int pos = 0; 919 920 hns3_dbg_dev_caps(h, buf, len, &pos); 921 922 hns3_dbg_dev_specs(h, buf, len, &pos); 923 924 return 0; 925 } 926 927 static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle, 928 const unsigned char *name, u32 *index) 929 { 930 u32 i; 931 932 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 933 if (!strncmp(name, hns3_dbg_cmd[i].name, 934 strlen(hns3_dbg_cmd[i].name))) { 935 *index = i; 936 return 0; 937 } 938 } 939 940 dev_err(&handle->pdev->dev, "unknown command(%s)\n", name); 941 return -EINVAL; 942 } 943 944 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 945 { 946 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 947 .dbg_dump = hns3_dbg_queue_map, 948 }, 949 { 950 .cmd = HNAE3_DBG_CMD_DEV_INFO, 951 .dbg_dump = hns3_dbg_dev_info, 952 }, 953 { 954 .cmd = HNAE3_DBG_CMD_TX_BD, 955 .dbg_dump_bd = hns3_dbg_tx_bd_info, 956 }, 957 { 958 .cmd = HNAE3_DBG_CMD_RX_BD, 959 .dbg_dump_bd = hns3_dbg_rx_bd_info, 960 }, 961 { 962 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 963 .dbg_dump = hns3_dbg_rx_queue_info, 964 }, 965 { 966 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 967 .dbg_dump = hns3_dbg_tx_queue_info, 968 }, 969 }; 970 971 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 972 enum hnae3_dbg_cmd cmd, char *buf, int len) 973 { 974 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 975 const struct hns3_dbg_func *cmd_func; 976 u32 i; 977 978 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 979 if (cmd == hns3_dbg_cmd_func[i].cmd) { 980 cmd_func = &hns3_dbg_cmd_func[i]; 981 if (cmd_func->dbg_dump) 982 return cmd_func->dbg_dump(dbg_data->handle, buf, 983 len); 984 else 985 return cmd_func->dbg_dump_bd(dbg_data, buf, 986 len); 987 } 988 } 989 990 if (!ops->dbg_read_cmd) 991 return -EOPNOTSUPP; 992 993 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 994 } 995 996 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 997 size_t count, loff_t *ppos) 998 { 999 struct hns3_dbg_data *dbg_data = filp->private_data; 1000 struct hnae3_handle *handle = dbg_data->handle; 1001 struct hns3_nic_priv *priv = handle->priv; 1002 ssize_t size = 0; 1003 char **save_buf; 1004 char *read_buf; 1005 u32 index; 1006 int ret; 1007 1008 ret = hns3_dbg_get_cmd_index(handle, filp->f_path.dentry->d_iname, 1009 &index); 1010 if (ret) 1011 return ret; 1012 1013 save_buf = &hns3_dbg_cmd[index].buf; 1014 1015 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1016 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 1017 ret = -EBUSY; 1018 goto out; 1019 } 1020 1021 if (*save_buf) { 1022 read_buf = *save_buf; 1023 } else { 1024 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 1025 if (!read_buf) 1026 return -ENOMEM; 1027 1028 /* save the buffer addr until the last read operation */ 1029 *save_buf = read_buf; 1030 } 1031 1032 /* get data ready for the first time to read */ 1033 if (!*ppos) { 1034 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 1035 read_buf, hns3_dbg_cmd[index].buf_len); 1036 if (ret) 1037 goto out; 1038 } 1039 1040 size = simple_read_from_buffer(buffer, count, ppos, read_buf, 1041 strlen(read_buf)); 1042 if (size > 0) 1043 return size; 1044 1045 out: 1046 /* free the buffer for the last read operation */ 1047 if (*save_buf) { 1048 kvfree(*save_buf); 1049 *save_buf = NULL; 1050 } 1051 1052 return ret; 1053 } 1054 1055 static const struct file_operations hns3_dbg_fops = { 1056 .owner = THIS_MODULE, 1057 .open = simple_open, 1058 .read = hns3_dbg_read, 1059 }; 1060 1061 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 1062 { 1063 struct dentry *entry_dir; 1064 struct hns3_dbg_data *data; 1065 u16 max_queue_num; 1066 unsigned int i; 1067 1068 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1069 max_queue_num = hns3_get_max_available_channels(handle); 1070 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 1071 GFP_KERNEL); 1072 if (!data) 1073 return -ENOMEM; 1074 1075 for (i = 0; i < max_queue_num; i++) { 1076 char name[HNS3_DBG_FILE_NAME_LEN]; 1077 1078 data[i].handle = handle; 1079 data[i].qid = i; 1080 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1081 debugfs_create_file(name, 0400, entry_dir, &data[i], 1082 &hns3_dbg_fops); 1083 } 1084 1085 return 0; 1086 } 1087 1088 static int 1089 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1090 { 1091 struct hns3_dbg_data *data; 1092 struct dentry *entry_dir; 1093 1094 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1095 if (!data) 1096 return -ENOMEM; 1097 1098 data->handle = handle; 1099 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1100 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1101 data, &hns3_dbg_fops); 1102 1103 return 0; 1104 } 1105 1106 int hns3_dbg_init(struct hnae3_handle *handle) 1107 { 1108 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1109 const char *name = pci_name(handle->pdev); 1110 int ret; 1111 u32 i; 1112 1113 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1114 debugfs_create_dir(name, hns3_dbgfs_root); 1115 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1116 1117 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1118 hns3_dbg_dentry[i].dentry = 1119 debugfs_create_dir(hns3_dbg_dentry[i].name, 1120 handle->hnae3_dbgfs); 1121 1122 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1123 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1124 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) || 1125 (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO && 1126 !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps))) 1127 continue; 1128 1129 if (!hns3_dbg_cmd[i].init) { 1130 dev_err(&handle->pdev->dev, 1131 "cmd %s lack of init func\n", 1132 hns3_dbg_cmd[i].name); 1133 ret = -EINVAL; 1134 goto out; 1135 } 1136 1137 ret = hns3_dbg_cmd[i].init(handle, i); 1138 if (ret) { 1139 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1140 hns3_dbg_cmd[i].name); 1141 goto out; 1142 } 1143 } 1144 1145 return 0; 1146 1147 out: 1148 debugfs_remove_recursive(handle->hnae3_dbgfs); 1149 handle->hnae3_dbgfs = NULL; 1150 return ret; 1151 } 1152 1153 void hns3_dbg_uninit(struct hnae3_handle *handle) 1154 { 1155 u32 i; 1156 1157 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1158 if (hns3_dbg_cmd[i].buf) { 1159 kvfree(hns3_dbg_cmd[i].buf); 1160 hns3_dbg_cmd[i].buf = NULL; 1161 } 1162 1163 debugfs_remove_recursive(handle->hnae3_dbgfs); 1164 handle->hnae3_dbgfs = NULL; 1165 } 1166 1167 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1168 { 1169 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1170 } 1171 1172 void hns3_dbg_unregister_debugfs(void) 1173 { 1174 debugfs_remove_recursive(hns3_dbgfs_root); 1175 hns3_dbgfs_root = NULL; 1176 } 1177