1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 7 #include "hnae3.h" 8 #include "hns3_debugfs.h" 9 #include "hns3_enet.h" 10 11 static struct dentry *hns3_dbgfs_root; 12 13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 14 { 15 .name = "tm" 16 }, 17 { 18 .name = "tx_bd_info" 19 }, 20 { 21 .name = "rx_bd_info" 22 }, 23 { 24 .name = "mac_list" 25 }, 26 { 27 .name = "reg" 28 }, 29 { 30 .name = "queue" 31 }, 32 { 33 .name = "fd" 34 }, 35 /* keep common at the bottom and add new directory above */ 36 { 37 .name = "common" 38 }, 39 }; 40 41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd); 42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, 43 unsigned int cmd); 44 45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 46 { 47 .name = "tm_nodes", 48 .cmd = HNAE3_DBG_CMD_TM_NODES, 49 .dentry = HNS3_DBG_DENTRY_TM, 50 .buf_len = HNS3_DBG_READ_LEN, 51 .init = hns3_dbg_common_file_init, 52 }, 53 { 54 .name = "tm_priority", 55 .cmd = HNAE3_DBG_CMD_TM_PRI, 56 .dentry = HNS3_DBG_DENTRY_TM, 57 .buf_len = HNS3_DBG_READ_LEN, 58 .init = hns3_dbg_common_file_init, 59 }, 60 { 61 .name = "tm_qset", 62 .cmd = HNAE3_DBG_CMD_TM_QSET, 63 .dentry = HNS3_DBG_DENTRY_TM, 64 .buf_len = HNS3_DBG_READ_LEN, 65 .init = hns3_dbg_common_file_init, 66 }, 67 { 68 .name = "tm_map", 69 .cmd = HNAE3_DBG_CMD_TM_MAP, 70 .dentry = HNS3_DBG_DENTRY_TM, 71 .buf_len = HNS3_DBG_READ_LEN_1MB, 72 .init = hns3_dbg_common_file_init, 73 }, 74 { 75 .name = "tm_pg", 76 .cmd = HNAE3_DBG_CMD_TM_PG, 77 .dentry = HNS3_DBG_DENTRY_TM, 78 .buf_len = HNS3_DBG_READ_LEN, 79 .init = hns3_dbg_common_file_init, 80 }, 81 { 82 .name = "tm_port", 83 .cmd = HNAE3_DBG_CMD_TM_PORT, 84 .dentry = HNS3_DBG_DENTRY_TM, 85 .buf_len = HNS3_DBG_READ_LEN, 86 .init = hns3_dbg_common_file_init, 87 }, 88 { 89 .name = "tc_sch_info", 90 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 91 .dentry = HNS3_DBG_DENTRY_TM, 92 .buf_len = HNS3_DBG_READ_LEN, 93 .init = hns3_dbg_common_file_init, 94 }, 95 { 96 .name = "qos_pause_cfg", 97 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 98 .dentry = HNS3_DBG_DENTRY_TM, 99 .buf_len = HNS3_DBG_READ_LEN, 100 .init = hns3_dbg_common_file_init, 101 }, 102 { 103 .name = "qos_pri_map", 104 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 105 .dentry = HNS3_DBG_DENTRY_TM, 106 .buf_len = HNS3_DBG_READ_LEN, 107 .init = hns3_dbg_common_file_init, 108 }, 109 { 110 .name = "qos_buf_cfg", 111 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 112 .dentry = HNS3_DBG_DENTRY_TM, 113 .buf_len = HNS3_DBG_READ_LEN, 114 .init = hns3_dbg_common_file_init, 115 }, 116 { 117 .name = "dev_info", 118 .cmd = HNAE3_DBG_CMD_DEV_INFO, 119 .dentry = HNS3_DBG_DENTRY_COMMON, 120 .buf_len = HNS3_DBG_READ_LEN, 121 .init = hns3_dbg_common_file_init, 122 }, 123 { 124 .name = "tx_bd_queue", 125 .cmd = HNAE3_DBG_CMD_TX_BD, 126 .dentry = HNS3_DBG_DENTRY_TX_BD, 127 .buf_len = HNS3_DBG_READ_LEN_4MB, 128 .init = hns3_dbg_bd_file_init, 129 }, 130 { 131 .name = "rx_bd_queue", 132 .cmd = HNAE3_DBG_CMD_RX_BD, 133 .dentry = HNS3_DBG_DENTRY_RX_BD, 134 .buf_len = HNS3_DBG_READ_LEN_4MB, 135 .init = hns3_dbg_bd_file_init, 136 }, 137 { 138 .name = "uc", 139 .cmd = HNAE3_DBG_CMD_MAC_UC, 140 .dentry = HNS3_DBG_DENTRY_MAC, 141 .buf_len = HNS3_DBG_READ_LEN, 142 .init = hns3_dbg_common_file_init, 143 }, 144 { 145 .name = "mc", 146 .cmd = HNAE3_DBG_CMD_MAC_MC, 147 .dentry = HNS3_DBG_DENTRY_MAC, 148 .buf_len = HNS3_DBG_READ_LEN, 149 .init = hns3_dbg_common_file_init, 150 }, 151 { 152 .name = "mng_tbl", 153 .cmd = HNAE3_DBG_CMD_MNG_TBL, 154 .dentry = HNS3_DBG_DENTRY_COMMON, 155 .buf_len = HNS3_DBG_READ_LEN, 156 .init = hns3_dbg_common_file_init, 157 }, 158 { 159 .name = "loopback", 160 .cmd = HNAE3_DBG_CMD_LOOPBACK, 161 .dentry = HNS3_DBG_DENTRY_COMMON, 162 .buf_len = HNS3_DBG_READ_LEN, 163 .init = hns3_dbg_common_file_init, 164 }, 165 { 166 .name = "interrupt_info", 167 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 168 .dentry = HNS3_DBG_DENTRY_COMMON, 169 .buf_len = HNS3_DBG_READ_LEN, 170 .init = hns3_dbg_common_file_init, 171 }, 172 { 173 .name = "reset_info", 174 .cmd = HNAE3_DBG_CMD_RESET_INFO, 175 .dentry = HNS3_DBG_DENTRY_COMMON, 176 .buf_len = HNS3_DBG_READ_LEN, 177 .init = hns3_dbg_common_file_init, 178 }, 179 { 180 .name = "imp_info", 181 .cmd = HNAE3_DBG_CMD_IMP_INFO, 182 .dentry = HNS3_DBG_DENTRY_COMMON, 183 .buf_len = HNS3_DBG_READ_LEN, 184 .init = hns3_dbg_common_file_init, 185 }, 186 { 187 .name = "ncl_config", 188 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 189 .dentry = HNS3_DBG_DENTRY_COMMON, 190 .buf_len = HNS3_DBG_READ_LEN_128KB, 191 .init = hns3_dbg_common_file_init, 192 }, 193 { 194 .name = "mac_tnl_status", 195 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 196 .dentry = HNS3_DBG_DENTRY_COMMON, 197 .buf_len = HNS3_DBG_READ_LEN, 198 .init = hns3_dbg_common_file_init, 199 }, 200 { 201 .name = "bios_common", 202 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 203 .dentry = HNS3_DBG_DENTRY_REG, 204 .buf_len = HNS3_DBG_READ_LEN, 205 .init = hns3_dbg_common_file_init, 206 }, 207 { 208 .name = "ssu", 209 .cmd = HNAE3_DBG_CMD_REG_SSU, 210 .dentry = HNS3_DBG_DENTRY_REG, 211 .buf_len = HNS3_DBG_READ_LEN, 212 .init = hns3_dbg_common_file_init, 213 }, 214 { 215 .name = "igu_egu", 216 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 217 .dentry = HNS3_DBG_DENTRY_REG, 218 .buf_len = HNS3_DBG_READ_LEN, 219 .init = hns3_dbg_common_file_init, 220 }, 221 { 222 .name = "rpu", 223 .cmd = HNAE3_DBG_CMD_REG_RPU, 224 .dentry = HNS3_DBG_DENTRY_REG, 225 .buf_len = HNS3_DBG_READ_LEN, 226 .init = hns3_dbg_common_file_init, 227 }, 228 { 229 .name = "ncsi", 230 .cmd = HNAE3_DBG_CMD_REG_NCSI, 231 .dentry = HNS3_DBG_DENTRY_REG, 232 .buf_len = HNS3_DBG_READ_LEN, 233 .init = hns3_dbg_common_file_init, 234 }, 235 { 236 .name = "rtc", 237 .cmd = HNAE3_DBG_CMD_REG_RTC, 238 .dentry = HNS3_DBG_DENTRY_REG, 239 .buf_len = HNS3_DBG_READ_LEN, 240 .init = hns3_dbg_common_file_init, 241 }, 242 { 243 .name = "ppp", 244 .cmd = HNAE3_DBG_CMD_REG_PPP, 245 .dentry = HNS3_DBG_DENTRY_REG, 246 .buf_len = HNS3_DBG_READ_LEN, 247 .init = hns3_dbg_common_file_init, 248 }, 249 { 250 .name = "rcb", 251 .cmd = HNAE3_DBG_CMD_REG_RCB, 252 .dentry = HNS3_DBG_DENTRY_REG, 253 .buf_len = HNS3_DBG_READ_LEN, 254 .init = hns3_dbg_common_file_init, 255 }, 256 { 257 .name = "tqp", 258 .cmd = HNAE3_DBG_CMD_REG_TQP, 259 .dentry = HNS3_DBG_DENTRY_REG, 260 .buf_len = HNS3_DBG_READ_LEN, 261 .init = hns3_dbg_common_file_init, 262 }, 263 { 264 .name = "mac", 265 .cmd = HNAE3_DBG_CMD_REG_MAC, 266 .dentry = HNS3_DBG_DENTRY_REG, 267 .buf_len = HNS3_DBG_READ_LEN, 268 .init = hns3_dbg_common_file_init, 269 }, 270 { 271 .name = "dcb", 272 .cmd = HNAE3_DBG_CMD_REG_DCB, 273 .dentry = HNS3_DBG_DENTRY_REG, 274 .buf_len = HNS3_DBG_READ_LEN, 275 .init = hns3_dbg_common_file_init, 276 }, 277 { 278 .name = "queue_map", 279 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 280 .dentry = HNS3_DBG_DENTRY_QUEUE, 281 .buf_len = HNS3_DBG_READ_LEN, 282 .init = hns3_dbg_common_file_init, 283 }, 284 { 285 .name = "rx_queue_info", 286 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 287 .dentry = HNS3_DBG_DENTRY_QUEUE, 288 .buf_len = HNS3_DBG_READ_LEN_1MB, 289 .init = hns3_dbg_common_file_init, 290 }, 291 { 292 .name = "tx_queue_info", 293 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 294 .dentry = HNS3_DBG_DENTRY_QUEUE, 295 .buf_len = HNS3_DBG_READ_LEN_1MB, 296 .init = hns3_dbg_common_file_init, 297 }, 298 { 299 .name = "fd_tcam", 300 .cmd = HNAE3_DBG_CMD_FD_TCAM, 301 .dentry = HNS3_DBG_DENTRY_FD, 302 .buf_len = HNS3_DBG_READ_LEN, 303 .init = hns3_dbg_common_file_init, 304 }, 305 { 306 .name = "service_task_info", 307 .cmd = HNAE3_DBG_CMD_SERV_INFO, 308 .dentry = HNS3_DBG_DENTRY_COMMON, 309 .buf_len = HNS3_DBG_READ_LEN, 310 .init = hns3_dbg_common_file_init, 311 }, 312 { 313 .name = "vlan_config", 314 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 315 .dentry = HNS3_DBG_DENTRY_COMMON, 316 .buf_len = HNS3_DBG_READ_LEN, 317 .init = hns3_dbg_common_file_init, 318 }, 319 { 320 .name = "ptp_info", 321 .cmd = HNAE3_DBG_CMD_PTP_INFO, 322 .dentry = HNS3_DBG_DENTRY_COMMON, 323 .buf_len = HNS3_DBG_READ_LEN, 324 .init = hns3_dbg_common_file_init, 325 }, 326 }; 327 328 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 329 { 330 .name = "support FD", 331 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 332 }, { 333 .name = "support GRO", 334 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 335 }, { 336 .name = "support FEC", 337 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 338 }, { 339 .name = "support UDP GSO", 340 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 341 }, { 342 .name = "support PTP", 343 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 344 }, { 345 .name = "support INT QL", 346 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 347 }, { 348 .name = "support HW TX csum", 349 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 350 }, { 351 .name = "support UDP tunnel csum", 352 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 353 }, { 354 .name = "support TX push", 355 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 356 }, { 357 .name = "support imp-controlled PHY", 358 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 359 }, { 360 .name = "support imp-controlled RAS", 361 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B, 362 }, { 363 .name = "support rxd advanced layout", 364 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 365 }, { 366 .name = "support port vlan bypass", 367 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 368 }, { 369 .name = "support modify vlan filter state", 370 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 371 } 372 }; 373 374 static void hns3_dbg_fill_content(char *content, u16 len, 375 const struct hns3_dbg_item *items, 376 const char **result, u16 size) 377 { 378 char *pos = content; 379 u16 i; 380 381 memset(content, ' ', len); 382 for (i = 0; i < size; i++) { 383 if (result) 384 strncpy(pos, result[i], strlen(result[i])); 385 else 386 strncpy(pos, items[i].name, strlen(items[i].name)); 387 388 pos += strlen(items[i].name) + items[i].interval; 389 } 390 391 *pos++ = '\n'; 392 *pos++ = '\0'; 393 } 394 395 static const struct hns3_dbg_item rx_queue_info_items[] = { 396 { "QUEUE_ID", 2 }, 397 { "BD_NUM", 2 }, 398 { "BD_LEN", 2 }, 399 { "TAIL", 2 }, 400 { "HEAD", 2 }, 401 { "FBDNUM", 2 }, 402 { "PKTNUM", 2 }, 403 { "RING_EN", 2 }, 404 { "RX_RING_EN", 2 }, 405 { "BASE_ADDR", 10 }, 406 }; 407 408 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 409 struct hnae3_ae_dev *ae_dev, char **result, 410 u32 index) 411 { 412 u32 base_add_l, base_add_h; 413 u32 j = 0; 414 415 sprintf(result[j++], "%8u", index); 416 417 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 418 HNS3_RING_RX_RING_BD_NUM_REG)); 419 420 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 421 HNS3_RING_RX_RING_BD_LEN_REG)); 422 423 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 424 HNS3_RING_RX_RING_TAIL_REG)); 425 426 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 427 HNS3_RING_RX_RING_HEAD_REG)); 428 429 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 430 HNS3_RING_RX_RING_FBDNUM_REG)); 431 432 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 433 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 434 435 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 436 HNS3_RING_EN_REG) ? "on" : "off"); 437 438 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 439 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 440 HNS3_RING_RX_EN_REG) ? "on" : "off"); 441 else 442 sprintf(result[j++], "%10s", "NA"); 443 444 base_add_h = readl_relaxed(ring->tqp->io_base + 445 HNS3_RING_RX_RING_BASEADDR_H_REG); 446 base_add_l = readl_relaxed(ring->tqp->io_base + 447 HNS3_RING_RX_RING_BASEADDR_L_REG); 448 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 449 } 450 451 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 452 char *buf, int len) 453 { 454 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 455 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 456 char *result[ARRAY_SIZE(rx_queue_info_items)]; 457 struct hns3_nic_priv *priv = h->priv; 458 char content[HNS3_DBG_INFO_LEN]; 459 struct hns3_enet_ring *ring; 460 int pos = 0; 461 u32 i; 462 463 if (!priv->ring) { 464 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 465 return -EFAULT; 466 } 467 468 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 469 result[i] = &data_str[i][0]; 470 471 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 472 NULL, ARRAY_SIZE(rx_queue_info_items)); 473 pos += scnprintf(buf + pos, len - pos, "%s", content); 474 for (i = 0; i < h->kinfo.num_tqps; i++) { 475 /* Each cycle needs to determine whether the instance is reset, 476 * to prevent reference to invalid memory. And need to ensure 477 * that the following code is executed within 100ms. 478 */ 479 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 480 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 481 return -EPERM; 482 483 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 484 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 485 hns3_dbg_fill_content(content, sizeof(content), 486 rx_queue_info_items, 487 (const char **)result, 488 ARRAY_SIZE(rx_queue_info_items)); 489 pos += scnprintf(buf + pos, len - pos, "%s", content); 490 } 491 492 return 0; 493 } 494 495 static const struct hns3_dbg_item tx_queue_info_items[] = { 496 { "QUEUE_ID", 2 }, 497 { "BD_NUM", 2 }, 498 { "TC", 2 }, 499 { "TAIL", 2 }, 500 { "HEAD", 2 }, 501 { "FBDNUM", 2 }, 502 { "OFFSET", 2 }, 503 { "PKTNUM", 2 }, 504 { "RING_EN", 2 }, 505 { "TX_RING_EN", 2 }, 506 { "BASE_ADDR", 10 }, 507 }; 508 509 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 510 struct hnae3_ae_dev *ae_dev, char **result, 511 u32 index) 512 { 513 u32 base_add_l, base_add_h; 514 u32 j = 0; 515 516 sprintf(result[j++], "%8u", index); 517 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 518 HNS3_RING_TX_RING_BD_NUM_REG)); 519 520 sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base + 521 HNS3_RING_TX_RING_TC_REG)); 522 523 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 524 HNS3_RING_TX_RING_TAIL_REG)); 525 526 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 527 HNS3_RING_TX_RING_HEAD_REG)); 528 529 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 530 HNS3_RING_TX_RING_FBDNUM_REG)); 531 532 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 533 HNS3_RING_TX_RING_OFFSET_REG)); 534 535 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 536 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 537 538 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 539 HNS3_RING_EN_REG) ? "on" : "off"); 540 541 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 542 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 543 HNS3_RING_TX_EN_REG) ? "on" : "off"); 544 else 545 sprintf(result[j++], "%10s", "NA"); 546 547 base_add_h = readl_relaxed(ring->tqp->io_base + 548 HNS3_RING_TX_RING_BASEADDR_H_REG); 549 base_add_l = readl_relaxed(ring->tqp->io_base + 550 HNS3_RING_TX_RING_BASEADDR_L_REG); 551 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 552 } 553 554 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 555 char *buf, int len) 556 { 557 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 558 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 559 char *result[ARRAY_SIZE(tx_queue_info_items)]; 560 struct hns3_nic_priv *priv = h->priv; 561 char content[HNS3_DBG_INFO_LEN]; 562 struct hns3_enet_ring *ring; 563 int pos = 0; 564 u32 i; 565 566 if (!priv->ring) { 567 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 568 return -EFAULT; 569 } 570 571 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 572 result[i] = &data_str[i][0]; 573 574 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 575 NULL, ARRAY_SIZE(tx_queue_info_items)); 576 pos += scnprintf(buf + pos, len - pos, "%s", content); 577 578 for (i = 0; i < h->kinfo.num_tqps; i++) { 579 /* Each cycle needs to determine whether the instance is reset, 580 * to prevent reference to invalid memory. And need to ensure 581 * that the following code is executed within 100ms. 582 */ 583 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 584 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 585 return -EPERM; 586 587 ring = &priv->ring[i]; 588 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 589 hns3_dbg_fill_content(content, sizeof(content), 590 tx_queue_info_items, 591 (const char **)result, 592 ARRAY_SIZE(tx_queue_info_items)); 593 pos += scnprintf(buf + pos, len - pos, "%s", content); 594 } 595 596 return 0; 597 } 598 599 static const struct hns3_dbg_item queue_map_items[] = { 600 { "local_queue_id", 2 }, 601 { "global_queue_id", 2 }, 602 { "vector_id", 2 }, 603 }; 604 605 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 606 { 607 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 608 char *result[ARRAY_SIZE(queue_map_items)]; 609 struct hns3_nic_priv *priv = h->priv; 610 char content[HNS3_DBG_INFO_LEN]; 611 int pos = 0; 612 int j; 613 u32 i; 614 615 if (!h->ae_algo->ops->get_global_queue_id) 616 return -EOPNOTSUPP; 617 618 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 619 result[i] = &data_str[i][0]; 620 621 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 622 NULL, ARRAY_SIZE(queue_map_items)); 623 pos += scnprintf(buf + pos, len - pos, "%s", content); 624 for (i = 0; i < h->kinfo.num_tqps; i++) { 625 if (!priv->ring || !priv->ring[i].tqp_vector) 626 continue; 627 j = 0; 628 sprintf(result[j++], "%u", i); 629 sprintf(result[j++], "%u", 630 h->ae_algo->ops->get_global_queue_id(h, i)); 631 sprintf(result[j++], "%u", 632 priv->ring[i].tqp_vector->vector_irq); 633 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 634 (const char **)result, 635 ARRAY_SIZE(queue_map_items)); 636 pos += scnprintf(buf + pos, len - pos, "%s", content); 637 } 638 639 return 0; 640 } 641 642 static const struct hns3_dbg_item rx_bd_info_items[] = { 643 { "BD_IDX", 3 }, 644 { "L234_INFO", 2 }, 645 { "PKT_LEN", 3 }, 646 { "SIZE", 4 }, 647 { "RSS_HASH", 4 }, 648 { "FD_ID", 2 }, 649 { "VLAN_TAG", 2 }, 650 { "O_DM_VLAN_ID_FB", 2 }, 651 { "OT_VLAN_TAG", 2 }, 652 { "BD_BASE_INFO", 2 }, 653 { "PTYPE", 2 }, 654 { "HW_CSUM", 2 }, 655 }; 656 657 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 658 struct hns3_desc *desc, char **result, int idx) 659 { 660 unsigned int j = 0; 661 662 sprintf(result[j++], "%5d", idx); 663 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 664 sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len)); 665 sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size)); 666 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 667 sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id)); 668 sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag)); 669 sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 670 sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag)); 671 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 672 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 673 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 674 675 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 676 HNS3_RXD_PTYPE_M, 677 HNS3_RXD_PTYPE_S)); 678 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 679 } else { 680 sprintf(result[j++], "NA"); 681 sprintf(result[j++], "NA"); 682 } 683 } 684 685 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 686 { 687 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 688 struct hns3_nic_priv *priv = d->handle->priv; 689 char *result[ARRAY_SIZE(rx_bd_info_items)]; 690 char content[HNS3_DBG_INFO_LEN]; 691 struct hns3_enet_ring *ring; 692 struct hns3_desc *desc; 693 unsigned int i; 694 int pos = 0; 695 696 if (d->qid >= d->handle->kinfo.num_tqps) { 697 dev_err(&d->handle->pdev->dev, 698 "queue%u is not in use\n", d->qid); 699 return -EINVAL; 700 } 701 702 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 703 result[i] = &data_str[i][0]; 704 705 pos += scnprintf(buf + pos, len - pos, 706 "Queue %u rx bd info:\n", d->qid); 707 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 708 NULL, ARRAY_SIZE(rx_bd_info_items)); 709 pos += scnprintf(buf + pos, len - pos, "%s", content); 710 711 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 712 for (i = 0; i < ring->desc_num; i++) { 713 desc = &ring->desc[i]; 714 715 hns3_dump_rx_bd_info(priv, desc, result, i); 716 hns3_dbg_fill_content(content, sizeof(content), 717 rx_bd_info_items, (const char **)result, 718 ARRAY_SIZE(rx_bd_info_items)); 719 pos += scnprintf(buf + pos, len - pos, "%s", content); 720 } 721 722 return 0; 723 } 724 725 static const struct hns3_dbg_item tx_bd_info_items[] = { 726 { "BD_IDX", 5 }, 727 { "ADDRESS", 2 }, 728 { "VLAN_TAG", 2 }, 729 { "SIZE", 2 }, 730 { "T_CS_VLAN_TSO", 2 }, 731 { "OT_VLAN_TAG", 3 }, 732 { "TV", 2 }, 733 { "OLT_VLAN_LEN", 2}, 734 { "PAYLEN_OL4CS", 2}, 735 { "BD_FE_SC_VLD", 2}, 736 { "MSS_HW_CSUM", 0}, 737 }; 738 739 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, 740 struct hns3_desc *desc, char **result, int idx) 741 { 742 unsigned int j = 0; 743 744 sprintf(result[j++], "%6d", idx); 745 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 746 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag)); 747 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size)); 748 sprintf(result[j++], "%#x", 749 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 750 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag)); 751 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv)); 752 sprintf(result[j++], "%10u", 753 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 754 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 755 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 756 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum)); 757 } 758 759 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 760 { 761 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 762 struct hns3_nic_priv *priv = d->handle->priv; 763 char *result[ARRAY_SIZE(tx_bd_info_items)]; 764 char content[HNS3_DBG_INFO_LEN]; 765 struct hns3_enet_ring *ring; 766 struct hns3_desc *desc; 767 unsigned int i; 768 int pos = 0; 769 770 if (d->qid >= d->handle->kinfo.num_tqps) { 771 dev_err(&d->handle->pdev->dev, 772 "queue%u is not in use\n", d->qid); 773 return -EINVAL; 774 } 775 776 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 777 result[i] = &data_str[i][0]; 778 779 pos += scnprintf(buf + pos, len - pos, 780 "Queue %u tx bd info:\n", d->qid); 781 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 782 NULL, ARRAY_SIZE(tx_bd_info_items)); 783 pos += scnprintf(buf + pos, len - pos, "%s", content); 784 785 ring = &priv->ring[d->qid]; 786 for (i = 0; i < ring->desc_num; i++) { 787 desc = &ring->desc[i]; 788 789 hns3_dump_tx_bd_info(priv, desc, result, i); 790 hns3_dbg_fill_content(content, sizeof(content), 791 tx_bd_info_items, (const char **)result, 792 ARRAY_SIZE(tx_bd_info_items)); 793 pos += scnprintf(buf + pos, len - pos, "%s", content); 794 } 795 796 return 0; 797 } 798 799 static void 800 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 801 { 802 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 803 static const char * const str[] = {"no", "yes"}; 804 unsigned long *caps = ae_dev->caps; 805 u32 i, state; 806 807 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 808 809 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 810 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 811 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 812 hns3_dbg_cap[i].name, str[state]); 813 } 814 815 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 816 } 817 818 static void 819 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 820 { 821 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 822 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 823 struct hnae3_knic_private_info *kinfo = &h->kinfo; 824 825 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 826 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 827 dev_specs->mac_entry_num); 828 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 829 dev_specs->mng_entry_num); 830 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 831 dev_specs->max_non_tso_bd_num); 832 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 833 dev_specs->rss_ind_tbl_size); 834 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 835 dev_specs->rss_key_size); 836 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 837 kinfo->rss_size); 838 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 839 kinfo->req_rss_size); 840 *pos += scnprintf(buf + *pos, len - *pos, 841 "Task queue pairs numbers: %u\n", 842 kinfo->num_tqps); 843 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 844 kinfo->rx_buf_len); 845 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 846 kinfo->num_tx_desc); 847 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 848 kinfo->num_rx_desc); 849 *pos += scnprintf(buf + *pos, len - *pos, 850 "Total number of enabled TCs: %u\n", 851 kinfo->tc_info.num_tc); 852 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 853 dev_specs->int_ql_max); 854 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 855 dev_specs->max_int_gl); 856 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 857 dev_specs->max_tm_rate); 858 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 859 dev_specs->max_qset_num); 860 } 861 862 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 863 { 864 int pos = 0; 865 866 hns3_dbg_dev_caps(h, buf, len, &pos); 867 868 hns3_dbg_dev_specs(h, buf, len, &pos); 869 870 return 0; 871 } 872 873 static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle, 874 const unsigned char *name, u32 *index) 875 { 876 u32 i; 877 878 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 879 if (!strncmp(name, hns3_dbg_cmd[i].name, 880 strlen(hns3_dbg_cmd[i].name))) { 881 *index = i; 882 return 0; 883 } 884 } 885 886 dev_err(&handle->pdev->dev, "unknown command(%s)\n", name); 887 return -EINVAL; 888 } 889 890 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 891 { 892 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 893 .dbg_dump = hns3_dbg_queue_map, 894 }, 895 { 896 .cmd = HNAE3_DBG_CMD_DEV_INFO, 897 .dbg_dump = hns3_dbg_dev_info, 898 }, 899 { 900 .cmd = HNAE3_DBG_CMD_TX_BD, 901 .dbg_dump_bd = hns3_dbg_tx_bd_info, 902 }, 903 { 904 .cmd = HNAE3_DBG_CMD_RX_BD, 905 .dbg_dump_bd = hns3_dbg_rx_bd_info, 906 }, 907 { 908 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 909 .dbg_dump = hns3_dbg_rx_queue_info, 910 }, 911 { 912 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 913 .dbg_dump = hns3_dbg_tx_queue_info, 914 }, 915 }; 916 917 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 918 enum hnae3_dbg_cmd cmd, char *buf, int len) 919 { 920 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 921 const struct hns3_dbg_func *cmd_func; 922 u32 i; 923 924 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 925 if (cmd == hns3_dbg_cmd_func[i].cmd) { 926 cmd_func = &hns3_dbg_cmd_func[i]; 927 if (cmd_func->dbg_dump) 928 return cmd_func->dbg_dump(dbg_data->handle, buf, 929 len); 930 else 931 return cmd_func->dbg_dump_bd(dbg_data, buf, 932 len); 933 } 934 } 935 936 if (!ops->dbg_read_cmd) 937 return -EOPNOTSUPP; 938 939 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 940 } 941 942 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 943 size_t count, loff_t *ppos) 944 { 945 struct hns3_dbg_data *dbg_data = filp->private_data; 946 struct hnae3_handle *handle = dbg_data->handle; 947 struct hns3_nic_priv *priv = handle->priv; 948 ssize_t size = 0; 949 char **save_buf; 950 char *read_buf; 951 u32 index; 952 int ret; 953 954 ret = hns3_dbg_get_cmd_index(handle, filp->f_path.dentry->d_iname, 955 &index); 956 if (ret) 957 return ret; 958 959 save_buf = &hns3_dbg_cmd[index].buf; 960 961 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 962 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 963 ret = -EBUSY; 964 goto out; 965 } 966 967 if (*save_buf) { 968 read_buf = *save_buf; 969 } else { 970 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 971 if (!read_buf) 972 return -ENOMEM; 973 974 /* save the buffer addr until the last read operation */ 975 *save_buf = read_buf; 976 } 977 978 /* get data ready for the first time to read */ 979 if (!*ppos) { 980 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 981 read_buf, hns3_dbg_cmd[index].buf_len); 982 if (ret) 983 goto out; 984 } 985 986 size = simple_read_from_buffer(buffer, count, ppos, read_buf, 987 strlen(read_buf)); 988 if (size > 0) 989 return size; 990 991 out: 992 /* free the buffer for the last read operation */ 993 if (*save_buf) { 994 kvfree(*save_buf); 995 *save_buf = NULL; 996 } 997 998 return ret; 999 } 1000 1001 static const struct file_operations hns3_dbg_fops = { 1002 .owner = THIS_MODULE, 1003 .open = simple_open, 1004 .read = hns3_dbg_read, 1005 }; 1006 1007 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 1008 { 1009 struct dentry *entry_dir; 1010 struct hns3_dbg_data *data; 1011 u16 max_queue_num; 1012 unsigned int i; 1013 1014 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1015 max_queue_num = hns3_get_max_available_channels(handle); 1016 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 1017 GFP_KERNEL); 1018 if (!data) 1019 return -ENOMEM; 1020 1021 for (i = 0; i < max_queue_num; i++) { 1022 char name[HNS3_DBG_FILE_NAME_LEN]; 1023 1024 data[i].handle = handle; 1025 data[i].qid = i; 1026 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1027 debugfs_create_file(name, 0400, entry_dir, &data[i], 1028 &hns3_dbg_fops); 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int 1035 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1036 { 1037 struct hns3_dbg_data *data; 1038 struct dentry *entry_dir; 1039 1040 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1041 if (!data) 1042 return -ENOMEM; 1043 1044 data->handle = handle; 1045 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1046 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1047 data, &hns3_dbg_fops); 1048 1049 return 0; 1050 } 1051 1052 int hns3_dbg_init(struct hnae3_handle *handle) 1053 { 1054 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1055 const char *name = pci_name(handle->pdev); 1056 int ret; 1057 u32 i; 1058 1059 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1060 debugfs_create_dir(name, hns3_dbgfs_root); 1061 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1062 1063 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1064 hns3_dbg_dentry[i].dentry = 1065 debugfs_create_dir(hns3_dbg_dentry[i].name, 1066 handle->hnae3_dbgfs); 1067 1068 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1069 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1070 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) || 1071 (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO && 1072 !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps))) 1073 continue; 1074 1075 if (!hns3_dbg_cmd[i].init) { 1076 dev_err(&handle->pdev->dev, 1077 "cmd %s lack of init func\n", 1078 hns3_dbg_cmd[i].name); 1079 ret = -EINVAL; 1080 goto out; 1081 } 1082 1083 ret = hns3_dbg_cmd[i].init(handle, i); 1084 if (ret) { 1085 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1086 hns3_dbg_cmd[i].name); 1087 goto out; 1088 } 1089 } 1090 1091 return 0; 1092 1093 out: 1094 debugfs_remove_recursive(handle->hnae3_dbgfs); 1095 handle->hnae3_dbgfs = NULL; 1096 return ret; 1097 } 1098 1099 void hns3_dbg_uninit(struct hnae3_handle *handle) 1100 { 1101 u32 i; 1102 1103 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1104 if (hns3_dbg_cmd[i].buf) { 1105 kvfree(hns3_dbg_cmd[i].buf); 1106 hns3_dbg_cmd[i].buf = NULL; 1107 } 1108 1109 debugfs_remove_recursive(handle->hnae3_dbgfs); 1110 handle->hnae3_dbgfs = NULL; 1111 } 1112 1113 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1114 { 1115 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1116 } 1117 1118 void hns3_dbg_unregister_debugfs(void) 1119 { 1120 debugfs_remove_recursive(hns3_dbgfs_root); 1121 hns3_dbgfs_root = NULL; 1122 } 1123