1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
3 
4 #include <linux/debugfs.h>
5 #include <linux/device.h>
6 
7 #include "hnae3.h"
8 #include "hns3_debugfs.h"
9 #include "hns3_enet.h"
10 
11 static struct dentry *hns3_dbgfs_root;
12 
13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
14 	{
15 		.name = "tm"
16 	},
17 	{
18 		.name = "tx_bd_info"
19 	},
20 	{
21 		.name = "rx_bd_info"
22 	},
23 	{
24 		.name = "mac_list"
25 	},
26 	{
27 		.name = "reg"
28 	},
29 	{
30 		.name = "queue"
31 	},
32 	{
33 		.name = "fd"
34 	},
35 	/* keep common at the bottom and add new directory above */
36 	{
37 		.name = "common"
38 	},
39 };
40 
41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd);
42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd);
43 
44 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
45 	{
46 		.name = "tm_nodes",
47 		.cmd = HNAE3_DBG_CMD_TM_NODES,
48 		.dentry = HNS3_DBG_DENTRY_TM,
49 		.buf_len = HNS3_DBG_READ_LEN,
50 		.init = hns3_dbg_common_file_init,
51 	},
52 	{
53 		.name = "tm_priority",
54 		.cmd = HNAE3_DBG_CMD_TM_PRI,
55 		.dentry = HNS3_DBG_DENTRY_TM,
56 		.buf_len = HNS3_DBG_READ_LEN,
57 		.init = hns3_dbg_common_file_init,
58 	},
59 	{
60 		.name = "tm_qset",
61 		.cmd = HNAE3_DBG_CMD_TM_QSET,
62 		.dentry = HNS3_DBG_DENTRY_TM,
63 		.buf_len = HNS3_DBG_READ_LEN,
64 		.init = hns3_dbg_common_file_init,
65 	},
66 	{
67 		.name = "tm_map",
68 		.cmd = HNAE3_DBG_CMD_TM_MAP,
69 		.dentry = HNS3_DBG_DENTRY_TM,
70 		.buf_len = HNS3_DBG_READ_LEN_1MB,
71 		.init = hns3_dbg_common_file_init,
72 	},
73 	{
74 		.name = "tm_pg",
75 		.cmd = HNAE3_DBG_CMD_TM_PG,
76 		.dentry = HNS3_DBG_DENTRY_TM,
77 		.buf_len = HNS3_DBG_READ_LEN,
78 		.init = hns3_dbg_common_file_init,
79 	},
80 	{
81 		.name = "tm_port",
82 		.cmd = HNAE3_DBG_CMD_TM_PORT,
83 		.dentry = HNS3_DBG_DENTRY_TM,
84 		.buf_len = HNS3_DBG_READ_LEN,
85 		.init = hns3_dbg_common_file_init,
86 	},
87 	{
88 		.name = "tc_sch_info",
89 		.cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
90 		.dentry = HNS3_DBG_DENTRY_TM,
91 		.buf_len = HNS3_DBG_READ_LEN,
92 		.init = hns3_dbg_common_file_init,
93 	},
94 	{
95 		.name = "qos_pause_cfg",
96 		.cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
97 		.dentry = HNS3_DBG_DENTRY_TM,
98 		.buf_len = HNS3_DBG_READ_LEN,
99 		.init = hns3_dbg_common_file_init,
100 	},
101 	{
102 		.name = "qos_pri_map",
103 		.cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
104 		.dentry = HNS3_DBG_DENTRY_TM,
105 		.buf_len = HNS3_DBG_READ_LEN,
106 		.init = hns3_dbg_common_file_init,
107 	},
108 	{
109 		.name = "qos_dscp_map",
110 		.cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP,
111 		.dentry = HNS3_DBG_DENTRY_TM,
112 		.buf_len = HNS3_DBG_READ_LEN,
113 		.init = hns3_dbg_common_file_init,
114 	},
115 	{
116 		.name = "qos_buf_cfg",
117 		.cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
118 		.dentry = HNS3_DBG_DENTRY_TM,
119 		.buf_len = HNS3_DBG_READ_LEN,
120 		.init = hns3_dbg_common_file_init,
121 	},
122 	{
123 		.name = "dev_info",
124 		.cmd = HNAE3_DBG_CMD_DEV_INFO,
125 		.dentry = HNS3_DBG_DENTRY_COMMON,
126 		.buf_len = HNS3_DBG_READ_LEN,
127 		.init = hns3_dbg_common_file_init,
128 	},
129 	{
130 		.name = "tx_bd_queue",
131 		.cmd = HNAE3_DBG_CMD_TX_BD,
132 		.dentry = HNS3_DBG_DENTRY_TX_BD,
133 		.buf_len = HNS3_DBG_READ_LEN_5MB,
134 		.init = hns3_dbg_bd_file_init,
135 	},
136 	{
137 		.name = "rx_bd_queue",
138 		.cmd = HNAE3_DBG_CMD_RX_BD,
139 		.dentry = HNS3_DBG_DENTRY_RX_BD,
140 		.buf_len = HNS3_DBG_READ_LEN_4MB,
141 		.init = hns3_dbg_bd_file_init,
142 	},
143 	{
144 		.name = "uc",
145 		.cmd = HNAE3_DBG_CMD_MAC_UC,
146 		.dentry = HNS3_DBG_DENTRY_MAC,
147 		.buf_len = HNS3_DBG_READ_LEN_128KB,
148 		.init = hns3_dbg_common_file_init,
149 	},
150 	{
151 		.name = "mc",
152 		.cmd = HNAE3_DBG_CMD_MAC_MC,
153 		.dentry = HNS3_DBG_DENTRY_MAC,
154 		.buf_len = HNS3_DBG_READ_LEN,
155 		.init = hns3_dbg_common_file_init,
156 	},
157 	{
158 		.name = "mng_tbl",
159 		.cmd = HNAE3_DBG_CMD_MNG_TBL,
160 		.dentry = HNS3_DBG_DENTRY_COMMON,
161 		.buf_len = HNS3_DBG_READ_LEN,
162 		.init = hns3_dbg_common_file_init,
163 	},
164 	{
165 		.name = "loopback",
166 		.cmd = HNAE3_DBG_CMD_LOOPBACK,
167 		.dentry = HNS3_DBG_DENTRY_COMMON,
168 		.buf_len = HNS3_DBG_READ_LEN,
169 		.init = hns3_dbg_common_file_init,
170 	},
171 	{
172 		.name = "interrupt_info",
173 		.cmd = HNAE3_DBG_CMD_INTERRUPT_INFO,
174 		.dentry = HNS3_DBG_DENTRY_COMMON,
175 		.buf_len = HNS3_DBG_READ_LEN,
176 		.init = hns3_dbg_common_file_init,
177 	},
178 	{
179 		.name = "reset_info",
180 		.cmd = HNAE3_DBG_CMD_RESET_INFO,
181 		.dentry = HNS3_DBG_DENTRY_COMMON,
182 		.buf_len = HNS3_DBG_READ_LEN,
183 		.init = hns3_dbg_common_file_init,
184 	},
185 	{
186 		.name = "imp_info",
187 		.cmd = HNAE3_DBG_CMD_IMP_INFO,
188 		.dentry = HNS3_DBG_DENTRY_COMMON,
189 		.buf_len = HNS3_DBG_READ_LEN,
190 		.init = hns3_dbg_common_file_init,
191 	},
192 	{
193 		.name = "ncl_config",
194 		.cmd = HNAE3_DBG_CMD_NCL_CONFIG,
195 		.dentry = HNS3_DBG_DENTRY_COMMON,
196 		.buf_len = HNS3_DBG_READ_LEN_128KB,
197 		.init = hns3_dbg_common_file_init,
198 	},
199 	{
200 		.name = "mac_tnl_status",
201 		.cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
202 		.dentry = HNS3_DBG_DENTRY_COMMON,
203 		.buf_len = HNS3_DBG_READ_LEN,
204 		.init = hns3_dbg_common_file_init,
205 	},
206 	{
207 		.name = "bios_common",
208 		.cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
209 		.dentry = HNS3_DBG_DENTRY_REG,
210 		.buf_len = HNS3_DBG_READ_LEN,
211 		.init = hns3_dbg_common_file_init,
212 	},
213 	{
214 		.name = "ssu",
215 		.cmd = HNAE3_DBG_CMD_REG_SSU,
216 		.dentry = HNS3_DBG_DENTRY_REG,
217 		.buf_len = HNS3_DBG_READ_LEN,
218 		.init = hns3_dbg_common_file_init,
219 	},
220 	{
221 		.name = "igu_egu",
222 		.cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
223 		.dentry = HNS3_DBG_DENTRY_REG,
224 		.buf_len = HNS3_DBG_READ_LEN,
225 		.init = hns3_dbg_common_file_init,
226 	},
227 	{
228 		.name = "rpu",
229 		.cmd = HNAE3_DBG_CMD_REG_RPU,
230 		.dentry = HNS3_DBG_DENTRY_REG,
231 		.buf_len = HNS3_DBG_READ_LEN,
232 		.init = hns3_dbg_common_file_init,
233 	},
234 	{
235 		.name = "ncsi",
236 		.cmd = HNAE3_DBG_CMD_REG_NCSI,
237 		.dentry = HNS3_DBG_DENTRY_REG,
238 		.buf_len = HNS3_DBG_READ_LEN,
239 		.init = hns3_dbg_common_file_init,
240 	},
241 	{
242 		.name = "rtc",
243 		.cmd = HNAE3_DBG_CMD_REG_RTC,
244 		.dentry = HNS3_DBG_DENTRY_REG,
245 		.buf_len = HNS3_DBG_READ_LEN,
246 		.init = hns3_dbg_common_file_init,
247 	},
248 	{
249 		.name = "ppp",
250 		.cmd = HNAE3_DBG_CMD_REG_PPP,
251 		.dentry = HNS3_DBG_DENTRY_REG,
252 		.buf_len = HNS3_DBG_READ_LEN,
253 		.init = hns3_dbg_common_file_init,
254 	},
255 	{
256 		.name = "rcb",
257 		.cmd = HNAE3_DBG_CMD_REG_RCB,
258 		.dentry = HNS3_DBG_DENTRY_REG,
259 		.buf_len = HNS3_DBG_READ_LEN,
260 		.init = hns3_dbg_common_file_init,
261 	},
262 	{
263 		.name = "tqp",
264 		.cmd = HNAE3_DBG_CMD_REG_TQP,
265 		.dentry = HNS3_DBG_DENTRY_REG,
266 		.buf_len = HNS3_DBG_READ_LEN_128KB,
267 		.init = hns3_dbg_common_file_init,
268 	},
269 	{
270 		.name = "mac",
271 		.cmd = HNAE3_DBG_CMD_REG_MAC,
272 		.dentry = HNS3_DBG_DENTRY_REG,
273 		.buf_len = HNS3_DBG_READ_LEN,
274 		.init = hns3_dbg_common_file_init,
275 	},
276 	{
277 		.name = "dcb",
278 		.cmd = HNAE3_DBG_CMD_REG_DCB,
279 		.dentry = HNS3_DBG_DENTRY_REG,
280 		.buf_len = HNS3_DBG_READ_LEN,
281 		.init = hns3_dbg_common_file_init,
282 	},
283 	{
284 		.name = "queue_map",
285 		.cmd = HNAE3_DBG_CMD_QUEUE_MAP,
286 		.dentry = HNS3_DBG_DENTRY_QUEUE,
287 		.buf_len = HNS3_DBG_READ_LEN,
288 		.init = hns3_dbg_common_file_init,
289 	},
290 	{
291 		.name = "rx_queue_info",
292 		.cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
293 		.dentry = HNS3_DBG_DENTRY_QUEUE,
294 		.buf_len = HNS3_DBG_READ_LEN_1MB,
295 		.init = hns3_dbg_common_file_init,
296 	},
297 	{
298 		.name = "tx_queue_info",
299 		.cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
300 		.dentry = HNS3_DBG_DENTRY_QUEUE,
301 		.buf_len = HNS3_DBG_READ_LEN_1MB,
302 		.init = hns3_dbg_common_file_init,
303 	},
304 	{
305 		.name = "fd_tcam",
306 		.cmd = HNAE3_DBG_CMD_FD_TCAM,
307 		.dentry = HNS3_DBG_DENTRY_FD,
308 		.buf_len = HNS3_DBG_READ_LEN_1MB,
309 		.init = hns3_dbg_common_file_init,
310 	},
311 	{
312 		.name = "service_task_info",
313 		.cmd = HNAE3_DBG_CMD_SERV_INFO,
314 		.dentry = HNS3_DBG_DENTRY_COMMON,
315 		.buf_len = HNS3_DBG_READ_LEN,
316 		.init = hns3_dbg_common_file_init,
317 	},
318 	{
319 		.name = "vlan_config",
320 		.cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
321 		.dentry = HNS3_DBG_DENTRY_COMMON,
322 		.buf_len = HNS3_DBG_READ_LEN,
323 		.init = hns3_dbg_common_file_init,
324 	},
325 	{
326 		.name = "ptp_info",
327 		.cmd = HNAE3_DBG_CMD_PTP_INFO,
328 		.dentry = HNS3_DBG_DENTRY_COMMON,
329 		.buf_len = HNS3_DBG_READ_LEN,
330 		.init = hns3_dbg_common_file_init,
331 	},
332 	{
333 		.name = "fd_counter",
334 		.cmd = HNAE3_DBG_CMD_FD_COUNTER,
335 		.dentry = HNS3_DBG_DENTRY_FD,
336 		.buf_len = HNS3_DBG_READ_LEN,
337 		.init = hns3_dbg_common_file_init,
338 	},
339 	{
340 		.name = "umv_info",
341 		.cmd = HNAE3_DBG_CMD_UMV_INFO,
342 		.dentry = HNS3_DBG_DENTRY_COMMON,
343 		.buf_len = HNS3_DBG_READ_LEN,
344 		.init = hns3_dbg_common_file_init,
345 	},
346 	{
347 		.name = "page_pool_info",
348 		.cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
349 		.dentry = HNS3_DBG_DENTRY_COMMON,
350 		.buf_len = HNS3_DBG_READ_LEN,
351 		.init = hns3_dbg_common_file_init,
352 	},
353 	{
354 		.name = "coalesce_info",
355 		.cmd = HNAE3_DBG_CMD_COAL_INFO,
356 		.dentry = HNS3_DBG_DENTRY_COMMON,
357 		.buf_len = HNS3_DBG_READ_LEN_1MB,
358 		.init = hns3_dbg_common_file_init,
359 	},
360 };
361 
362 static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
363 	{
364 		.name = "support FD",
365 		.cap_bit = HNAE3_DEV_SUPPORT_FD_B,
366 	}, {
367 		.name = "support GRO",
368 		.cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
369 	}, {
370 		.name = "support FEC",
371 		.cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
372 	}, {
373 		.name = "support UDP GSO",
374 		.cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
375 	}, {
376 		.name = "support PTP",
377 		.cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
378 	}, {
379 		.name = "support INT QL",
380 		.cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
381 	}, {
382 		.name = "support HW TX csum",
383 		.cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
384 	}, {
385 		.name = "support UDP tunnel csum",
386 		.cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
387 	}, {
388 		.name = "support TX push",
389 		.cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
390 	}, {
391 		.name = "support imp-controlled PHY",
392 		.cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
393 	}, {
394 		.name = "support imp-controlled RAS",
395 		.cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,
396 	}, {
397 		.name = "support rxd advanced layout",
398 		.cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
399 	}, {
400 		.name = "support port vlan bypass",
401 		.cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
402 	}, {
403 		.name = "support modify vlan filter state",
404 		.cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
405 	}, {
406 		.name = "support FEC statistics",
407 		.cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B,
408 	}, {
409 		.name = "support lane num",
410 		.cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B,
411 	}, {
412 		.name = "support wake on lan",
413 		.cap_bit = HNAE3_DEV_SUPPORT_WOL_B,
414 	}
415 };
416 
417 static const struct hns3_dbg_item coal_info_items[] = {
418 	{ "VEC_ID", 2 },
419 	{ "ALGO_STATE", 2 },
420 	{ "PROFILE_ID", 2 },
421 	{ "CQE_MODE", 2 },
422 	{ "TUNE_STATE", 2 },
423 	{ "STEPS_LEFT", 2 },
424 	{ "STEPS_RIGHT", 2 },
425 	{ "TIRED", 2 },
426 	{ "SW_GL", 2 },
427 	{ "SW_QL", 2 },
428 	{ "HW_GL", 2 },
429 	{ "HW_QL", 2 },
430 };
431 
432 static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" };
433 static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" };
434 static const char * const
435 dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" };
436 
437 static void hns3_dbg_fill_content(char *content, u16 len,
438 				  const struct hns3_dbg_item *items,
439 				  const char **result, u16 size)
440 {
441 #define HNS3_DBG_LINE_END_LEN	2
442 	char *pos = content;
443 	u16 item_len;
444 	u16 i;
445 
446 	if (!len) {
447 		return;
448 	} else if (len <= HNS3_DBG_LINE_END_LEN) {
449 		*pos++ = '\0';
450 		return;
451 	}
452 
453 	memset(content, ' ', len);
454 	len -= HNS3_DBG_LINE_END_LEN;
455 
456 	for (i = 0; i < size; i++) {
457 		item_len = strlen(items[i].name) + items[i].interval;
458 		if (len < item_len)
459 			break;
460 
461 		if (result) {
462 			if (item_len < strlen(result[i]))
463 				break;
464 			strscpy(pos, result[i], strlen(result[i]));
465 		} else {
466 			strscpy(pos, items[i].name, strlen(items[i].name));
467 		}
468 		pos += item_len;
469 		len -= item_len;
470 	}
471 	*pos++ = '\n';
472 	*pos++ = '\0';
473 }
474 
475 static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector,
476 			       char **result, int i, bool is_tx)
477 {
478 	unsigned int gl_offset, ql_offset;
479 	struct hns3_enet_coalesce *coal;
480 	unsigned int reg_val;
481 	unsigned int j = 0;
482 	struct dim *dim;
483 	bool ql_enable;
484 
485 	if (is_tx) {
486 		coal = &tqp_vector->tx_group.coal;
487 		dim = &tqp_vector->tx_group.dim;
488 		gl_offset = HNS3_VECTOR_GL1_OFFSET;
489 		ql_offset = HNS3_VECTOR_TX_QL_OFFSET;
490 		ql_enable = tqp_vector->tx_group.coal.ql_enable;
491 	} else {
492 		coal = &tqp_vector->rx_group.coal;
493 		dim = &tqp_vector->rx_group.dim;
494 		gl_offset = HNS3_VECTOR_GL0_OFFSET;
495 		ql_offset = HNS3_VECTOR_RX_QL_OFFSET;
496 		ql_enable = tqp_vector->rx_group.coal.ql_enable;
497 	}
498 
499 	sprintf(result[j++], "%d", i);
500 	sprintf(result[j++], "%s", dim_state_str[dim->state]);
501 	sprintf(result[j++], "%u", dim->profile_ix);
502 	sprintf(result[j++], "%s", dim_cqe_mode_str[dim->mode]);
503 	sprintf(result[j++], "%s",
504 		dim_tune_stat_str[dim->tune_state]);
505 	sprintf(result[j++], "%u", dim->steps_left);
506 	sprintf(result[j++], "%u", dim->steps_right);
507 	sprintf(result[j++], "%u", dim->tired);
508 	sprintf(result[j++], "%u", coal->int_gl);
509 	sprintf(result[j++], "%u", coal->int_ql);
510 	reg_val = readl(tqp_vector->mask_addr + gl_offset) &
511 		  HNS3_VECTOR_GL_MASK;
512 	sprintf(result[j++], "%u", reg_val);
513 	if (ql_enable) {
514 		reg_val = readl(tqp_vector->mask_addr + ql_offset) &
515 			  HNS3_VECTOR_QL_MASK;
516 		sprintf(result[j++], "%u", reg_val);
517 	} else {
518 		sprintf(result[j++], "NA");
519 	}
520 }
521 
522 static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len,
523 				int *pos, bool is_tx)
524 {
525 	char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN];
526 	char *result[ARRAY_SIZE(coal_info_items)];
527 	struct hns3_enet_tqp_vector *tqp_vector;
528 	struct hns3_nic_priv *priv = h->priv;
529 	char content[HNS3_DBG_INFO_LEN];
530 	unsigned int i;
531 
532 	for (i = 0; i < ARRAY_SIZE(coal_info_items); i++)
533 		result[i] = &data_str[i][0];
534 
535 	*pos += scnprintf(buf + *pos, len - *pos,
536 			  "%s interrupt coalesce info:\n",
537 			  is_tx ? "tx" : "rx");
538 	hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
539 			      NULL, ARRAY_SIZE(coal_info_items));
540 	*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
541 
542 	for (i = 0; i < priv->vector_num; i++) {
543 		tqp_vector = &priv->tqp_vector[i];
544 		hns3_get_coal_info(tqp_vector, result, i, is_tx);
545 		hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
546 				      (const char **)result,
547 				      ARRAY_SIZE(coal_info_items));
548 		*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
549 	}
550 }
551 
552 static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len)
553 {
554 	int pos = 0;
555 
556 	hns3_dump_coal_info(h, buf, len, &pos, true);
557 	pos += scnprintf(buf + pos, len - pos, "\n");
558 	hns3_dump_coal_info(h, buf, len, &pos, false);
559 
560 	return 0;
561 }
562 
563 static const struct hns3_dbg_item tx_spare_info_items[] = {
564 	{ "QUEUE_ID", 2 },
565 	{ "COPYBREAK", 2 },
566 	{ "LEN", 7 },
567 	{ "NTU", 4 },
568 	{ "NTC", 4 },
569 	{ "LTC", 4 },
570 	{ "DMA", 17 },
571 };
572 
573 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf,
574 				   int len, u32 ring_num, int *pos)
575 {
576 	char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN];
577 	struct hns3_tx_spare *tx_spare = ring->tx_spare;
578 	char *result[ARRAY_SIZE(tx_spare_info_items)];
579 	char content[HNS3_DBG_INFO_LEN];
580 	u32 i, j;
581 
582 	if (!tx_spare) {
583 		*pos += scnprintf(buf + *pos, len - *pos,
584 				  "tx spare buffer is not enabled\n");
585 		return;
586 	}
587 
588 	for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++)
589 		result[i] = &data_str[i][0];
590 
591 	*pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n");
592 	hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items,
593 			      NULL, ARRAY_SIZE(tx_spare_info_items));
594 	*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
595 
596 	for (i = 0; i < ring_num; i++) {
597 		j = 0;
598 		sprintf(result[j++], "%u", i);
599 		sprintf(result[j++], "%u", ring->tx_copybreak);
600 		sprintf(result[j++], "%u", tx_spare->len);
601 		sprintf(result[j++], "%u", tx_spare->next_to_use);
602 		sprintf(result[j++], "%u", tx_spare->next_to_clean);
603 		sprintf(result[j++], "%u", tx_spare->last_to_clean);
604 		sprintf(result[j++], "%pad", &tx_spare->dma);
605 		hns3_dbg_fill_content(content, sizeof(content),
606 				      tx_spare_info_items,
607 				      (const char **)result,
608 				      ARRAY_SIZE(tx_spare_info_items));
609 		*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
610 	}
611 }
612 
613 static const struct hns3_dbg_item rx_queue_info_items[] = {
614 	{ "QUEUE_ID", 2 },
615 	{ "BD_NUM", 2 },
616 	{ "BD_LEN", 2 },
617 	{ "TAIL", 2 },
618 	{ "HEAD", 2 },
619 	{ "FBDNUM", 2 },
620 	{ "PKTNUM", 5 },
621 	{ "COPYBREAK", 2 },
622 	{ "RING_EN", 2 },
623 	{ "RX_RING_EN", 2 },
624 	{ "BASE_ADDR", 10 },
625 };
626 
627 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
628 				    struct hnae3_ae_dev *ae_dev, char **result,
629 				    u32 index)
630 {
631 	u32 base_add_l, base_add_h;
632 	u32 j = 0;
633 
634 	sprintf(result[j++], "%u", index);
635 
636 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
637 		HNS3_RING_RX_RING_BD_NUM_REG));
638 
639 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
640 		HNS3_RING_RX_RING_BD_LEN_REG));
641 
642 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
643 		HNS3_RING_RX_RING_TAIL_REG));
644 
645 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
646 		HNS3_RING_RX_RING_HEAD_REG));
647 
648 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
649 		HNS3_RING_RX_RING_FBDNUM_REG));
650 
651 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
652 		HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
653 	sprintf(result[j++], "%u", ring->rx_copybreak);
654 
655 	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
656 		HNS3_RING_EN_REG) ? "on" : "off");
657 
658 	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
659 		sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
660 			HNS3_RING_RX_EN_REG) ? "on" : "off");
661 	else
662 		sprintf(result[j++], "%s", "NA");
663 
664 	base_add_h = readl_relaxed(ring->tqp->io_base +
665 					HNS3_RING_RX_RING_BASEADDR_H_REG);
666 	base_add_l = readl_relaxed(ring->tqp->io_base +
667 					HNS3_RING_RX_RING_BASEADDR_L_REG);
668 	sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
669 }
670 
671 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h,
672 				  char *buf, int len)
673 {
674 	char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
675 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
676 	char *result[ARRAY_SIZE(rx_queue_info_items)];
677 	struct hns3_nic_priv *priv = h->priv;
678 	char content[HNS3_DBG_INFO_LEN];
679 	struct hns3_enet_ring *ring;
680 	int pos = 0;
681 	u32 i;
682 
683 	if (!priv->ring) {
684 		dev_err(&h->pdev->dev, "priv->ring is NULL\n");
685 		return -EFAULT;
686 	}
687 
688 	for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++)
689 		result[i] = &data_str[i][0];
690 
691 	hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items,
692 			      NULL, ARRAY_SIZE(rx_queue_info_items));
693 	pos += scnprintf(buf + pos, len - pos, "%s", content);
694 	for (i = 0; i < h->kinfo.num_tqps; i++) {
695 		/* Each cycle needs to determine whether the instance is reset,
696 		 * to prevent reference to invalid memory. And need to ensure
697 		 * that the following code is executed within 100ms.
698 		 */
699 		if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
700 		    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
701 			return -EPERM;
702 
703 		ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
704 		hns3_dump_rx_queue_info(ring, ae_dev, result, i);
705 		hns3_dbg_fill_content(content, sizeof(content),
706 				      rx_queue_info_items,
707 				      (const char **)result,
708 				      ARRAY_SIZE(rx_queue_info_items));
709 		pos += scnprintf(buf + pos, len - pos, "%s", content);
710 	}
711 
712 	return 0;
713 }
714 
715 static const struct hns3_dbg_item tx_queue_info_items[] = {
716 	{ "QUEUE_ID", 2 },
717 	{ "BD_NUM", 2 },
718 	{ "TC", 2 },
719 	{ "TAIL", 2 },
720 	{ "HEAD", 2 },
721 	{ "FBDNUM", 2 },
722 	{ "OFFSET", 2 },
723 	{ "PKTNUM", 5 },
724 	{ "RING_EN", 2 },
725 	{ "TX_RING_EN", 2 },
726 	{ "BASE_ADDR", 10 },
727 };
728 
729 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring,
730 				    struct hnae3_ae_dev *ae_dev, char **result,
731 				    u32 index)
732 {
733 	u32 base_add_l, base_add_h;
734 	u32 j = 0;
735 
736 	sprintf(result[j++], "%u", index);
737 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
738 		HNS3_RING_TX_RING_BD_NUM_REG));
739 
740 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
741 		HNS3_RING_TX_RING_TC_REG));
742 
743 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
744 		HNS3_RING_TX_RING_TAIL_REG));
745 
746 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
747 		HNS3_RING_TX_RING_HEAD_REG));
748 
749 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
750 		HNS3_RING_TX_RING_FBDNUM_REG));
751 
752 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
753 		HNS3_RING_TX_RING_OFFSET_REG));
754 
755 	sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
756 		HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
757 
758 	sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
759 		HNS3_RING_EN_REG) ? "on" : "off");
760 
761 	if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
762 		sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
763 			HNS3_RING_TX_EN_REG) ? "on" : "off");
764 	else
765 		sprintf(result[j++], "%s", "NA");
766 
767 	base_add_h = readl_relaxed(ring->tqp->io_base +
768 					HNS3_RING_TX_RING_BASEADDR_H_REG);
769 	base_add_l = readl_relaxed(ring->tqp->io_base +
770 					HNS3_RING_TX_RING_BASEADDR_L_REG);
771 	sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
772 }
773 
774 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
775 				  char *buf, int len)
776 {
777 	char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
778 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
779 	char *result[ARRAY_SIZE(tx_queue_info_items)];
780 	struct hns3_nic_priv *priv = h->priv;
781 	char content[HNS3_DBG_INFO_LEN];
782 	struct hns3_enet_ring *ring;
783 	int pos = 0;
784 	u32 i;
785 
786 	if (!priv->ring) {
787 		dev_err(&h->pdev->dev, "priv->ring is NULL\n");
788 		return -EFAULT;
789 	}
790 
791 	for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++)
792 		result[i] = &data_str[i][0];
793 
794 	hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items,
795 			      NULL, ARRAY_SIZE(tx_queue_info_items));
796 	pos += scnprintf(buf + pos, len - pos, "%s", content);
797 
798 	for (i = 0; i < h->kinfo.num_tqps; i++) {
799 		/* Each cycle needs to determine whether the instance is reset,
800 		 * to prevent reference to invalid memory. And need to ensure
801 		 * that the following code is executed within 100ms.
802 		 */
803 		if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
804 		    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
805 			return -EPERM;
806 
807 		ring = &priv->ring[i];
808 		hns3_dump_tx_queue_info(ring, ae_dev, result, i);
809 		hns3_dbg_fill_content(content, sizeof(content),
810 				      tx_queue_info_items,
811 				      (const char **)result,
812 				      ARRAY_SIZE(tx_queue_info_items));
813 		pos += scnprintf(buf + pos, len - pos, "%s", content);
814 	}
815 
816 	hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos);
817 
818 	return 0;
819 }
820 
821 static const struct hns3_dbg_item queue_map_items[] = {
822 	{ "local_queue_id", 2 },
823 	{ "global_queue_id", 2 },
824 	{ "vector_id", 2 },
825 };
826 
827 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
828 {
829 	char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN];
830 	char *result[ARRAY_SIZE(queue_map_items)];
831 	struct hns3_nic_priv *priv = h->priv;
832 	char content[HNS3_DBG_INFO_LEN];
833 	int pos = 0;
834 	int j;
835 	u32 i;
836 
837 	if (!h->ae_algo->ops->get_global_queue_id)
838 		return -EOPNOTSUPP;
839 
840 	for (i = 0; i < ARRAY_SIZE(queue_map_items); i++)
841 		result[i] = &data_str[i][0];
842 
843 	hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
844 			      NULL, ARRAY_SIZE(queue_map_items));
845 	pos += scnprintf(buf + pos, len - pos, "%s", content);
846 	for (i = 0; i < h->kinfo.num_tqps; i++) {
847 		if (!priv->ring || !priv->ring[i].tqp_vector)
848 			continue;
849 		j = 0;
850 		sprintf(result[j++], "%u", i);
851 		sprintf(result[j++], "%u",
852 			h->ae_algo->ops->get_global_queue_id(h, i));
853 		sprintf(result[j++], "%d",
854 			priv->ring[i].tqp_vector->vector_irq);
855 		hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
856 				      (const char **)result,
857 				      ARRAY_SIZE(queue_map_items));
858 		pos += scnprintf(buf + pos, len - pos, "%s", content);
859 	}
860 
861 	return 0;
862 }
863 
864 static const struct hns3_dbg_item rx_bd_info_items[] = {
865 	{ "BD_IDX", 3 },
866 	{ "L234_INFO", 2 },
867 	{ "PKT_LEN", 3 },
868 	{ "SIZE", 4 },
869 	{ "RSS_HASH", 4 },
870 	{ "FD_ID", 2 },
871 	{ "VLAN_TAG", 2 },
872 	{ "O_DM_VLAN_ID_FB", 2 },
873 	{ "OT_VLAN_TAG", 2 },
874 	{ "BD_BASE_INFO", 2 },
875 	{ "PTYPE", 2 },
876 	{ "HW_CSUM", 2 },
877 };
878 
879 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv,
880 				 struct hns3_desc *desc, char **result, int idx)
881 {
882 	unsigned int j = 0;
883 
884 	sprintf(result[j++], "%d", idx);
885 	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));
886 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len));
887 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size));
888 	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));
889 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id));
890 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag));
891 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));
892 	sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag));
893 	sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));
894 	if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
895 		u32 ol_info = le32_to_cpu(desc->rx.ol_info);
896 
897 		sprintf(result[j++], "%5lu", hnae3_get_field(ol_info,
898 							     HNS3_RXD_PTYPE_M,
899 							     HNS3_RXD_PTYPE_S));
900 		sprintf(result[j++], "%7u", le16_to_cpu(desc->csum));
901 	} else {
902 		sprintf(result[j++], "NA");
903 		sprintf(result[j++], "NA");
904 	}
905 }
906 
907 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
908 {
909 	char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
910 	struct hns3_nic_priv *priv = d->handle->priv;
911 	char *result[ARRAY_SIZE(rx_bd_info_items)];
912 	char content[HNS3_DBG_INFO_LEN];
913 	struct hns3_enet_ring *ring;
914 	struct hns3_desc *desc;
915 	unsigned int i;
916 	int pos = 0;
917 
918 	if (d->qid >= d->handle->kinfo.num_tqps) {
919 		dev_err(&d->handle->pdev->dev,
920 			"queue%u is not in use\n", d->qid);
921 		return -EINVAL;
922 	}
923 
924 	for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++)
925 		result[i] = &data_str[i][0];
926 
927 	pos += scnprintf(buf + pos, len - pos,
928 			  "Queue %u rx bd info:\n", d->qid);
929 	hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items,
930 			      NULL, ARRAY_SIZE(rx_bd_info_items));
931 	pos += scnprintf(buf + pos, len - pos, "%s", content);
932 
933 	ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps];
934 	for (i = 0; i < ring->desc_num; i++) {
935 		desc = &ring->desc[i];
936 
937 		hns3_dump_rx_bd_info(priv, desc, result, i);
938 		hns3_dbg_fill_content(content, sizeof(content),
939 				      rx_bd_info_items, (const char **)result,
940 				      ARRAY_SIZE(rx_bd_info_items));
941 		pos += scnprintf(buf + pos, len - pos, "%s", content);
942 	}
943 
944 	return 0;
945 }
946 
947 static const struct hns3_dbg_item tx_bd_info_items[] = {
948 	{ "BD_IDX", 2 },
949 	{ "ADDRESS", 13 },
950 	{ "VLAN_TAG", 2 },
951 	{ "SIZE", 2 },
952 	{ "T_CS_VLAN_TSO", 2 },
953 	{ "OT_VLAN_TAG", 3 },
954 	{ "TV", 5 },
955 	{ "OLT_VLAN_LEN", 2 },
956 	{ "PAYLEN_OL4CS", 2 },
957 	{ "BD_FE_SC_VLD", 2 },
958 	{ "MSS_HW_CSUM", 0 },
959 };
960 
961 static void hns3_dump_tx_bd_info(struct hns3_desc *desc, char **result, int idx)
962 {
963 	unsigned int j = 0;
964 
965 	sprintf(result[j++], "%d", idx);
966 	sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));
967 	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag));
968 	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size));
969 	sprintf(result[j++], "%#x",
970 		le32_to_cpu(desc->tx.type_cs_vlan_tso_len));
971 	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag));
972 	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv));
973 	sprintf(result[j++], "%u",
974 		le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
975 	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));
976 	sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
977 	sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum));
978 }
979 
980 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
981 {
982 	char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
983 	struct hns3_nic_priv *priv = d->handle->priv;
984 	char *result[ARRAY_SIZE(tx_bd_info_items)];
985 	char content[HNS3_DBG_INFO_LEN];
986 	struct hns3_enet_ring *ring;
987 	struct hns3_desc *desc;
988 	unsigned int i;
989 	int pos = 0;
990 
991 	if (d->qid >= d->handle->kinfo.num_tqps) {
992 		dev_err(&d->handle->pdev->dev,
993 			"queue%u is not in use\n", d->qid);
994 		return -EINVAL;
995 	}
996 
997 	for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++)
998 		result[i] = &data_str[i][0];
999 
1000 	pos += scnprintf(buf + pos, len - pos,
1001 			  "Queue %u tx bd info:\n", d->qid);
1002 	hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items,
1003 			      NULL, ARRAY_SIZE(tx_bd_info_items));
1004 	pos += scnprintf(buf + pos, len - pos, "%s", content);
1005 
1006 	ring = &priv->ring[d->qid];
1007 	for (i = 0; i < ring->desc_num; i++) {
1008 		desc = &ring->desc[i];
1009 
1010 		hns3_dump_tx_bd_info(desc, result, i);
1011 		hns3_dbg_fill_content(content, sizeof(content),
1012 				      tx_bd_info_items, (const char **)result,
1013 				      ARRAY_SIZE(tx_bd_info_items));
1014 		pos += scnprintf(buf + pos, len - pos, "%s", content);
1015 	}
1016 
1017 	return 0;
1018 }
1019 
1020 static void
1021 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
1022 {
1023 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1024 	const char * const str[] = {"no", "yes"};
1025 	unsigned long *caps = ae_dev->caps;
1026 	u32 i, state;
1027 
1028 	*pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
1029 
1030 	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
1031 		state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
1032 		*pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
1033 				  hns3_dbg_cap[i].name, str[state]);
1034 	}
1035 
1036 	*pos += scnprintf(buf + *pos, len - *pos, "\n");
1037 }
1038 
1039 static void
1040 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
1041 {
1042 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1043 	struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
1044 	struct hnae3_knic_private_info *kinfo = &h->kinfo;
1045 
1046 	*pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
1047 	*pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
1048 			  dev_specs->mac_entry_num);
1049 	*pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
1050 			  dev_specs->mng_entry_num);
1051 	*pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
1052 			  dev_specs->max_non_tso_bd_num);
1053 	*pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
1054 			  dev_specs->rss_ind_tbl_size);
1055 	*pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
1056 			  dev_specs->rss_key_size);
1057 	*pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
1058 			  kinfo->rss_size);
1059 	*pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
1060 			  kinfo->req_rss_size);
1061 	*pos += scnprintf(buf + *pos, len - *pos,
1062 			  "Task queue pairs numbers: %u\n",
1063 			  kinfo->num_tqps);
1064 	*pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
1065 			  kinfo->rx_buf_len);
1066 	*pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
1067 			  kinfo->num_tx_desc);
1068 	*pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
1069 			  kinfo->num_rx_desc);
1070 	*pos += scnprintf(buf + *pos, len - *pos,
1071 			  "Total number of enabled TCs: %u\n",
1072 			  kinfo->tc_info.num_tc);
1073 	*pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
1074 			  dev_specs->int_ql_max);
1075 	*pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
1076 			  dev_specs->max_int_gl);
1077 	*pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
1078 			  dev_specs->max_tm_rate);
1079 	*pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
1080 			  dev_specs->max_qset_num);
1081 	*pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n",
1082 			  dev_specs->umv_size);
1083 	*pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n",
1084 			  dev_specs->mc_mac_size);
1085 	*pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n",
1086 			  dev_specs->mac_stats_num);
1087 }
1088 
1089 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
1090 {
1091 	int pos = 0;
1092 
1093 	hns3_dbg_dev_caps(h, buf, len, &pos);
1094 
1095 	hns3_dbg_dev_specs(h, buf, len, &pos);
1096 
1097 	return 0;
1098 }
1099 
1100 static const struct hns3_dbg_item page_pool_info_items[] = {
1101 	{ "QUEUE_ID", 2 },
1102 	{ "ALLOCATE_CNT", 2 },
1103 	{ "FREE_CNT", 6 },
1104 	{ "POOL_SIZE(PAGE_NUM)", 2 },
1105 	{ "ORDER", 2 },
1106 	{ "NUMA_ID", 2 },
1107 	{ "MAX_LEN", 2 },
1108 };
1109 
1110 static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring,
1111 				     char **result, u32 index)
1112 {
1113 	u32 j = 0;
1114 
1115 	sprintf(result[j++], "%u", index);
1116 	sprintf(result[j++], "%u",
1117 		READ_ONCE(ring->page_pool->pages_state_hold_cnt));
1118 	sprintf(result[j++], "%d",
1119 		atomic_read(&ring->page_pool->pages_state_release_cnt));
1120 	sprintf(result[j++], "%u", ring->page_pool->p.pool_size);
1121 	sprintf(result[j++], "%u", ring->page_pool->p.order);
1122 	sprintf(result[j++], "%d", ring->page_pool->p.nid);
1123 	sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024);
1124 }
1125 
1126 static int
1127 hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len)
1128 {
1129 	char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN];
1130 	char *result[ARRAY_SIZE(page_pool_info_items)];
1131 	struct hns3_nic_priv *priv = h->priv;
1132 	char content[HNS3_DBG_INFO_LEN];
1133 	struct hns3_enet_ring *ring;
1134 	int pos = 0;
1135 	u32 i;
1136 
1137 	if (!priv->ring) {
1138 		dev_err(&h->pdev->dev, "priv->ring is NULL\n");
1139 		return -EFAULT;
1140 	}
1141 
1142 	if (!priv->ring[h->kinfo.num_tqps].page_pool) {
1143 		dev_err(&h->pdev->dev, "page pool is not initialized\n");
1144 		return -EFAULT;
1145 	}
1146 
1147 	for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++)
1148 		result[i] = &data_str[i][0];
1149 
1150 	hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items,
1151 			      NULL, ARRAY_SIZE(page_pool_info_items));
1152 	pos += scnprintf(buf + pos, len - pos, "%s", content);
1153 	for (i = 0; i < h->kinfo.num_tqps; i++) {
1154 		if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1155 		    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
1156 			return -EPERM;
1157 		ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
1158 		hns3_dump_page_pool_info(ring, result, i);
1159 		hns3_dbg_fill_content(content, sizeof(content),
1160 				      page_pool_info_items,
1161 				      (const char **)result,
1162 				      ARRAY_SIZE(page_pool_info_items));
1163 		pos += scnprintf(buf + pos, len - pos, "%s", content);
1164 	}
1165 
1166 	return 0;
1167 }
1168 
1169 static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index)
1170 {
1171 	u32 i;
1172 
1173 	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1174 		if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) {
1175 			*index = i;
1176 			return 0;
1177 		}
1178 	}
1179 
1180 	dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n",
1181 		dbg_data->cmd);
1182 	return -EINVAL;
1183 }
1184 
1185 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
1186 	{
1187 		.cmd = HNAE3_DBG_CMD_QUEUE_MAP,
1188 		.dbg_dump = hns3_dbg_queue_map,
1189 	},
1190 	{
1191 		.cmd = HNAE3_DBG_CMD_DEV_INFO,
1192 		.dbg_dump = hns3_dbg_dev_info,
1193 	},
1194 	{
1195 		.cmd = HNAE3_DBG_CMD_TX_BD,
1196 		.dbg_dump_bd = hns3_dbg_tx_bd_info,
1197 	},
1198 	{
1199 		.cmd = HNAE3_DBG_CMD_RX_BD,
1200 		.dbg_dump_bd = hns3_dbg_rx_bd_info,
1201 	},
1202 	{
1203 		.cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
1204 		.dbg_dump = hns3_dbg_rx_queue_info,
1205 	},
1206 	{
1207 		.cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
1208 		.dbg_dump = hns3_dbg_tx_queue_info,
1209 	},
1210 	{
1211 		.cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
1212 		.dbg_dump = hns3_dbg_page_pool_info,
1213 	},
1214 	{
1215 		.cmd = HNAE3_DBG_CMD_COAL_INFO,
1216 		.dbg_dump = hns3_dbg_coal_info,
1217 	},
1218 };
1219 
1220 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
1221 			     enum hnae3_dbg_cmd cmd, char *buf, int len)
1222 {
1223 	const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops;
1224 	const struct hns3_dbg_func *cmd_func;
1225 	u32 i;
1226 
1227 	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) {
1228 		if (cmd == hns3_dbg_cmd_func[i].cmd) {
1229 			cmd_func = &hns3_dbg_cmd_func[i];
1230 			if (cmd_func->dbg_dump)
1231 				return cmd_func->dbg_dump(dbg_data->handle, buf,
1232 							  len);
1233 			else
1234 				return cmd_func->dbg_dump_bd(dbg_data, buf,
1235 							     len);
1236 		}
1237 	}
1238 
1239 	if (!ops->dbg_read_cmd)
1240 		return -EOPNOTSUPP;
1241 
1242 	return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len);
1243 }
1244 
1245 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
1246 			     size_t count, loff_t *ppos)
1247 {
1248 	struct hns3_dbg_data *dbg_data = filp->private_data;
1249 	struct hnae3_handle *handle = dbg_data->handle;
1250 	struct hns3_nic_priv *priv = handle->priv;
1251 	ssize_t size = 0;
1252 	char **save_buf;
1253 	char *read_buf;
1254 	u32 index;
1255 	int ret;
1256 
1257 	ret = hns3_dbg_get_cmd_index(dbg_data, &index);
1258 	if (ret)
1259 		return ret;
1260 
1261 	mutex_lock(&handle->dbgfs_lock);
1262 	save_buf = &handle->dbgfs_buf[index];
1263 
1264 	if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1265 	    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
1266 		ret = -EBUSY;
1267 		goto out;
1268 	}
1269 
1270 	if (*save_buf) {
1271 		read_buf = *save_buf;
1272 	} else {
1273 		read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
1274 		if (!read_buf) {
1275 			ret = -ENOMEM;
1276 			goto out;
1277 		}
1278 
1279 		/* save the buffer addr until the last read operation */
1280 		*save_buf = read_buf;
1281 
1282 		/* get data ready for the first time to read */
1283 		ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
1284 					read_buf, hns3_dbg_cmd[index].buf_len);
1285 		if (ret)
1286 			goto out;
1287 	}
1288 
1289 	size = simple_read_from_buffer(buffer, count, ppos, read_buf,
1290 				       strlen(read_buf));
1291 	if (size > 0) {
1292 		mutex_unlock(&handle->dbgfs_lock);
1293 		return size;
1294 	}
1295 
1296 out:
1297 	/* free the buffer for the last read operation */
1298 	if (*save_buf) {
1299 		kvfree(*save_buf);
1300 		*save_buf = NULL;
1301 	}
1302 
1303 	mutex_unlock(&handle->dbgfs_lock);
1304 	return ret;
1305 }
1306 
1307 static const struct file_operations hns3_dbg_fops = {
1308 	.owner = THIS_MODULE,
1309 	.open  = simple_open,
1310 	.read  = hns3_dbg_read,
1311 };
1312 
1313 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd)
1314 {
1315 	struct dentry *entry_dir;
1316 	struct hns3_dbg_data *data;
1317 	u16 max_queue_num;
1318 	unsigned int i;
1319 
1320 	entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1321 	max_queue_num = hns3_get_max_available_channels(handle);
1322 	data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data),
1323 			    GFP_KERNEL);
1324 	if (!data)
1325 		return -ENOMEM;
1326 
1327 	for (i = 0; i < max_queue_num; i++) {
1328 		char name[HNS3_DBG_FILE_NAME_LEN];
1329 
1330 		data[i].handle = handle;
1331 		data[i].cmd = hns3_dbg_cmd[cmd].cmd;
1332 		data[i].qid = i;
1333 		sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i);
1334 		debugfs_create_file(name, 0400, entry_dir, &data[i],
1335 				    &hns3_dbg_fops);
1336 	}
1337 
1338 	return 0;
1339 }
1340 
1341 static int
1342 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd)
1343 {
1344 	struct hns3_dbg_data *data;
1345 	struct dentry *entry_dir;
1346 
1347 	data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL);
1348 	if (!data)
1349 		return -ENOMEM;
1350 
1351 	data->handle = handle;
1352 	data->cmd = hns3_dbg_cmd[cmd].cmd;
1353 	entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1354 	debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir,
1355 			    data, &hns3_dbg_fops);
1356 
1357 	return 0;
1358 }
1359 
1360 int hns3_dbg_init(struct hnae3_handle *handle)
1361 {
1362 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1363 	const char *name = pci_name(handle->pdev);
1364 	int ret;
1365 	u32 i;
1366 
1367 	handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev,
1368 					 ARRAY_SIZE(hns3_dbg_cmd),
1369 					 sizeof(*handle->dbgfs_buf),
1370 					 GFP_KERNEL);
1371 	if (!handle->dbgfs_buf)
1372 		return -ENOMEM;
1373 
1374 	hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry =
1375 				debugfs_create_dir(name, hns3_dbgfs_root);
1376 	handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
1377 
1378 	for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++)
1379 		hns3_dbg_dentry[i].dentry =
1380 			debugfs_create_dir(hns3_dbg_dentry[i].name,
1381 					   handle->hnae3_dbgfs);
1382 
1383 	mutex_init(&handle->dbgfs_lock);
1384 
1385 	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1386 		if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES &&
1387 		     ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) ||
1388 		    (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO &&
1389 		     !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)))
1390 			continue;
1391 
1392 		if (!hns3_dbg_cmd[i].init) {
1393 			dev_err(&handle->pdev->dev,
1394 				"cmd %s lack of init func\n",
1395 				hns3_dbg_cmd[i].name);
1396 			ret = -EINVAL;
1397 			goto out;
1398 		}
1399 
1400 		ret = hns3_dbg_cmd[i].init(handle, i);
1401 		if (ret) {
1402 			dev_err(&handle->pdev->dev, "failed to init cmd %s\n",
1403 				hns3_dbg_cmd[i].name);
1404 			goto out;
1405 		}
1406 	}
1407 
1408 	return 0;
1409 
1410 out:
1411 	mutex_destroy(&handle->dbgfs_lock);
1412 	debugfs_remove_recursive(handle->hnae3_dbgfs);
1413 	handle->hnae3_dbgfs = NULL;
1414 	return ret;
1415 }
1416 
1417 void hns3_dbg_uninit(struct hnae3_handle *handle)
1418 {
1419 	u32 i;
1420 
1421 	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++)
1422 		if (handle->dbgfs_buf[i]) {
1423 			kvfree(handle->dbgfs_buf[i]);
1424 			handle->dbgfs_buf[i] = NULL;
1425 		}
1426 
1427 	mutex_destroy(&handle->dbgfs_lock);
1428 	debugfs_remove_recursive(handle->hnae3_dbgfs);
1429 	handle->hnae3_dbgfs = NULL;
1430 }
1431 
1432 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
1433 {
1434 	hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1435 }
1436 
1437 void hns3_dbg_unregister_debugfs(void)
1438 {
1439 	debugfs_remove_recursive(hns3_dbgfs_root);
1440 	hns3_dbgfs_root = NULL;
1441 }
1442