1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 7 #include "hnae3.h" 8 #include "hns3_debugfs.h" 9 #include "hns3_enet.h" 10 11 static struct dentry *hns3_dbgfs_root; 12 13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 14 { 15 .name = "tm" 16 }, 17 { 18 .name = "tx_bd_info" 19 }, 20 { 21 .name = "rx_bd_info" 22 }, 23 { 24 .name = "mac_list" 25 }, 26 { 27 .name = "reg" 28 }, 29 { 30 .name = "queue" 31 }, 32 { 33 .name = "fd" 34 }, 35 /* keep common at the bottom and add new directory above */ 36 { 37 .name = "common" 38 }, 39 }; 40 41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd); 42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, 43 unsigned int cmd); 44 45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 46 { 47 .name = "tm_nodes", 48 .cmd = HNAE3_DBG_CMD_TM_NODES, 49 .dentry = HNS3_DBG_DENTRY_TM, 50 .buf_len = HNS3_DBG_READ_LEN, 51 .init = hns3_dbg_common_file_init, 52 }, 53 { 54 .name = "tm_priority", 55 .cmd = HNAE3_DBG_CMD_TM_PRI, 56 .dentry = HNS3_DBG_DENTRY_TM, 57 .buf_len = HNS3_DBG_READ_LEN, 58 .init = hns3_dbg_common_file_init, 59 }, 60 { 61 .name = "tm_qset", 62 .cmd = HNAE3_DBG_CMD_TM_QSET, 63 .dentry = HNS3_DBG_DENTRY_TM, 64 .buf_len = HNS3_DBG_READ_LEN, 65 .init = hns3_dbg_common_file_init, 66 }, 67 { 68 .name = "tm_map", 69 .cmd = HNAE3_DBG_CMD_TM_MAP, 70 .dentry = HNS3_DBG_DENTRY_TM, 71 .buf_len = HNS3_DBG_READ_LEN_1MB, 72 .init = hns3_dbg_common_file_init, 73 }, 74 { 75 .name = "tm_pg", 76 .cmd = HNAE3_DBG_CMD_TM_PG, 77 .dentry = HNS3_DBG_DENTRY_TM, 78 .buf_len = HNS3_DBG_READ_LEN, 79 .init = hns3_dbg_common_file_init, 80 }, 81 { 82 .name = "tm_port", 83 .cmd = HNAE3_DBG_CMD_TM_PORT, 84 .dentry = HNS3_DBG_DENTRY_TM, 85 .buf_len = HNS3_DBG_READ_LEN, 86 .init = hns3_dbg_common_file_init, 87 }, 88 { 89 .name = "tc_sch_info", 90 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 91 .dentry = HNS3_DBG_DENTRY_TM, 92 .buf_len = HNS3_DBG_READ_LEN, 93 .init = hns3_dbg_common_file_init, 94 }, 95 { 96 .name = "qos_pause_cfg", 97 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 98 .dentry = HNS3_DBG_DENTRY_TM, 99 .buf_len = HNS3_DBG_READ_LEN, 100 .init = hns3_dbg_common_file_init, 101 }, 102 { 103 .name = "qos_pri_map", 104 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 105 .dentry = HNS3_DBG_DENTRY_TM, 106 .buf_len = HNS3_DBG_READ_LEN, 107 .init = hns3_dbg_common_file_init, 108 }, 109 { 110 .name = "qos_buf_cfg", 111 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 112 .dentry = HNS3_DBG_DENTRY_TM, 113 .buf_len = HNS3_DBG_READ_LEN, 114 .init = hns3_dbg_common_file_init, 115 }, 116 { 117 .name = "dev_info", 118 .cmd = HNAE3_DBG_CMD_DEV_INFO, 119 .dentry = HNS3_DBG_DENTRY_COMMON, 120 .buf_len = HNS3_DBG_READ_LEN, 121 .init = hns3_dbg_common_file_init, 122 }, 123 { 124 .name = "tx_bd_queue", 125 .cmd = HNAE3_DBG_CMD_TX_BD, 126 .dentry = HNS3_DBG_DENTRY_TX_BD, 127 .buf_len = HNS3_DBG_READ_LEN_4MB, 128 .init = hns3_dbg_bd_file_init, 129 }, 130 { 131 .name = "rx_bd_queue", 132 .cmd = HNAE3_DBG_CMD_RX_BD, 133 .dentry = HNS3_DBG_DENTRY_RX_BD, 134 .buf_len = HNS3_DBG_READ_LEN_4MB, 135 .init = hns3_dbg_bd_file_init, 136 }, 137 { 138 .name = "uc", 139 .cmd = HNAE3_DBG_CMD_MAC_UC, 140 .dentry = HNS3_DBG_DENTRY_MAC, 141 .buf_len = HNS3_DBG_READ_LEN, 142 .init = hns3_dbg_common_file_init, 143 }, 144 { 145 .name = "mc", 146 .cmd = HNAE3_DBG_CMD_MAC_MC, 147 .dentry = HNS3_DBG_DENTRY_MAC, 148 .buf_len = HNS3_DBG_READ_LEN, 149 .init = hns3_dbg_common_file_init, 150 }, 151 { 152 .name = "mng_tbl", 153 .cmd = HNAE3_DBG_CMD_MNG_TBL, 154 .dentry = HNS3_DBG_DENTRY_COMMON, 155 .buf_len = HNS3_DBG_READ_LEN, 156 .init = hns3_dbg_common_file_init, 157 }, 158 { 159 .name = "loopback", 160 .cmd = HNAE3_DBG_CMD_LOOPBACK, 161 .dentry = HNS3_DBG_DENTRY_COMMON, 162 .buf_len = HNS3_DBG_READ_LEN, 163 .init = hns3_dbg_common_file_init, 164 }, 165 { 166 .name = "interrupt_info", 167 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 168 .dentry = HNS3_DBG_DENTRY_COMMON, 169 .buf_len = HNS3_DBG_READ_LEN, 170 .init = hns3_dbg_common_file_init, 171 }, 172 { 173 .name = "reset_info", 174 .cmd = HNAE3_DBG_CMD_RESET_INFO, 175 .dentry = HNS3_DBG_DENTRY_COMMON, 176 .buf_len = HNS3_DBG_READ_LEN, 177 .init = hns3_dbg_common_file_init, 178 }, 179 { 180 .name = "imp_info", 181 .cmd = HNAE3_DBG_CMD_IMP_INFO, 182 .dentry = HNS3_DBG_DENTRY_COMMON, 183 .buf_len = HNS3_DBG_READ_LEN, 184 .init = hns3_dbg_common_file_init, 185 }, 186 { 187 .name = "ncl_config", 188 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 189 .dentry = HNS3_DBG_DENTRY_COMMON, 190 .buf_len = HNS3_DBG_READ_LEN_128KB, 191 .init = hns3_dbg_common_file_init, 192 }, 193 { 194 .name = "mac_tnl_status", 195 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 196 .dentry = HNS3_DBG_DENTRY_COMMON, 197 .buf_len = HNS3_DBG_READ_LEN, 198 .init = hns3_dbg_common_file_init, 199 }, 200 { 201 .name = "bios_common", 202 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 203 .dentry = HNS3_DBG_DENTRY_REG, 204 .buf_len = HNS3_DBG_READ_LEN, 205 .init = hns3_dbg_common_file_init, 206 }, 207 { 208 .name = "ssu", 209 .cmd = HNAE3_DBG_CMD_REG_SSU, 210 .dentry = HNS3_DBG_DENTRY_REG, 211 .buf_len = HNS3_DBG_READ_LEN, 212 .init = hns3_dbg_common_file_init, 213 }, 214 { 215 .name = "igu_egu", 216 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 217 .dentry = HNS3_DBG_DENTRY_REG, 218 .buf_len = HNS3_DBG_READ_LEN, 219 .init = hns3_dbg_common_file_init, 220 }, 221 { 222 .name = "rpu", 223 .cmd = HNAE3_DBG_CMD_REG_RPU, 224 .dentry = HNS3_DBG_DENTRY_REG, 225 .buf_len = HNS3_DBG_READ_LEN, 226 .init = hns3_dbg_common_file_init, 227 }, 228 { 229 .name = "ncsi", 230 .cmd = HNAE3_DBG_CMD_REG_NCSI, 231 .dentry = HNS3_DBG_DENTRY_REG, 232 .buf_len = HNS3_DBG_READ_LEN, 233 .init = hns3_dbg_common_file_init, 234 }, 235 { 236 .name = "rtc", 237 .cmd = HNAE3_DBG_CMD_REG_RTC, 238 .dentry = HNS3_DBG_DENTRY_REG, 239 .buf_len = HNS3_DBG_READ_LEN, 240 .init = hns3_dbg_common_file_init, 241 }, 242 { 243 .name = "ppp", 244 .cmd = HNAE3_DBG_CMD_REG_PPP, 245 .dentry = HNS3_DBG_DENTRY_REG, 246 .buf_len = HNS3_DBG_READ_LEN, 247 .init = hns3_dbg_common_file_init, 248 }, 249 { 250 .name = "rcb", 251 .cmd = HNAE3_DBG_CMD_REG_RCB, 252 .dentry = HNS3_DBG_DENTRY_REG, 253 .buf_len = HNS3_DBG_READ_LEN, 254 .init = hns3_dbg_common_file_init, 255 }, 256 { 257 .name = "tqp", 258 .cmd = HNAE3_DBG_CMD_REG_TQP, 259 .dentry = HNS3_DBG_DENTRY_REG, 260 .buf_len = HNS3_DBG_READ_LEN, 261 .init = hns3_dbg_common_file_init, 262 }, 263 { 264 .name = "mac", 265 .cmd = HNAE3_DBG_CMD_REG_MAC, 266 .dentry = HNS3_DBG_DENTRY_REG, 267 .buf_len = HNS3_DBG_READ_LEN, 268 .init = hns3_dbg_common_file_init, 269 }, 270 { 271 .name = "dcb", 272 .cmd = HNAE3_DBG_CMD_REG_DCB, 273 .dentry = HNS3_DBG_DENTRY_REG, 274 .buf_len = HNS3_DBG_READ_LEN, 275 .init = hns3_dbg_common_file_init, 276 }, 277 { 278 .name = "queue_map", 279 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 280 .dentry = HNS3_DBG_DENTRY_QUEUE, 281 .buf_len = HNS3_DBG_READ_LEN, 282 .init = hns3_dbg_common_file_init, 283 }, 284 { 285 .name = "rx_queue_info", 286 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 287 .dentry = HNS3_DBG_DENTRY_QUEUE, 288 .buf_len = HNS3_DBG_READ_LEN_1MB, 289 .init = hns3_dbg_common_file_init, 290 }, 291 { 292 .name = "tx_queue_info", 293 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 294 .dentry = HNS3_DBG_DENTRY_QUEUE, 295 .buf_len = HNS3_DBG_READ_LEN_1MB, 296 .init = hns3_dbg_common_file_init, 297 }, 298 { 299 .name = "fd_tcam", 300 .cmd = HNAE3_DBG_CMD_FD_TCAM, 301 .dentry = HNS3_DBG_DENTRY_FD, 302 .buf_len = HNS3_DBG_READ_LEN, 303 .init = hns3_dbg_common_file_init, 304 }, 305 { 306 .name = "service_task_info", 307 .cmd = HNAE3_DBG_CMD_SERV_INFO, 308 .dentry = HNS3_DBG_DENTRY_COMMON, 309 .buf_len = HNS3_DBG_READ_LEN, 310 .init = hns3_dbg_common_file_init, 311 }, 312 { 313 .name = "vlan_config", 314 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 315 .dentry = HNS3_DBG_DENTRY_COMMON, 316 .buf_len = HNS3_DBG_READ_LEN, 317 .init = hns3_dbg_common_file_init, 318 }, 319 }; 320 321 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 322 { 323 .name = "support FD", 324 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 325 }, { 326 .name = "support GRO", 327 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 328 }, { 329 .name = "support FEC", 330 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 331 }, { 332 .name = "support UDP GSO", 333 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 334 }, { 335 .name = "support PTP", 336 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 337 }, { 338 .name = "support INT QL", 339 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 340 }, { 341 .name = "support HW TX csum", 342 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 343 }, { 344 .name = "support UDP tunnel csum", 345 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 346 }, { 347 .name = "support TX push", 348 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 349 }, { 350 .name = "support imp-controlled PHY", 351 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 352 }, { 353 .name = "support rxd advanced layout", 354 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 355 }, { 356 .name = "support port vlan bypass", 357 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 358 }, { 359 .name = "support modify vlan filter state", 360 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 361 } 362 }; 363 364 static void hns3_dbg_fill_content(char *content, u16 len, 365 const struct hns3_dbg_item *items, 366 const char **result, u16 size) 367 { 368 char *pos = content; 369 u16 i; 370 371 memset(content, ' ', len); 372 for (i = 0; i < size; i++) { 373 if (result) 374 strncpy(pos, result[i], strlen(result[i])); 375 else 376 strncpy(pos, items[i].name, strlen(items[i].name)); 377 378 pos += strlen(items[i].name) + items[i].interval; 379 } 380 381 *pos++ = '\n'; 382 *pos++ = '\0'; 383 } 384 385 static const struct hns3_dbg_item rx_queue_info_items[] = { 386 { "QUEUE_ID", 2 }, 387 { "BD_NUM", 2 }, 388 { "BD_LEN", 2 }, 389 { "TAIL", 2 }, 390 { "HEAD", 2 }, 391 { "FBDNUM", 2 }, 392 { "PKTNUM", 2 }, 393 { "RING_EN", 2 }, 394 { "RX_RING_EN", 2 }, 395 { "BASE_ADDR", 10 }, 396 }; 397 398 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 399 struct hnae3_ae_dev *ae_dev, char **result, 400 u32 index) 401 { 402 u32 base_add_l, base_add_h; 403 u32 j = 0; 404 405 sprintf(result[j++], "%8u", index); 406 407 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 408 HNS3_RING_RX_RING_BD_NUM_REG)); 409 410 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 411 HNS3_RING_RX_RING_BD_LEN_REG)); 412 413 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 414 HNS3_RING_RX_RING_TAIL_REG)); 415 416 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 417 HNS3_RING_RX_RING_HEAD_REG)); 418 419 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 420 HNS3_RING_RX_RING_FBDNUM_REG)); 421 422 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 423 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 424 425 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 426 HNS3_RING_EN_REG) ? "on" : "off"); 427 428 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 429 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 430 HNS3_RING_RX_EN_REG) ? "on" : "off"); 431 else 432 sprintf(result[j++], "%10s", "NA"); 433 434 base_add_h = readl_relaxed(ring->tqp->io_base + 435 HNS3_RING_RX_RING_BASEADDR_H_REG); 436 base_add_l = readl_relaxed(ring->tqp->io_base + 437 HNS3_RING_RX_RING_BASEADDR_L_REG); 438 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 439 } 440 441 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 442 char *buf, int len) 443 { 444 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 445 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 446 char *result[ARRAY_SIZE(rx_queue_info_items)]; 447 struct hns3_nic_priv *priv = h->priv; 448 char content[HNS3_DBG_INFO_LEN]; 449 struct hns3_enet_ring *ring; 450 int pos = 0; 451 u32 i; 452 453 if (!priv->ring) { 454 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 455 return -EFAULT; 456 } 457 458 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 459 result[i] = &data_str[i][0]; 460 461 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 462 NULL, ARRAY_SIZE(rx_queue_info_items)); 463 pos += scnprintf(buf + pos, len - pos, "%s", content); 464 for (i = 0; i < h->kinfo.num_tqps; i++) { 465 /* Each cycle needs to determine whether the instance is reset, 466 * to prevent reference to invalid memory. And need to ensure 467 * that the following code is executed within 100ms. 468 */ 469 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 470 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 471 return -EPERM; 472 473 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 474 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 475 hns3_dbg_fill_content(content, sizeof(content), 476 rx_queue_info_items, 477 (const char **)result, 478 ARRAY_SIZE(rx_queue_info_items)); 479 pos += scnprintf(buf + pos, len - pos, "%s", content); 480 } 481 482 return 0; 483 } 484 485 static const struct hns3_dbg_item tx_queue_info_items[] = { 486 { "QUEUE_ID", 2 }, 487 { "BD_NUM", 2 }, 488 { "TC", 2 }, 489 { "TAIL", 2 }, 490 { "HEAD", 2 }, 491 { "FBDNUM", 2 }, 492 { "OFFSET", 2 }, 493 { "PKTNUM", 2 }, 494 { "RING_EN", 2 }, 495 { "TX_RING_EN", 2 }, 496 { "BASE_ADDR", 10 }, 497 }; 498 499 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 500 struct hnae3_ae_dev *ae_dev, char **result, 501 u32 index) 502 { 503 u32 base_add_l, base_add_h; 504 u32 j = 0; 505 506 sprintf(result[j++], "%8u", index); 507 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 508 HNS3_RING_TX_RING_BD_NUM_REG)); 509 510 sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base + 511 HNS3_RING_TX_RING_TC_REG)); 512 513 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 514 HNS3_RING_TX_RING_TAIL_REG)); 515 516 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 517 HNS3_RING_TX_RING_HEAD_REG)); 518 519 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 520 HNS3_RING_TX_RING_FBDNUM_REG)); 521 522 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 523 HNS3_RING_TX_RING_OFFSET_REG)); 524 525 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 526 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 527 528 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 529 HNS3_RING_EN_REG) ? "on" : "off"); 530 531 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 532 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 533 HNS3_RING_TX_EN_REG) ? "on" : "off"); 534 else 535 sprintf(result[j++], "%10s", "NA"); 536 537 base_add_h = readl_relaxed(ring->tqp->io_base + 538 HNS3_RING_TX_RING_BASEADDR_H_REG); 539 base_add_l = readl_relaxed(ring->tqp->io_base + 540 HNS3_RING_TX_RING_BASEADDR_L_REG); 541 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 542 } 543 544 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 545 char *buf, int len) 546 { 547 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 548 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 549 char *result[ARRAY_SIZE(tx_queue_info_items)]; 550 struct hns3_nic_priv *priv = h->priv; 551 char content[HNS3_DBG_INFO_LEN]; 552 struct hns3_enet_ring *ring; 553 int pos = 0; 554 u32 i; 555 556 if (!priv->ring) { 557 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 558 return -EFAULT; 559 } 560 561 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 562 result[i] = &data_str[i][0]; 563 564 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 565 NULL, ARRAY_SIZE(tx_queue_info_items)); 566 pos += scnprintf(buf + pos, len - pos, "%s", content); 567 568 for (i = 0; i < h->kinfo.num_tqps; i++) { 569 /* Each cycle needs to determine whether the instance is reset, 570 * to prevent reference to invalid memory. And need to ensure 571 * that the following code is executed within 100ms. 572 */ 573 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 574 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 575 return -EPERM; 576 577 ring = &priv->ring[i]; 578 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 579 hns3_dbg_fill_content(content, sizeof(content), 580 tx_queue_info_items, 581 (const char **)result, 582 ARRAY_SIZE(tx_queue_info_items)); 583 pos += scnprintf(buf + pos, len - pos, "%s", content); 584 } 585 586 return 0; 587 } 588 589 static const struct hns3_dbg_item queue_map_items[] = { 590 { "local_queue_id", 2 }, 591 { "global_queue_id", 2 }, 592 { "vector_id", 2 }, 593 }; 594 595 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 596 { 597 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 598 char *result[ARRAY_SIZE(queue_map_items)]; 599 struct hns3_nic_priv *priv = h->priv; 600 char content[HNS3_DBG_INFO_LEN]; 601 int pos = 0; 602 int j; 603 u32 i; 604 605 if (!h->ae_algo->ops->get_global_queue_id) 606 return -EOPNOTSUPP; 607 608 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 609 result[i] = &data_str[i][0]; 610 611 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 612 NULL, ARRAY_SIZE(queue_map_items)); 613 pos += scnprintf(buf + pos, len - pos, "%s", content); 614 for (i = 0; i < h->kinfo.num_tqps; i++) { 615 if (!priv->ring || !priv->ring[i].tqp_vector) 616 continue; 617 j = 0; 618 sprintf(result[j++], "%u", i); 619 sprintf(result[j++], "%u", 620 h->ae_algo->ops->get_global_queue_id(h, i)); 621 sprintf(result[j++], "%u", 622 priv->ring[i].tqp_vector->vector_irq); 623 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 624 (const char **)result, 625 ARRAY_SIZE(queue_map_items)); 626 pos += scnprintf(buf + pos, len - pos, "%s", content); 627 } 628 629 return 0; 630 } 631 632 static const struct hns3_dbg_item rx_bd_info_items[] = { 633 { "BD_IDX", 3 }, 634 { "L234_INFO", 2 }, 635 { "PKT_LEN", 3 }, 636 { "SIZE", 4 }, 637 { "RSS_HASH", 4 }, 638 { "FD_ID", 2 }, 639 { "VLAN_TAG", 2 }, 640 { "O_DM_VLAN_ID_FB", 2 }, 641 { "OT_VLAN_TAG", 2 }, 642 { "BD_BASE_INFO", 2 }, 643 { "PTYPE", 2 }, 644 { "HW_CSUM", 2 }, 645 }; 646 647 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 648 struct hns3_desc *desc, char **result, int idx) 649 { 650 unsigned int j = 0; 651 652 sprintf(result[j++], "%5d", idx); 653 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 654 sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len)); 655 sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size)); 656 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 657 sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id)); 658 sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag)); 659 sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 660 sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag)); 661 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 662 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 663 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 664 665 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 666 HNS3_RXD_PTYPE_M, 667 HNS3_RXD_PTYPE_S)); 668 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 669 } else { 670 sprintf(result[j++], "NA"); 671 sprintf(result[j++], "NA"); 672 } 673 } 674 675 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 676 { 677 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 678 struct hns3_nic_priv *priv = d->handle->priv; 679 char *result[ARRAY_SIZE(rx_bd_info_items)]; 680 char content[HNS3_DBG_INFO_LEN]; 681 struct hns3_enet_ring *ring; 682 struct hns3_desc *desc; 683 unsigned int i; 684 int pos = 0; 685 686 if (d->qid >= d->handle->kinfo.num_tqps) { 687 dev_err(&d->handle->pdev->dev, 688 "queue%u is not in use\n", d->qid); 689 return -EINVAL; 690 } 691 692 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 693 result[i] = &data_str[i][0]; 694 695 pos += scnprintf(buf + pos, len - pos, 696 "Queue %u rx bd info:\n", d->qid); 697 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 698 NULL, ARRAY_SIZE(rx_bd_info_items)); 699 pos += scnprintf(buf + pos, len - pos, "%s", content); 700 701 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 702 for (i = 0; i < ring->desc_num; i++) { 703 desc = &ring->desc[i]; 704 705 hns3_dump_rx_bd_info(priv, desc, result, i); 706 hns3_dbg_fill_content(content, sizeof(content), 707 rx_bd_info_items, (const char **)result, 708 ARRAY_SIZE(rx_bd_info_items)); 709 pos += scnprintf(buf + pos, len - pos, "%s", content); 710 } 711 712 return 0; 713 } 714 715 static const struct hns3_dbg_item tx_bd_info_items[] = { 716 { "BD_IDX", 5 }, 717 { "ADDRESS", 2 }, 718 { "VLAN_TAG", 2 }, 719 { "SIZE", 2 }, 720 { "T_CS_VLAN_TSO", 2 }, 721 { "OT_VLAN_TAG", 3 }, 722 { "TV", 2 }, 723 { "OLT_VLAN_LEN", 2}, 724 { "PAYLEN_OL4CS", 2}, 725 { "BD_FE_SC_VLD", 2}, 726 { "MSS_HW_CSUM", 0}, 727 }; 728 729 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, 730 struct hns3_desc *desc, char **result, int idx) 731 { 732 unsigned int j = 0; 733 734 sprintf(result[j++], "%6d", idx); 735 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 736 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag)); 737 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size)); 738 sprintf(result[j++], "%#x", 739 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 740 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag)); 741 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv)); 742 sprintf(result[j++], "%10u", 743 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 744 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 745 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 746 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum)); 747 } 748 749 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 750 { 751 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 752 struct hns3_nic_priv *priv = d->handle->priv; 753 char *result[ARRAY_SIZE(tx_bd_info_items)]; 754 char content[HNS3_DBG_INFO_LEN]; 755 struct hns3_enet_ring *ring; 756 struct hns3_desc *desc; 757 unsigned int i; 758 int pos = 0; 759 760 if (d->qid >= d->handle->kinfo.num_tqps) { 761 dev_err(&d->handle->pdev->dev, 762 "queue%u is not in use\n", d->qid); 763 return -EINVAL; 764 } 765 766 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 767 result[i] = &data_str[i][0]; 768 769 pos += scnprintf(buf + pos, len - pos, 770 "Queue %u tx bd info:\n", d->qid); 771 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 772 NULL, ARRAY_SIZE(tx_bd_info_items)); 773 pos += scnprintf(buf + pos, len - pos, "%s", content); 774 775 ring = &priv->ring[d->qid]; 776 for (i = 0; i < ring->desc_num; i++) { 777 desc = &ring->desc[i]; 778 779 hns3_dump_tx_bd_info(priv, desc, result, i); 780 hns3_dbg_fill_content(content, sizeof(content), 781 tx_bd_info_items, (const char **)result, 782 ARRAY_SIZE(tx_bd_info_items)); 783 pos += scnprintf(buf + pos, len - pos, "%s", content); 784 } 785 786 return 0; 787 } 788 789 static void 790 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 791 { 792 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 793 static const char * const str[] = {"no", "yes"}; 794 unsigned long *caps = ae_dev->caps; 795 u32 i, state; 796 797 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 798 799 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 800 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 801 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 802 hns3_dbg_cap[i].name, str[state]); 803 } 804 805 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 806 } 807 808 static void 809 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 810 { 811 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 812 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 813 struct hnae3_knic_private_info *kinfo = &h->kinfo; 814 815 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 816 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 817 dev_specs->mac_entry_num); 818 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 819 dev_specs->mng_entry_num); 820 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 821 dev_specs->max_non_tso_bd_num); 822 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 823 dev_specs->rss_ind_tbl_size); 824 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 825 dev_specs->rss_key_size); 826 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 827 kinfo->rss_size); 828 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 829 kinfo->req_rss_size); 830 *pos += scnprintf(buf + *pos, len - *pos, 831 "Task queue pairs numbers: %u\n", 832 kinfo->num_tqps); 833 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 834 kinfo->rx_buf_len); 835 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 836 kinfo->num_tx_desc); 837 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 838 kinfo->num_rx_desc); 839 *pos += scnprintf(buf + *pos, len - *pos, 840 "Total number of enabled TCs: %u\n", 841 kinfo->tc_info.num_tc); 842 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 843 dev_specs->int_ql_max); 844 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 845 dev_specs->max_int_gl); 846 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 847 dev_specs->max_tm_rate); 848 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 849 dev_specs->max_qset_num); 850 } 851 852 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 853 { 854 int pos = 0; 855 856 hns3_dbg_dev_caps(h, buf, len, &pos); 857 858 hns3_dbg_dev_specs(h, buf, len, &pos); 859 860 return 0; 861 } 862 863 static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle, 864 const unsigned char *name, u32 *index) 865 { 866 u32 i; 867 868 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 869 if (!strncmp(name, hns3_dbg_cmd[i].name, 870 strlen(hns3_dbg_cmd[i].name))) { 871 *index = i; 872 return 0; 873 } 874 } 875 876 dev_err(&handle->pdev->dev, "unknown command(%s)\n", name); 877 return -EINVAL; 878 } 879 880 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 881 { 882 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 883 .dbg_dump = hns3_dbg_queue_map, 884 }, 885 { 886 .cmd = HNAE3_DBG_CMD_DEV_INFO, 887 .dbg_dump = hns3_dbg_dev_info, 888 }, 889 { 890 .cmd = HNAE3_DBG_CMD_TX_BD, 891 .dbg_dump_bd = hns3_dbg_tx_bd_info, 892 }, 893 { 894 .cmd = HNAE3_DBG_CMD_RX_BD, 895 .dbg_dump_bd = hns3_dbg_rx_bd_info, 896 }, 897 { 898 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 899 .dbg_dump = hns3_dbg_rx_queue_info, 900 }, 901 { 902 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 903 .dbg_dump = hns3_dbg_tx_queue_info, 904 }, 905 }; 906 907 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 908 enum hnae3_dbg_cmd cmd, char *buf, int len) 909 { 910 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 911 const struct hns3_dbg_func *cmd_func; 912 u32 i; 913 914 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 915 if (cmd == hns3_dbg_cmd_func[i].cmd) { 916 cmd_func = &hns3_dbg_cmd_func[i]; 917 if (cmd_func->dbg_dump) 918 return cmd_func->dbg_dump(dbg_data->handle, buf, 919 len); 920 else 921 return cmd_func->dbg_dump_bd(dbg_data, buf, 922 len); 923 } 924 } 925 926 if (!ops->dbg_read_cmd) 927 return -EOPNOTSUPP; 928 929 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 930 } 931 932 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 933 size_t count, loff_t *ppos) 934 { 935 struct hns3_dbg_data *dbg_data = filp->private_data; 936 struct hnae3_handle *handle = dbg_data->handle; 937 struct hns3_nic_priv *priv = handle->priv; 938 ssize_t size = 0; 939 char **save_buf; 940 char *read_buf; 941 u32 index; 942 int ret; 943 944 ret = hns3_dbg_get_cmd_index(handle, filp->f_path.dentry->d_iname, 945 &index); 946 if (ret) 947 return ret; 948 949 save_buf = &hns3_dbg_cmd[index].buf; 950 951 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 952 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 953 ret = -EBUSY; 954 goto out; 955 } 956 957 if (*save_buf) { 958 read_buf = *save_buf; 959 } else { 960 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 961 if (!read_buf) 962 return -ENOMEM; 963 964 /* save the buffer addr until the last read operation */ 965 *save_buf = read_buf; 966 } 967 968 /* get data ready for the first time to read */ 969 if (!*ppos) { 970 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 971 read_buf, hns3_dbg_cmd[index].buf_len); 972 if (ret) 973 goto out; 974 } 975 976 size = simple_read_from_buffer(buffer, count, ppos, read_buf, 977 strlen(read_buf)); 978 if (size > 0) 979 return size; 980 981 out: 982 /* free the buffer for the last read operation */ 983 if (*save_buf) { 984 kvfree(*save_buf); 985 *save_buf = NULL; 986 } 987 988 return ret; 989 } 990 991 static const struct file_operations hns3_dbg_fops = { 992 .owner = THIS_MODULE, 993 .open = simple_open, 994 .read = hns3_dbg_read, 995 }; 996 997 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 998 { 999 struct dentry *entry_dir; 1000 struct hns3_dbg_data *data; 1001 u16 max_queue_num; 1002 unsigned int i; 1003 1004 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1005 max_queue_num = hns3_get_max_available_channels(handle); 1006 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 1007 GFP_KERNEL); 1008 if (!data) 1009 return -ENOMEM; 1010 1011 for (i = 0; i < max_queue_num; i++) { 1012 char name[HNS3_DBG_FILE_NAME_LEN]; 1013 1014 data[i].handle = handle; 1015 data[i].qid = i; 1016 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1017 debugfs_create_file(name, 0400, entry_dir, &data[i], 1018 &hns3_dbg_fops); 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int 1025 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1026 { 1027 struct hns3_dbg_data *data; 1028 struct dentry *entry_dir; 1029 1030 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1031 if (!data) 1032 return -ENOMEM; 1033 1034 data->handle = handle; 1035 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1036 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1037 data, &hns3_dbg_fops); 1038 1039 return 0; 1040 } 1041 1042 int hns3_dbg_init(struct hnae3_handle *handle) 1043 { 1044 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1045 const char *name = pci_name(handle->pdev); 1046 int ret; 1047 u32 i; 1048 1049 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1050 debugfs_create_dir(name, hns3_dbgfs_root); 1051 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1052 1053 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1054 hns3_dbg_dentry[i].dentry = 1055 debugfs_create_dir(hns3_dbg_dentry[i].name, 1056 handle->hnae3_dbgfs); 1057 1058 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1059 if (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1060 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 1061 continue; 1062 1063 if (!hns3_dbg_cmd[i].init) { 1064 dev_err(&handle->pdev->dev, 1065 "cmd %s lack of init func\n", 1066 hns3_dbg_cmd[i].name); 1067 ret = -EINVAL; 1068 goto out; 1069 } 1070 1071 ret = hns3_dbg_cmd[i].init(handle, i); 1072 if (ret) { 1073 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1074 hns3_dbg_cmd[i].name); 1075 goto out; 1076 } 1077 } 1078 1079 return 0; 1080 1081 out: 1082 debugfs_remove_recursive(handle->hnae3_dbgfs); 1083 handle->hnae3_dbgfs = NULL; 1084 return ret; 1085 } 1086 1087 void hns3_dbg_uninit(struct hnae3_handle *handle) 1088 { 1089 u32 i; 1090 1091 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1092 if (hns3_dbg_cmd[i].buf) { 1093 kvfree(hns3_dbg_cmd[i].buf); 1094 hns3_dbg_cmd[i].buf = NULL; 1095 } 1096 1097 debugfs_remove_recursive(handle->hnae3_dbgfs); 1098 handle->hnae3_dbgfs = NULL; 1099 } 1100 1101 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1102 { 1103 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1104 } 1105 1106 void hns3_dbg_unregister_debugfs(void) 1107 { 1108 debugfs_remove_recursive(hns3_dbgfs_root); 1109 hns3_dbgfs_root = NULL; 1110 } 1111