1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 7 #include "hnae3.h" 8 #include "hns3_debugfs.h" 9 #include "hns3_enet.h" 10 11 static struct dentry *hns3_dbgfs_root; 12 13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 14 { 15 .name = "tm" 16 }, 17 { 18 .name = "tx_bd_info" 19 }, 20 { 21 .name = "rx_bd_info" 22 }, 23 { 24 .name = "mac_list" 25 }, 26 { 27 .name = "reg" 28 }, 29 { 30 .name = "queue" 31 }, 32 { 33 .name = "fd" 34 }, 35 /* keep common at the bottom and add new directory above */ 36 { 37 .name = "common" 38 }, 39 }; 40 41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd); 42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd); 43 44 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 45 { 46 .name = "tm_nodes", 47 .cmd = HNAE3_DBG_CMD_TM_NODES, 48 .dentry = HNS3_DBG_DENTRY_TM, 49 .buf_len = HNS3_DBG_READ_LEN, 50 .init = hns3_dbg_common_file_init, 51 }, 52 { 53 .name = "tm_priority", 54 .cmd = HNAE3_DBG_CMD_TM_PRI, 55 .dentry = HNS3_DBG_DENTRY_TM, 56 .buf_len = HNS3_DBG_READ_LEN, 57 .init = hns3_dbg_common_file_init, 58 }, 59 { 60 .name = "tm_qset", 61 .cmd = HNAE3_DBG_CMD_TM_QSET, 62 .dentry = HNS3_DBG_DENTRY_TM, 63 .buf_len = HNS3_DBG_READ_LEN, 64 .init = hns3_dbg_common_file_init, 65 }, 66 { 67 .name = "tm_map", 68 .cmd = HNAE3_DBG_CMD_TM_MAP, 69 .dentry = HNS3_DBG_DENTRY_TM, 70 .buf_len = HNS3_DBG_READ_LEN_1MB, 71 .init = hns3_dbg_common_file_init, 72 }, 73 { 74 .name = "tm_pg", 75 .cmd = HNAE3_DBG_CMD_TM_PG, 76 .dentry = HNS3_DBG_DENTRY_TM, 77 .buf_len = HNS3_DBG_READ_LEN, 78 .init = hns3_dbg_common_file_init, 79 }, 80 { 81 .name = "tm_port", 82 .cmd = HNAE3_DBG_CMD_TM_PORT, 83 .dentry = HNS3_DBG_DENTRY_TM, 84 .buf_len = HNS3_DBG_READ_LEN, 85 .init = hns3_dbg_common_file_init, 86 }, 87 { 88 .name = "tc_sch_info", 89 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 90 .dentry = HNS3_DBG_DENTRY_TM, 91 .buf_len = HNS3_DBG_READ_LEN, 92 .init = hns3_dbg_common_file_init, 93 }, 94 { 95 .name = "qos_pause_cfg", 96 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 97 .dentry = HNS3_DBG_DENTRY_TM, 98 .buf_len = HNS3_DBG_READ_LEN, 99 .init = hns3_dbg_common_file_init, 100 }, 101 { 102 .name = "qos_pri_map", 103 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 104 .dentry = HNS3_DBG_DENTRY_TM, 105 .buf_len = HNS3_DBG_READ_LEN, 106 .init = hns3_dbg_common_file_init, 107 }, 108 { 109 .name = "qos_dscp_map", 110 .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP, 111 .dentry = HNS3_DBG_DENTRY_TM, 112 .buf_len = HNS3_DBG_READ_LEN, 113 .init = hns3_dbg_common_file_init, 114 }, 115 { 116 .name = "qos_buf_cfg", 117 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 118 .dentry = HNS3_DBG_DENTRY_TM, 119 .buf_len = HNS3_DBG_READ_LEN, 120 .init = hns3_dbg_common_file_init, 121 }, 122 { 123 .name = "dev_info", 124 .cmd = HNAE3_DBG_CMD_DEV_INFO, 125 .dentry = HNS3_DBG_DENTRY_COMMON, 126 .buf_len = HNS3_DBG_READ_LEN, 127 .init = hns3_dbg_common_file_init, 128 }, 129 { 130 .name = "tx_bd_queue", 131 .cmd = HNAE3_DBG_CMD_TX_BD, 132 .dentry = HNS3_DBG_DENTRY_TX_BD, 133 .buf_len = HNS3_DBG_READ_LEN_5MB, 134 .init = hns3_dbg_bd_file_init, 135 }, 136 { 137 .name = "rx_bd_queue", 138 .cmd = HNAE3_DBG_CMD_RX_BD, 139 .dentry = HNS3_DBG_DENTRY_RX_BD, 140 .buf_len = HNS3_DBG_READ_LEN_4MB, 141 .init = hns3_dbg_bd_file_init, 142 }, 143 { 144 .name = "uc", 145 .cmd = HNAE3_DBG_CMD_MAC_UC, 146 .dentry = HNS3_DBG_DENTRY_MAC, 147 .buf_len = HNS3_DBG_READ_LEN_128KB, 148 .init = hns3_dbg_common_file_init, 149 }, 150 { 151 .name = "mc", 152 .cmd = HNAE3_DBG_CMD_MAC_MC, 153 .dentry = HNS3_DBG_DENTRY_MAC, 154 .buf_len = HNS3_DBG_READ_LEN, 155 .init = hns3_dbg_common_file_init, 156 }, 157 { 158 .name = "mng_tbl", 159 .cmd = HNAE3_DBG_CMD_MNG_TBL, 160 .dentry = HNS3_DBG_DENTRY_COMMON, 161 .buf_len = HNS3_DBG_READ_LEN, 162 .init = hns3_dbg_common_file_init, 163 }, 164 { 165 .name = "loopback", 166 .cmd = HNAE3_DBG_CMD_LOOPBACK, 167 .dentry = HNS3_DBG_DENTRY_COMMON, 168 .buf_len = HNS3_DBG_READ_LEN, 169 .init = hns3_dbg_common_file_init, 170 }, 171 { 172 .name = "interrupt_info", 173 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 174 .dentry = HNS3_DBG_DENTRY_COMMON, 175 .buf_len = HNS3_DBG_READ_LEN, 176 .init = hns3_dbg_common_file_init, 177 }, 178 { 179 .name = "reset_info", 180 .cmd = HNAE3_DBG_CMD_RESET_INFO, 181 .dentry = HNS3_DBG_DENTRY_COMMON, 182 .buf_len = HNS3_DBG_READ_LEN, 183 .init = hns3_dbg_common_file_init, 184 }, 185 { 186 .name = "imp_info", 187 .cmd = HNAE3_DBG_CMD_IMP_INFO, 188 .dentry = HNS3_DBG_DENTRY_COMMON, 189 .buf_len = HNS3_DBG_READ_LEN, 190 .init = hns3_dbg_common_file_init, 191 }, 192 { 193 .name = "ncl_config", 194 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 195 .dentry = HNS3_DBG_DENTRY_COMMON, 196 .buf_len = HNS3_DBG_READ_LEN_128KB, 197 .init = hns3_dbg_common_file_init, 198 }, 199 { 200 .name = "mac_tnl_status", 201 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 202 .dentry = HNS3_DBG_DENTRY_COMMON, 203 .buf_len = HNS3_DBG_READ_LEN, 204 .init = hns3_dbg_common_file_init, 205 }, 206 { 207 .name = "bios_common", 208 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 209 .dentry = HNS3_DBG_DENTRY_REG, 210 .buf_len = HNS3_DBG_READ_LEN, 211 .init = hns3_dbg_common_file_init, 212 }, 213 { 214 .name = "ssu", 215 .cmd = HNAE3_DBG_CMD_REG_SSU, 216 .dentry = HNS3_DBG_DENTRY_REG, 217 .buf_len = HNS3_DBG_READ_LEN, 218 .init = hns3_dbg_common_file_init, 219 }, 220 { 221 .name = "igu_egu", 222 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 223 .dentry = HNS3_DBG_DENTRY_REG, 224 .buf_len = HNS3_DBG_READ_LEN, 225 .init = hns3_dbg_common_file_init, 226 }, 227 { 228 .name = "rpu", 229 .cmd = HNAE3_DBG_CMD_REG_RPU, 230 .dentry = HNS3_DBG_DENTRY_REG, 231 .buf_len = HNS3_DBG_READ_LEN, 232 .init = hns3_dbg_common_file_init, 233 }, 234 { 235 .name = "ncsi", 236 .cmd = HNAE3_DBG_CMD_REG_NCSI, 237 .dentry = HNS3_DBG_DENTRY_REG, 238 .buf_len = HNS3_DBG_READ_LEN, 239 .init = hns3_dbg_common_file_init, 240 }, 241 { 242 .name = "rtc", 243 .cmd = HNAE3_DBG_CMD_REG_RTC, 244 .dentry = HNS3_DBG_DENTRY_REG, 245 .buf_len = HNS3_DBG_READ_LEN, 246 .init = hns3_dbg_common_file_init, 247 }, 248 { 249 .name = "ppp", 250 .cmd = HNAE3_DBG_CMD_REG_PPP, 251 .dentry = HNS3_DBG_DENTRY_REG, 252 .buf_len = HNS3_DBG_READ_LEN, 253 .init = hns3_dbg_common_file_init, 254 }, 255 { 256 .name = "rcb", 257 .cmd = HNAE3_DBG_CMD_REG_RCB, 258 .dentry = HNS3_DBG_DENTRY_REG, 259 .buf_len = HNS3_DBG_READ_LEN, 260 .init = hns3_dbg_common_file_init, 261 }, 262 { 263 .name = "tqp", 264 .cmd = HNAE3_DBG_CMD_REG_TQP, 265 .dentry = HNS3_DBG_DENTRY_REG, 266 .buf_len = HNS3_DBG_READ_LEN_128KB, 267 .init = hns3_dbg_common_file_init, 268 }, 269 { 270 .name = "mac", 271 .cmd = HNAE3_DBG_CMD_REG_MAC, 272 .dentry = HNS3_DBG_DENTRY_REG, 273 .buf_len = HNS3_DBG_READ_LEN, 274 .init = hns3_dbg_common_file_init, 275 }, 276 { 277 .name = "dcb", 278 .cmd = HNAE3_DBG_CMD_REG_DCB, 279 .dentry = HNS3_DBG_DENTRY_REG, 280 .buf_len = HNS3_DBG_READ_LEN, 281 .init = hns3_dbg_common_file_init, 282 }, 283 { 284 .name = "queue_map", 285 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 286 .dentry = HNS3_DBG_DENTRY_QUEUE, 287 .buf_len = HNS3_DBG_READ_LEN, 288 .init = hns3_dbg_common_file_init, 289 }, 290 { 291 .name = "rx_queue_info", 292 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 293 .dentry = HNS3_DBG_DENTRY_QUEUE, 294 .buf_len = HNS3_DBG_READ_LEN_1MB, 295 .init = hns3_dbg_common_file_init, 296 }, 297 { 298 .name = "tx_queue_info", 299 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 300 .dentry = HNS3_DBG_DENTRY_QUEUE, 301 .buf_len = HNS3_DBG_READ_LEN_1MB, 302 .init = hns3_dbg_common_file_init, 303 }, 304 { 305 .name = "fd_tcam", 306 .cmd = HNAE3_DBG_CMD_FD_TCAM, 307 .dentry = HNS3_DBG_DENTRY_FD, 308 .buf_len = HNS3_DBG_READ_LEN_1MB, 309 .init = hns3_dbg_common_file_init, 310 }, 311 { 312 .name = "service_task_info", 313 .cmd = HNAE3_DBG_CMD_SERV_INFO, 314 .dentry = HNS3_DBG_DENTRY_COMMON, 315 .buf_len = HNS3_DBG_READ_LEN, 316 .init = hns3_dbg_common_file_init, 317 }, 318 { 319 .name = "vlan_config", 320 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 321 .dentry = HNS3_DBG_DENTRY_COMMON, 322 .buf_len = HNS3_DBG_READ_LEN, 323 .init = hns3_dbg_common_file_init, 324 }, 325 { 326 .name = "ptp_info", 327 .cmd = HNAE3_DBG_CMD_PTP_INFO, 328 .dentry = HNS3_DBG_DENTRY_COMMON, 329 .buf_len = HNS3_DBG_READ_LEN, 330 .init = hns3_dbg_common_file_init, 331 }, 332 { 333 .name = "fd_counter", 334 .cmd = HNAE3_DBG_CMD_FD_COUNTER, 335 .dentry = HNS3_DBG_DENTRY_FD, 336 .buf_len = HNS3_DBG_READ_LEN, 337 .init = hns3_dbg_common_file_init, 338 }, 339 { 340 .name = "umv_info", 341 .cmd = HNAE3_DBG_CMD_UMV_INFO, 342 .dentry = HNS3_DBG_DENTRY_COMMON, 343 .buf_len = HNS3_DBG_READ_LEN, 344 .init = hns3_dbg_common_file_init, 345 }, 346 { 347 .name = "page_pool_info", 348 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, 349 .dentry = HNS3_DBG_DENTRY_COMMON, 350 .buf_len = HNS3_DBG_READ_LEN, 351 .init = hns3_dbg_common_file_init, 352 }, 353 { 354 .name = "coalesce_info", 355 .cmd = HNAE3_DBG_CMD_COAL_INFO, 356 .dentry = HNS3_DBG_DENTRY_COMMON, 357 .buf_len = HNS3_DBG_READ_LEN_1MB, 358 .init = hns3_dbg_common_file_init, 359 }, 360 }; 361 362 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 363 { 364 .name = "support FD", 365 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 366 }, { 367 .name = "support GRO", 368 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 369 }, { 370 .name = "support FEC", 371 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 372 }, { 373 .name = "support UDP GSO", 374 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 375 }, { 376 .name = "support PTP", 377 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 378 }, { 379 .name = "support INT QL", 380 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 381 }, { 382 .name = "support HW TX csum", 383 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 384 }, { 385 .name = "support UDP tunnel csum", 386 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 387 }, { 388 .name = "support TX push", 389 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 390 }, { 391 .name = "support imp-controlled PHY", 392 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 393 }, { 394 .name = "support imp-controlled RAS", 395 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B, 396 }, { 397 .name = "support rxd advanced layout", 398 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 399 }, { 400 .name = "support port vlan bypass", 401 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 402 }, { 403 .name = "support modify vlan filter state", 404 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 405 }, { 406 .name = "support FEC statistics", 407 .cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B, 408 }, { 409 .name = "support lane num", 410 .cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B, 411 }, { 412 .name = "support wake on lan", 413 .cap_bit = HNAE3_DEV_SUPPORT_WOL_B, 414 } 415 }; 416 417 static const struct hns3_dbg_item coal_info_items[] = { 418 { "VEC_ID", 2 }, 419 { "ALGO_STATE", 2 }, 420 { "PROFILE_ID", 2 }, 421 { "CQE_MODE", 2 }, 422 { "TUNE_STATE", 2 }, 423 { "STEPS_LEFT", 2 }, 424 { "STEPS_RIGHT", 2 }, 425 { "TIRED", 2 }, 426 { "SW_GL", 2 }, 427 { "SW_QL", 2 }, 428 { "HW_GL", 2 }, 429 { "HW_QL", 2 }, 430 }; 431 432 static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" }; 433 static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" }; 434 static const char * const 435 dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" }; 436 437 static void hns3_dbg_fill_content(char *content, u16 len, 438 const struct hns3_dbg_item *items, 439 const char **result, u16 size) 440 { 441 char *pos = content; 442 u16 i; 443 444 memset(content, ' ', len); 445 for (i = 0; i < size; i++) { 446 if (result) 447 strncpy(pos, result[i], strlen(result[i])); 448 else 449 strncpy(pos, items[i].name, strlen(items[i].name)); 450 451 pos += strlen(items[i].name) + items[i].interval; 452 } 453 454 *pos++ = '\n'; 455 *pos++ = '\0'; 456 } 457 458 static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector, 459 char **result, int i, bool is_tx) 460 { 461 unsigned int gl_offset, ql_offset; 462 struct hns3_enet_coalesce *coal; 463 unsigned int reg_val; 464 unsigned int j = 0; 465 struct dim *dim; 466 bool ql_enable; 467 468 if (is_tx) { 469 coal = &tqp_vector->tx_group.coal; 470 dim = &tqp_vector->tx_group.dim; 471 gl_offset = HNS3_VECTOR_GL1_OFFSET; 472 ql_offset = HNS3_VECTOR_TX_QL_OFFSET; 473 ql_enable = tqp_vector->tx_group.coal.ql_enable; 474 } else { 475 coal = &tqp_vector->rx_group.coal; 476 dim = &tqp_vector->rx_group.dim; 477 gl_offset = HNS3_VECTOR_GL0_OFFSET; 478 ql_offset = HNS3_VECTOR_RX_QL_OFFSET; 479 ql_enable = tqp_vector->rx_group.coal.ql_enable; 480 } 481 482 sprintf(result[j++], "%d", i); 483 sprintf(result[j++], "%s", dim_state_str[dim->state]); 484 sprintf(result[j++], "%u", dim->profile_ix); 485 sprintf(result[j++], "%s", dim_cqe_mode_str[dim->mode]); 486 sprintf(result[j++], "%s", 487 dim_tune_stat_str[dim->tune_state]); 488 sprintf(result[j++], "%u", dim->steps_left); 489 sprintf(result[j++], "%u", dim->steps_right); 490 sprintf(result[j++], "%u", dim->tired); 491 sprintf(result[j++], "%u", coal->int_gl); 492 sprintf(result[j++], "%u", coal->int_ql); 493 reg_val = readl(tqp_vector->mask_addr + gl_offset) & 494 HNS3_VECTOR_GL_MASK; 495 sprintf(result[j++], "%u", reg_val); 496 if (ql_enable) { 497 reg_val = readl(tqp_vector->mask_addr + ql_offset) & 498 HNS3_VECTOR_QL_MASK; 499 sprintf(result[j++], "%u", reg_val); 500 } else { 501 sprintf(result[j++], "NA"); 502 } 503 } 504 505 static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len, 506 int *pos, bool is_tx) 507 { 508 char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN]; 509 char *result[ARRAY_SIZE(coal_info_items)]; 510 struct hns3_enet_tqp_vector *tqp_vector; 511 struct hns3_nic_priv *priv = h->priv; 512 char content[HNS3_DBG_INFO_LEN]; 513 unsigned int i; 514 515 for (i = 0; i < ARRAY_SIZE(coal_info_items); i++) 516 result[i] = &data_str[i][0]; 517 518 *pos += scnprintf(buf + *pos, len - *pos, 519 "%s interrupt coalesce info:\n", 520 is_tx ? "tx" : "rx"); 521 hns3_dbg_fill_content(content, sizeof(content), coal_info_items, 522 NULL, ARRAY_SIZE(coal_info_items)); 523 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 524 525 for (i = 0; i < priv->vector_num; i++) { 526 tqp_vector = &priv->tqp_vector[i]; 527 hns3_get_coal_info(tqp_vector, result, i, is_tx); 528 hns3_dbg_fill_content(content, sizeof(content), coal_info_items, 529 (const char **)result, 530 ARRAY_SIZE(coal_info_items)); 531 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 532 } 533 } 534 535 static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len) 536 { 537 int pos = 0; 538 539 hns3_dump_coal_info(h, buf, len, &pos, true); 540 pos += scnprintf(buf + pos, len - pos, "\n"); 541 hns3_dump_coal_info(h, buf, len, &pos, false); 542 543 return 0; 544 } 545 546 static const struct hns3_dbg_item tx_spare_info_items[] = { 547 { "QUEUE_ID", 2 }, 548 { "COPYBREAK", 2 }, 549 { "LEN", 7 }, 550 { "NTU", 4 }, 551 { "NTC", 4 }, 552 { "LTC", 4 }, 553 { "DMA", 17 }, 554 }; 555 556 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf, 557 int len, u32 ring_num, int *pos) 558 { 559 char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN]; 560 struct hns3_tx_spare *tx_spare = ring->tx_spare; 561 char *result[ARRAY_SIZE(tx_spare_info_items)]; 562 char content[HNS3_DBG_INFO_LEN]; 563 u32 i, j; 564 565 if (!tx_spare) { 566 *pos += scnprintf(buf + *pos, len - *pos, 567 "tx spare buffer is not enabled\n"); 568 return; 569 } 570 571 for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++) 572 result[i] = &data_str[i][0]; 573 574 *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n"); 575 hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items, 576 NULL, ARRAY_SIZE(tx_spare_info_items)); 577 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 578 579 for (i = 0; i < ring_num; i++) { 580 j = 0; 581 sprintf(result[j++], "%u", i); 582 sprintf(result[j++], "%u", ring->tx_copybreak); 583 sprintf(result[j++], "%u", tx_spare->len); 584 sprintf(result[j++], "%u", tx_spare->next_to_use); 585 sprintf(result[j++], "%u", tx_spare->next_to_clean); 586 sprintf(result[j++], "%u", tx_spare->last_to_clean); 587 sprintf(result[j++], "%pad", &tx_spare->dma); 588 hns3_dbg_fill_content(content, sizeof(content), 589 tx_spare_info_items, 590 (const char **)result, 591 ARRAY_SIZE(tx_spare_info_items)); 592 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 593 } 594 } 595 596 static const struct hns3_dbg_item rx_queue_info_items[] = { 597 { "QUEUE_ID", 2 }, 598 { "BD_NUM", 2 }, 599 { "BD_LEN", 2 }, 600 { "TAIL", 2 }, 601 { "HEAD", 2 }, 602 { "FBDNUM", 2 }, 603 { "PKTNUM", 5 }, 604 { "COPYBREAK", 2 }, 605 { "RING_EN", 2 }, 606 { "RX_RING_EN", 2 }, 607 { "BASE_ADDR", 10 }, 608 }; 609 610 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 611 struct hnae3_ae_dev *ae_dev, char **result, 612 u32 index) 613 { 614 u32 base_add_l, base_add_h; 615 u32 j = 0; 616 617 sprintf(result[j++], "%u", index); 618 619 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 620 HNS3_RING_RX_RING_BD_NUM_REG)); 621 622 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 623 HNS3_RING_RX_RING_BD_LEN_REG)); 624 625 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 626 HNS3_RING_RX_RING_TAIL_REG)); 627 628 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 629 HNS3_RING_RX_RING_HEAD_REG)); 630 631 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 632 HNS3_RING_RX_RING_FBDNUM_REG)); 633 634 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 635 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 636 sprintf(result[j++], "%u", ring->rx_copybreak); 637 638 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + 639 HNS3_RING_EN_REG) ? "on" : "off"); 640 641 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 642 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + 643 HNS3_RING_RX_EN_REG) ? "on" : "off"); 644 else 645 sprintf(result[j++], "%s", "NA"); 646 647 base_add_h = readl_relaxed(ring->tqp->io_base + 648 HNS3_RING_RX_RING_BASEADDR_H_REG); 649 base_add_l = readl_relaxed(ring->tqp->io_base + 650 HNS3_RING_RX_RING_BASEADDR_L_REG); 651 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 652 } 653 654 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 655 char *buf, int len) 656 { 657 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 658 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 659 char *result[ARRAY_SIZE(rx_queue_info_items)]; 660 struct hns3_nic_priv *priv = h->priv; 661 char content[HNS3_DBG_INFO_LEN]; 662 struct hns3_enet_ring *ring; 663 int pos = 0; 664 u32 i; 665 666 if (!priv->ring) { 667 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 668 return -EFAULT; 669 } 670 671 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 672 result[i] = &data_str[i][0]; 673 674 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 675 NULL, ARRAY_SIZE(rx_queue_info_items)); 676 pos += scnprintf(buf + pos, len - pos, "%s", content); 677 for (i = 0; i < h->kinfo.num_tqps; i++) { 678 /* Each cycle needs to determine whether the instance is reset, 679 * to prevent reference to invalid memory. And need to ensure 680 * that the following code is executed within 100ms. 681 */ 682 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 683 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 684 return -EPERM; 685 686 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 687 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 688 hns3_dbg_fill_content(content, sizeof(content), 689 rx_queue_info_items, 690 (const char **)result, 691 ARRAY_SIZE(rx_queue_info_items)); 692 pos += scnprintf(buf + pos, len - pos, "%s", content); 693 } 694 695 return 0; 696 } 697 698 static const struct hns3_dbg_item tx_queue_info_items[] = { 699 { "QUEUE_ID", 2 }, 700 { "BD_NUM", 2 }, 701 { "TC", 2 }, 702 { "TAIL", 2 }, 703 { "HEAD", 2 }, 704 { "FBDNUM", 2 }, 705 { "OFFSET", 2 }, 706 { "PKTNUM", 5 }, 707 { "RING_EN", 2 }, 708 { "TX_RING_EN", 2 }, 709 { "BASE_ADDR", 10 }, 710 }; 711 712 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 713 struct hnae3_ae_dev *ae_dev, char **result, 714 u32 index) 715 { 716 u32 base_add_l, base_add_h; 717 u32 j = 0; 718 719 sprintf(result[j++], "%u", index); 720 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 721 HNS3_RING_TX_RING_BD_NUM_REG)); 722 723 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 724 HNS3_RING_TX_RING_TC_REG)); 725 726 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 727 HNS3_RING_TX_RING_TAIL_REG)); 728 729 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 730 HNS3_RING_TX_RING_HEAD_REG)); 731 732 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 733 HNS3_RING_TX_RING_FBDNUM_REG)); 734 735 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 736 HNS3_RING_TX_RING_OFFSET_REG)); 737 738 sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base + 739 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 740 741 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + 742 HNS3_RING_EN_REG) ? "on" : "off"); 743 744 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 745 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base + 746 HNS3_RING_TX_EN_REG) ? "on" : "off"); 747 else 748 sprintf(result[j++], "%s", "NA"); 749 750 base_add_h = readl_relaxed(ring->tqp->io_base + 751 HNS3_RING_TX_RING_BASEADDR_H_REG); 752 base_add_l = readl_relaxed(ring->tqp->io_base + 753 HNS3_RING_TX_RING_BASEADDR_L_REG); 754 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 755 } 756 757 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 758 char *buf, int len) 759 { 760 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 761 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 762 char *result[ARRAY_SIZE(tx_queue_info_items)]; 763 struct hns3_nic_priv *priv = h->priv; 764 char content[HNS3_DBG_INFO_LEN]; 765 struct hns3_enet_ring *ring; 766 int pos = 0; 767 u32 i; 768 769 if (!priv->ring) { 770 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 771 return -EFAULT; 772 } 773 774 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 775 result[i] = &data_str[i][0]; 776 777 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 778 NULL, ARRAY_SIZE(tx_queue_info_items)); 779 pos += scnprintf(buf + pos, len - pos, "%s", content); 780 781 for (i = 0; i < h->kinfo.num_tqps; i++) { 782 /* Each cycle needs to determine whether the instance is reset, 783 * to prevent reference to invalid memory. And need to ensure 784 * that the following code is executed within 100ms. 785 */ 786 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 787 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 788 return -EPERM; 789 790 ring = &priv->ring[i]; 791 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 792 hns3_dbg_fill_content(content, sizeof(content), 793 tx_queue_info_items, 794 (const char **)result, 795 ARRAY_SIZE(tx_queue_info_items)); 796 pos += scnprintf(buf + pos, len - pos, "%s", content); 797 } 798 799 hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos); 800 801 return 0; 802 } 803 804 static const struct hns3_dbg_item queue_map_items[] = { 805 { "local_queue_id", 2 }, 806 { "global_queue_id", 2 }, 807 { "vector_id", 2 }, 808 }; 809 810 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 811 { 812 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 813 char *result[ARRAY_SIZE(queue_map_items)]; 814 struct hns3_nic_priv *priv = h->priv; 815 char content[HNS3_DBG_INFO_LEN]; 816 int pos = 0; 817 int j; 818 u32 i; 819 820 if (!h->ae_algo->ops->get_global_queue_id) 821 return -EOPNOTSUPP; 822 823 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 824 result[i] = &data_str[i][0]; 825 826 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 827 NULL, ARRAY_SIZE(queue_map_items)); 828 pos += scnprintf(buf + pos, len - pos, "%s", content); 829 for (i = 0; i < h->kinfo.num_tqps; i++) { 830 if (!priv->ring || !priv->ring[i].tqp_vector) 831 continue; 832 j = 0; 833 sprintf(result[j++], "%u", i); 834 sprintf(result[j++], "%u", 835 h->ae_algo->ops->get_global_queue_id(h, i)); 836 sprintf(result[j++], "%d", 837 priv->ring[i].tqp_vector->vector_irq); 838 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 839 (const char **)result, 840 ARRAY_SIZE(queue_map_items)); 841 pos += scnprintf(buf + pos, len - pos, "%s", content); 842 } 843 844 return 0; 845 } 846 847 static const struct hns3_dbg_item rx_bd_info_items[] = { 848 { "BD_IDX", 3 }, 849 { "L234_INFO", 2 }, 850 { "PKT_LEN", 3 }, 851 { "SIZE", 4 }, 852 { "RSS_HASH", 4 }, 853 { "FD_ID", 2 }, 854 { "VLAN_TAG", 2 }, 855 { "O_DM_VLAN_ID_FB", 2 }, 856 { "OT_VLAN_TAG", 2 }, 857 { "BD_BASE_INFO", 2 }, 858 { "PTYPE", 2 }, 859 { "HW_CSUM", 2 }, 860 }; 861 862 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 863 struct hns3_desc *desc, char **result, int idx) 864 { 865 unsigned int j = 0; 866 867 sprintf(result[j++], "%d", idx); 868 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 869 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len)); 870 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size)); 871 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 872 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id)); 873 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag)); 874 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 875 sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag)); 876 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 877 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 878 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 879 880 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 881 HNS3_RXD_PTYPE_M, 882 HNS3_RXD_PTYPE_S)); 883 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 884 } else { 885 sprintf(result[j++], "NA"); 886 sprintf(result[j++], "NA"); 887 } 888 } 889 890 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 891 { 892 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 893 struct hns3_nic_priv *priv = d->handle->priv; 894 char *result[ARRAY_SIZE(rx_bd_info_items)]; 895 char content[HNS3_DBG_INFO_LEN]; 896 struct hns3_enet_ring *ring; 897 struct hns3_desc *desc; 898 unsigned int i; 899 int pos = 0; 900 901 if (d->qid >= d->handle->kinfo.num_tqps) { 902 dev_err(&d->handle->pdev->dev, 903 "queue%u is not in use\n", d->qid); 904 return -EINVAL; 905 } 906 907 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 908 result[i] = &data_str[i][0]; 909 910 pos += scnprintf(buf + pos, len - pos, 911 "Queue %u rx bd info:\n", d->qid); 912 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 913 NULL, ARRAY_SIZE(rx_bd_info_items)); 914 pos += scnprintf(buf + pos, len - pos, "%s", content); 915 916 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 917 for (i = 0; i < ring->desc_num; i++) { 918 desc = &ring->desc[i]; 919 920 hns3_dump_rx_bd_info(priv, desc, result, i); 921 hns3_dbg_fill_content(content, sizeof(content), 922 rx_bd_info_items, (const char **)result, 923 ARRAY_SIZE(rx_bd_info_items)); 924 pos += scnprintf(buf + pos, len - pos, "%s", content); 925 } 926 927 return 0; 928 } 929 930 static const struct hns3_dbg_item tx_bd_info_items[] = { 931 { "BD_IDX", 2 }, 932 { "ADDRESS", 13 }, 933 { "VLAN_TAG", 2 }, 934 { "SIZE", 2 }, 935 { "T_CS_VLAN_TSO", 2 }, 936 { "OT_VLAN_TAG", 3 }, 937 { "TV", 5 }, 938 { "OLT_VLAN_LEN", 2 }, 939 { "PAYLEN_OL4CS", 2 }, 940 { "BD_FE_SC_VLD", 2 }, 941 { "MSS_HW_CSUM", 0 }, 942 }; 943 944 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, 945 struct hns3_desc *desc, char **result, int idx) 946 { 947 unsigned int j = 0; 948 949 sprintf(result[j++], "%d", idx); 950 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 951 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag)); 952 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size)); 953 sprintf(result[j++], "%#x", 954 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 955 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag)); 956 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv)); 957 sprintf(result[j++], "%u", 958 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 959 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 960 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 961 sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum)); 962 } 963 964 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 965 { 966 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 967 struct hns3_nic_priv *priv = d->handle->priv; 968 char *result[ARRAY_SIZE(tx_bd_info_items)]; 969 char content[HNS3_DBG_INFO_LEN]; 970 struct hns3_enet_ring *ring; 971 struct hns3_desc *desc; 972 unsigned int i; 973 int pos = 0; 974 975 if (d->qid >= d->handle->kinfo.num_tqps) { 976 dev_err(&d->handle->pdev->dev, 977 "queue%u is not in use\n", d->qid); 978 return -EINVAL; 979 } 980 981 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 982 result[i] = &data_str[i][0]; 983 984 pos += scnprintf(buf + pos, len - pos, 985 "Queue %u tx bd info:\n", d->qid); 986 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 987 NULL, ARRAY_SIZE(tx_bd_info_items)); 988 pos += scnprintf(buf + pos, len - pos, "%s", content); 989 990 ring = &priv->ring[d->qid]; 991 for (i = 0; i < ring->desc_num; i++) { 992 desc = &ring->desc[i]; 993 994 hns3_dump_tx_bd_info(priv, desc, result, i); 995 hns3_dbg_fill_content(content, sizeof(content), 996 tx_bd_info_items, (const char **)result, 997 ARRAY_SIZE(tx_bd_info_items)); 998 pos += scnprintf(buf + pos, len - pos, "%s", content); 999 } 1000 1001 return 0; 1002 } 1003 1004 static void 1005 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 1006 { 1007 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 1008 const char * const str[] = {"no", "yes"}; 1009 unsigned long *caps = ae_dev->caps; 1010 u32 i, state; 1011 1012 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 1013 1014 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 1015 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 1016 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 1017 hns3_dbg_cap[i].name, str[state]); 1018 } 1019 1020 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 1021 } 1022 1023 static void 1024 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 1025 { 1026 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 1027 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 1028 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1029 1030 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 1031 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 1032 dev_specs->mac_entry_num); 1033 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 1034 dev_specs->mng_entry_num); 1035 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 1036 dev_specs->max_non_tso_bd_num); 1037 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 1038 dev_specs->rss_ind_tbl_size); 1039 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 1040 dev_specs->rss_key_size); 1041 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 1042 kinfo->rss_size); 1043 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 1044 kinfo->req_rss_size); 1045 *pos += scnprintf(buf + *pos, len - *pos, 1046 "Task queue pairs numbers: %u\n", 1047 kinfo->num_tqps); 1048 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 1049 kinfo->rx_buf_len); 1050 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 1051 kinfo->num_tx_desc); 1052 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 1053 kinfo->num_rx_desc); 1054 *pos += scnprintf(buf + *pos, len - *pos, 1055 "Total number of enabled TCs: %u\n", 1056 kinfo->tc_info.num_tc); 1057 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 1058 dev_specs->int_ql_max); 1059 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 1060 dev_specs->max_int_gl); 1061 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 1062 dev_specs->max_tm_rate); 1063 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 1064 dev_specs->max_qset_num); 1065 *pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n", 1066 dev_specs->umv_size); 1067 *pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n", 1068 dev_specs->mc_mac_size); 1069 *pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n", 1070 dev_specs->mac_stats_num); 1071 } 1072 1073 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 1074 { 1075 int pos = 0; 1076 1077 hns3_dbg_dev_caps(h, buf, len, &pos); 1078 1079 hns3_dbg_dev_specs(h, buf, len, &pos); 1080 1081 return 0; 1082 } 1083 1084 static const struct hns3_dbg_item page_pool_info_items[] = { 1085 { "QUEUE_ID", 2 }, 1086 { "ALLOCATE_CNT", 2 }, 1087 { "FREE_CNT", 6 }, 1088 { "POOL_SIZE(PAGE_NUM)", 2 }, 1089 { "ORDER", 2 }, 1090 { "NUMA_ID", 2 }, 1091 { "MAX_LEN", 2 }, 1092 }; 1093 1094 static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring, 1095 char **result, u32 index) 1096 { 1097 u32 j = 0; 1098 1099 sprintf(result[j++], "%u", index); 1100 sprintf(result[j++], "%u", 1101 READ_ONCE(ring->page_pool->pages_state_hold_cnt)); 1102 sprintf(result[j++], "%d", 1103 atomic_read(&ring->page_pool->pages_state_release_cnt)); 1104 sprintf(result[j++], "%u", ring->page_pool->p.pool_size); 1105 sprintf(result[j++], "%u", ring->page_pool->p.order); 1106 sprintf(result[j++], "%d", ring->page_pool->p.nid); 1107 sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024); 1108 } 1109 1110 static int 1111 hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len) 1112 { 1113 char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN]; 1114 char *result[ARRAY_SIZE(page_pool_info_items)]; 1115 struct hns3_nic_priv *priv = h->priv; 1116 char content[HNS3_DBG_INFO_LEN]; 1117 struct hns3_enet_ring *ring; 1118 int pos = 0; 1119 u32 i; 1120 1121 if (!priv->ring) { 1122 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 1123 return -EFAULT; 1124 } 1125 1126 if (!priv->ring[h->kinfo.num_tqps].page_pool) { 1127 dev_err(&h->pdev->dev, "page pool is not initialized\n"); 1128 return -EFAULT; 1129 } 1130 1131 for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++) 1132 result[i] = &data_str[i][0]; 1133 1134 hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items, 1135 NULL, ARRAY_SIZE(page_pool_info_items)); 1136 pos += scnprintf(buf + pos, len - pos, "%s", content); 1137 for (i = 0; i < h->kinfo.num_tqps; i++) { 1138 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1139 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 1140 return -EPERM; 1141 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 1142 hns3_dump_page_pool_info(ring, result, i); 1143 hns3_dbg_fill_content(content, sizeof(content), 1144 page_pool_info_items, 1145 (const char **)result, 1146 ARRAY_SIZE(page_pool_info_items)); 1147 pos += scnprintf(buf + pos, len - pos, "%s", content); 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index) 1154 { 1155 u32 i; 1156 1157 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1158 if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) { 1159 *index = i; 1160 return 0; 1161 } 1162 } 1163 1164 dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n", 1165 dbg_data->cmd); 1166 return -EINVAL; 1167 } 1168 1169 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 1170 { 1171 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 1172 .dbg_dump = hns3_dbg_queue_map, 1173 }, 1174 { 1175 .cmd = HNAE3_DBG_CMD_DEV_INFO, 1176 .dbg_dump = hns3_dbg_dev_info, 1177 }, 1178 { 1179 .cmd = HNAE3_DBG_CMD_TX_BD, 1180 .dbg_dump_bd = hns3_dbg_tx_bd_info, 1181 }, 1182 { 1183 .cmd = HNAE3_DBG_CMD_RX_BD, 1184 .dbg_dump_bd = hns3_dbg_rx_bd_info, 1185 }, 1186 { 1187 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 1188 .dbg_dump = hns3_dbg_rx_queue_info, 1189 }, 1190 { 1191 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 1192 .dbg_dump = hns3_dbg_tx_queue_info, 1193 }, 1194 { 1195 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO, 1196 .dbg_dump = hns3_dbg_page_pool_info, 1197 }, 1198 { 1199 .cmd = HNAE3_DBG_CMD_COAL_INFO, 1200 .dbg_dump = hns3_dbg_coal_info, 1201 }, 1202 }; 1203 1204 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 1205 enum hnae3_dbg_cmd cmd, char *buf, int len) 1206 { 1207 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 1208 const struct hns3_dbg_func *cmd_func; 1209 u32 i; 1210 1211 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 1212 if (cmd == hns3_dbg_cmd_func[i].cmd) { 1213 cmd_func = &hns3_dbg_cmd_func[i]; 1214 if (cmd_func->dbg_dump) 1215 return cmd_func->dbg_dump(dbg_data->handle, buf, 1216 len); 1217 else 1218 return cmd_func->dbg_dump_bd(dbg_data, buf, 1219 len); 1220 } 1221 } 1222 1223 if (!ops->dbg_read_cmd) 1224 return -EOPNOTSUPP; 1225 1226 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 1227 } 1228 1229 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 1230 size_t count, loff_t *ppos) 1231 { 1232 struct hns3_dbg_data *dbg_data = filp->private_data; 1233 struct hnae3_handle *handle = dbg_data->handle; 1234 struct hns3_nic_priv *priv = handle->priv; 1235 ssize_t size = 0; 1236 char **save_buf; 1237 char *read_buf; 1238 u32 index; 1239 int ret; 1240 1241 ret = hns3_dbg_get_cmd_index(dbg_data, &index); 1242 if (ret) 1243 return ret; 1244 1245 mutex_lock(&handle->dbgfs_lock); 1246 save_buf = &handle->dbgfs_buf[index]; 1247 1248 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 1249 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 1250 ret = -EBUSY; 1251 goto out; 1252 } 1253 1254 if (*save_buf) { 1255 read_buf = *save_buf; 1256 } else { 1257 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 1258 if (!read_buf) { 1259 ret = -ENOMEM; 1260 goto out; 1261 } 1262 1263 /* save the buffer addr until the last read operation */ 1264 *save_buf = read_buf; 1265 1266 /* get data ready for the first time to read */ 1267 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 1268 read_buf, hns3_dbg_cmd[index].buf_len); 1269 if (ret) 1270 goto out; 1271 } 1272 1273 size = simple_read_from_buffer(buffer, count, ppos, read_buf, 1274 strlen(read_buf)); 1275 if (size > 0) { 1276 mutex_unlock(&handle->dbgfs_lock); 1277 return size; 1278 } 1279 1280 out: 1281 /* free the buffer for the last read operation */ 1282 if (*save_buf) { 1283 kvfree(*save_buf); 1284 *save_buf = NULL; 1285 } 1286 1287 mutex_unlock(&handle->dbgfs_lock); 1288 return ret; 1289 } 1290 1291 static const struct file_operations hns3_dbg_fops = { 1292 .owner = THIS_MODULE, 1293 .open = simple_open, 1294 .read = hns3_dbg_read, 1295 }; 1296 1297 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 1298 { 1299 struct dentry *entry_dir; 1300 struct hns3_dbg_data *data; 1301 u16 max_queue_num; 1302 unsigned int i; 1303 1304 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1305 max_queue_num = hns3_get_max_available_channels(handle); 1306 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 1307 GFP_KERNEL); 1308 if (!data) 1309 return -ENOMEM; 1310 1311 for (i = 0; i < max_queue_num; i++) { 1312 char name[HNS3_DBG_FILE_NAME_LEN]; 1313 1314 data[i].handle = handle; 1315 data[i].cmd = hns3_dbg_cmd[cmd].cmd; 1316 data[i].qid = i; 1317 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1318 debugfs_create_file(name, 0400, entry_dir, &data[i], 1319 &hns3_dbg_fops); 1320 } 1321 1322 return 0; 1323 } 1324 1325 static int 1326 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1327 { 1328 struct hns3_dbg_data *data; 1329 struct dentry *entry_dir; 1330 1331 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1332 if (!data) 1333 return -ENOMEM; 1334 1335 data->handle = handle; 1336 data->cmd = hns3_dbg_cmd[cmd].cmd; 1337 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1338 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1339 data, &hns3_dbg_fops); 1340 1341 return 0; 1342 } 1343 1344 int hns3_dbg_init(struct hnae3_handle *handle) 1345 { 1346 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1347 const char *name = pci_name(handle->pdev); 1348 int ret; 1349 u32 i; 1350 1351 handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev, 1352 ARRAY_SIZE(hns3_dbg_cmd), 1353 sizeof(*handle->dbgfs_buf), 1354 GFP_KERNEL); 1355 if (!handle->dbgfs_buf) 1356 return -ENOMEM; 1357 1358 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1359 debugfs_create_dir(name, hns3_dbgfs_root); 1360 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1361 1362 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1363 hns3_dbg_dentry[i].dentry = 1364 debugfs_create_dir(hns3_dbg_dentry[i].name, 1365 handle->hnae3_dbgfs); 1366 1367 mutex_init(&handle->dbgfs_lock); 1368 1369 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1370 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1371 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) || 1372 (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO && 1373 !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps))) 1374 continue; 1375 1376 if (!hns3_dbg_cmd[i].init) { 1377 dev_err(&handle->pdev->dev, 1378 "cmd %s lack of init func\n", 1379 hns3_dbg_cmd[i].name); 1380 ret = -EINVAL; 1381 goto out; 1382 } 1383 1384 ret = hns3_dbg_cmd[i].init(handle, i); 1385 if (ret) { 1386 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1387 hns3_dbg_cmd[i].name); 1388 goto out; 1389 } 1390 } 1391 1392 return 0; 1393 1394 out: 1395 mutex_destroy(&handle->dbgfs_lock); 1396 debugfs_remove_recursive(handle->hnae3_dbgfs); 1397 handle->hnae3_dbgfs = NULL; 1398 return ret; 1399 } 1400 1401 void hns3_dbg_uninit(struct hnae3_handle *handle) 1402 { 1403 u32 i; 1404 1405 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1406 if (handle->dbgfs_buf[i]) { 1407 kvfree(handle->dbgfs_buf[i]); 1408 handle->dbgfs_buf[i] = NULL; 1409 } 1410 1411 mutex_destroy(&handle->dbgfs_lock); 1412 debugfs_remove_recursive(handle->hnae3_dbgfs); 1413 handle->hnae3_dbgfs = NULL; 1414 } 1415 1416 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1417 { 1418 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1419 } 1420 1421 void hns3_dbg_unregister_debugfs(void) 1422 { 1423 debugfs_remove_recursive(hns3_dbgfs_root); 1424 hns3_dbgfs_root = NULL; 1425 } 1426