1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/device.h> 6 7 #include "hnae3.h" 8 #include "hns3_debugfs.h" 9 #include "hns3_enet.h" 10 11 static struct dentry *hns3_dbgfs_root; 12 13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = { 14 { 15 .name = "tm" 16 }, 17 { 18 .name = "tx_bd_info" 19 }, 20 { 21 .name = "rx_bd_info" 22 }, 23 { 24 .name = "mac_list" 25 }, 26 { 27 .name = "reg" 28 }, 29 { 30 .name = "queue" 31 }, 32 { 33 .name = "fd" 34 }, 35 /* keep common at the bottom and add new directory above */ 36 { 37 .name = "common" 38 }, 39 }; 40 41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd); 42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, 43 unsigned int cmd); 44 45 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = { 46 { 47 .name = "tm_nodes", 48 .cmd = HNAE3_DBG_CMD_TM_NODES, 49 .dentry = HNS3_DBG_DENTRY_TM, 50 .buf_len = HNS3_DBG_READ_LEN, 51 .init = hns3_dbg_common_file_init, 52 }, 53 { 54 .name = "tm_priority", 55 .cmd = HNAE3_DBG_CMD_TM_PRI, 56 .dentry = HNS3_DBG_DENTRY_TM, 57 .buf_len = HNS3_DBG_READ_LEN, 58 .init = hns3_dbg_common_file_init, 59 }, 60 { 61 .name = "tm_qset", 62 .cmd = HNAE3_DBG_CMD_TM_QSET, 63 .dentry = HNS3_DBG_DENTRY_TM, 64 .buf_len = HNS3_DBG_READ_LEN, 65 .init = hns3_dbg_common_file_init, 66 }, 67 { 68 .name = "tm_map", 69 .cmd = HNAE3_DBG_CMD_TM_MAP, 70 .dentry = HNS3_DBG_DENTRY_TM, 71 .buf_len = HNS3_DBG_READ_LEN_1MB, 72 .init = hns3_dbg_common_file_init, 73 }, 74 { 75 .name = "tm_pg", 76 .cmd = HNAE3_DBG_CMD_TM_PG, 77 .dentry = HNS3_DBG_DENTRY_TM, 78 .buf_len = HNS3_DBG_READ_LEN, 79 .init = hns3_dbg_common_file_init, 80 }, 81 { 82 .name = "tm_port", 83 .cmd = HNAE3_DBG_CMD_TM_PORT, 84 .dentry = HNS3_DBG_DENTRY_TM, 85 .buf_len = HNS3_DBG_READ_LEN, 86 .init = hns3_dbg_common_file_init, 87 }, 88 { 89 .name = "tc_sch_info", 90 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 91 .dentry = HNS3_DBG_DENTRY_TM, 92 .buf_len = HNS3_DBG_READ_LEN, 93 .init = hns3_dbg_common_file_init, 94 }, 95 { 96 .name = "qos_pause_cfg", 97 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 98 .dentry = HNS3_DBG_DENTRY_TM, 99 .buf_len = HNS3_DBG_READ_LEN, 100 .init = hns3_dbg_common_file_init, 101 }, 102 { 103 .name = "qos_pri_map", 104 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 105 .dentry = HNS3_DBG_DENTRY_TM, 106 .buf_len = HNS3_DBG_READ_LEN, 107 .init = hns3_dbg_common_file_init, 108 }, 109 { 110 .name = "qos_buf_cfg", 111 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 112 .dentry = HNS3_DBG_DENTRY_TM, 113 .buf_len = HNS3_DBG_READ_LEN, 114 .init = hns3_dbg_common_file_init, 115 }, 116 { 117 .name = "dev_info", 118 .cmd = HNAE3_DBG_CMD_DEV_INFO, 119 .dentry = HNS3_DBG_DENTRY_COMMON, 120 .buf_len = HNS3_DBG_READ_LEN, 121 .init = hns3_dbg_common_file_init, 122 }, 123 { 124 .name = "tx_bd_queue", 125 .cmd = HNAE3_DBG_CMD_TX_BD, 126 .dentry = HNS3_DBG_DENTRY_TX_BD, 127 .buf_len = HNS3_DBG_READ_LEN_4MB, 128 .init = hns3_dbg_bd_file_init, 129 }, 130 { 131 .name = "rx_bd_queue", 132 .cmd = HNAE3_DBG_CMD_RX_BD, 133 .dentry = HNS3_DBG_DENTRY_RX_BD, 134 .buf_len = HNS3_DBG_READ_LEN_4MB, 135 .init = hns3_dbg_bd_file_init, 136 }, 137 { 138 .name = "uc", 139 .cmd = HNAE3_DBG_CMD_MAC_UC, 140 .dentry = HNS3_DBG_DENTRY_MAC, 141 .buf_len = HNS3_DBG_READ_LEN, 142 .init = hns3_dbg_common_file_init, 143 }, 144 { 145 .name = "mc", 146 .cmd = HNAE3_DBG_CMD_MAC_MC, 147 .dentry = HNS3_DBG_DENTRY_MAC, 148 .buf_len = HNS3_DBG_READ_LEN, 149 .init = hns3_dbg_common_file_init, 150 }, 151 { 152 .name = "mng_tbl", 153 .cmd = HNAE3_DBG_CMD_MNG_TBL, 154 .dentry = HNS3_DBG_DENTRY_COMMON, 155 .buf_len = HNS3_DBG_READ_LEN, 156 .init = hns3_dbg_common_file_init, 157 }, 158 { 159 .name = "loopback", 160 .cmd = HNAE3_DBG_CMD_LOOPBACK, 161 .dentry = HNS3_DBG_DENTRY_COMMON, 162 .buf_len = HNS3_DBG_READ_LEN, 163 .init = hns3_dbg_common_file_init, 164 }, 165 { 166 .name = "interrupt_info", 167 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 168 .dentry = HNS3_DBG_DENTRY_COMMON, 169 .buf_len = HNS3_DBG_READ_LEN, 170 .init = hns3_dbg_common_file_init, 171 }, 172 { 173 .name = "reset_info", 174 .cmd = HNAE3_DBG_CMD_RESET_INFO, 175 .dentry = HNS3_DBG_DENTRY_COMMON, 176 .buf_len = HNS3_DBG_READ_LEN, 177 .init = hns3_dbg_common_file_init, 178 }, 179 { 180 .name = "imp_info", 181 .cmd = HNAE3_DBG_CMD_IMP_INFO, 182 .dentry = HNS3_DBG_DENTRY_COMMON, 183 .buf_len = HNS3_DBG_READ_LEN, 184 .init = hns3_dbg_common_file_init, 185 }, 186 { 187 .name = "ncl_config", 188 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 189 .dentry = HNS3_DBG_DENTRY_COMMON, 190 .buf_len = HNS3_DBG_READ_LEN_128KB, 191 .init = hns3_dbg_common_file_init, 192 }, 193 { 194 .name = "mac_tnl_status", 195 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 196 .dentry = HNS3_DBG_DENTRY_COMMON, 197 .buf_len = HNS3_DBG_READ_LEN, 198 .init = hns3_dbg_common_file_init, 199 }, 200 { 201 .name = "bios_common", 202 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 203 .dentry = HNS3_DBG_DENTRY_REG, 204 .buf_len = HNS3_DBG_READ_LEN, 205 .init = hns3_dbg_common_file_init, 206 }, 207 { 208 .name = "ssu", 209 .cmd = HNAE3_DBG_CMD_REG_SSU, 210 .dentry = HNS3_DBG_DENTRY_REG, 211 .buf_len = HNS3_DBG_READ_LEN, 212 .init = hns3_dbg_common_file_init, 213 }, 214 { 215 .name = "igu_egu", 216 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 217 .dentry = HNS3_DBG_DENTRY_REG, 218 .buf_len = HNS3_DBG_READ_LEN, 219 .init = hns3_dbg_common_file_init, 220 }, 221 { 222 .name = "rpu", 223 .cmd = HNAE3_DBG_CMD_REG_RPU, 224 .dentry = HNS3_DBG_DENTRY_REG, 225 .buf_len = HNS3_DBG_READ_LEN, 226 .init = hns3_dbg_common_file_init, 227 }, 228 { 229 .name = "ncsi", 230 .cmd = HNAE3_DBG_CMD_REG_NCSI, 231 .dentry = HNS3_DBG_DENTRY_REG, 232 .buf_len = HNS3_DBG_READ_LEN, 233 .init = hns3_dbg_common_file_init, 234 }, 235 { 236 .name = "rtc", 237 .cmd = HNAE3_DBG_CMD_REG_RTC, 238 .dentry = HNS3_DBG_DENTRY_REG, 239 .buf_len = HNS3_DBG_READ_LEN, 240 .init = hns3_dbg_common_file_init, 241 }, 242 { 243 .name = "ppp", 244 .cmd = HNAE3_DBG_CMD_REG_PPP, 245 .dentry = HNS3_DBG_DENTRY_REG, 246 .buf_len = HNS3_DBG_READ_LEN, 247 .init = hns3_dbg_common_file_init, 248 }, 249 { 250 .name = "rcb", 251 .cmd = HNAE3_DBG_CMD_REG_RCB, 252 .dentry = HNS3_DBG_DENTRY_REG, 253 .buf_len = HNS3_DBG_READ_LEN, 254 .init = hns3_dbg_common_file_init, 255 }, 256 { 257 .name = "tqp", 258 .cmd = HNAE3_DBG_CMD_REG_TQP, 259 .dentry = HNS3_DBG_DENTRY_REG, 260 .buf_len = HNS3_DBG_READ_LEN, 261 .init = hns3_dbg_common_file_init, 262 }, 263 { 264 .name = "mac", 265 .cmd = HNAE3_DBG_CMD_REG_MAC, 266 .dentry = HNS3_DBG_DENTRY_REG, 267 .buf_len = HNS3_DBG_READ_LEN, 268 .init = hns3_dbg_common_file_init, 269 }, 270 { 271 .name = "dcb", 272 .cmd = HNAE3_DBG_CMD_REG_DCB, 273 .dentry = HNS3_DBG_DENTRY_REG, 274 .buf_len = HNS3_DBG_READ_LEN, 275 .init = hns3_dbg_common_file_init, 276 }, 277 { 278 .name = "queue_map", 279 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 280 .dentry = HNS3_DBG_DENTRY_QUEUE, 281 .buf_len = HNS3_DBG_READ_LEN, 282 .init = hns3_dbg_common_file_init, 283 }, 284 { 285 .name = "rx_queue_info", 286 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 287 .dentry = HNS3_DBG_DENTRY_QUEUE, 288 .buf_len = HNS3_DBG_READ_LEN_1MB, 289 .init = hns3_dbg_common_file_init, 290 }, 291 { 292 .name = "tx_queue_info", 293 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 294 .dentry = HNS3_DBG_DENTRY_QUEUE, 295 .buf_len = HNS3_DBG_READ_LEN_1MB, 296 .init = hns3_dbg_common_file_init, 297 }, 298 { 299 .name = "fd_tcam", 300 .cmd = HNAE3_DBG_CMD_FD_TCAM, 301 .dentry = HNS3_DBG_DENTRY_FD, 302 .buf_len = HNS3_DBG_READ_LEN, 303 .init = hns3_dbg_common_file_init, 304 }, 305 { 306 .name = "service_task_info", 307 .cmd = HNAE3_DBG_CMD_SERV_INFO, 308 .dentry = HNS3_DBG_DENTRY_COMMON, 309 .buf_len = HNS3_DBG_READ_LEN, 310 .init = hns3_dbg_common_file_init, 311 }, 312 }; 313 314 static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 315 { 316 .name = "support FD", 317 .cap_bit = HNAE3_DEV_SUPPORT_FD_B, 318 }, { 319 .name = "support GRO", 320 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B, 321 }, { 322 .name = "support FEC", 323 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B, 324 }, { 325 .name = "support UDP GSO", 326 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B, 327 }, { 328 .name = "support PTP", 329 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B, 330 }, { 331 .name = "support INT QL", 332 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B, 333 }, { 334 .name = "support HW TX csum", 335 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 336 }, { 337 .name = "support UDP tunnel csum", 338 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 339 }, { 340 .name = "support TX push", 341 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B, 342 }, { 343 .name = "support imp-controlled PHY", 344 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B, 345 }, { 346 .name = "support rxd advanced layout", 347 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 348 }, 349 }; 350 351 static void hns3_dbg_fill_content(char *content, u16 len, 352 const struct hns3_dbg_item *items, 353 const char **result, u16 size) 354 { 355 char *pos = content; 356 u16 i; 357 358 memset(content, ' ', len); 359 for (i = 0; i < size; i++) { 360 if (result) 361 strncpy(pos, result[i], strlen(result[i])); 362 else 363 strncpy(pos, items[i].name, strlen(items[i].name)); 364 365 pos += strlen(items[i].name) + items[i].interval; 366 } 367 368 *pos++ = '\n'; 369 *pos++ = '\0'; 370 } 371 372 static const struct hns3_dbg_item rx_queue_info_items[] = { 373 { "QUEUE_ID", 2 }, 374 { "BD_NUM", 2 }, 375 { "BD_LEN", 2 }, 376 { "TAIL", 2 }, 377 { "HEAD", 2 }, 378 { "FBDNUM", 2 }, 379 { "PKTNUM", 2 }, 380 { "RING_EN", 2 }, 381 { "RX_RING_EN", 2 }, 382 { "BASE_ADDR", 10 }, 383 }; 384 385 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring, 386 struct hnae3_ae_dev *ae_dev, char **result, 387 u32 index) 388 { 389 u32 base_add_l, base_add_h; 390 u32 j = 0; 391 392 sprintf(result[j++], "%8u", index); 393 394 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 395 HNS3_RING_RX_RING_BD_NUM_REG)); 396 397 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 398 HNS3_RING_RX_RING_BD_LEN_REG)); 399 400 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 401 HNS3_RING_RX_RING_TAIL_REG)); 402 403 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 404 HNS3_RING_RX_RING_HEAD_REG)); 405 406 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 407 HNS3_RING_RX_RING_FBDNUM_REG)); 408 409 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 410 HNS3_RING_RX_RING_PKTNUM_RECORD_REG)); 411 412 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 413 HNS3_RING_EN_REG) ? "on" : "off"); 414 415 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 416 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 417 HNS3_RING_RX_EN_REG) ? "on" : "off"); 418 else 419 sprintf(result[j++], "%10s", "NA"); 420 421 base_add_h = readl_relaxed(ring->tqp->io_base + 422 HNS3_RING_RX_RING_BASEADDR_H_REG); 423 base_add_l = readl_relaxed(ring->tqp->io_base + 424 HNS3_RING_RX_RING_BASEADDR_L_REG); 425 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 426 } 427 428 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h, 429 char *buf, int len) 430 { 431 char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 432 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 433 char *result[ARRAY_SIZE(rx_queue_info_items)]; 434 struct hns3_nic_priv *priv = h->priv; 435 char content[HNS3_DBG_INFO_LEN]; 436 struct hns3_enet_ring *ring; 437 int pos = 0; 438 u32 i; 439 440 if (!priv->ring) { 441 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 442 return -EFAULT; 443 } 444 445 for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++) 446 result[i] = &data_str[i][0]; 447 448 hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items, 449 NULL, ARRAY_SIZE(rx_queue_info_items)); 450 pos += scnprintf(buf + pos, len - pos, "%s", content); 451 for (i = 0; i < h->kinfo.num_tqps; i++) { 452 /* Each cycle needs to determine whether the instance is reset, 453 * to prevent reference to invalid memory. And need to ensure 454 * that the following code is executed within 100ms. 455 */ 456 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 457 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 458 return -EPERM; 459 460 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)]; 461 hns3_dump_rx_queue_info(ring, ae_dev, result, i); 462 hns3_dbg_fill_content(content, sizeof(content), 463 rx_queue_info_items, 464 (const char **)result, 465 ARRAY_SIZE(rx_queue_info_items)); 466 pos += scnprintf(buf + pos, len - pos, "%s", content); 467 } 468 469 return 0; 470 } 471 472 static const struct hns3_dbg_item tx_queue_info_items[] = { 473 { "QUEUE_ID", 2 }, 474 { "BD_NUM", 2 }, 475 { "TC", 2 }, 476 { "TAIL", 2 }, 477 { "HEAD", 2 }, 478 { "FBDNUM", 2 }, 479 { "OFFSET", 2 }, 480 { "PKTNUM", 2 }, 481 { "RING_EN", 2 }, 482 { "TX_RING_EN", 2 }, 483 { "BASE_ADDR", 10 }, 484 }; 485 486 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring, 487 struct hnae3_ae_dev *ae_dev, char **result, 488 u32 index) 489 { 490 u32 base_add_l, base_add_h; 491 u32 j = 0; 492 493 sprintf(result[j++], "%8u", index); 494 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 495 HNS3_RING_TX_RING_BD_NUM_REG)); 496 497 sprintf(result[j++], "%2u", readl_relaxed(ring->tqp->io_base + 498 HNS3_RING_TX_RING_TC_REG)); 499 500 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 501 HNS3_RING_TX_RING_TAIL_REG)); 502 503 sprintf(result[j++], "%4u", readl_relaxed(ring->tqp->io_base + 504 HNS3_RING_TX_RING_HEAD_REG)); 505 506 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 507 HNS3_RING_TX_RING_FBDNUM_REG)); 508 509 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 510 HNS3_RING_TX_RING_OFFSET_REG)); 511 512 sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base + 513 HNS3_RING_TX_RING_PKTNUM_RECORD_REG)); 514 515 sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base + 516 HNS3_RING_EN_REG) ? "on" : "off"); 517 518 if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev)) 519 sprintf(result[j++], "%10s", readl_relaxed(ring->tqp->io_base + 520 HNS3_RING_TX_EN_REG) ? "on" : "off"); 521 else 522 sprintf(result[j++], "%10s", "NA"); 523 524 base_add_h = readl_relaxed(ring->tqp->io_base + 525 HNS3_RING_TX_RING_BASEADDR_H_REG); 526 base_add_l = readl_relaxed(ring->tqp->io_base + 527 HNS3_RING_TX_RING_BASEADDR_L_REG); 528 sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l); 529 } 530 531 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h, 532 char *buf, int len) 533 { 534 char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN]; 535 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 536 char *result[ARRAY_SIZE(tx_queue_info_items)]; 537 struct hns3_nic_priv *priv = h->priv; 538 char content[HNS3_DBG_INFO_LEN]; 539 struct hns3_enet_ring *ring; 540 int pos = 0; 541 u32 i; 542 543 if (!priv->ring) { 544 dev_err(&h->pdev->dev, "priv->ring is NULL\n"); 545 return -EFAULT; 546 } 547 548 for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++) 549 result[i] = &data_str[i][0]; 550 551 hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items, 552 NULL, ARRAY_SIZE(tx_queue_info_items)); 553 pos += scnprintf(buf + pos, len - pos, "%s", content); 554 555 for (i = 0; i < h->kinfo.num_tqps; i++) { 556 /* Each cycle needs to determine whether the instance is reset, 557 * to prevent reference to invalid memory. And need to ensure 558 * that the following code is executed within 100ms. 559 */ 560 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 561 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 562 return -EPERM; 563 564 ring = &priv->ring[i]; 565 hns3_dump_tx_queue_info(ring, ae_dev, result, i); 566 hns3_dbg_fill_content(content, sizeof(content), 567 tx_queue_info_items, 568 (const char **)result, 569 ARRAY_SIZE(tx_queue_info_items)); 570 pos += scnprintf(buf + pos, len - pos, "%s", content); 571 } 572 573 return 0; 574 } 575 576 static const struct hns3_dbg_item queue_map_items[] = { 577 { "local_queue_id", 2 }, 578 { "global_queue_id", 2 }, 579 { "vector_id", 2 }, 580 }; 581 582 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len) 583 { 584 char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN]; 585 char *result[ARRAY_SIZE(queue_map_items)]; 586 struct hns3_nic_priv *priv = h->priv; 587 char content[HNS3_DBG_INFO_LEN]; 588 int pos = 0; 589 int j; 590 u32 i; 591 592 if (!h->ae_algo->ops->get_global_queue_id) 593 return -EOPNOTSUPP; 594 595 for (i = 0; i < ARRAY_SIZE(queue_map_items); i++) 596 result[i] = &data_str[i][0]; 597 598 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 599 NULL, ARRAY_SIZE(queue_map_items)); 600 pos += scnprintf(buf + pos, len - pos, "%s", content); 601 for (i = 0; i < h->kinfo.num_tqps; i++) { 602 if (!priv->ring || !priv->ring[i].tqp_vector) 603 continue; 604 j = 0; 605 sprintf(result[j++], "%u", i); 606 sprintf(result[j++], "%u", 607 h->ae_algo->ops->get_global_queue_id(h, i)); 608 sprintf(result[j++], "%u", 609 priv->ring[i].tqp_vector->vector_irq); 610 hns3_dbg_fill_content(content, sizeof(content), queue_map_items, 611 (const char **)result, 612 ARRAY_SIZE(queue_map_items)); 613 pos += scnprintf(buf + pos, len - pos, "%s", content); 614 } 615 616 return 0; 617 } 618 619 static const struct hns3_dbg_item rx_bd_info_items[] = { 620 { "BD_IDX", 3 }, 621 { "L234_INFO", 2 }, 622 { "PKT_LEN", 3 }, 623 { "SIZE", 4 }, 624 { "RSS_HASH", 4 }, 625 { "FD_ID", 2 }, 626 { "VLAN_TAG", 2 }, 627 { "O_DM_VLAN_ID_FB", 2 }, 628 { "OT_VLAN_TAG", 2 }, 629 { "BD_BASE_INFO", 2 }, 630 { "PTYPE", 2 }, 631 { "HW_CSUM", 2 }, 632 }; 633 634 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv, 635 struct hns3_desc *desc, char **result, int idx) 636 { 637 unsigned int j = 0; 638 639 sprintf(result[j++], "%5d", idx); 640 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info)); 641 sprintf(result[j++], "%7u", le16_to_cpu(desc->rx.pkt_len)); 642 sprintf(result[j++], "%4u", le16_to_cpu(desc->rx.size)); 643 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash)); 644 sprintf(result[j++], "%5u", le16_to_cpu(desc->rx.fd_id)); 645 sprintf(result[j++], "%8u", le16_to_cpu(desc->rx.vlan_tag)); 646 sprintf(result[j++], "%15u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb)); 647 sprintf(result[j++], "%11u", le16_to_cpu(desc->rx.ot_vlan_tag)); 648 sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info)); 649 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 650 u32 ol_info = le32_to_cpu(desc->rx.ol_info); 651 652 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info, 653 HNS3_RXD_PTYPE_M, 654 HNS3_RXD_PTYPE_S)); 655 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum)); 656 } else { 657 sprintf(result[j++], "NA"); 658 sprintf(result[j++], "NA"); 659 } 660 } 661 662 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 663 { 664 char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 665 struct hns3_nic_priv *priv = d->handle->priv; 666 char *result[ARRAY_SIZE(rx_bd_info_items)]; 667 char content[HNS3_DBG_INFO_LEN]; 668 struct hns3_enet_ring *ring; 669 struct hns3_desc *desc; 670 unsigned int i; 671 int pos = 0; 672 673 if (d->qid >= d->handle->kinfo.num_tqps) { 674 dev_err(&d->handle->pdev->dev, 675 "queue%u is not in use\n", d->qid); 676 return -EINVAL; 677 } 678 679 for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++) 680 result[i] = &data_str[i][0]; 681 682 pos += scnprintf(buf + pos, len - pos, 683 "Queue %u rx bd info:\n", d->qid); 684 hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items, 685 NULL, ARRAY_SIZE(rx_bd_info_items)); 686 pos += scnprintf(buf + pos, len - pos, "%s", content); 687 688 ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps]; 689 for (i = 0; i < ring->desc_num; i++) { 690 desc = &ring->desc[i]; 691 692 hns3_dump_rx_bd_info(priv, desc, result, i); 693 hns3_dbg_fill_content(content, sizeof(content), 694 rx_bd_info_items, (const char **)result, 695 ARRAY_SIZE(rx_bd_info_items)); 696 pos += scnprintf(buf + pos, len - pos, "%s", content); 697 } 698 699 return 0; 700 } 701 702 static const struct hns3_dbg_item tx_bd_info_items[] = { 703 { "BD_IDX", 5 }, 704 { "ADDRESS", 2 }, 705 { "VLAN_TAG", 2 }, 706 { "SIZE", 2 }, 707 { "T_CS_VLAN_TSO", 2 }, 708 { "OT_VLAN_TAG", 3 }, 709 { "TV", 2 }, 710 { "OLT_VLAN_LEN", 2}, 711 { "PAYLEN_OL4CS", 2}, 712 { "BD_FE_SC_VLD", 2}, 713 { "MSS_HW_CSUM", 0}, 714 }; 715 716 static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv, 717 struct hns3_desc *desc, char **result, int idx) 718 { 719 unsigned int j = 0; 720 721 sprintf(result[j++], "%6d", idx); 722 sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr)); 723 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.vlan_tag)); 724 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.send_size)); 725 sprintf(result[j++], "%#x", 726 le32_to_cpu(desc->tx.type_cs_vlan_tso_len)); 727 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.outer_vlan_tag)); 728 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv)); 729 sprintf(result[j++], "%10u", 730 le32_to_cpu(desc->tx.ol_type_vlan_len_msec)); 731 sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs)); 732 sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri)); 733 sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum)); 734 } 735 736 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len) 737 { 738 char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN]; 739 struct hns3_nic_priv *priv = d->handle->priv; 740 char *result[ARRAY_SIZE(tx_bd_info_items)]; 741 char content[HNS3_DBG_INFO_LEN]; 742 struct hns3_enet_ring *ring; 743 struct hns3_desc *desc; 744 unsigned int i; 745 int pos = 0; 746 747 if (d->qid >= d->handle->kinfo.num_tqps) { 748 dev_err(&d->handle->pdev->dev, 749 "queue%u is not in use\n", d->qid); 750 return -EINVAL; 751 } 752 753 for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++) 754 result[i] = &data_str[i][0]; 755 756 pos += scnprintf(buf + pos, len - pos, 757 "Queue %u tx bd info:\n", d->qid); 758 hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items, 759 NULL, ARRAY_SIZE(tx_bd_info_items)); 760 pos += scnprintf(buf + pos, len - pos, "%s", content); 761 762 ring = &priv->ring[d->qid]; 763 for (i = 0; i < ring->desc_num; i++) { 764 desc = &ring->desc[i]; 765 766 hns3_dump_tx_bd_info(priv, desc, result, i); 767 hns3_dbg_fill_content(content, sizeof(content), 768 tx_bd_info_items, (const char **)result, 769 ARRAY_SIZE(tx_bd_info_items)); 770 pos += scnprintf(buf + pos, len - pos, "%s", content); 771 } 772 773 return 0; 774 } 775 776 static void 777 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos) 778 { 779 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 780 static const char * const str[] = {"no", "yes"}; 781 unsigned long *caps = ae_dev->caps; 782 u32 i, state; 783 784 *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n"); 785 786 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) { 787 state = test_bit(hns3_dbg_cap[i].cap_bit, caps); 788 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n", 789 hns3_dbg_cap[i].name, str[state]); 790 } 791 792 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 793 } 794 795 static void 796 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 797 { 798 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev); 799 struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs; 800 struct hnae3_knic_private_info *kinfo = &h->kinfo; 801 802 *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n"); 803 *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n", 804 dev_specs->mac_entry_num); 805 *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n", 806 dev_specs->mng_entry_num); 807 *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n", 808 dev_specs->max_non_tso_bd_num); 809 *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n", 810 dev_specs->rss_ind_tbl_size); 811 *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n", 812 dev_specs->rss_key_size); 813 *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n", 814 kinfo->rss_size); 815 *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n", 816 kinfo->req_rss_size); 817 *pos += scnprintf(buf + *pos, len - *pos, 818 "Task queue pairs numbers: %u\n", 819 kinfo->num_tqps); 820 *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n", 821 kinfo->rx_buf_len); 822 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n", 823 kinfo->num_tx_desc); 824 *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n", 825 kinfo->num_rx_desc); 826 *pos += scnprintf(buf + *pos, len - *pos, 827 "Total number of enabled TCs: %u\n", 828 kinfo->tc_info.num_tc); 829 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n", 830 dev_specs->int_ql_max); 831 *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n", 832 dev_specs->max_int_gl); 833 *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n", 834 dev_specs->max_tm_rate); 835 *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n", 836 dev_specs->max_qset_num); 837 } 838 839 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len) 840 { 841 int pos = 0; 842 843 hns3_dbg_dev_caps(h, buf, len, &pos); 844 845 hns3_dbg_dev_specs(h, buf, len, &pos); 846 847 return 0; 848 } 849 850 static int hns3_dbg_get_cmd_index(struct hnae3_handle *handle, 851 const unsigned char *name, u32 *index) 852 { 853 u32 i; 854 855 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 856 if (!strncmp(name, hns3_dbg_cmd[i].name, 857 strlen(hns3_dbg_cmd[i].name))) { 858 *index = i; 859 return 0; 860 } 861 } 862 863 dev_err(&handle->pdev->dev, "unknown command(%s)\n", name); 864 return -EINVAL; 865 } 866 867 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = { 868 { 869 .cmd = HNAE3_DBG_CMD_QUEUE_MAP, 870 .dbg_dump = hns3_dbg_queue_map, 871 }, 872 { 873 .cmd = HNAE3_DBG_CMD_DEV_INFO, 874 .dbg_dump = hns3_dbg_dev_info, 875 }, 876 { 877 .cmd = HNAE3_DBG_CMD_TX_BD, 878 .dbg_dump_bd = hns3_dbg_tx_bd_info, 879 }, 880 { 881 .cmd = HNAE3_DBG_CMD_RX_BD, 882 .dbg_dump_bd = hns3_dbg_rx_bd_info, 883 }, 884 { 885 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO, 886 .dbg_dump = hns3_dbg_rx_queue_info, 887 }, 888 { 889 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO, 890 .dbg_dump = hns3_dbg_tx_queue_info, 891 }, 892 }; 893 894 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data, 895 enum hnae3_dbg_cmd cmd, char *buf, int len) 896 { 897 const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops; 898 const struct hns3_dbg_func *cmd_func; 899 u32 i; 900 901 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) { 902 if (cmd == hns3_dbg_cmd_func[i].cmd) { 903 cmd_func = &hns3_dbg_cmd_func[i]; 904 if (cmd_func->dbg_dump) 905 return cmd_func->dbg_dump(dbg_data->handle, buf, 906 len); 907 else 908 return cmd_func->dbg_dump_bd(dbg_data, buf, 909 len); 910 } 911 } 912 913 if (!ops->dbg_read_cmd) 914 return -EOPNOTSUPP; 915 916 return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len); 917 } 918 919 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, 920 size_t count, loff_t *ppos) 921 { 922 struct hns3_dbg_data *dbg_data = filp->private_data; 923 struct hnae3_handle *handle = dbg_data->handle; 924 struct hns3_nic_priv *priv = handle->priv; 925 ssize_t size = 0; 926 char **save_buf; 927 char *read_buf; 928 u32 index; 929 int ret; 930 931 ret = hns3_dbg_get_cmd_index(handle, filp->f_path.dentry->d_iname, 932 &index); 933 if (ret) 934 return ret; 935 936 save_buf = &hns3_dbg_cmd[index].buf; 937 938 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) || 939 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) { 940 ret = -EBUSY; 941 goto out; 942 } 943 944 if (*save_buf) { 945 read_buf = *save_buf; 946 } else { 947 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL); 948 if (!read_buf) 949 return -ENOMEM; 950 951 /* save the buffer addr until the last read operation */ 952 *save_buf = read_buf; 953 } 954 955 /* get data ready for the first time to read */ 956 if (!*ppos) { 957 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd, 958 read_buf, hns3_dbg_cmd[index].buf_len); 959 if (ret) 960 goto out; 961 } 962 963 size = simple_read_from_buffer(buffer, count, ppos, read_buf, 964 strlen(read_buf)); 965 if (size > 0) 966 return size; 967 968 out: 969 /* free the buffer for the last read operation */ 970 if (*save_buf) { 971 kvfree(*save_buf); 972 *save_buf = NULL; 973 } 974 975 return ret; 976 } 977 978 static const struct file_operations hns3_dbg_fops = { 979 .owner = THIS_MODULE, 980 .open = simple_open, 981 .read = hns3_dbg_read, 982 }; 983 984 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd) 985 { 986 struct dentry *entry_dir; 987 struct hns3_dbg_data *data; 988 u16 max_queue_num; 989 unsigned int i; 990 991 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 992 max_queue_num = hns3_get_max_available_channels(handle); 993 data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data), 994 GFP_KERNEL); 995 if (!data) 996 return -ENOMEM; 997 998 for (i = 0; i < max_queue_num; i++) { 999 char name[HNS3_DBG_FILE_NAME_LEN]; 1000 1001 data[i].handle = handle; 1002 data[i].qid = i; 1003 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i); 1004 debugfs_create_file(name, 0400, entry_dir, &data[i], 1005 &hns3_dbg_fops); 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int 1012 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd) 1013 { 1014 struct hns3_dbg_data *data; 1015 struct dentry *entry_dir; 1016 1017 data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL); 1018 if (!data) 1019 return -ENOMEM; 1020 1021 data->handle = handle; 1022 entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry; 1023 debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir, 1024 data, &hns3_dbg_fops); 1025 1026 return 0; 1027 } 1028 1029 int hns3_dbg_init(struct hnae3_handle *handle) 1030 { 1031 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 1032 const char *name = pci_name(handle->pdev); 1033 int ret; 1034 u32 i; 1035 1036 hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry = 1037 debugfs_create_dir(name, hns3_dbgfs_root); 1038 handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry; 1039 1040 for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++) 1041 hns3_dbg_dentry[i].dentry = 1042 debugfs_create_dir(hns3_dbg_dentry[i].name, 1043 handle->hnae3_dbgfs); 1044 1045 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) { 1046 if (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES && 1047 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 1048 continue; 1049 1050 if (!hns3_dbg_cmd[i].init) { 1051 dev_err(&handle->pdev->dev, 1052 "cmd %s lack of init func\n", 1053 hns3_dbg_cmd[i].name); 1054 ret = -EINVAL; 1055 goto out; 1056 } 1057 1058 ret = hns3_dbg_cmd[i].init(handle, i); 1059 if (ret) { 1060 dev_err(&handle->pdev->dev, "failed to init cmd %s\n", 1061 hns3_dbg_cmd[i].name); 1062 goto out; 1063 } 1064 } 1065 1066 return 0; 1067 1068 out: 1069 debugfs_remove_recursive(handle->hnae3_dbgfs); 1070 handle->hnae3_dbgfs = NULL; 1071 return ret; 1072 } 1073 1074 void hns3_dbg_uninit(struct hnae3_handle *handle) 1075 { 1076 u32 i; 1077 1078 for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) 1079 if (hns3_dbg_cmd[i].buf) { 1080 kvfree(hns3_dbg_cmd[i].buf); 1081 hns3_dbg_cmd[i].buf = NULL; 1082 } 1083 1084 debugfs_remove_recursive(handle->hnae3_dbgfs); 1085 handle->hnae3_dbgfs = NULL; 1086 } 1087 1088 void hns3_dbg_register_debugfs(const char *debugfs_dir_name) 1089 { 1090 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL); 1091 } 1092 1093 void hns3_dbg_unregister_debugfs(void) 1094 { 1095 debugfs_remove_recursive(hns3_dbgfs_root); 1096 hns3_dbgfs_root = NULL; 1097 } 1098