1*287db5c4SJie Wang /* SPDX-License-Identifier: GPL-2.0+ */ 2*287db5c4SJie Wang // Copyright (c) 2021-2021 Hisilicon Limited. 3*287db5c4SJie Wang 4*287db5c4SJie Wang #ifndef __HCLGE_COMM_TQP_STATS_H 5*287db5c4SJie Wang #define __HCLGE_COMM_TQP_STATS_H 6*287db5c4SJie Wang #include <linux/types.h> 7*287db5c4SJie Wang #include <linux/etherdevice.h> 8*287db5c4SJie Wang #include "hnae3.h" 9*287db5c4SJie Wang 10*287db5c4SJie Wang /* each tqp has TX & RX two queues */ 11*287db5c4SJie Wang #define HCLGE_COMM_QUEUE_PAIR_SIZE 2 12*287db5c4SJie Wang 13*287db5c4SJie Wang /* TQP stats */ 14*287db5c4SJie Wang struct hclge_comm_tqp_stats { 15*287db5c4SJie Wang /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 16*287db5c4SJie Wang u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 17*287db5c4SJie Wang /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 18*287db5c4SJie Wang u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 19*287db5c4SJie Wang }; 20*287db5c4SJie Wang 21*287db5c4SJie Wang struct hclge_comm_tqp { 22*287db5c4SJie Wang /* copy of device pointer from pci_dev, 23*287db5c4SJie Wang * used when perform DMA mapping 24*287db5c4SJie Wang */ 25*287db5c4SJie Wang struct device *dev; 26*287db5c4SJie Wang struct hnae3_queue q; 27*287db5c4SJie Wang struct hclge_comm_tqp_stats tqp_stats; 28*287db5c4SJie Wang u16 index; /* Global index in a NIC controller */ 29*287db5c4SJie Wang 30*287db5c4SJie Wang bool alloced; 31*287db5c4SJie Wang }; 32*287db5c4SJie Wang 33*287db5c4SJie Wang u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data); 34*287db5c4SJie Wang int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle); 35*287db5c4SJie Wang u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data); 36*287db5c4SJie Wang void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle); 37*287db5c4SJie Wang int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, 38*287db5c4SJie Wang struct hclge_comm_hw *hw); 39*287db5c4SJie Wang #endif 40