1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 HNAE3_DEV_SUPPORT_PAUSE_B, 94 HNAE3_DEV_SUPPORT_RAS_IMP_B, 95 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 96 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 97 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 98 }; 99 100 #define hnae3_dev_fd_supported(hdev) \ 101 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 102 103 #define hnae3_dev_gro_supported(hdev) \ 104 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 105 106 #define hnae3_dev_fec_supported(hdev) \ 107 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 108 109 #define hnae3_dev_udp_gso_supported(hdev) \ 110 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 111 112 #define hnae3_dev_qb_supported(hdev) \ 113 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 114 115 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 116 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 117 118 #define hnae3_dev_ptp_supported(hdev) \ 119 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 120 121 #define hnae3_dev_int_ql_supported(hdev) \ 122 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 123 124 #define hnae3_dev_hw_csum_supported(hdev) \ 125 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 126 127 #define hnae3_dev_tx_push_supported(hdev) \ 128 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 129 130 #define hnae3_dev_phy_imp_supported(hdev) \ 131 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 132 133 #define hnae3_dev_ras_imp_supported(hdev) \ 134 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps) 135 136 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 137 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 138 139 #define hnae3_dev_hw_pad_supported(hdev) \ 140 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 141 142 #define hnae3_dev_stash_supported(hdev) \ 143 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 144 145 #define hnae3_dev_pause_supported(hdev) \ 146 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 147 148 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 149 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 150 151 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 152 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 153 154 enum HNAE3_PF_CAP_BITS { 155 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, 156 }; 157 #define ring_ptr_move_fw(ring, p) \ 158 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 159 #define ring_ptr_move_bw(ring, p) \ 160 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 161 162 enum hns_desc_type { 163 DESC_TYPE_UNKNOWN, 164 DESC_TYPE_SKB, 165 DESC_TYPE_FRAGLIST_SKB, 166 DESC_TYPE_PAGE, 167 }; 168 169 struct hnae3_handle; 170 171 struct hnae3_queue { 172 void __iomem *io_base; 173 struct hnae3_ae_algo *ae_algo; 174 struct hnae3_handle *handle; 175 int tqp_index; /* index in a handle */ 176 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 177 u16 tx_desc_num; /* total number of tx desc */ 178 u16 rx_desc_num; /* total number of rx desc */ 179 }; 180 181 struct hns3_mac_stats { 182 u64 tx_pause_cnt; 183 u64 rx_pause_cnt; 184 }; 185 186 /* hnae3 loop mode */ 187 enum hnae3_loop { 188 HNAE3_LOOP_APP, 189 HNAE3_LOOP_SERIAL_SERDES, 190 HNAE3_LOOP_PARALLEL_SERDES, 191 HNAE3_LOOP_PHY, 192 HNAE3_LOOP_NONE, 193 }; 194 195 enum hnae3_client_type { 196 HNAE3_CLIENT_KNIC, 197 HNAE3_CLIENT_ROCE, 198 }; 199 200 /* mac media type */ 201 enum hnae3_media_type { 202 HNAE3_MEDIA_TYPE_UNKNOWN, 203 HNAE3_MEDIA_TYPE_FIBER, 204 HNAE3_MEDIA_TYPE_COPPER, 205 HNAE3_MEDIA_TYPE_BACKPLANE, 206 HNAE3_MEDIA_TYPE_NONE, 207 }; 208 209 /* must be consistent with definition in firmware */ 210 enum hnae3_module_type { 211 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 212 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 213 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 214 HNAE3_MODULE_TYPE_AOC = 0x03, 215 HNAE3_MODULE_TYPE_CR = 0x04, 216 HNAE3_MODULE_TYPE_KR = 0x05, 217 HNAE3_MODULE_TYPE_TP = 0x06, 218 }; 219 220 enum hnae3_fec_mode { 221 HNAE3_FEC_AUTO = 0, 222 HNAE3_FEC_BASER, 223 HNAE3_FEC_RS, 224 HNAE3_FEC_USER_DEF, 225 }; 226 227 enum hnae3_reset_notify_type { 228 HNAE3_UP_CLIENT, 229 HNAE3_DOWN_CLIENT, 230 HNAE3_INIT_CLIENT, 231 HNAE3_UNINIT_CLIENT, 232 }; 233 234 enum hnae3_hw_error_type { 235 HNAE3_PPU_POISON_ERROR, 236 HNAE3_CMDQ_ECC_ERROR, 237 HNAE3_IMP_RD_POISON_ERROR, 238 HNAE3_ROCEE_AXI_RESP_ERROR, 239 }; 240 241 enum hnae3_reset_type { 242 HNAE3_VF_RESET, 243 HNAE3_VF_FUNC_RESET, 244 HNAE3_VF_PF_FUNC_RESET, 245 HNAE3_VF_FULL_RESET, 246 HNAE3_FLR_RESET, 247 HNAE3_FUNC_RESET, 248 HNAE3_GLOBAL_RESET, 249 HNAE3_IMP_RESET, 250 HNAE3_NONE_RESET, 251 HNAE3_MAX_RESET, 252 }; 253 254 enum hnae3_port_base_vlan_state { 255 HNAE3_PORT_BASE_VLAN_DISABLE, 256 HNAE3_PORT_BASE_VLAN_ENABLE, 257 HNAE3_PORT_BASE_VLAN_MODIFY, 258 HNAE3_PORT_BASE_VLAN_NOCHANGE, 259 }; 260 261 enum hnae3_dbg_cmd { 262 HNAE3_DBG_CMD_TM_NODES, 263 HNAE3_DBG_CMD_TM_PRI, 264 HNAE3_DBG_CMD_TM_QSET, 265 HNAE3_DBG_CMD_TM_MAP, 266 HNAE3_DBG_CMD_TM_PG, 267 HNAE3_DBG_CMD_TM_PORT, 268 HNAE3_DBG_CMD_TC_SCH_INFO, 269 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 270 HNAE3_DBG_CMD_QOS_PRI_MAP, 271 HNAE3_DBG_CMD_QOS_BUF_CFG, 272 HNAE3_DBG_CMD_DEV_INFO, 273 HNAE3_DBG_CMD_TX_BD, 274 HNAE3_DBG_CMD_RX_BD, 275 HNAE3_DBG_CMD_MAC_UC, 276 HNAE3_DBG_CMD_MAC_MC, 277 HNAE3_DBG_CMD_MNG_TBL, 278 HNAE3_DBG_CMD_LOOPBACK, 279 HNAE3_DBG_CMD_PTP_INFO, 280 HNAE3_DBG_CMD_INTERRUPT_INFO, 281 HNAE3_DBG_CMD_RESET_INFO, 282 HNAE3_DBG_CMD_IMP_INFO, 283 HNAE3_DBG_CMD_NCL_CONFIG, 284 HNAE3_DBG_CMD_REG_BIOS_COMMON, 285 HNAE3_DBG_CMD_REG_SSU, 286 HNAE3_DBG_CMD_REG_IGU_EGU, 287 HNAE3_DBG_CMD_REG_RPU, 288 HNAE3_DBG_CMD_REG_NCSI, 289 HNAE3_DBG_CMD_REG_RTC, 290 HNAE3_DBG_CMD_REG_PPP, 291 HNAE3_DBG_CMD_REG_RCB, 292 HNAE3_DBG_CMD_REG_TQP, 293 HNAE3_DBG_CMD_REG_MAC, 294 HNAE3_DBG_CMD_REG_DCB, 295 HNAE3_DBG_CMD_VLAN_CONFIG, 296 HNAE3_DBG_CMD_QUEUE_MAP, 297 HNAE3_DBG_CMD_RX_QUEUE_INFO, 298 HNAE3_DBG_CMD_TX_QUEUE_INFO, 299 HNAE3_DBG_CMD_FD_TCAM, 300 HNAE3_DBG_CMD_MAC_TNL_STATUS, 301 HNAE3_DBG_CMD_SERV_INFO, 302 HNAE3_DBG_CMD_UNKNOWN, 303 }; 304 305 struct hnae3_vector_info { 306 u8 __iomem *io_addr; 307 int vector; 308 }; 309 310 #define HNAE3_RING_TYPE_B 0 311 #define HNAE3_RING_TYPE_TX 0 312 #define HNAE3_RING_TYPE_RX 1 313 #define HNAE3_RING_GL_IDX_S 0 314 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 315 #define HNAE3_RING_GL_RX 0 316 #define HNAE3_RING_GL_TX 1 317 318 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 319 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 320 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 321 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 322 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 323 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 324 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 325 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 326 327 struct hnae3_ring_chain_node { 328 struct hnae3_ring_chain_node *next; 329 u32 tqp_index; 330 u32 flag; 331 u32 int_gl_idx; 332 }; 333 334 #define HNAE3_IS_TX_RING(node) \ 335 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 336 337 /* device specification info from firmware */ 338 struct hnae3_dev_specs { 339 u32 mac_entry_num; /* number of mac-vlan table entry */ 340 u32 mng_entry_num; /* number of manager table entry */ 341 u32 max_tm_rate; 342 u16 rss_ind_tbl_size; 343 u16 rss_key_size; 344 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 345 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 346 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 347 u16 max_frm_size; 348 u16 max_qset_num; 349 }; 350 351 struct hnae3_client_ops { 352 int (*init_instance)(struct hnae3_handle *handle); 353 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 354 void (*link_status_change)(struct hnae3_handle *handle, bool state); 355 int (*reset_notify)(struct hnae3_handle *handle, 356 enum hnae3_reset_notify_type type); 357 void (*process_hw_error)(struct hnae3_handle *handle, 358 enum hnae3_hw_error_type); 359 }; 360 361 #define HNAE3_CLIENT_NAME_LENGTH 16 362 struct hnae3_client { 363 char name[HNAE3_CLIENT_NAME_LENGTH]; 364 unsigned long state; 365 enum hnae3_client_type type; 366 const struct hnae3_client_ops *ops; 367 struct list_head node; 368 }; 369 370 #define HNAE3_DEV_CAPS_MAX_NUM 96 371 struct hnae3_ae_dev { 372 struct pci_dev *pdev; 373 const struct hnae3_ae_ops *ops; 374 struct list_head node; 375 u32 flag; 376 unsigned long hw_err_reset_req; 377 struct hnae3_dev_specs dev_specs; 378 u32 dev_version; 379 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 380 void *priv; 381 }; 382 383 /* This struct defines the operation on the handle. 384 * 385 * init_ae_dev(): (mandatory) 386 * Get PF configure from pci_dev and initialize PF hardware 387 * uninit_ae_dev() 388 * Disable PF device and release PF resource 389 * register_client 390 * Register client to ae_dev 391 * unregister_client() 392 * Unregister client from ae_dev 393 * start() 394 * Enable the hardware 395 * stop() 396 * Disable the hardware 397 * start_client() 398 * Inform the hclge that client has been started 399 * stop_client() 400 * Inform the hclge that client has been stopped 401 * get_status() 402 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 403 * non-ok 404 * get_ksettings_an_result() 405 * Get negotiation status,speed and duplex 406 * get_media_type() 407 * Get media type of MAC 408 * check_port_speed() 409 * Check target speed whether is supported 410 * adjust_link() 411 * Adjust link status 412 * set_loopback() 413 * Set loopback 414 * set_promisc_mode 415 * Set promisc mode 416 * request_update_promisc_mode 417 * request to hclge(vf) to update promisc mode 418 * set_mtu() 419 * set mtu 420 * get_pauseparam() 421 * get tx and rx of pause frame use 422 * set_pauseparam() 423 * set tx and rx of pause frame use 424 * set_autoneg() 425 * set auto autonegotiation of pause frame use 426 * get_autoneg() 427 * get auto autonegotiation of pause frame use 428 * restart_autoneg() 429 * restart autonegotiation 430 * halt_autoneg() 431 * halt/resume autonegotiation when autonegotiation on 432 * get_coalesce_usecs() 433 * get usecs to delay a TX interrupt after a packet is sent 434 * get_rx_max_coalesced_frames() 435 * get Maximum number of packets to be sent before a TX interrupt. 436 * set_coalesce_usecs() 437 * set usecs to delay a TX interrupt after a packet is sent 438 * set_coalesce_frames() 439 * set Maximum number of packets to be sent before a TX interrupt. 440 * get_mac_addr() 441 * get mac address 442 * set_mac_addr() 443 * set mac address 444 * add_uc_addr 445 * Add unicast addr to mac table 446 * rm_uc_addr 447 * Remove unicast addr from mac table 448 * set_mc_addr() 449 * Set multicast address 450 * add_mc_addr 451 * Add multicast address to mac table 452 * rm_mc_addr 453 * Remove multicast address from mac table 454 * update_stats() 455 * Update Old network device statistics 456 * get_mac_stats() 457 * get mac pause statistics including tx_cnt and rx_cnt 458 * get_ethtool_stats() 459 * Get ethtool network device statistics 460 * get_strings() 461 * Get a set of strings that describe the requested objects 462 * get_sset_count() 463 * Get number of strings that @get_strings will write 464 * update_led_status() 465 * Update the led status 466 * set_led_id() 467 * Set led id 468 * get_regs() 469 * Get regs dump 470 * get_regs_len() 471 * Get the len of the regs dump 472 * get_rss_key_size() 473 * Get rss key size 474 * get_rss() 475 * Get rss table 476 * set_rss() 477 * Set rss table 478 * get_tc_size() 479 * Get tc size of handle 480 * get_vector() 481 * Get vector number and vector information 482 * put_vector() 483 * Put the vector in hdev 484 * map_ring_to_vector() 485 * Map rings to vector 486 * unmap_ring_from_vector() 487 * Unmap rings from vector 488 * reset_queue() 489 * Reset queue 490 * get_fw_version() 491 * Get firmware version 492 * get_mdix_mode() 493 * Get media typr of phy 494 * enable_vlan_filter() 495 * Enable vlan filter 496 * set_vlan_filter() 497 * Set vlan filter config of Ports 498 * set_vf_vlan_filter() 499 * Set vlan filter config of vf 500 * enable_hw_strip_rxvtag() 501 * Enable/disable hardware strip vlan tag of packets received 502 * set_gro_en 503 * Enable/disable HW GRO 504 * add_arfs_entry 505 * Check the 5-tuples of flow, and create flow director rule 506 * get_vf_config 507 * Get the VF configuration setting by the host 508 * set_vf_link_state 509 * Set VF link status 510 * set_vf_spoofchk 511 * Enable/disable spoof check for specified vf 512 * set_vf_trust 513 * Enable/disable trust for specified vf, if the vf being trusted, then 514 * it can enable promisc mode 515 * set_vf_rate 516 * Set the max tx rate of specified vf. 517 * set_vf_mac 518 * Configure the default MAC for specified VF 519 * get_module_eeprom 520 * Get the optical module eeprom info. 521 * add_cls_flower 522 * Add clsflower rule 523 * del_cls_flower 524 * Delete clsflower rule 525 * cls_flower_active 526 * Check if any cls flower rule exist 527 * dbg_read_cmd 528 * Execute debugfs read command. 529 * set_tx_hwts_info 530 * Save information for 1588 tx packet 531 * get_rx_hwts 532 * Get 1588 rx hwstamp 533 * get_ts_info 534 * Get phc info 535 */ 536 struct hnae3_ae_ops { 537 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 538 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 539 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 540 enum hnae3_reset_type rst_type); 541 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 542 int (*init_client_instance)(struct hnae3_client *client, 543 struct hnae3_ae_dev *ae_dev); 544 void (*uninit_client_instance)(struct hnae3_client *client, 545 struct hnae3_ae_dev *ae_dev); 546 int (*start)(struct hnae3_handle *handle); 547 void (*stop)(struct hnae3_handle *handle); 548 int (*client_start)(struct hnae3_handle *handle); 549 void (*client_stop)(struct hnae3_handle *handle); 550 int (*get_status)(struct hnae3_handle *handle); 551 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 552 u8 *auto_neg, u32 *speed, u8 *duplex); 553 554 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 555 u8 duplex); 556 557 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 558 u8 *module_type); 559 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 560 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 561 u8 *fec_mode); 562 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 563 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 564 int (*set_loopback)(struct hnae3_handle *handle, 565 enum hnae3_loop loop_mode, bool en); 566 567 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 568 bool en_mc_pmc); 569 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 570 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 571 572 void (*get_pauseparam)(struct hnae3_handle *handle, 573 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 574 int (*set_pauseparam)(struct hnae3_handle *handle, 575 u32 auto_neg, u32 rx_en, u32 tx_en); 576 577 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 578 int (*get_autoneg)(struct hnae3_handle *handle); 579 int (*restart_autoneg)(struct hnae3_handle *handle); 580 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 581 582 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 583 u32 *tx_usecs, u32 *rx_usecs); 584 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 585 u32 *tx_frames, u32 *rx_frames); 586 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 587 int (*set_coalesce_frames)(struct hnae3_handle *handle, 588 u32 coalesce_frames); 589 void (*get_coalesce_range)(struct hnae3_handle *handle, 590 u32 *tx_frames_low, u32 *rx_frames_low, 591 u32 *tx_frames_high, u32 *rx_frames_high, 592 u32 *tx_usecs_low, u32 *rx_usecs_low, 593 u32 *tx_usecs_high, u32 *rx_usecs_high); 594 595 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 596 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 597 bool is_first); 598 int (*do_ioctl)(struct hnae3_handle *handle, 599 struct ifreq *ifr, int cmd); 600 int (*add_uc_addr)(struct hnae3_handle *handle, 601 const unsigned char *addr); 602 int (*rm_uc_addr)(struct hnae3_handle *handle, 603 const unsigned char *addr); 604 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 605 int (*add_mc_addr)(struct hnae3_handle *handle, 606 const unsigned char *addr); 607 int (*rm_mc_addr)(struct hnae3_handle *handle, 608 const unsigned char *addr); 609 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 610 void (*update_stats)(struct hnae3_handle *handle, 611 struct net_device_stats *net_stats); 612 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 613 void (*get_mac_stats)(struct hnae3_handle *handle, 614 struct hns3_mac_stats *mac_stats); 615 void (*get_strings)(struct hnae3_handle *handle, 616 u32 stringset, u8 *data); 617 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 618 619 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 620 void *data); 621 int (*get_regs_len)(struct hnae3_handle *handle); 622 623 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 624 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 625 u8 *hfunc); 626 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 627 const u8 *key, const u8 hfunc); 628 int (*set_rss_tuple)(struct hnae3_handle *handle, 629 struct ethtool_rxnfc *cmd); 630 int (*get_rss_tuple)(struct hnae3_handle *handle, 631 struct ethtool_rxnfc *cmd); 632 633 int (*get_tc_size)(struct hnae3_handle *handle); 634 635 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 636 struct hnae3_vector_info *vector_info); 637 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 638 int (*map_ring_to_vector)(struct hnae3_handle *handle, 639 int vector_num, 640 struct hnae3_ring_chain_node *vr_chain); 641 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 642 int vector_num, 643 struct hnae3_ring_chain_node *vr_chain); 644 645 int (*reset_queue)(struct hnae3_handle *handle); 646 u32 (*get_fw_version)(struct hnae3_handle *handle); 647 void (*get_mdix_mode)(struct hnae3_handle *handle, 648 u8 *tp_mdix_ctrl, u8 *tp_mdix); 649 650 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 651 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 652 u16 vlan_id, bool is_kill); 653 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 654 u16 vlan, u8 qos, __be16 proto); 655 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 656 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 657 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 658 unsigned long *addr); 659 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 660 enum hnae3_reset_type rst_type); 661 void (*get_channels)(struct hnae3_handle *handle, 662 struct ethtool_channels *ch); 663 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 664 u16 *alloc_tqps, u16 *max_rss_size); 665 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 666 bool rxfh_configured); 667 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 668 u32 *flowctrl_adv); 669 int (*set_led_id)(struct hnae3_handle *handle, 670 enum ethtool_phys_id_state status); 671 void (*get_link_mode)(struct hnae3_handle *handle, 672 unsigned long *supported, 673 unsigned long *advertising); 674 int (*add_fd_entry)(struct hnae3_handle *handle, 675 struct ethtool_rxnfc *cmd); 676 int (*del_fd_entry)(struct hnae3_handle *handle, 677 struct ethtool_rxnfc *cmd); 678 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 679 struct ethtool_rxnfc *cmd); 680 int (*get_fd_rule_info)(struct hnae3_handle *handle, 681 struct ethtool_rxnfc *cmd); 682 int (*get_fd_all_rules)(struct hnae3_handle *handle, 683 struct ethtool_rxnfc *cmd, u32 *rule_locs); 684 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 685 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 686 u16 flow_id, struct flow_keys *fkeys); 687 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 688 char *buf, int len); 689 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 690 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 691 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 692 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 693 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 694 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 695 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 696 int (*mac_connect_phy)(struct hnae3_handle *handle); 697 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 698 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 699 struct ifla_vf_info *ivf); 700 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 701 int link_state); 702 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 703 bool enable); 704 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 705 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 706 int min_tx_rate, int max_tx_rate, bool force); 707 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 708 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 709 u32 len, u8 *data); 710 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 711 int (*add_cls_flower)(struct hnae3_handle *handle, 712 struct flow_cls_offload *cls_flower, int tc); 713 int (*del_cls_flower)(struct hnae3_handle *handle, 714 struct flow_cls_offload *cls_flower); 715 bool (*cls_flower_active)(struct hnae3_handle *handle); 716 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 717 struct ethtool_link_ksettings *cmd); 718 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 719 const struct ethtool_link_ksettings *cmd); 720 bool (*set_tx_hwts_info)(struct hnae3_handle *handle, 721 struct sk_buff *skb); 722 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb, 723 u32 nsec, u32 sec); 724 int (*get_ts_info)(struct hnae3_handle *handle, 725 struct ethtool_ts_info *info); 726 }; 727 728 struct hnae3_dcb_ops { 729 /* IEEE 802.1Qaz std */ 730 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 731 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 732 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 733 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 734 735 /* DCBX configuration */ 736 u8 (*getdcbx)(struct hnae3_handle *); 737 u8 (*setdcbx)(struct hnae3_handle *, u8); 738 739 int (*setup_tc)(struct hnae3_handle *handle, 740 struct tc_mqprio_qopt_offload *mqprio_qopt); 741 }; 742 743 struct hnae3_ae_algo { 744 const struct hnae3_ae_ops *ops; 745 struct list_head node; 746 const struct pci_device_id *pdev_id_table; 747 }; 748 749 #define HNAE3_INT_NAME_LEN 32 750 #define HNAE3_ITR_COUNTDOWN_START 100 751 752 #define HNAE3_MAX_TC 8 753 #define HNAE3_MAX_USER_PRIO 8 754 struct hnae3_tc_info { 755 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 756 u16 tqp_count[HNAE3_MAX_TC]; 757 u16 tqp_offset[HNAE3_MAX_TC]; 758 unsigned long tc_en; /* bitmap of TC enabled */ 759 u8 num_tc; /* Total number of enabled TCs */ 760 bool mqprio_active; 761 }; 762 763 struct hnae3_knic_private_info { 764 struct net_device *netdev; /* Set by KNIC client when init instance */ 765 u16 rss_size; /* Allocated RSS queues */ 766 u16 req_rss_size; 767 u16 rx_buf_len; 768 u16 num_tx_desc; 769 u16 num_rx_desc; 770 771 struct hnae3_tc_info tc_info; 772 773 u16 num_tqps; /* total number of TQPs in this handle */ 774 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 775 const struct hnae3_dcb_ops *dcb_ops; 776 777 u16 int_rl_setting; 778 enum pkt_hash_types rss_type; 779 }; 780 781 struct hnae3_roce_private_info { 782 struct net_device *netdev; 783 void __iomem *roce_io_base; 784 void __iomem *roce_mem_base; 785 int base_vector; 786 int num_vectors; 787 788 /* The below attributes defined for RoCE client, hnae3 gives 789 * initial values to them, and RoCE client can modify and use 790 * them. 791 */ 792 unsigned long reset_state; 793 unsigned long instance_state; 794 unsigned long state; 795 }; 796 797 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 798 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 799 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 800 #define HNAE3_SUPPORT_VF BIT(3) 801 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 802 803 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 804 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 805 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 806 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 807 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 808 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 809 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 810 811 enum hnae3_pflag { 812 HNAE3_PFLAG_LIMIT_PROMISC, 813 HNAE3_PFLAG_MAX 814 }; 815 816 struct hnae3_handle { 817 struct hnae3_client *client; 818 struct pci_dev *pdev; 819 void *priv; 820 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 821 u64 flags; /* Indicate the capabilities for this handle */ 822 823 union { 824 struct net_device *netdev; /* first member */ 825 struct hnae3_knic_private_info kinfo; 826 struct hnae3_roce_private_info rinfo; 827 }; 828 829 u32 numa_node_mask; /* for multi-chip support */ 830 831 enum hnae3_port_base_vlan_state port_base_vlan_state; 832 833 u8 netdev_flags; 834 struct dentry *hnae3_dbgfs; 835 836 /* Network interface message level enabled bits */ 837 u32 msg_enable; 838 839 unsigned long supported_pflags; 840 unsigned long priv_flags; 841 }; 842 843 #define hnae3_set_field(origin, mask, shift, val) \ 844 do { \ 845 (origin) &= (~(mask)); \ 846 (origin) |= ((val) << (shift)) & (mask); \ 847 } while (0) 848 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 849 850 #define hnae3_set_bit(origin, shift, val) \ 851 hnae3_set_field(origin, 0x1 << (shift), shift, val) 852 #define hnae3_get_bit(origin, shift) \ 853 hnae3_get_field(origin, 0x1 << (shift), shift) 854 855 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 856 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 857 858 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 859 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 860 861 void hnae3_unregister_client(struct hnae3_client *client); 862 int hnae3_register_client(struct hnae3_client *client); 863 864 void hnae3_set_client_init_flag(struct hnae3_client *client, 865 struct hnae3_ae_dev *ae_dev, 866 unsigned int inited); 867 #endif 868