1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 HNAE3_DEV_SUPPORT_PAUSE_B, 94 HNAE3_DEV_SUPPORT_RAS_IMP_B, 95 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 96 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 97 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 98 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, 99 HNAE3_DEV_SUPPORT_CQ_B, 100 HNAE3_DEV_SUPPORT_FEC_STATS_B, 101 HNAE3_DEV_SUPPORT_LANE_NUM_B, 102 }; 103 104 #define hnae3_ae_dev_fd_supported(ae_dev) \ 105 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps) 106 107 #define hnae3_ae_dev_gro_supported(ae_dev) \ 108 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps) 109 110 #define hnae3_dev_fec_supported(hdev) \ 111 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 112 113 #define hnae3_dev_udp_gso_supported(hdev) \ 114 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 115 116 #define hnae3_dev_qb_supported(hdev) \ 117 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 118 119 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 120 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 121 122 #define hnae3_dev_ptp_supported(hdev) \ 123 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 124 125 #define hnae3_dev_int_ql_supported(hdev) \ 126 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 127 128 #define hnae3_dev_hw_csum_supported(hdev) \ 129 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 130 131 #define hnae3_dev_tx_push_supported(hdev) \ 132 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 133 134 #define hnae3_dev_phy_imp_supported(hdev) \ 135 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 136 137 #define hnae3_dev_ras_imp_supported(hdev) \ 138 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps) 139 140 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 141 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 142 143 #define hnae3_dev_hw_pad_supported(hdev) \ 144 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 145 146 #define hnae3_dev_stash_supported(hdev) \ 147 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 148 149 #define hnae3_dev_pause_supported(hdev) \ 150 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 151 152 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 153 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 154 155 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 156 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 157 158 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \ 159 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps) 160 161 #define hnae3_ae_dev_cq_supported(ae_dev) \ 162 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps) 163 164 #define hnae3_ae_dev_fec_stats_supported(ae_dev) \ 165 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps) 166 167 #define hnae3_ae_dev_lane_num_supported(ae_dev) \ 168 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps) 169 170 enum HNAE3_PF_CAP_BITS { 171 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, 172 }; 173 #define ring_ptr_move_fw(ring, p) \ 174 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 175 #define ring_ptr_move_bw(ring, p) \ 176 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 177 178 struct hnae3_handle; 179 180 struct hnae3_queue { 181 void __iomem *io_base; 182 void __iomem *mem_base; 183 struct hnae3_ae_algo *ae_algo; 184 struct hnae3_handle *handle; 185 int tqp_index; /* index in a handle */ 186 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 187 u16 tx_desc_num; /* total number of tx desc */ 188 u16 rx_desc_num; /* total number of rx desc */ 189 }; 190 191 struct hns3_mac_stats { 192 u64 tx_pause_cnt; 193 u64 rx_pause_cnt; 194 }; 195 196 /* hnae3 loop mode */ 197 enum hnae3_loop { 198 HNAE3_LOOP_EXTERNAL, 199 HNAE3_LOOP_APP, 200 HNAE3_LOOP_SERIAL_SERDES, 201 HNAE3_LOOP_PARALLEL_SERDES, 202 HNAE3_LOOP_PHY, 203 HNAE3_LOOP_NONE, 204 }; 205 206 enum hnae3_client_type { 207 HNAE3_CLIENT_KNIC, 208 HNAE3_CLIENT_ROCE, 209 }; 210 211 /* mac media type */ 212 enum hnae3_media_type { 213 HNAE3_MEDIA_TYPE_UNKNOWN, 214 HNAE3_MEDIA_TYPE_FIBER, 215 HNAE3_MEDIA_TYPE_COPPER, 216 HNAE3_MEDIA_TYPE_BACKPLANE, 217 HNAE3_MEDIA_TYPE_NONE, 218 }; 219 220 /* must be consistent with definition in firmware */ 221 enum hnae3_module_type { 222 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 223 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 224 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 225 HNAE3_MODULE_TYPE_AOC = 0x03, 226 HNAE3_MODULE_TYPE_CR = 0x04, 227 HNAE3_MODULE_TYPE_KR = 0x05, 228 HNAE3_MODULE_TYPE_TP = 0x06, 229 }; 230 231 enum hnae3_fec_mode { 232 HNAE3_FEC_AUTO = 0, 233 HNAE3_FEC_BASER, 234 HNAE3_FEC_RS, 235 HNAE3_FEC_LLRS, 236 HNAE3_FEC_NONE, 237 HNAE3_FEC_USER_DEF, 238 }; 239 240 enum hnae3_reset_notify_type { 241 HNAE3_UP_CLIENT, 242 HNAE3_DOWN_CLIENT, 243 HNAE3_INIT_CLIENT, 244 HNAE3_UNINIT_CLIENT, 245 }; 246 247 enum hnae3_hw_error_type { 248 HNAE3_PPU_POISON_ERROR, 249 HNAE3_CMDQ_ECC_ERROR, 250 HNAE3_IMP_RD_POISON_ERROR, 251 HNAE3_ROCEE_AXI_RESP_ERROR, 252 }; 253 254 enum hnae3_reset_type { 255 HNAE3_VF_RESET, 256 HNAE3_VF_FUNC_RESET, 257 HNAE3_VF_PF_FUNC_RESET, 258 HNAE3_VF_FULL_RESET, 259 HNAE3_FLR_RESET, 260 HNAE3_FUNC_RESET, 261 HNAE3_GLOBAL_RESET, 262 HNAE3_IMP_RESET, 263 HNAE3_NONE_RESET, 264 HNAE3_MAX_RESET, 265 }; 266 267 enum hnae3_port_base_vlan_state { 268 HNAE3_PORT_BASE_VLAN_DISABLE, 269 HNAE3_PORT_BASE_VLAN_ENABLE, 270 HNAE3_PORT_BASE_VLAN_MODIFY, 271 HNAE3_PORT_BASE_VLAN_NOCHANGE, 272 }; 273 274 enum hnae3_dbg_cmd { 275 HNAE3_DBG_CMD_TM_NODES, 276 HNAE3_DBG_CMD_TM_PRI, 277 HNAE3_DBG_CMD_TM_QSET, 278 HNAE3_DBG_CMD_TM_MAP, 279 HNAE3_DBG_CMD_TM_PG, 280 HNAE3_DBG_CMD_TM_PORT, 281 HNAE3_DBG_CMD_TC_SCH_INFO, 282 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 283 HNAE3_DBG_CMD_QOS_PRI_MAP, 284 HNAE3_DBG_CMD_QOS_DSCP_MAP, 285 HNAE3_DBG_CMD_QOS_BUF_CFG, 286 HNAE3_DBG_CMD_DEV_INFO, 287 HNAE3_DBG_CMD_TX_BD, 288 HNAE3_DBG_CMD_RX_BD, 289 HNAE3_DBG_CMD_MAC_UC, 290 HNAE3_DBG_CMD_MAC_MC, 291 HNAE3_DBG_CMD_MNG_TBL, 292 HNAE3_DBG_CMD_LOOPBACK, 293 HNAE3_DBG_CMD_PTP_INFO, 294 HNAE3_DBG_CMD_INTERRUPT_INFO, 295 HNAE3_DBG_CMD_RESET_INFO, 296 HNAE3_DBG_CMD_IMP_INFO, 297 HNAE3_DBG_CMD_NCL_CONFIG, 298 HNAE3_DBG_CMD_REG_BIOS_COMMON, 299 HNAE3_DBG_CMD_REG_SSU, 300 HNAE3_DBG_CMD_REG_IGU_EGU, 301 HNAE3_DBG_CMD_REG_RPU, 302 HNAE3_DBG_CMD_REG_NCSI, 303 HNAE3_DBG_CMD_REG_RTC, 304 HNAE3_DBG_CMD_REG_PPP, 305 HNAE3_DBG_CMD_REG_RCB, 306 HNAE3_DBG_CMD_REG_TQP, 307 HNAE3_DBG_CMD_REG_MAC, 308 HNAE3_DBG_CMD_REG_DCB, 309 HNAE3_DBG_CMD_VLAN_CONFIG, 310 HNAE3_DBG_CMD_QUEUE_MAP, 311 HNAE3_DBG_CMD_RX_QUEUE_INFO, 312 HNAE3_DBG_CMD_TX_QUEUE_INFO, 313 HNAE3_DBG_CMD_FD_TCAM, 314 HNAE3_DBG_CMD_FD_COUNTER, 315 HNAE3_DBG_CMD_MAC_TNL_STATUS, 316 HNAE3_DBG_CMD_SERV_INFO, 317 HNAE3_DBG_CMD_UMV_INFO, 318 HNAE3_DBG_CMD_PAGE_POOL_INFO, 319 HNAE3_DBG_CMD_COAL_INFO, 320 HNAE3_DBG_CMD_UNKNOWN, 321 }; 322 323 enum hnae3_tc_map_mode { 324 HNAE3_TC_MAP_MODE_PRIO, 325 HNAE3_TC_MAP_MODE_DSCP, 326 }; 327 328 struct hnae3_vector_info { 329 u8 __iomem *io_addr; 330 int vector; 331 }; 332 333 #define HNAE3_RING_TYPE_B 0 334 #define HNAE3_RING_TYPE_TX 0 335 #define HNAE3_RING_TYPE_RX 1 336 #define HNAE3_RING_GL_IDX_S 0 337 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 338 #define HNAE3_RING_GL_RX 0 339 #define HNAE3_RING_GL_TX 1 340 341 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 342 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 343 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 344 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 345 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 346 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 347 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 348 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 349 350 struct hnae3_ring_chain_node { 351 struct hnae3_ring_chain_node *next; 352 u32 tqp_index; 353 u32 flag; 354 u32 int_gl_idx; 355 }; 356 357 #define HNAE3_IS_TX_RING(node) \ 358 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 359 360 /* device specification info from firmware */ 361 struct hnae3_dev_specs { 362 u32 mac_entry_num; /* number of mac-vlan table entry */ 363 u32 mng_entry_num; /* number of manager table entry */ 364 u32 max_tm_rate; 365 u16 rss_ind_tbl_size; 366 u16 rss_key_size; 367 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 368 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 369 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 370 u16 max_frm_size; 371 u16 max_qset_num; 372 u16 umv_size; 373 u16 mc_mac_size; 374 u32 mac_stats_num; 375 }; 376 377 struct hnae3_client_ops { 378 int (*init_instance)(struct hnae3_handle *handle); 379 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 380 void (*link_status_change)(struct hnae3_handle *handle, bool state); 381 int (*reset_notify)(struct hnae3_handle *handle, 382 enum hnae3_reset_notify_type type); 383 void (*process_hw_error)(struct hnae3_handle *handle, 384 enum hnae3_hw_error_type); 385 }; 386 387 #define HNAE3_CLIENT_NAME_LENGTH 16 388 struct hnae3_client { 389 char name[HNAE3_CLIENT_NAME_LENGTH]; 390 unsigned long state; 391 enum hnae3_client_type type; 392 const struct hnae3_client_ops *ops; 393 struct list_head node; 394 }; 395 396 #define HNAE3_DEV_CAPS_MAX_NUM 96 397 struct hnae3_ae_dev { 398 struct pci_dev *pdev; 399 const struct hnae3_ae_ops *ops; 400 struct list_head node; 401 u32 flag; 402 unsigned long hw_err_reset_req; 403 struct hnae3_dev_specs dev_specs; 404 u32 dev_version; 405 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 406 void *priv; 407 }; 408 409 /* This struct defines the operation on the handle. 410 * 411 * init_ae_dev(): (mandatory) 412 * Get PF configure from pci_dev and initialize PF hardware 413 * uninit_ae_dev() 414 * Disable PF device and release PF resource 415 * register_client 416 * Register client to ae_dev 417 * unregister_client() 418 * Unregister client from ae_dev 419 * start() 420 * Enable the hardware 421 * stop() 422 * Disable the hardware 423 * start_client() 424 * Inform the hclge that client has been started 425 * stop_client() 426 * Inform the hclge that client has been stopped 427 * get_status() 428 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 429 * non-ok 430 * get_ksettings_an_result() 431 * Get negotiation status,speed and duplex 432 * get_media_type() 433 * Get media type of MAC 434 * check_port_speed() 435 * Check target speed whether is supported 436 * adjust_link() 437 * Adjust link status 438 * set_loopback() 439 * Set loopback 440 * set_promisc_mode 441 * Set promisc mode 442 * request_update_promisc_mode 443 * request to hclge(vf) to update promisc mode 444 * set_mtu() 445 * set mtu 446 * get_pauseparam() 447 * get tx and rx of pause frame use 448 * set_pauseparam() 449 * set tx and rx of pause frame use 450 * set_autoneg() 451 * set auto autonegotiation of pause frame use 452 * get_autoneg() 453 * get auto autonegotiation of pause frame use 454 * restart_autoneg() 455 * restart autonegotiation 456 * halt_autoneg() 457 * halt/resume autonegotiation when autonegotiation on 458 * get_coalesce_usecs() 459 * get usecs to delay a TX interrupt after a packet is sent 460 * get_rx_max_coalesced_frames() 461 * get Maximum number of packets to be sent before a TX interrupt. 462 * set_coalesce_usecs() 463 * set usecs to delay a TX interrupt after a packet is sent 464 * set_coalesce_frames() 465 * set Maximum number of packets to be sent before a TX interrupt. 466 * get_mac_addr() 467 * get mac address 468 * set_mac_addr() 469 * set mac address 470 * add_uc_addr 471 * Add unicast addr to mac table 472 * rm_uc_addr 473 * Remove unicast addr from mac table 474 * set_mc_addr() 475 * Set multicast address 476 * add_mc_addr 477 * Add multicast address to mac table 478 * rm_mc_addr 479 * Remove multicast address from mac table 480 * update_stats() 481 * Update Old network device statistics 482 * get_mac_stats() 483 * get mac pause statistics including tx_cnt and rx_cnt 484 * get_ethtool_stats() 485 * Get ethtool network device statistics 486 * get_strings() 487 * Get a set of strings that describe the requested objects 488 * get_sset_count() 489 * Get number of strings that @get_strings will write 490 * update_led_status() 491 * Update the led status 492 * set_led_id() 493 * Set led id 494 * get_regs() 495 * Get regs dump 496 * get_regs_len() 497 * Get the len of the regs dump 498 * get_rss_key_size() 499 * Get rss key size 500 * get_rss() 501 * Get rss table 502 * set_rss() 503 * Set rss table 504 * get_tc_size() 505 * Get tc size of handle 506 * get_vector() 507 * Get vector number and vector information 508 * put_vector() 509 * Put the vector in hdev 510 * map_ring_to_vector() 511 * Map rings to vector 512 * unmap_ring_from_vector() 513 * Unmap rings from vector 514 * reset_queue() 515 * Reset queue 516 * get_fw_version() 517 * Get firmware version 518 * get_mdix_mode() 519 * Get media typr of phy 520 * enable_vlan_filter() 521 * Enable vlan filter 522 * set_vlan_filter() 523 * Set vlan filter config of Ports 524 * set_vf_vlan_filter() 525 * Set vlan filter config of vf 526 * enable_hw_strip_rxvtag() 527 * Enable/disable hardware strip vlan tag of packets received 528 * set_gro_en 529 * Enable/disable HW GRO 530 * add_arfs_entry 531 * Check the 5-tuples of flow, and create flow director rule 532 * get_vf_config 533 * Get the VF configuration setting by the host 534 * set_vf_link_state 535 * Set VF link status 536 * set_vf_spoofchk 537 * Enable/disable spoof check for specified vf 538 * set_vf_trust 539 * Enable/disable trust for specified vf, if the vf being trusted, then 540 * it can enable promisc mode 541 * set_vf_rate 542 * Set the max tx rate of specified vf. 543 * set_vf_mac 544 * Configure the default MAC for specified VF 545 * get_module_eeprom 546 * Get the optical module eeprom info. 547 * add_cls_flower 548 * Add clsflower rule 549 * del_cls_flower 550 * Delete clsflower rule 551 * cls_flower_active 552 * Check if any cls flower rule exist 553 * dbg_read_cmd 554 * Execute debugfs read command. 555 * set_tx_hwts_info 556 * Save information for 1588 tx packet 557 * get_rx_hwts 558 * Get 1588 rx hwstamp 559 * get_ts_info 560 * Get phc info 561 * clean_vf_config 562 * Clean residual vf info after disable sriov 563 */ 564 struct hnae3_ae_ops { 565 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 566 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 567 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 568 enum hnae3_reset_type rst_type); 569 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 570 int (*init_client_instance)(struct hnae3_client *client, 571 struct hnae3_ae_dev *ae_dev); 572 void (*uninit_client_instance)(struct hnae3_client *client, 573 struct hnae3_ae_dev *ae_dev); 574 int (*start)(struct hnae3_handle *handle); 575 void (*stop)(struct hnae3_handle *handle); 576 int (*client_start)(struct hnae3_handle *handle); 577 void (*client_stop)(struct hnae3_handle *handle); 578 int (*get_status)(struct hnae3_handle *handle); 579 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 580 u8 *auto_neg, u32 *speed, u8 *duplex, 581 u32 *lane_num); 582 583 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 584 u8 duplex, u8 lane_num); 585 586 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 587 u8 *module_type); 588 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 589 void (*get_fec_stats)(struct hnae3_handle *handle, 590 struct ethtool_fec_stats *fec_stats); 591 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 592 u8 *fec_mode); 593 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 594 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 595 int (*set_loopback)(struct hnae3_handle *handle, 596 enum hnae3_loop loop_mode, bool en); 597 598 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 599 bool en_mc_pmc); 600 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 601 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 602 603 void (*get_pauseparam)(struct hnae3_handle *handle, 604 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 605 int (*set_pauseparam)(struct hnae3_handle *handle, 606 u32 auto_neg, u32 rx_en, u32 tx_en); 607 608 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 609 int (*get_autoneg)(struct hnae3_handle *handle); 610 int (*restart_autoneg)(struct hnae3_handle *handle); 611 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 612 613 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 614 u32 *tx_usecs, u32 *rx_usecs); 615 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 616 u32 *tx_frames, u32 *rx_frames); 617 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 618 int (*set_coalesce_frames)(struct hnae3_handle *handle, 619 u32 coalesce_frames); 620 void (*get_coalesce_range)(struct hnae3_handle *handle, 621 u32 *tx_frames_low, u32 *rx_frames_low, 622 u32 *tx_frames_high, u32 *rx_frames_high, 623 u32 *tx_usecs_low, u32 *rx_usecs_low, 624 u32 *tx_usecs_high, u32 *rx_usecs_high); 625 626 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 627 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p, 628 bool is_first); 629 int (*do_ioctl)(struct hnae3_handle *handle, 630 struct ifreq *ifr, int cmd); 631 int (*add_uc_addr)(struct hnae3_handle *handle, 632 const unsigned char *addr); 633 int (*rm_uc_addr)(struct hnae3_handle *handle, 634 const unsigned char *addr); 635 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 636 int (*add_mc_addr)(struct hnae3_handle *handle, 637 const unsigned char *addr); 638 int (*rm_mc_addr)(struct hnae3_handle *handle, 639 const unsigned char *addr); 640 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 641 void (*update_stats)(struct hnae3_handle *handle, 642 struct net_device_stats *net_stats); 643 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 644 void (*get_mac_stats)(struct hnae3_handle *handle, 645 struct hns3_mac_stats *mac_stats); 646 void (*get_strings)(struct hnae3_handle *handle, 647 u32 stringset, u8 *data); 648 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 649 650 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 651 void *data); 652 int (*get_regs_len)(struct hnae3_handle *handle); 653 654 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 655 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 656 u8 *hfunc); 657 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 658 const u8 *key, const u8 hfunc); 659 int (*set_rss_tuple)(struct hnae3_handle *handle, 660 struct ethtool_rxnfc *cmd); 661 int (*get_rss_tuple)(struct hnae3_handle *handle, 662 struct ethtool_rxnfc *cmd); 663 664 int (*get_tc_size)(struct hnae3_handle *handle); 665 666 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 667 struct hnae3_vector_info *vector_info); 668 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 669 int (*map_ring_to_vector)(struct hnae3_handle *handle, 670 int vector_num, 671 struct hnae3_ring_chain_node *vr_chain); 672 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 673 int vector_num, 674 struct hnae3_ring_chain_node *vr_chain); 675 676 int (*reset_queue)(struct hnae3_handle *handle); 677 u32 (*get_fw_version)(struct hnae3_handle *handle); 678 void (*get_mdix_mode)(struct hnae3_handle *handle, 679 u8 *tp_mdix_ctrl, u8 *tp_mdix); 680 681 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 682 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 683 u16 vlan_id, bool is_kill); 684 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 685 u16 vlan, u8 qos, __be16 proto); 686 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 687 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 688 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 689 unsigned long *addr); 690 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 691 enum hnae3_reset_type rst_type); 692 void (*get_channels)(struct hnae3_handle *handle, 693 struct ethtool_channels *ch); 694 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 695 u16 *alloc_tqps, u16 *max_rss_size); 696 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 697 bool rxfh_configured); 698 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 699 u32 *flowctrl_adv); 700 int (*set_led_id)(struct hnae3_handle *handle, 701 enum ethtool_phys_id_state status); 702 void (*get_link_mode)(struct hnae3_handle *handle, 703 unsigned long *supported, 704 unsigned long *advertising); 705 int (*add_fd_entry)(struct hnae3_handle *handle, 706 struct ethtool_rxnfc *cmd); 707 int (*del_fd_entry)(struct hnae3_handle *handle, 708 struct ethtool_rxnfc *cmd); 709 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 710 struct ethtool_rxnfc *cmd); 711 int (*get_fd_rule_info)(struct hnae3_handle *handle, 712 struct ethtool_rxnfc *cmd); 713 int (*get_fd_all_rules)(struct hnae3_handle *handle, 714 struct ethtool_rxnfc *cmd, u32 *rule_locs); 715 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 716 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 717 u16 flow_id, struct flow_keys *fkeys); 718 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 719 char *buf, int len); 720 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 721 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 722 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 723 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 724 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 725 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 726 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 727 int (*mac_connect_phy)(struct hnae3_handle *handle); 728 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 729 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 730 struct ifla_vf_info *ivf); 731 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 732 int link_state); 733 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 734 bool enable); 735 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 736 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 737 int min_tx_rate, int max_tx_rate, bool force); 738 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 739 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 740 u32 len, u8 *data); 741 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 742 int (*add_cls_flower)(struct hnae3_handle *handle, 743 struct flow_cls_offload *cls_flower, int tc); 744 int (*del_cls_flower)(struct hnae3_handle *handle, 745 struct flow_cls_offload *cls_flower); 746 bool (*cls_flower_active)(struct hnae3_handle *handle); 747 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 748 struct ethtool_link_ksettings *cmd); 749 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 750 const struct ethtool_link_ksettings *cmd); 751 bool (*set_tx_hwts_info)(struct hnae3_handle *handle, 752 struct sk_buff *skb); 753 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb, 754 u32 nsec, u32 sec); 755 int (*get_ts_info)(struct hnae3_handle *handle, 756 struct ethtool_ts_info *info); 757 int (*get_link_diagnosis_info)(struct hnae3_handle *handle, 758 u32 *status_code); 759 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs); 760 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp, 761 u8 *tc_map_mode, u8 *priority); 762 }; 763 764 struct hnae3_dcb_ops { 765 /* IEEE 802.1Qaz std */ 766 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 767 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 768 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 769 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 770 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app); 771 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app); 772 773 /* DCBX configuration */ 774 u8 (*getdcbx)(struct hnae3_handle *); 775 u8 (*setdcbx)(struct hnae3_handle *, u8); 776 777 int (*setup_tc)(struct hnae3_handle *handle, 778 struct tc_mqprio_qopt_offload *mqprio_qopt); 779 }; 780 781 struct hnae3_ae_algo { 782 const struct hnae3_ae_ops *ops; 783 struct list_head node; 784 const struct pci_device_id *pdev_id_table; 785 }; 786 787 #define HNAE3_INT_NAME_LEN 32 788 #define HNAE3_ITR_COUNTDOWN_START 100 789 790 #define HNAE3_MAX_TC 8 791 #define HNAE3_MAX_USER_PRIO 8 792 struct hnae3_tc_info { 793 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 794 u16 tqp_count[HNAE3_MAX_TC]; 795 u16 tqp_offset[HNAE3_MAX_TC]; 796 u8 max_tc; /* Total number of TCs */ 797 u8 num_tc; /* Total number of enabled TCs */ 798 bool mqprio_active; 799 }; 800 801 #define HNAE3_MAX_DSCP 64 802 #define HNAE3_PRIO_ID_INVALID 0xff 803 struct hnae3_knic_private_info { 804 struct net_device *netdev; /* Set by KNIC client when init instance */ 805 u16 rss_size; /* Allocated RSS queues */ 806 u16 req_rss_size; 807 u16 rx_buf_len; 808 u16 num_tx_desc; 809 u16 num_rx_desc; 810 u32 tx_spare_buf_size; 811 812 struct hnae3_tc_info tc_info; 813 u8 tc_map_mode; 814 u8 dscp_app_cnt; 815 u8 dscp_prio[HNAE3_MAX_DSCP]; 816 817 u16 num_tqps; /* total number of TQPs in this handle */ 818 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 819 const struct hnae3_dcb_ops *dcb_ops; 820 821 u16 int_rl_setting; 822 void __iomem *io_base; 823 }; 824 825 struct hnae3_roce_private_info { 826 struct net_device *netdev; 827 void __iomem *roce_io_base; 828 void __iomem *roce_mem_base; 829 int base_vector; 830 int num_vectors; 831 832 /* The below attributes defined for RoCE client, hnae3 gives 833 * initial values to them, and RoCE client can modify and use 834 * them. 835 */ 836 unsigned long reset_state; 837 unsigned long instance_state; 838 unsigned long state; 839 }; 840 841 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 842 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 843 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 844 #define HNAE3_SUPPORT_VF BIT(3) 845 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 846 #define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5) 847 848 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 849 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 850 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 851 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 852 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 853 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 854 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 855 856 enum hnae3_pflag { 857 HNAE3_PFLAG_LIMIT_PROMISC, 858 HNAE3_PFLAG_MAX 859 }; 860 861 struct hnae3_handle { 862 struct hnae3_client *client; 863 struct pci_dev *pdev; 864 void *priv; 865 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 866 u64 flags; /* Indicate the capabilities for this handle */ 867 868 union { 869 struct net_device *netdev; /* first member */ 870 struct hnae3_knic_private_info kinfo; 871 struct hnae3_roce_private_info rinfo; 872 }; 873 874 u32 numa_node_mask; /* for multi-chip support */ 875 876 enum hnae3_port_base_vlan_state port_base_vlan_state; 877 878 u8 netdev_flags; 879 struct dentry *hnae3_dbgfs; 880 /* protects concurrent contention between debugfs commands */ 881 struct mutex dbgfs_lock; 882 char **dbgfs_buf; 883 884 /* Network interface message level enabled bits */ 885 u32 msg_enable; 886 887 unsigned long supported_pflags; 888 unsigned long priv_flags; 889 }; 890 891 #define hnae3_set_field(origin, mask, shift, val) \ 892 do { \ 893 (origin) &= (~(mask)); \ 894 (origin) |= ((val) << (shift)) & (mask); \ 895 } while (0) 896 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 897 898 #define hnae3_set_bit(origin, shift, val) \ 899 hnae3_set_field(origin, 0x1 << (shift), shift, val) 900 #define hnae3_get_bit(origin, shift) \ 901 hnae3_get_field(origin, 0x1 << (shift), shift) 902 903 #define HNAE3_FORMAT_MAC_ADDR_LEN 18 904 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0 905 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4 906 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5 907 908 static inline void hnae3_format_mac_addr(char *format_mac_addr, 909 const u8 *mac_addr) 910 { 911 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x", 912 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0], 913 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4], 914 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]); 915 } 916 917 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 918 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 919 920 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo); 921 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 922 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 923 924 void hnae3_unregister_client(struct hnae3_client *client); 925 int hnae3_register_client(struct hnae3_client *client); 926 927 void hnae3_set_client_init_flag(struct hnae3_client *client, 928 struct hnae3_ae_dev *ae_dev, 929 unsigned int inited); 930 #endif 931