1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 #include <net/pkt_sched.h> 36 37 #define HNAE3_MOD_VERSION "1.0" 38 39 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 40 41 /* Device version */ 42 #define HNAE3_DEVICE_VERSION_V1 0x00020 43 #define HNAE3_DEVICE_VERSION_V2 0x00021 44 #define HNAE3_DEVICE_VERSION_V3 0x00030 45 46 #define HNAE3_PCI_REVISION_BIT_SIZE 8 47 48 /* Device IDs */ 49 #define HNAE3_DEV_ID_GE 0xA220 50 #define HNAE3_DEV_ID_25GE 0xA221 51 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 52 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 53 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 54 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 55 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 56 #define HNAE3_DEV_ID_200G_RDMA 0xA228 57 #define HNAE3_DEV_ID_VF 0xA22E 58 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 59 60 #define HNAE3_CLASS_NAME_SIZE 16 61 62 #define HNAE3_DEV_INITED_B 0x0 63 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 64 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 65 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 66 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 67 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 68 69 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \ 70 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 71 72 #define hnae3_dev_roce_supported(hdev) \ 73 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 74 75 #define hnae3_dev_dcb_supported(hdev) \ 76 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 77 78 enum HNAE3_DEV_CAP_BITS { 79 HNAE3_DEV_SUPPORT_FD_B, 80 HNAE3_DEV_SUPPORT_GRO_B, 81 HNAE3_DEV_SUPPORT_FEC_B, 82 HNAE3_DEV_SUPPORT_UDP_GSO_B, 83 HNAE3_DEV_SUPPORT_QB_B, 84 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 85 HNAE3_DEV_SUPPORT_PTP_B, 86 HNAE3_DEV_SUPPORT_INT_QL_B, 87 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 88 HNAE3_DEV_SUPPORT_TX_PUSH_B, 89 HNAE3_DEV_SUPPORT_PHY_IMP_B, 90 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 91 HNAE3_DEV_SUPPORT_HW_PAD_B, 92 HNAE3_DEV_SUPPORT_STASH_B, 93 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 94 HNAE3_DEV_SUPPORT_PAUSE_B, 95 HNAE3_DEV_SUPPORT_RAS_IMP_B, 96 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 97 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 98 HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 99 HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, 100 HNAE3_DEV_SUPPORT_CQ_B, 101 HNAE3_DEV_SUPPORT_FEC_STATS_B, 102 HNAE3_DEV_SUPPORT_LANE_NUM_B, 103 HNAE3_DEV_SUPPORT_WOL_B, 104 }; 105 106 #define hnae3_ae_dev_fd_supported(ae_dev) \ 107 test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps) 108 109 #define hnae3_ae_dev_gro_supported(ae_dev) \ 110 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps) 111 112 #define hnae3_dev_fec_supported(hdev) \ 113 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 114 115 #define hnae3_dev_udp_gso_supported(hdev) \ 116 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 117 118 #define hnae3_dev_qb_supported(hdev) \ 119 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 120 121 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 122 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 123 124 #define hnae3_dev_ptp_supported(hdev) \ 125 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 126 127 #define hnae3_dev_int_ql_supported(hdev) \ 128 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 129 130 #define hnae3_dev_hw_csum_supported(hdev) \ 131 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 132 133 #define hnae3_dev_tx_push_supported(hdev) \ 134 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 135 136 #define hnae3_dev_phy_imp_supported(hdev) \ 137 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 138 139 #define hnae3_dev_ras_imp_supported(hdev) \ 140 test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps) 141 142 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 143 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 144 145 #define hnae3_dev_hw_pad_supported(hdev) \ 146 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 147 148 #define hnae3_dev_stash_supported(hdev) \ 149 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 150 151 #define hnae3_dev_pause_supported(hdev) \ 152 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 153 154 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 155 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 156 157 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 158 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 159 160 #define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \ 161 test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps) 162 163 #define hnae3_ae_dev_cq_supported(ae_dev) \ 164 test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps) 165 166 #define hnae3_ae_dev_fec_stats_supported(ae_dev) \ 167 test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps) 168 169 #define hnae3_ae_dev_lane_num_supported(ae_dev) \ 170 test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps) 171 172 #define hnae3_ae_dev_wol_supported(ae_dev) \ 173 test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps) 174 175 enum HNAE3_PF_CAP_BITS { 176 HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0, 177 }; 178 #define ring_ptr_move_fw(ring, p) \ 179 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 180 #define ring_ptr_move_bw(ring, p) \ 181 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 182 183 struct hnae3_handle; 184 185 struct hnae3_queue { 186 void __iomem *io_base; 187 void __iomem *mem_base; 188 struct hnae3_ae_algo *ae_algo; 189 struct hnae3_handle *handle; 190 int tqp_index; /* index in a handle */ 191 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 192 u16 tx_desc_num; /* total number of tx desc */ 193 u16 rx_desc_num; /* total number of rx desc */ 194 }; 195 196 struct hns3_mac_stats { 197 u64 tx_pause_cnt; 198 u64 rx_pause_cnt; 199 }; 200 201 /* hnae3 loop mode */ 202 enum hnae3_loop { 203 HNAE3_LOOP_EXTERNAL, 204 HNAE3_LOOP_APP, 205 HNAE3_LOOP_SERIAL_SERDES, 206 HNAE3_LOOP_PARALLEL_SERDES, 207 HNAE3_LOOP_PHY, 208 HNAE3_LOOP_NONE, 209 }; 210 211 enum hnae3_client_type { 212 HNAE3_CLIENT_KNIC, 213 HNAE3_CLIENT_ROCE, 214 }; 215 216 /* mac media type */ 217 enum hnae3_media_type { 218 HNAE3_MEDIA_TYPE_UNKNOWN, 219 HNAE3_MEDIA_TYPE_FIBER, 220 HNAE3_MEDIA_TYPE_COPPER, 221 HNAE3_MEDIA_TYPE_BACKPLANE, 222 HNAE3_MEDIA_TYPE_NONE, 223 }; 224 225 /* must be consistent with definition in firmware */ 226 enum hnae3_module_type { 227 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 228 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 229 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 230 HNAE3_MODULE_TYPE_AOC = 0x03, 231 HNAE3_MODULE_TYPE_CR = 0x04, 232 HNAE3_MODULE_TYPE_KR = 0x05, 233 HNAE3_MODULE_TYPE_TP = 0x06, 234 }; 235 236 enum hnae3_fec_mode { 237 HNAE3_FEC_AUTO = 0, 238 HNAE3_FEC_BASER, 239 HNAE3_FEC_RS, 240 HNAE3_FEC_LLRS, 241 HNAE3_FEC_NONE, 242 HNAE3_FEC_USER_DEF, 243 }; 244 245 enum hnae3_reset_notify_type { 246 HNAE3_UP_CLIENT, 247 HNAE3_DOWN_CLIENT, 248 HNAE3_INIT_CLIENT, 249 HNAE3_UNINIT_CLIENT, 250 }; 251 252 enum hnae3_hw_error_type { 253 HNAE3_PPU_POISON_ERROR, 254 HNAE3_CMDQ_ECC_ERROR, 255 HNAE3_IMP_RD_POISON_ERROR, 256 HNAE3_ROCEE_AXI_RESP_ERROR, 257 }; 258 259 enum hnae3_reset_type { 260 HNAE3_VF_RESET, 261 HNAE3_VF_FUNC_RESET, 262 HNAE3_VF_PF_FUNC_RESET, 263 HNAE3_VF_FULL_RESET, 264 HNAE3_FLR_RESET, 265 HNAE3_FUNC_RESET, 266 HNAE3_GLOBAL_RESET, 267 HNAE3_IMP_RESET, 268 HNAE3_NONE_RESET, 269 HNAE3_MAX_RESET, 270 }; 271 272 enum hnae3_port_base_vlan_state { 273 HNAE3_PORT_BASE_VLAN_DISABLE, 274 HNAE3_PORT_BASE_VLAN_ENABLE, 275 HNAE3_PORT_BASE_VLAN_MODIFY, 276 HNAE3_PORT_BASE_VLAN_NOCHANGE, 277 }; 278 279 enum hnae3_dbg_cmd { 280 HNAE3_DBG_CMD_TM_NODES, 281 HNAE3_DBG_CMD_TM_PRI, 282 HNAE3_DBG_CMD_TM_QSET, 283 HNAE3_DBG_CMD_TM_MAP, 284 HNAE3_DBG_CMD_TM_PG, 285 HNAE3_DBG_CMD_TM_PORT, 286 HNAE3_DBG_CMD_TC_SCH_INFO, 287 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 288 HNAE3_DBG_CMD_QOS_PRI_MAP, 289 HNAE3_DBG_CMD_QOS_DSCP_MAP, 290 HNAE3_DBG_CMD_QOS_BUF_CFG, 291 HNAE3_DBG_CMD_DEV_INFO, 292 HNAE3_DBG_CMD_TX_BD, 293 HNAE3_DBG_CMD_RX_BD, 294 HNAE3_DBG_CMD_MAC_UC, 295 HNAE3_DBG_CMD_MAC_MC, 296 HNAE3_DBG_CMD_MNG_TBL, 297 HNAE3_DBG_CMD_LOOPBACK, 298 HNAE3_DBG_CMD_PTP_INFO, 299 HNAE3_DBG_CMD_INTERRUPT_INFO, 300 HNAE3_DBG_CMD_RESET_INFO, 301 HNAE3_DBG_CMD_IMP_INFO, 302 HNAE3_DBG_CMD_NCL_CONFIG, 303 HNAE3_DBG_CMD_REG_BIOS_COMMON, 304 HNAE3_DBG_CMD_REG_SSU, 305 HNAE3_DBG_CMD_REG_IGU_EGU, 306 HNAE3_DBG_CMD_REG_RPU, 307 HNAE3_DBG_CMD_REG_NCSI, 308 HNAE3_DBG_CMD_REG_RTC, 309 HNAE3_DBG_CMD_REG_PPP, 310 HNAE3_DBG_CMD_REG_RCB, 311 HNAE3_DBG_CMD_REG_TQP, 312 HNAE3_DBG_CMD_REG_MAC, 313 HNAE3_DBG_CMD_REG_DCB, 314 HNAE3_DBG_CMD_VLAN_CONFIG, 315 HNAE3_DBG_CMD_QUEUE_MAP, 316 HNAE3_DBG_CMD_RX_QUEUE_INFO, 317 HNAE3_DBG_CMD_TX_QUEUE_INFO, 318 HNAE3_DBG_CMD_FD_TCAM, 319 HNAE3_DBG_CMD_FD_COUNTER, 320 HNAE3_DBG_CMD_MAC_TNL_STATUS, 321 HNAE3_DBG_CMD_SERV_INFO, 322 HNAE3_DBG_CMD_UMV_INFO, 323 HNAE3_DBG_CMD_PAGE_POOL_INFO, 324 HNAE3_DBG_CMD_COAL_INFO, 325 HNAE3_DBG_CMD_UNKNOWN, 326 }; 327 328 enum hnae3_tc_map_mode { 329 HNAE3_TC_MAP_MODE_PRIO, 330 HNAE3_TC_MAP_MODE_DSCP, 331 }; 332 333 struct hnae3_vector_info { 334 u8 __iomem *io_addr; 335 int vector; 336 }; 337 338 #define HNAE3_RING_TYPE_B 0 339 #define HNAE3_RING_TYPE_TX 0 340 #define HNAE3_RING_TYPE_RX 1 341 #define HNAE3_RING_GL_IDX_S 0 342 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 343 #define HNAE3_RING_GL_RX 0 344 #define HNAE3_RING_GL_TX 1 345 346 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 347 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 348 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 349 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 350 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 351 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 352 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 353 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 354 355 struct hnae3_ring_chain_node { 356 struct hnae3_ring_chain_node *next; 357 u32 tqp_index; 358 u32 flag; 359 u32 int_gl_idx; 360 }; 361 362 #define HNAE3_IS_TX_RING(node) \ 363 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 364 365 /* device specification info from firmware */ 366 struct hnae3_dev_specs { 367 u32 mac_entry_num; /* number of mac-vlan table entry */ 368 u32 mng_entry_num; /* number of manager table entry */ 369 u32 max_tm_rate; 370 u16 rss_ind_tbl_size; 371 u16 rss_key_size; 372 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 373 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 374 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 375 u16 max_frm_size; 376 u16 max_qset_num; 377 u16 umv_size; 378 u16 mc_mac_size; 379 u32 mac_stats_num; 380 }; 381 382 struct hnae3_client_ops { 383 int (*init_instance)(struct hnae3_handle *handle); 384 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 385 void (*link_status_change)(struct hnae3_handle *handle, bool state); 386 int (*reset_notify)(struct hnae3_handle *handle, 387 enum hnae3_reset_notify_type type); 388 void (*process_hw_error)(struct hnae3_handle *handle, 389 enum hnae3_hw_error_type); 390 }; 391 392 #define HNAE3_CLIENT_NAME_LENGTH 16 393 struct hnae3_client { 394 char name[HNAE3_CLIENT_NAME_LENGTH]; 395 unsigned long state; 396 enum hnae3_client_type type; 397 const struct hnae3_client_ops *ops; 398 struct list_head node; 399 }; 400 401 #define HNAE3_DEV_CAPS_MAX_NUM 96 402 struct hnae3_ae_dev { 403 struct pci_dev *pdev; 404 const struct hnae3_ae_ops *ops; 405 struct list_head node; 406 u32 flag; 407 unsigned long hw_err_reset_req; 408 struct hnae3_dev_specs dev_specs; 409 u32 dev_version; 410 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 411 void *priv; 412 }; 413 414 /* This struct defines the operation on the handle. 415 * 416 * init_ae_dev(): (mandatory) 417 * Get PF configure from pci_dev and initialize PF hardware 418 * uninit_ae_dev() 419 * Disable PF device and release PF resource 420 * register_client 421 * Register client to ae_dev 422 * unregister_client() 423 * Unregister client from ae_dev 424 * start() 425 * Enable the hardware 426 * stop() 427 * Disable the hardware 428 * start_client() 429 * Inform the hclge that client has been started 430 * stop_client() 431 * Inform the hclge that client has been stopped 432 * get_status() 433 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 434 * non-ok 435 * get_ksettings_an_result() 436 * Get negotiation status,speed and duplex 437 * get_media_type() 438 * Get media type of MAC 439 * check_port_speed() 440 * Check target speed whether is supported 441 * adjust_link() 442 * Adjust link status 443 * set_loopback() 444 * Set loopback 445 * set_promisc_mode 446 * Set promisc mode 447 * request_update_promisc_mode 448 * request to hclge(vf) to update promisc mode 449 * set_mtu() 450 * set mtu 451 * get_pauseparam() 452 * get tx and rx of pause frame use 453 * set_pauseparam() 454 * set tx and rx of pause frame use 455 * set_autoneg() 456 * set auto autonegotiation of pause frame use 457 * get_autoneg() 458 * get auto autonegotiation of pause frame use 459 * restart_autoneg() 460 * restart autonegotiation 461 * halt_autoneg() 462 * halt/resume autonegotiation when autonegotiation on 463 * get_coalesce_usecs() 464 * get usecs to delay a TX interrupt after a packet is sent 465 * get_rx_max_coalesced_frames() 466 * get Maximum number of packets to be sent before a TX interrupt. 467 * set_coalesce_usecs() 468 * set usecs to delay a TX interrupt after a packet is sent 469 * set_coalesce_frames() 470 * set Maximum number of packets to be sent before a TX interrupt. 471 * get_mac_addr() 472 * get mac address 473 * set_mac_addr() 474 * set mac address 475 * add_uc_addr 476 * Add unicast addr to mac table 477 * rm_uc_addr 478 * Remove unicast addr from mac table 479 * set_mc_addr() 480 * Set multicast address 481 * add_mc_addr 482 * Add multicast address to mac table 483 * rm_mc_addr 484 * Remove multicast address from mac table 485 * update_stats() 486 * Update Old network device statistics 487 * get_mac_stats() 488 * get mac pause statistics including tx_cnt and rx_cnt 489 * get_ethtool_stats() 490 * Get ethtool network device statistics 491 * get_strings() 492 * Get a set of strings that describe the requested objects 493 * get_sset_count() 494 * Get number of strings that @get_strings will write 495 * update_led_status() 496 * Update the led status 497 * set_led_id() 498 * Set led id 499 * get_regs() 500 * Get regs dump 501 * get_regs_len() 502 * Get the len of the regs dump 503 * get_rss_key_size() 504 * Get rss key size 505 * get_rss() 506 * Get rss table 507 * set_rss() 508 * Set rss table 509 * get_tc_size() 510 * Get tc size of handle 511 * get_vector() 512 * Get vector number and vector information 513 * put_vector() 514 * Put the vector in hdev 515 * map_ring_to_vector() 516 * Map rings to vector 517 * unmap_ring_from_vector() 518 * Unmap rings from vector 519 * reset_queue() 520 * Reset queue 521 * get_fw_version() 522 * Get firmware version 523 * get_mdix_mode() 524 * Get media typr of phy 525 * enable_vlan_filter() 526 * Enable vlan filter 527 * set_vlan_filter() 528 * Set vlan filter config of Ports 529 * set_vf_vlan_filter() 530 * Set vlan filter config of vf 531 * enable_hw_strip_rxvtag() 532 * Enable/disable hardware strip vlan tag of packets received 533 * set_gro_en 534 * Enable/disable HW GRO 535 * add_arfs_entry 536 * Check the 5-tuples of flow, and create flow director rule 537 * get_vf_config 538 * Get the VF configuration setting by the host 539 * set_vf_link_state 540 * Set VF link status 541 * set_vf_spoofchk 542 * Enable/disable spoof check for specified vf 543 * set_vf_trust 544 * Enable/disable trust for specified vf, if the vf being trusted, then 545 * it can enable promisc mode 546 * set_vf_rate 547 * Set the max tx rate of specified vf. 548 * set_vf_mac 549 * Configure the default MAC for specified VF 550 * get_module_eeprom 551 * Get the optical module eeprom info. 552 * add_cls_flower 553 * Add clsflower rule 554 * del_cls_flower 555 * Delete clsflower rule 556 * cls_flower_active 557 * Check if any cls flower rule exist 558 * dbg_read_cmd 559 * Execute debugfs read command. 560 * set_tx_hwts_info 561 * Save information for 1588 tx packet 562 * get_rx_hwts 563 * Get 1588 rx hwstamp 564 * get_ts_info 565 * Get phc info 566 * clean_vf_config 567 * Clean residual vf info after disable sriov 568 * get_wol 569 * Get wake on lan info 570 * set_wol 571 * Config wake on lan 572 */ 573 struct hnae3_ae_ops { 574 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 575 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 576 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 577 enum hnae3_reset_type rst_type); 578 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 579 int (*init_client_instance)(struct hnae3_client *client, 580 struct hnae3_ae_dev *ae_dev); 581 void (*uninit_client_instance)(struct hnae3_client *client, 582 struct hnae3_ae_dev *ae_dev); 583 int (*start)(struct hnae3_handle *handle); 584 void (*stop)(struct hnae3_handle *handle); 585 int (*client_start)(struct hnae3_handle *handle); 586 void (*client_stop)(struct hnae3_handle *handle); 587 int (*get_status)(struct hnae3_handle *handle); 588 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 589 u8 *auto_neg, u32 *speed, u8 *duplex, 590 u32 *lane_num); 591 592 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 593 u8 duplex, u8 lane_num); 594 595 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 596 u8 *module_type); 597 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 598 void (*get_fec_stats)(struct hnae3_handle *handle, 599 struct ethtool_fec_stats *fec_stats); 600 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 601 u8 *fec_mode); 602 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 603 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 604 int (*set_loopback)(struct hnae3_handle *handle, 605 enum hnae3_loop loop_mode, bool en); 606 607 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 608 bool en_mc_pmc); 609 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 610 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 611 612 void (*get_pauseparam)(struct hnae3_handle *handle, 613 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 614 int (*set_pauseparam)(struct hnae3_handle *handle, 615 u32 auto_neg, u32 rx_en, u32 tx_en); 616 617 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 618 int (*get_autoneg)(struct hnae3_handle *handle); 619 int (*restart_autoneg)(struct hnae3_handle *handle); 620 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 621 622 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 623 u32 *tx_usecs, u32 *rx_usecs); 624 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 625 u32 *tx_frames, u32 *rx_frames); 626 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 627 int (*set_coalesce_frames)(struct hnae3_handle *handle, 628 u32 coalesce_frames); 629 void (*get_coalesce_range)(struct hnae3_handle *handle, 630 u32 *tx_frames_low, u32 *rx_frames_low, 631 u32 *tx_frames_high, u32 *rx_frames_high, 632 u32 *tx_usecs_low, u32 *rx_usecs_low, 633 u32 *tx_usecs_high, u32 *rx_usecs_high); 634 635 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 636 int (*set_mac_addr)(struct hnae3_handle *handle, const void *p, 637 bool is_first); 638 int (*do_ioctl)(struct hnae3_handle *handle, 639 struct ifreq *ifr, int cmd); 640 int (*add_uc_addr)(struct hnae3_handle *handle, 641 const unsigned char *addr); 642 int (*rm_uc_addr)(struct hnae3_handle *handle, 643 const unsigned char *addr); 644 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 645 int (*add_mc_addr)(struct hnae3_handle *handle, 646 const unsigned char *addr); 647 int (*rm_mc_addr)(struct hnae3_handle *handle, 648 const unsigned char *addr); 649 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 650 void (*update_stats)(struct hnae3_handle *handle); 651 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 652 void (*get_mac_stats)(struct hnae3_handle *handle, 653 struct hns3_mac_stats *mac_stats); 654 void (*get_strings)(struct hnae3_handle *handle, 655 u32 stringset, u8 *data); 656 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 657 658 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 659 void *data); 660 int (*get_regs_len)(struct hnae3_handle *handle); 661 662 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 663 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 664 u8 *hfunc); 665 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 666 const u8 *key, const u8 hfunc); 667 int (*set_rss_tuple)(struct hnae3_handle *handle, 668 struct ethtool_rxnfc *cmd); 669 int (*get_rss_tuple)(struct hnae3_handle *handle, 670 struct ethtool_rxnfc *cmd); 671 672 int (*get_tc_size)(struct hnae3_handle *handle); 673 674 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 675 struct hnae3_vector_info *vector_info); 676 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 677 int (*map_ring_to_vector)(struct hnae3_handle *handle, 678 int vector_num, 679 struct hnae3_ring_chain_node *vr_chain); 680 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 681 int vector_num, 682 struct hnae3_ring_chain_node *vr_chain); 683 684 int (*reset_queue)(struct hnae3_handle *handle); 685 u32 (*get_fw_version)(struct hnae3_handle *handle); 686 void (*get_mdix_mode)(struct hnae3_handle *handle, 687 u8 *tp_mdix_ctrl, u8 *tp_mdix); 688 689 int (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 690 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 691 u16 vlan_id, bool is_kill); 692 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 693 u16 vlan, u8 qos, __be16 proto); 694 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 695 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 696 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 697 unsigned long *addr); 698 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 699 enum hnae3_reset_type rst_type); 700 void (*get_channels)(struct hnae3_handle *handle, 701 struct ethtool_channels *ch); 702 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 703 u16 *alloc_tqps, u16 *max_rss_size); 704 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 705 bool rxfh_configured); 706 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 707 u32 *flowctrl_adv); 708 int (*set_led_id)(struct hnae3_handle *handle, 709 enum ethtool_phys_id_state status); 710 void (*get_link_mode)(struct hnae3_handle *handle, 711 unsigned long *supported, 712 unsigned long *advertising); 713 int (*add_fd_entry)(struct hnae3_handle *handle, 714 struct ethtool_rxnfc *cmd); 715 int (*del_fd_entry)(struct hnae3_handle *handle, 716 struct ethtool_rxnfc *cmd); 717 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 718 struct ethtool_rxnfc *cmd); 719 int (*get_fd_rule_info)(struct hnae3_handle *handle, 720 struct ethtool_rxnfc *cmd); 721 int (*get_fd_all_rules)(struct hnae3_handle *handle, 722 struct ethtool_rxnfc *cmd, u32 *rule_locs); 723 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 724 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 725 u16 flow_id, struct flow_keys *fkeys); 726 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 727 char *buf, int len); 728 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 729 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 730 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 731 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 732 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 733 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 734 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 735 int (*mac_connect_phy)(struct hnae3_handle *handle); 736 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 737 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 738 struct ifla_vf_info *ivf); 739 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 740 int link_state); 741 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 742 bool enable); 743 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 744 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 745 int min_tx_rate, int max_tx_rate, bool force); 746 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 747 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 748 u32 len, u8 *data); 749 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 750 int (*add_cls_flower)(struct hnae3_handle *handle, 751 struct flow_cls_offload *cls_flower, int tc); 752 int (*del_cls_flower)(struct hnae3_handle *handle, 753 struct flow_cls_offload *cls_flower); 754 bool (*cls_flower_active)(struct hnae3_handle *handle); 755 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 756 struct ethtool_link_ksettings *cmd); 757 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 758 const struct ethtool_link_ksettings *cmd); 759 bool (*set_tx_hwts_info)(struct hnae3_handle *handle, 760 struct sk_buff *skb); 761 void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb, 762 u32 nsec, u32 sec); 763 int (*get_ts_info)(struct hnae3_handle *handle, 764 struct ethtool_ts_info *info); 765 int (*get_link_diagnosis_info)(struct hnae3_handle *handle, 766 u32 *status_code); 767 void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs); 768 int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp, 769 u8 *tc_map_mode, u8 *priority); 770 void (*get_wol)(struct hnae3_handle *handle, 771 struct ethtool_wolinfo *wol); 772 int (*set_wol)(struct hnae3_handle *handle, 773 struct ethtool_wolinfo *wol); 774 }; 775 776 struct hnae3_dcb_ops { 777 /* IEEE 802.1Qaz std */ 778 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 779 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 780 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 781 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 782 int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app); 783 int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app); 784 785 /* DCBX configuration */ 786 u8 (*getdcbx)(struct hnae3_handle *); 787 u8 (*setdcbx)(struct hnae3_handle *, u8); 788 789 int (*setup_tc)(struct hnae3_handle *handle, 790 struct tc_mqprio_qopt_offload *mqprio_qopt); 791 }; 792 793 struct hnae3_ae_algo { 794 const struct hnae3_ae_ops *ops; 795 struct list_head node; 796 const struct pci_device_id *pdev_id_table; 797 }; 798 799 #define HNAE3_INT_NAME_LEN 32 800 #define HNAE3_ITR_COUNTDOWN_START 100 801 802 #define HNAE3_MAX_TC 8 803 #define HNAE3_MAX_USER_PRIO 8 804 struct hnae3_tc_info { 805 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 806 u16 tqp_count[HNAE3_MAX_TC]; 807 u16 tqp_offset[HNAE3_MAX_TC]; 808 u8 max_tc; /* Total number of TCs */ 809 u8 num_tc; /* Total number of enabled TCs */ 810 bool mqprio_active; 811 }; 812 813 #define HNAE3_MAX_DSCP 64 814 #define HNAE3_PRIO_ID_INVALID 0xff 815 struct hnae3_knic_private_info { 816 struct net_device *netdev; /* Set by KNIC client when init instance */ 817 u16 rss_size; /* Allocated RSS queues */ 818 u16 req_rss_size; 819 u16 rx_buf_len; 820 u16 num_tx_desc; 821 u16 num_rx_desc; 822 u32 tx_spare_buf_size; 823 824 struct hnae3_tc_info tc_info; 825 u8 tc_map_mode; 826 u8 dscp_app_cnt; 827 u8 dscp_prio[HNAE3_MAX_DSCP]; 828 829 u16 num_tqps; /* total number of TQPs in this handle */ 830 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 831 const struct hnae3_dcb_ops *dcb_ops; 832 833 u16 int_rl_setting; 834 void __iomem *io_base; 835 }; 836 837 struct hnae3_roce_private_info { 838 struct net_device *netdev; 839 void __iomem *roce_io_base; 840 void __iomem *roce_mem_base; 841 int base_vector; 842 int num_vectors; 843 844 /* The below attributes defined for RoCE client, hnae3 gives 845 * initial values to them, and RoCE client can modify and use 846 * them. 847 */ 848 unsigned long reset_state; 849 unsigned long instance_state; 850 unsigned long state; 851 }; 852 853 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 854 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 855 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 856 #define HNAE3_SUPPORT_VF BIT(3) 857 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 858 #define HNAE3_SUPPORT_EXTERNAL_LOOPBACK BIT(5) 859 860 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 861 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 862 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 863 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 864 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 865 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 866 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 867 868 enum hnae3_pflag { 869 HNAE3_PFLAG_LIMIT_PROMISC, 870 HNAE3_PFLAG_MAX 871 }; 872 873 struct hnae3_handle { 874 struct hnae3_client *client; 875 struct pci_dev *pdev; 876 void *priv; 877 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 878 u64 flags; /* Indicate the capabilities for this handle */ 879 880 union { 881 struct net_device *netdev; /* first member */ 882 struct hnae3_knic_private_info kinfo; 883 struct hnae3_roce_private_info rinfo; 884 }; 885 886 u32 numa_node_mask; /* for multi-chip support */ 887 888 enum hnae3_port_base_vlan_state port_base_vlan_state; 889 890 u8 netdev_flags; 891 struct dentry *hnae3_dbgfs; 892 /* protects concurrent contention between debugfs commands */ 893 struct mutex dbgfs_lock; 894 char **dbgfs_buf; 895 896 /* Network interface message level enabled bits */ 897 u32 msg_enable; 898 899 unsigned long supported_pflags; 900 unsigned long priv_flags; 901 }; 902 903 #define hnae3_set_field(origin, mask, shift, val) \ 904 do { \ 905 (origin) &= (~(mask)); \ 906 (origin) |= ((val) << (shift)) & (mask); \ 907 } while (0) 908 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 909 910 #define hnae3_set_bit(origin, shift, val) \ 911 hnae3_set_field(origin, 0x1 << (shift), shift, val) 912 #define hnae3_get_bit(origin, shift) \ 913 hnae3_get_field(origin, 0x1 << (shift), shift) 914 915 #define HNAE3_FORMAT_MAC_ADDR_LEN 18 916 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_0 0 917 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_4 4 918 #define HNAE3_FORMAT_MAC_ADDR_OFFSET_5 5 919 920 static inline void hnae3_format_mac_addr(char *format_mac_addr, 921 const u8 *mac_addr) 922 { 923 snprintf(format_mac_addr, HNAE3_FORMAT_MAC_ADDR_LEN, "%02x:**:**:**:%02x:%02x", 924 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_0], 925 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_4], 926 mac_addr[HNAE3_FORMAT_MAC_ADDR_OFFSET_5]); 927 } 928 929 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 930 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 931 932 void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo); 933 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 934 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 935 936 void hnae3_unregister_client(struct hnae3_client *client); 937 int hnae3_register_client(struct hnae3_client *client); 938 939 void hnae3_set_client_init_flag(struct hnae3_client *client, 940 struct hnae3_ae_dev *ae_dev, 941 unsigned int inited); 942 #endif 943