1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 }; 94 95 #define hnae3_dev_fd_supported(hdev) \ 96 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 97 98 #define hnae3_dev_gro_supported(hdev) \ 99 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 100 101 #define hnae3_dev_fec_supported(hdev) \ 102 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 103 104 #define hnae3_dev_udp_gso_supported(hdev) \ 105 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 106 107 #define hnae3_dev_qb_supported(hdev) \ 108 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 109 110 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 111 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 112 113 #define hnae3_dev_ptp_supported(hdev) \ 114 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 115 116 #define hnae3_dev_int_ql_supported(hdev) \ 117 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 118 119 #define hnae3_dev_hw_csum_supported(hdev) \ 120 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 121 122 #define hnae3_dev_tx_push_supported(hdev) \ 123 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 124 125 #define hnae3_dev_phy_imp_supported(hdev) \ 126 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 127 128 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 129 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 130 131 #define hnae3_dev_hw_pad_supported(hdev) \ 132 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 133 134 #define hnae3_dev_stash_supported(hdev) \ 135 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 136 137 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 138 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 139 140 #define ring_ptr_move_fw(ring, p) \ 141 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 142 #define ring_ptr_move_bw(ring, p) \ 143 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 144 145 enum hns_desc_type { 146 DESC_TYPE_UNKNOWN, 147 DESC_TYPE_SKB, 148 DESC_TYPE_FRAGLIST_SKB, 149 DESC_TYPE_PAGE, 150 }; 151 152 struct hnae3_handle; 153 154 struct hnae3_queue { 155 void __iomem *io_base; 156 struct hnae3_ae_algo *ae_algo; 157 struct hnae3_handle *handle; 158 int tqp_index; /* index in a handle */ 159 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 160 u16 tx_desc_num; /* total number of tx desc */ 161 u16 rx_desc_num; /* total number of rx desc */ 162 }; 163 164 struct hns3_mac_stats { 165 u64 tx_pause_cnt; 166 u64 rx_pause_cnt; 167 }; 168 169 /* hnae3 loop mode */ 170 enum hnae3_loop { 171 HNAE3_LOOP_APP, 172 HNAE3_LOOP_SERIAL_SERDES, 173 HNAE3_LOOP_PARALLEL_SERDES, 174 HNAE3_LOOP_PHY, 175 HNAE3_LOOP_NONE, 176 }; 177 178 enum hnae3_client_type { 179 HNAE3_CLIENT_KNIC, 180 HNAE3_CLIENT_ROCE, 181 }; 182 183 /* mac media type */ 184 enum hnae3_media_type { 185 HNAE3_MEDIA_TYPE_UNKNOWN, 186 HNAE3_MEDIA_TYPE_FIBER, 187 HNAE3_MEDIA_TYPE_COPPER, 188 HNAE3_MEDIA_TYPE_BACKPLANE, 189 HNAE3_MEDIA_TYPE_NONE, 190 }; 191 192 /* must be consistent with definition in firmware */ 193 enum hnae3_module_type { 194 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 195 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 196 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 197 HNAE3_MODULE_TYPE_AOC = 0x03, 198 HNAE3_MODULE_TYPE_CR = 0x04, 199 HNAE3_MODULE_TYPE_KR = 0x05, 200 HNAE3_MODULE_TYPE_TP = 0x06, 201 }; 202 203 enum hnae3_fec_mode { 204 HNAE3_FEC_AUTO = 0, 205 HNAE3_FEC_BASER, 206 HNAE3_FEC_RS, 207 HNAE3_FEC_USER_DEF, 208 }; 209 210 enum hnae3_reset_notify_type { 211 HNAE3_UP_CLIENT, 212 HNAE3_DOWN_CLIENT, 213 HNAE3_INIT_CLIENT, 214 HNAE3_UNINIT_CLIENT, 215 }; 216 217 enum hnae3_hw_error_type { 218 HNAE3_PPU_POISON_ERROR, 219 HNAE3_CMDQ_ECC_ERROR, 220 HNAE3_IMP_RD_POISON_ERROR, 221 HNAE3_ROCEE_AXI_RESP_ERROR, 222 }; 223 224 enum hnae3_reset_type { 225 HNAE3_VF_RESET, 226 HNAE3_VF_FUNC_RESET, 227 HNAE3_VF_PF_FUNC_RESET, 228 HNAE3_VF_FULL_RESET, 229 HNAE3_FLR_RESET, 230 HNAE3_FUNC_RESET, 231 HNAE3_GLOBAL_RESET, 232 HNAE3_IMP_RESET, 233 HNAE3_UNKNOWN_RESET, 234 HNAE3_NONE_RESET, 235 HNAE3_MAX_RESET, 236 }; 237 238 enum hnae3_port_base_vlan_state { 239 HNAE3_PORT_BASE_VLAN_DISABLE, 240 HNAE3_PORT_BASE_VLAN_ENABLE, 241 HNAE3_PORT_BASE_VLAN_MODIFY, 242 HNAE3_PORT_BASE_VLAN_NOCHANGE, 243 }; 244 245 struct hnae3_vector_info { 246 u8 __iomem *io_addr; 247 int vector; 248 }; 249 250 #define HNAE3_RING_TYPE_B 0 251 #define HNAE3_RING_TYPE_TX 0 252 #define HNAE3_RING_TYPE_RX 1 253 #define HNAE3_RING_GL_IDX_S 0 254 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 255 #define HNAE3_RING_GL_RX 0 256 #define HNAE3_RING_GL_TX 1 257 258 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 259 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 260 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 261 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 262 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 263 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 264 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 265 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 266 267 struct hnae3_ring_chain_node { 268 struct hnae3_ring_chain_node *next; 269 u32 tqp_index; 270 u32 flag; 271 u32 int_gl_idx; 272 }; 273 274 #define HNAE3_IS_TX_RING(node) \ 275 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 276 277 /* device specification info from firmware */ 278 struct hnae3_dev_specs { 279 u32 mac_entry_num; /* number of mac-vlan table entry */ 280 u32 mng_entry_num; /* number of manager table entry */ 281 u32 max_tm_rate; 282 u16 rss_ind_tbl_size; 283 u16 rss_key_size; 284 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 285 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 286 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 287 u16 max_frm_size; 288 u16 max_qset_num; 289 }; 290 291 struct hnae3_client_ops { 292 int (*init_instance)(struct hnae3_handle *handle); 293 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 294 void (*link_status_change)(struct hnae3_handle *handle, bool state); 295 int (*reset_notify)(struct hnae3_handle *handle, 296 enum hnae3_reset_notify_type type); 297 void (*process_hw_error)(struct hnae3_handle *handle, 298 enum hnae3_hw_error_type); 299 }; 300 301 #define HNAE3_CLIENT_NAME_LENGTH 16 302 struct hnae3_client { 303 char name[HNAE3_CLIENT_NAME_LENGTH]; 304 unsigned long state; 305 enum hnae3_client_type type; 306 const struct hnae3_client_ops *ops; 307 struct list_head node; 308 }; 309 310 #define HNAE3_DEV_CAPS_MAX_NUM 96 311 struct hnae3_ae_dev { 312 struct pci_dev *pdev; 313 const struct hnae3_ae_ops *ops; 314 struct list_head node; 315 u32 flag; 316 unsigned long hw_err_reset_req; 317 struct hnae3_dev_specs dev_specs; 318 u32 dev_version; 319 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 320 void *priv; 321 }; 322 323 /* This struct defines the operation on the handle. 324 * 325 * init_ae_dev(): (mandatory) 326 * Get PF configure from pci_dev and initialize PF hardware 327 * uninit_ae_dev() 328 * Disable PF device and release PF resource 329 * register_client 330 * Register client to ae_dev 331 * unregister_client() 332 * Unregister client from ae_dev 333 * start() 334 * Enable the hardware 335 * stop() 336 * Disable the hardware 337 * start_client() 338 * Inform the hclge that client has been started 339 * stop_client() 340 * Inform the hclge that client has been stopped 341 * get_status() 342 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 343 * non-ok 344 * get_ksettings_an_result() 345 * Get negotiation status,speed and duplex 346 * get_media_type() 347 * Get media type of MAC 348 * check_port_speed() 349 * Check target speed whether is supported 350 * adjust_link() 351 * Adjust link status 352 * set_loopback() 353 * Set loopback 354 * set_promisc_mode 355 * Set promisc mode 356 * request_update_promisc_mode 357 * request to hclge(vf) to update promisc mode 358 * set_mtu() 359 * set mtu 360 * get_pauseparam() 361 * get tx and rx of pause frame use 362 * set_pauseparam() 363 * set tx and rx of pause frame use 364 * set_autoneg() 365 * set auto autonegotiation of pause frame use 366 * get_autoneg() 367 * get auto autonegotiation of pause frame use 368 * restart_autoneg() 369 * restart autonegotiation 370 * halt_autoneg() 371 * halt/resume autonegotiation when autonegotiation on 372 * get_coalesce_usecs() 373 * get usecs to delay a TX interrupt after a packet is sent 374 * get_rx_max_coalesced_frames() 375 * get Maximum number of packets to be sent before a TX interrupt. 376 * set_coalesce_usecs() 377 * set usecs to delay a TX interrupt after a packet is sent 378 * set_coalesce_frames() 379 * set Maximum number of packets to be sent before a TX interrupt. 380 * get_mac_addr() 381 * get mac address 382 * set_mac_addr() 383 * set mac address 384 * add_uc_addr 385 * Add unicast addr to mac table 386 * rm_uc_addr 387 * Remove unicast addr from mac table 388 * set_mc_addr() 389 * Set multicast address 390 * add_mc_addr 391 * Add multicast address to mac table 392 * rm_mc_addr 393 * Remove multicast address from mac table 394 * update_stats() 395 * Update Old network device statistics 396 * get_mac_stats() 397 * get mac pause statistics including tx_cnt and rx_cnt 398 * get_ethtool_stats() 399 * Get ethtool network device statistics 400 * get_strings() 401 * Get a set of strings that describe the requested objects 402 * get_sset_count() 403 * Get number of strings that @get_strings will write 404 * update_led_status() 405 * Update the led status 406 * set_led_id() 407 * Set led id 408 * get_regs() 409 * Get regs dump 410 * get_regs_len() 411 * Get the len of the regs dump 412 * get_rss_key_size() 413 * Get rss key size 414 * get_rss() 415 * Get rss table 416 * set_rss() 417 * Set rss table 418 * get_tc_size() 419 * Get tc size of handle 420 * get_vector() 421 * Get vector number and vector information 422 * put_vector() 423 * Put the vector in hdev 424 * map_ring_to_vector() 425 * Map rings to vector 426 * unmap_ring_from_vector() 427 * Unmap rings from vector 428 * reset_queue() 429 * Reset queue 430 * get_fw_version() 431 * Get firmware version 432 * get_mdix_mode() 433 * Get media typr of phy 434 * enable_vlan_filter() 435 * Enable vlan filter 436 * set_vlan_filter() 437 * Set vlan filter config of Ports 438 * set_vf_vlan_filter() 439 * Set vlan filter config of vf 440 * enable_hw_strip_rxvtag() 441 * Enable/disable hardware strip vlan tag of packets received 442 * set_gro_en 443 * Enable/disable HW GRO 444 * add_arfs_entry 445 * Check the 5-tuples of flow, and create flow director rule 446 * get_vf_config 447 * Get the VF configuration setting by the host 448 * set_vf_link_state 449 * Set VF link status 450 * set_vf_spoofchk 451 * Enable/disable spoof check for specified vf 452 * set_vf_trust 453 * Enable/disable trust for specified vf, if the vf being trusted, then 454 * it can enable promisc mode 455 * set_vf_rate 456 * Set the max tx rate of specified vf. 457 * set_vf_mac 458 * Configure the default MAC for specified VF 459 * get_module_eeprom 460 * Get the optical module eeprom info. 461 * add_cls_flower 462 * Add clsflower rule 463 * del_cls_flower 464 * Delete clsflower rule 465 * cls_flower_active 466 * Check if any cls flower rule exist 467 * dbg_read_cmd 468 * Execute debugfs read command. 469 */ 470 struct hnae3_ae_ops { 471 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 472 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 473 void (*flr_prepare)(struct hnae3_ae_dev *ae_dev); 474 void (*flr_done)(struct hnae3_ae_dev *ae_dev); 475 int (*init_client_instance)(struct hnae3_client *client, 476 struct hnae3_ae_dev *ae_dev); 477 void (*uninit_client_instance)(struct hnae3_client *client, 478 struct hnae3_ae_dev *ae_dev); 479 int (*start)(struct hnae3_handle *handle); 480 void (*stop)(struct hnae3_handle *handle); 481 int (*client_start)(struct hnae3_handle *handle); 482 void (*client_stop)(struct hnae3_handle *handle); 483 int (*get_status)(struct hnae3_handle *handle); 484 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 485 u8 *auto_neg, u32 *speed, u8 *duplex); 486 487 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 488 u8 duplex); 489 490 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 491 u8 *module_type); 492 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 493 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 494 u8 *fec_mode); 495 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 496 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 497 int (*set_loopback)(struct hnae3_handle *handle, 498 enum hnae3_loop loop_mode, bool en); 499 500 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 501 bool en_mc_pmc); 502 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 503 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 504 505 void (*get_pauseparam)(struct hnae3_handle *handle, 506 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 507 int (*set_pauseparam)(struct hnae3_handle *handle, 508 u32 auto_neg, u32 rx_en, u32 tx_en); 509 510 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 511 int (*get_autoneg)(struct hnae3_handle *handle); 512 int (*restart_autoneg)(struct hnae3_handle *handle); 513 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 514 515 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 516 u32 *tx_usecs, u32 *rx_usecs); 517 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 518 u32 *tx_frames, u32 *rx_frames); 519 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 520 int (*set_coalesce_frames)(struct hnae3_handle *handle, 521 u32 coalesce_frames); 522 void (*get_coalesce_range)(struct hnae3_handle *handle, 523 u32 *tx_frames_low, u32 *rx_frames_low, 524 u32 *tx_frames_high, u32 *rx_frames_high, 525 u32 *tx_usecs_low, u32 *rx_usecs_low, 526 u32 *tx_usecs_high, u32 *rx_usecs_high); 527 528 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 529 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 530 bool is_first); 531 int (*do_ioctl)(struct hnae3_handle *handle, 532 struct ifreq *ifr, int cmd); 533 int (*add_uc_addr)(struct hnae3_handle *handle, 534 const unsigned char *addr); 535 int (*rm_uc_addr)(struct hnae3_handle *handle, 536 const unsigned char *addr); 537 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 538 int (*add_mc_addr)(struct hnae3_handle *handle, 539 const unsigned char *addr); 540 int (*rm_mc_addr)(struct hnae3_handle *handle, 541 const unsigned char *addr); 542 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 543 void (*update_stats)(struct hnae3_handle *handle, 544 struct net_device_stats *net_stats); 545 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 546 void (*get_mac_stats)(struct hnae3_handle *handle, 547 struct hns3_mac_stats *mac_stats); 548 void (*get_strings)(struct hnae3_handle *handle, 549 u32 stringset, u8 *data); 550 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 551 552 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 553 void *data); 554 int (*get_regs_len)(struct hnae3_handle *handle); 555 556 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 557 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 558 u8 *hfunc); 559 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 560 const u8 *key, const u8 hfunc); 561 int (*set_rss_tuple)(struct hnae3_handle *handle, 562 struct ethtool_rxnfc *cmd); 563 int (*get_rss_tuple)(struct hnae3_handle *handle, 564 struct ethtool_rxnfc *cmd); 565 566 int (*get_tc_size)(struct hnae3_handle *handle); 567 568 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 569 struct hnae3_vector_info *vector_info); 570 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 571 int (*map_ring_to_vector)(struct hnae3_handle *handle, 572 int vector_num, 573 struct hnae3_ring_chain_node *vr_chain); 574 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 575 int vector_num, 576 struct hnae3_ring_chain_node *vr_chain); 577 578 int (*reset_queue)(struct hnae3_handle *handle, u16 queue_id); 579 u32 (*get_fw_version)(struct hnae3_handle *handle); 580 void (*get_mdix_mode)(struct hnae3_handle *handle, 581 u8 *tp_mdix_ctrl, u8 *tp_mdix); 582 583 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 584 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 585 u16 vlan_id, bool is_kill); 586 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 587 u16 vlan, u8 qos, __be16 proto); 588 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 589 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 590 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 591 unsigned long *addr); 592 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 593 enum hnae3_reset_type rst_type); 594 void (*get_channels)(struct hnae3_handle *handle, 595 struct ethtool_channels *ch); 596 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 597 u16 *alloc_tqps, u16 *max_rss_size); 598 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 599 bool rxfh_configured); 600 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 601 u32 *flowctrl_adv); 602 int (*set_led_id)(struct hnae3_handle *handle, 603 enum ethtool_phys_id_state status); 604 void (*get_link_mode)(struct hnae3_handle *handle, 605 unsigned long *supported, 606 unsigned long *advertising); 607 int (*add_fd_entry)(struct hnae3_handle *handle, 608 struct ethtool_rxnfc *cmd); 609 int (*del_fd_entry)(struct hnae3_handle *handle, 610 struct ethtool_rxnfc *cmd); 611 void (*del_all_fd_entries)(struct hnae3_handle *handle, 612 bool clear_list); 613 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 614 struct ethtool_rxnfc *cmd); 615 int (*get_fd_rule_info)(struct hnae3_handle *handle, 616 struct ethtool_rxnfc *cmd); 617 int (*get_fd_all_rules)(struct hnae3_handle *handle, 618 struct ethtool_rxnfc *cmd, u32 *rule_locs); 619 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 620 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 621 u16 flow_id, struct flow_keys *fkeys); 622 int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); 623 int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf, 624 char *buf, int len); 625 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 626 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 627 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 628 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 629 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 630 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 631 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 632 int (*mac_connect_phy)(struct hnae3_handle *handle); 633 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 634 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 635 struct ifla_vf_info *ivf); 636 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 637 int link_state); 638 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 639 bool enable); 640 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 641 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 642 int min_tx_rate, int max_tx_rate, bool force); 643 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 644 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 645 u32 len, u8 *data); 646 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 647 int (*add_cls_flower)(struct hnae3_handle *handle, 648 struct flow_cls_offload *cls_flower, int tc); 649 int (*del_cls_flower)(struct hnae3_handle *handle, 650 struct flow_cls_offload *cls_flower); 651 bool (*cls_flower_active)(struct hnae3_handle *handle); 652 }; 653 654 struct hnae3_dcb_ops { 655 /* IEEE 802.1Qaz std */ 656 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 657 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 658 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 659 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 660 661 /* DCBX configuration */ 662 u8 (*getdcbx)(struct hnae3_handle *); 663 u8 (*setdcbx)(struct hnae3_handle *, u8); 664 665 int (*setup_tc)(struct hnae3_handle *handle, 666 struct tc_mqprio_qopt_offload *mqprio_qopt); 667 }; 668 669 struct hnae3_ae_algo { 670 const struct hnae3_ae_ops *ops; 671 struct list_head node; 672 const struct pci_device_id *pdev_id_table; 673 }; 674 675 #define HNAE3_INT_NAME_LEN 32 676 #define HNAE3_ITR_COUNTDOWN_START 100 677 678 #define HNAE3_MAX_TC 8 679 #define HNAE3_MAX_USER_PRIO 8 680 struct hnae3_tc_info { 681 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 682 u16 tqp_count[HNAE3_MAX_TC]; 683 u16 tqp_offset[HNAE3_MAX_TC]; 684 unsigned long tc_en; /* bitmap of TC enabled */ 685 u8 num_tc; /* Total number of enabled TCs */ 686 bool mqprio_active; 687 }; 688 689 struct hnae3_knic_private_info { 690 struct net_device *netdev; /* Set by KNIC client when init instance */ 691 u16 rss_size; /* Allocated RSS queues */ 692 u16 req_rss_size; 693 u16 rx_buf_len; 694 u16 num_tx_desc; 695 u16 num_rx_desc; 696 697 struct hnae3_tc_info tc_info; 698 699 u16 num_tqps; /* total number of TQPs in this handle */ 700 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 701 const struct hnae3_dcb_ops *dcb_ops; 702 703 u16 int_rl_setting; 704 enum pkt_hash_types rss_type; 705 }; 706 707 struct hnae3_roce_private_info { 708 struct net_device *netdev; 709 void __iomem *roce_io_base; 710 void __iomem *roce_mem_base; 711 int base_vector; 712 int num_vectors; 713 714 /* The below attributes defined for RoCE client, hnae3 gives 715 * initial values to them, and RoCE client can modify and use 716 * them. 717 */ 718 unsigned long reset_state; 719 unsigned long instance_state; 720 unsigned long state; 721 }; 722 723 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 724 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 725 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 726 #define HNAE3_SUPPORT_VF BIT(3) 727 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 728 729 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 730 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 731 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 732 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 733 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 734 #define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ 735 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 736 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 737 738 enum hnae3_pflag { 739 HNAE3_PFLAG_LIMIT_PROMISC, 740 HNAE3_PFLAG_MAX 741 }; 742 743 struct hnae3_handle { 744 struct hnae3_client *client; 745 struct pci_dev *pdev; 746 void *priv; 747 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 748 u64 flags; /* Indicate the capabilities for this handle */ 749 750 union { 751 struct net_device *netdev; /* first member */ 752 struct hnae3_knic_private_info kinfo; 753 struct hnae3_roce_private_info rinfo; 754 }; 755 756 u32 numa_node_mask; /* for multi-chip support */ 757 758 enum hnae3_port_base_vlan_state port_base_vlan_state; 759 760 u8 netdev_flags; 761 struct dentry *hnae3_dbgfs; 762 763 /* Network interface message level enabled bits */ 764 u32 msg_enable; 765 766 unsigned long supported_pflags; 767 unsigned long priv_flags; 768 }; 769 770 #define hnae3_set_field(origin, mask, shift, val) \ 771 do { \ 772 (origin) &= (~(mask)); \ 773 (origin) |= ((val) << (shift)) & (mask); \ 774 } while (0) 775 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 776 777 #define hnae3_set_bit(origin, shift, val) \ 778 hnae3_set_field(origin, 0x1 << (shift), shift, val) 779 #define hnae3_get_bit(origin, shift) \ 780 hnae3_get_field(origin, 0x1 << (shift), shift) 781 782 #define HNAE3_DBG_TM_NODES "tm_nodes" 783 #define HNAE3_DBG_TM_PRI "tm_priority" 784 #define HNAE3_DBG_TM_QSET "tm_qset" 785 786 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 787 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 788 789 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 790 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 791 792 void hnae3_unregister_client(struct hnae3_client *client); 793 int hnae3_register_client(struct hnae3_client *client); 794 795 void hnae3_set_client_init_flag(struct hnae3_client *client, 796 struct hnae3_ae_dev *ae_dev, 797 unsigned int inited); 798 #endif 799