1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 HNAE3_DEV_SUPPORT_PAUSE_B, 94 HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 95 }; 96 97 #define hnae3_dev_fd_supported(hdev) \ 98 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 99 100 #define hnae3_dev_gro_supported(hdev) \ 101 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 102 103 #define hnae3_dev_fec_supported(hdev) \ 104 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 105 106 #define hnae3_dev_udp_gso_supported(hdev) \ 107 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 108 109 #define hnae3_dev_qb_supported(hdev) \ 110 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 111 112 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 113 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 114 115 #define hnae3_dev_ptp_supported(hdev) \ 116 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 117 118 #define hnae3_dev_int_ql_supported(hdev) \ 119 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 120 121 #define hnae3_dev_hw_csum_supported(hdev) \ 122 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 123 124 #define hnae3_dev_tx_push_supported(hdev) \ 125 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 126 127 #define hnae3_dev_phy_imp_supported(hdev) \ 128 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 129 130 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 131 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 132 133 #define hnae3_dev_hw_pad_supported(hdev) \ 134 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 135 136 #define hnae3_dev_stash_supported(hdev) \ 137 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 138 139 #define hnae3_dev_pause_supported(hdev) \ 140 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 141 142 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 143 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 144 145 #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \ 146 test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps) 147 148 #define ring_ptr_move_fw(ring, p) \ 149 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 150 #define ring_ptr_move_bw(ring, p) \ 151 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 152 153 enum hns_desc_type { 154 DESC_TYPE_UNKNOWN, 155 DESC_TYPE_SKB, 156 DESC_TYPE_FRAGLIST_SKB, 157 DESC_TYPE_PAGE, 158 }; 159 160 struct hnae3_handle; 161 162 struct hnae3_queue { 163 void __iomem *io_base; 164 struct hnae3_ae_algo *ae_algo; 165 struct hnae3_handle *handle; 166 int tqp_index; /* index in a handle */ 167 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 168 u16 tx_desc_num; /* total number of tx desc */ 169 u16 rx_desc_num; /* total number of rx desc */ 170 }; 171 172 struct hns3_mac_stats { 173 u64 tx_pause_cnt; 174 u64 rx_pause_cnt; 175 }; 176 177 /* hnae3 loop mode */ 178 enum hnae3_loop { 179 HNAE3_LOOP_APP, 180 HNAE3_LOOP_SERIAL_SERDES, 181 HNAE3_LOOP_PARALLEL_SERDES, 182 HNAE3_LOOP_PHY, 183 HNAE3_LOOP_NONE, 184 }; 185 186 enum hnae3_client_type { 187 HNAE3_CLIENT_KNIC, 188 HNAE3_CLIENT_ROCE, 189 }; 190 191 /* mac media type */ 192 enum hnae3_media_type { 193 HNAE3_MEDIA_TYPE_UNKNOWN, 194 HNAE3_MEDIA_TYPE_FIBER, 195 HNAE3_MEDIA_TYPE_COPPER, 196 HNAE3_MEDIA_TYPE_BACKPLANE, 197 HNAE3_MEDIA_TYPE_NONE, 198 }; 199 200 /* must be consistent with definition in firmware */ 201 enum hnae3_module_type { 202 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 203 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 204 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 205 HNAE3_MODULE_TYPE_AOC = 0x03, 206 HNAE3_MODULE_TYPE_CR = 0x04, 207 HNAE3_MODULE_TYPE_KR = 0x05, 208 HNAE3_MODULE_TYPE_TP = 0x06, 209 }; 210 211 enum hnae3_fec_mode { 212 HNAE3_FEC_AUTO = 0, 213 HNAE3_FEC_BASER, 214 HNAE3_FEC_RS, 215 HNAE3_FEC_USER_DEF, 216 }; 217 218 enum hnae3_reset_notify_type { 219 HNAE3_UP_CLIENT, 220 HNAE3_DOWN_CLIENT, 221 HNAE3_INIT_CLIENT, 222 HNAE3_UNINIT_CLIENT, 223 }; 224 225 enum hnae3_hw_error_type { 226 HNAE3_PPU_POISON_ERROR, 227 HNAE3_CMDQ_ECC_ERROR, 228 HNAE3_IMP_RD_POISON_ERROR, 229 HNAE3_ROCEE_AXI_RESP_ERROR, 230 }; 231 232 enum hnae3_reset_type { 233 HNAE3_VF_RESET, 234 HNAE3_VF_FUNC_RESET, 235 HNAE3_VF_PF_FUNC_RESET, 236 HNAE3_VF_FULL_RESET, 237 HNAE3_FLR_RESET, 238 HNAE3_FUNC_RESET, 239 HNAE3_GLOBAL_RESET, 240 HNAE3_IMP_RESET, 241 HNAE3_UNKNOWN_RESET, 242 HNAE3_NONE_RESET, 243 HNAE3_MAX_RESET, 244 }; 245 246 enum hnae3_port_base_vlan_state { 247 HNAE3_PORT_BASE_VLAN_DISABLE, 248 HNAE3_PORT_BASE_VLAN_ENABLE, 249 HNAE3_PORT_BASE_VLAN_MODIFY, 250 HNAE3_PORT_BASE_VLAN_NOCHANGE, 251 }; 252 253 enum hnae3_dbg_cmd { 254 HNAE3_DBG_CMD_TM_NODES, 255 HNAE3_DBG_CMD_TM_PRI, 256 HNAE3_DBG_CMD_TM_QSET, 257 HNAE3_DBG_CMD_TM_MAP, 258 HNAE3_DBG_CMD_TM_PG, 259 HNAE3_DBG_CMD_TM_PORT, 260 HNAE3_DBG_CMD_TC_SCH_INFO, 261 HNAE3_DBG_CMD_QOS_PAUSE_CFG, 262 HNAE3_DBG_CMD_QOS_PRI_MAP, 263 HNAE3_DBG_CMD_QOS_BUF_CFG, 264 HNAE3_DBG_CMD_DEV_INFO, 265 HNAE3_DBG_CMD_TX_BD, 266 HNAE3_DBG_CMD_RX_BD, 267 HNAE3_DBG_CMD_MAC_UC, 268 HNAE3_DBG_CMD_MAC_MC, 269 HNAE3_DBG_CMD_MNG_TBL, 270 HNAE3_DBG_CMD_LOOPBACK, 271 HNAE3_DBG_CMD_INTERRUPT_INFO, 272 HNAE3_DBG_CMD_RESET_INFO, 273 HNAE3_DBG_CMD_IMP_INFO, 274 HNAE3_DBG_CMD_NCL_CONFIG, 275 HNAE3_DBG_CMD_REG_BIOS_COMMON, 276 HNAE3_DBG_CMD_REG_SSU, 277 HNAE3_DBG_CMD_REG_IGU_EGU, 278 HNAE3_DBG_CMD_REG_RPU, 279 HNAE3_DBG_CMD_REG_NCSI, 280 HNAE3_DBG_CMD_REG_RTC, 281 HNAE3_DBG_CMD_REG_PPP, 282 HNAE3_DBG_CMD_REG_RCB, 283 HNAE3_DBG_CMD_REG_TQP, 284 HNAE3_DBG_CMD_REG_MAC, 285 HNAE3_DBG_CMD_REG_DCB, 286 HNAE3_DBG_CMD_QUEUE_MAP, 287 HNAE3_DBG_CMD_RX_QUEUE_INFO, 288 HNAE3_DBG_CMD_TX_QUEUE_INFO, 289 HNAE3_DBG_CMD_FD_TCAM, 290 HNAE3_DBG_CMD_MAC_TNL_STATUS, 291 HNAE3_DBG_CMD_SERV_INFO, 292 HNAE3_DBG_CMD_UNKNOWN, 293 }; 294 295 struct hnae3_vector_info { 296 u8 __iomem *io_addr; 297 int vector; 298 }; 299 300 #define HNAE3_RING_TYPE_B 0 301 #define HNAE3_RING_TYPE_TX 0 302 #define HNAE3_RING_TYPE_RX 1 303 #define HNAE3_RING_GL_IDX_S 0 304 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 305 #define HNAE3_RING_GL_RX 0 306 #define HNAE3_RING_GL_TX 1 307 308 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 309 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 310 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 311 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 312 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 313 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 314 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 315 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 316 317 struct hnae3_ring_chain_node { 318 struct hnae3_ring_chain_node *next; 319 u32 tqp_index; 320 u32 flag; 321 u32 int_gl_idx; 322 }; 323 324 #define HNAE3_IS_TX_RING(node) \ 325 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 326 327 /* device specification info from firmware */ 328 struct hnae3_dev_specs { 329 u32 mac_entry_num; /* number of mac-vlan table entry */ 330 u32 mng_entry_num; /* number of manager table entry */ 331 u32 max_tm_rate; 332 u16 rss_ind_tbl_size; 333 u16 rss_key_size; 334 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 335 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 336 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 337 u16 max_frm_size; 338 u16 max_qset_num; 339 }; 340 341 struct hnae3_client_ops { 342 int (*init_instance)(struct hnae3_handle *handle); 343 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 344 void (*link_status_change)(struct hnae3_handle *handle, bool state); 345 int (*reset_notify)(struct hnae3_handle *handle, 346 enum hnae3_reset_notify_type type); 347 void (*process_hw_error)(struct hnae3_handle *handle, 348 enum hnae3_hw_error_type); 349 }; 350 351 #define HNAE3_CLIENT_NAME_LENGTH 16 352 struct hnae3_client { 353 char name[HNAE3_CLIENT_NAME_LENGTH]; 354 unsigned long state; 355 enum hnae3_client_type type; 356 const struct hnae3_client_ops *ops; 357 struct list_head node; 358 }; 359 360 #define HNAE3_DEV_CAPS_MAX_NUM 96 361 struct hnae3_ae_dev { 362 struct pci_dev *pdev; 363 const struct hnae3_ae_ops *ops; 364 struct list_head node; 365 u32 flag; 366 unsigned long hw_err_reset_req; 367 struct hnae3_dev_specs dev_specs; 368 u32 dev_version; 369 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 370 void *priv; 371 }; 372 373 /* This struct defines the operation on the handle. 374 * 375 * init_ae_dev(): (mandatory) 376 * Get PF configure from pci_dev and initialize PF hardware 377 * uninit_ae_dev() 378 * Disable PF device and release PF resource 379 * register_client 380 * Register client to ae_dev 381 * unregister_client() 382 * Unregister client from ae_dev 383 * start() 384 * Enable the hardware 385 * stop() 386 * Disable the hardware 387 * start_client() 388 * Inform the hclge that client has been started 389 * stop_client() 390 * Inform the hclge that client has been stopped 391 * get_status() 392 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 393 * non-ok 394 * get_ksettings_an_result() 395 * Get negotiation status,speed and duplex 396 * get_media_type() 397 * Get media type of MAC 398 * check_port_speed() 399 * Check target speed whether is supported 400 * adjust_link() 401 * Adjust link status 402 * set_loopback() 403 * Set loopback 404 * set_promisc_mode 405 * Set promisc mode 406 * request_update_promisc_mode 407 * request to hclge(vf) to update promisc mode 408 * set_mtu() 409 * set mtu 410 * get_pauseparam() 411 * get tx and rx of pause frame use 412 * set_pauseparam() 413 * set tx and rx of pause frame use 414 * set_autoneg() 415 * set auto autonegotiation of pause frame use 416 * get_autoneg() 417 * get auto autonegotiation of pause frame use 418 * restart_autoneg() 419 * restart autonegotiation 420 * halt_autoneg() 421 * halt/resume autonegotiation when autonegotiation on 422 * get_coalesce_usecs() 423 * get usecs to delay a TX interrupt after a packet is sent 424 * get_rx_max_coalesced_frames() 425 * get Maximum number of packets to be sent before a TX interrupt. 426 * set_coalesce_usecs() 427 * set usecs to delay a TX interrupt after a packet is sent 428 * set_coalesce_frames() 429 * set Maximum number of packets to be sent before a TX interrupt. 430 * get_mac_addr() 431 * get mac address 432 * set_mac_addr() 433 * set mac address 434 * add_uc_addr 435 * Add unicast addr to mac table 436 * rm_uc_addr 437 * Remove unicast addr from mac table 438 * set_mc_addr() 439 * Set multicast address 440 * add_mc_addr 441 * Add multicast address to mac table 442 * rm_mc_addr 443 * Remove multicast address from mac table 444 * update_stats() 445 * Update Old network device statistics 446 * get_mac_stats() 447 * get mac pause statistics including tx_cnt and rx_cnt 448 * get_ethtool_stats() 449 * Get ethtool network device statistics 450 * get_strings() 451 * Get a set of strings that describe the requested objects 452 * get_sset_count() 453 * Get number of strings that @get_strings will write 454 * update_led_status() 455 * Update the led status 456 * set_led_id() 457 * Set led id 458 * get_regs() 459 * Get regs dump 460 * get_regs_len() 461 * Get the len of the regs dump 462 * get_rss_key_size() 463 * Get rss key size 464 * get_rss() 465 * Get rss table 466 * set_rss() 467 * Set rss table 468 * get_tc_size() 469 * Get tc size of handle 470 * get_vector() 471 * Get vector number and vector information 472 * put_vector() 473 * Put the vector in hdev 474 * map_ring_to_vector() 475 * Map rings to vector 476 * unmap_ring_from_vector() 477 * Unmap rings from vector 478 * reset_queue() 479 * Reset queue 480 * get_fw_version() 481 * Get firmware version 482 * get_mdix_mode() 483 * Get media typr of phy 484 * enable_vlan_filter() 485 * Enable vlan filter 486 * set_vlan_filter() 487 * Set vlan filter config of Ports 488 * set_vf_vlan_filter() 489 * Set vlan filter config of vf 490 * enable_hw_strip_rxvtag() 491 * Enable/disable hardware strip vlan tag of packets received 492 * set_gro_en 493 * Enable/disable HW GRO 494 * add_arfs_entry 495 * Check the 5-tuples of flow, and create flow director rule 496 * get_vf_config 497 * Get the VF configuration setting by the host 498 * set_vf_link_state 499 * Set VF link status 500 * set_vf_spoofchk 501 * Enable/disable spoof check for specified vf 502 * set_vf_trust 503 * Enable/disable trust for specified vf, if the vf being trusted, then 504 * it can enable promisc mode 505 * set_vf_rate 506 * Set the max tx rate of specified vf. 507 * set_vf_mac 508 * Configure the default MAC for specified VF 509 * get_module_eeprom 510 * Get the optical module eeprom info. 511 * add_cls_flower 512 * Add clsflower rule 513 * del_cls_flower 514 * Delete clsflower rule 515 * cls_flower_active 516 * Check if any cls flower rule exist 517 * dbg_read_cmd 518 * Execute debugfs read command. 519 */ 520 struct hnae3_ae_ops { 521 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 522 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 523 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 524 enum hnae3_reset_type rst_type); 525 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 526 int (*init_client_instance)(struct hnae3_client *client, 527 struct hnae3_ae_dev *ae_dev); 528 void (*uninit_client_instance)(struct hnae3_client *client, 529 struct hnae3_ae_dev *ae_dev); 530 int (*start)(struct hnae3_handle *handle); 531 void (*stop)(struct hnae3_handle *handle); 532 int (*client_start)(struct hnae3_handle *handle); 533 void (*client_stop)(struct hnae3_handle *handle); 534 int (*get_status)(struct hnae3_handle *handle); 535 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 536 u8 *auto_neg, u32 *speed, u8 *duplex); 537 538 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 539 u8 duplex); 540 541 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 542 u8 *module_type); 543 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 544 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 545 u8 *fec_mode); 546 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 547 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 548 int (*set_loopback)(struct hnae3_handle *handle, 549 enum hnae3_loop loop_mode, bool en); 550 551 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 552 bool en_mc_pmc); 553 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 554 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 555 556 void (*get_pauseparam)(struct hnae3_handle *handle, 557 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 558 int (*set_pauseparam)(struct hnae3_handle *handle, 559 u32 auto_neg, u32 rx_en, u32 tx_en); 560 561 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 562 int (*get_autoneg)(struct hnae3_handle *handle); 563 int (*restart_autoneg)(struct hnae3_handle *handle); 564 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 565 566 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 567 u32 *tx_usecs, u32 *rx_usecs); 568 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 569 u32 *tx_frames, u32 *rx_frames); 570 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 571 int (*set_coalesce_frames)(struct hnae3_handle *handle, 572 u32 coalesce_frames); 573 void (*get_coalesce_range)(struct hnae3_handle *handle, 574 u32 *tx_frames_low, u32 *rx_frames_low, 575 u32 *tx_frames_high, u32 *rx_frames_high, 576 u32 *tx_usecs_low, u32 *rx_usecs_low, 577 u32 *tx_usecs_high, u32 *rx_usecs_high); 578 579 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 580 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 581 bool is_first); 582 int (*do_ioctl)(struct hnae3_handle *handle, 583 struct ifreq *ifr, int cmd); 584 int (*add_uc_addr)(struct hnae3_handle *handle, 585 const unsigned char *addr); 586 int (*rm_uc_addr)(struct hnae3_handle *handle, 587 const unsigned char *addr); 588 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 589 int (*add_mc_addr)(struct hnae3_handle *handle, 590 const unsigned char *addr); 591 int (*rm_mc_addr)(struct hnae3_handle *handle, 592 const unsigned char *addr); 593 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 594 void (*update_stats)(struct hnae3_handle *handle, 595 struct net_device_stats *net_stats); 596 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 597 void (*get_mac_stats)(struct hnae3_handle *handle, 598 struct hns3_mac_stats *mac_stats); 599 void (*get_strings)(struct hnae3_handle *handle, 600 u32 stringset, u8 *data); 601 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 602 603 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 604 void *data); 605 int (*get_regs_len)(struct hnae3_handle *handle); 606 607 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 608 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 609 u8 *hfunc); 610 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 611 const u8 *key, const u8 hfunc); 612 int (*set_rss_tuple)(struct hnae3_handle *handle, 613 struct ethtool_rxnfc *cmd); 614 int (*get_rss_tuple)(struct hnae3_handle *handle, 615 struct ethtool_rxnfc *cmd); 616 617 int (*get_tc_size)(struct hnae3_handle *handle); 618 619 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 620 struct hnae3_vector_info *vector_info); 621 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 622 int (*map_ring_to_vector)(struct hnae3_handle *handle, 623 int vector_num, 624 struct hnae3_ring_chain_node *vr_chain); 625 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 626 int vector_num, 627 struct hnae3_ring_chain_node *vr_chain); 628 629 int (*reset_queue)(struct hnae3_handle *handle); 630 u32 (*get_fw_version)(struct hnae3_handle *handle); 631 void (*get_mdix_mode)(struct hnae3_handle *handle, 632 u8 *tp_mdix_ctrl, u8 *tp_mdix); 633 634 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 635 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 636 u16 vlan_id, bool is_kill); 637 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 638 u16 vlan, u8 qos, __be16 proto); 639 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 640 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 641 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 642 unsigned long *addr); 643 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 644 enum hnae3_reset_type rst_type); 645 void (*get_channels)(struct hnae3_handle *handle, 646 struct ethtool_channels *ch); 647 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 648 u16 *alloc_tqps, u16 *max_rss_size); 649 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 650 bool rxfh_configured); 651 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 652 u32 *flowctrl_adv); 653 int (*set_led_id)(struct hnae3_handle *handle, 654 enum ethtool_phys_id_state status); 655 void (*get_link_mode)(struct hnae3_handle *handle, 656 unsigned long *supported, 657 unsigned long *advertising); 658 int (*add_fd_entry)(struct hnae3_handle *handle, 659 struct ethtool_rxnfc *cmd); 660 int (*del_fd_entry)(struct hnae3_handle *handle, 661 struct ethtool_rxnfc *cmd); 662 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 663 struct ethtool_rxnfc *cmd); 664 int (*get_fd_rule_info)(struct hnae3_handle *handle, 665 struct ethtool_rxnfc *cmd); 666 int (*get_fd_all_rules)(struct hnae3_handle *handle, 667 struct ethtool_rxnfc *cmd, u32 *rule_locs); 668 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 669 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 670 u16 flow_id, struct flow_keys *fkeys); 671 int (*dbg_read_cmd)(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 672 char *buf, int len); 673 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 674 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 675 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 676 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 677 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 678 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 679 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 680 int (*mac_connect_phy)(struct hnae3_handle *handle); 681 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 682 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 683 struct ifla_vf_info *ivf); 684 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 685 int link_state); 686 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 687 bool enable); 688 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 689 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 690 int min_tx_rate, int max_tx_rate, bool force); 691 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 692 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 693 u32 len, u8 *data); 694 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 695 int (*add_cls_flower)(struct hnae3_handle *handle, 696 struct flow_cls_offload *cls_flower, int tc); 697 int (*del_cls_flower)(struct hnae3_handle *handle, 698 struct flow_cls_offload *cls_flower); 699 bool (*cls_flower_active)(struct hnae3_handle *handle); 700 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 701 struct ethtool_link_ksettings *cmd); 702 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 703 const struct ethtool_link_ksettings *cmd); 704 }; 705 706 struct hnae3_dcb_ops { 707 /* IEEE 802.1Qaz std */ 708 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 709 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 710 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 711 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 712 713 /* DCBX configuration */ 714 u8 (*getdcbx)(struct hnae3_handle *); 715 u8 (*setdcbx)(struct hnae3_handle *, u8); 716 717 int (*setup_tc)(struct hnae3_handle *handle, 718 struct tc_mqprio_qopt_offload *mqprio_qopt); 719 }; 720 721 struct hnae3_ae_algo { 722 const struct hnae3_ae_ops *ops; 723 struct list_head node; 724 const struct pci_device_id *pdev_id_table; 725 }; 726 727 #define HNAE3_INT_NAME_LEN 32 728 #define HNAE3_ITR_COUNTDOWN_START 100 729 730 #define HNAE3_MAX_TC 8 731 #define HNAE3_MAX_USER_PRIO 8 732 struct hnae3_tc_info { 733 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 734 u16 tqp_count[HNAE3_MAX_TC]; 735 u16 tqp_offset[HNAE3_MAX_TC]; 736 unsigned long tc_en; /* bitmap of TC enabled */ 737 u8 num_tc; /* Total number of enabled TCs */ 738 bool mqprio_active; 739 }; 740 741 struct hnae3_knic_private_info { 742 struct net_device *netdev; /* Set by KNIC client when init instance */ 743 u16 rss_size; /* Allocated RSS queues */ 744 u16 req_rss_size; 745 u16 rx_buf_len; 746 u16 num_tx_desc; 747 u16 num_rx_desc; 748 749 struct hnae3_tc_info tc_info; 750 751 u16 num_tqps; /* total number of TQPs in this handle */ 752 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 753 const struct hnae3_dcb_ops *dcb_ops; 754 755 u16 int_rl_setting; 756 enum pkt_hash_types rss_type; 757 }; 758 759 struct hnae3_roce_private_info { 760 struct net_device *netdev; 761 void __iomem *roce_io_base; 762 void __iomem *roce_mem_base; 763 int base_vector; 764 int num_vectors; 765 766 /* The below attributes defined for RoCE client, hnae3 gives 767 * initial values to them, and RoCE client can modify and use 768 * them. 769 */ 770 unsigned long reset_state; 771 unsigned long instance_state; 772 unsigned long state; 773 }; 774 775 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 776 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 777 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 778 #define HNAE3_SUPPORT_VF BIT(3) 779 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 780 781 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 782 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 783 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 784 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 785 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 786 #define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ 787 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 788 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 789 790 enum hnae3_pflag { 791 HNAE3_PFLAG_LIMIT_PROMISC, 792 HNAE3_PFLAG_MAX 793 }; 794 795 struct hnae3_handle { 796 struct hnae3_client *client; 797 struct pci_dev *pdev; 798 void *priv; 799 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 800 u64 flags; /* Indicate the capabilities for this handle */ 801 802 union { 803 struct net_device *netdev; /* first member */ 804 struct hnae3_knic_private_info kinfo; 805 struct hnae3_roce_private_info rinfo; 806 }; 807 808 u32 numa_node_mask; /* for multi-chip support */ 809 810 enum hnae3_port_base_vlan_state port_base_vlan_state; 811 812 u8 netdev_flags; 813 struct dentry *hnae3_dbgfs; 814 815 /* Network interface message level enabled bits */ 816 u32 msg_enable; 817 818 unsigned long supported_pflags; 819 unsigned long priv_flags; 820 }; 821 822 #define hnae3_set_field(origin, mask, shift, val) \ 823 do { \ 824 (origin) &= (~(mask)); \ 825 (origin) |= ((val) << (shift)) & (mask); \ 826 } while (0) 827 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 828 829 #define hnae3_set_bit(origin, shift, val) \ 830 hnae3_set_field(origin, 0x1 << (shift), shift, val) 831 #define hnae3_get_bit(origin, shift) \ 832 hnae3_get_field(origin, 0x1 << (shift), shift) 833 834 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 835 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 836 837 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 838 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 839 840 void hnae3_unregister_client(struct hnae3_client *client); 841 int hnae3_register_client(struct hnae3_client *client); 842 843 void hnae3_set_client_init_flag(struct hnae3_client *client, 844 struct hnae3_ae_dev *ae_dev, 845 unsigned int inited); 846 #endif 847