1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNAE3_H 5 #define __HNAE3_H 6 7 /* Names used in this framework: 8 * ae handle (handle): 9 * a set of queues provided by AE 10 * ring buffer queue (rbq): 11 * the channel between upper layer and the AE, can do tx and rx 12 * ring: 13 * a tx or rx channel within a rbq 14 * ring description (desc): 15 * an element in the ring with packet information 16 * buffer: 17 * a memory region referred by desc with the full packet payload 18 * 19 * "num" means a static number set as a parameter, "count" mean a dynamic 20 * number set while running 21 * "cb" means control block 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/dcbnl.h> 26 #include <linux/delay.h> 27 #include <linux/device.h> 28 #include <linux/ethtool.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/pci.h> 32 #include <linux/pkt_sched.h> 33 #include <linux/types.h> 34 #include <net/pkt_cls.h> 35 36 #define HNAE3_MOD_VERSION "1.0" 37 38 #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 39 40 /* Device version */ 41 #define HNAE3_DEVICE_VERSION_V1 0x00020 42 #define HNAE3_DEVICE_VERSION_V2 0x00021 43 #define HNAE3_DEVICE_VERSION_V3 0x00030 44 45 #define HNAE3_PCI_REVISION_BIT_SIZE 8 46 47 /* Device IDs */ 48 #define HNAE3_DEV_ID_GE 0xA220 49 #define HNAE3_DEV_ID_25GE 0xA221 50 #define HNAE3_DEV_ID_25GE_RDMA 0xA222 51 #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 52 #define HNAE3_DEV_ID_50GE_RDMA 0xA224 53 #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 54 #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 55 #define HNAE3_DEV_ID_200G_RDMA 0xA228 56 #define HNAE3_DEV_ID_VF 0xA22E 57 #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 58 59 #define HNAE3_CLASS_NAME_SIZE 16 60 61 #define HNAE3_DEV_INITED_B 0x0 62 #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 63 #define HNAE3_DEV_SUPPORT_DCB_B 0x2 64 #define HNAE3_KNIC_CLIENT_INITED_B 0x3 65 #define HNAE3_UNIC_CLIENT_INITED_B 0x4 66 #define HNAE3_ROCE_CLIENT_INITED_B 0x5 67 68 #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 69 BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 70 71 #define hnae3_dev_roce_supported(hdev) \ 72 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 73 74 #define hnae3_dev_dcb_supported(hdev) \ 75 hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 76 77 enum HNAE3_DEV_CAP_BITS { 78 HNAE3_DEV_SUPPORT_FD_B, 79 HNAE3_DEV_SUPPORT_GRO_B, 80 HNAE3_DEV_SUPPORT_FEC_B, 81 HNAE3_DEV_SUPPORT_UDP_GSO_B, 82 HNAE3_DEV_SUPPORT_QB_B, 83 HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 84 HNAE3_DEV_SUPPORT_PTP_B, 85 HNAE3_DEV_SUPPORT_INT_QL_B, 86 HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, 87 HNAE3_DEV_SUPPORT_TX_PUSH_B, 88 HNAE3_DEV_SUPPORT_PHY_IMP_B, 89 HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 90 HNAE3_DEV_SUPPORT_HW_PAD_B, 91 HNAE3_DEV_SUPPORT_STASH_B, 92 HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, 93 HNAE3_DEV_SUPPORT_PAUSE_B, 94 }; 95 96 #define hnae3_dev_fd_supported(hdev) \ 97 test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 98 99 #define hnae3_dev_gro_supported(hdev) \ 100 test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 101 102 #define hnae3_dev_fec_supported(hdev) \ 103 test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 104 105 #define hnae3_dev_udp_gso_supported(hdev) \ 106 test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 107 108 #define hnae3_dev_qb_supported(hdev) \ 109 test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 110 111 #define hnae3_dev_fd_forward_tc_supported(hdev) \ 112 test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 113 114 #define hnae3_dev_ptp_supported(hdev) \ 115 test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 116 117 #define hnae3_dev_int_ql_supported(hdev) \ 118 test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 119 120 #define hnae3_dev_hw_csum_supported(hdev) \ 121 test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps) 122 123 #define hnae3_dev_tx_push_supported(hdev) \ 124 test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 125 126 #define hnae3_dev_phy_imp_supported(hdev) \ 127 test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 128 129 #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 130 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 131 132 #define hnae3_dev_hw_pad_supported(hdev) \ 133 test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 134 135 #define hnae3_dev_stash_supported(hdev) \ 136 test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 137 138 #define hnae3_dev_pause_supported(hdev) \ 139 test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps) 140 141 #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 142 test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 143 144 #define ring_ptr_move_fw(ring, p) \ 145 ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 146 #define ring_ptr_move_bw(ring, p) \ 147 ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 148 149 enum hns_desc_type { 150 DESC_TYPE_UNKNOWN, 151 DESC_TYPE_SKB, 152 DESC_TYPE_FRAGLIST_SKB, 153 DESC_TYPE_PAGE, 154 }; 155 156 struct hnae3_handle; 157 158 struct hnae3_queue { 159 void __iomem *io_base; 160 struct hnae3_ae_algo *ae_algo; 161 struct hnae3_handle *handle; 162 int tqp_index; /* index in a handle */ 163 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 164 u16 tx_desc_num; /* total number of tx desc */ 165 u16 rx_desc_num; /* total number of rx desc */ 166 }; 167 168 struct hns3_mac_stats { 169 u64 tx_pause_cnt; 170 u64 rx_pause_cnt; 171 }; 172 173 /* hnae3 loop mode */ 174 enum hnae3_loop { 175 HNAE3_LOOP_APP, 176 HNAE3_LOOP_SERIAL_SERDES, 177 HNAE3_LOOP_PARALLEL_SERDES, 178 HNAE3_LOOP_PHY, 179 HNAE3_LOOP_NONE, 180 }; 181 182 enum hnae3_client_type { 183 HNAE3_CLIENT_KNIC, 184 HNAE3_CLIENT_ROCE, 185 }; 186 187 /* mac media type */ 188 enum hnae3_media_type { 189 HNAE3_MEDIA_TYPE_UNKNOWN, 190 HNAE3_MEDIA_TYPE_FIBER, 191 HNAE3_MEDIA_TYPE_COPPER, 192 HNAE3_MEDIA_TYPE_BACKPLANE, 193 HNAE3_MEDIA_TYPE_NONE, 194 }; 195 196 /* must be consistent with definition in firmware */ 197 enum hnae3_module_type { 198 HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 199 HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 200 HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 201 HNAE3_MODULE_TYPE_AOC = 0x03, 202 HNAE3_MODULE_TYPE_CR = 0x04, 203 HNAE3_MODULE_TYPE_KR = 0x05, 204 HNAE3_MODULE_TYPE_TP = 0x06, 205 }; 206 207 enum hnae3_fec_mode { 208 HNAE3_FEC_AUTO = 0, 209 HNAE3_FEC_BASER, 210 HNAE3_FEC_RS, 211 HNAE3_FEC_USER_DEF, 212 }; 213 214 enum hnae3_reset_notify_type { 215 HNAE3_UP_CLIENT, 216 HNAE3_DOWN_CLIENT, 217 HNAE3_INIT_CLIENT, 218 HNAE3_UNINIT_CLIENT, 219 }; 220 221 enum hnae3_hw_error_type { 222 HNAE3_PPU_POISON_ERROR, 223 HNAE3_CMDQ_ECC_ERROR, 224 HNAE3_IMP_RD_POISON_ERROR, 225 HNAE3_ROCEE_AXI_RESP_ERROR, 226 }; 227 228 enum hnae3_reset_type { 229 HNAE3_VF_RESET, 230 HNAE3_VF_FUNC_RESET, 231 HNAE3_VF_PF_FUNC_RESET, 232 HNAE3_VF_FULL_RESET, 233 HNAE3_FLR_RESET, 234 HNAE3_FUNC_RESET, 235 HNAE3_GLOBAL_RESET, 236 HNAE3_IMP_RESET, 237 HNAE3_UNKNOWN_RESET, 238 HNAE3_NONE_RESET, 239 HNAE3_MAX_RESET, 240 }; 241 242 enum hnae3_port_base_vlan_state { 243 HNAE3_PORT_BASE_VLAN_DISABLE, 244 HNAE3_PORT_BASE_VLAN_ENABLE, 245 HNAE3_PORT_BASE_VLAN_MODIFY, 246 HNAE3_PORT_BASE_VLAN_NOCHANGE, 247 }; 248 249 struct hnae3_vector_info { 250 u8 __iomem *io_addr; 251 int vector; 252 }; 253 254 #define HNAE3_RING_TYPE_B 0 255 #define HNAE3_RING_TYPE_TX 0 256 #define HNAE3_RING_TYPE_RX 1 257 #define HNAE3_RING_GL_IDX_S 0 258 #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 259 #define HNAE3_RING_GL_RX 0 260 #define HNAE3_RING_GL_TX 1 261 262 #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 263 #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 264 #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 265 #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 266 #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 267 #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 268 #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 269 #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 270 271 struct hnae3_ring_chain_node { 272 struct hnae3_ring_chain_node *next; 273 u32 tqp_index; 274 u32 flag; 275 u32 int_gl_idx; 276 }; 277 278 #define HNAE3_IS_TX_RING(node) \ 279 (((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX) 280 281 /* device specification info from firmware */ 282 struct hnae3_dev_specs { 283 u32 mac_entry_num; /* number of mac-vlan table entry */ 284 u32 mng_entry_num; /* number of manager table entry */ 285 u32 max_tm_rate; 286 u16 rss_ind_tbl_size; 287 u16 rss_key_size; 288 u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 289 u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */ 290 u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 291 u16 max_frm_size; 292 u16 max_qset_num; 293 }; 294 295 struct hnae3_client_ops { 296 int (*init_instance)(struct hnae3_handle *handle); 297 void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 298 void (*link_status_change)(struct hnae3_handle *handle, bool state); 299 int (*reset_notify)(struct hnae3_handle *handle, 300 enum hnae3_reset_notify_type type); 301 void (*process_hw_error)(struct hnae3_handle *handle, 302 enum hnae3_hw_error_type); 303 }; 304 305 #define HNAE3_CLIENT_NAME_LENGTH 16 306 struct hnae3_client { 307 char name[HNAE3_CLIENT_NAME_LENGTH]; 308 unsigned long state; 309 enum hnae3_client_type type; 310 const struct hnae3_client_ops *ops; 311 struct list_head node; 312 }; 313 314 #define HNAE3_DEV_CAPS_MAX_NUM 96 315 struct hnae3_ae_dev { 316 struct pci_dev *pdev; 317 const struct hnae3_ae_ops *ops; 318 struct list_head node; 319 u32 flag; 320 unsigned long hw_err_reset_req; 321 struct hnae3_dev_specs dev_specs; 322 u32 dev_version; 323 unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 324 void *priv; 325 }; 326 327 /* This struct defines the operation on the handle. 328 * 329 * init_ae_dev(): (mandatory) 330 * Get PF configure from pci_dev and initialize PF hardware 331 * uninit_ae_dev() 332 * Disable PF device and release PF resource 333 * register_client 334 * Register client to ae_dev 335 * unregister_client() 336 * Unregister client from ae_dev 337 * start() 338 * Enable the hardware 339 * stop() 340 * Disable the hardware 341 * start_client() 342 * Inform the hclge that client has been started 343 * stop_client() 344 * Inform the hclge that client has been stopped 345 * get_status() 346 * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 347 * non-ok 348 * get_ksettings_an_result() 349 * Get negotiation status,speed and duplex 350 * get_media_type() 351 * Get media type of MAC 352 * check_port_speed() 353 * Check target speed whether is supported 354 * adjust_link() 355 * Adjust link status 356 * set_loopback() 357 * Set loopback 358 * set_promisc_mode 359 * Set promisc mode 360 * request_update_promisc_mode 361 * request to hclge(vf) to update promisc mode 362 * set_mtu() 363 * set mtu 364 * get_pauseparam() 365 * get tx and rx of pause frame use 366 * set_pauseparam() 367 * set tx and rx of pause frame use 368 * set_autoneg() 369 * set auto autonegotiation of pause frame use 370 * get_autoneg() 371 * get auto autonegotiation of pause frame use 372 * restart_autoneg() 373 * restart autonegotiation 374 * halt_autoneg() 375 * halt/resume autonegotiation when autonegotiation on 376 * get_coalesce_usecs() 377 * get usecs to delay a TX interrupt after a packet is sent 378 * get_rx_max_coalesced_frames() 379 * get Maximum number of packets to be sent before a TX interrupt. 380 * set_coalesce_usecs() 381 * set usecs to delay a TX interrupt after a packet is sent 382 * set_coalesce_frames() 383 * set Maximum number of packets to be sent before a TX interrupt. 384 * get_mac_addr() 385 * get mac address 386 * set_mac_addr() 387 * set mac address 388 * add_uc_addr 389 * Add unicast addr to mac table 390 * rm_uc_addr 391 * Remove unicast addr from mac table 392 * set_mc_addr() 393 * Set multicast address 394 * add_mc_addr 395 * Add multicast address to mac table 396 * rm_mc_addr 397 * Remove multicast address from mac table 398 * update_stats() 399 * Update Old network device statistics 400 * get_mac_stats() 401 * get mac pause statistics including tx_cnt and rx_cnt 402 * get_ethtool_stats() 403 * Get ethtool network device statistics 404 * get_strings() 405 * Get a set of strings that describe the requested objects 406 * get_sset_count() 407 * Get number of strings that @get_strings will write 408 * update_led_status() 409 * Update the led status 410 * set_led_id() 411 * Set led id 412 * get_regs() 413 * Get regs dump 414 * get_regs_len() 415 * Get the len of the regs dump 416 * get_rss_key_size() 417 * Get rss key size 418 * get_rss() 419 * Get rss table 420 * set_rss() 421 * Set rss table 422 * get_tc_size() 423 * Get tc size of handle 424 * get_vector() 425 * Get vector number and vector information 426 * put_vector() 427 * Put the vector in hdev 428 * map_ring_to_vector() 429 * Map rings to vector 430 * unmap_ring_from_vector() 431 * Unmap rings from vector 432 * reset_queue() 433 * Reset queue 434 * get_fw_version() 435 * Get firmware version 436 * get_mdix_mode() 437 * Get media typr of phy 438 * enable_vlan_filter() 439 * Enable vlan filter 440 * set_vlan_filter() 441 * Set vlan filter config of Ports 442 * set_vf_vlan_filter() 443 * Set vlan filter config of vf 444 * enable_hw_strip_rxvtag() 445 * Enable/disable hardware strip vlan tag of packets received 446 * set_gro_en 447 * Enable/disable HW GRO 448 * add_arfs_entry 449 * Check the 5-tuples of flow, and create flow director rule 450 * get_vf_config 451 * Get the VF configuration setting by the host 452 * set_vf_link_state 453 * Set VF link status 454 * set_vf_spoofchk 455 * Enable/disable spoof check for specified vf 456 * set_vf_trust 457 * Enable/disable trust for specified vf, if the vf being trusted, then 458 * it can enable promisc mode 459 * set_vf_rate 460 * Set the max tx rate of specified vf. 461 * set_vf_mac 462 * Configure the default MAC for specified VF 463 * get_module_eeprom 464 * Get the optical module eeprom info. 465 * add_cls_flower 466 * Add clsflower rule 467 * del_cls_flower 468 * Delete clsflower rule 469 * cls_flower_active 470 * Check if any cls flower rule exist 471 * dbg_read_cmd 472 * Execute debugfs read command. 473 */ 474 struct hnae3_ae_ops { 475 int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 476 void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 477 void (*reset_prepare)(struct hnae3_ae_dev *ae_dev, 478 enum hnae3_reset_type rst_type); 479 void (*reset_done)(struct hnae3_ae_dev *ae_dev); 480 int (*init_client_instance)(struct hnae3_client *client, 481 struct hnae3_ae_dev *ae_dev); 482 void (*uninit_client_instance)(struct hnae3_client *client, 483 struct hnae3_ae_dev *ae_dev); 484 int (*start)(struct hnae3_handle *handle); 485 void (*stop)(struct hnae3_handle *handle); 486 int (*client_start)(struct hnae3_handle *handle); 487 void (*client_stop)(struct hnae3_handle *handle); 488 int (*get_status)(struct hnae3_handle *handle); 489 void (*get_ksettings_an_result)(struct hnae3_handle *handle, 490 u8 *auto_neg, u32 *speed, u8 *duplex); 491 492 int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 493 u8 duplex); 494 495 void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 496 u8 *module_type); 497 int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 498 void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 499 u8 *fec_mode); 500 int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 501 void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 502 int (*set_loopback)(struct hnae3_handle *handle, 503 enum hnae3_loop loop_mode, bool en); 504 505 int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 506 bool en_mc_pmc); 507 void (*request_update_promisc_mode)(struct hnae3_handle *handle); 508 int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 509 510 void (*get_pauseparam)(struct hnae3_handle *handle, 511 u32 *auto_neg, u32 *rx_en, u32 *tx_en); 512 int (*set_pauseparam)(struct hnae3_handle *handle, 513 u32 auto_neg, u32 rx_en, u32 tx_en); 514 515 int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 516 int (*get_autoneg)(struct hnae3_handle *handle); 517 int (*restart_autoneg)(struct hnae3_handle *handle); 518 int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 519 520 void (*get_coalesce_usecs)(struct hnae3_handle *handle, 521 u32 *tx_usecs, u32 *rx_usecs); 522 void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 523 u32 *tx_frames, u32 *rx_frames); 524 int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 525 int (*set_coalesce_frames)(struct hnae3_handle *handle, 526 u32 coalesce_frames); 527 void (*get_coalesce_range)(struct hnae3_handle *handle, 528 u32 *tx_frames_low, u32 *rx_frames_low, 529 u32 *tx_frames_high, u32 *rx_frames_high, 530 u32 *tx_usecs_low, u32 *rx_usecs_low, 531 u32 *tx_usecs_high, u32 *rx_usecs_high); 532 533 void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 534 int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 535 bool is_first); 536 int (*do_ioctl)(struct hnae3_handle *handle, 537 struct ifreq *ifr, int cmd); 538 int (*add_uc_addr)(struct hnae3_handle *handle, 539 const unsigned char *addr); 540 int (*rm_uc_addr)(struct hnae3_handle *handle, 541 const unsigned char *addr); 542 int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 543 int (*add_mc_addr)(struct hnae3_handle *handle, 544 const unsigned char *addr); 545 int (*rm_mc_addr)(struct hnae3_handle *handle, 546 const unsigned char *addr); 547 void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 548 void (*update_stats)(struct hnae3_handle *handle, 549 struct net_device_stats *net_stats); 550 void (*get_stats)(struct hnae3_handle *handle, u64 *data); 551 void (*get_mac_stats)(struct hnae3_handle *handle, 552 struct hns3_mac_stats *mac_stats); 553 void (*get_strings)(struct hnae3_handle *handle, 554 u32 stringset, u8 *data); 555 int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 556 557 void (*get_regs)(struct hnae3_handle *handle, u32 *version, 558 void *data); 559 int (*get_regs_len)(struct hnae3_handle *handle); 560 561 u32 (*get_rss_key_size)(struct hnae3_handle *handle); 562 int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 563 u8 *hfunc); 564 int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 565 const u8 *key, const u8 hfunc); 566 int (*set_rss_tuple)(struct hnae3_handle *handle, 567 struct ethtool_rxnfc *cmd); 568 int (*get_rss_tuple)(struct hnae3_handle *handle, 569 struct ethtool_rxnfc *cmd); 570 571 int (*get_tc_size)(struct hnae3_handle *handle); 572 573 int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 574 struct hnae3_vector_info *vector_info); 575 int (*put_vector)(struct hnae3_handle *handle, int vector_num); 576 int (*map_ring_to_vector)(struct hnae3_handle *handle, 577 int vector_num, 578 struct hnae3_ring_chain_node *vr_chain); 579 int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 580 int vector_num, 581 struct hnae3_ring_chain_node *vr_chain); 582 583 int (*reset_queue)(struct hnae3_handle *handle); 584 u32 (*get_fw_version)(struct hnae3_handle *handle); 585 void (*get_mdix_mode)(struct hnae3_handle *handle, 586 u8 *tp_mdix_ctrl, u8 *tp_mdix); 587 588 void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 589 int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 590 u16 vlan_id, bool is_kill); 591 int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 592 u16 vlan, u8 qos, __be16 proto); 593 int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 594 void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 595 enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 596 unsigned long *addr); 597 void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 598 enum hnae3_reset_type rst_type); 599 void (*get_channels)(struct hnae3_handle *handle, 600 struct ethtool_channels *ch); 601 void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 602 u16 *alloc_tqps, u16 *max_rss_size); 603 int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 604 bool rxfh_configured); 605 void (*get_flowctrl_adv)(struct hnae3_handle *handle, 606 u32 *flowctrl_adv); 607 int (*set_led_id)(struct hnae3_handle *handle, 608 enum ethtool_phys_id_state status); 609 void (*get_link_mode)(struct hnae3_handle *handle, 610 unsigned long *supported, 611 unsigned long *advertising); 612 int (*add_fd_entry)(struct hnae3_handle *handle, 613 struct ethtool_rxnfc *cmd); 614 int (*del_fd_entry)(struct hnae3_handle *handle, 615 struct ethtool_rxnfc *cmd); 616 int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 617 struct ethtool_rxnfc *cmd); 618 int (*get_fd_rule_info)(struct hnae3_handle *handle, 619 struct ethtool_rxnfc *cmd); 620 int (*get_fd_all_rules)(struct hnae3_handle *handle, 621 struct ethtool_rxnfc *cmd, u32 *rule_locs); 622 void (*enable_fd)(struct hnae3_handle *handle, bool enable); 623 int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 624 u16 flow_id, struct flow_keys *fkeys); 625 int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); 626 int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf, 627 char *buf, int len); 628 pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 629 bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 630 bool (*ae_dev_resetting)(struct hnae3_handle *handle); 631 unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 632 int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 633 u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 634 void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 635 int (*mac_connect_phy)(struct hnae3_handle *handle); 636 void (*mac_disconnect_phy)(struct hnae3_handle *handle); 637 int (*get_vf_config)(struct hnae3_handle *handle, int vf, 638 struct ifla_vf_info *ivf); 639 int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 640 int link_state); 641 int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 642 bool enable); 643 int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 644 int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 645 int min_tx_rate, int max_tx_rate, bool force); 646 int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 647 int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 648 u32 len, u8 *data); 649 bool (*get_cmdq_stat)(struct hnae3_handle *handle); 650 int (*add_cls_flower)(struct hnae3_handle *handle, 651 struct flow_cls_offload *cls_flower, int tc); 652 int (*del_cls_flower)(struct hnae3_handle *handle, 653 struct flow_cls_offload *cls_flower); 654 bool (*cls_flower_active)(struct hnae3_handle *handle); 655 int (*get_phy_link_ksettings)(struct hnae3_handle *handle, 656 struct ethtool_link_ksettings *cmd); 657 int (*set_phy_link_ksettings)(struct hnae3_handle *handle, 658 const struct ethtool_link_ksettings *cmd); 659 }; 660 661 struct hnae3_dcb_ops { 662 /* IEEE 802.1Qaz std */ 663 int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 664 int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 665 int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 666 int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 667 668 /* DCBX configuration */ 669 u8 (*getdcbx)(struct hnae3_handle *); 670 u8 (*setdcbx)(struct hnae3_handle *, u8); 671 672 int (*setup_tc)(struct hnae3_handle *handle, 673 struct tc_mqprio_qopt_offload *mqprio_qopt); 674 }; 675 676 struct hnae3_ae_algo { 677 const struct hnae3_ae_ops *ops; 678 struct list_head node; 679 const struct pci_device_id *pdev_id_table; 680 }; 681 682 #define HNAE3_INT_NAME_LEN 32 683 #define HNAE3_ITR_COUNTDOWN_START 100 684 685 #define HNAE3_MAX_TC 8 686 #define HNAE3_MAX_USER_PRIO 8 687 struct hnae3_tc_info { 688 u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 689 u16 tqp_count[HNAE3_MAX_TC]; 690 u16 tqp_offset[HNAE3_MAX_TC]; 691 unsigned long tc_en; /* bitmap of TC enabled */ 692 u8 num_tc; /* Total number of enabled TCs */ 693 bool mqprio_active; 694 }; 695 696 struct hnae3_knic_private_info { 697 struct net_device *netdev; /* Set by KNIC client when init instance */ 698 u16 rss_size; /* Allocated RSS queues */ 699 u16 req_rss_size; 700 u16 rx_buf_len; 701 u16 num_tx_desc; 702 u16 num_rx_desc; 703 704 struct hnae3_tc_info tc_info; 705 706 u16 num_tqps; /* total number of TQPs in this handle */ 707 struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 708 const struct hnae3_dcb_ops *dcb_ops; 709 710 u16 int_rl_setting; 711 enum pkt_hash_types rss_type; 712 }; 713 714 struct hnae3_roce_private_info { 715 struct net_device *netdev; 716 void __iomem *roce_io_base; 717 void __iomem *roce_mem_base; 718 int base_vector; 719 int num_vectors; 720 721 /* The below attributes defined for RoCE client, hnae3 gives 722 * initial values to them, and RoCE client can modify and use 723 * them. 724 */ 725 unsigned long reset_state; 726 unsigned long instance_state; 727 unsigned long state; 728 }; 729 730 #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 731 #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 732 #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 733 #define HNAE3_SUPPORT_VF BIT(3) 734 #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 735 736 #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 737 #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 738 #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 739 #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 740 #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 741 #define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ 742 #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 743 #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 744 745 enum hnae3_pflag { 746 HNAE3_PFLAG_LIMIT_PROMISC, 747 HNAE3_PFLAG_MAX 748 }; 749 750 struct hnae3_handle { 751 struct hnae3_client *client; 752 struct pci_dev *pdev; 753 void *priv; 754 struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 755 u64 flags; /* Indicate the capabilities for this handle */ 756 757 union { 758 struct net_device *netdev; /* first member */ 759 struct hnae3_knic_private_info kinfo; 760 struct hnae3_roce_private_info rinfo; 761 }; 762 763 u32 numa_node_mask; /* for multi-chip support */ 764 765 enum hnae3_port_base_vlan_state port_base_vlan_state; 766 767 u8 netdev_flags; 768 struct dentry *hnae3_dbgfs; 769 770 /* Network interface message level enabled bits */ 771 u32 msg_enable; 772 773 unsigned long supported_pflags; 774 unsigned long priv_flags; 775 }; 776 777 #define hnae3_set_field(origin, mask, shift, val) \ 778 do { \ 779 (origin) &= (~(mask)); \ 780 (origin) |= ((val) << (shift)) & (mask); \ 781 } while (0) 782 #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 783 784 #define hnae3_set_bit(origin, shift, val) \ 785 hnae3_set_field(origin, 0x1 << (shift), shift, val) 786 #define hnae3_get_bit(origin, shift) \ 787 hnae3_get_field(origin, 0x1 << (shift), shift) 788 789 #define HNAE3_DBG_TM_NODES "tm_nodes" 790 #define HNAE3_DBG_TM_PRI "tm_priority" 791 #define HNAE3_DBG_TM_QSET "tm_qset" 792 793 int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 794 void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 795 796 void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 797 void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 798 799 void hnae3_unregister_client(struct hnae3_client *client); 800 int hnae3_register_client(struct hnae3_client *client); 801 802 void hnae3_set_client_init_flag(struct hnae3_client *client, 803 struct hnae3_ae_dev *ae_dev, 804 unsigned int inited); 805 #endif 806