1 /*
2  * Copyright (c) 2014-2015 Hisilicon Limited.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #ifndef _DSAF_REG_H_
11 #define _DSAF_REG_H_
12 
13 #define HNS_GE_FIFO_ERR_INTNUM 8
14 #define HNS_XGE_ERR_INTNUM 6
15 #define HNS_RCB_COMM_ERR_INTNUM 12
16 #define HNS_PPE_TNL_ERR_INTNUM 8
17 #define HNS_DSAF_EVENT_INTNUM 21
18 #define HNS_DEBUG_RING_INTNUM 4
19 #define HNS_SERVICE_RING_INTNUM 256
20 
21 #define HNS_DEBUG_RING_IRQ_IDX (HNS_GE_FIFO_ERR_INTNUM + HNS_XGE_ERR_INTNUM +\
22 		HNS_RCB_COMM_ERR_INTNUM + HNS_PPE_TNL_ERR_INTNUM +\
23 		HNS_DSAF_EVENT_INTNUM)
24 #define HNS_SERVICE_RING_IRQ_IDX (HNS_DEBUG_RING_IRQ_IDX +\
25 		HNS_DEBUG_RING_INTNUM)
26 
27 #define DSAF_IRQ_NUM 18
28 
29 #define DSAF_MAX_PORT_NUM_PER_CHIP 8
30 #define DSAF_SERVICE_PORT_NUM_PER_DSAF 6
31 #define DSAF_MAX_VM_NUM 128
32 
33 #define DSAF_COMM_DEV_NUM 3
34 #define DSAF_PPE_INODE_BASE 6
35 #define HNS_DSAF_COMM_SERVICE_NW_IDX 0
36 #define DSAF_DEBUG_NW_NUM	2
37 #define DSAF_SERVICE_NW_NUM	6
38 #define DSAF_COMM_CHN		DSAF_SERVICE_NW_NUM
39 #define DSAF_GE_NUM		((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM))
40 #define DSAF_PORT_NUM		((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM))
41 #define DSAF_XGE_NUM		DSAF_SERVICE_NW_NUM
42 #define DSAF_NODE_NUM		18
43 #define DSAF_XOD_BIG_NUM	DSAF_NODE_NUM
44 #define DSAF_SBM_NUM		DSAF_NODE_NUM
45 #define DSAF_VOQ_NUM		DSAF_NODE_NUM
46 #define DSAF_INODE_NUM		DSAF_NODE_NUM
47 #define DSAF_XOD_NUM		8
48 #define DSAF_TBL_NUM		8
49 #define DSAF_SW_PORT_NUM	8
50 #define DSAF_TOTAL_QUEUE_NUM	129
51 
52 #define DSAF_TCAM_SUM		512
53 #define DSAF_LINE_SUM		(2048 * 14)
54 
55 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG                0x100
56 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG              0x180
57 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG              0x184
58 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG              0x188
59 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG              0x18C
60 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG              0x190
61 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG              0x194
62 #define DSAF_SUB_SC_DSAF_CLK_EN_REG                    0x300
63 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG                   0x304
64 #define DSAF_SUB_SC_NT_CLK_EN_REG                      0x308
65 #define DSAF_SUB_SC_NT_CLK_DIS_REG                     0x30C
66 #define DSAF_SUB_SC_XGE_CLK_EN_REG                     0x310
67 #define DSAF_SUB_SC_XGE_CLK_DIS_REG                    0x314
68 #define DSAF_SUB_SC_GE_CLK_EN_REG                      0x318
69 #define DSAF_SUB_SC_GE_CLK_DIS_REG                     0x31C
70 #define DSAF_SUB_SC_PPE_CLK_EN_REG                     0x320
71 #define DSAF_SUB_SC_PPE_CLK_DIS_REG                    0x324
72 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG             0x350
73 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG            0x354
74 #define DSAF_SUB_SC_XBAR_RESET_REQ_REG                 0xA00
75 #define DSAF_SUB_SC_XBAR_RESET_DREQ_REG                0xA04
76 #define DSAF_SUB_SC_NT_RESET_REQ_REG                   0xA08
77 #define DSAF_SUB_SC_NT_RESET_DREQ_REG                  0xA0C
78 #define DSAF_SUB_SC_XGE_RESET_REQ_REG                  0xA10
79 #define DSAF_SUB_SC_XGE_RESET_DREQ_REG                 0xA14
80 #define DSAF_SUB_SC_GE_RESET_REQ0_REG                  0xA18
81 #define DSAF_SUB_SC_GE_RESET_DREQ0_REG                 0xA1C
82 #define DSAF_SUB_SC_GE_RESET_REQ1_REG                  0xA20
83 #define DSAF_SUB_SC_GE_RESET_DREQ1_REG                 0xA24
84 #define DSAF_SUB_SC_PPE_RESET_REQ_REG                  0xA48
85 #define DSAF_SUB_SC_PPE_RESET_DREQ_REG                 0xA4C
86 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG          0xA88
87 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG         0xA8C
88 #define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG         0x2060
89 #define DSAF_SUB_SC_TCAM_MBIST_EN_REG                  0x2300
90 #define DSAF_SUB_SC_DSAF_CLK_ST_REG                    0x5300
91 #define DSAF_SUB_SC_NT_CLK_ST_REG                      0x5304
92 #define DSAF_SUB_SC_XGE_CLK_ST_REG                     0x5308
93 #define DSAF_SUB_SC_GE_CLK_ST_REG                      0x530C
94 #define DSAF_SUB_SC_PPE_CLK_ST_REG                     0x5310
95 #define DSAF_SUB_SC_ROCEE_CLK_ST_REG                   0x5314
96 #define DSAF_SUB_SC_CPU_CLK_ST_REG                     0x5318
97 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG             0x5328
98 #define DSAF_SUB_SC_XBAR_RESET_ST_REG                  0x5A00
99 #define DSAF_SUB_SC_NT_RESET_ST_REG                    0x5A04
100 #define DSAF_SUB_SC_XGE_RESET_ST_REG                   0x5A08
101 #define DSAF_SUB_SC_GE_RESET_ST0_REG                   0x5A0C
102 #define DSAF_SUB_SC_GE_RESET_ST1_REG                   0x5A10
103 #define DSAF_SUB_SC_PPE_RESET_ST_REG                   0x5A24
104 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG           0x5A44
105 
106 /*serdes offset**/
107 #define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG
108 #define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG
109 #define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL
110 #define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL
111 #define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL
112 #define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL
113 #define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL
114 #define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL
115 #define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL
116 #define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL
117 
118 #define HILINK_RESET_TIMOUT 10000
119 
120 #define DSAF_SRAM_INIT_OVER_0_REG	0x0
121 #define DSAF_CFG_0_REG			0x4
122 #define DSAF_ECC_ERR_INVERT_0_REG	0x8
123 #define DSAF_ABNORMAL_TIMEOUT_0_REG	0x1C
124 #define DSAF_FSM_TIMEOUT_0_REG		0x20
125 #define DSAF_DSA_REG_CNT_CLR_CE_REG	0x2C
126 #define DSAF_DSA_SBM_INF_FIFO_THRD_REG	0x30
127 #define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG	0x34
128 #define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG	0x38
129 #define DSAF_PFC_EN_0_REG		0x50
130 #define DSAF_PFC_UNIT_CNT_0_REG		0x70
131 #define DSAF_XGE_INT_MSK_0_REG		0x100
132 #define DSAF_PPE_INT_MSK_0_REG		0x120
133 #define DSAF_ROCEE_INT_MSK_0_REG	0x140
134 #define DSAF_XGE_INT_SRC_0_REG		0x160
135 #define DSAF_PPE_INT_SRC_0_REG		0x180
136 #define DSAF_ROCEE_INT_SRC_0_REG	0x1A0
137 #define DSAF_XGE_INT_STS_0_REG		0x1C0
138 #define DSAF_PPE_INT_STS_0_REG		0x1E0
139 #define DSAF_ROCEE_INT_STS_0_REG	0x200
140 #define DSAF_PPE_QID_CFG_0_REG		0x300
141 #define DSAF_SW_PORT_TYPE_0_REG		0x320
142 #define DSAF_STP_PORT_TYPE_0_REG	0x340
143 #define DSAF_MIX_DEF_QID_0_REG		0x360
144 #define DSAF_PORT_DEF_VLAN_0_REG	0x380
145 #define DSAF_VM_DEF_VLAN_0_REG		0x400
146 
147 #define DSAF_INODE_CUT_THROUGH_CFG_0_REG	0x1000
148 #define DSAF_INODE_ECC_INVERT_EN_0_REG		0x1008
149 #define DSAF_INODE_ECC_ERR_ADDR_0_REG		0x100C
150 #define DSAF_INODE_IN_PORT_NUM_0_REG		0x1018
151 #define DSAF_INODE_PRI_TC_CFG_0_REG		0x101C
152 #define DSAF_INODE_BP_STATUS_0_REG		0x1020
153 #define DSAF_INODE_PAD_DISCARD_NUM_0_REG	0x1028
154 #define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG	0x102C
155 #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG	0x1030
156 #define DSAF_INODE_SBM_PID_NUM_0_REG		0x1038
157 #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG	0x103C
158 #define DSAF_INODE_SBM_RELS_NUM_0_REG		0x104C
159 #define DSAF_INODE_SBM_DROP_NUM_0_REG		0x1050
160 #define DSAF_INODE_CRC_FALSE_NUM_0_REG		0x1054
161 #define DSAF_INODE_BP_DISCARD_NUM_0_REG		0x1058
162 #define DSAF_INODE_RSLT_DISCARD_NUM_0_REG	0x105C
163 #define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG	0x1060
164 #define DSAF_INODE_VOQ_OVER_NUM_0_REG		0x1068
165 #define DSAF_INODE_BD_SAVE_STATUS_0_REG		0x1900
166 #define DSAF_INODE_BD_ORDER_STATUS_0_REG	0x1950
167 #define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG	0x1A00
168 #define DSAF_INODE_IN_DATA_STP_DISC_0_REG	0x1A50
169 #define DSAF_INODE_GE_FC_EN_0_REG		0x1B00
170 #define DSAF_INODE_VC0_IN_PKT_NUM_0_REG		0x1B50
171 #define DSAF_INODE_VC1_IN_PKT_NUM_0_REG		0x1C00
172 
173 #define DSAF_SBM_CFG_REG_0_REG			0x2000
174 #define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG		0x2004
175 #define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG		0x2304
176 #define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG	0x2604
177 #define DSAF_SBM_BP_CFG_1_REG_0_REG		0x2008
178 #define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG		0x200C
179 #define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG		0x230C
180 #define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG	0x260C
181 #define DSAF_SBM_FREE_CNT_0_0_REG		0x2010
182 #define DSAF_SBM_FREE_CNT_1_0_REG		0x2014
183 #define DSAF_SBM_BP_CNT_0_0_REG			0x2018
184 #define DSAF_SBM_BP_CNT_1_0_REG			0x201C
185 #define DSAF_SBM_BP_CNT_2_0_REG			0x2020
186 #define DSAF_SBM_BP_CNT_3_0_REG			0x2024
187 #define DSAF_SBM_INER_ST_0_REG			0x2028
188 #define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG	0x202C
189 #define DSAF_SBM_LNK_INPORT_CNT_0_REG		0x2030
190 #define DSAF_SBM_LNK_DROP_CNT_0_REG		0x2034
191 #define DSAF_SBM_INF_OUTPORT_CNT_0_REG		0x2038
192 #define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG	0x203C
193 #define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG	0x2040
194 #define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG	0x2044
195 #define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG	0x2048
196 #define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG	0x204C
197 #define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG	0x2050
198 #define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG	0x2054
199 #define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG	0x2058
200 #define DSAF_SBM_LNK_REQ_CNT_0_REG		0x205C
201 #define DSAF_SBM_LNK_RELS_CNT_0_REG		0x2060
202 #define DSAF_SBM_BP_CFG_3_REG_0_REG		0x2068
203 #define DSAF_SBM_BP_CFG_4_REG_0_REG		0x206C
204 
205 #define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG	0x3000
206 #define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG	0x3004
207 #define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG	0x3008
208 #define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG	0x300C
209 #define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG	0x3010
210 #define DSAF_XOD_ETS_TOKEN_CFG_0_REG		0x3014
211 #define DSAF_XOD_PFS_CFG_0_0_REG		0x3018
212 #define DSAF_XOD_PFS_CFG_1_0_REG		0x301C
213 #define DSAF_XOD_PFS_CFG_2_0_REG		0x3020
214 #define DSAF_XOD_GNT_L_0_REG			0x3024
215 #define DSAF_XOD_GNT_H_0_REG			0x3028
216 #define DSAF_XOD_CONNECT_STATE_0_REG		0x302C
217 #define DSAF_XOD_RCVPKT_CNT_0_REG		0x3030
218 #define DSAF_XOD_RCVTC0_CNT_0_REG		0x3034
219 #define DSAF_XOD_RCVTC1_CNT_0_REG		0x3038
220 #define DSAF_XOD_RCVTC2_CNT_0_REG		0x303C
221 #define DSAF_XOD_RCVTC3_CNT_0_REG		0x3040
222 #define DSAF_XOD_RCVVC0_CNT_0_REG		0x3044
223 #define DSAF_XOD_RCVVC1_CNT_0_REG		0x3048
224 #define DSAF_XOD_XGE_RCVIN0_CNT_0_REG		0x304C
225 #define DSAF_XOD_XGE_RCVIN1_CNT_0_REG		0x3050
226 #define DSAF_XOD_XGE_RCVIN2_CNT_0_REG		0x3054
227 #define DSAF_XOD_XGE_RCVIN3_CNT_0_REG		0x3058
228 #define DSAF_XOD_XGE_RCVIN4_CNT_0_REG		0x305C
229 #define DSAF_XOD_XGE_RCVIN5_CNT_0_REG		0x3060
230 #define DSAF_XOD_XGE_RCVIN6_CNT_0_REG		0x3064
231 #define DSAF_XOD_XGE_RCVIN7_CNT_0_REG		0x3068
232 #define DSAF_XOD_PPE_RCVIN0_CNT_0_REG		0x306C
233 #define DSAF_XOD_PPE_RCVIN1_CNT_0_REG		0x3070
234 #define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG		0x3074
235 #define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG		0x3078
236 #define DSAF_XOD_FIFO_STATUS_0_REG		0x307C
237 
238 #define DSAF_VOQ_ECC_INVERT_EN_0_REG		0x4004
239 #define DSAF_VOQ_SRAM_PKT_NUM_0_REG		0x4008
240 #define DSAF_VOQ_IN_PKT_NUM_0_REG		0x400C
241 #define DSAF_VOQ_OUT_PKT_NUM_0_REG		0x4010
242 #define DSAF_VOQ_ECC_ERR_ADDR_0_REG		0x4014
243 #define DSAF_VOQ_BP_STATUS_0_REG		0x4018
244 #define DSAF_VOQ_SPUP_IDLE_0_REG		0x401C
245 #define DSAF_VOQ_XGE_XOD_REQ_0_0_REG		0x4024
246 #define DSAF_VOQ_XGE_XOD_REQ_1_0_REG		0x4028
247 #define DSAF_VOQ_PPE_XOD_REQ_0_REG		0x402C
248 #define DSAF_VOQ_ROCEE_XOD_REQ_0_REG		0x4030
249 #define DSAF_VOQ_BP_ALL_THRD_0_REG		0x4034
250 
251 #define DSAF_TBL_CTRL_0_REG			0x5000
252 #define DSAF_TBL_INT_MSK_0_REG			0x5004
253 #define DSAF_TBL_INT_SRC_0_REG			0x5008
254 #define DSAF_TBL_INT_STS_0_REG			0x5100
255 #define DSAF_TBL_TCAM_ADDR_0_REG		0x500C
256 #define DSAF_TBL_LINE_ADDR_0_REG		0x5010
257 #define DSAF_TBL_TCAM_HIGH_0_REG		0x5014
258 #define DSAF_TBL_TCAM_LOW_0_REG			0x5018
259 #define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG		0x501C
260 #define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG		0x5020
261 #define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG		0x5024
262 #define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG		0x5028
263 #define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG		0x502C
264 #define DSAF_TBL_TCAM_UCAST_CFG_0_REG		0x5030
265 #define DSAF_TBL_LIN_CFG_0_REG			0x5034
266 #define DSAF_TBL_TCAM_RDATA_HIGH_0_REG		0x5038
267 #define DSAF_TBL_TCAM_RDATA_LOW_0_REG		0x503C
268 #define DSAF_TBL_TCAM_RAM_RDATA4_0_REG		0x5040
269 #define DSAF_TBL_TCAM_RAM_RDATA3_0_REG		0x5044
270 #define DSAF_TBL_TCAM_RAM_RDATA2_0_REG		0x5048
271 #define DSAF_TBL_TCAM_RAM_RDATA1_0_REG		0x504C
272 #define DSAF_TBL_TCAM_RAM_RDATA0_0_REG		0x5050
273 #define DSAF_TBL_LIN_RDATA_0_REG		0x5054
274 #define DSAF_TBL_DA0_MIS_INFO1_0_REG		0x5058
275 #define DSAF_TBL_DA0_MIS_INFO0_0_REG		0x505C
276 #define DSAF_TBL_SA_MIS_INFO2_0_REG		0x5104
277 #define DSAF_TBL_SA_MIS_INFO1_0_REG		0x5098
278 #define DSAF_TBL_SA_MIS_INFO0_0_REG		0x509C
279 #define DSAF_TBL_PUL_0_REG			0x50A0
280 #define DSAF_TBL_OLD_RSLT_0_REG			0x50A4
281 #define DSAF_TBL_OLD_SCAN_VAL_0_REG		0x50A8
282 #define DSAF_TBL_DFX_CTRL_0_REG			0x50AC
283 #define DSAF_TBL_DFX_STAT_0_REG			0x50B0
284 #define DSAF_TBL_DFX_STAT_2_0_REG		0x5108
285 #define DSAF_TBL_LKUP_NUM_I_0_REG		0x50C0
286 #define DSAF_TBL_LKUP_NUM_O_0_REG		0x50E0
287 #define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG	0x510C
288 
289 #define DSAF_INODE_FIFO_WL_0_REG		0x6000
290 #define DSAF_ONODE_FIFO_WL_0_REG		0x6020
291 #define DSAF_XGE_GE_WORK_MODE_0_REG		0x6040
292 #define DSAF_XGE_APP_RX_LINK_UP_0_REG		0x6080
293 #define DSAF_NETPORT_CTRL_SIG_0_REG		0x60A0
294 #define DSAF_XGE_CTRL_SIG_CFG_0_REG		0x60C0
295 
296 #define PPE_COM_CFG_QID_MODE_REG		0x0
297 #define PPE_COM_INTEN_REG			0x110
298 #define PPE_COM_RINT_REG			0x114
299 #define PPE_COM_INTSTS_REG			0x118
300 #define PPE_COM_COMMON_CNT_CLR_CE_REG		0x1120
301 #define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG	0x300
302 #define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG	0x600
303 #define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG	0x900
304 #define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG	0xC00
305 #define PPE_COM_COMMON_CNT_CLR_CE_REG		0x1120
306 
307 #define PPE_CFG_TX_FIFO_THRSLD_REG		0x0
308 #define PPE_CFG_RX_FIFO_THRSLD_REG		0x4
309 #define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG	0x8
310 #define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG	0xC
311 #define PPE_CFG_PAUSE_IDLE_CNT_REG		0x10
312 #define PPE_CFG_BUS_CTRL_REG			0x40
313 #define PPE_CFG_TNL_TO_BE_RST_REG		0x48
314 #define PPE_CURR_TNL_CAN_RST_REG		0x4C
315 #define PPE_CFG_XGE_MODE_REG			0x80
316 #define PPE_CFG_MAX_FRAME_LEN_REG		0x84
317 #define PPE_CFG_RX_PKT_MODE_REG			0x88
318 #define PPE_CFG_RX_VLAN_TAG_REG			0x8C
319 #define PPE_CFG_TAG_GEN_REG			0x90
320 #define PPE_CFG_PARSE_TAG_REG			0x94
321 #define PPE_CFG_PRO_CHECK_EN_REG		0x98
322 #define PPE_INTEN_REG				0x100
323 #define PPE_RINT_REG				0x104
324 #define PPE_INTSTS_REG				0x108
325 #define PPE_CFG_RX_PKT_INT_REG			0x140
326 #define PPE_CFG_HEAT_DECT_TIME0_REG		0x144
327 #define PPE_CFG_HEAT_DECT_TIME1_REG		0x148
328 #define PPE_HIS_RX_SW_PKT_CNT_REG		0x200
329 #define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG		0x204
330 #define PPE_HIS_RX_PKT_NO_BUF_CNT_REG		0x208
331 #define PPE_HIS_TX_BD_CNT_REG			0x20C
332 #define PPE_HIS_TX_PKT_CNT_REG			0x210
333 #define PPE_HIS_TX_PKT_OK_CNT_REG		0x214
334 #define PPE_HIS_TX_PKT_EPT_CNT_REG		0x218
335 #define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG		0x21C
336 #define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG		0x220
337 #define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG		0x224
338 #define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG		0x228
339 #define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG		0x22C
340 #define PPE_TNL_0_5_CNT_CLR_CE_REG		0x300
341 #define PPE_CFG_AXI_DBG_REG			0x304
342 #define PPE_HIS_PRO_ERR_REG			0x308
343 #define PPE_HIS_TNL_FIFO_ERR_REG		0x30C
344 #define PPE_CURR_CFF_DATA_NUM_REG		0x310
345 #define PPE_CURR_RX_ST_REG			0x314
346 #define PPE_CURR_TX_ST_REG			0x318
347 #define PPE_CURR_RX_FIFO0_REG			0x31C
348 #define PPE_CURR_RX_FIFO1_REG			0x320
349 #define PPE_CURR_TX_FIFO0_REG			0x324
350 #define PPE_CURR_TX_FIFO1_REG			0x328
351 #define PPE_ECO0_REG				0x32C
352 #define PPE_ECO1_REG				0x330
353 #define PPE_ECO2_REG				0x334
354 
355 #define RCB_COM_CFG_ENDIAN_REG			0x0
356 #define RCB_COM_CFG_SYS_FSH_REG			0xC
357 #define RCB_COM_CFG_INIT_FLAG_REG		0x10
358 #define RCB_COM_CFG_PKT_REG			0x30
359 #define RCB_COM_CFG_RINVLD_REG			0x34
360 #define RCB_COM_CFG_FNA_REG			0x38
361 #define RCB_COM_CFG_FA_REG			0x3C
362 #define RCB_COM_CFG_PKT_TC_BP_REG		0x40
363 #define RCB_COM_CFG_PPE_TNL_CLKEN_REG		0x44
364 
365 #define RCB_COM_INTMSK_TX_PKT_REG		0x3A0
366 #define RCB_COM_RINT_TX_PKT_REG			0x3A8
367 #define RCB_COM_INTMASK_ECC_ERR_REG		0x400
368 #define RCB_COM_INTSTS_ECC_ERR_REG		0x408
369 #define RCB_COM_EBD_SRAM_ERR_REG		0x410
370 #define RCB_COM_RXRING_ERR_REG			0x41C
371 #define RCB_COM_TXRING_ERR_REG			0x420
372 #define RCB_COM_TX_FBD_ERR_REG			0x424
373 #define RCB_SRAM_ECC_CHK_EN_REG			0x428
374 #define RCB_SRAM_ECC_CHK0_REG			0x42C
375 #define RCB_SRAM_ECC_CHK1_REG			0x430
376 #define RCB_SRAM_ECC_CHK2_REG			0x434
377 #define RCB_SRAM_ECC_CHK3_REG			0x438
378 #define RCB_SRAM_ECC_CHK4_REG			0x43c
379 #define RCB_SRAM_ECC_CHK5_REG			0x440
380 #define RCB_ECC_ERR_ADDR0_REG			0x450
381 #define RCB_ECC_ERR_ADDR3_REG			0x45C
382 #define RCB_ECC_ERR_ADDR4_REG			0x460
383 #define RCB_ECC_ERR_ADDR5_REG			0x464
384 
385 #define RCB_COM_SF_CFG_INTMASK_RING		0x480
386 #define RCB_COM_SF_CFG_RING_STS			0x484
387 #define RCB_COM_SF_CFG_RING			0x488
388 #define RCB_COM_SF_CFG_INTMASK_BD		0x48C
389 #define RCB_COM_SF_CFG_BD_RINT_STS		0x470
390 #define RCB_COM_RCB_RD_BD_BUSY			0x490
391 #define RCB_COM_RCB_FBD_CRT_EN			0x494
392 #define RCB_COM_AXI_WR_ERR_INTMASK		0x498
393 #define RCB_COM_AXI_ERR_STS			0x49C
394 #define RCB_COM_CHK_TX_FBD_NUM_REG		0x4a0
395 
396 #define RCB_CFG_BD_NUM_REG			0x9000
397 #define RCB_CFG_PKTLINE_REG			0x9050
398 
399 #define RCB_CFG_OVERTIME_REG			0x9300
400 #define RCB_CFG_PKTLINE_INT_NUM_REG		0x9304
401 #define RCB_CFG_OVERTIME_INT_NUM_REG		0x9308
402 
403 #define RCB_RING_RX_RING_BASEADDR_L_REG		0x00000
404 #define RCB_RING_RX_RING_BASEADDR_H_REG		0x00004
405 #define RCB_RING_RX_RING_BD_NUM_REG		0x00008
406 #define RCB_RING_RX_RING_BD_LEN_REG		0x0000C
407 #define RCB_RING_RX_RING_PKTLINE_REG		0x00010
408 #define RCB_RING_RX_RING_TAIL_REG		0x00018
409 #define RCB_RING_RX_RING_HEAD_REG		0x0001C
410 #define RCB_RING_RX_RING_FBDNUM_REG		0x00020
411 #define RCB_RING_RX_RING_PKTNUM_RECORD_REG	0x0002C
412 
413 #define RCB_RING_TX_RING_BASEADDR_L_REG		0x00040
414 #define RCB_RING_TX_RING_BASEADDR_H_REG		0x00044
415 #define RCB_RING_TX_RING_BD_NUM_REG		0x00048
416 #define RCB_RING_TX_RING_BD_LEN_REG		0x0004C
417 #define RCB_RING_TX_RING_PKTLINE_REG		0x00050
418 #define RCB_RING_TX_RING_TAIL_REG		0x00058
419 #define RCB_RING_TX_RING_HEAD_REG		0x0005C
420 #define RCB_RING_TX_RING_FBDNUM_REG		0x00060
421 #define RCB_RING_TX_RING_OFFSET_REG		0x00064
422 #define RCB_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C
423 
424 #define RCB_RING_PREFETCH_EN_REG		0x0007C
425 #define RCB_RING_CFG_VF_NUM_REG			0x00080
426 #define RCB_RING_ASID_REG			0x0008C
427 #define RCB_RING_RX_VM_REG			0x00090
428 #define RCB_RING_T0_BE_RST			0x00094
429 #define RCB_RING_COULD_BE_RST			0x00098
430 #define RCB_RING_WRR_WEIGHT_REG			0x0009c
431 
432 #define RCB_RING_INTMSK_RXWL_REG		0x000A0
433 #define RCB_RING_INTSTS_RX_RING_REG		0x000A4
434 #define RCB_RING_INTMSK_TXWL_REG		0x000AC
435 #define RCB_RING_INTSTS_TX_RING_REG		0x000B0
436 #define RCB_RING_INTMSK_RX_OVERTIME_REG		0x000B8
437 #define RCB_RING_INTSTS_RX_OVERTIME_REG		0x000BC
438 #define RCB_RING_INTMSK_TX_OVERTIME_REG		0x000C4
439 #define RCB_RING_INTSTS_TX_OVERTIME_REG		0x000C8
440 
441 #define GMAC_DUPLEX_TYPE_REG			0x0008UL
442 #define GMAC_FD_FC_TYPE_REG			0x000CUL
443 #define GMAC_FC_TX_TIMER_REG			0x001CUL
444 #define GMAC_FD_FC_ADDR_LOW_REG			0x0020UL
445 #define GMAC_FD_FC_ADDR_HIGH_REG		0x0024UL
446 #define GMAC_IPG_TX_TIMER_REG			0x0030UL
447 #define GMAC_PAUSE_THR_REG			0x0038UL
448 #define GMAC_MAX_FRM_SIZE_REG			0x003CUL
449 #define GMAC_PORT_MODE_REG			0x0040UL
450 #define GMAC_PORT_EN_REG			0x0044UL
451 #define GMAC_PAUSE_EN_REG			0x0048UL
452 #define GMAC_SHORT_RUNTS_THR_REG		0x0050UL
453 #define GMAC_AN_NEG_STATE_REG			0x0058UL
454 #define GMAC_TX_LOCAL_PAGE_REG			0x005CUL
455 #define GMAC_TRANSMIT_CONTROL_REG		0x0060UL
456 #define GMAC_REC_FILT_CONTROL_REG		0x0064UL
457 #define GMAC_PTP_CONFIG_REG			0x0074UL
458 
459 #define GMAC_RX_OCTETS_TOTAL_OK_REG		0x0080UL
460 #define GMAC_RX_OCTETS_BAD_REG			0x0084UL
461 #define GMAC_RX_UC_PKTS_REG			0x0088UL
462 #define GMAC_RX_MC_PKTS_REG			0x008CUL
463 #define GMAC_RX_BC_PKTS_REG			0x0090UL
464 #define GMAC_RX_PKTS_64OCTETS_REG		0x0094UL
465 #define GMAC_RX_PKTS_65TO127OCTETS_REG		0x0098UL
466 #define GMAC_RX_PKTS_128TO255OCTETS_REG		0x009CUL
467 #define GMAC_RX_PKTS_255TO511OCTETS_REG		0x00A0UL
468 #define GMAC_RX_PKTS_512TO1023OCTETS_REG	0x00A4UL
469 #define GMAC_RX_PKTS_1024TO1518OCTETS_REG	0x00A8UL
470 #define GMAC_RX_PKTS_1519TOMAXOCTETS_REG	0x00ACUL
471 #define GMAC_RX_FCS_ERRORS_REG			0x00B0UL
472 #define GMAC_RX_TAGGED_REG			0x00B4UL
473 #define GMAC_RX_DATA_ERR_REG			0x00B8UL
474 #define GMAC_RX_ALIGN_ERRORS_REG		0x00BCUL
475 #define GMAC_RX_LONG_ERRORS_REG			0x00C0UL
476 #define GMAC_RX_JABBER_ERRORS_REG		0x00C4UL
477 #define GMAC_RX_PAUSE_MACCTRL_FRAM_REG		0x00C8UL
478 #define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG	0x00CCUL
479 #define GMAC_RX_VERY_LONG_ERR_CNT_REG		0x00D0UL
480 #define GMAC_RX_RUNT_ERR_CNT_REG		0x00D4UL
481 #define GMAC_RX_SHORT_ERR_CNT_REG		0x00D8UL
482 #define GMAC_RX_FILT_PKT_CNT_REG		0x00E8UL
483 #define GMAC_RX_OCTETS_TOTAL_FILT_REG		0x00ECUL
484 #define GMAC_OCTETS_TRANSMITTED_OK_REG		0x0100UL
485 #define GMAC_OCTETS_TRANSMITTED_BAD_REG		0x0104UL
486 #define GMAC_TX_UC_PKTS_REG			0x0108UL
487 #define GMAC_TX_MC_PKTS_REG			0x010CUL
488 #define GMAC_TX_BC_PKTS_REG			0x0110UL
489 #define GMAC_TX_PKTS_64OCTETS_REG		0x0114UL
490 #define GMAC_TX_PKTS_65TO127OCTETS_REG		0x0118UL
491 #define GMAC_TX_PKTS_128TO255OCTETS_REG		0x011CUL
492 #define GMAC_TX_PKTS_255TO511OCTETS_REG		0x0120UL
493 #define GMAC_TX_PKTS_512TO1023OCTETS_REG	0x0124UL
494 #define GMAC_TX_PKTS_1024TO1518OCTETS_REG	0x0128UL
495 #define GMAC_TX_PKTS_1519TOMAXOCTETS_REG	0x012CUL
496 #define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG	0x014CUL
497 #define GMAC_TX_UNDERRUN_REG			0x0150UL
498 #define GMAC_TX_TAGGED_REG			0x0154UL
499 #define GMAC_TX_CRC_ERROR_REG			0x0158UL
500 #define GMAC_TX_PAUSE_FRAMES_REG		0x015CUL
501 #define GAMC_RX_MAX_FRAME			0x0170UL
502 #define GMAC_LINE_LOOP_BACK_REG			0x01A8UL
503 #define GMAC_CF_CRC_STRIP_REG			0x01B0UL
504 #define GMAC_MODE_CHANGE_EN_REG			0x01B4UL
505 #define GMAC_SIXTEEN_BIT_CNTR_REG		0x01CCUL
506 #define GMAC_LD_LINK_COUNTER_REG		0x01D0UL
507 #define GMAC_LOOP_REG				0x01DCUL
508 #define GMAC_RECV_CONTROL_REG			0x01E0UL
509 #define GMAC_VLAN_CODE_REG			0x01E8UL
510 #define GMAC_RX_OVERRUN_CNT_REG			0x01ECUL
511 #define GMAC_RX_LENGTHFIELD_ERR_CNT_REG		0x01F4UL
512 #define GMAC_RX_FAIL_COMMA_CNT_REG		0x01F8UL
513 #define GMAC_STATION_ADDR_LOW_0_REG		0x0200UL
514 #define GMAC_STATION_ADDR_HIGH_0_REG		0x0204UL
515 #define GMAC_STATION_ADDR_LOW_1_REG		0x0208UL
516 #define GMAC_STATION_ADDR_HIGH_1_REG		0x020CUL
517 #define GMAC_STATION_ADDR_LOW_2_REG		0x0210UL
518 #define GMAC_STATION_ADDR_HIGH_2_REG		0x0214UL
519 #define GMAC_STATION_ADDR_LOW_3_REG		0x0218UL
520 #define GMAC_STATION_ADDR_HIGH_3_REG		0x021CUL
521 #define GMAC_STATION_ADDR_LOW_4_REG		0x0220UL
522 #define GMAC_STATION_ADDR_HIGH_4_REG		0x0224UL
523 #define GMAC_STATION_ADDR_LOW_5_REG		0x0228UL
524 #define GMAC_STATION_ADDR_HIGH_5_REG		0x022CUL
525 #define GMAC_STATION_ADDR_LOW_MSK_0_REG		0x0230UL
526 #define GMAC_STATION_ADDR_HIGH_MSK_0_REG	0x0234UL
527 #define GMAC_STATION_ADDR_LOW_MSK_1_REG		0x0238UL
528 #define GMAC_STATION_ADDR_HIGH_MSK_1_REG	0x023CUL
529 #define GMAC_MAC_SKIP_LEN_REG			0x0240UL
530 #define GMAC_TX_LOOP_PKT_PRI_REG		0x0378UL
531 
532 #define XGMAC_INT_STATUS_REG			0x0
533 #define XGMAC_INT_ENABLE_REG			0x4
534 #define XGMAC_INT_SET_REG			0x8
535 #define XGMAC_IERR_U_INFO_REG			0xC
536 #define XGMAC_OVF_INFO_REG			0x10
537 #define XGMAC_OVF_CNT_REG			0x14
538 #define XGMAC_PORT_MODE_REG			0x40
539 #define XGMAC_CLK_ENABLE_REG			0x44
540 #define XGMAC_RESET_REG				0x48
541 #define XGMAC_LINK_CONTROL_REG			0x50
542 #define XGMAC_LINK_STATUS_REG			0x54
543 #define XGMAC_SPARE_REG				0xC0
544 #define XGMAC_SPARE_CNT_REG			0xC4
545 
546 #define XGMAC_MAC_ENABLE_REG			0x100
547 #define XGMAC_MAC_CONTROL_REG			0x104
548 #define XGMAC_MAC_IPG_REG			0x120
549 #define XGMAC_MAC_MSG_CRC_EN_REG		0x124
550 #define XGMAC_MAC_MSG_IMG_REG			0x128
551 #define XGMAC_MAC_MSG_FC_CFG_REG		0x12C
552 #define XGMAC_MAC_MSG_TC_CFG_REG		0x130
553 #define XGMAC_MAC_PAD_SIZE_REG			0x134
554 #define XGMAC_MAC_MIN_PKT_SIZE_REG		0x138
555 #define XGMAC_MAC_MAX_PKT_SIZE_REG		0x13C
556 #define XGMAC_MAC_PAUSE_CTRL_REG		0x160
557 #define XGMAC_MAC_PAUSE_TIME_REG		0x164
558 #define XGMAC_MAC_PAUSE_GAP_REG			0x168
559 #define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG		0x16C
560 #define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG		0x170
561 #define XGMAC_MAC_PAUSE_PEER_MAC_H_REG		0x174
562 #define XGMAC_MAC_PAUSE_PEER_MAC_L_REG		0x178
563 #define XGMAC_MAC_PFC_PRI_EN_REG		0x17C
564 #define XGMAC_MAC_1588_CTRL_REG			0x180
565 #define XGMAC_MAC_1588_TX_PORT_DLY_REG		0x184
566 #define XGMAC_MAC_1588_RX_PORT_DLY_REG		0x188
567 #define XGMAC_MAC_1588_ASYM_DLY_REG		0x18C
568 #define XGMAC_MAC_1588_ADJUST_CFG_REG		0x190
569 #define XGMAC_MAC_Y1731_ETH_TYPE_REG		0x194
570 #define XGMAC_MAC_MIB_CONTROL_REG		0x198
571 #define XGMAC_MAC_WAN_RATE_ADJUST_REG		0x19C
572 #define XGMAC_MAC_TX_ERR_MARK_REG		0x1A0
573 #define XGMAC_MAC_TX_LF_RF_CONTROL_REG		0x1A4
574 #define XGMAC_MAC_RX_LF_RF_STATUS_REG		0x1A8
575 #define XGMAC_MAC_TX_RUNT_PKT_CNT_REG		0x1C0
576 #define XGMAC_MAC_RX_RUNT_PKT_CNT_REG		0x1C4
577 #define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG	0x1C8
578 #define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG	0x1CC
579 #define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG	0x1D0
580 #define XGMAC_MAC_RX_ERR_MSG_CNT_REG		0x1D4
581 #define XGMAC_MAC_RX_ERR_EFD_CNT_REG		0x1D8
582 #define XGMAC_MAC_ERR_INFO_REG			0x1DC
583 #define XGMAC_MAC_DBG_INFO_REG			0x1E0
584 
585 #define XGMAC_PCS_BASER_SYNC_THD_REG		0x330
586 #define XGMAC_PCS_STATUS1_REG			0x404
587 #define XGMAC_PCS_BASER_STATUS1_REG		0x410
588 #define XGMAC_PCS_BASER_STATUS2_REG		0x414
589 #define XGMAC_PCS_BASER_SEEDA_0_REG		0x420
590 #define XGMAC_PCS_BASER_SEEDA_1_REG		0x424
591 #define XGMAC_PCS_BASER_SEEDB_0_REG		0x428
592 #define XGMAC_PCS_BASER_SEEDB_1_REG		0x42C
593 #define XGMAC_PCS_BASER_TEST_CONTROL_REG	0x430
594 #define XGMAC_PCS_BASER_TEST_ERR_CNT_REG	0x434
595 #define XGMAC_PCS_DBG_INFO_REG			0x4C0
596 #define XGMAC_PCS_DBG_INFO1_REG			0x4C4
597 #define XGMAC_PCS_DBG_INFO2_REG			0x4C8
598 #define XGMAC_PCS_DBG_INFO3_REG			0x4CC
599 
600 #define XGMAC_PMA_ENABLE_REG			0x700
601 #define XGMAC_PMA_CONTROL_REG			0x704
602 #define XGMAC_PMA_SIGNAL_STATUS_REG		0x708
603 #define XGMAC_PMA_DBG_INFO_REG			0x70C
604 #define XGMAC_PMA_FEC_ABILITY_REG		0x740
605 #define XGMAC_PMA_FEC_CONTROL_REG		0x744
606 #define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG	0x750
607 #define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG	0x760
608 
609 #define XGMAC_TX_PKTS_FRAGMENT			0x0000
610 #define XGMAC_TX_PKTS_UNDERSIZE			0x0008
611 #define XGMAC_TX_PKTS_UNDERMIN			0x0010
612 #define XGMAC_TX_PKTS_64OCTETS			0x0018
613 #define XGMAC_TX_PKTS_65TO127OCTETS		0x0020
614 #define XGMAC_TX_PKTS_128TO255OCTETS		0x0028
615 #define XGMAC_TX_PKTS_256TO511OCTETS		0x0030
616 #define XGMAC_TX_PKTS_512TO1023OCTETS		0x0038
617 #define XGMAC_TX_PKTS_1024TO1518OCTETS		0x0040
618 #define XGMAC_TX_PKTS_1519TOMAXOCTETS		0x0048
619 #define XGMAC_TX_PKTS_1519TOMAXOCTETSOK		0x0050
620 #define XGMAC_TX_PKTS_OVERSIZE			0x0058
621 #define XGMAC_TX_PKTS_JABBER			0x0060
622 #define XGMAC_TX_GOODPKTS			0x0068
623 #define XGMAC_TX_GOODOCTETS			0x0070
624 #define XGMAC_TX_TOTAL_PKTS			0x0078
625 #define XGMAC_TX_TOTALOCTETS			0x0080
626 #define XGMAC_TX_UNICASTPKTS			0x0088
627 #define XGMAC_TX_MULTICASTPKTS			0x0090
628 #define XGMAC_TX_BROADCASTPKTS			0x0098
629 #define XGMAC_TX_PRI0PAUSEPKTS			0x00a0
630 #define XGMAC_TX_PRI1PAUSEPKTS			0x00a8
631 #define XGMAC_TX_PRI2PAUSEPKTS			0x00b0
632 #define XGMAC_TX_PRI3PAUSEPKTS			0x00b8
633 #define XGMAC_TX_PRI4PAUSEPKTS			0x00c0
634 #define XGMAC_TX_PRI5PAUSEPKTS			0x00c8
635 #define XGMAC_TX_PRI6PAUSEPKTS			0x00d0
636 #define XGMAC_TX_PRI7PAUSEPKTS			0x00d8
637 #define XGMAC_TX_MACCTRLPKTS			0x00e0
638 #define XGMAC_TX_1731PKTS			0x00e8
639 #define XGMAC_TX_1588PKTS			0x00f0
640 #define XGMAC_RX_FROMAPPGOODPKTS		0x00f8
641 #define XGMAC_RX_FROMAPPBADPKTS			0x0100
642 #define XGMAC_TX_ERRALLPKTS			0x0108
643 
644 #define XGMAC_RX_PKTS_FRAGMENT			0x0110
645 #define XGMAC_RX_PKTSUNDERSIZE			0x0118
646 #define XGMAC_RX_PKTS_UNDERMIN			0x0120
647 #define XGMAC_RX_PKTS_64OCTETS			0x0128
648 #define XGMAC_RX_PKTS_65TO127OCTETS		0x0130
649 #define XGMAC_RX_PKTS_128TO255OCTETS		0x0138
650 #define XGMAC_RX_PKTS_256TO511OCTETS		0x0140
651 #define XGMAC_RX_PKTS_512TO1023OCTETS		0x0148
652 #define XGMAC_RX_PKTS_1024TO1518OCTETS		0x0150
653 #define XGMAC_RX_PKTS_1519TOMAXOCTETS		0x0158
654 #define XGMAC_RX_PKTS_1519TOMAXOCTETSOK		0x0160
655 #define XGMAC_RX_PKTS_OVERSIZE			0x0168
656 #define XGMAC_RX_PKTS_JABBER			0x0170
657 #define XGMAC_RX_GOODPKTS			0x0178
658 #define XGMAC_RX_GOODOCTETS			0x0180
659 #define XGMAC_RX_TOTAL_PKTS			0x0188
660 #define XGMAC_RX_TOTALOCTETS			0x0190
661 #define XGMAC_RX_UNICASTPKTS			0x0198
662 #define XGMAC_RX_MULTICASTPKTS			0x01a0
663 #define XGMAC_RX_BROADCASTPKTS			0x01a8
664 #define XGMAC_RX_PRI0PAUSEPKTS			0x01b0
665 #define XGMAC_RX_PRI1PAUSEPKTS			0x01b8
666 #define XGMAC_RX_PRI2PAUSEPKTS			0x01c0
667 #define XGMAC_RX_PRI3PAUSEPKTS			0x01c8
668 #define XGMAC_RX_PRI4PAUSEPKTS			0x01d0
669 #define XGMAC_RX_PRI5PAUSEPKTS			0x01d8
670 #define XGMAC_RX_PRI6PAUSEPKTS			0x01e0
671 #define XGMAC_RX_PRI7PAUSEPKTS			0x01e8
672 #define XGMAC_RX_MACCTRLPKTS			0x01f0
673 #define XGMAC_TX_SENDAPPGOODPKTS		0x01f8
674 #define XGMAC_TX_SENDAPPBADPKTS			0x0200
675 #define XGMAC_RX_1731PKTS			0x0208
676 #define XGMAC_RX_SYMBOLERRPKTS			0x0210
677 #define XGMAC_RX_FCSERRPKTS			0x0218
678 
679 #define XGMAC_TRX_CORE_SRST_M			0x2080
680 
681 #define DSAF_CFG_EN_S 0
682 #define DSAF_CFG_TC_MODE_S 1
683 #define DSAF_CFG_CRC_EN_S 2
684 #define DSAF_CFG_SBM_INIT_S 3
685 #define DSAF_CFG_MIX_MODE_S 4
686 #define DSAF_CFG_STP_MODE_S 5
687 #define DSAF_CFG_LOCA_ADDR_EN_S 6
688 
689 #define DSAF_CNT_CLR_CE_S 0
690 #define DSAF_SNAP_EN_S 1
691 
692 #define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE 41
693 #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 410
694 #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 103
695 
696 #define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1)
697 #define DSAF_PFC_UNINT_CNT_S 0
698 
699 #define DSAF_PPE_QID_CFG_M 0xFF
700 #define DSAF_PPE_QID_CFG_S 0
701 
702 #define DSAF_SW_PORT_TYPE_M 3
703 #define DSAF_SW_PORT_TYPE_S 0
704 
705 #define DSAF_STP_PORT_TYPE_M 7
706 #define DSAF_STP_PORT_TYPE_S 0
707 
708 #define DSAF_INODE_IN_PORT_NUM_M 7
709 #define DSAF_INODE_IN_PORT_NUM_S 0
710 
711 #define HNS_DSAF_I4TC_CFG 0x18688688
712 #define HNS_DSAF_I8TC_CFG 0x18FAC688
713 
714 #define DSAF_SBM_CFG_SHCUT_EN_S 0
715 #define DSAF_SBM_CFG_EN_S 1
716 #define DSAF_SBM_CFG_MIB_EN_S 2
717 #define DSAF_SBM_CFG_ECC_INVERT_EN_S 3
718 
719 #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S 0
720 #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)
721 #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S 10
722 #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)
723 #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S 20
724 #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 11) - 1) << 20)
725 
726 #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S 0
727 #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)
728 #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S 10
729 #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)
730 
731 #define DSAF_SBM_CFG2_SET_BUF_NUM_S 0
732 #define DSAF_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 10) - 1) << 0)
733 #define DSAF_SBM_CFG2_RESET_BUF_NUM_S 10
734 #define DSAF_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 10) - 1) << 10)
735 
736 #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0
737 #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 0)
738 #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 10
739 #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 10)
740 
741 #define DSAF_TBL_TCAM_ADDR_S 0
742 #define DSAF_TBL_TCAM_ADDR_M ((1ULL << 9) - 1)
743 
744 #define DSAF_TBL_LINE_ADDR_S 0
745 #define DSAF_TBL_LINE_ADDR_M ((1ULL << 15) - 1)
746 
747 #define DSAF_TBL_MCAST_CFG4_VM128_112_S 0
748 #define DSAF_TBL_MCAST_CFG4_VM128_112_M (((1ULL << 7) - 1) << 0)
749 #define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S 7
750 #define DSAF_TBL_MCAST_CFG4_OLD_EN_S 8
751 
752 #define DSAF_TBL_MCAST_CFG0_XGE5_0_S 0
753 #define DSAF_TBL_MCAST_CFG0_XGE5_0_M (((1ULL << 6) - 1) << 0)
754 #define DSAF_TBL_MCAST_CFG0_VM25_0_S 6
755 #define DSAF_TBL_MCAST_CFG0_VM25_0_M (((1ULL << 26) - 1) << 6)
756 
757 #define DSAF_TBL_UCAST_CFG1_OUT_PORT_S 0
758 #define DSAF_TBL_UCAST_CFG1_OUT_PORT_M (((1ULL << 8) - 1) << 0)
759 #define DSAF_TBL_UCAST_CFG1_DVC_S 8
760 #define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S 9
761 #define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S 10
762 #define DSAF_TBL_UCAST_CFG1_OLD_EN_S 11
763 
764 #define DSAF_TBL_LINE_CFG_OUT_PORT_S 0
765 #define DSAF_TBL_LINE_CFG_OUT_PORT_M (((1ULL << 8) - 1) << 0)
766 #define DSAF_TBL_LINE_CFG_DVC_S 8
767 #define DSAF_TBL_LINE_CFG_MAC_DISCARD_S 9
768 
769 #define DSAF_TBL_PUL_OLD_RSLT_RE_S 0
770 #define DSAF_TBL_PUL_MCAST_VLD_S 1
771 #define DSAF_TBL_PUL_TCAM_DATA_VLD_S 2
772 #define DSAF_TBL_PUL_UCAST_VLD_S 3
773 #define DSAF_TBL_PUL_LINE_VLD_S 4
774 #define DSAF_TBL_PUL_TCAM_LOAD_S 5
775 #define DSAF_TBL_PUL_LINE_LOAD_S 6
776 
777 #define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S 0
778 #define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S 1
779 #define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S 2
780 #define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S 3
781 #define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S 4
782 
783 #define DSAF_VOQ_BP_ALL_DOWNTHRD_S 0
784 #define DSAF_VOQ_BP_ALL_DOWNTHRD_M (((1ULL << 10) - 1) << 0)
785 #define DSAF_VOQ_BP_ALL_UPTHRD_S 10
786 #define DSAF_VOQ_BP_ALL_UPTHRD_M (((1ULL << 10) - 1) << 10)
787 
788 #define DSAF_XGE_GE_WORK_MODE_S 0
789 #define DSAF_XGE_GE_LOOPBACK_S 1
790 
791 #define DSAF_FC_XGE_TX_PAUSE_S 0
792 #define DSAF_REGS_XGE_CNT_CAR_S 1
793 
794 #define PPE_CFG_QID_MODE_DEF_QID_S	0
795 #define PPE_CFG_QID_MODE_DEF_QID_M	(0xff << PPE_CFG_QID_MODE_DEF_QID_S)
796 
797 #define PPE_CFG_QID_MODE_CF_QID_MODE_S	8
798 #define PPE_CFG_QID_MODE_CF_QID_MODE_M	(0x7 << PPE_CFG_QID_MODE_CF_QID_MODE_S)
799 
800 #define PPE_CNT_CLR_CE_B	0
801 #define PPE_CNT_CLR_SNAP_EN_B	1
802 
803 #define PPE_COMMON_CNT_CLR_CE_B	0
804 #define PPE_COMMON_CNT_CLR_SNAP_EN_B	1
805 
806 #define GMAC_DUPLEX_TYPE_B 0
807 
808 #define GMAC_FC_TX_TIMER_S 0
809 #define GMAC_FC_TX_TIMER_M 0xffff
810 
811 #define GMAC_MAX_FRM_SIZE_S 0
812 #define GMAC_MAX_FRM_SIZE_M 0xffff
813 
814 #define GMAC_PORT_MODE_S	0
815 #define GMAC_PORT_MODE_M	0xf
816 
817 #define GMAC_RGMII_1000M_DELAY_B	4
818 #define GMAC_MII_TX_EDGE_SEL_B		5
819 #define GMAC_FIFO_ERR_AUTO_RST_B	6
820 #define GMAC_DBG_CLK_LOS_MSK_B		7
821 
822 #define GMAC_PORT_RX_EN_B	1
823 #define GMAC_PORT_TX_EN_B	2
824 
825 #define GMAC_PAUSE_EN_RX_FDFC_B 0
826 #define GMAC_PAUSE_EN_TX_FDFC_B 1
827 #define GMAC_PAUSE_EN_TX_HDFC_B 2
828 
829 #define GMAC_SHORT_RUNTS_THR_S 0
830 #define GMAC_SHORT_RUNTS_THR_M 0x1f
831 
832 #define GMAC_AN_NEG_STAT_FD_B		5
833 #define GMAC_AN_NEG_STAT_HD_B		6
834 #define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B	12
835 #define GMAC_AN_NEG_STAT_RF2_B		13
836 
837 #define GMAC_AN_NEG_STAT_NP_LNK_OK_B	15
838 #define GMAC_AN_NEG_STAT_RX_SYNC_OK_B	20
839 #define GMAC_AN_NEG_STAT_AN_DONE_B	21
840 
841 #define GMAC_AN_NEG_STAT_PS_S		7
842 #define GMAC_AN_NEG_STAT_PS_M		(0x3 << GMAC_AN_NEG_STAT_PS_S)
843 
844 #define GMAC_AN_NEG_STAT_SPEED_S	10
845 #define GMAC_AN_NEG_STAT_SPEED_M	(0x3 << GMAC_AN_NEG_STAT_SPEED_S)
846 
847 #define GMAC_TX_AN_EN_B		5
848 #define GMAC_TX_CRC_ADD_B	6
849 #define GMAC_TX_PAD_EN_B	7
850 
851 #define GMAC_LINE_LOOPBACK_B	0
852 
853 #define GMAC_LP_REG_CF_EXT_DRV_LP_B	1
854 #define GMAC_LP_REG_CF2MI_LP_EN_B	2
855 
856 #define GMAC_MODE_CHANGE_EB_B	0
857 
858 #define GMAC_RECV_CTRL_STRIP_PAD_EN_B	3
859 #define GMAC_RECV_CTRL_RUNT_PKT_EN_B	4
860 
861 #define GMAC_TX_LOOP_PKT_HIG_PRI_B	0
862 #define GMAC_TX_LOOP_PKT_EN_B		1
863 
864 #define XGMAC_PORT_MODE_TX_S		0x0
865 #define XGMAC_PORT_MODE_TX_M		(0x3 << XGMAC_PORT_MODE_TX_S)
866 #define XGMAC_PORT_MODE_TX_40G_B	0x3
867 #define XGMAC_PORT_MODE_RX_S		0x4
868 #define XGMAC_PORT_MODE_RX_M		(0x3 << XGMAC_PORT_MODE_RX_S)
869 #define XGMAC_PORT_MODE_RX_40G_B	0x7
870 
871 #define XGMAC_ENABLE_TX_B		0
872 #define XGMAC_ENABLE_RX_B		1
873 
874 #define XGMAC_CTL_TX_FCS_B		0
875 #define XGMAC_CTL_TX_PAD_B		1
876 #define XGMAC_CTL_TX_PREAMBLE_TRANS_B	3
877 #define XGMAC_CTL_TX_UNDER_MIN_ERR_B	4
878 #define XGMAC_CTL_TX_TRUNCATE_B		5
879 #define XGMAC_CTL_TX_1588_B		8
880 #define XGMAC_CTL_TX_1731_B		9
881 #define XGMAC_CTL_TX_PFC_B		10
882 #define XGMAC_CTL_RX_FCS_B		16
883 #define XGMAC_CTL_RX_FCS_STRIP_B	17
884 #define XGMAC_CTL_RX_PREAMBLE_TRANS_B	19
885 #define XGMAC_CTL_RX_UNDER_MIN_ERR_B	20
886 #define XGMAC_CTL_RX_TRUNCATE_B		21
887 #define XGMAC_CTL_RX_1588_B		24
888 #define XGMAC_CTL_RX_1731_B		25
889 #define XGMAC_CTL_RX_PFC_B		26
890 
891 #define XGMAC_PMA_FEC_CTL_TX_B		0
892 #define XGMAC_PMA_FEC_CTL_RX_B		1
893 #define XGMAC_PMA_FEC_CTL_ERR_EN	2
894 #define XGMAC_PMA_FEC_CTL_ERR_SH	3
895 
896 #define XGMAC_PAUSE_CTL_TX_B		0
897 #define XGMAC_PAUSE_CTL_RX_B		1
898 #define XGMAC_PAUSE_CTL_RSP_MODE_B	2
899 #define XGMAC_PAUSE_CTL_TX_XOFF_B	3
900 
901 static inline void dsaf_write_reg(void *base, u32 reg, u32 value)
902 {
903 	u8 __iomem *reg_addr = ACCESS_ONCE(base);
904 
905 	writel(value, reg_addr + reg);
906 }
907 
908 #define dsaf_write_dev(a, reg, value) \
909 	dsaf_write_reg((a)->io_base, (reg), (value))
910 
911 static inline u32 dsaf_read_reg(u8 *base, u32 reg)
912 {
913 	u8 __iomem *reg_addr = ACCESS_ONCE(base);
914 
915 	return readl(reg_addr + reg);
916 }
917 
918 #define dsaf_read_dev(a, reg) \
919 	dsaf_read_reg((a)->io_base, (reg))
920 
921 #define dsaf_set_field(origin, mask, shift, val) \
922 	do { \
923 		(origin) &= (~(mask)); \
924 		(origin) |= (((val) << (shift)) & (mask)); \
925 	} while (0)
926 
927 #define dsaf_set_bit(origin, shift, val) \
928 	dsaf_set_field((origin), (1ull << (shift)), (shift), (val))
929 
930 static inline void dsaf_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
931 				      u32 val)
932 {
933 	u32 origin = dsaf_read_reg(base, reg);
934 
935 	dsaf_set_field(origin, mask, shift, val);
936 	dsaf_write_reg(base, reg, origin);
937 }
938 
939 #define dsaf_set_dev_field(dev, reg, mask, shift, val) \
940 	dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val))
941 
942 #define dsaf_set_dev_bit(dev, reg, bit, val) \
943 	dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val))
944 
945 #define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
946 
947 #define dsaf_get_bit(origin, shift) \
948 	dsaf_get_field((origin), (1ull << (shift)), (shift))
949 
950 static inline u32 dsaf_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
951 {
952 	u32 origin;
953 
954 	origin = dsaf_read_reg(base, reg);
955 	return dsaf_get_field(origin, mask, shift);
956 }
957 
958 #define dsaf_get_dev_field(dev, reg, mask, shift) \
959 	dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift))
960 
961 #define dsaf_get_dev_bit(dev, reg, bit) \
962 	dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit))
963 
964 #define dsaf_write_b(addr, data)\
965 	writeb((data), (__iomem unsigned char *)(addr))
966 #define dsaf_read_b(addr)\
967 	readb((__iomem unsigned char *)(addr))
968 
969 #define hns_mac_reg_read64(drv, offset) \
970 	readq((__iomem void *)(((u8 *)(drv)->io_base + 0xc00 + (offset))))
971 
972 #endif	/* _DSAF_REG_H */
973