1 /*
2  * Copyright (c) 2014-2015 Hisilicon Limited.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #ifndef _DSAF_REG_H_
11 #define _DSAF_REG_H_
12 
13 #include <linux/regmap.h>
14 #define HNS_DEBUG_RING_IRQ_IDX		0
15 #define HNS_SERVICE_RING_IRQ_IDX	59
16 #define HNSV2_SERVICE_RING_IRQ_IDX	25
17 
18 #define DSAF_MAX_PORT_NUM	6
19 #define DSAF_MAX_VM_NUM		128
20 
21 #define DSAF_COMM_DEV_NUM	1
22 #define DSAF_PPE_INODE_BASE	6
23 #define DSAF_DEBUG_NW_NUM	2
24 #define DSAF_SERVICE_NW_NUM	6
25 #define DSAF_COMM_CHN		DSAF_SERVICE_NW_NUM
26 #define DSAF_GE_NUM		((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM))
27 #define DSAF_XGE_NUM		DSAF_SERVICE_NW_NUM
28 #define DSAF_PORT_TYPE_NUM 3
29 #define DSAF_NODE_NUM		18
30 #define DSAF_XOD_BIG_NUM	DSAF_NODE_NUM
31 #define DSAF_SBM_NUM		DSAF_NODE_NUM
32 #define DSAFV2_SBM_NUM		8
33 #define DSAFV2_SBM_XGE_CHN    6
34 #define DSAFV2_SBM_PPE_CHN    1
35 #define DASFV2_ROCEE_CRD_NUM  1
36 
37 #define DSAF_VOQ_NUM		DSAF_NODE_NUM
38 #define DSAF_INODE_NUM		DSAF_NODE_NUM
39 #define DSAF_XOD_NUM		8
40 #define DSAF_TBL_NUM		8
41 #define DSAF_SW_PORT_NUM	8
42 #define DSAF_TOTAL_QUEUE_NUM	129
43 
44 /* reserved a tcam entry for each port to support promisc by fuzzy match */
45 #define DSAFV2_MAC_FUZZY_TCAM_NUM    DSAF_MAX_PORT_NUM
46 
47 #define DSAF_TCAM_SUM		512
48 #define DSAF_LINE_SUM		(2048 * 14)
49 
50 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG			0x100
51 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG		0x180
52 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG		0x184
53 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG		0x188
54 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG		0x18C
55 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG		0x190
56 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG		0x194
57 #define DSAF_SUB_SC_DSAF_CLK_EN_REG			0x300
58 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG			0x304
59 #define DSAF_SUB_SC_NT_CLK_EN_REG			0x308
60 #define DSAF_SUB_SC_NT_CLK_DIS_REG			0x30C
61 #define DSAF_SUB_SC_XGE_CLK_EN_REG			0x310
62 #define DSAF_SUB_SC_XGE_CLK_DIS_REG			0x314
63 #define DSAF_SUB_SC_GE_CLK_EN_REG			0x318
64 #define DSAF_SUB_SC_GE_CLK_DIS_REG			0x31C
65 #define DSAF_SUB_SC_PPE_CLK_EN_REG			0x320
66 #define DSAF_SUB_SC_PPE_CLK_DIS_REG			0x324
67 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG		0x350
68 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG		0x354
69 #define DSAF_SUB_SC_XBAR_RESET_REQ_REG			0xA00
70 #define DSAF_SUB_SC_XBAR_RESET_DREQ_REG			0xA04
71 #define DSAF_SUB_SC_NT_RESET_REQ_REG			0xA08
72 #define DSAF_SUB_SC_NT_RESET_DREQ_REG			0xA0C
73 #define DSAF_SUB_SC_XGE_RESET_REQ_REG			0xA10
74 #define DSAF_SUB_SC_XGE_RESET_DREQ_REG			0xA14
75 #define DSAF_SUB_SC_GE_RESET_REQ0_REG			0xA18
76 #define DSAF_SUB_SC_GE_RESET_DREQ0_REG			0xA1C
77 #define DSAF_SUB_SC_GE_RESET_REQ1_REG			0xA20
78 #define DSAF_SUB_SC_GE_RESET_DREQ1_REG			0xA24
79 #define DSAF_SUB_SC_PPE_RESET_REQ_REG			0xA48
80 #define DSAF_SUB_SC_PPE_RESET_DREQ_REG			0xA4C
81 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG		0xA88
82 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG		0xA8C
83 #define DSAF_SUB_SC_DSAF_RESET_REQ_REG			0xAA8
84 #define DSAF_SUB_SC_DSAF_RESET_DREQ_REG			0xAAC
85 #define DSAF_SUB_SC_ROCEE_RESET_REQ_REG			0xA50
86 #define DSAF_SUB_SC_ROCEE_RESET_DREQ_REG		0xA54
87 #define DSAF_SUB_SC_ROCEE_CLK_DIS_REG			0x32C
88 #define DSAF_SUB_SC_ROCEE_CLK_EN_REG			0x328
89 #define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG		0x2060
90 #define DSAF_SUB_SC_TCAM_MBIST_EN_REG			0x2300
91 #define DSAF_SUB_SC_DSAF_CLK_ST_REG			0x5300
92 #define DSAF_SUB_SC_NT_CLK_ST_REG			0x5304
93 #define DSAF_SUB_SC_XGE_CLK_ST_REG			0x5308
94 #define DSAF_SUB_SC_GE_CLK_ST_REG			0x530C
95 #define DSAF_SUB_SC_PPE_CLK_ST_REG			0x5310
96 #define DSAF_SUB_SC_ROCEE_CLK_ST_REG			0x5314
97 #define DSAF_SUB_SC_CPU_CLK_ST_REG			0x5318
98 #define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG		0x5328
99 #define DSAF_SUB_SC_XBAR_RESET_ST_REG			0x5A00
100 #define DSAF_SUB_SC_NT_RESET_ST_REG			0x5A04
101 #define DSAF_SUB_SC_XGE_RESET_ST_REG			0x5A08
102 #define DSAF_SUB_SC_GE_RESET_ST0_REG			0x5A0C
103 #define DSAF_SUB_SC_GE_RESET_ST1_REG			0x5A10
104 #define DSAF_SUB_SC_PPE_RESET_ST_REG			0x5A24
105 #define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG		0x5A44
106 
107 /*serdes offset**/
108 #define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG
109 #define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG
110 #define HNS_MAC_HILINK3V2_REG DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG
111 #define HNS_MAC_HILINK4V2_REG DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG
112 #define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL
113 #define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL
114 #define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL
115 #define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL
116 #define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL
117 #define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL
118 #define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL
119 #define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL
120 
121 #define HILINK_RESET_TIMOUT 10000
122 
123 #define DSAF_SRAM_INIT_OVER_0_REG	0x0
124 #define DSAF_CFG_0_REG			0x4
125 #define DSAF_ECC_ERR_INVERT_0_REG	0x8
126 #define DSAF_ABNORMAL_TIMEOUT_0_REG	0x1C
127 #define DSAF_FSM_TIMEOUT_0_REG		0x20
128 #define DSAF_DSA_REG_CNT_CLR_CE_REG	0x2C
129 #define DSAF_DSA_SBM_INF_FIFO_THRD_REG	0x30
130 #define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG	0x34
131 #define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG	0x38
132 #define DSAF_PFC_EN_0_REG		0x50
133 #define DSAF_PFC_UNIT_CNT_0_REG		0x70
134 #define DSAF_XGE_INT_MSK_0_REG		0x100
135 #define DSAF_PPE_INT_MSK_0_REG		0x120
136 #define DSAF_ROCEE_INT_MSK_0_REG	0x140
137 #define DSAF_XGE_INT_SRC_0_REG		0x160
138 #define DSAF_PPE_INT_SRC_0_REG		0x180
139 #define DSAF_ROCEE_INT_SRC_0_REG	0x1A0
140 #define DSAF_XGE_INT_STS_0_REG		0x1C0
141 #define DSAF_PPE_INT_STS_0_REG		0x1E0
142 #define DSAF_ROCEE_INT_STS_0_REG	0x200
143 #define DSAFV2_SERDES_LBK_0_REG         0x220
144 #define DSAF_PAUSE_CFG_REG		0x240
145 #define DSAF_ROCE_PORT_MAP_REG		0x2A0
146 #define DSAF_ROCE_SL_MAP_REG		0x2A4
147 #define DSAF_PPE_QID_CFG_0_REG		0x300
148 #define DSAF_SW_PORT_TYPE_0_REG		0x320
149 #define DSAF_STP_PORT_TYPE_0_REG	0x340
150 #define DSAF_MIX_DEF_QID_0_REG		0x360
151 #define DSAF_PORT_DEF_VLAN_0_REG	0x380
152 #define DSAF_VM_DEF_VLAN_0_REG		0x400
153 
154 #define DSAF_INODE_CUT_THROUGH_CFG_0_REG	0x1000
155 #define DSAF_INODE_ECC_INVERT_EN_0_REG		0x1008
156 #define DSAF_INODE_ECC_ERR_ADDR_0_REG		0x100C
157 #define DSAF_INODE_IN_PORT_NUM_0_REG		0x1018
158 #define DSAF_INODE_PRI_TC_CFG_0_REG		0x101C
159 #define DSAF_INODE_BP_STATUS_0_REG		0x1020
160 #define DSAF_INODE_PAD_DISCARD_NUM_0_REG	0x1028
161 #define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG	0x102C
162 #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG	0x1030
163 #define DSAF_INODE_SBM_PID_NUM_0_REG		0x1038
164 #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG	0x103C
165 #define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG	0x1024
166 #define DSAF_INODE_SBM_RELS_NUM_0_REG		0x104C
167 #define DSAF_INODE_SBM_DROP_NUM_0_REG		0x1050
168 #define DSAF_INODE_CRC_FALSE_NUM_0_REG		0x1054
169 #define DSAF_INODE_BP_DISCARD_NUM_0_REG		0x1058
170 #define DSAF_INODE_RSLT_DISCARD_NUM_0_REG	0x105C
171 #define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG	0x1060
172 #define DSAF_INODE_VOQ_OVER_NUM_0_REG		0x1068
173 #define DSAF_INODE_BD_SAVE_STATUS_0_REG		0x1900
174 #define DSAF_INODE_BD_ORDER_STATUS_0_REG	0x1950
175 #define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG	0x1A00
176 #define DSAF_INODE_IN_DATA_STP_DISC_0_REG	0x1A50
177 #define DSAF_INODE_GE_FC_EN_0_REG		0x1B00
178 #define DSAF_INODE_VC0_IN_PKT_NUM_0_REG		0x1B50
179 #define DSAF_INODE_VC1_IN_PKT_NUM_0_REG		0x1C00
180 #define DSAF_INODE_IN_PRIO_PAUSE_BASE_REG	0x1C00
181 #define DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET	0x100
182 #define DSAF_INODE_IN_PRIO_PAUSE_OFFSET		0x50
183 
184 #define DSAF_SBM_CFG_REG_0_REG			0x2000
185 #define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG		0x2004
186 #define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG		0x2304
187 #define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG	0x2604
188 #define DSAF_SBM_BP_CFG_1_REG_0_REG		0x2008
189 #define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG		0x200C
190 #define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG		0x230C
191 #define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG	0x260C
192 #define DSAF_SBM_ROCEE_CFG_REG_REG		0x2380
193 #define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG	0x238C
194 #define DSAF_SBM_FREE_CNT_0_0_REG		0x2010
195 #define DSAF_SBM_FREE_CNT_1_0_REG		0x2014
196 #define DSAF_SBM_BP_CNT_0_0_REG			0x2018
197 #define DSAF_SBM_BP_CNT_1_0_REG			0x201C
198 #define DSAF_SBM_BP_CNT_2_0_REG			0x2020
199 #define DSAF_SBM_BP_CNT_3_0_REG			0x2024
200 #define DSAF_SBM_INER_ST_0_REG			0x2028
201 #define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG	0x202C
202 #define DSAF_SBM_LNK_INPORT_CNT_0_REG		0x2030
203 #define DSAF_SBM_LNK_DROP_CNT_0_REG		0x2034
204 #define DSAF_SBM_INF_OUTPORT_CNT_0_REG		0x2038
205 #define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG	0x203C
206 #define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG	0x2040
207 #define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG	0x2044
208 #define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG	0x2048
209 #define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG	0x204C
210 #define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG	0x2050
211 #define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG	0x2054
212 #define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG	0x2058
213 #define DSAF_SBM_LNK_REQ_CNT_0_REG		0x205C
214 #define DSAF_SBM_LNK_RELS_CNT_0_REG		0x2060
215 #define DSAF_SBM_BP_CFG_3_REG_0_REG		0x2068
216 #define DSAF_SBM_BP_CFG_4_REG_0_REG		0x206C
217 
218 #define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG	0x3000
219 #define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG	0x3004
220 #define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG	0x3008
221 #define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG	0x300C
222 #define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG	0x3010
223 #define DSAF_XOD_ETS_TOKEN_CFG_0_REG		0x3014
224 #define DSAF_XOD_PFS_CFG_0_0_REG		0x3018
225 #define DSAF_XOD_PFS_CFG_1_0_REG		0x301C
226 #define DSAF_XOD_PFS_CFG_2_0_REG		0x3020
227 #define DSAF_XOD_GNT_L_0_REG			0x3024
228 #define DSAF_XOD_GNT_H_0_REG			0x3028
229 #define DSAF_XOD_CONNECT_STATE_0_REG		0x302C
230 #define DSAF_XOD_RCVPKT_CNT_0_REG		0x3030
231 #define DSAF_XOD_RCVTC0_CNT_0_REG		0x3034
232 #define DSAF_XOD_RCVTC1_CNT_0_REG		0x3038
233 #define DSAF_XOD_RCVTC2_CNT_0_REG		0x303C
234 #define DSAF_XOD_RCVTC3_CNT_0_REG		0x3040
235 #define DSAF_XOD_RCVVC0_CNT_0_REG		0x3044
236 #define DSAF_XOD_RCVVC1_CNT_0_REG		0x3048
237 #define DSAF_XOD_XGE_RCVIN0_CNT_0_REG		0x304C
238 #define DSAF_XOD_XGE_RCVIN1_CNT_0_REG		0x3050
239 #define DSAF_XOD_XGE_RCVIN2_CNT_0_REG		0x3054
240 #define DSAF_XOD_XGE_RCVIN3_CNT_0_REG		0x3058
241 #define DSAF_XOD_XGE_RCVIN4_CNT_0_REG		0x305C
242 #define DSAF_XOD_XGE_RCVIN5_CNT_0_REG		0x3060
243 #define DSAF_XOD_XGE_RCVIN6_CNT_0_REG		0x3064
244 #define DSAF_XOD_XGE_RCVIN7_CNT_0_REG		0x3068
245 #define DSAF_XOD_PPE_RCVIN0_CNT_0_REG		0x306C
246 #define DSAF_XOD_PPE_RCVIN1_CNT_0_REG		0x3070
247 #define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG		0x3074
248 #define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG		0x3078
249 #define DSAF_XOD_FIFO_STATUS_0_REG		0x307C
250 #define DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG	0x3A00
251 #define DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET	0x4
252 
253 #define DSAF_VOQ_ECC_INVERT_EN_0_REG		0x4004
254 #define DSAF_VOQ_SRAM_PKT_NUM_0_REG		0x4008
255 #define DSAF_VOQ_IN_PKT_NUM_0_REG		0x400C
256 #define DSAF_VOQ_OUT_PKT_NUM_0_REG		0x4010
257 #define DSAF_VOQ_ECC_ERR_ADDR_0_REG		0x4014
258 #define DSAF_VOQ_BP_STATUS_0_REG		0x4018
259 #define DSAF_VOQ_SPUP_IDLE_0_REG		0x401C
260 #define DSAF_VOQ_XGE_XOD_REQ_0_0_REG		0x4024
261 #define DSAF_VOQ_XGE_XOD_REQ_1_0_REG		0x4028
262 #define DSAF_VOQ_PPE_XOD_REQ_0_REG		0x402C
263 #define DSAF_VOQ_ROCEE_XOD_REQ_0_REG		0x4030
264 #define DSAF_VOQ_BP_ALL_THRD_0_REG		0x4034
265 
266 #define DSAF_TBL_CTRL_0_REG			0x5000
267 #define DSAF_TBL_INT_MSK_0_REG			0x5004
268 #define DSAF_TBL_INT_SRC_0_REG			0x5008
269 #define DSAF_TBL_INT_STS_0_REG			0x5100
270 #define DSAF_TBL_TCAM_ADDR_0_REG		0x500C
271 #define DSAF_TBL_LINE_ADDR_0_REG		0x5010
272 #define DSAF_TBL_TCAM_HIGH_0_REG		0x5014
273 #define DSAF_TBL_TCAM_LOW_0_REG			0x5018
274 #define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG		0x501C
275 #define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG		0x5020
276 #define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG		0x5024
277 #define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG		0x5028
278 #define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG		0x502C
279 #define DSAF_TBL_TCAM_UCAST_CFG_0_REG		0x5030
280 #define DSAF_TBL_LIN_CFG_0_REG			0x5034
281 #define DSAF_TBL_TCAM_RDATA_HIGH_0_REG		0x5038
282 #define DSAF_TBL_TCAM_RDATA_LOW_0_REG		0x503C
283 #define DSAF_TBL_TCAM_RAM_RDATA4_0_REG		0x5040
284 #define DSAF_TBL_TCAM_RAM_RDATA3_0_REG		0x5044
285 #define DSAF_TBL_TCAM_RAM_RDATA2_0_REG		0x5048
286 #define DSAF_TBL_TCAM_RAM_RDATA1_0_REG		0x504C
287 #define DSAF_TBL_TCAM_RAM_RDATA0_0_REG		0x5050
288 #define DSAF_TBL_LIN_RDATA_0_REG		0x5054
289 #define DSAF_TBL_DA0_MIS_INFO1_0_REG		0x5058
290 #define DSAF_TBL_DA0_MIS_INFO0_0_REG		0x505C
291 #define DSAF_TBL_SA_MIS_INFO2_0_REG		0x5104
292 #define DSAF_TBL_SA_MIS_INFO1_0_REG		0x5098
293 #define DSAF_TBL_SA_MIS_INFO0_0_REG		0x509C
294 #define DSAF_TBL_PUL_0_REG			0x50A0
295 #define DSAF_TBL_OLD_RSLT_0_REG			0x50A4
296 #define DSAF_TBL_OLD_SCAN_VAL_0_REG		0x50A8
297 #define DSAF_TBL_DFX_CTRL_0_REG			0x50AC
298 #define DSAF_TBL_DFX_STAT_0_REG			0x50B0
299 #define DSAF_TBL_DFX_STAT_2_0_REG		0x5108
300 #define DSAF_TBL_LKUP_NUM_I_0_REG		0x50C0
301 #define DSAF_TBL_LKUP_NUM_O_0_REG		0x50E0
302 #define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG	0x510C
303 #define DSAF_TBL_TCAM_MATCH_CFG_H_REG		0x5130
304 #define DSAF_TBL_TCAM_MATCH_CFG_L_REG		0x5134
305 
306 #define DSAF_INODE_FIFO_WL_0_REG		0x6000
307 #define DSAF_ONODE_FIFO_WL_0_REG		0x6020
308 #define DSAF_XGE_GE_WORK_MODE_0_REG		0x6040
309 #define DSAF_XGE_APP_RX_LINK_UP_0_REG		0x6080
310 #define DSAF_NETPORT_CTRL_SIG_0_REG		0x60A0
311 #define DSAF_XGE_CTRL_SIG_CFG_0_REG		0x60C0
312 
313 #define PPE_COM_CFG_QID_MODE_REG		0x0
314 #define PPE_COM_INTEN_REG			0x110
315 #define PPE_COM_RINT_REG			0x114
316 #define PPE_COM_INTSTS_REG			0x118
317 #define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG	0x300
318 #define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG	0x600
319 #define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG	0x900
320 #define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG	0xC00
321 #define PPE_COM_COMMON_CNT_CLR_CE_REG		0x1120
322 
323 #define PPE_CFG_TX_FIFO_THRSLD_REG		0x0
324 #define PPE_CFG_RX_FIFO_THRSLD_REG		0x4
325 #define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG	0x8
326 #define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG	0xC
327 #define PPE_CFG_PAUSE_IDLE_CNT_REG		0x10
328 #define PPE_CFG_BUS_CTRL_REG			0x40
329 #define PPE_CFG_TNL_TO_BE_RST_REG		0x48
330 #define PPE_CURR_TNL_CAN_RST_REG		0x4C
331 #define PPE_CFG_XGE_MODE_REG			0x80
332 #define PPE_CFG_MAX_FRAME_LEN_REG		0x84
333 #define PPE_CFG_RX_PKT_MODE_REG			0x88
334 #define PPE_CFG_RX_VLAN_TAG_REG			0x8C
335 #define PPE_CFG_TAG_GEN_REG			0x90
336 #define PPE_CFG_PARSE_TAG_REG			0x94
337 #define PPE_CFG_PRO_CHECK_EN_REG		0x98
338 #define PPEV2_CFG_TSO_EN_REG			0xA0
339 #define PPEV2_VLAN_STRIP_EN_REG			0xAC
340 #define PPE_INTEN_REG				0x100
341 #define PPE_RINT_REG				0x104
342 #define PPE_INTSTS_REG				0x108
343 #define PPE_CFG_RX_PKT_INT_REG			0x140
344 #define PPE_CFG_HEAT_DECT_TIME0_REG		0x144
345 #define PPE_CFG_HEAT_DECT_TIME1_REG		0x148
346 #define PPE_HIS_RX_SW_PKT_CNT_REG		0x200
347 #define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG		0x204
348 #define PPE_HIS_RX_PKT_NO_BUF_CNT_REG		0x208
349 #define PPE_HIS_TX_BD_CNT_REG			0x20C
350 #define PPE_HIS_TX_PKT_CNT_REG			0x210
351 #define PPE_HIS_TX_PKT_OK_CNT_REG		0x214
352 #define PPE_HIS_TX_PKT_EPT_CNT_REG		0x218
353 #define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG		0x21C
354 #define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG		0x220
355 #define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG		0x224
356 #define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG		0x228
357 #define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG		0x22C
358 #define PPE_TNL_0_5_CNT_CLR_CE_REG		0x300
359 #define PPE_CFG_AXI_DBG_REG			0x304
360 #define PPE_HIS_PRO_ERR_REG			0x308
361 #define PPE_HIS_TNL_FIFO_ERR_REG		0x30C
362 #define PPE_CURR_CFF_DATA_NUM_REG		0x310
363 #define PPE_CURR_RX_ST_REG			0x314
364 #define PPE_CURR_TX_ST_REG			0x318
365 #define PPE_CURR_RX_FIFO0_REG			0x31C
366 #define PPE_CURR_RX_FIFO1_REG			0x320
367 #define PPE_CURR_TX_FIFO0_REG			0x324
368 #define PPE_CURR_TX_FIFO1_REG			0x328
369 #define PPE_ECO0_REG				0x32C
370 #define PPE_ECO1_REG				0x330
371 #define PPE_ECO2_REG				0x334
372 #define PPEV2_INDRECTION_TBL_REG		0x800
373 #define PPEV2_RSS_KEY_REG			0x900
374 
375 #define RCB_COM_CFG_ENDIAN_REG			0x0
376 #define RCB_COM_CFG_SYS_FSH_REG			0xC
377 #define RCB_COM_CFG_INIT_FLAG_REG		0x10
378 #define RCB_COM_CFG_PKT_REG			0x30
379 #define RCB_COM_CFG_RINVLD_REG			0x34
380 #define RCB_COM_CFG_FNA_REG			0x38
381 #define RCB_COM_CFG_FA_REG			0x3C
382 #define RCB_COM_CFG_PKT_TC_BP_REG		0x40
383 #define RCB_COM_CFG_PPE_TNL_CLKEN_REG		0x44
384 #define RCBV2_COM_CFG_USER_REG			0x30
385 #define RCBV2_COM_CFG_TSO_MODE_REG		0x50
386 
387 #define RCB_COM_INTMSK_TX_PKT_REG		0x3A0
388 #define RCB_COM_RINT_TX_PKT_REG			0x3A8
389 #define RCB_COM_INTMASK_ECC_ERR_REG		0x400
390 #define RCB_COM_INTSTS_ECC_ERR_REG		0x408
391 #define RCB_COM_EBD_SRAM_ERR_REG		0x410
392 #define RCB_COM_RXRING_ERR_REG			0x41C
393 #define RCB_COM_TXRING_ERR_REG			0x420
394 #define RCB_COM_TX_FBD_ERR_REG			0x424
395 #define RCB_SRAM_ECC_CHK_EN_REG			0x428
396 #define RCB_SRAM_ECC_CHK0_REG			0x42C
397 #define RCB_SRAM_ECC_CHK1_REG			0x430
398 #define RCB_SRAM_ECC_CHK2_REG			0x434
399 #define RCB_SRAM_ECC_CHK3_REG			0x438
400 #define RCB_SRAM_ECC_CHK4_REG			0x43c
401 #define RCB_SRAM_ECC_CHK5_REG			0x440
402 #define RCB_ECC_ERR_ADDR0_REG			0x450
403 #define RCB_ECC_ERR_ADDR3_REG			0x45C
404 #define RCB_ECC_ERR_ADDR4_REG			0x460
405 #define RCB_ECC_ERR_ADDR5_REG			0x464
406 
407 #define RCB_COM_SF_CFG_INTMASK_RING		0x480
408 #define RCB_COM_SF_CFG_RING_STS			0x484
409 #define RCB_COM_SF_CFG_RING			0x488
410 #define RCB_COM_SF_CFG_INTMASK_BD		0x48C
411 #define RCB_COM_SF_CFG_BD_RINT_STS		0x470
412 #define RCB_COM_RCB_RD_BD_BUSY			0x490
413 #define RCB_COM_RCB_FBD_CRT_EN			0x494
414 #define RCB_COM_AXI_WR_ERR_INTMASK		0x498
415 #define RCB_COM_AXI_ERR_STS			0x49C
416 #define RCB_COM_CHK_TX_FBD_NUM_REG		0x4a0
417 
418 #define RCB_CFG_BD_NUM_REG			0x9000
419 #define RCB_CFG_PKTLINE_REG			0x9050
420 
421 #define RCB_CFG_OVERTIME_REG			0x9300
422 #define RCB_CFG_PKTLINE_INT_NUM_REG		0x9304
423 #define RCB_CFG_OVERTIME_INT_NUM_REG		0x9308
424 #define RCB_INT_GAP_TIME_REG			0x9400
425 #define RCB_PORT_CFG_OVERTIME_REG		0x9430
426 
427 #define RCB_RING_RX_RING_BASEADDR_L_REG		0x00000
428 #define RCB_RING_RX_RING_BASEADDR_H_REG		0x00004
429 #define RCB_RING_RX_RING_BD_NUM_REG		0x00008
430 #define RCB_RING_RX_RING_BD_LEN_REG		0x0000C
431 #define RCB_RING_RX_RING_PKTLINE_REG		0x00010
432 #define RCB_RING_RX_RING_TAIL_REG		0x00018
433 #define RCB_RING_RX_RING_HEAD_REG		0x0001C
434 #define RCB_RING_RX_RING_FBDNUM_REG		0x00020
435 #define RCB_RING_RX_RING_PKTNUM_RECORD_REG	0x0002C
436 
437 #define RCB_RING_TX_RING_BASEADDR_L_REG		0x00040
438 #define RCB_RING_TX_RING_BASEADDR_H_REG		0x00044
439 #define RCB_RING_TX_RING_BD_NUM_REG		0x00048
440 #define RCB_RING_TX_RING_BD_LEN_REG		0x0004C
441 #define RCB_RING_TX_RING_PKTLINE_REG		0x00050
442 #define RCB_RING_TX_RING_TAIL_REG		0x00058
443 #define RCB_RING_TX_RING_HEAD_REG		0x0005C
444 #define RCB_RING_TX_RING_FBDNUM_REG		0x00060
445 #define RCB_RING_TX_RING_OFFSET_REG		0x00064
446 #define RCB_RING_TX_RING_PKTNUM_RECORD_REG	0x0006C
447 
448 #define RCB_RING_PREFETCH_EN_REG		0x0007C
449 #define RCB_RING_CFG_VF_NUM_REG			0x00080
450 #define RCB_RING_ASID_REG			0x0008C
451 #define RCB_RING_RX_VM_REG			0x00090
452 #define RCB_RING_T0_BE_RST			0x00094
453 #define RCB_RING_COULD_BE_RST			0x00098
454 #define RCB_RING_WRR_WEIGHT_REG			0x0009c
455 
456 #define RCB_RING_INTMSK_RXWL_REG		0x000A0
457 #define RCB_RING_INTSTS_RX_RING_REG		0x000A4
458 #define RCBV2_RX_RING_INT_STS_REG		0x000A8
459 #define RCB_RING_INTMSK_TXWL_REG		0x000AC
460 #define RCB_RING_INTSTS_TX_RING_REG		0x000B0
461 #define RCBV2_TX_RING_INT_STS_REG		0x000B4
462 #define RCB_RING_INTMSK_RX_OVERTIME_REG		0x000B8
463 #define RCB_RING_INTSTS_RX_OVERTIME_REG		0x000BC
464 #define RCB_RING_INTMSK_TX_OVERTIME_REG		0x000C4
465 #define RCB_RING_INTSTS_TX_OVERTIME_REG		0x000C8
466 
467 #define GMAC_DUPLEX_TYPE_REG			0x0008UL
468 #define GMAC_FD_FC_TYPE_REG			0x000CUL
469 #define GMAC_FC_TX_TIMER_REG			0x001CUL
470 #define GMAC_FD_FC_ADDR_LOW_REG			0x0020UL
471 #define GMAC_FD_FC_ADDR_HIGH_REG		0x0024UL
472 #define GMAC_IPG_TX_TIMER_REG			0x0030UL
473 #define GMAC_PAUSE_THR_REG			0x0038UL
474 #define GMAC_MAX_FRM_SIZE_REG			0x003CUL
475 #define GMAC_PORT_MODE_REG			0x0040UL
476 #define GMAC_PORT_EN_REG			0x0044UL
477 #define GMAC_PAUSE_EN_REG			0x0048UL
478 #define GMAC_SHORT_RUNTS_THR_REG		0x0050UL
479 #define GMAC_AN_NEG_STATE_REG			0x0058UL
480 #define GMAC_TX_LOCAL_PAGE_REG			0x005CUL
481 #define GMAC_TRANSMIT_CONTROL_REG		0x0060UL
482 #define GMAC_REC_FILT_CONTROL_REG		0x0064UL
483 #define GMAC_PTP_CONFIG_REG			0x0074UL
484 
485 #define GMAC_RX_OCTETS_TOTAL_OK_REG		0x0080UL
486 #define GMAC_RX_OCTETS_BAD_REG			0x0084UL
487 #define GMAC_RX_UC_PKTS_REG			0x0088UL
488 #define GMAC_RX_MC_PKTS_REG			0x008CUL
489 #define GMAC_RX_BC_PKTS_REG			0x0090UL
490 #define GMAC_RX_PKTS_64OCTETS_REG		0x0094UL
491 #define GMAC_RX_PKTS_65TO127OCTETS_REG		0x0098UL
492 #define GMAC_RX_PKTS_128TO255OCTETS_REG		0x009CUL
493 #define GMAC_RX_PKTS_255TO511OCTETS_REG		0x00A0UL
494 #define GMAC_RX_PKTS_512TO1023OCTETS_REG	0x00A4UL
495 #define GMAC_RX_PKTS_1024TO1518OCTETS_REG	0x00A8UL
496 #define GMAC_RX_PKTS_1519TOMAXOCTETS_REG	0x00ACUL
497 #define GMAC_RX_FCS_ERRORS_REG			0x00B0UL
498 #define GMAC_RX_TAGGED_REG			0x00B4UL
499 #define GMAC_RX_DATA_ERR_REG			0x00B8UL
500 #define GMAC_RX_ALIGN_ERRORS_REG		0x00BCUL
501 #define GMAC_RX_LONG_ERRORS_REG			0x00C0UL
502 #define GMAC_RX_JABBER_ERRORS_REG		0x00C4UL
503 #define GMAC_RX_PAUSE_MACCTRL_FRAM_REG		0x00C8UL
504 #define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG	0x00CCUL
505 #define GMAC_RX_VERY_LONG_ERR_CNT_REG		0x00D0UL
506 #define GMAC_RX_RUNT_ERR_CNT_REG		0x00D4UL
507 #define GMAC_RX_SHORT_ERR_CNT_REG		0x00D8UL
508 #define GMAC_RX_FILT_PKT_CNT_REG		0x00E8UL
509 #define GMAC_RX_OCTETS_TOTAL_FILT_REG		0x00ECUL
510 #define GMAC_OCTETS_TRANSMITTED_OK_REG		0x0100UL
511 #define GMAC_OCTETS_TRANSMITTED_BAD_REG		0x0104UL
512 #define GMAC_TX_UC_PKTS_REG			0x0108UL
513 #define GMAC_TX_MC_PKTS_REG			0x010CUL
514 #define GMAC_TX_BC_PKTS_REG			0x0110UL
515 #define GMAC_TX_PKTS_64OCTETS_REG		0x0114UL
516 #define GMAC_TX_PKTS_65TO127OCTETS_REG		0x0118UL
517 #define GMAC_TX_PKTS_128TO255OCTETS_REG		0x011CUL
518 #define GMAC_TX_PKTS_255TO511OCTETS_REG		0x0120UL
519 #define GMAC_TX_PKTS_512TO1023OCTETS_REG	0x0124UL
520 #define GMAC_TX_PKTS_1024TO1518OCTETS_REG	0x0128UL
521 #define GMAC_TX_PKTS_1519TOMAXOCTETS_REG	0x012CUL
522 #define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG	0x014CUL
523 #define GMAC_TX_UNDERRUN_REG			0x0150UL
524 #define GMAC_TX_TAGGED_REG			0x0154UL
525 #define GMAC_TX_CRC_ERROR_REG			0x0158UL
526 #define GMAC_TX_PAUSE_FRAMES_REG		0x015CUL
527 #define GAMC_RX_MAX_FRAME			0x0170UL
528 #define GMAC_LINE_LOOP_BACK_REG			0x01A8UL
529 #define GMAC_CF_CRC_STRIP_REG			0x01B0UL
530 #define GMAC_MODE_CHANGE_EN_REG			0x01B4UL
531 #define GMAC_SIXTEEN_BIT_CNTR_REG		0x01CCUL
532 #define GMAC_LD_LINK_COUNTER_REG		0x01D0UL
533 #define GMAC_LOOP_REG				0x01DCUL
534 #define GMAC_RECV_CONTROL_REG			0x01E0UL
535 #define GMAC_VLAN_CODE_REG			0x01E8UL
536 #define GMAC_RX_OVERRUN_CNT_REG			0x01ECUL
537 #define GMAC_RX_LENGTHFIELD_ERR_CNT_REG		0x01F4UL
538 #define GMAC_RX_FAIL_COMMA_CNT_REG		0x01F8UL
539 #define GMAC_STATION_ADDR_LOW_0_REG		0x0200UL
540 #define GMAC_STATION_ADDR_HIGH_0_REG		0x0204UL
541 #define GMAC_STATION_ADDR_LOW_1_REG		0x0208UL
542 #define GMAC_STATION_ADDR_HIGH_1_REG		0x020CUL
543 #define GMAC_STATION_ADDR_LOW_2_REG		0x0210UL
544 #define GMAC_STATION_ADDR_HIGH_2_REG		0x0214UL
545 #define GMAC_STATION_ADDR_LOW_3_REG		0x0218UL
546 #define GMAC_STATION_ADDR_HIGH_3_REG		0x021CUL
547 #define GMAC_STATION_ADDR_LOW_4_REG		0x0220UL
548 #define GMAC_STATION_ADDR_HIGH_4_REG		0x0224UL
549 #define GMAC_STATION_ADDR_LOW_5_REG		0x0228UL
550 #define GMAC_STATION_ADDR_HIGH_5_REG		0x022CUL
551 #define GMAC_STATION_ADDR_LOW_MSK_0_REG		0x0230UL
552 #define GMAC_STATION_ADDR_HIGH_MSK_0_REG	0x0234UL
553 #define GMAC_STATION_ADDR_LOW_MSK_1_REG		0x0238UL
554 #define GMAC_STATION_ADDR_HIGH_MSK_1_REG	0x023CUL
555 #define GMAC_MAC_SKIP_LEN_REG			0x0240UL
556 #define GMAC_TX_LOOP_PKT_PRI_REG		0x0378UL
557 
558 #define XGMAC_INT_STATUS_REG			0x0
559 #define XGMAC_INT_ENABLE_REG			0x4
560 #define XGMAC_INT_SET_REG			0x8
561 #define XGMAC_IERR_U_INFO_REG			0xC
562 #define XGMAC_OVF_INFO_REG			0x10
563 #define XGMAC_OVF_CNT_REG			0x14
564 #define XGMAC_PORT_MODE_REG			0x40
565 #define XGMAC_CLK_ENABLE_REG			0x44
566 #define XGMAC_RESET_REG				0x48
567 #define XGMAC_LINK_CONTROL_REG			0x50
568 #define XGMAC_LINK_STATUS_REG			0x54
569 #define XGMAC_SPARE_REG				0xC0
570 #define XGMAC_SPARE_CNT_REG			0xC4
571 
572 #define XGMAC_MAC_ENABLE_REG			0x100
573 #define XGMAC_MAC_CONTROL_REG			0x104
574 #define XGMAC_MAC_IPG_REG			0x120
575 #define XGMAC_MAC_MSG_CRC_EN_REG		0x124
576 #define XGMAC_MAC_MSG_IMG_REG			0x128
577 #define XGMAC_MAC_MSG_FC_CFG_REG		0x12C
578 #define XGMAC_MAC_MSG_TC_CFG_REG		0x130
579 #define XGMAC_MAC_PAD_SIZE_REG			0x134
580 #define XGMAC_MAC_MIN_PKT_SIZE_REG		0x138
581 #define XGMAC_MAC_MAX_PKT_SIZE_REG		0x13C
582 #define XGMAC_MAC_PAUSE_CTRL_REG		0x160
583 #define XGMAC_MAC_PAUSE_TIME_REG		0x164
584 #define XGMAC_MAC_PAUSE_GAP_REG			0x168
585 #define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG		0x16C
586 #define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG		0x170
587 #define XGMAC_MAC_PAUSE_PEER_MAC_H_REG		0x174
588 #define XGMAC_MAC_PAUSE_PEER_MAC_L_REG		0x178
589 #define XGMAC_MAC_PFC_PRI_EN_REG		0x17C
590 #define XGMAC_MAC_1588_CTRL_REG			0x180
591 #define XGMAC_MAC_1588_TX_PORT_DLY_REG		0x184
592 #define XGMAC_MAC_1588_RX_PORT_DLY_REG		0x188
593 #define XGMAC_MAC_1588_ASYM_DLY_REG		0x18C
594 #define XGMAC_MAC_1588_ADJUST_CFG_REG		0x190
595 #define XGMAC_MAC_Y1731_ETH_TYPE_REG		0x194
596 #define XGMAC_MAC_MIB_CONTROL_REG		0x198
597 #define XGMAC_MAC_WAN_RATE_ADJUST_REG		0x19C
598 #define XGMAC_MAC_TX_ERR_MARK_REG		0x1A0
599 #define XGMAC_MAC_TX_LF_RF_CONTROL_REG		0x1A4
600 #define XGMAC_MAC_RX_LF_RF_STATUS_REG		0x1A8
601 #define XGMAC_MAC_TX_RUNT_PKT_CNT_REG		0x1C0
602 #define XGMAC_MAC_RX_RUNT_PKT_CNT_REG		0x1C4
603 #define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG	0x1C8
604 #define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG	0x1CC
605 #define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG	0x1D0
606 #define XGMAC_MAC_RX_ERR_MSG_CNT_REG		0x1D4
607 #define XGMAC_MAC_RX_ERR_EFD_CNT_REG		0x1D8
608 #define XGMAC_MAC_ERR_INFO_REG			0x1DC
609 #define XGMAC_MAC_DBG_INFO_REG			0x1E0
610 
611 #define XGMAC_PCS_BASER_SYNC_THD_REG		0x330
612 #define XGMAC_PCS_STATUS1_REG			0x404
613 #define XGMAC_PCS_BASER_STATUS1_REG		0x410
614 #define XGMAC_PCS_BASER_STATUS2_REG		0x414
615 #define XGMAC_PCS_BASER_SEEDA_0_REG		0x420
616 #define XGMAC_PCS_BASER_SEEDA_1_REG		0x424
617 #define XGMAC_PCS_BASER_SEEDB_0_REG		0x428
618 #define XGMAC_PCS_BASER_SEEDB_1_REG		0x42C
619 #define XGMAC_PCS_BASER_TEST_CONTROL_REG	0x430
620 #define XGMAC_PCS_BASER_TEST_ERR_CNT_REG	0x434
621 #define XGMAC_PCS_DBG_INFO_REG			0x4C0
622 #define XGMAC_PCS_DBG_INFO1_REG			0x4C4
623 #define XGMAC_PCS_DBG_INFO2_REG			0x4C8
624 #define XGMAC_PCS_DBG_INFO3_REG			0x4CC
625 
626 #define XGMAC_PMA_ENABLE_REG			0x700
627 #define XGMAC_PMA_CONTROL_REG			0x704
628 #define XGMAC_PMA_SIGNAL_STATUS_REG		0x708
629 #define XGMAC_PMA_DBG_INFO_REG			0x70C
630 #define XGMAC_PMA_FEC_ABILITY_REG		0x740
631 #define XGMAC_PMA_FEC_CONTROL_REG		0x744
632 #define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG	0x750
633 #define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG	0x760
634 
635 #define XGMAC_TX_PKTS_FRAGMENT			0x0000
636 #define XGMAC_TX_PKTS_UNDERSIZE			0x0008
637 #define XGMAC_TX_PKTS_UNDERMIN			0x0010
638 #define XGMAC_TX_PKTS_64OCTETS			0x0018
639 #define XGMAC_TX_PKTS_65TO127OCTETS		0x0020
640 #define XGMAC_TX_PKTS_128TO255OCTETS		0x0028
641 #define XGMAC_TX_PKTS_256TO511OCTETS		0x0030
642 #define XGMAC_TX_PKTS_512TO1023OCTETS		0x0038
643 #define XGMAC_TX_PKTS_1024TO1518OCTETS		0x0040
644 #define XGMAC_TX_PKTS_1519TOMAXOCTETS		0x0048
645 #define XGMAC_TX_PKTS_1519TOMAXOCTETSOK		0x0050
646 #define XGMAC_TX_PKTS_OVERSIZE			0x0058
647 #define XGMAC_TX_PKTS_JABBER			0x0060
648 #define XGMAC_TX_GOODPKTS			0x0068
649 #define XGMAC_TX_GOODOCTETS			0x0070
650 #define XGMAC_TX_TOTAL_PKTS			0x0078
651 #define XGMAC_TX_TOTALOCTETS			0x0080
652 #define XGMAC_TX_UNICASTPKTS			0x0088
653 #define XGMAC_TX_MULTICASTPKTS			0x0090
654 #define XGMAC_TX_BROADCASTPKTS			0x0098
655 #define XGMAC_TX_PRI0PAUSEPKTS			0x00a0
656 #define XGMAC_TX_PRI1PAUSEPKTS			0x00a8
657 #define XGMAC_TX_PRI2PAUSEPKTS			0x00b0
658 #define XGMAC_TX_PRI3PAUSEPKTS			0x00b8
659 #define XGMAC_TX_PRI4PAUSEPKTS			0x00c0
660 #define XGMAC_TX_PRI5PAUSEPKTS			0x00c8
661 #define XGMAC_TX_PRI6PAUSEPKTS			0x00d0
662 #define XGMAC_TX_PRI7PAUSEPKTS			0x00d8
663 #define XGMAC_TX_MACCTRLPKTS			0x00e0
664 #define XGMAC_TX_1731PKTS			0x00e8
665 #define XGMAC_TX_1588PKTS			0x00f0
666 #define XGMAC_RX_FROMAPPGOODPKTS		0x00f8
667 #define XGMAC_RX_FROMAPPBADPKTS			0x0100
668 #define XGMAC_TX_ERRALLPKTS			0x0108
669 
670 #define XGMAC_RX_PKTS_FRAGMENT			0x0110
671 #define XGMAC_RX_PKTSUNDERSIZE			0x0118
672 #define XGMAC_RX_PKTS_UNDERMIN			0x0120
673 #define XGMAC_RX_PKTS_64OCTETS			0x0128
674 #define XGMAC_RX_PKTS_65TO127OCTETS		0x0130
675 #define XGMAC_RX_PKTS_128TO255OCTETS		0x0138
676 #define XGMAC_RX_PKTS_256TO511OCTETS		0x0140
677 #define XGMAC_RX_PKTS_512TO1023OCTETS		0x0148
678 #define XGMAC_RX_PKTS_1024TO1518OCTETS		0x0150
679 #define XGMAC_RX_PKTS_1519TOMAXOCTETS		0x0158
680 #define XGMAC_RX_PKTS_1519TOMAXOCTETSOK		0x0160
681 #define XGMAC_RX_PKTS_OVERSIZE			0x0168
682 #define XGMAC_RX_PKTS_JABBER			0x0170
683 #define XGMAC_RX_GOODPKTS			0x0178
684 #define XGMAC_RX_GOODOCTETS			0x0180
685 #define XGMAC_RX_TOTAL_PKTS			0x0188
686 #define XGMAC_RX_TOTALOCTETS			0x0190
687 #define XGMAC_RX_UNICASTPKTS			0x0198
688 #define XGMAC_RX_MULTICASTPKTS			0x01a0
689 #define XGMAC_RX_BROADCASTPKTS			0x01a8
690 #define XGMAC_RX_PRI0PAUSEPKTS			0x01b0
691 #define XGMAC_RX_PRI1PAUSEPKTS			0x01b8
692 #define XGMAC_RX_PRI2PAUSEPKTS			0x01c0
693 #define XGMAC_RX_PRI3PAUSEPKTS			0x01c8
694 #define XGMAC_RX_PRI4PAUSEPKTS			0x01d0
695 #define XGMAC_RX_PRI5PAUSEPKTS			0x01d8
696 #define XGMAC_RX_PRI6PAUSEPKTS			0x01e0
697 #define XGMAC_RX_PRI7PAUSEPKTS			0x01e8
698 #define XGMAC_RX_MACCTRLPKTS			0x01f0
699 #define XGMAC_TX_SENDAPPGOODPKTS		0x01f8
700 #define XGMAC_TX_SENDAPPBADPKTS			0x0200
701 #define XGMAC_RX_1731PKTS			0x0208
702 #define XGMAC_RX_SYMBOLERRPKTS			0x0210
703 #define XGMAC_RX_FCSERRPKTS			0x0218
704 
705 #define DSAF_SRAM_INIT_OVER_M 0xff
706 #define DSAFV2_SRAM_INIT_OVER_M 0x3ff
707 #define DSAF_SRAM_INIT_OVER_S 0
708 
709 #define DSAF_CFG_EN_S 0
710 #define DSAF_CFG_TC_MODE_S 1
711 #define DSAF_CFG_CRC_EN_S 2
712 #define DSAF_CFG_SBM_INIT_S 3
713 #define DSAF_CFG_MIX_MODE_S 4
714 #define DSAF_CFG_STP_MODE_S 5
715 #define DSAF_CFG_LOCA_ADDR_EN_S 6
716 #define DSAFV2_CFG_VLAN_TAG_MODE_S 17
717 
718 #define DSAF_CNT_CLR_CE_S 0
719 #define DSAF_SNAP_EN_S 1
720 
721 #define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE 41
722 #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 410
723 #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 103
724 
725 #define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1)
726 #define DSAF_PFC_UNINT_CNT_S 0
727 
728 #define DSAF_MAC_PAUSE_RX_EN_B 2
729 #define DSAF_PFC_PAUSE_RX_EN_B 1
730 #define DSAF_PFC_PAUSE_TX_EN_B 0
731 
732 #define DSAF_PPE_QID_CFG_M 0xFF
733 #define DSAF_PPE_QID_CFG_S 0
734 
735 #define DSAF_SW_PORT_TYPE_M 3
736 #define DSAF_SW_PORT_TYPE_S 0
737 
738 #define DSAF_STP_PORT_TYPE_M 7
739 #define DSAF_STP_PORT_TYPE_S 0
740 
741 #define DSAF_INODE_IN_PORT_NUM_M 7
742 #define DSAF_INODE_IN_PORT_NUM_S 0
743 #define DSAFV2_INODE_IN_PORT1_NUM_M (7ULL << 3)
744 #define DSAFV2_INODE_IN_PORT1_NUM_S 3
745 #define DSAFV2_INODE_IN_PORT2_NUM_M (7ULL << 6)
746 #define DSAFV2_INODE_IN_PORT2_NUM_S 6
747 #define DSAFV2_INODE_IN_PORT3_NUM_M (7ULL << 9)
748 #define DSAFV2_INODE_IN_PORT3_NUM_S 9
749 #define DSAFV2_INODE_IN_PORT4_NUM_M (7ULL << 12)
750 #define DSAFV2_INODE_IN_PORT4_NUM_S 12
751 #define DSAFV2_INODE_IN_PORT5_NUM_M (7ULL << 15)
752 #define DSAFV2_INODE_IN_PORT5_NUM_S 15
753 
754 #define HNS_DSAF_I4TC_CFG 0x18688688
755 #define HNS_DSAF_I8TC_CFG 0x18FAC688
756 
757 #define DSAF_SBM_CFG_SHCUT_EN_S 0
758 #define DSAF_SBM_CFG_EN_S 1
759 #define DSAF_SBM_CFG_MIB_EN_S 2
760 #define DSAF_SBM_CFG_ECC_INVERT_EN_S 3
761 
762 #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S 0
763 #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)
764 #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S 10
765 #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)
766 #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S 20
767 #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 11) - 1) << 20)
768 
769 #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S 0
770 #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0)
771 #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S 10
772 #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10)
773 
774 #define DSAF_SBM_CFG2_SET_BUF_NUM_S 0
775 #define DSAF_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 10) - 1) << 0)
776 #define DSAF_SBM_CFG2_RESET_BUF_NUM_S 10
777 #define DSAF_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 10) - 1) << 10)
778 
779 #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0
780 #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 0)
781 #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 10
782 #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 10)
783 
784 #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S 0
785 #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0)
786 #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S 9
787 #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9)
788 #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S 18
789 #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 18)
790 
791 #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S 0
792 #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0)
793 #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S 9
794 #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9)
795 
796 #define DSAFV2_SBM_CFG2_SET_BUF_NUM_S 0
797 #define DSAFV2_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 9) - 1) << 0)
798 #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_S 9
799 #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 9) - 1) << 9)
800 
801 #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0
802 #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0)
803 #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 9
804 #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9)
805 
806 #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S 0
807 #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0)
808 #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S 9
809 #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9)
810 
811 #define DSAF_CHNS_MASK			0x3f000
812 #define DSAF_SBM_ROCEE_CFG_CRD_EN_B	2
813 #define SRST_TIME_INTERVAL		20
814 #define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S 0
815 #define DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M (((1ULL << 8) - 1) << 0)
816 #define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S 8
817 #define DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M (((1ULL << 8) - 1) << 8)
818 
819 #define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S (0)
820 #define DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M (((1ULL << 6) - 1) << 0)
821 #define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S (6)
822 #define DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M (((1ULL << 6) - 1) << 6)
823 #define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S (12)
824 #define DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M (((1ULL << 6) - 1) << 12)
825 
826 #define DSAF_TBL_TCAM_ADDR_S 0
827 #define DSAF_TBL_TCAM_ADDR_M ((1ULL << 9) - 1)
828 
829 #define DSAF_TBL_LINE_ADDR_S 0
830 #define DSAF_TBL_LINE_ADDR_M ((1ULL << 15) - 1)
831 
832 #define DSAF_TBL_MCAST_CFG4_VM128_112_S 0
833 #define DSAF_TBL_MCAST_CFG4_VM128_112_M (((1ULL << 7) - 1) << 0)
834 #define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S 7
835 #define DSAF_TBL_MCAST_CFG4_OLD_EN_S 8
836 
837 #define DSAF_TBL_MCAST_CFG0_XGE5_0_S 0
838 #define DSAF_TBL_MCAST_CFG0_XGE5_0_M (((1ULL << 6) - 1) << 0)
839 #define DSAF_TBL_MCAST_CFG0_VM25_0_S 6
840 #define DSAF_TBL_MCAST_CFG0_VM25_0_M (((1ULL << 26) - 1) << 6)
841 
842 #define DSAF_TBL_UCAST_CFG1_OUT_PORT_S 0
843 #define DSAF_TBL_UCAST_CFG1_OUT_PORT_M (((1ULL << 8) - 1) << 0)
844 #define DSAF_TBL_UCAST_CFG1_DVC_S 8
845 #define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S 9
846 #define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S 10
847 #define DSAF_TBL_UCAST_CFG1_OLD_EN_S 11
848 
849 #define DSAF_TBL_LINE_CFG_OUT_PORT_S 0
850 #define DSAF_TBL_LINE_CFG_OUT_PORT_M (((1ULL << 8) - 1) << 0)
851 #define DSAF_TBL_LINE_CFG_DVC_S 8
852 #define DSAF_TBL_LINE_CFG_MAC_DISCARD_S 9
853 
854 #define DSAF_TBL_PUL_OLD_RSLT_RE_S 0
855 #define DSAF_TBL_PUL_MCAST_VLD_S 1
856 #define DSAF_TBL_PUL_TCAM_DATA_VLD_S 2
857 #define DSAF_TBL_PUL_UCAST_VLD_S 3
858 #define DSAF_TBL_PUL_LINE_VLD_S 4
859 #define DSAF_TBL_PUL_TCAM_LOAD_S 5
860 #define DSAF_TBL_PUL_LINE_LOAD_S 6
861 
862 #define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S 0
863 #define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S 1
864 #define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S 2
865 #define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S 3
866 #define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S 4
867 
868 #define DSAF_VOQ_BP_ALL_DOWNTHRD_S 0
869 #define DSAF_VOQ_BP_ALL_DOWNTHRD_M (((1ULL << 10) - 1) << 0)
870 #define DSAF_VOQ_BP_ALL_UPTHRD_S 10
871 #define DSAF_VOQ_BP_ALL_UPTHRD_M (((1ULL << 10) - 1) << 10)
872 
873 #define DSAF_XGE_GE_WORK_MODE_S 0
874 #define DSAF_XGE_GE_LOOPBACK_S 1
875 
876 #define DSAF_FC_XGE_TX_PAUSE_S 0
877 #define DSAF_REGS_XGE_CNT_CAR_S 1
878 
879 #define PPE_CFG_QID_MODE_DEF_QID_S	0
880 #define PPE_CFG_QID_MODE_DEF_QID_M	(0xff << PPE_CFG_QID_MODE_DEF_QID_S)
881 
882 #define PPE_CFG_QID_MODE_CF_QID_MODE_S	8
883 #define PPE_CFG_QID_MODE_CF_QID_MODE_M	(0x7 << PPE_CFG_QID_MODE_CF_QID_MODE_S)
884 
885 #define PPEV2_CFG_RSS_TBL_4N0_S	0
886 #define PPEV2_CFG_RSS_TBL_4N0_M	(((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N0_S)
887 
888 #define PPEV2_CFG_RSS_TBL_4N1_S	8
889 #define PPEV2_CFG_RSS_TBL_4N1_M	(((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N1_S)
890 
891 #define PPEV2_CFG_RSS_TBL_4N2_S	16
892 #define PPEV2_CFG_RSS_TBL_4N2_M	(((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N2_S)
893 
894 #define PPEV2_CFG_RSS_TBL_4N3_S	24
895 #define PPEV2_CFG_RSS_TBL_4N3_M	(((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N3_S)
896 
897 #define DSAFV2_SERDES_LBK_EN_B  8
898 #define DSAFV2_SERDES_LBK_QID_S 0
899 #define DSAFV2_SERDES_LBK_QID_M	(((1UL << 8) - 1) << DSAFV2_SERDES_LBK_QID_S)
900 
901 #define PPE_CNT_CLR_CE_B	0
902 #define PPE_CNT_CLR_SNAP_EN_B	1
903 
904 #define PPE_INT_GAPTIME_B	0
905 #define PPE_INT_GAPTIME_M	0x3ff
906 
907 #define PPE_COMMON_CNT_CLR_CE_B	0
908 #define PPE_COMMON_CNT_CLR_SNAP_EN_B	1
909 #define RCB_COM_TSO_MODE_B	0
910 #define RCB_COM_CFG_FNA_B	1
911 #define RCB_COM_CFG_FA_B	0
912 
913 #define GMAC_DUPLEX_TYPE_B 0
914 
915 #define GMAC_FC_TX_TIMER_S 0
916 #define GMAC_FC_TX_TIMER_M 0xffff
917 
918 #define GMAC_MAX_FRM_SIZE_S 0
919 #define GMAC_MAX_FRM_SIZE_M 0xffff
920 
921 #define GMAC_PORT_MODE_S	0
922 #define GMAC_PORT_MODE_M	0xf
923 
924 #define GMAC_RGMII_1000M_DELAY_B	4
925 #define GMAC_MII_TX_EDGE_SEL_B		5
926 #define GMAC_FIFO_ERR_AUTO_RST_B	6
927 #define GMAC_DBG_CLK_LOS_MSK_B		7
928 
929 #define GMAC_PORT_RX_EN_B	1
930 #define GMAC_PORT_TX_EN_B	2
931 
932 #define GMAC_PAUSE_EN_RX_FDFC_B 0
933 #define GMAC_PAUSE_EN_TX_FDFC_B 1
934 #define GMAC_PAUSE_EN_TX_HDFC_B 2
935 
936 #define GMAC_SHORT_RUNTS_THR_S 0
937 #define GMAC_SHORT_RUNTS_THR_M 0x1f
938 
939 #define GMAC_AN_NEG_STAT_FD_B		5
940 #define GMAC_AN_NEG_STAT_HD_B		6
941 #define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B	12
942 #define GMAC_AN_NEG_STAT_RF2_B		13
943 
944 #define GMAC_AN_NEG_STAT_NP_LNK_OK_B	15
945 #define GMAC_AN_NEG_STAT_RX_SYNC_OK_B	20
946 #define GMAC_AN_NEG_STAT_AN_DONE_B	21
947 
948 #define GMAC_AN_NEG_STAT_PS_S		7
949 #define GMAC_AN_NEG_STAT_PS_M		(0x3 << GMAC_AN_NEG_STAT_PS_S)
950 
951 #define GMAC_AN_NEG_STAT_SPEED_S	10
952 #define GMAC_AN_NEG_STAT_SPEED_M	(0x3 << GMAC_AN_NEG_STAT_SPEED_S)
953 
954 #define GMAC_TX_AN_EN_B		5
955 #define GMAC_TX_CRC_ADD_B	6
956 #define GMAC_TX_PAD_EN_B	7
957 
958 #define GMAC_LINE_LOOPBACK_B	0
959 
960 #define GMAC_LP_REG_CF_EXT_DRV_LP_B	1
961 #define GMAC_LP_REG_CF2MI_LP_EN_B	2
962 
963 #define GMAC_MODE_CHANGE_EB_B	0
964 #define GMAC_UC_MATCH_EN_B	0
965 #define GMAC_ADDR_EN_B		16
966 
967 #define GMAC_RECV_CTRL_STRIP_PAD_EN_B	3
968 #define GMAC_RECV_CTRL_RUNT_PKT_EN_B	4
969 
970 #define GMAC_TX_LOOP_PKT_HIG_PRI_B	0
971 #define GMAC_TX_LOOP_PKT_EN_B		1
972 
973 #define XGMAC_PORT_MODE_TX_S		0x0
974 #define XGMAC_PORT_MODE_TX_M		(0x3 << XGMAC_PORT_MODE_TX_S)
975 #define XGMAC_PORT_MODE_TX_40G_B	0x3
976 #define XGMAC_PORT_MODE_RX_S		0x4
977 #define XGMAC_PORT_MODE_RX_M		(0x3 << XGMAC_PORT_MODE_RX_S)
978 #define XGMAC_PORT_MODE_RX_40G_B	0x7
979 
980 #define XGMAC_ENABLE_TX_B		0
981 #define XGMAC_ENABLE_RX_B		1
982 
983 #define XGMAC_UNIDIR_EN_B		0
984 #define XGMAC_RF_TX_EN_B		1
985 #define XGMAC_LF_RF_INSERT_S		2
986 #define XGMAC_LF_RF_INSERT_M		(0x3 << XGMAC_LF_RF_INSERT_S)
987 
988 #define XGMAC_CTL_TX_FCS_B		0
989 #define XGMAC_CTL_TX_PAD_B		1
990 #define XGMAC_CTL_TX_PREAMBLE_TRANS_B	3
991 #define XGMAC_CTL_TX_UNDER_MIN_ERR_B	4
992 #define XGMAC_CTL_TX_TRUNCATE_B		5
993 #define XGMAC_CTL_TX_1588_B		8
994 #define XGMAC_CTL_TX_1731_B		9
995 #define XGMAC_CTL_TX_PFC_B		10
996 #define XGMAC_CTL_RX_FCS_B		16
997 #define XGMAC_CTL_RX_FCS_STRIP_B	17
998 #define XGMAC_CTL_RX_PREAMBLE_TRANS_B	19
999 #define XGMAC_CTL_RX_UNDER_MIN_ERR_B	20
1000 #define XGMAC_CTL_RX_TRUNCATE_B		21
1001 #define XGMAC_CTL_RX_1588_B		24
1002 #define XGMAC_CTL_RX_1731_B		25
1003 #define XGMAC_CTL_RX_PFC_B		26
1004 
1005 #define XGMAC_PMA_FEC_CTL_TX_B		0
1006 #define XGMAC_PMA_FEC_CTL_RX_B		1
1007 #define XGMAC_PMA_FEC_CTL_ERR_EN	2
1008 #define XGMAC_PMA_FEC_CTL_ERR_SH	3
1009 
1010 #define XGMAC_PAUSE_CTL_TX_B		0
1011 #define XGMAC_PAUSE_CTL_RX_B		1
1012 #define XGMAC_PAUSE_CTL_RSP_MODE_B	2
1013 #define XGMAC_PAUSE_CTL_TX_XOFF_B	3
1014 
1015 static inline void dsaf_write_reg(void __iomem *base, u32 reg, u32 value)
1016 {
1017 	writel(value, base + reg);
1018 }
1019 
1020 #define dsaf_write_dev(a, reg, value) \
1021 	dsaf_write_reg((a)->io_base, (reg), (value))
1022 
1023 static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg)
1024 {
1025 	return readl(base + reg);
1026 }
1027 
1028 static inline void dsaf_write_syscon(struct regmap *base, u32 reg, u32 value)
1029 {
1030 	regmap_write(base, reg, value);
1031 }
1032 
1033 static inline u32 dsaf_read_syscon(struct regmap *base, u32 reg)
1034 {
1035 	unsigned int val;
1036 
1037 	regmap_read(base, reg, &val);
1038 	return val;
1039 }
1040 
1041 #define dsaf_read_dev(a, reg) \
1042 	dsaf_read_reg((a)->io_base, (reg))
1043 
1044 #define dsaf_set_field(origin, mask, shift, val) \
1045 	do { \
1046 		(origin) &= (~(mask)); \
1047 		(origin) |= (((val) << (shift)) & (mask)); \
1048 	} while (0)
1049 
1050 #define dsaf_set_bit(origin, shift, val) \
1051 	dsaf_set_field((origin), (1ull << (shift)), (shift), (val))
1052 
1053 static inline void dsaf_set_reg_field(void __iomem *base, u32 reg, u32 mask,
1054 				      u32 shift, u32 val)
1055 {
1056 	u32 origin = dsaf_read_reg(base, reg);
1057 
1058 	dsaf_set_field(origin, mask, shift, val);
1059 	dsaf_write_reg(base, reg, origin);
1060 }
1061 
1062 #define dsaf_set_dev_field(dev, reg, mask, shift, val) \
1063 	dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val))
1064 
1065 #define dsaf_set_dev_bit(dev, reg, bit, val) \
1066 	dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val))
1067 
1068 #define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
1069 
1070 #define dsaf_get_bit(origin, shift) \
1071 	dsaf_get_field((origin), (1ull << (shift)), (shift))
1072 
1073 static inline u32 dsaf_get_reg_field(void __iomem *base, u32 reg, u32 mask,
1074 				     u32 shift)
1075 {
1076 	u32 origin;
1077 
1078 	origin = dsaf_read_reg(base, reg);
1079 	return dsaf_get_field(origin, mask, shift);
1080 }
1081 
1082 #define dsaf_get_dev_field(dev, reg, mask, shift) \
1083 	dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift))
1084 
1085 #define dsaf_get_dev_bit(dev, reg, bit) \
1086 	dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit))
1087 
1088 #define dsaf_write_b(addr, data)\
1089 	writeb((data), (__iomem unsigned char *)(addr))
1090 #define dsaf_read_b(addr)\
1091 	readb((__iomem unsigned char *)(addr))
1092 
1093 #define hns_mac_reg_read64(drv, offset) \
1094 	readq((__iomem void *)(((u8 *)(drv)->io_base + 0xc00 + (offset))))
1095 
1096 #endif	/* _DSAF_REG_H */
1097