1511e6bc0Shuangdaode /* 2511e6bc0Shuangdaode * Copyright (c) 2014-2015 Hisilicon Limited. 3511e6bc0Shuangdaode * 4511e6bc0Shuangdaode * This program is free software; you can redistribute it and/or modify 5511e6bc0Shuangdaode * it under the terms of the GNU General Public License as published by 6511e6bc0Shuangdaode * the Free Software Foundation; either version 2 of the License, or 7511e6bc0Shuangdaode * (at your option) any later version. 8511e6bc0Shuangdaode */ 9511e6bc0Shuangdaode 10511e6bc0Shuangdaode #ifndef _DSAF_REG_H_ 11511e6bc0Shuangdaode #define _DSAF_REG_H_ 12511e6bc0Shuangdaode 1313ac695eSSalil #define HNS_DEBUG_RING_IRQ_IDX 55 1413ac695eSSalil #define HNS_SERVICE_RING_IRQ_IDX 59 1513ac695eSSalil #define HNS_DEBUG_RING_IRQ_OFFSET 2 1613ac695eSSalil #define HNSV2_DEBUG_RING_IRQ_IDX 409 1713ac695eSSalil #define HNSV2_SERVICE_RING_IRQ_IDX 25 1813ac695eSSalil #define HNSV2_DEBUG_RING_IRQ_OFFSET 9 19511e6bc0Shuangdaode 20511e6bc0Shuangdaode #define DSAF_MAX_PORT_NUM_PER_CHIP 8 21511e6bc0Shuangdaode #define DSAF_SERVICE_PORT_NUM_PER_DSAF 6 22511e6bc0Shuangdaode #define DSAF_MAX_VM_NUM 128 23511e6bc0Shuangdaode 24511e6bc0Shuangdaode #define DSAF_COMM_DEV_NUM 3 25511e6bc0Shuangdaode #define DSAF_PPE_INODE_BASE 6 26511e6bc0Shuangdaode #define HNS_DSAF_COMM_SERVICE_NW_IDX 0 27511e6bc0Shuangdaode #define DSAF_DEBUG_NW_NUM 2 28511e6bc0Shuangdaode #define DSAF_SERVICE_NW_NUM 6 29511e6bc0Shuangdaode #define DSAF_COMM_CHN DSAF_SERVICE_NW_NUM 30511e6bc0Shuangdaode #define DSAF_GE_NUM ((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM)) 31511e6bc0Shuangdaode #define DSAF_PORT_NUM ((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM)) 32511e6bc0Shuangdaode #define DSAF_XGE_NUM DSAF_SERVICE_NW_NUM 3313ac695eSSalil #define DSAF_PORT_TYPE_NUM 3 34511e6bc0Shuangdaode #define DSAF_NODE_NUM 18 35511e6bc0Shuangdaode #define DSAF_XOD_BIG_NUM DSAF_NODE_NUM 36511e6bc0Shuangdaode #define DSAF_SBM_NUM DSAF_NODE_NUM 3713ac695eSSalil #define DSAFV2_SBM_NUM 8 3813ac695eSSalil #define DSAFV2_SBM_XGE_CHN 6 3913ac695eSSalil #define DSAFV2_SBM_PPE_CHN 1 4013ac695eSSalil #define DASFV2_ROCEE_CRD_NUM 8 4113ac695eSSalil 42511e6bc0Shuangdaode #define DSAF_VOQ_NUM DSAF_NODE_NUM 43511e6bc0Shuangdaode #define DSAF_INODE_NUM DSAF_NODE_NUM 44511e6bc0Shuangdaode #define DSAF_XOD_NUM 8 45511e6bc0Shuangdaode #define DSAF_TBL_NUM 8 46511e6bc0Shuangdaode #define DSAF_SW_PORT_NUM 8 47511e6bc0Shuangdaode #define DSAF_TOTAL_QUEUE_NUM 129 48511e6bc0Shuangdaode 49511e6bc0Shuangdaode #define DSAF_TCAM_SUM 512 50511e6bc0Shuangdaode #define DSAF_LINE_SUM (2048 * 14) 51511e6bc0Shuangdaode 52511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100 53511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180 54511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184 55511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188 56511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C 57511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190 58511e6bc0Shuangdaode #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194 59511e6bc0Shuangdaode #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300 60511e6bc0Shuangdaode #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304 61511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_CLK_EN_REG 0x308 62511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_CLK_DIS_REG 0x30C 63511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_CLK_EN_REG 0x310 64511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_CLK_DIS_REG 0x314 65511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_CLK_EN_REG 0x318 66511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_CLK_DIS_REG 0x31C 67511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_CLK_EN_REG 0x320 68511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_CLK_DIS_REG 0x324 69511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG 0x350 70511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG 0x354 71511e6bc0Shuangdaode #define DSAF_SUB_SC_XBAR_RESET_REQ_REG 0xA00 72511e6bc0Shuangdaode #define DSAF_SUB_SC_XBAR_RESET_DREQ_REG 0xA04 73511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_RESET_REQ_REG 0xA08 74511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_RESET_DREQ_REG 0xA0C 75511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_RESET_REQ_REG 0xA10 76511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_RESET_DREQ_REG 0xA14 77511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_REQ0_REG 0xA18 78511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_DREQ0_REG 0xA1C 79511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_REQ1_REG 0xA20 80511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_DREQ1_REG 0xA24 81511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_RESET_REQ_REG 0xA48 82511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_RESET_DREQ_REG 0xA4C 83511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG 0xA88 84511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG 0xA8C 85511e6bc0Shuangdaode #define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG 0x2060 86511e6bc0Shuangdaode #define DSAF_SUB_SC_TCAM_MBIST_EN_REG 0x2300 87511e6bc0Shuangdaode #define DSAF_SUB_SC_DSAF_CLK_ST_REG 0x5300 88511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_CLK_ST_REG 0x5304 89511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_CLK_ST_REG 0x5308 90511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_CLK_ST_REG 0x530C 91511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_CLK_ST_REG 0x5310 92511e6bc0Shuangdaode #define DSAF_SUB_SC_ROCEE_CLK_ST_REG 0x5314 93511e6bc0Shuangdaode #define DSAF_SUB_SC_CPU_CLK_ST_REG 0x5318 94511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG 0x5328 95511e6bc0Shuangdaode #define DSAF_SUB_SC_XBAR_RESET_ST_REG 0x5A00 96511e6bc0Shuangdaode #define DSAF_SUB_SC_NT_RESET_ST_REG 0x5A04 97511e6bc0Shuangdaode #define DSAF_SUB_SC_XGE_RESET_ST_REG 0x5A08 98511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_ST0_REG 0x5A0C 99511e6bc0Shuangdaode #define DSAF_SUB_SC_GE_RESET_ST1_REG 0x5A10 100511e6bc0Shuangdaode #define DSAF_SUB_SC_PPE_RESET_ST_REG 0x5A24 101511e6bc0Shuangdaode #define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG 0x5A44 102511e6bc0Shuangdaode 103511e6bc0Shuangdaode /*serdes offset**/ 104511e6bc0Shuangdaode #define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 105511e6bc0Shuangdaode #define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 106511e6bc0Shuangdaode #define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL 107511e6bc0Shuangdaode #define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL 108511e6bc0Shuangdaode #define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL 109511e6bc0Shuangdaode #define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL 110511e6bc0Shuangdaode #define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL 111511e6bc0Shuangdaode #define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL 112511e6bc0Shuangdaode #define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL 113511e6bc0Shuangdaode #define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL 114511e6bc0Shuangdaode 115511e6bc0Shuangdaode #define HILINK_RESET_TIMOUT 10000 116511e6bc0Shuangdaode 117511e6bc0Shuangdaode #define DSAF_SRAM_INIT_OVER_0_REG 0x0 118511e6bc0Shuangdaode #define DSAF_CFG_0_REG 0x4 119511e6bc0Shuangdaode #define DSAF_ECC_ERR_INVERT_0_REG 0x8 120511e6bc0Shuangdaode #define DSAF_ABNORMAL_TIMEOUT_0_REG 0x1C 121511e6bc0Shuangdaode #define DSAF_FSM_TIMEOUT_0_REG 0x20 122511e6bc0Shuangdaode #define DSAF_DSA_REG_CNT_CLR_CE_REG 0x2C 123511e6bc0Shuangdaode #define DSAF_DSA_SBM_INF_FIFO_THRD_REG 0x30 124511e6bc0Shuangdaode #define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG 0x34 125511e6bc0Shuangdaode #define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG 0x38 126511e6bc0Shuangdaode #define DSAF_PFC_EN_0_REG 0x50 127511e6bc0Shuangdaode #define DSAF_PFC_UNIT_CNT_0_REG 0x70 128511e6bc0Shuangdaode #define DSAF_XGE_INT_MSK_0_REG 0x100 129511e6bc0Shuangdaode #define DSAF_PPE_INT_MSK_0_REG 0x120 130511e6bc0Shuangdaode #define DSAF_ROCEE_INT_MSK_0_REG 0x140 131511e6bc0Shuangdaode #define DSAF_XGE_INT_SRC_0_REG 0x160 132511e6bc0Shuangdaode #define DSAF_PPE_INT_SRC_0_REG 0x180 133511e6bc0Shuangdaode #define DSAF_ROCEE_INT_SRC_0_REG 0x1A0 134511e6bc0Shuangdaode #define DSAF_XGE_INT_STS_0_REG 0x1C0 135511e6bc0Shuangdaode #define DSAF_PPE_INT_STS_0_REG 0x1E0 136511e6bc0Shuangdaode #define DSAF_ROCEE_INT_STS_0_REG 0x200 137511e6bc0Shuangdaode #define DSAF_PPE_QID_CFG_0_REG 0x300 138511e6bc0Shuangdaode #define DSAF_SW_PORT_TYPE_0_REG 0x320 139511e6bc0Shuangdaode #define DSAF_STP_PORT_TYPE_0_REG 0x340 140511e6bc0Shuangdaode #define DSAF_MIX_DEF_QID_0_REG 0x360 141511e6bc0Shuangdaode #define DSAF_PORT_DEF_VLAN_0_REG 0x380 142511e6bc0Shuangdaode #define DSAF_VM_DEF_VLAN_0_REG 0x400 143511e6bc0Shuangdaode 144511e6bc0Shuangdaode #define DSAF_INODE_CUT_THROUGH_CFG_0_REG 0x1000 145511e6bc0Shuangdaode #define DSAF_INODE_ECC_INVERT_EN_0_REG 0x1008 146511e6bc0Shuangdaode #define DSAF_INODE_ECC_ERR_ADDR_0_REG 0x100C 147511e6bc0Shuangdaode #define DSAF_INODE_IN_PORT_NUM_0_REG 0x1018 148511e6bc0Shuangdaode #define DSAF_INODE_PRI_TC_CFG_0_REG 0x101C 149511e6bc0Shuangdaode #define DSAF_INODE_BP_STATUS_0_REG 0x1020 150511e6bc0Shuangdaode #define DSAF_INODE_PAD_DISCARD_NUM_0_REG 0x1028 151511e6bc0Shuangdaode #define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG 0x102C 152511e6bc0Shuangdaode #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG 0x1030 153511e6bc0Shuangdaode #define DSAF_INODE_SBM_PID_NUM_0_REG 0x1038 154511e6bc0Shuangdaode #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x103C 155511e6bc0Shuangdaode #define DSAF_INODE_SBM_RELS_NUM_0_REG 0x104C 156511e6bc0Shuangdaode #define DSAF_INODE_SBM_DROP_NUM_0_REG 0x1050 157511e6bc0Shuangdaode #define DSAF_INODE_CRC_FALSE_NUM_0_REG 0x1054 158511e6bc0Shuangdaode #define DSAF_INODE_BP_DISCARD_NUM_0_REG 0x1058 159511e6bc0Shuangdaode #define DSAF_INODE_RSLT_DISCARD_NUM_0_REG 0x105C 160511e6bc0Shuangdaode #define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG 0x1060 161511e6bc0Shuangdaode #define DSAF_INODE_VOQ_OVER_NUM_0_REG 0x1068 162511e6bc0Shuangdaode #define DSAF_INODE_BD_SAVE_STATUS_0_REG 0x1900 163511e6bc0Shuangdaode #define DSAF_INODE_BD_ORDER_STATUS_0_REG 0x1950 164511e6bc0Shuangdaode #define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG 0x1A00 165511e6bc0Shuangdaode #define DSAF_INODE_IN_DATA_STP_DISC_0_REG 0x1A50 166511e6bc0Shuangdaode #define DSAF_INODE_GE_FC_EN_0_REG 0x1B00 167511e6bc0Shuangdaode #define DSAF_INODE_VC0_IN_PKT_NUM_0_REG 0x1B50 168511e6bc0Shuangdaode #define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x1C00 169511e6bc0Shuangdaode 170511e6bc0Shuangdaode #define DSAF_SBM_CFG_REG_0_REG 0x2000 171511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG 0x2004 172511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG 0x2304 173511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG 0x2604 174511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_1_REG_0_REG 0x2008 175511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG 0x200C 176511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG 0x230C 177511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x260C 17813ac695eSSalil #define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x238C 179511e6bc0Shuangdaode #define DSAF_SBM_FREE_CNT_0_0_REG 0x2010 180511e6bc0Shuangdaode #define DSAF_SBM_FREE_CNT_1_0_REG 0x2014 181511e6bc0Shuangdaode #define DSAF_SBM_BP_CNT_0_0_REG 0x2018 182511e6bc0Shuangdaode #define DSAF_SBM_BP_CNT_1_0_REG 0x201C 183511e6bc0Shuangdaode #define DSAF_SBM_BP_CNT_2_0_REG 0x2020 184511e6bc0Shuangdaode #define DSAF_SBM_BP_CNT_3_0_REG 0x2024 185511e6bc0Shuangdaode #define DSAF_SBM_INER_ST_0_REG 0x2028 186511e6bc0Shuangdaode #define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG 0x202C 187511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_CNT_0_REG 0x2030 188511e6bc0Shuangdaode #define DSAF_SBM_LNK_DROP_CNT_0_REG 0x2034 189511e6bc0Shuangdaode #define DSAF_SBM_INF_OUTPORT_CNT_0_REG 0x2038 190511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG 0x203C 191511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG 0x2040 192511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG 0x2044 193511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG 0x2048 194511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG 0x204C 195511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG 0x2050 196511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG 0x2054 197511e6bc0Shuangdaode #define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG 0x2058 198511e6bc0Shuangdaode #define DSAF_SBM_LNK_REQ_CNT_0_REG 0x205C 199511e6bc0Shuangdaode #define DSAF_SBM_LNK_RELS_CNT_0_REG 0x2060 200511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_3_REG_0_REG 0x2068 201511e6bc0Shuangdaode #define DSAF_SBM_BP_CFG_4_REG_0_REG 0x206C 202511e6bc0Shuangdaode 203511e6bc0Shuangdaode #define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG 0x3000 204511e6bc0Shuangdaode #define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG 0x3004 205511e6bc0Shuangdaode #define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG 0x3008 206511e6bc0Shuangdaode #define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG 0x300C 207511e6bc0Shuangdaode #define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG 0x3010 208511e6bc0Shuangdaode #define DSAF_XOD_ETS_TOKEN_CFG_0_REG 0x3014 209511e6bc0Shuangdaode #define DSAF_XOD_PFS_CFG_0_0_REG 0x3018 210511e6bc0Shuangdaode #define DSAF_XOD_PFS_CFG_1_0_REG 0x301C 211511e6bc0Shuangdaode #define DSAF_XOD_PFS_CFG_2_0_REG 0x3020 212511e6bc0Shuangdaode #define DSAF_XOD_GNT_L_0_REG 0x3024 213511e6bc0Shuangdaode #define DSAF_XOD_GNT_H_0_REG 0x3028 214511e6bc0Shuangdaode #define DSAF_XOD_CONNECT_STATE_0_REG 0x302C 215511e6bc0Shuangdaode #define DSAF_XOD_RCVPKT_CNT_0_REG 0x3030 216511e6bc0Shuangdaode #define DSAF_XOD_RCVTC0_CNT_0_REG 0x3034 217511e6bc0Shuangdaode #define DSAF_XOD_RCVTC1_CNT_0_REG 0x3038 218511e6bc0Shuangdaode #define DSAF_XOD_RCVTC2_CNT_0_REG 0x303C 219511e6bc0Shuangdaode #define DSAF_XOD_RCVTC3_CNT_0_REG 0x3040 220511e6bc0Shuangdaode #define DSAF_XOD_RCVVC0_CNT_0_REG 0x3044 221511e6bc0Shuangdaode #define DSAF_XOD_RCVVC1_CNT_0_REG 0x3048 222511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN0_CNT_0_REG 0x304C 223511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN1_CNT_0_REG 0x3050 224511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN2_CNT_0_REG 0x3054 225511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN3_CNT_0_REG 0x3058 226511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN4_CNT_0_REG 0x305C 227511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN5_CNT_0_REG 0x3060 228511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN6_CNT_0_REG 0x3064 229511e6bc0Shuangdaode #define DSAF_XOD_XGE_RCVIN7_CNT_0_REG 0x3068 230511e6bc0Shuangdaode #define DSAF_XOD_PPE_RCVIN0_CNT_0_REG 0x306C 231511e6bc0Shuangdaode #define DSAF_XOD_PPE_RCVIN1_CNT_0_REG 0x3070 232511e6bc0Shuangdaode #define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG 0x3074 233511e6bc0Shuangdaode #define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG 0x3078 234511e6bc0Shuangdaode #define DSAF_XOD_FIFO_STATUS_0_REG 0x307C 235511e6bc0Shuangdaode 236511e6bc0Shuangdaode #define DSAF_VOQ_ECC_INVERT_EN_0_REG 0x4004 237511e6bc0Shuangdaode #define DSAF_VOQ_SRAM_PKT_NUM_0_REG 0x4008 238511e6bc0Shuangdaode #define DSAF_VOQ_IN_PKT_NUM_0_REG 0x400C 239511e6bc0Shuangdaode #define DSAF_VOQ_OUT_PKT_NUM_0_REG 0x4010 240511e6bc0Shuangdaode #define DSAF_VOQ_ECC_ERR_ADDR_0_REG 0x4014 241511e6bc0Shuangdaode #define DSAF_VOQ_BP_STATUS_0_REG 0x4018 242511e6bc0Shuangdaode #define DSAF_VOQ_SPUP_IDLE_0_REG 0x401C 243511e6bc0Shuangdaode #define DSAF_VOQ_XGE_XOD_REQ_0_0_REG 0x4024 244511e6bc0Shuangdaode #define DSAF_VOQ_XGE_XOD_REQ_1_0_REG 0x4028 245511e6bc0Shuangdaode #define DSAF_VOQ_PPE_XOD_REQ_0_REG 0x402C 246511e6bc0Shuangdaode #define DSAF_VOQ_ROCEE_XOD_REQ_0_REG 0x4030 247511e6bc0Shuangdaode #define DSAF_VOQ_BP_ALL_THRD_0_REG 0x4034 248511e6bc0Shuangdaode 249511e6bc0Shuangdaode #define DSAF_TBL_CTRL_0_REG 0x5000 250511e6bc0Shuangdaode #define DSAF_TBL_INT_MSK_0_REG 0x5004 251511e6bc0Shuangdaode #define DSAF_TBL_INT_SRC_0_REG 0x5008 252511e6bc0Shuangdaode #define DSAF_TBL_INT_STS_0_REG 0x5100 253511e6bc0Shuangdaode #define DSAF_TBL_TCAM_ADDR_0_REG 0x500C 254511e6bc0Shuangdaode #define DSAF_TBL_LINE_ADDR_0_REG 0x5010 255511e6bc0Shuangdaode #define DSAF_TBL_TCAM_HIGH_0_REG 0x5014 256511e6bc0Shuangdaode #define DSAF_TBL_TCAM_LOW_0_REG 0x5018 257511e6bc0Shuangdaode #define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG 0x501C 258511e6bc0Shuangdaode #define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG 0x5020 259511e6bc0Shuangdaode #define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG 0x5024 260511e6bc0Shuangdaode #define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG 0x5028 261511e6bc0Shuangdaode #define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG 0x502C 262511e6bc0Shuangdaode #define DSAF_TBL_TCAM_UCAST_CFG_0_REG 0x5030 263511e6bc0Shuangdaode #define DSAF_TBL_LIN_CFG_0_REG 0x5034 264511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RDATA_HIGH_0_REG 0x5038 265511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RDATA_LOW_0_REG 0x503C 266511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RAM_RDATA4_0_REG 0x5040 267511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RAM_RDATA3_0_REG 0x5044 268511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RAM_RDATA2_0_REG 0x5048 269511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RAM_RDATA1_0_REG 0x504C 270511e6bc0Shuangdaode #define DSAF_TBL_TCAM_RAM_RDATA0_0_REG 0x5050 271511e6bc0Shuangdaode #define DSAF_TBL_LIN_RDATA_0_REG 0x5054 272511e6bc0Shuangdaode #define DSAF_TBL_DA0_MIS_INFO1_0_REG 0x5058 273511e6bc0Shuangdaode #define DSAF_TBL_DA0_MIS_INFO0_0_REG 0x505C 274511e6bc0Shuangdaode #define DSAF_TBL_SA_MIS_INFO2_0_REG 0x5104 275511e6bc0Shuangdaode #define DSAF_TBL_SA_MIS_INFO1_0_REG 0x5098 276511e6bc0Shuangdaode #define DSAF_TBL_SA_MIS_INFO0_0_REG 0x509C 277511e6bc0Shuangdaode #define DSAF_TBL_PUL_0_REG 0x50A0 278511e6bc0Shuangdaode #define DSAF_TBL_OLD_RSLT_0_REG 0x50A4 279511e6bc0Shuangdaode #define DSAF_TBL_OLD_SCAN_VAL_0_REG 0x50A8 280511e6bc0Shuangdaode #define DSAF_TBL_DFX_CTRL_0_REG 0x50AC 281511e6bc0Shuangdaode #define DSAF_TBL_DFX_STAT_0_REG 0x50B0 282511e6bc0Shuangdaode #define DSAF_TBL_DFX_STAT_2_0_REG 0x5108 283511e6bc0Shuangdaode #define DSAF_TBL_LKUP_NUM_I_0_REG 0x50C0 284511e6bc0Shuangdaode #define DSAF_TBL_LKUP_NUM_O_0_REG 0x50E0 285511e6bc0Shuangdaode #define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG 0x510C 286511e6bc0Shuangdaode 287511e6bc0Shuangdaode #define DSAF_INODE_FIFO_WL_0_REG 0x6000 288511e6bc0Shuangdaode #define DSAF_ONODE_FIFO_WL_0_REG 0x6020 289511e6bc0Shuangdaode #define DSAF_XGE_GE_WORK_MODE_0_REG 0x6040 290511e6bc0Shuangdaode #define DSAF_XGE_APP_RX_LINK_UP_0_REG 0x6080 291511e6bc0Shuangdaode #define DSAF_NETPORT_CTRL_SIG_0_REG 0x60A0 292511e6bc0Shuangdaode #define DSAF_XGE_CTRL_SIG_CFG_0_REG 0x60C0 293511e6bc0Shuangdaode 294511e6bc0Shuangdaode #define PPE_COM_CFG_QID_MODE_REG 0x0 295511e6bc0Shuangdaode #define PPE_COM_INTEN_REG 0x110 296511e6bc0Shuangdaode #define PPE_COM_RINT_REG 0x114 297511e6bc0Shuangdaode #define PPE_COM_INTSTS_REG 0x118 298511e6bc0Shuangdaode #define PPE_COM_COMMON_CNT_CLR_CE_REG 0x1120 299511e6bc0Shuangdaode #define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG 0x300 300511e6bc0Shuangdaode #define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG 0x600 301511e6bc0Shuangdaode #define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG 0x900 302511e6bc0Shuangdaode #define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG 0xC00 303511e6bc0Shuangdaode #define PPE_COM_COMMON_CNT_CLR_CE_REG 0x1120 304511e6bc0Shuangdaode 305511e6bc0Shuangdaode #define PPE_CFG_TX_FIFO_THRSLD_REG 0x0 306511e6bc0Shuangdaode #define PPE_CFG_RX_FIFO_THRSLD_REG 0x4 307511e6bc0Shuangdaode #define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG 0x8 308511e6bc0Shuangdaode #define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG 0xC 309511e6bc0Shuangdaode #define PPE_CFG_PAUSE_IDLE_CNT_REG 0x10 310511e6bc0Shuangdaode #define PPE_CFG_BUS_CTRL_REG 0x40 311511e6bc0Shuangdaode #define PPE_CFG_TNL_TO_BE_RST_REG 0x48 312511e6bc0Shuangdaode #define PPE_CURR_TNL_CAN_RST_REG 0x4C 313511e6bc0Shuangdaode #define PPE_CFG_XGE_MODE_REG 0x80 314511e6bc0Shuangdaode #define PPE_CFG_MAX_FRAME_LEN_REG 0x84 315511e6bc0Shuangdaode #define PPE_CFG_RX_PKT_MODE_REG 0x88 316511e6bc0Shuangdaode #define PPE_CFG_RX_VLAN_TAG_REG 0x8C 317511e6bc0Shuangdaode #define PPE_CFG_TAG_GEN_REG 0x90 318511e6bc0Shuangdaode #define PPE_CFG_PARSE_TAG_REG 0x94 319511e6bc0Shuangdaode #define PPE_CFG_PRO_CHECK_EN_REG 0x98 32064353af6SSalil #define PPEV2_CFG_TSO_EN_REG 0xA0 3218044f97eSSalil #define PPEV2_VLAN_STRIP_EN_REG 0xAC 322511e6bc0Shuangdaode #define PPE_INTEN_REG 0x100 323511e6bc0Shuangdaode #define PPE_RINT_REG 0x104 324511e6bc0Shuangdaode #define PPE_INTSTS_REG 0x108 325511e6bc0Shuangdaode #define PPE_CFG_RX_PKT_INT_REG 0x140 326511e6bc0Shuangdaode #define PPE_CFG_HEAT_DECT_TIME0_REG 0x144 327511e6bc0Shuangdaode #define PPE_CFG_HEAT_DECT_TIME1_REG 0x148 328511e6bc0Shuangdaode #define PPE_HIS_RX_SW_PKT_CNT_REG 0x200 329511e6bc0Shuangdaode #define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG 0x204 330511e6bc0Shuangdaode #define PPE_HIS_RX_PKT_NO_BUF_CNT_REG 0x208 331511e6bc0Shuangdaode #define PPE_HIS_TX_BD_CNT_REG 0x20C 332511e6bc0Shuangdaode #define PPE_HIS_TX_PKT_CNT_REG 0x210 333511e6bc0Shuangdaode #define PPE_HIS_TX_PKT_OK_CNT_REG 0x214 334511e6bc0Shuangdaode #define PPE_HIS_TX_PKT_EPT_CNT_REG 0x218 335511e6bc0Shuangdaode #define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG 0x21C 336511e6bc0Shuangdaode #define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG 0x220 337511e6bc0Shuangdaode #define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG 0x224 338511e6bc0Shuangdaode #define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG 0x228 339511e6bc0Shuangdaode #define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG 0x22C 340511e6bc0Shuangdaode #define PPE_TNL_0_5_CNT_CLR_CE_REG 0x300 341511e6bc0Shuangdaode #define PPE_CFG_AXI_DBG_REG 0x304 342511e6bc0Shuangdaode #define PPE_HIS_PRO_ERR_REG 0x308 343511e6bc0Shuangdaode #define PPE_HIS_TNL_FIFO_ERR_REG 0x30C 344511e6bc0Shuangdaode #define PPE_CURR_CFF_DATA_NUM_REG 0x310 345511e6bc0Shuangdaode #define PPE_CURR_RX_ST_REG 0x314 346511e6bc0Shuangdaode #define PPE_CURR_TX_ST_REG 0x318 347511e6bc0Shuangdaode #define PPE_CURR_RX_FIFO0_REG 0x31C 348511e6bc0Shuangdaode #define PPE_CURR_RX_FIFO1_REG 0x320 349511e6bc0Shuangdaode #define PPE_CURR_TX_FIFO0_REG 0x324 350511e6bc0Shuangdaode #define PPE_CURR_TX_FIFO1_REG 0x328 351511e6bc0Shuangdaode #define PPE_ECO0_REG 0x32C 352511e6bc0Shuangdaode #define PPE_ECO1_REG 0x330 353511e6bc0Shuangdaode #define PPE_ECO2_REG 0x334 3546bc0ce7dSSalil #define PPEV2_INDRECTION_TBL_REG 0x800 3556bc0ce7dSSalil #define PPEV2_RSS_KEY_REG 0x900 356511e6bc0Shuangdaode 357511e6bc0Shuangdaode #define RCB_COM_CFG_ENDIAN_REG 0x0 358511e6bc0Shuangdaode #define RCB_COM_CFG_SYS_FSH_REG 0xC 359511e6bc0Shuangdaode #define RCB_COM_CFG_INIT_FLAG_REG 0x10 360511e6bc0Shuangdaode #define RCB_COM_CFG_PKT_REG 0x30 361511e6bc0Shuangdaode #define RCB_COM_CFG_RINVLD_REG 0x34 362511e6bc0Shuangdaode #define RCB_COM_CFG_FNA_REG 0x38 363511e6bc0Shuangdaode #define RCB_COM_CFG_FA_REG 0x3C 364511e6bc0Shuangdaode #define RCB_COM_CFG_PKT_TC_BP_REG 0x40 365511e6bc0Shuangdaode #define RCB_COM_CFG_PPE_TNL_CLKEN_REG 0x44 366511e6bc0Shuangdaode 367511e6bc0Shuangdaode #define RCB_COM_INTMSK_TX_PKT_REG 0x3A0 368511e6bc0Shuangdaode #define RCB_COM_RINT_TX_PKT_REG 0x3A8 369511e6bc0Shuangdaode #define RCB_COM_INTMASK_ECC_ERR_REG 0x400 370511e6bc0Shuangdaode #define RCB_COM_INTSTS_ECC_ERR_REG 0x408 371511e6bc0Shuangdaode #define RCB_COM_EBD_SRAM_ERR_REG 0x410 372511e6bc0Shuangdaode #define RCB_COM_RXRING_ERR_REG 0x41C 373511e6bc0Shuangdaode #define RCB_COM_TXRING_ERR_REG 0x420 374511e6bc0Shuangdaode #define RCB_COM_TX_FBD_ERR_REG 0x424 375511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK_EN_REG 0x428 376511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK0_REG 0x42C 377511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK1_REG 0x430 378511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK2_REG 0x434 379511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK3_REG 0x438 380511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK4_REG 0x43c 381511e6bc0Shuangdaode #define RCB_SRAM_ECC_CHK5_REG 0x440 382511e6bc0Shuangdaode #define RCB_ECC_ERR_ADDR0_REG 0x450 383511e6bc0Shuangdaode #define RCB_ECC_ERR_ADDR3_REG 0x45C 384511e6bc0Shuangdaode #define RCB_ECC_ERR_ADDR4_REG 0x460 385511e6bc0Shuangdaode #define RCB_ECC_ERR_ADDR5_REG 0x464 386511e6bc0Shuangdaode 387511e6bc0Shuangdaode #define RCB_COM_SF_CFG_INTMASK_RING 0x480 388511e6bc0Shuangdaode #define RCB_COM_SF_CFG_RING_STS 0x484 389511e6bc0Shuangdaode #define RCB_COM_SF_CFG_RING 0x488 390511e6bc0Shuangdaode #define RCB_COM_SF_CFG_INTMASK_BD 0x48C 391511e6bc0Shuangdaode #define RCB_COM_SF_CFG_BD_RINT_STS 0x470 392511e6bc0Shuangdaode #define RCB_COM_RCB_RD_BD_BUSY 0x490 393511e6bc0Shuangdaode #define RCB_COM_RCB_FBD_CRT_EN 0x494 394511e6bc0Shuangdaode #define RCB_COM_AXI_WR_ERR_INTMASK 0x498 395511e6bc0Shuangdaode #define RCB_COM_AXI_ERR_STS 0x49C 396511e6bc0Shuangdaode #define RCB_COM_CHK_TX_FBD_NUM_REG 0x4a0 397511e6bc0Shuangdaode 398511e6bc0Shuangdaode #define RCB_CFG_BD_NUM_REG 0x9000 399511e6bc0Shuangdaode #define RCB_CFG_PKTLINE_REG 0x9050 400511e6bc0Shuangdaode 401511e6bc0Shuangdaode #define RCB_CFG_OVERTIME_REG 0x9300 402511e6bc0Shuangdaode #define RCB_CFG_PKTLINE_INT_NUM_REG 0x9304 403511e6bc0Shuangdaode #define RCB_CFG_OVERTIME_INT_NUM_REG 0x9308 404511e6bc0Shuangdaode 405511e6bc0Shuangdaode #define RCB_RING_RX_RING_BASEADDR_L_REG 0x00000 406511e6bc0Shuangdaode #define RCB_RING_RX_RING_BASEADDR_H_REG 0x00004 407511e6bc0Shuangdaode #define RCB_RING_RX_RING_BD_NUM_REG 0x00008 408511e6bc0Shuangdaode #define RCB_RING_RX_RING_BD_LEN_REG 0x0000C 409511e6bc0Shuangdaode #define RCB_RING_RX_RING_PKTLINE_REG 0x00010 410511e6bc0Shuangdaode #define RCB_RING_RX_RING_TAIL_REG 0x00018 411511e6bc0Shuangdaode #define RCB_RING_RX_RING_HEAD_REG 0x0001C 412511e6bc0Shuangdaode #define RCB_RING_RX_RING_FBDNUM_REG 0x00020 413511e6bc0Shuangdaode #define RCB_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 414511e6bc0Shuangdaode 415511e6bc0Shuangdaode #define RCB_RING_TX_RING_BASEADDR_L_REG 0x00040 416511e6bc0Shuangdaode #define RCB_RING_TX_RING_BASEADDR_H_REG 0x00044 417511e6bc0Shuangdaode #define RCB_RING_TX_RING_BD_NUM_REG 0x00048 418511e6bc0Shuangdaode #define RCB_RING_TX_RING_BD_LEN_REG 0x0004C 419511e6bc0Shuangdaode #define RCB_RING_TX_RING_PKTLINE_REG 0x00050 420511e6bc0Shuangdaode #define RCB_RING_TX_RING_TAIL_REG 0x00058 421511e6bc0Shuangdaode #define RCB_RING_TX_RING_HEAD_REG 0x0005C 422511e6bc0Shuangdaode #define RCB_RING_TX_RING_FBDNUM_REG 0x00060 423511e6bc0Shuangdaode #define RCB_RING_TX_RING_OFFSET_REG 0x00064 424511e6bc0Shuangdaode #define RCB_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 425511e6bc0Shuangdaode 426511e6bc0Shuangdaode #define RCB_RING_PREFETCH_EN_REG 0x0007C 427511e6bc0Shuangdaode #define RCB_RING_CFG_VF_NUM_REG 0x00080 428511e6bc0Shuangdaode #define RCB_RING_ASID_REG 0x0008C 429511e6bc0Shuangdaode #define RCB_RING_RX_VM_REG 0x00090 430511e6bc0Shuangdaode #define RCB_RING_T0_BE_RST 0x00094 431511e6bc0Shuangdaode #define RCB_RING_COULD_BE_RST 0x00098 432511e6bc0Shuangdaode #define RCB_RING_WRR_WEIGHT_REG 0x0009c 433511e6bc0Shuangdaode 434511e6bc0Shuangdaode #define RCB_RING_INTMSK_RXWL_REG 0x000A0 435511e6bc0Shuangdaode #define RCB_RING_INTSTS_RX_RING_REG 0x000A4 43613ac695eSSalil #define RCBV2_RX_RING_INT_STS_REG 0x000A8 437511e6bc0Shuangdaode #define RCB_RING_INTMSK_TXWL_REG 0x000AC 438511e6bc0Shuangdaode #define RCB_RING_INTSTS_TX_RING_REG 0x000B0 43913ac695eSSalil #define RCBV2_TX_RING_INT_STS_REG 0x000B4 440511e6bc0Shuangdaode #define RCB_RING_INTMSK_RX_OVERTIME_REG 0x000B8 441511e6bc0Shuangdaode #define RCB_RING_INTSTS_RX_OVERTIME_REG 0x000BC 442511e6bc0Shuangdaode #define RCB_RING_INTMSK_TX_OVERTIME_REG 0x000C4 443511e6bc0Shuangdaode #define RCB_RING_INTSTS_TX_OVERTIME_REG 0x000C8 444511e6bc0Shuangdaode 445511e6bc0Shuangdaode #define GMAC_DUPLEX_TYPE_REG 0x0008UL 446511e6bc0Shuangdaode #define GMAC_FD_FC_TYPE_REG 0x000CUL 447511e6bc0Shuangdaode #define GMAC_FC_TX_TIMER_REG 0x001CUL 448511e6bc0Shuangdaode #define GMAC_FD_FC_ADDR_LOW_REG 0x0020UL 449511e6bc0Shuangdaode #define GMAC_FD_FC_ADDR_HIGH_REG 0x0024UL 450511e6bc0Shuangdaode #define GMAC_IPG_TX_TIMER_REG 0x0030UL 451511e6bc0Shuangdaode #define GMAC_PAUSE_THR_REG 0x0038UL 452511e6bc0Shuangdaode #define GMAC_MAX_FRM_SIZE_REG 0x003CUL 453511e6bc0Shuangdaode #define GMAC_PORT_MODE_REG 0x0040UL 454511e6bc0Shuangdaode #define GMAC_PORT_EN_REG 0x0044UL 455511e6bc0Shuangdaode #define GMAC_PAUSE_EN_REG 0x0048UL 456511e6bc0Shuangdaode #define GMAC_SHORT_RUNTS_THR_REG 0x0050UL 457511e6bc0Shuangdaode #define GMAC_AN_NEG_STATE_REG 0x0058UL 458511e6bc0Shuangdaode #define GMAC_TX_LOCAL_PAGE_REG 0x005CUL 459511e6bc0Shuangdaode #define GMAC_TRANSMIT_CONTROL_REG 0x0060UL 460511e6bc0Shuangdaode #define GMAC_REC_FILT_CONTROL_REG 0x0064UL 461511e6bc0Shuangdaode #define GMAC_PTP_CONFIG_REG 0x0074UL 462511e6bc0Shuangdaode 463511e6bc0Shuangdaode #define GMAC_RX_OCTETS_TOTAL_OK_REG 0x0080UL 464511e6bc0Shuangdaode #define GMAC_RX_OCTETS_BAD_REG 0x0084UL 465511e6bc0Shuangdaode #define GMAC_RX_UC_PKTS_REG 0x0088UL 466511e6bc0Shuangdaode #define GMAC_RX_MC_PKTS_REG 0x008CUL 467511e6bc0Shuangdaode #define GMAC_RX_BC_PKTS_REG 0x0090UL 468511e6bc0Shuangdaode #define GMAC_RX_PKTS_64OCTETS_REG 0x0094UL 469511e6bc0Shuangdaode #define GMAC_RX_PKTS_65TO127OCTETS_REG 0x0098UL 470511e6bc0Shuangdaode #define GMAC_RX_PKTS_128TO255OCTETS_REG 0x009CUL 471511e6bc0Shuangdaode #define GMAC_RX_PKTS_255TO511OCTETS_REG 0x00A0UL 472511e6bc0Shuangdaode #define GMAC_RX_PKTS_512TO1023OCTETS_REG 0x00A4UL 473511e6bc0Shuangdaode #define GMAC_RX_PKTS_1024TO1518OCTETS_REG 0x00A8UL 474511e6bc0Shuangdaode #define GMAC_RX_PKTS_1519TOMAXOCTETS_REG 0x00ACUL 475511e6bc0Shuangdaode #define GMAC_RX_FCS_ERRORS_REG 0x00B0UL 476511e6bc0Shuangdaode #define GMAC_RX_TAGGED_REG 0x00B4UL 477511e6bc0Shuangdaode #define GMAC_RX_DATA_ERR_REG 0x00B8UL 478511e6bc0Shuangdaode #define GMAC_RX_ALIGN_ERRORS_REG 0x00BCUL 479511e6bc0Shuangdaode #define GMAC_RX_LONG_ERRORS_REG 0x00C0UL 480511e6bc0Shuangdaode #define GMAC_RX_JABBER_ERRORS_REG 0x00C4UL 481511e6bc0Shuangdaode #define GMAC_RX_PAUSE_MACCTRL_FRAM_REG 0x00C8UL 482511e6bc0Shuangdaode #define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG 0x00CCUL 483511e6bc0Shuangdaode #define GMAC_RX_VERY_LONG_ERR_CNT_REG 0x00D0UL 484511e6bc0Shuangdaode #define GMAC_RX_RUNT_ERR_CNT_REG 0x00D4UL 485511e6bc0Shuangdaode #define GMAC_RX_SHORT_ERR_CNT_REG 0x00D8UL 486511e6bc0Shuangdaode #define GMAC_RX_FILT_PKT_CNT_REG 0x00E8UL 487511e6bc0Shuangdaode #define GMAC_RX_OCTETS_TOTAL_FILT_REG 0x00ECUL 488511e6bc0Shuangdaode #define GMAC_OCTETS_TRANSMITTED_OK_REG 0x0100UL 489511e6bc0Shuangdaode #define GMAC_OCTETS_TRANSMITTED_BAD_REG 0x0104UL 490511e6bc0Shuangdaode #define GMAC_TX_UC_PKTS_REG 0x0108UL 491511e6bc0Shuangdaode #define GMAC_TX_MC_PKTS_REG 0x010CUL 492511e6bc0Shuangdaode #define GMAC_TX_BC_PKTS_REG 0x0110UL 493511e6bc0Shuangdaode #define GMAC_TX_PKTS_64OCTETS_REG 0x0114UL 494511e6bc0Shuangdaode #define GMAC_TX_PKTS_65TO127OCTETS_REG 0x0118UL 495511e6bc0Shuangdaode #define GMAC_TX_PKTS_128TO255OCTETS_REG 0x011CUL 496511e6bc0Shuangdaode #define GMAC_TX_PKTS_255TO511OCTETS_REG 0x0120UL 497511e6bc0Shuangdaode #define GMAC_TX_PKTS_512TO1023OCTETS_REG 0x0124UL 498511e6bc0Shuangdaode #define GMAC_TX_PKTS_1024TO1518OCTETS_REG 0x0128UL 499511e6bc0Shuangdaode #define GMAC_TX_PKTS_1519TOMAXOCTETS_REG 0x012CUL 500511e6bc0Shuangdaode #define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG 0x014CUL 501511e6bc0Shuangdaode #define GMAC_TX_UNDERRUN_REG 0x0150UL 502511e6bc0Shuangdaode #define GMAC_TX_TAGGED_REG 0x0154UL 503511e6bc0Shuangdaode #define GMAC_TX_CRC_ERROR_REG 0x0158UL 504511e6bc0Shuangdaode #define GMAC_TX_PAUSE_FRAMES_REG 0x015CUL 505511e6bc0Shuangdaode #define GAMC_RX_MAX_FRAME 0x0170UL 506511e6bc0Shuangdaode #define GMAC_LINE_LOOP_BACK_REG 0x01A8UL 507511e6bc0Shuangdaode #define GMAC_CF_CRC_STRIP_REG 0x01B0UL 508511e6bc0Shuangdaode #define GMAC_MODE_CHANGE_EN_REG 0x01B4UL 509511e6bc0Shuangdaode #define GMAC_SIXTEEN_BIT_CNTR_REG 0x01CCUL 510511e6bc0Shuangdaode #define GMAC_LD_LINK_COUNTER_REG 0x01D0UL 511511e6bc0Shuangdaode #define GMAC_LOOP_REG 0x01DCUL 512511e6bc0Shuangdaode #define GMAC_RECV_CONTROL_REG 0x01E0UL 513511e6bc0Shuangdaode #define GMAC_VLAN_CODE_REG 0x01E8UL 514511e6bc0Shuangdaode #define GMAC_RX_OVERRUN_CNT_REG 0x01ECUL 515511e6bc0Shuangdaode #define GMAC_RX_LENGTHFIELD_ERR_CNT_REG 0x01F4UL 516511e6bc0Shuangdaode #define GMAC_RX_FAIL_COMMA_CNT_REG 0x01F8UL 517511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_0_REG 0x0200UL 518511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_0_REG 0x0204UL 519511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_1_REG 0x0208UL 520511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_1_REG 0x020CUL 521511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_2_REG 0x0210UL 522511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_2_REG 0x0214UL 523511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_3_REG 0x0218UL 524511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_3_REG 0x021CUL 525511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_4_REG 0x0220UL 526511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_4_REG 0x0224UL 527511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_5_REG 0x0228UL 528511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_5_REG 0x022CUL 529511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_MSK_0_REG 0x0230UL 530511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_MSK_0_REG 0x0234UL 531511e6bc0Shuangdaode #define GMAC_STATION_ADDR_LOW_MSK_1_REG 0x0238UL 532511e6bc0Shuangdaode #define GMAC_STATION_ADDR_HIGH_MSK_1_REG 0x023CUL 533511e6bc0Shuangdaode #define GMAC_MAC_SKIP_LEN_REG 0x0240UL 534511e6bc0Shuangdaode #define GMAC_TX_LOOP_PKT_PRI_REG 0x0378UL 535511e6bc0Shuangdaode 536511e6bc0Shuangdaode #define XGMAC_INT_STATUS_REG 0x0 537511e6bc0Shuangdaode #define XGMAC_INT_ENABLE_REG 0x4 538511e6bc0Shuangdaode #define XGMAC_INT_SET_REG 0x8 539511e6bc0Shuangdaode #define XGMAC_IERR_U_INFO_REG 0xC 540511e6bc0Shuangdaode #define XGMAC_OVF_INFO_REG 0x10 541511e6bc0Shuangdaode #define XGMAC_OVF_CNT_REG 0x14 542511e6bc0Shuangdaode #define XGMAC_PORT_MODE_REG 0x40 543511e6bc0Shuangdaode #define XGMAC_CLK_ENABLE_REG 0x44 544511e6bc0Shuangdaode #define XGMAC_RESET_REG 0x48 545511e6bc0Shuangdaode #define XGMAC_LINK_CONTROL_REG 0x50 546511e6bc0Shuangdaode #define XGMAC_LINK_STATUS_REG 0x54 547511e6bc0Shuangdaode #define XGMAC_SPARE_REG 0xC0 548511e6bc0Shuangdaode #define XGMAC_SPARE_CNT_REG 0xC4 549511e6bc0Shuangdaode 550511e6bc0Shuangdaode #define XGMAC_MAC_ENABLE_REG 0x100 551511e6bc0Shuangdaode #define XGMAC_MAC_CONTROL_REG 0x104 552511e6bc0Shuangdaode #define XGMAC_MAC_IPG_REG 0x120 553511e6bc0Shuangdaode #define XGMAC_MAC_MSG_CRC_EN_REG 0x124 554511e6bc0Shuangdaode #define XGMAC_MAC_MSG_IMG_REG 0x128 555511e6bc0Shuangdaode #define XGMAC_MAC_MSG_FC_CFG_REG 0x12C 556511e6bc0Shuangdaode #define XGMAC_MAC_MSG_TC_CFG_REG 0x130 557511e6bc0Shuangdaode #define XGMAC_MAC_PAD_SIZE_REG 0x134 558511e6bc0Shuangdaode #define XGMAC_MAC_MIN_PKT_SIZE_REG 0x138 559511e6bc0Shuangdaode #define XGMAC_MAC_MAX_PKT_SIZE_REG 0x13C 560511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_CTRL_REG 0x160 561511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_TIME_REG 0x164 562511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_GAP_REG 0x168 563511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG 0x16C 564511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG 0x170 565511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_PEER_MAC_H_REG 0x174 566511e6bc0Shuangdaode #define XGMAC_MAC_PAUSE_PEER_MAC_L_REG 0x178 567511e6bc0Shuangdaode #define XGMAC_MAC_PFC_PRI_EN_REG 0x17C 568511e6bc0Shuangdaode #define XGMAC_MAC_1588_CTRL_REG 0x180 569511e6bc0Shuangdaode #define XGMAC_MAC_1588_TX_PORT_DLY_REG 0x184 570511e6bc0Shuangdaode #define XGMAC_MAC_1588_RX_PORT_DLY_REG 0x188 571511e6bc0Shuangdaode #define XGMAC_MAC_1588_ASYM_DLY_REG 0x18C 572511e6bc0Shuangdaode #define XGMAC_MAC_1588_ADJUST_CFG_REG 0x190 573511e6bc0Shuangdaode #define XGMAC_MAC_Y1731_ETH_TYPE_REG 0x194 574511e6bc0Shuangdaode #define XGMAC_MAC_MIB_CONTROL_REG 0x198 575511e6bc0Shuangdaode #define XGMAC_MAC_WAN_RATE_ADJUST_REG 0x19C 576511e6bc0Shuangdaode #define XGMAC_MAC_TX_ERR_MARK_REG 0x1A0 577511e6bc0Shuangdaode #define XGMAC_MAC_TX_LF_RF_CONTROL_REG 0x1A4 578511e6bc0Shuangdaode #define XGMAC_MAC_RX_LF_RF_STATUS_REG 0x1A8 579511e6bc0Shuangdaode #define XGMAC_MAC_TX_RUNT_PKT_CNT_REG 0x1C0 580511e6bc0Shuangdaode #define XGMAC_MAC_RX_RUNT_PKT_CNT_REG 0x1C4 581511e6bc0Shuangdaode #define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG 0x1C8 582511e6bc0Shuangdaode #define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG 0x1CC 583511e6bc0Shuangdaode #define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG 0x1D0 584511e6bc0Shuangdaode #define XGMAC_MAC_RX_ERR_MSG_CNT_REG 0x1D4 585511e6bc0Shuangdaode #define XGMAC_MAC_RX_ERR_EFD_CNT_REG 0x1D8 586511e6bc0Shuangdaode #define XGMAC_MAC_ERR_INFO_REG 0x1DC 587511e6bc0Shuangdaode #define XGMAC_MAC_DBG_INFO_REG 0x1E0 588511e6bc0Shuangdaode 589511e6bc0Shuangdaode #define XGMAC_PCS_BASER_SYNC_THD_REG 0x330 590511e6bc0Shuangdaode #define XGMAC_PCS_STATUS1_REG 0x404 591511e6bc0Shuangdaode #define XGMAC_PCS_BASER_STATUS1_REG 0x410 592511e6bc0Shuangdaode #define XGMAC_PCS_BASER_STATUS2_REG 0x414 593511e6bc0Shuangdaode #define XGMAC_PCS_BASER_SEEDA_0_REG 0x420 594511e6bc0Shuangdaode #define XGMAC_PCS_BASER_SEEDA_1_REG 0x424 595511e6bc0Shuangdaode #define XGMAC_PCS_BASER_SEEDB_0_REG 0x428 596511e6bc0Shuangdaode #define XGMAC_PCS_BASER_SEEDB_1_REG 0x42C 597511e6bc0Shuangdaode #define XGMAC_PCS_BASER_TEST_CONTROL_REG 0x430 598511e6bc0Shuangdaode #define XGMAC_PCS_BASER_TEST_ERR_CNT_REG 0x434 599511e6bc0Shuangdaode #define XGMAC_PCS_DBG_INFO_REG 0x4C0 600511e6bc0Shuangdaode #define XGMAC_PCS_DBG_INFO1_REG 0x4C4 601511e6bc0Shuangdaode #define XGMAC_PCS_DBG_INFO2_REG 0x4C8 602511e6bc0Shuangdaode #define XGMAC_PCS_DBG_INFO3_REG 0x4CC 603511e6bc0Shuangdaode 604511e6bc0Shuangdaode #define XGMAC_PMA_ENABLE_REG 0x700 605511e6bc0Shuangdaode #define XGMAC_PMA_CONTROL_REG 0x704 606511e6bc0Shuangdaode #define XGMAC_PMA_SIGNAL_STATUS_REG 0x708 607511e6bc0Shuangdaode #define XGMAC_PMA_DBG_INFO_REG 0x70C 608511e6bc0Shuangdaode #define XGMAC_PMA_FEC_ABILITY_REG 0x740 609511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CONTROL_REG 0x744 610511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG 0x750 611511e6bc0Shuangdaode #define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG 0x760 612511e6bc0Shuangdaode 613511e6bc0Shuangdaode #define XGMAC_TX_PKTS_FRAGMENT 0x0000 614511e6bc0Shuangdaode #define XGMAC_TX_PKTS_UNDERSIZE 0x0008 615511e6bc0Shuangdaode #define XGMAC_TX_PKTS_UNDERMIN 0x0010 616511e6bc0Shuangdaode #define XGMAC_TX_PKTS_64OCTETS 0x0018 617511e6bc0Shuangdaode #define XGMAC_TX_PKTS_65TO127OCTETS 0x0020 618511e6bc0Shuangdaode #define XGMAC_TX_PKTS_128TO255OCTETS 0x0028 619511e6bc0Shuangdaode #define XGMAC_TX_PKTS_256TO511OCTETS 0x0030 620511e6bc0Shuangdaode #define XGMAC_TX_PKTS_512TO1023OCTETS 0x0038 621511e6bc0Shuangdaode #define XGMAC_TX_PKTS_1024TO1518OCTETS 0x0040 622511e6bc0Shuangdaode #define XGMAC_TX_PKTS_1519TOMAXOCTETS 0x0048 623511e6bc0Shuangdaode #define XGMAC_TX_PKTS_1519TOMAXOCTETSOK 0x0050 624511e6bc0Shuangdaode #define XGMAC_TX_PKTS_OVERSIZE 0x0058 625511e6bc0Shuangdaode #define XGMAC_TX_PKTS_JABBER 0x0060 626511e6bc0Shuangdaode #define XGMAC_TX_GOODPKTS 0x0068 627511e6bc0Shuangdaode #define XGMAC_TX_GOODOCTETS 0x0070 628511e6bc0Shuangdaode #define XGMAC_TX_TOTAL_PKTS 0x0078 629511e6bc0Shuangdaode #define XGMAC_TX_TOTALOCTETS 0x0080 630511e6bc0Shuangdaode #define XGMAC_TX_UNICASTPKTS 0x0088 631511e6bc0Shuangdaode #define XGMAC_TX_MULTICASTPKTS 0x0090 632511e6bc0Shuangdaode #define XGMAC_TX_BROADCASTPKTS 0x0098 633511e6bc0Shuangdaode #define XGMAC_TX_PRI0PAUSEPKTS 0x00a0 634511e6bc0Shuangdaode #define XGMAC_TX_PRI1PAUSEPKTS 0x00a8 635511e6bc0Shuangdaode #define XGMAC_TX_PRI2PAUSEPKTS 0x00b0 636511e6bc0Shuangdaode #define XGMAC_TX_PRI3PAUSEPKTS 0x00b8 637511e6bc0Shuangdaode #define XGMAC_TX_PRI4PAUSEPKTS 0x00c0 638511e6bc0Shuangdaode #define XGMAC_TX_PRI5PAUSEPKTS 0x00c8 639511e6bc0Shuangdaode #define XGMAC_TX_PRI6PAUSEPKTS 0x00d0 640511e6bc0Shuangdaode #define XGMAC_TX_PRI7PAUSEPKTS 0x00d8 641511e6bc0Shuangdaode #define XGMAC_TX_MACCTRLPKTS 0x00e0 642511e6bc0Shuangdaode #define XGMAC_TX_1731PKTS 0x00e8 643511e6bc0Shuangdaode #define XGMAC_TX_1588PKTS 0x00f0 644511e6bc0Shuangdaode #define XGMAC_RX_FROMAPPGOODPKTS 0x00f8 645511e6bc0Shuangdaode #define XGMAC_RX_FROMAPPBADPKTS 0x0100 646511e6bc0Shuangdaode #define XGMAC_TX_ERRALLPKTS 0x0108 647511e6bc0Shuangdaode 648511e6bc0Shuangdaode #define XGMAC_RX_PKTS_FRAGMENT 0x0110 649511e6bc0Shuangdaode #define XGMAC_RX_PKTSUNDERSIZE 0x0118 650511e6bc0Shuangdaode #define XGMAC_RX_PKTS_UNDERMIN 0x0120 651511e6bc0Shuangdaode #define XGMAC_RX_PKTS_64OCTETS 0x0128 652511e6bc0Shuangdaode #define XGMAC_RX_PKTS_65TO127OCTETS 0x0130 653511e6bc0Shuangdaode #define XGMAC_RX_PKTS_128TO255OCTETS 0x0138 654511e6bc0Shuangdaode #define XGMAC_RX_PKTS_256TO511OCTETS 0x0140 655511e6bc0Shuangdaode #define XGMAC_RX_PKTS_512TO1023OCTETS 0x0148 656511e6bc0Shuangdaode #define XGMAC_RX_PKTS_1024TO1518OCTETS 0x0150 657511e6bc0Shuangdaode #define XGMAC_RX_PKTS_1519TOMAXOCTETS 0x0158 658511e6bc0Shuangdaode #define XGMAC_RX_PKTS_1519TOMAXOCTETSOK 0x0160 659511e6bc0Shuangdaode #define XGMAC_RX_PKTS_OVERSIZE 0x0168 660511e6bc0Shuangdaode #define XGMAC_RX_PKTS_JABBER 0x0170 661511e6bc0Shuangdaode #define XGMAC_RX_GOODPKTS 0x0178 662511e6bc0Shuangdaode #define XGMAC_RX_GOODOCTETS 0x0180 663511e6bc0Shuangdaode #define XGMAC_RX_TOTAL_PKTS 0x0188 664511e6bc0Shuangdaode #define XGMAC_RX_TOTALOCTETS 0x0190 665511e6bc0Shuangdaode #define XGMAC_RX_UNICASTPKTS 0x0198 666511e6bc0Shuangdaode #define XGMAC_RX_MULTICASTPKTS 0x01a0 667511e6bc0Shuangdaode #define XGMAC_RX_BROADCASTPKTS 0x01a8 668511e6bc0Shuangdaode #define XGMAC_RX_PRI0PAUSEPKTS 0x01b0 669511e6bc0Shuangdaode #define XGMAC_RX_PRI1PAUSEPKTS 0x01b8 670511e6bc0Shuangdaode #define XGMAC_RX_PRI2PAUSEPKTS 0x01c0 671511e6bc0Shuangdaode #define XGMAC_RX_PRI3PAUSEPKTS 0x01c8 672511e6bc0Shuangdaode #define XGMAC_RX_PRI4PAUSEPKTS 0x01d0 673511e6bc0Shuangdaode #define XGMAC_RX_PRI5PAUSEPKTS 0x01d8 674511e6bc0Shuangdaode #define XGMAC_RX_PRI6PAUSEPKTS 0x01e0 675511e6bc0Shuangdaode #define XGMAC_RX_PRI7PAUSEPKTS 0x01e8 676511e6bc0Shuangdaode #define XGMAC_RX_MACCTRLPKTS 0x01f0 677511e6bc0Shuangdaode #define XGMAC_TX_SENDAPPGOODPKTS 0x01f8 678511e6bc0Shuangdaode #define XGMAC_TX_SENDAPPBADPKTS 0x0200 679511e6bc0Shuangdaode #define XGMAC_RX_1731PKTS 0x0208 680511e6bc0Shuangdaode #define XGMAC_RX_SYMBOLERRPKTS 0x0210 681511e6bc0Shuangdaode #define XGMAC_RX_FCSERRPKTS 0x0218 682511e6bc0Shuangdaode 683511e6bc0Shuangdaode #define XGMAC_TRX_CORE_SRST_M 0x2080 684511e6bc0Shuangdaode 68513ac695eSSalil #define DSAF_SRAM_INIT_OVER_M 0xff 68613ac695eSSalil #define DSAFV2_SRAM_INIT_OVER_M 0x3ff 68713ac695eSSalil #define DSAF_SRAM_INIT_OVER_S 0 68813ac695eSSalil 689511e6bc0Shuangdaode #define DSAF_CFG_EN_S 0 690511e6bc0Shuangdaode #define DSAF_CFG_TC_MODE_S 1 691511e6bc0Shuangdaode #define DSAF_CFG_CRC_EN_S 2 692511e6bc0Shuangdaode #define DSAF_CFG_SBM_INIT_S 3 693511e6bc0Shuangdaode #define DSAF_CFG_MIX_MODE_S 4 694511e6bc0Shuangdaode #define DSAF_CFG_STP_MODE_S 5 695511e6bc0Shuangdaode #define DSAF_CFG_LOCA_ADDR_EN_S 6 69613ac695eSSalil #define DSAFV2_CFG_VLAN_TAG_MODE_S 17 697511e6bc0Shuangdaode 698511e6bc0Shuangdaode #define DSAF_CNT_CLR_CE_S 0 699511e6bc0Shuangdaode #define DSAF_SNAP_EN_S 1 700511e6bc0Shuangdaode 701511e6bc0Shuangdaode #define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE 41 702511e6bc0Shuangdaode #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 410 703511e6bc0Shuangdaode #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 103 704511e6bc0Shuangdaode 705511e6bc0Shuangdaode #define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1) 706511e6bc0Shuangdaode #define DSAF_PFC_UNINT_CNT_S 0 707511e6bc0Shuangdaode 708511e6bc0Shuangdaode #define DSAF_PPE_QID_CFG_M 0xFF 709511e6bc0Shuangdaode #define DSAF_PPE_QID_CFG_S 0 710511e6bc0Shuangdaode 711511e6bc0Shuangdaode #define DSAF_SW_PORT_TYPE_M 3 712511e6bc0Shuangdaode #define DSAF_SW_PORT_TYPE_S 0 713511e6bc0Shuangdaode 714511e6bc0Shuangdaode #define DSAF_STP_PORT_TYPE_M 7 715511e6bc0Shuangdaode #define DSAF_STP_PORT_TYPE_S 0 716511e6bc0Shuangdaode 717511e6bc0Shuangdaode #define DSAF_INODE_IN_PORT_NUM_M 7 718511e6bc0Shuangdaode #define DSAF_INODE_IN_PORT_NUM_S 0 71913ac695eSSalil #define DSAFV2_INODE_IN_PORT1_NUM_M (7ULL << 3) 72013ac695eSSalil #define DSAFV2_INODE_IN_PORT1_NUM_S 3 72113ac695eSSalil #define DSAFV2_INODE_IN_PORT2_NUM_M (7ULL << 6) 72213ac695eSSalil #define DSAFV2_INODE_IN_PORT2_NUM_S 6 72313ac695eSSalil #define DSAFV2_INODE_IN_PORT3_NUM_M (7ULL << 9) 72413ac695eSSalil #define DSAFV2_INODE_IN_PORT3_NUM_S 9 72513ac695eSSalil #define DSAFV2_INODE_IN_PORT4_NUM_M (7ULL << 12) 72613ac695eSSalil #define DSAFV2_INODE_IN_PORT4_NUM_S 12 72713ac695eSSalil #define DSAFV2_INODE_IN_PORT5_NUM_M (7ULL << 15) 72813ac695eSSalil #define DSAFV2_INODE_IN_PORT5_NUM_S 15 729511e6bc0Shuangdaode 730511e6bc0Shuangdaode #define HNS_DSAF_I4TC_CFG 0x18688688 731511e6bc0Shuangdaode #define HNS_DSAF_I8TC_CFG 0x18FAC688 732511e6bc0Shuangdaode 733511e6bc0Shuangdaode #define DSAF_SBM_CFG_SHCUT_EN_S 0 734511e6bc0Shuangdaode #define DSAF_SBM_CFG_EN_S 1 735511e6bc0Shuangdaode #define DSAF_SBM_CFG_MIB_EN_S 2 736511e6bc0Shuangdaode #define DSAF_SBM_CFG_ECC_INVERT_EN_S 3 737511e6bc0Shuangdaode 738511e6bc0Shuangdaode #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S 0 739511e6bc0Shuangdaode #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0) 740511e6bc0Shuangdaode #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S 10 741511e6bc0Shuangdaode #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10) 742511e6bc0Shuangdaode #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S 20 743511e6bc0Shuangdaode #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 11) - 1) << 20) 744511e6bc0Shuangdaode 745511e6bc0Shuangdaode #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S 0 746511e6bc0Shuangdaode #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0) 747511e6bc0Shuangdaode #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S 10 748511e6bc0Shuangdaode #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10) 749511e6bc0Shuangdaode 750511e6bc0Shuangdaode #define DSAF_SBM_CFG2_SET_BUF_NUM_S 0 751511e6bc0Shuangdaode #define DSAF_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 10) - 1) << 0) 752511e6bc0Shuangdaode #define DSAF_SBM_CFG2_RESET_BUF_NUM_S 10 753511e6bc0Shuangdaode #define DSAF_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 10) - 1) << 10) 754511e6bc0Shuangdaode 755511e6bc0Shuangdaode #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0 756511e6bc0Shuangdaode #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 0) 757511e6bc0Shuangdaode #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 10 758511e6bc0Shuangdaode #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 10) 759511e6bc0Shuangdaode 76013ac695eSSalil #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S 0 76113ac695eSSalil #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0) 76213ac695eSSalil #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S 9 76313ac695eSSalil #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9) 76413ac695eSSalil #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S 18 76513ac695eSSalil #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 18) 76613ac695eSSalil 76713ac695eSSalil #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S 0 76813ac695eSSalil #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0) 76913ac695eSSalil #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S 9 77013ac695eSSalil #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9) 77113ac695eSSalil 77213ac695eSSalil #define DSAFV2_SBM_CFG2_SET_BUF_NUM_S 0 77313ac695eSSalil #define DSAFV2_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 9) - 1) << 0) 77413ac695eSSalil #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_S 9 77513ac695eSSalil #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 9) - 1) << 9) 77613ac695eSSalil 77713ac695eSSalil #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0 77813ac695eSSalil #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0) 77913ac695eSSalil #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 9 78013ac695eSSalil #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9) 78113ac695eSSalil 78213ac695eSSalil #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S 0 78313ac695eSSalil #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0) 78413ac695eSSalil #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S 9 78513ac695eSSalil #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9) 78613ac695eSSalil 787511e6bc0Shuangdaode #define DSAF_TBL_TCAM_ADDR_S 0 788511e6bc0Shuangdaode #define DSAF_TBL_TCAM_ADDR_M ((1ULL << 9) - 1) 789511e6bc0Shuangdaode 790511e6bc0Shuangdaode #define DSAF_TBL_LINE_ADDR_S 0 791511e6bc0Shuangdaode #define DSAF_TBL_LINE_ADDR_M ((1ULL << 15) - 1) 792511e6bc0Shuangdaode 793511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG4_VM128_112_S 0 794511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG4_VM128_112_M (((1ULL << 7) - 1) << 0) 795511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S 7 796511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG4_OLD_EN_S 8 797511e6bc0Shuangdaode 798511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG0_XGE5_0_S 0 799511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG0_XGE5_0_M (((1ULL << 6) - 1) << 0) 800511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG0_VM25_0_S 6 801511e6bc0Shuangdaode #define DSAF_TBL_MCAST_CFG0_VM25_0_M (((1ULL << 26) - 1) << 6) 802511e6bc0Shuangdaode 803511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_OUT_PORT_S 0 804511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_OUT_PORT_M (((1ULL << 8) - 1) << 0) 805511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_DVC_S 8 806511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S 9 807511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S 10 808511e6bc0Shuangdaode #define DSAF_TBL_UCAST_CFG1_OLD_EN_S 11 809511e6bc0Shuangdaode 810511e6bc0Shuangdaode #define DSAF_TBL_LINE_CFG_OUT_PORT_S 0 811511e6bc0Shuangdaode #define DSAF_TBL_LINE_CFG_OUT_PORT_M (((1ULL << 8) - 1) << 0) 812511e6bc0Shuangdaode #define DSAF_TBL_LINE_CFG_DVC_S 8 813511e6bc0Shuangdaode #define DSAF_TBL_LINE_CFG_MAC_DISCARD_S 9 814511e6bc0Shuangdaode 815511e6bc0Shuangdaode #define DSAF_TBL_PUL_OLD_RSLT_RE_S 0 816511e6bc0Shuangdaode #define DSAF_TBL_PUL_MCAST_VLD_S 1 817511e6bc0Shuangdaode #define DSAF_TBL_PUL_TCAM_DATA_VLD_S 2 818511e6bc0Shuangdaode #define DSAF_TBL_PUL_UCAST_VLD_S 3 819511e6bc0Shuangdaode #define DSAF_TBL_PUL_LINE_VLD_S 4 820511e6bc0Shuangdaode #define DSAF_TBL_PUL_TCAM_LOAD_S 5 821511e6bc0Shuangdaode #define DSAF_TBL_PUL_LINE_LOAD_S 6 822511e6bc0Shuangdaode 823511e6bc0Shuangdaode #define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S 0 824511e6bc0Shuangdaode #define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S 1 825511e6bc0Shuangdaode #define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S 2 826511e6bc0Shuangdaode #define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S 3 827511e6bc0Shuangdaode #define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S 4 828511e6bc0Shuangdaode 829511e6bc0Shuangdaode #define DSAF_VOQ_BP_ALL_DOWNTHRD_S 0 830511e6bc0Shuangdaode #define DSAF_VOQ_BP_ALL_DOWNTHRD_M (((1ULL << 10) - 1) << 0) 831511e6bc0Shuangdaode #define DSAF_VOQ_BP_ALL_UPTHRD_S 10 832511e6bc0Shuangdaode #define DSAF_VOQ_BP_ALL_UPTHRD_M (((1ULL << 10) - 1) << 10) 833511e6bc0Shuangdaode 834511e6bc0Shuangdaode #define DSAF_XGE_GE_WORK_MODE_S 0 835511e6bc0Shuangdaode #define DSAF_XGE_GE_LOOPBACK_S 1 836511e6bc0Shuangdaode 837511e6bc0Shuangdaode #define DSAF_FC_XGE_TX_PAUSE_S 0 838511e6bc0Shuangdaode #define DSAF_REGS_XGE_CNT_CAR_S 1 839511e6bc0Shuangdaode 840511e6bc0Shuangdaode #define PPE_CFG_QID_MODE_DEF_QID_S 0 841511e6bc0Shuangdaode #define PPE_CFG_QID_MODE_DEF_QID_M (0xff << PPE_CFG_QID_MODE_DEF_QID_S) 842511e6bc0Shuangdaode 843511e6bc0Shuangdaode #define PPE_CFG_QID_MODE_CF_QID_MODE_S 8 844511e6bc0Shuangdaode #define PPE_CFG_QID_MODE_CF_QID_MODE_M (0x7 << PPE_CFG_QID_MODE_CF_QID_MODE_S) 845511e6bc0Shuangdaode 8466bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N0_S 0 8476bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N0_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N0_S) 8486bc0ce7dSSalil 8496bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N1_S 8 8506bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N1_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N1_S) 8516bc0ce7dSSalil 8526bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N2_S 16 8536bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N2_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N2_S) 8546bc0ce7dSSalil 8556bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N3_S 24 8566bc0ce7dSSalil #define PPEV2_CFG_RSS_TBL_4N3_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N3_S) 8576bc0ce7dSSalil 858511e6bc0Shuangdaode #define PPE_CNT_CLR_CE_B 0 859511e6bc0Shuangdaode #define PPE_CNT_CLR_SNAP_EN_B 1 860511e6bc0Shuangdaode 861511e6bc0Shuangdaode #define PPE_COMMON_CNT_CLR_CE_B 0 862511e6bc0Shuangdaode #define PPE_COMMON_CNT_CLR_SNAP_EN_B 1 863511e6bc0Shuangdaode 864511e6bc0Shuangdaode #define GMAC_DUPLEX_TYPE_B 0 865511e6bc0Shuangdaode 866511e6bc0Shuangdaode #define GMAC_FC_TX_TIMER_S 0 867511e6bc0Shuangdaode #define GMAC_FC_TX_TIMER_M 0xffff 868511e6bc0Shuangdaode 869511e6bc0Shuangdaode #define GMAC_MAX_FRM_SIZE_S 0 870511e6bc0Shuangdaode #define GMAC_MAX_FRM_SIZE_M 0xffff 871511e6bc0Shuangdaode 872511e6bc0Shuangdaode #define GMAC_PORT_MODE_S 0 873511e6bc0Shuangdaode #define GMAC_PORT_MODE_M 0xf 874511e6bc0Shuangdaode 875511e6bc0Shuangdaode #define GMAC_RGMII_1000M_DELAY_B 4 876511e6bc0Shuangdaode #define GMAC_MII_TX_EDGE_SEL_B 5 877511e6bc0Shuangdaode #define GMAC_FIFO_ERR_AUTO_RST_B 6 878511e6bc0Shuangdaode #define GMAC_DBG_CLK_LOS_MSK_B 7 879511e6bc0Shuangdaode 880511e6bc0Shuangdaode #define GMAC_PORT_RX_EN_B 1 881511e6bc0Shuangdaode #define GMAC_PORT_TX_EN_B 2 882511e6bc0Shuangdaode 883511e6bc0Shuangdaode #define GMAC_PAUSE_EN_RX_FDFC_B 0 884511e6bc0Shuangdaode #define GMAC_PAUSE_EN_TX_FDFC_B 1 885511e6bc0Shuangdaode #define GMAC_PAUSE_EN_TX_HDFC_B 2 886511e6bc0Shuangdaode 887511e6bc0Shuangdaode #define GMAC_SHORT_RUNTS_THR_S 0 888511e6bc0Shuangdaode #define GMAC_SHORT_RUNTS_THR_M 0x1f 889511e6bc0Shuangdaode 890511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_FD_B 5 891511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_HD_B 6 892511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B 12 893511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_RF2_B 13 894511e6bc0Shuangdaode 895511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_NP_LNK_OK_B 15 896511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_RX_SYNC_OK_B 20 897511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_AN_DONE_B 21 898511e6bc0Shuangdaode 899511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_PS_S 7 900511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_PS_M (0x3 << GMAC_AN_NEG_STAT_PS_S) 901511e6bc0Shuangdaode 902511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_SPEED_S 10 903511e6bc0Shuangdaode #define GMAC_AN_NEG_STAT_SPEED_M (0x3 << GMAC_AN_NEG_STAT_SPEED_S) 904511e6bc0Shuangdaode 905511e6bc0Shuangdaode #define GMAC_TX_AN_EN_B 5 906511e6bc0Shuangdaode #define GMAC_TX_CRC_ADD_B 6 907511e6bc0Shuangdaode #define GMAC_TX_PAD_EN_B 7 908511e6bc0Shuangdaode 909511e6bc0Shuangdaode #define GMAC_LINE_LOOPBACK_B 0 910511e6bc0Shuangdaode 911511e6bc0Shuangdaode #define GMAC_LP_REG_CF_EXT_DRV_LP_B 1 912511e6bc0Shuangdaode #define GMAC_LP_REG_CF2MI_LP_EN_B 2 913511e6bc0Shuangdaode 914511e6bc0Shuangdaode #define GMAC_MODE_CHANGE_EB_B 0 915511e6bc0Shuangdaode 916511e6bc0Shuangdaode #define GMAC_RECV_CTRL_STRIP_PAD_EN_B 3 917511e6bc0Shuangdaode #define GMAC_RECV_CTRL_RUNT_PKT_EN_B 4 918511e6bc0Shuangdaode 919511e6bc0Shuangdaode #define GMAC_TX_LOOP_PKT_HIG_PRI_B 0 920511e6bc0Shuangdaode #define GMAC_TX_LOOP_PKT_EN_B 1 921511e6bc0Shuangdaode 922511e6bc0Shuangdaode #define XGMAC_PORT_MODE_TX_S 0x0 923511e6bc0Shuangdaode #define XGMAC_PORT_MODE_TX_M (0x3 << XGMAC_PORT_MODE_TX_S) 924511e6bc0Shuangdaode #define XGMAC_PORT_MODE_TX_40G_B 0x3 925511e6bc0Shuangdaode #define XGMAC_PORT_MODE_RX_S 0x4 926511e6bc0Shuangdaode #define XGMAC_PORT_MODE_RX_M (0x3 << XGMAC_PORT_MODE_RX_S) 927511e6bc0Shuangdaode #define XGMAC_PORT_MODE_RX_40G_B 0x7 928511e6bc0Shuangdaode 929511e6bc0Shuangdaode #define XGMAC_ENABLE_TX_B 0 930511e6bc0Shuangdaode #define XGMAC_ENABLE_RX_B 1 931511e6bc0Shuangdaode 932511e6bc0Shuangdaode #define XGMAC_CTL_TX_FCS_B 0 933511e6bc0Shuangdaode #define XGMAC_CTL_TX_PAD_B 1 934511e6bc0Shuangdaode #define XGMAC_CTL_TX_PREAMBLE_TRANS_B 3 935511e6bc0Shuangdaode #define XGMAC_CTL_TX_UNDER_MIN_ERR_B 4 936511e6bc0Shuangdaode #define XGMAC_CTL_TX_TRUNCATE_B 5 937511e6bc0Shuangdaode #define XGMAC_CTL_TX_1588_B 8 938511e6bc0Shuangdaode #define XGMAC_CTL_TX_1731_B 9 939511e6bc0Shuangdaode #define XGMAC_CTL_TX_PFC_B 10 940511e6bc0Shuangdaode #define XGMAC_CTL_RX_FCS_B 16 941511e6bc0Shuangdaode #define XGMAC_CTL_RX_FCS_STRIP_B 17 942511e6bc0Shuangdaode #define XGMAC_CTL_RX_PREAMBLE_TRANS_B 19 943511e6bc0Shuangdaode #define XGMAC_CTL_RX_UNDER_MIN_ERR_B 20 944511e6bc0Shuangdaode #define XGMAC_CTL_RX_TRUNCATE_B 21 945511e6bc0Shuangdaode #define XGMAC_CTL_RX_1588_B 24 946511e6bc0Shuangdaode #define XGMAC_CTL_RX_1731_B 25 947511e6bc0Shuangdaode #define XGMAC_CTL_RX_PFC_B 26 948511e6bc0Shuangdaode 949511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CTL_TX_B 0 950511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CTL_RX_B 1 951511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CTL_ERR_EN 2 952511e6bc0Shuangdaode #define XGMAC_PMA_FEC_CTL_ERR_SH 3 953511e6bc0Shuangdaode 954511e6bc0Shuangdaode #define XGMAC_PAUSE_CTL_TX_B 0 955511e6bc0Shuangdaode #define XGMAC_PAUSE_CTL_RX_B 1 956511e6bc0Shuangdaode #define XGMAC_PAUSE_CTL_RSP_MODE_B 2 957511e6bc0Shuangdaode #define XGMAC_PAUSE_CTL_TX_XOFF_B 3 958511e6bc0Shuangdaode 959511e6bc0Shuangdaode static inline void dsaf_write_reg(void *base, u32 reg, u32 value) 960511e6bc0Shuangdaode { 961511e6bc0Shuangdaode u8 __iomem *reg_addr = ACCESS_ONCE(base); 962511e6bc0Shuangdaode 963511e6bc0Shuangdaode writel(value, reg_addr + reg); 964511e6bc0Shuangdaode } 965511e6bc0Shuangdaode 966511e6bc0Shuangdaode #define dsaf_write_dev(a, reg, value) \ 967511e6bc0Shuangdaode dsaf_write_reg((a)->io_base, (reg), (value)) 968511e6bc0Shuangdaode 969511e6bc0Shuangdaode static inline u32 dsaf_read_reg(u8 *base, u32 reg) 970511e6bc0Shuangdaode { 971511e6bc0Shuangdaode u8 __iomem *reg_addr = ACCESS_ONCE(base); 972511e6bc0Shuangdaode 973511e6bc0Shuangdaode return readl(reg_addr + reg); 974511e6bc0Shuangdaode } 975511e6bc0Shuangdaode 976511e6bc0Shuangdaode #define dsaf_read_dev(a, reg) \ 977511e6bc0Shuangdaode dsaf_read_reg((a)->io_base, (reg)) 978511e6bc0Shuangdaode 979511e6bc0Shuangdaode #define dsaf_set_field(origin, mask, shift, val) \ 980511e6bc0Shuangdaode do { \ 981511e6bc0Shuangdaode (origin) &= (~(mask)); \ 982511e6bc0Shuangdaode (origin) |= (((val) << (shift)) & (mask)); \ 983511e6bc0Shuangdaode } while (0) 984511e6bc0Shuangdaode 985511e6bc0Shuangdaode #define dsaf_set_bit(origin, shift, val) \ 986511e6bc0Shuangdaode dsaf_set_field((origin), (1ull << (shift)), (shift), (val)) 987511e6bc0Shuangdaode 988511e6bc0Shuangdaode static inline void dsaf_set_reg_field(void *base, u32 reg, u32 mask, u32 shift, 989511e6bc0Shuangdaode u32 val) 990511e6bc0Shuangdaode { 991511e6bc0Shuangdaode u32 origin = dsaf_read_reg(base, reg); 992511e6bc0Shuangdaode 993511e6bc0Shuangdaode dsaf_set_field(origin, mask, shift, val); 994511e6bc0Shuangdaode dsaf_write_reg(base, reg, origin); 995511e6bc0Shuangdaode } 996511e6bc0Shuangdaode 997511e6bc0Shuangdaode #define dsaf_set_dev_field(dev, reg, mask, shift, val) \ 998511e6bc0Shuangdaode dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val)) 999511e6bc0Shuangdaode 1000511e6bc0Shuangdaode #define dsaf_set_dev_bit(dev, reg, bit, val) \ 1001511e6bc0Shuangdaode dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val)) 1002511e6bc0Shuangdaode 1003511e6bc0Shuangdaode #define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 1004511e6bc0Shuangdaode 1005511e6bc0Shuangdaode #define dsaf_get_bit(origin, shift) \ 1006511e6bc0Shuangdaode dsaf_get_field((origin), (1ull << (shift)), (shift)) 1007511e6bc0Shuangdaode 1008511e6bc0Shuangdaode static inline u32 dsaf_get_reg_field(void *base, u32 reg, u32 mask, u32 shift) 1009511e6bc0Shuangdaode { 1010511e6bc0Shuangdaode u32 origin; 1011511e6bc0Shuangdaode 1012511e6bc0Shuangdaode origin = dsaf_read_reg(base, reg); 1013511e6bc0Shuangdaode return dsaf_get_field(origin, mask, shift); 1014511e6bc0Shuangdaode } 1015511e6bc0Shuangdaode 1016511e6bc0Shuangdaode #define dsaf_get_dev_field(dev, reg, mask, shift) \ 1017511e6bc0Shuangdaode dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift)) 1018511e6bc0Shuangdaode 1019511e6bc0Shuangdaode #define dsaf_get_dev_bit(dev, reg, bit) \ 1020511e6bc0Shuangdaode dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit)) 1021511e6bc0Shuangdaode 1022511e6bc0Shuangdaode #define dsaf_write_b(addr, data)\ 1023511e6bc0Shuangdaode writeb((data), (__iomem unsigned char *)(addr)) 1024511e6bc0Shuangdaode #define dsaf_read_b(addr)\ 1025511e6bc0Shuangdaode readb((__iomem unsigned char *)(addr)) 1026511e6bc0Shuangdaode 1027511e6bc0Shuangdaode #define hns_mac_reg_read64(drv, offset) \ 1028e4600d69Shuangdaode readq((__iomem void *)(((u8 *)(drv)->io_base + 0xc00 + (offset)))) 1029511e6bc0Shuangdaode 1030511e6bc0Shuangdaode #endif /* _DSAF_REG_H */ 1031