1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/cdev.h> 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <asm/cacheflush.h> 17 #include <linux/platform_device.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_platform.h> 21 #include <linux/of_irq.h> 22 #include <linux/spinlock.h> 23 24 #include "hns_dsaf_main.h" 25 #include "hns_dsaf_ppe.h" 26 #include "hns_dsaf_rcb.h" 27 28 #define RCB_COMMON_REG_OFFSET 0x80000 29 #define TX_RING 0 30 #define RX_RING 1 31 32 #define RCB_RESET_WAIT_TIMES 30 33 #define RCB_RESET_TRY_TIMES 10 34 35 /* Because default mtu is 1500, rcb buffer size is set to 2048 enough */ 36 #define RCB_DEFAULT_BUFFER_SIZE 2048 37 38 /** 39 *hns_rcb_wait_fbd_clean - clean fbd 40 *@qs: ring struct pointer array 41 *@qnum: num of array 42 *@flag: tx or rx flag 43 */ 44 void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag) 45 { 46 int i, wait_cnt; 47 u32 fbd_num; 48 49 for (wait_cnt = i = 0; i < q_num; wait_cnt++) { 50 usleep_range(200, 300); 51 fbd_num = 0; 52 if (flag & RCB_INT_FLAG_TX) 53 fbd_num += dsaf_read_dev(qs[i], 54 RCB_RING_TX_RING_FBDNUM_REG); 55 if (flag & RCB_INT_FLAG_RX) 56 fbd_num += dsaf_read_dev(qs[i], 57 RCB_RING_RX_RING_FBDNUM_REG); 58 if (!fbd_num) 59 i++; 60 if (wait_cnt >= 10000) 61 break; 62 } 63 64 if (i < q_num) 65 dev_err(qs[i]->handle->owner_dev, 66 "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num); 67 } 68 69 int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs) 70 { 71 u32 head, tail; 72 int wait_cnt; 73 74 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL); 75 wait_cnt = 0; 76 while (wait_cnt++ < HNS_MAX_WAIT_CNT) { 77 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD); 78 if (tail == head) 79 break; 80 81 usleep_range(100, 200); 82 } 83 84 if (wait_cnt >= HNS_MAX_WAIT_CNT) { 85 dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n"); 86 return -EBUSY; 87 } 88 89 return 0; 90 } 91 92 /** 93 *hns_rcb_reset_ring_hw - ring reset 94 *@q: ring struct pointer 95 */ 96 void hns_rcb_reset_ring_hw(struct hnae_queue *q) 97 { 98 u32 wait_cnt; 99 u32 try_cnt = 0; 100 u32 could_ret; 101 102 u32 tx_fbd_num; 103 104 while (try_cnt++ < RCB_RESET_TRY_TIMES) { 105 usleep_range(100, 200); 106 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG); 107 if (tx_fbd_num) 108 continue; 109 110 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0); 111 112 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); 113 114 msleep(20); 115 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); 116 117 wait_cnt = 0; 118 while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) { 119 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); 120 121 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1); 122 123 msleep(20); 124 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST); 125 126 wait_cnt++; 127 } 128 129 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0); 130 131 if (could_ret) 132 break; 133 } 134 135 if (try_cnt >= RCB_RESET_TRY_TIMES) 136 dev_err(q->dev->dev, "port%d reset ring fail\n", 137 hns_ae_get_vf_cb(q->handle)->port_index); 138 } 139 140 /** 141 *hns_rcb_int_ctrl_hw - rcb irq enable control 142 *@q: hnae queue struct pointer 143 *@flag:ring flag tx or rx 144 *@mask:mask 145 */ 146 void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask) 147 { 148 u32 int_mask_en = !!mask; 149 150 if (flag & RCB_INT_FLAG_TX) { 151 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en); 152 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG, 153 int_mask_en); 154 } 155 156 if (flag & RCB_INT_FLAG_RX) { 157 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en); 158 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG, 159 int_mask_en); 160 } 161 } 162 163 void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag) 164 { 165 if (flag & RCB_INT_FLAG_TX) { 166 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1); 167 dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1); 168 } 169 170 if (flag & RCB_INT_FLAG_RX) { 171 dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1); 172 dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1); 173 } 174 } 175 176 void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask) 177 { 178 u32 int_mask_en = !!mask; 179 180 if (flag & RCB_INT_FLAG_TX) 181 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en); 182 183 if (flag & RCB_INT_FLAG_RX) 184 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en); 185 } 186 187 void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag) 188 { 189 if (flag & RCB_INT_FLAG_TX) 190 dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1); 191 192 if (flag & RCB_INT_FLAG_RX) 193 dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1); 194 } 195 196 /** 197 *hns_rcb_ring_enable_hw - enable ring 198 *@ring: rcb ring 199 */ 200 void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val) 201 { 202 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val); 203 } 204 205 void hns_rcb_start(struct hnae_queue *q, u32 val) 206 { 207 hns_rcb_ring_enable_hw(q, val); 208 } 209 210 /** 211 *hns_rcb_common_init_commit_hw - make rcb common init completed 212 *@rcb_common: rcb common device 213 */ 214 void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common) 215 { 216 wmb(); /* Sync point before breakpoint */ 217 dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1); 218 wmb(); /* Sync point after breakpoint */ 219 } 220 221 /* hns_rcb_set_tx_ring_bs - init rcb ring buf size regester 222 *@q: hnae_queue 223 *@buf_size: buffer size set to hw 224 */ 225 void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size) 226 { 227 u32 bd_size_type = hns_rcb_buf_size2type(buf_size); 228 229 dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG, 230 bd_size_type); 231 } 232 233 /* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester 234 *@q: hnae_queue 235 *@buf_size: buffer size set to hw 236 */ 237 void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size) 238 { 239 u32 bd_size_type = hns_rcb_buf_size2type(buf_size); 240 241 dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG, 242 bd_size_type); 243 } 244 245 /** 246 *hns_rcb_ring_init - init rcb ring 247 *@ring_pair: ring pair control block 248 *@ring_type: ring type, RX_RING or TX_RING 249 */ 250 static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type) 251 { 252 struct hnae_queue *q = &ring_pair->q; 253 struct hnae_ring *ring = 254 (ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring; 255 dma_addr_t dma = ring->desc_dma_addr; 256 257 if (ring_type == RX_RING) { 258 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG, 259 (u32)dma); 260 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG, 261 (u32)((dma >> 31) >> 1)); 262 263 hns_rcb_set_rx_ring_bs(q, ring->buf_size); 264 265 dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG, 266 ring_pair->port_id_in_comm); 267 dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG, 268 ring_pair->port_id_in_comm); 269 } else { 270 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG, 271 (u32)dma); 272 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG, 273 (u32)((dma >> 31) >> 1)); 274 275 hns_rcb_set_tx_ring_bs(q, ring->buf_size); 276 277 dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG, 278 ring_pair->port_id_in_comm); 279 dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG, 280 ring_pair->port_id_in_comm + HNS_RCB_TX_PKTLINE_OFFSET); 281 } 282 } 283 284 /** 285 *hns_rcb_init_hw - init rcb hardware 286 *@ring: rcb ring 287 */ 288 void hns_rcb_init_hw(struct ring_pair_cb *ring) 289 { 290 hns_rcb_ring_init(ring, RX_RING); 291 hns_rcb_ring_init(ring, TX_RING); 292 } 293 294 /** 295 *hns_rcb_set_port_desc_cnt - set rcb port description num 296 *@rcb_common: rcb_common device 297 *@port_idx:port index 298 *@desc_cnt:BD num 299 */ 300 static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common, 301 u32 port_idx, u32 desc_cnt) 302 { 303 dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4, 304 desc_cnt); 305 } 306 307 static void hns_rcb_set_port_timeout( 308 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout) 309 { 310 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) { 311 dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG, 312 timeout * HNS_RCB_CLK_FREQ_MHZ); 313 } else if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) { 314 if (timeout > HNS_RCB_DEF_GAP_TIME_USECS) 315 dsaf_write_dev(rcb_common, 316 RCB_PORT_INT_GAPTIME_REG + port_idx * 4, 317 HNS_RCB_DEF_GAP_TIME_USECS); 318 else 319 dsaf_write_dev(rcb_common, 320 RCB_PORT_INT_GAPTIME_REG + port_idx * 4, 321 timeout); 322 323 dsaf_write_dev(rcb_common, 324 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4, 325 timeout); 326 } else { 327 dsaf_write_dev(rcb_common, 328 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4, 329 timeout); 330 } 331 } 332 333 static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common) 334 { 335 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) 336 return HNS_RCB_SERVICE_NW_ENGINE_NUM; 337 else 338 return HNS_RCB_DEBUG_NW_ENGINE_NUM; 339 } 340 341 /*clr rcb comm exception irq**/ 342 static void hns_rcb_comm_exc_irq_en( 343 struct rcb_common_cb *rcb_common, int en) 344 { 345 u32 clr_vlue = 0xfffffffful; 346 u32 msk_vlue = en ? 0 : 0xfffffffful; 347 348 /* clr int*/ 349 dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue); 350 351 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue); 352 353 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue); 354 355 dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue); 356 dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue); 357 358 /*en msk*/ 359 dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue); 360 361 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue); 362 363 /*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/ 364 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2); 365 366 dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue); 367 dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue); 368 } 369 370 /** 371 *hns_rcb_common_init_hw - init rcb common hardware 372 *@rcb_common: rcb_common device 373 *retuen 0 - success , negative --fail 374 */ 375 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common) 376 { 377 u32 reg_val; 378 int i; 379 int port_num = hns_rcb_common_get_port_num(rcb_common); 380 381 hns_rcb_comm_exc_irq_en(rcb_common, 0); 382 383 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG); 384 if (0x1 != (reg_val & 0x1)) { 385 dev_err(rcb_common->dsaf_dev->dev, 386 "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val); 387 return -EBUSY; 388 } 389 390 for (i = 0; i < port_num; i++) { 391 hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num); 392 hns_rcb_set_rx_coalesced_frames( 393 rcb_common, i, HNS_RCB_DEF_RX_COALESCED_FRAMES); 394 if (!AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver) && 395 !HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) 396 hns_rcb_set_tx_coalesced_frames( 397 rcb_common, i, HNS_RCB_DEF_TX_COALESCED_FRAMES); 398 hns_rcb_set_port_timeout( 399 rcb_common, i, HNS_RCB_DEF_COALESCED_USECS); 400 } 401 402 dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG, 403 HNS_RCB_COMMON_ENDIAN); 404 405 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) { 406 dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0); 407 dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1); 408 } else { 409 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG, 410 RCB_COM_CFG_FNA_B, false); 411 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG, 412 RCB_COM_CFG_FA_B, true); 413 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG, 414 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K); 415 } 416 417 return 0; 418 } 419 420 int hns_rcb_buf_size2type(u32 buf_size) 421 { 422 int bd_size_type; 423 424 switch (buf_size) { 425 case 512: 426 bd_size_type = HNS_BD_SIZE_512_TYPE; 427 break; 428 case 1024: 429 bd_size_type = HNS_BD_SIZE_1024_TYPE; 430 break; 431 case 2048: 432 bd_size_type = HNS_BD_SIZE_2048_TYPE; 433 break; 434 case 4096: 435 bd_size_type = HNS_BD_SIZE_4096_TYPE; 436 break; 437 default: 438 bd_size_type = -EINVAL; 439 } 440 441 return bd_size_type; 442 } 443 444 static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type) 445 { 446 struct hnae_ring *ring; 447 struct rcb_common_cb *rcb_common; 448 struct ring_pair_cb *ring_pair_cb; 449 u16 desc_num, mdnum_ppkt; 450 bool irq_idx, is_ver1; 451 452 ring_pair_cb = container_of(q, struct ring_pair_cb, q); 453 is_ver1 = AE_IS_VER1(ring_pair_cb->rcb_common->dsaf_dev->dsaf_ver); 454 if (ring_type == RX_RING) { 455 ring = &q->rx_ring; 456 ring->io_base = ring_pair_cb->q.io_base; 457 irq_idx = HNS_RCB_IRQ_IDX_RX; 458 mdnum_ppkt = HNS_RCB_RING_MAX_BD_PER_PKT; 459 } else { 460 ring = &q->tx_ring; 461 ring->io_base = (u8 __iomem *)ring_pair_cb->q.io_base + 462 HNS_RCB_TX_REG_OFFSET; 463 irq_idx = HNS_RCB_IRQ_IDX_TX; 464 mdnum_ppkt = is_ver1 ? HNS_RCB_RING_MAX_TXBD_PER_PKT : 465 HNS_RCBV2_RING_MAX_TXBD_PER_PKT; 466 } 467 468 rcb_common = ring_pair_cb->rcb_common; 469 desc_num = rcb_common->dsaf_dev->desc_num; 470 471 ring->desc = NULL; 472 ring->desc_cb = NULL; 473 474 ring->irq = ring_pair_cb->virq[irq_idx]; 475 ring->desc_dma_addr = 0; 476 477 ring->buf_size = RCB_DEFAULT_BUFFER_SIZE; 478 ring->desc_num = desc_num; 479 ring->max_desc_num_per_pkt = mdnum_ppkt; 480 ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE; 481 ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE; 482 ring->next_to_use = 0; 483 ring->next_to_clean = 0; 484 } 485 486 static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb) 487 { 488 ring_pair_cb->q.handle = NULL; 489 490 hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING); 491 hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING); 492 } 493 494 static int hns_rcb_get_port_in_comm( 495 struct rcb_common_cb *rcb_common, int ring_idx) 496 { 497 return ring_idx / (rcb_common->max_q_per_vf * rcb_common->max_vfn); 498 } 499 500 #define SERVICE_RING_IRQ_IDX(v1) \ 501 ((v1) ? HNS_SERVICE_RING_IRQ_IDX : HNSV2_SERVICE_RING_IRQ_IDX) 502 static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common) 503 { 504 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver); 505 506 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) 507 return SERVICE_RING_IRQ_IDX(is_ver1); 508 else 509 return HNS_DEBUG_RING_IRQ_IDX; 510 } 511 512 #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\ 513 ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid)) 514 /** 515 *hns_rcb_get_cfg - get rcb config 516 *@rcb_common: rcb common device 517 */ 518 int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common) 519 { 520 struct ring_pair_cb *ring_pair_cb; 521 u32 i; 522 u32 ring_num = rcb_common->ring_num; 523 int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common); 524 struct platform_device *pdev = 525 to_platform_device(rcb_common->dsaf_dev->dev); 526 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver); 527 528 for (i = 0; i < ring_num; i++) { 529 ring_pair_cb = &rcb_common->ring_pair_cb[i]; 530 ring_pair_cb->rcb_common = rcb_common; 531 ring_pair_cb->dev = rcb_common->dsaf_dev->dev; 532 ring_pair_cb->index = i; 533 ring_pair_cb->q.io_base = 534 RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i); 535 ring_pair_cb->port_id_in_comm = 536 hns_rcb_get_port_in_comm(rcb_common, i); 537 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] = 538 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2) : 539 platform_get_irq(pdev, base_irq_idx + i * 3 + 1); 540 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] = 541 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2 + 1) : 542 platform_get_irq(pdev, base_irq_idx + i * 3); 543 if ((ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] == -EPROBE_DEFER) || 544 (ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] == -EPROBE_DEFER)) 545 return -EPROBE_DEFER; 546 547 ring_pair_cb->q.phy_base = 548 RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i); 549 hns_rcb_ring_pair_get_cfg(ring_pair_cb); 550 } 551 552 return 0; 553 } 554 555 /** 556 *hns_rcb_get_rx_coalesced_frames - get rcb port rx coalesced frames 557 *@rcb_common: rcb_common device 558 *@port_idx:port id in comm 559 * 560 *Returns: coalesced_frames 561 */ 562 u32 hns_rcb_get_rx_coalesced_frames( 563 struct rcb_common_cb *rcb_common, u32 port_idx) 564 { 565 return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4); 566 } 567 568 /** 569 *hns_rcb_get_tx_coalesced_frames - get rcb port tx coalesced frames 570 *@rcb_common: rcb_common device 571 *@port_idx:port id in comm 572 * 573 *Returns: coalesced_frames 574 */ 575 u32 hns_rcb_get_tx_coalesced_frames( 576 struct rcb_common_cb *rcb_common, u32 port_idx) 577 { 578 u64 reg; 579 580 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4; 581 return dsaf_read_dev(rcb_common, reg); 582 } 583 584 /** 585 *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out 586 *@rcb_common: rcb_common device 587 *@port_idx:port id in comm 588 * 589 *Returns: time_out 590 */ 591 u32 hns_rcb_get_coalesce_usecs( 592 struct rcb_common_cb *rcb_common, u32 port_idx) 593 { 594 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) 595 return dsaf_read_dev(rcb_common, RCB_CFG_OVERTIME_REG) / 596 HNS_RCB_CLK_FREQ_MHZ; 597 else 598 return dsaf_read_dev(rcb_common, 599 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4); 600 } 601 602 /** 603 *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out 604 *@rcb_common: rcb_common device 605 *@port_idx:port id in comm 606 *@timeout:tx/rx time for coalesced time_out 607 * 608 * Returns: 609 * Zero for success, or an error code in case of failure 610 */ 611 int hns_rcb_set_coalesce_usecs( 612 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout) 613 { 614 u32 old_timeout = hns_rcb_get_coalesce_usecs(rcb_common, port_idx); 615 616 if (timeout == old_timeout) 617 return 0; 618 619 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) { 620 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) { 621 dev_err(rcb_common->dsaf_dev->dev, 622 "error: not support coalesce_usecs setting!\n"); 623 return -EINVAL; 624 } 625 } 626 if (timeout > HNS_RCB_MAX_COALESCED_USECS || timeout == 0) { 627 dev_err(rcb_common->dsaf_dev->dev, 628 "error: coalesce_usecs setting supports 1~1023us\n"); 629 return -EINVAL; 630 } 631 hns_rcb_set_port_timeout(rcb_common, port_idx, timeout); 632 return 0; 633 } 634 635 /** 636 *hns_rcb_set_tx_coalesced_frames - set rcb coalesced frames 637 *@rcb_common: rcb_common device 638 *@port_idx:port id in comm 639 *@coalesced_frames:tx/rx BD num for coalesced frames 640 * 641 * Returns: 642 * Zero for success, or an error code in case of failure 643 */ 644 int hns_rcb_set_tx_coalesced_frames( 645 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames) 646 { 647 u32 old_waterline = 648 hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx); 649 u64 reg; 650 651 if (coalesced_frames == old_waterline) 652 return 0; 653 654 if (coalesced_frames != 1) { 655 dev_err(rcb_common->dsaf_dev->dev, 656 "error: not support tx coalesce_frames setting!\n"); 657 return -EINVAL; 658 } 659 660 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4; 661 dsaf_write_dev(rcb_common, reg, coalesced_frames); 662 return 0; 663 } 664 665 /** 666 *hns_rcb_set_rx_coalesced_frames - set rcb rx coalesced frames 667 *@rcb_common: rcb_common device 668 *@port_idx:port id in comm 669 *@coalesced_frames:tx/rx BD num for coalesced frames 670 * 671 * Returns: 672 * Zero for success, or an error code in case of failure 673 */ 674 int hns_rcb_set_rx_coalesced_frames( 675 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames) 676 { 677 u32 old_waterline = 678 hns_rcb_get_rx_coalesced_frames(rcb_common, port_idx); 679 680 if (coalesced_frames == old_waterline) 681 return 0; 682 683 if (coalesced_frames >= rcb_common->desc_num || 684 coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES || 685 coalesced_frames < HNS_RCB_MIN_COALESCED_FRAMES) { 686 dev_err(rcb_common->dsaf_dev->dev, 687 "error: not support coalesce_frames setting!\n"); 688 return -EINVAL; 689 } 690 691 dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4, 692 coalesced_frames); 693 return 0; 694 } 695 696 /** 697 *hns_rcb_get_queue_mode - get max VM number and max ring number per VM 698 * accordding to dsaf mode 699 *@dsaf_mode: dsaf mode 700 *@max_vfn : max vfn number 701 *@max_q_per_vf:max ring number per vm 702 */ 703 void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, u16 *max_vfn, 704 u16 *max_q_per_vf) 705 { 706 switch (dsaf_mode) { 707 case DSAF_MODE_DISABLE_6PORT_0VM: 708 *max_vfn = 1; 709 *max_q_per_vf = 16; 710 break; 711 case DSAF_MODE_DISABLE_FIX: 712 case DSAF_MODE_DISABLE_SP: 713 *max_vfn = 1; 714 *max_q_per_vf = 1; 715 break; 716 case DSAF_MODE_DISABLE_2PORT_64VM: 717 *max_vfn = 64; 718 *max_q_per_vf = 1; 719 break; 720 case DSAF_MODE_DISABLE_6PORT_16VM: 721 *max_vfn = 16; 722 *max_q_per_vf = 1; 723 break; 724 default: 725 *max_vfn = 1; 726 *max_q_per_vf = 16; 727 break; 728 } 729 } 730 731 static int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev) 732 { 733 switch (dsaf_dev->dsaf_mode) { 734 case DSAF_MODE_ENABLE_FIX: 735 case DSAF_MODE_DISABLE_SP: 736 return 1; 737 738 case DSAF_MODE_DISABLE_FIX: 739 return 6; 740 741 case DSAF_MODE_ENABLE_0VM: 742 return 32; 743 744 case DSAF_MODE_DISABLE_6PORT_0VM: 745 case DSAF_MODE_ENABLE_16VM: 746 case DSAF_MODE_DISABLE_6PORT_2VM: 747 case DSAF_MODE_DISABLE_6PORT_16VM: 748 case DSAF_MODE_DISABLE_6PORT_4VM: 749 case DSAF_MODE_ENABLE_8VM: 750 return 96; 751 752 case DSAF_MODE_DISABLE_2PORT_16VM: 753 case DSAF_MODE_DISABLE_2PORT_8VM: 754 case DSAF_MODE_ENABLE_32VM: 755 case DSAF_MODE_DISABLE_2PORT_64VM: 756 case DSAF_MODE_ENABLE_128VM: 757 return 128; 758 759 default: 760 dev_warn(dsaf_dev->dev, 761 "get ring num fail,use default!dsaf_mode=%d\n", 762 dsaf_dev->dsaf_mode); 763 return 128; 764 } 765 } 766 767 static void __iomem *hns_rcb_common_get_vaddr(struct rcb_common_cb *rcb_common) 768 { 769 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev; 770 771 return dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET; 772 } 773 774 static phys_addr_t hns_rcb_common_get_paddr(struct rcb_common_cb *rcb_common) 775 { 776 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev; 777 778 return dsaf_dev->ppe_paddr + RCB_COMMON_REG_OFFSET; 779 } 780 781 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev, 782 int comm_index) 783 { 784 struct rcb_common_cb *rcb_common; 785 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode; 786 u16 max_vfn; 787 u16 max_q_per_vf; 788 int ring_num = hns_rcb_get_ring_num(dsaf_dev); 789 790 rcb_common = 791 devm_kzalloc(dsaf_dev->dev, 792 struct_size(rcb_common, ring_pair_cb, ring_num), 793 GFP_KERNEL); 794 if (!rcb_common) { 795 dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n"); 796 return -ENOMEM; 797 } 798 rcb_common->comm_index = comm_index; 799 rcb_common->ring_num = ring_num; 800 rcb_common->dsaf_dev = dsaf_dev; 801 802 rcb_common->desc_num = dsaf_dev->desc_num; 803 804 hns_rcb_get_queue_mode(dsaf_mode, &max_vfn, &max_q_per_vf); 805 rcb_common->max_vfn = max_vfn; 806 rcb_common->max_q_per_vf = max_q_per_vf; 807 808 rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common); 809 rcb_common->phy_base = hns_rcb_common_get_paddr(rcb_common); 810 811 dsaf_dev->rcb_common[comm_index] = rcb_common; 812 return 0; 813 } 814 815 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev, 816 u32 comm_index) 817 { 818 dsaf_dev->rcb_common[comm_index] = NULL; 819 } 820 821 void hns_rcb_update_stats(struct hnae_queue *queue) 822 { 823 struct ring_pair_cb *ring = 824 container_of(queue, struct ring_pair_cb, q); 825 struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev; 826 struct ppe_common_cb *ppe_common 827 = dsaf_dev->ppe_common[ring->rcb_common->comm_index]; 828 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats; 829 830 hw_stats->rx_pkts += dsaf_read_dev(queue, 831 RCB_RING_RX_RING_PKTNUM_RECORD_REG); 832 dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1); 833 834 hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common, 835 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index); 836 hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common, 837 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index); 838 839 hw_stats->tx_pkts += dsaf_read_dev(queue, 840 RCB_RING_TX_RING_PKTNUM_RECORD_REG); 841 dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1); 842 843 hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common, 844 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index); 845 hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common, 846 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index); 847 } 848 849 /** 850 *hns_rcb_get_stats - get rcb statistic 851 *@ring: rcb ring 852 *@data:statistic value 853 */ 854 void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data) 855 { 856 u64 *regs_buff = data; 857 struct ring_pair_cb *ring = 858 container_of(queue, struct ring_pair_cb, q); 859 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats; 860 861 regs_buff[0] = hw_stats->tx_pkts; 862 regs_buff[1] = hw_stats->ppe_tx_ok_pkts; 863 regs_buff[2] = hw_stats->ppe_tx_drop_pkts; 864 regs_buff[3] = 865 dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG); 866 867 regs_buff[4] = queue->tx_ring.stats.tx_pkts; 868 regs_buff[5] = queue->tx_ring.stats.tx_bytes; 869 regs_buff[6] = queue->tx_ring.stats.tx_err_cnt; 870 regs_buff[7] = queue->tx_ring.stats.io_err_cnt; 871 regs_buff[8] = queue->tx_ring.stats.sw_err_cnt; 872 regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt; 873 regs_buff[10] = queue->tx_ring.stats.restart_queue; 874 regs_buff[11] = queue->tx_ring.stats.tx_busy; 875 876 regs_buff[12] = hw_stats->rx_pkts; 877 regs_buff[13] = hw_stats->ppe_rx_ok_pkts; 878 regs_buff[14] = hw_stats->ppe_rx_drop_pkts; 879 regs_buff[15] = 880 dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG); 881 882 regs_buff[16] = queue->rx_ring.stats.rx_pkts; 883 regs_buff[17] = queue->rx_ring.stats.rx_bytes; 884 regs_buff[18] = queue->rx_ring.stats.rx_err_cnt; 885 regs_buff[19] = queue->rx_ring.stats.io_err_cnt; 886 regs_buff[20] = queue->rx_ring.stats.sw_err_cnt; 887 regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt; 888 regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt; 889 regs_buff[23] = queue->rx_ring.stats.err_pkt_len; 890 regs_buff[24] = queue->rx_ring.stats.non_vld_descs; 891 regs_buff[25] = queue->rx_ring.stats.err_bd_num; 892 regs_buff[26] = queue->rx_ring.stats.l2_err; 893 regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err; 894 } 895 896 /** 897 *hns_rcb_get_ring_sset_count - rcb string set count 898 *@stringset:ethtool cmd 899 *return rcb ring string set count 900 */ 901 int hns_rcb_get_ring_sset_count(int stringset) 902 { 903 if (stringset == ETH_SS_STATS) 904 return HNS_RING_STATIC_REG_NUM; 905 906 return 0; 907 } 908 909 /** 910 *hns_rcb_get_common_regs_count - rcb common regs count 911 *return regs count 912 */ 913 int hns_rcb_get_common_regs_count(void) 914 { 915 return HNS_RCB_COMMON_DUMP_REG_NUM; 916 } 917 918 /** 919 *rcb_get_sset_count - rcb ring regs count 920 *return regs count 921 */ 922 int hns_rcb_get_ring_regs_count(void) 923 { 924 return HNS_RCB_RING_DUMP_REG_NUM; 925 } 926 927 /** 928 *hns_rcb_get_strings - get rcb string set 929 *@stringset:string set index 930 *@data:strings name value 931 *@index:queue index 932 */ 933 void hns_rcb_get_strings(int stringset, u8 *data, int index) 934 { 935 char *buff = (char *)data; 936 937 if (stringset != ETH_SS_STATS) 938 return; 939 940 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_rcb_pkt_num", index); 941 buff = buff + ETH_GSTRING_LEN; 942 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_tx_pkt_num", index); 943 buff = buff + ETH_GSTRING_LEN; 944 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_drop_pkt_num", index); 945 buff = buff + ETH_GSTRING_LEN; 946 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_fbd_num", index); 947 buff = buff + ETH_GSTRING_LEN; 948 949 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_pkt_num", index); 950 buff = buff + ETH_GSTRING_LEN; 951 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_bytes", index); 952 buff = buff + ETH_GSTRING_LEN; 953 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_err_cnt", index); 954 buff = buff + ETH_GSTRING_LEN; 955 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_io_err", index); 956 buff = buff + ETH_GSTRING_LEN; 957 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_sw_err", index); 958 buff = buff + ETH_GSTRING_LEN; 959 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_seg_pkt", index); 960 buff = buff + ETH_GSTRING_LEN; 961 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_restart_queue", index); 962 buff = buff + ETH_GSTRING_LEN; 963 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_tx_busy", index); 964 buff = buff + ETH_GSTRING_LEN; 965 966 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_rcb_pkt_num", index); 967 buff = buff + ETH_GSTRING_LEN; 968 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_pkt_num", index); 969 buff = buff + ETH_GSTRING_LEN; 970 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_drop_pkt_num", index); 971 buff = buff + ETH_GSTRING_LEN; 972 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_fbd_num", index); 973 buff = buff + ETH_GSTRING_LEN; 974 975 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_pkt_num", index); 976 buff = buff + ETH_GSTRING_LEN; 977 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bytes", index); 978 buff = buff + ETH_GSTRING_LEN; 979 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_err_cnt", index); 980 buff = buff + ETH_GSTRING_LEN; 981 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_io_err", index); 982 buff = buff + ETH_GSTRING_LEN; 983 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_sw_err", index); 984 buff = buff + ETH_GSTRING_LEN; 985 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_seg_pkt", index); 986 buff = buff + ETH_GSTRING_LEN; 987 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_reuse_pg", index); 988 buff = buff + ETH_GSTRING_LEN; 989 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_len_err", index); 990 buff = buff + ETH_GSTRING_LEN; 991 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_non_vld_desc_err", index); 992 buff = buff + ETH_GSTRING_LEN; 993 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bd_num_err", index); 994 buff = buff + ETH_GSTRING_LEN; 995 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l2_err", index); 996 buff = buff + ETH_GSTRING_LEN; 997 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l3l4csum_err", index); 998 } 999 1000 void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data) 1001 { 1002 u32 *regs = data; 1003 bool is_ver1 = AE_IS_VER1(rcb_com->dsaf_dev->dsaf_ver); 1004 bool is_dbg = HNS_DSAF_IS_DEBUG(rcb_com->dsaf_dev); 1005 u32 reg_tmp; 1006 u32 reg_num_tmp; 1007 u32 i = 0; 1008 1009 /*rcb common registers */ 1010 regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG); 1011 regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG); 1012 regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG); 1013 1014 regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG); 1015 regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG); 1016 regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG); 1017 regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG); 1018 regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG); 1019 regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG); 1020 1021 regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG); 1022 regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG); 1023 regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG); 1024 regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG); 1025 regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG); 1026 regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG); 1027 regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG); 1028 regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG); 1029 regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG); 1030 regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG); 1031 regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG); 1032 regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG); 1033 regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG); 1034 regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG); 1035 regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG); 1036 regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG); 1037 regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG); 1038 regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG); 1039 regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG); 1040 1041 regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING); 1042 regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS); 1043 regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING); 1044 regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD); 1045 regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS); 1046 regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY); 1047 regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN); 1048 regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK); 1049 regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS); 1050 regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG); 1051 1052 /* rcb common entry registers */ 1053 for (i = 0; i < 16; i++) { /* total 16 model registers */ 1054 regs[38 + i] 1055 = dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i); 1056 regs[54 + i] 1057 = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i); 1058 } 1059 1060 reg_tmp = is_ver1 ? RCB_CFG_OVERTIME_REG : RCB_PORT_CFG_OVERTIME_REG; 1061 reg_num_tmp = (is_ver1 || is_dbg) ? 1 : 6; 1062 for (i = 0; i < reg_num_tmp; i++) 1063 regs[70 + i] = dsaf_read_dev(rcb_com, reg_tmp); 1064 1065 regs[76] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG); 1066 regs[77] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG); 1067 1068 /* mark end of rcb common regs */ 1069 for (i = 78; i < 80; i++) 1070 regs[i] = 0xcccccccc; 1071 } 1072 1073 void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data) 1074 { 1075 u32 *regs = data; 1076 struct ring_pair_cb *ring_pair 1077 = container_of(queue, struct ring_pair_cb, q); 1078 u32 i = 0; 1079 1080 /*rcb ring registers */ 1081 regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG); 1082 regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG); 1083 regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG); 1084 regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG); 1085 regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG); 1086 regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG); 1087 regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG); 1088 regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG); 1089 regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG); 1090 1091 regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG); 1092 regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG); 1093 regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG); 1094 regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG); 1095 regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG); 1096 regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG); 1097 regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG); 1098 regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG); 1099 regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG); 1100 regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG); 1101 1102 regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG); 1103 regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG); 1104 regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG); 1105 regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG); 1106 regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST); 1107 regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST); 1108 regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG); 1109 1110 regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG); 1111 regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG); 1112 regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG); 1113 regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG); 1114 regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG); 1115 regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG); 1116 regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG); 1117 regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG); 1118 1119 /* mark end of ring regs */ 1120 for (i = 35; i < 40; i++) 1121 regs[i] = 0xcccccc00 + ring_pair->index; 1122 } 1123