1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2014-2015 Hisilicon Limited.
4  */
5 
6 #include <linux/cdev.h>
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <asm/cacheflush.h>
13 #include <linux/platform_device.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/of_irq.h>
18 #include <linux/spinlock.h>
19 
20 #include "hns_dsaf_main.h"
21 #include "hns_dsaf_ppe.h"
22 #include "hns_dsaf_rcb.h"
23 
24 #define RCB_COMMON_REG_OFFSET 0x80000
25 #define TX_RING 0
26 #define RX_RING 1
27 
28 #define RCB_RESET_WAIT_TIMES 30
29 #define RCB_RESET_TRY_TIMES 10
30 
31 /* Because default mtu is 1500, rcb buffer size is set to 2048 enough */
32 #define RCB_DEFAULT_BUFFER_SIZE 2048
33 
34 /**
35  *hns_rcb_wait_fbd_clean - clean fbd
36  *@qs: ring struct pointer array
37  *@qnum: num of array
38  *@flag: tx or rx flag
39  */
40 void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)
41 {
42 	int i, wait_cnt;
43 	u32 fbd_num;
44 
45 	for (wait_cnt = i = 0; i < q_num; wait_cnt++) {
46 		usleep_range(200, 300);
47 		fbd_num = 0;
48 		if (flag & RCB_INT_FLAG_TX)
49 			fbd_num += dsaf_read_dev(qs[i],
50 						 RCB_RING_TX_RING_FBDNUM_REG);
51 		if (flag & RCB_INT_FLAG_RX)
52 			fbd_num += dsaf_read_dev(qs[i],
53 						 RCB_RING_RX_RING_FBDNUM_REG);
54 		if (!fbd_num)
55 			i++;
56 		if (wait_cnt >= 10000)
57 			break;
58 	}
59 
60 	if (i < q_num)
61 		dev_err(qs[i]->handle->owner_dev,
62 			"queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);
63 }
64 
65 int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs)
66 {
67 	u32 head, tail;
68 	int wait_cnt;
69 
70 	tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL);
71 	wait_cnt = 0;
72 	while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
73 		head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD);
74 		if (tail == head)
75 			break;
76 
77 		usleep_range(100, 200);
78 	}
79 
80 	if (wait_cnt >= HNS_MAX_WAIT_CNT) {
81 		dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n");
82 		return -EBUSY;
83 	}
84 
85 	return 0;
86 }
87 
88 /**
89  *hns_rcb_reset_ring_hw - ring reset
90  *@q: ring struct pointer
91  */
92 void hns_rcb_reset_ring_hw(struct hnae_queue *q)
93 {
94 	u32 wait_cnt;
95 	u32 try_cnt = 0;
96 	u32 could_ret;
97 
98 	u32 tx_fbd_num;
99 
100 	while (try_cnt++ < RCB_RESET_TRY_TIMES) {
101 		usleep_range(100, 200);
102 		tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
103 		if (tx_fbd_num)
104 			continue;
105 
106 		dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
107 
108 		dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
109 
110 		msleep(20);
111 		could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
112 
113 		wait_cnt = 0;
114 		while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
115 			dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
116 
117 			dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
118 
119 			msleep(20);
120 			could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
121 
122 			wait_cnt++;
123 		}
124 
125 		dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
126 
127 		if (could_ret)
128 			break;
129 	}
130 
131 	if (try_cnt >= RCB_RESET_TRY_TIMES)
132 		dev_err(q->dev->dev, "port%d reset ring fail\n",
133 			hns_ae_get_vf_cb(q->handle)->port_index);
134 }
135 
136 /**
137  *hns_rcb_int_ctrl_hw - rcb irq enable control
138  *@q: hnae queue struct pointer
139  *@flag:ring flag tx or rx
140  *@mask:mask
141  */
142 void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
143 {
144 	u32 int_mask_en = !!mask;
145 
146 	if (flag & RCB_INT_FLAG_TX) {
147 		dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
148 		dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
149 			       int_mask_en);
150 	}
151 
152 	if (flag & RCB_INT_FLAG_RX) {
153 		dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
154 		dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
155 			       int_mask_en);
156 	}
157 }
158 
159 void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
160 {
161 	if (flag & RCB_INT_FLAG_TX) {
162 		dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
163 		dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);
164 	}
165 
166 	if (flag & RCB_INT_FLAG_RX) {
167 		dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);
168 		dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);
169 	}
170 }
171 
172 void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
173 {
174 	u32 int_mask_en = !!mask;
175 
176 	if (flag & RCB_INT_FLAG_TX)
177 		dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
178 
179 	if (flag & RCB_INT_FLAG_RX)
180 		dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
181 }
182 
183 void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag)
184 {
185 	if (flag & RCB_INT_FLAG_TX)
186 		dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);
187 
188 	if (flag & RCB_INT_FLAG_RX)
189 		dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);
190 }
191 
192 /**
193  *hns_rcb_ring_enable_hw - enable ring
194  *@ring: rcb ring
195  */
196 void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)
197 {
198 	dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
199 }
200 
201 void hns_rcb_start(struct hnae_queue *q, u32 val)
202 {
203 	hns_rcb_ring_enable_hw(q, val);
204 }
205 
206 /**
207  *hns_rcb_common_init_commit_hw - make rcb common init completed
208  *@rcb_common: rcb common device
209  */
210 void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)
211 {
212 	wmb();	/* Sync point before breakpoint */
213 	dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
214 	wmb();	/* Sync point after breakpoint */
215 }
216 
217 /* hns_rcb_set_tx_ring_bs - init rcb ring buf size regester
218  *@q: hnae_queue
219  *@buf_size: buffer size set to hw
220  */
221 void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size)
222 {
223 	u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
224 
225 	dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,
226 		       bd_size_type);
227 }
228 
229 /* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester
230  *@q: hnae_queue
231  *@buf_size: buffer size set to hw
232  */
233 void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size)
234 {
235 	u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
236 
237 	dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
238 		       bd_size_type);
239 }
240 
241 /**
242  *hns_rcb_ring_init - init rcb ring
243  *@ring_pair: ring pair control block
244  *@ring_type: ring type, RX_RING or TX_RING
245  */
246 static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)
247 {
248 	struct hnae_queue *q = &ring_pair->q;
249 	struct hnae_ring *ring =
250 		(ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;
251 	dma_addr_t dma = ring->desc_dma_addr;
252 
253 	if (ring_type == RX_RING) {
254 		dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
255 			       (u32)dma);
256 		dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
257 			       (u32)((dma >> 31) >> 1));
258 
259 		hns_rcb_set_rx_ring_bs(q, ring->buf_size);
260 
261 		dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
262 			       ring_pair->port_id_in_comm);
263 		dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
264 			       ring_pair->port_id_in_comm);
265 	} else {
266 		dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,
267 			       (u32)dma);
268 		dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,
269 			       (u32)((dma >> 31) >> 1));
270 
271 		hns_rcb_set_tx_ring_bs(q, ring->buf_size);
272 
273 		dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,
274 			       ring_pair->port_id_in_comm);
275 		dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,
276 			ring_pair->port_id_in_comm + HNS_RCB_TX_PKTLINE_OFFSET);
277 	}
278 }
279 
280 /**
281  *hns_rcb_init_hw - init rcb hardware
282  *@ring: rcb ring
283  */
284 void hns_rcb_init_hw(struct ring_pair_cb *ring)
285 {
286 	hns_rcb_ring_init(ring, RX_RING);
287 	hns_rcb_ring_init(ring, TX_RING);
288 }
289 
290 /**
291  *hns_rcb_set_port_desc_cnt - set rcb port description num
292  *@rcb_common: rcb_common device
293  *@port_idx:port index
294  *@desc_cnt:BD num
295  */
296 static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common,
297 				      u32 port_idx, u32 desc_cnt)
298 {
299 	dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,
300 		       desc_cnt);
301 }
302 
303 static void hns_rcb_set_port_timeout(
304 	struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
305 {
306 	if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
307 		dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG,
308 			       timeout * HNS_RCB_CLK_FREQ_MHZ);
309 	} else if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
310 		if (timeout > HNS_RCB_DEF_GAP_TIME_USECS)
311 			dsaf_write_dev(rcb_common,
312 				       RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
313 				       HNS_RCB_DEF_GAP_TIME_USECS);
314 		else
315 			dsaf_write_dev(rcb_common,
316 				       RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
317 				       timeout);
318 
319 		dsaf_write_dev(rcb_common,
320 			       RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
321 			       timeout);
322 	} else {
323 		dsaf_write_dev(rcb_common,
324 			       RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
325 			       timeout);
326 	}
327 }
328 
329 static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common)
330 {
331 	if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
332 		return HNS_RCB_SERVICE_NW_ENGINE_NUM;
333 	else
334 		return HNS_RCB_DEBUG_NW_ENGINE_NUM;
335 }
336 
337 /*clr rcb comm exception irq**/
338 static void hns_rcb_comm_exc_irq_en(
339 			struct rcb_common_cb *rcb_common, int en)
340 {
341 	u32 clr_vlue = 0xfffffffful;
342 	u32 msk_vlue = en ? 0 : 0xfffffffful;
343 
344 	/* clr int*/
345 	dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);
346 
347 	dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);
348 
349 	dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);
350 
351 	dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);
352 	dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);
353 
354 	/*en msk*/
355 	dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);
356 
357 	dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);
358 
359 	/*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/
360 	dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);
361 
362 	dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);
363 	dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);
364 }
365 
366 /**
367  *hns_rcb_common_init_hw - init rcb common hardware
368  *@rcb_common: rcb_common device
369  *retuen 0 - success , negative --fail
370  */
371 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common)
372 {
373 	u32 reg_val;
374 	int i;
375 	int port_num = hns_rcb_common_get_port_num(rcb_common);
376 
377 	hns_rcb_comm_exc_irq_en(rcb_common, 0);
378 
379 	reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);
380 	if (0x1 != (reg_val & 0x1)) {
381 		dev_err(rcb_common->dsaf_dev->dev,
382 			"RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);
383 		return -EBUSY;
384 	}
385 
386 	for (i = 0; i < port_num; i++) {
387 		hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num);
388 		hns_rcb_set_rx_coalesced_frames(
389 			rcb_common, i, HNS_RCB_DEF_RX_COALESCED_FRAMES);
390 		if (!AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver) &&
391 		    !HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
392 			hns_rcb_set_tx_coalesced_frames(
393 				rcb_common, i, HNS_RCB_DEF_TX_COALESCED_FRAMES);
394 		hns_rcb_set_port_timeout(
395 			rcb_common, i, HNS_RCB_DEF_COALESCED_USECS);
396 	}
397 
398 	dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,
399 		       HNS_RCB_COMMON_ENDIAN);
400 
401 	if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
402 		dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);
403 		dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);
404 	} else {
405 		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
406 				 RCB_COM_CFG_FNA_B, false);
407 		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
408 				 RCB_COM_CFG_FA_B, true);
409 		dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,
410 				 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K);
411 	}
412 
413 	return 0;
414 }
415 
416 int hns_rcb_buf_size2type(u32 buf_size)
417 {
418 	int bd_size_type;
419 
420 	switch (buf_size) {
421 	case 512:
422 		bd_size_type = HNS_BD_SIZE_512_TYPE;
423 		break;
424 	case 1024:
425 		bd_size_type = HNS_BD_SIZE_1024_TYPE;
426 		break;
427 	case 2048:
428 		bd_size_type = HNS_BD_SIZE_2048_TYPE;
429 		break;
430 	case 4096:
431 		bd_size_type = HNS_BD_SIZE_4096_TYPE;
432 		break;
433 	default:
434 		bd_size_type = -EINVAL;
435 	}
436 
437 	return bd_size_type;
438 }
439 
440 static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type)
441 {
442 	struct hnae_ring *ring;
443 	struct rcb_common_cb *rcb_common;
444 	struct ring_pair_cb *ring_pair_cb;
445 	u16 desc_num, mdnum_ppkt;
446 	bool irq_idx, is_ver1;
447 
448 	ring_pair_cb = container_of(q, struct ring_pair_cb, q);
449 	is_ver1 = AE_IS_VER1(ring_pair_cb->rcb_common->dsaf_dev->dsaf_ver);
450 	if (ring_type == RX_RING) {
451 		ring = &q->rx_ring;
452 		ring->io_base = ring_pair_cb->q.io_base;
453 		irq_idx = HNS_RCB_IRQ_IDX_RX;
454 		mdnum_ppkt = HNS_RCB_RING_MAX_BD_PER_PKT;
455 	} else {
456 		ring = &q->tx_ring;
457 		ring->io_base = ring_pair_cb->q.io_base +
458 			HNS_RCB_TX_REG_OFFSET;
459 		irq_idx = HNS_RCB_IRQ_IDX_TX;
460 		mdnum_ppkt = is_ver1 ? HNS_RCB_RING_MAX_TXBD_PER_PKT :
461 				 HNS_RCBV2_RING_MAX_TXBD_PER_PKT;
462 	}
463 
464 	rcb_common = ring_pair_cb->rcb_common;
465 	desc_num = rcb_common->dsaf_dev->desc_num;
466 
467 	ring->desc = NULL;
468 	ring->desc_cb = NULL;
469 
470 	ring->irq = ring_pair_cb->virq[irq_idx];
471 	ring->desc_dma_addr = 0;
472 
473 	ring->buf_size = RCB_DEFAULT_BUFFER_SIZE;
474 	ring->desc_num = desc_num;
475 	ring->max_desc_num_per_pkt = mdnum_ppkt;
476 	ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE;
477 	ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE;
478 	ring->next_to_use = 0;
479 	ring->next_to_clean = 0;
480 }
481 
482 static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb)
483 {
484 	ring_pair_cb->q.handle = NULL;
485 
486 	hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING);
487 	hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING);
488 }
489 
490 static int hns_rcb_get_port_in_comm(
491 	struct rcb_common_cb *rcb_common, int ring_idx)
492 {
493 	return ring_idx / (rcb_common->max_q_per_vf * rcb_common->max_vfn);
494 }
495 
496 #define SERVICE_RING_IRQ_IDX(v1) \
497 	((v1) ? HNS_SERVICE_RING_IRQ_IDX : HNSV2_SERVICE_RING_IRQ_IDX)
498 static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common)
499 {
500 	bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
501 
502 	if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
503 		return SERVICE_RING_IRQ_IDX(is_ver1);
504 	else
505 		return  HNS_DEBUG_RING_IRQ_IDX;
506 }
507 
508 #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\
509 	((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid))
510 /**
511  *hns_rcb_get_cfg - get rcb config
512  *@rcb_common: rcb common device
513  */
514 int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common)
515 {
516 	struct ring_pair_cb *ring_pair_cb;
517 	u32 i;
518 	u32 ring_num = rcb_common->ring_num;
519 	int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common);
520 	struct platform_device *pdev =
521 		to_platform_device(rcb_common->dsaf_dev->dev);
522 	bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
523 
524 	for (i = 0; i < ring_num; i++) {
525 		ring_pair_cb = &rcb_common->ring_pair_cb[i];
526 		ring_pair_cb->rcb_common = rcb_common;
527 		ring_pair_cb->dev = rcb_common->dsaf_dev->dev;
528 		ring_pair_cb->index = i;
529 		ring_pair_cb->q.io_base =
530 			RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);
531 		ring_pair_cb->port_id_in_comm =
532 			hns_rcb_get_port_in_comm(rcb_common, i);
533 		ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] =
534 		is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2) :
535 			  platform_get_irq(pdev, base_irq_idx + i * 3 + 1);
536 		ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] =
537 		is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2 + 1) :
538 			  platform_get_irq(pdev, base_irq_idx + i * 3);
539 		if ((ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] == -EPROBE_DEFER) ||
540 		    (ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] == -EPROBE_DEFER))
541 			return -EPROBE_DEFER;
542 
543 		ring_pair_cb->q.phy_base =
544 			RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i);
545 		hns_rcb_ring_pair_get_cfg(ring_pair_cb);
546 	}
547 
548 	return 0;
549 }
550 
551 /**
552  *hns_rcb_get_rx_coalesced_frames - get rcb port rx coalesced frames
553  *@rcb_common: rcb_common device
554  *@port_idx:port id in comm
555  *
556  *Returns: coalesced_frames
557  */
558 u32 hns_rcb_get_rx_coalesced_frames(
559 	struct rcb_common_cb *rcb_common, u32 port_idx)
560 {
561 	return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4);
562 }
563 
564 /**
565  *hns_rcb_get_tx_coalesced_frames - get rcb port tx coalesced frames
566  *@rcb_common: rcb_common device
567  *@port_idx:port id in comm
568  *
569  *Returns: coalesced_frames
570  */
571 u32 hns_rcb_get_tx_coalesced_frames(
572 	struct rcb_common_cb *rcb_common, u32 port_idx)
573 {
574 	u64 reg;
575 
576 	reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
577 	return dsaf_read_dev(rcb_common, reg);
578 }
579 
580 /**
581  *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out
582  *@rcb_common: rcb_common device
583  *@port_idx:port id in comm
584  *
585  *Returns: time_out
586  */
587 u32 hns_rcb_get_coalesce_usecs(
588 	struct rcb_common_cb *rcb_common, u32 port_idx)
589 {
590 	if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver))
591 		return dsaf_read_dev(rcb_common, RCB_CFG_OVERTIME_REG) /
592 		       HNS_RCB_CLK_FREQ_MHZ;
593 	else
594 		return dsaf_read_dev(rcb_common,
595 				     RCB_PORT_CFG_OVERTIME_REG + port_idx * 4);
596 }
597 
598 /**
599  *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out
600  *@rcb_common: rcb_common device
601  *@port_idx:port id in comm
602  *@timeout:tx/rx time for coalesced time_out
603  *
604  * Returns:
605  * Zero for success, or an error code in case of failure
606  */
607 int hns_rcb_set_coalesce_usecs(
608 	struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
609 {
610 	u32 old_timeout = hns_rcb_get_coalesce_usecs(rcb_common, port_idx);
611 
612 	if (timeout == old_timeout)
613 		return 0;
614 
615 	if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
616 		if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
617 			dev_err(rcb_common->dsaf_dev->dev,
618 				"error: not support coalesce_usecs setting!\n");
619 			return -EINVAL;
620 		}
621 	}
622 	if (timeout > HNS_RCB_MAX_COALESCED_USECS || timeout == 0) {
623 		dev_err(rcb_common->dsaf_dev->dev,
624 			"error: coalesce_usecs setting supports 1~1023us\n");
625 		return -EINVAL;
626 	}
627 	hns_rcb_set_port_timeout(rcb_common, port_idx, timeout);
628 	return 0;
629 }
630 
631 /**
632  *hns_rcb_set_tx_coalesced_frames - set rcb coalesced frames
633  *@rcb_common: rcb_common device
634  *@port_idx:port id in comm
635  *@coalesced_frames:tx/rx BD num for coalesced frames
636  *
637  * Returns:
638  * Zero for success, or an error code in case of failure
639  */
640 int hns_rcb_set_tx_coalesced_frames(
641 	struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
642 {
643 	u32 old_waterline =
644 		hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx);
645 	u64 reg;
646 
647 	if (coalesced_frames == old_waterline)
648 		return 0;
649 
650 	if (coalesced_frames != 1) {
651 		dev_err(rcb_common->dsaf_dev->dev,
652 			"error: not support tx coalesce_frames setting!\n");
653 		return -EINVAL;
654 	}
655 
656 	reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
657 	dsaf_write_dev(rcb_common, reg,	coalesced_frames);
658 	return 0;
659 }
660 
661 /**
662  *hns_rcb_set_rx_coalesced_frames - set rcb rx coalesced frames
663  *@rcb_common: rcb_common device
664  *@port_idx:port id in comm
665  *@coalesced_frames:tx/rx BD num for coalesced frames
666  *
667  * Returns:
668  * Zero for success, or an error code in case of failure
669  */
670 int hns_rcb_set_rx_coalesced_frames(
671 	struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
672 {
673 	u32 old_waterline =
674 		hns_rcb_get_rx_coalesced_frames(rcb_common, port_idx);
675 
676 	if (coalesced_frames == old_waterline)
677 		return 0;
678 
679 	if (coalesced_frames >= rcb_common->desc_num ||
680 	    coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES ||
681 	    coalesced_frames < HNS_RCB_MIN_COALESCED_FRAMES) {
682 		dev_err(rcb_common->dsaf_dev->dev,
683 			"error: not support coalesce_frames setting!\n");
684 		return -EINVAL;
685 	}
686 
687 	dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,
688 		       coalesced_frames);
689 	return 0;
690 }
691 
692 /**
693  *hns_rcb_get_queue_mode - get max VM number and max ring number per VM
694  *						accordding to dsaf mode
695  *@dsaf_mode: dsaf mode
696  *@max_vfn : max vfn number
697  *@max_q_per_vf:max ring number per vm
698  */
699 void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, u16 *max_vfn,
700 			    u16 *max_q_per_vf)
701 {
702 	switch (dsaf_mode) {
703 	case DSAF_MODE_DISABLE_6PORT_0VM:
704 		*max_vfn = 1;
705 		*max_q_per_vf = 16;
706 		break;
707 	case DSAF_MODE_DISABLE_FIX:
708 	case DSAF_MODE_DISABLE_SP:
709 		*max_vfn = 1;
710 		*max_q_per_vf = 1;
711 		break;
712 	case DSAF_MODE_DISABLE_2PORT_64VM:
713 		*max_vfn = 64;
714 		*max_q_per_vf = 1;
715 		break;
716 	case DSAF_MODE_DISABLE_6PORT_16VM:
717 		*max_vfn = 16;
718 		*max_q_per_vf = 1;
719 		break;
720 	default:
721 		*max_vfn = 1;
722 		*max_q_per_vf = 16;
723 		break;
724 	}
725 }
726 
727 static int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev)
728 {
729 	switch (dsaf_dev->dsaf_mode) {
730 	case DSAF_MODE_ENABLE_FIX:
731 	case DSAF_MODE_DISABLE_SP:
732 		return 1;
733 
734 	case DSAF_MODE_DISABLE_FIX:
735 		return 6;
736 
737 	case DSAF_MODE_ENABLE_0VM:
738 		return 32;
739 
740 	case DSAF_MODE_DISABLE_6PORT_0VM:
741 	case DSAF_MODE_ENABLE_16VM:
742 	case DSAF_MODE_DISABLE_6PORT_2VM:
743 	case DSAF_MODE_DISABLE_6PORT_16VM:
744 	case DSAF_MODE_DISABLE_6PORT_4VM:
745 	case DSAF_MODE_ENABLE_8VM:
746 		return 96;
747 
748 	case DSAF_MODE_DISABLE_2PORT_16VM:
749 	case DSAF_MODE_DISABLE_2PORT_8VM:
750 	case DSAF_MODE_ENABLE_32VM:
751 	case DSAF_MODE_DISABLE_2PORT_64VM:
752 	case DSAF_MODE_ENABLE_128VM:
753 		return 128;
754 
755 	default:
756 		dev_warn(dsaf_dev->dev,
757 			 "get ring num fail,use default!dsaf_mode=%d\n",
758 			 dsaf_dev->dsaf_mode);
759 		return 128;
760 	}
761 }
762 
763 static u8 __iomem *hns_rcb_common_get_vaddr(struct rcb_common_cb *rcb_common)
764 {
765 	struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
766 
767 	return dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET;
768 }
769 
770 static phys_addr_t hns_rcb_common_get_paddr(struct rcb_common_cb *rcb_common)
771 {
772 	struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
773 
774 	return dsaf_dev->ppe_paddr + RCB_COMMON_REG_OFFSET;
775 }
776 
777 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev,
778 			   int comm_index)
779 {
780 	struct rcb_common_cb *rcb_common;
781 	enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
782 	u16 max_vfn;
783 	u16 max_q_per_vf;
784 	int ring_num = hns_rcb_get_ring_num(dsaf_dev);
785 
786 	rcb_common =
787 		devm_kzalloc(dsaf_dev->dev,
788 			     struct_size(rcb_common, ring_pair_cb, ring_num),
789 			     GFP_KERNEL);
790 	if (!rcb_common) {
791 		dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n");
792 		return -ENOMEM;
793 	}
794 	rcb_common->comm_index = comm_index;
795 	rcb_common->ring_num = ring_num;
796 	rcb_common->dsaf_dev = dsaf_dev;
797 
798 	rcb_common->desc_num = dsaf_dev->desc_num;
799 
800 	hns_rcb_get_queue_mode(dsaf_mode, &max_vfn, &max_q_per_vf);
801 	rcb_common->max_vfn = max_vfn;
802 	rcb_common->max_q_per_vf = max_q_per_vf;
803 
804 	rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common);
805 	rcb_common->phy_base = hns_rcb_common_get_paddr(rcb_common);
806 
807 	dsaf_dev->rcb_common[comm_index] = rcb_common;
808 	return 0;
809 }
810 
811 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev,
812 			     u32 comm_index)
813 {
814 	dsaf_dev->rcb_common[comm_index] = NULL;
815 }
816 
817 void hns_rcb_update_stats(struct hnae_queue *queue)
818 {
819 	struct ring_pair_cb *ring =
820 		container_of(queue, struct ring_pair_cb, q);
821 	struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev;
822 	struct ppe_common_cb *ppe_common
823 		= dsaf_dev->ppe_common[ring->rcb_common->comm_index];
824 	struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
825 
826 	hw_stats->rx_pkts += dsaf_read_dev(queue,
827 			 RCB_RING_RX_RING_PKTNUM_RECORD_REG);
828 	dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);
829 
830 	hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common,
831 			 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index);
832 	hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common,
833 			 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index);
834 
835 	hw_stats->tx_pkts += dsaf_read_dev(queue,
836 			 RCB_RING_TX_RING_PKTNUM_RECORD_REG);
837 	dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);
838 
839 	hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common,
840 			 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index);
841 	hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common,
842 			 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index);
843 }
844 
845 /**
846  *hns_rcb_get_stats - get rcb statistic
847  *@ring: rcb ring
848  *@data:statistic value
849  */
850 void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)
851 {
852 	u64 *regs_buff = data;
853 	struct ring_pair_cb *ring =
854 		container_of(queue, struct ring_pair_cb, q);
855 	struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
856 
857 	regs_buff[0] = hw_stats->tx_pkts;
858 	regs_buff[1] = hw_stats->ppe_tx_ok_pkts;
859 	regs_buff[2] = hw_stats->ppe_tx_drop_pkts;
860 	regs_buff[3] =
861 		dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
862 
863 	regs_buff[4] = queue->tx_ring.stats.tx_pkts;
864 	regs_buff[5] = queue->tx_ring.stats.tx_bytes;
865 	regs_buff[6] = queue->tx_ring.stats.tx_err_cnt;
866 	regs_buff[7] = queue->tx_ring.stats.io_err_cnt;
867 	regs_buff[8] = queue->tx_ring.stats.sw_err_cnt;
868 	regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt;
869 	regs_buff[10] = queue->tx_ring.stats.restart_queue;
870 	regs_buff[11] = queue->tx_ring.stats.tx_busy;
871 
872 	regs_buff[12] = hw_stats->rx_pkts;
873 	regs_buff[13] = hw_stats->ppe_rx_ok_pkts;
874 	regs_buff[14] = hw_stats->ppe_rx_drop_pkts;
875 	regs_buff[15] =
876 		dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
877 
878 	regs_buff[16] = queue->rx_ring.stats.rx_pkts;
879 	regs_buff[17] = queue->rx_ring.stats.rx_bytes;
880 	regs_buff[18] = queue->rx_ring.stats.rx_err_cnt;
881 	regs_buff[19] = queue->rx_ring.stats.io_err_cnt;
882 	regs_buff[20] = queue->rx_ring.stats.sw_err_cnt;
883 	regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt;
884 	regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt;
885 	regs_buff[23] = queue->rx_ring.stats.err_pkt_len;
886 	regs_buff[24] = queue->rx_ring.stats.non_vld_descs;
887 	regs_buff[25] = queue->rx_ring.stats.err_bd_num;
888 	regs_buff[26] = queue->rx_ring.stats.l2_err;
889 	regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err;
890 }
891 
892 /**
893  *hns_rcb_get_ring_sset_count - rcb string set count
894  *@stringset:ethtool cmd
895  *return rcb ring string set count
896  */
897 int hns_rcb_get_ring_sset_count(int stringset)
898 {
899 	if (stringset == ETH_SS_STATS)
900 		return HNS_RING_STATIC_REG_NUM;
901 
902 	return 0;
903 }
904 
905 /**
906  *hns_rcb_get_common_regs_count - rcb common regs count
907  *return regs count
908  */
909 int hns_rcb_get_common_regs_count(void)
910 {
911 	return HNS_RCB_COMMON_DUMP_REG_NUM;
912 }
913 
914 /**
915  *rcb_get_sset_count - rcb ring regs count
916  *return regs count
917  */
918 int hns_rcb_get_ring_regs_count(void)
919 {
920 	return HNS_RCB_RING_DUMP_REG_NUM;
921 }
922 
923 /**
924  *hns_rcb_get_strings - get rcb string set
925  *@stringset:string set index
926  *@data:strings name value
927  *@index:queue index
928  */
929 void hns_rcb_get_strings(int stringset, u8 *data, int index)
930 {
931 	char *buff = (char *)data;
932 
933 	if (stringset != ETH_SS_STATS)
934 		return;
935 
936 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_rcb_pkt_num", index);
937 	buff = buff + ETH_GSTRING_LEN;
938 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_tx_pkt_num", index);
939 	buff = buff + ETH_GSTRING_LEN;
940 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_drop_pkt_num", index);
941 	buff = buff + ETH_GSTRING_LEN;
942 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_fbd_num", index);
943 	buff = buff + ETH_GSTRING_LEN;
944 
945 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_pkt_num", index);
946 	buff = buff + ETH_GSTRING_LEN;
947 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_bytes", index);
948 	buff = buff + ETH_GSTRING_LEN;
949 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_err_cnt", index);
950 	buff = buff + ETH_GSTRING_LEN;
951 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_io_err", index);
952 	buff = buff + ETH_GSTRING_LEN;
953 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_sw_err", index);
954 	buff = buff + ETH_GSTRING_LEN;
955 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_seg_pkt", index);
956 	buff = buff + ETH_GSTRING_LEN;
957 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_restart_queue", index);
958 	buff = buff + ETH_GSTRING_LEN;
959 	snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_tx_busy", index);
960 	buff = buff + ETH_GSTRING_LEN;
961 
962 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_rcb_pkt_num", index);
963 	buff = buff + ETH_GSTRING_LEN;
964 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_pkt_num", index);
965 	buff = buff + ETH_GSTRING_LEN;
966 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_drop_pkt_num", index);
967 	buff = buff + ETH_GSTRING_LEN;
968 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_fbd_num", index);
969 	buff = buff + ETH_GSTRING_LEN;
970 
971 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_pkt_num", index);
972 	buff = buff + ETH_GSTRING_LEN;
973 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bytes", index);
974 	buff = buff + ETH_GSTRING_LEN;
975 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_err_cnt", index);
976 	buff = buff + ETH_GSTRING_LEN;
977 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_io_err", index);
978 	buff = buff + ETH_GSTRING_LEN;
979 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_sw_err", index);
980 	buff = buff + ETH_GSTRING_LEN;
981 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_seg_pkt", index);
982 	buff = buff + ETH_GSTRING_LEN;
983 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_reuse_pg", index);
984 	buff = buff + ETH_GSTRING_LEN;
985 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_len_err", index);
986 	buff = buff + ETH_GSTRING_LEN;
987 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_non_vld_desc_err", index);
988 	buff = buff + ETH_GSTRING_LEN;
989 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bd_num_err", index);
990 	buff = buff + ETH_GSTRING_LEN;
991 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l2_err", index);
992 	buff = buff + ETH_GSTRING_LEN;
993 	snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l3l4csum_err", index);
994 }
995 
996 void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data)
997 {
998 	u32 *regs = data;
999 	bool is_ver1 = AE_IS_VER1(rcb_com->dsaf_dev->dsaf_ver);
1000 	bool is_dbg = HNS_DSAF_IS_DEBUG(rcb_com->dsaf_dev);
1001 	u32 reg_tmp;
1002 	u32 reg_num_tmp;
1003 	u32 i = 0;
1004 
1005 	/*rcb common registers */
1006 	regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG);
1007 	regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG);
1008 	regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG);
1009 
1010 	regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG);
1011 	regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG);
1012 	regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG);
1013 	regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG);
1014 	regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG);
1015 	regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG);
1016 
1017 	regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG);
1018 	regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG);
1019 	regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG);
1020 	regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG);
1021 	regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG);
1022 	regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG);
1023 	regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG);
1024 	regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG);
1025 	regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG);
1026 	regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG);
1027 	regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG);
1028 	regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG);
1029 	regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG);
1030 	regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG);
1031 	regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG);
1032 	regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG);
1033 	regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG);
1034 	regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG);
1035 	regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG);
1036 
1037 	regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING);
1038 	regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS);
1039 	regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING);
1040 	regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD);
1041 	regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS);
1042 	regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY);
1043 	regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN);
1044 	regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK);
1045 	regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS);
1046 	regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG);
1047 
1048 	/* rcb common entry registers */
1049 	for (i = 0; i < 16; i++) { /* total 16 model registers */
1050 		regs[38 + i]
1051 			= dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i);
1052 		regs[54 + i]
1053 			= dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i);
1054 	}
1055 
1056 	reg_tmp = is_ver1 ? RCB_CFG_OVERTIME_REG : RCB_PORT_CFG_OVERTIME_REG;
1057 	reg_num_tmp = (is_ver1 || is_dbg) ? 1 : 6;
1058 	for (i = 0; i < reg_num_tmp; i++)
1059 		regs[70 + i] = dsaf_read_dev(rcb_com, reg_tmp);
1060 
1061 	regs[76] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG);
1062 	regs[77] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG);
1063 
1064 	/* mark end of rcb common regs */
1065 	for (i = 78; i < 80; i++)
1066 		regs[i] = 0xcccccccc;
1067 }
1068 
1069 void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data)
1070 {
1071 	u32 *regs = data;
1072 	struct ring_pair_cb *ring_pair
1073 		= container_of(queue, struct ring_pair_cb, q);
1074 	u32 i = 0;
1075 
1076 	/*rcb ring registers */
1077 	regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG);
1078 	regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG);
1079 	regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG);
1080 	regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG);
1081 	regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG);
1082 	regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG);
1083 	regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG);
1084 	regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
1085 	regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG);
1086 
1087 	regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG);
1088 	regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG);
1089 	regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG);
1090 	regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG);
1091 	regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG);
1092 	regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG);
1093 	regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG);
1094 	regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
1095 	regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG);
1096 	regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG);
1097 
1098 	regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG);
1099 	regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG);
1100 	regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG);
1101 	regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG);
1102 	regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST);
1103 	regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST);
1104 	regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG);
1105 
1106 	regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG);
1107 	regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG);
1108 	regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG);
1109 	regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG);
1110 	regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG);
1111 	regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG);
1112 	regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG);
1113 	regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG);
1114 
1115 	/* mark end of ring regs */
1116 	for (i = 35; i < 40; i++)
1117 		regs[i] = 0xcccccc00 + ring_pair->index;
1118 }
1119