1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014-2015 Hisilicon Limited. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/kernel.h> 8 #include <linux/init.h> 9 #include <linux/netdevice.h> 10 #include <linux/etherdevice.h> 11 #include <linux/platform_device.h> 12 13 #include "hns_dsaf_ppe.h" 14 15 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value) 16 { 17 dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value); 18 } 19 20 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb, 21 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]) 22 { 23 u32 key_item; 24 25 for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++) 26 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4, 27 rss_key[key_item]); 28 } 29 30 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb, 31 const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]) 32 { 33 int i; 34 int reg_value; 35 36 for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) { 37 reg_value = dsaf_read_dev(ppe_cb, 38 PPEV2_INDRECTION_TBL_REG + i * 0x4); 39 40 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M, 41 PPEV2_CFG_RSS_TBL_4N0_S, 42 rss_tab[i * 4 + 0] & 0x1F); 43 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M, 44 PPEV2_CFG_RSS_TBL_4N1_S, 45 rss_tab[i * 4 + 1] & 0x1F); 46 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M, 47 PPEV2_CFG_RSS_TBL_4N2_S, 48 rss_tab[i * 4 + 2] & 0x1F); 49 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M, 50 PPEV2_CFG_RSS_TBL_4N3_S, 51 rss_tab[i * 4 + 3] & 0x1F); 52 dsaf_write_dev( 53 ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value); 54 } 55 } 56 57 static u8 __iomem * 58 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common) 59 { 60 return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET; 61 } 62 63 /** 64 * hns_ppe_common_get_cfg - get ppe common config 65 * @dsaf_dev: dasf device 66 * @comm_index: common index 67 * return 0 - success , negative --fail 68 */ 69 static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index) 70 { 71 struct ppe_common_cb *ppe_common; 72 int ppe_num; 73 74 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 75 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM; 76 else 77 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM; 78 79 ppe_common = devm_kzalloc(dsaf_dev->dev, 80 struct_size(ppe_common, ppe_cb, ppe_num), 81 GFP_KERNEL); 82 if (!ppe_common) 83 return -ENOMEM; 84 85 ppe_common->ppe_num = ppe_num; 86 ppe_common->dsaf_dev = dsaf_dev; 87 ppe_common->comm_index = comm_index; 88 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 89 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE; 90 else 91 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG; 92 ppe_common->dev = dsaf_dev->dev; 93 94 ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common); 95 96 dsaf_dev->ppe_common[comm_index] = ppe_common; 97 98 return 0; 99 } 100 101 static void 102 hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index) 103 { 104 dsaf_dev->ppe_common[comm_index] = NULL; 105 } 106 107 static u8 __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common, 108 int ppe_idx) 109 { 110 return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET; 111 } 112 113 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common) 114 { 115 u32 i; 116 struct hns_ppe_cb *ppe_cb; 117 u32 ppe_num = ppe_common->ppe_num; 118 119 for (i = 0; i < ppe_num; i++) { 120 ppe_cb = &ppe_common->ppe_cb[i]; 121 ppe_cb->dev = ppe_common->dev; 122 ppe_cb->next = NULL; 123 ppe_cb->ppe_common_cb = ppe_common; 124 ppe_cb->index = i; 125 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i); 126 ppe_cb->virq = 0; 127 } 128 } 129 130 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb) 131 { 132 dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG, 133 PPE_CNT_CLR_CE_B, 1); 134 } 135 136 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en) 137 { 138 dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en); 139 } 140 141 /** 142 * hns_ppe_checksum_hw - set ppe checksum caculate 143 * @ppe_cb: ppe device 144 * @value: value 145 */ 146 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value) 147 { 148 dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG, 149 0xfffffff, 0, value); 150 } 151 152 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common, 153 enum ppe_qid_mode qid_mdoe) 154 { 155 dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG, 156 PPE_CFG_QID_MODE_CF_QID_MODE_M, 157 PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe); 158 } 159 160 /** 161 * hns_ppe_set_qid - set ppe qid 162 * @ppe_common: ppe common device 163 * @qid: queue id 164 */ 165 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid) 166 { 167 u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 168 169 if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 170 PPE_CFG_QID_MODE_DEF_QID_S)) { 171 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 172 PPE_CFG_QID_MODE_DEF_QID_S, qid); 173 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod); 174 } 175 } 176 177 /** 178 * hns_ppe_set_port_mode - set port mode 179 * @ppe_cb: ppe device 180 * @mode: port mode 181 */ 182 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb, 183 enum ppe_port_mode mode) 184 { 185 dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode); 186 } 187 188 /** 189 * hns_ppe_common_init_hw - init ppe common device 190 * @ppe_common: ppe common device 191 * 192 * Return 0 on success, negative on failure 193 */ 194 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common) 195 { 196 enum ppe_qid_mode qid_mode; 197 struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev; 198 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode; 199 200 dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0); 201 msleep(100); 202 dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1); 203 msleep(100); 204 205 if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) { 206 switch (dsaf_mode) { 207 case DSAF_MODE_ENABLE_FIX: 208 case DSAF_MODE_DISABLE_FIX: 209 qid_mode = PPE_QID_MODE0; 210 hns_ppe_set_qid(ppe_common, 0); 211 break; 212 case DSAF_MODE_ENABLE_0VM: 213 case DSAF_MODE_DISABLE_2PORT_64VM: 214 qid_mode = PPE_QID_MODE3; 215 break; 216 case DSAF_MODE_ENABLE_8VM: 217 case DSAF_MODE_DISABLE_2PORT_16VM: 218 qid_mode = PPE_QID_MODE4; 219 break; 220 case DSAF_MODE_ENABLE_16VM: 221 case DSAF_MODE_DISABLE_6PORT_0VM: 222 qid_mode = PPE_QID_MODE5; 223 break; 224 case DSAF_MODE_ENABLE_32VM: 225 case DSAF_MODE_DISABLE_6PORT_16VM: 226 qid_mode = PPE_QID_MODE2; 227 break; 228 case DSAF_MODE_ENABLE_128VM: 229 case DSAF_MODE_DISABLE_6PORT_4VM: 230 qid_mode = PPE_QID_MODE1; 231 break; 232 case DSAF_MODE_DISABLE_2PORT_8VM: 233 qid_mode = PPE_QID_MODE7; 234 break; 235 case DSAF_MODE_DISABLE_6PORT_2VM: 236 qid_mode = PPE_QID_MODE6; 237 break; 238 default: 239 dev_err(ppe_common->dev, 240 "get ppe queue mode failed! dsaf_mode=%d\n", 241 dsaf_mode); 242 return -EINVAL; 243 } 244 hns_ppe_set_qid_mode(ppe_common, qid_mode); 245 } 246 247 dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG, 248 PPE_COMMON_CNT_CLR_CE_B, 1); 249 250 return 0; 251 } 252 253 /*clr ppe exception irq*/ 254 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en) 255 { 256 u32 clr_vlue = 0xfffffffful; 257 u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/ 258 u32 vld_msk = 0; 259 260 /*only care bit 0,1,7*/ 261 dsaf_set_bit(vld_msk, 0, 1); 262 dsaf_set_bit(vld_msk, 1, 1); 263 dsaf_set_bit(vld_msk, 7, 1); 264 265 /*clr sts**/ 266 dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue); 267 268 /*for some reserved bits, so set 0**/ 269 dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk); 270 } 271 272 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb) 273 { 274 int wait_cnt; 275 u32 val; 276 277 wait_cnt = 0; 278 while (wait_cnt++ < HNS_MAX_WAIT_CNT) { 279 val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU; 280 if (!val) 281 break; 282 283 usleep_range(100, 200); 284 } 285 286 if (wait_cnt >= HNS_MAX_WAIT_CNT) { 287 dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n", 288 val); 289 return -EBUSY; 290 } 291 292 return 0; 293 } 294 295 /** 296 * hns_ppe_init_hw - init ppe 297 * @ppe_cb: ppe device 298 */ 299 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb) 300 { 301 struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb; 302 u32 port = ppe_cb->index; 303 struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev; 304 int i; 305 306 /* get default RSS key */ 307 netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE); 308 309 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0); 310 mdelay(10); 311 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1); 312 313 /* clr and msk except irq*/ 314 hns_ppe_exc_irq_en(ppe_cb, 0); 315 316 if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) { 317 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE); 318 dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0); 319 } else { 320 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE); 321 } 322 323 hns_ppe_checksum_hw(ppe_cb, 0xffffffff); 324 hns_ppe_cnt_clr_ce(ppe_cb); 325 326 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 327 hns_ppe_set_vlan_strip(ppe_cb, 0); 328 329 dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG, 330 HNS_PPEV2_MAX_FRAME_LEN); 331 332 /* set default RSS key in h/w */ 333 hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key); 334 335 /* Set default indrection table in h/w */ 336 for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++) 337 ppe_cb->rss_indir_table[i] = i; 338 hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table); 339 } 340 } 341 342 /** 343 * hns_ppe_uninit_hw - uninit ppe 344 * @ppe_cb: ppe device 345 */ 346 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb) 347 { 348 u32 port; 349 350 if (ppe_cb->ppe_common_cb) { 351 struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev; 352 353 port = ppe_cb->index; 354 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0); 355 } 356 } 357 358 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common) 359 { 360 u32 i; 361 362 for (i = 0; i < ppe_common->ppe_num; i++) { 363 if (ppe_common->dsaf_dev->mac_cb[i]) 364 hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]); 365 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb)); 366 } 367 } 368 369 void hns_ppe_uninit(struct dsaf_device *dsaf_dev) 370 { 371 u32 i; 372 373 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 374 if (dsaf_dev->ppe_common[i]) 375 hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]); 376 hns_rcb_common_free_cfg(dsaf_dev, i); 377 hns_ppe_common_free_cfg(dsaf_dev, i); 378 } 379 } 380 381 /** 382 * hns_ppe_reset_common - reinit ppe/rcb hw 383 * @dsaf_dev: dasf device 384 * @ppe_common_index: the index 385 * return void 386 */ 387 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index) 388 { 389 u32 i; 390 int ret; 391 struct ppe_common_cb *ppe_common; 392 393 ppe_common = dsaf_dev->ppe_common[ppe_common_index]; 394 ret = hns_ppe_common_init_hw(ppe_common); 395 if (ret) 396 return; 397 398 for (i = 0; i < ppe_common->ppe_num; i++) { 399 /* We only need to initiate ppe when the port exists */ 400 if (dsaf_dev->mac_cb[i]) 401 hns_ppe_init_hw(&ppe_common->ppe_cb[i]); 402 } 403 404 ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]); 405 if (ret) 406 return; 407 408 hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]); 409 } 410 411 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb) 412 { 413 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 414 415 hw_stats->rx_pkts_from_sw 416 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 417 hw_stats->rx_pkts 418 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 419 hw_stats->rx_drop_no_bd 420 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 421 hw_stats->rx_alloc_buf_fail 422 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 423 hw_stats->rx_alloc_buf_wait 424 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 425 hw_stats->rx_drop_no_buf 426 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 427 hw_stats->rx_err_fifo_full 428 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 429 430 hw_stats->tx_bd_form_rcb 431 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 432 hw_stats->tx_pkts_from_rcb 433 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 434 hw_stats->tx_pkts 435 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 436 hw_stats->tx_err_fifo_empty 437 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 438 hw_stats->tx_err_checksum 439 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 440 } 441 442 int hns_ppe_get_sset_count(int stringset) 443 { 444 if (stringset == ETH_SS_STATS) 445 return ETH_PPE_STATIC_NUM; 446 return 0; 447 } 448 449 int hns_ppe_get_regs_count(void) 450 { 451 return ETH_PPE_DUMP_NUM; 452 } 453 454 /** 455 * hns_ppe_get_strings - get ppe srting 456 * @ppe_cb: ppe device 457 * @stringset: string set type 458 * @data: output string 459 */ 460 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data) 461 { 462 int index = ppe_cb->index; 463 u8 *buff = data; 464 465 ethtool_sprintf(&buff, "ppe%d_rx_sw_pkt", index); 466 ethtool_sprintf(&buff, "ppe%d_rx_pkt_ok", index); 467 ethtool_sprintf(&buff, "ppe%d_rx_drop_pkt_no_bd", index); 468 ethtool_sprintf(&buff, "ppe%d_rx_alloc_buf_fail", index); 469 ethtool_sprintf(&buff, "ppe%d_rx_alloc_buf_wait", index); 470 ethtool_sprintf(&buff, "ppe%d_rx_pkt_drop_no_buf", index); 471 ethtool_sprintf(&buff, "ppe%d_rx_pkt_err_fifo_full", index); 472 473 ethtool_sprintf(&buff, "ppe%d_tx_bd", index); 474 ethtool_sprintf(&buff, "ppe%d_tx_pkt", index); 475 ethtool_sprintf(&buff, "ppe%d_tx_pkt_ok", index); 476 ethtool_sprintf(&buff, "ppe%d_tx_pkt_err_fifo_empty", index); 477 ethtool_sprintf(&buff, "ppe%d_tx_pkt_err_csum_fail", index); 478 } 479 480 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data) 481 { 482 u64 *regs_buff = data; 483 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 484 485 regs_buff[0] = hw_stats->rx_pkts_from_sw; 486 regs_buff[1] = hw_stats->rx_pkts; 487 regs_buff[2] = hw_stats->rx_drop_no_bd; 488 regs_buff[3] = hw_stats->rx_alloc_buf_fail; 489 regs_buff[4] = hw_stats->rx_alloc_buf_wait; 490 regs_buff[5] = hw_stats->rx_drop_no_buf; 491 regs_buff[6] = hw_stats->rx_err_fifo_full; 492 493 regs_buff[7] = hw_stats->tx_bd_form_rcb; 494 regs_buff[8] = hw_stats->tx_pkts_from_rcb; 495 regs_buff[9] = hw_stats->tx_pkts; 496 regs_buff[10] = hw_stats->tx_err_fifo_empty; 497 regs_buff[11] = hw_stats->tx_err_checksum; 498 } 499 500 /** 501 * hns_ppe_init - init ppe device 502 * @dsaf_dev: dasf device 503 * return 0 - success , negative --fail 504 */ 505 int hns_ppe_init(struct dsaf_device *dsaf_dev) 506 { 507 int ret; 508 int i; 509 510 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 511 ret = hns_ppe_common_get_cfg(dsaf_dev, i); 512 if (ret) 513 goto get_cfg_fail; 514 515 ret = hns_rcb_common_get_cfg(dsaf_dev, i); 516 if (ret) 517 goto get_cfg_fail; 518 519 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]); 520 521 ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]); 522 if (ret) 523 goto get_cfg_fail; 524 } 525 526 for (i = 0; i < HNS_PPE_COM_NUM; i++) 527 hns_ppe_reset_common(dsaf_dev, i); 528 529 return 0; 530 531 get_cfg_fail: 532 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 533 hns_rcb_common_free_cfg(dsaf_dev, i); 534 hns_ppe_common_free_cfg(dsaf_dev, i); 535 } 536 537 return ret; 538 } 539 540 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data) 541 { 542 struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb; 543 u32 *regs = data; 544 u32 i; 545 u32 offset; 546 547 /* ppe common registers */ 548 regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 549 regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG); 550 regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG); 551 regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG); 552 regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG); 553 554 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) { 555 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i; 556 regs[5 + i] = dsaf_read_dev(ppe_common, offset); 557 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i; 558 regs[5 + i + DSAF_TOTAL_QUEUE_NUM] 559 = dsaf_read_dev(ppe_common, offset); 560 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i; 561 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2] 562 = dsaf_read_dev(ppe_common, offset); 563 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i; 564 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3] 565 = dsaf_read_dev(ppe_common, offset); 566 } 567 568 /* mark end of ppe regs */ 569 for (i = 521; i < 524; i++) 570 regs[i] = 0xeeeeeeee; 571 572 /* ppe channel registers */ 573 regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG); 574 regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG); 575 regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG); 576 regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG); 577 regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG); 578 regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG); 579 regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG); 580 regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG); 581 582 regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG); 583 regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG); 584 regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG); 585 regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG); 586 regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG); 587 regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG); 588 regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG); 589 590 regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG); 591 regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG); 592 regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG); 593 regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG); 594 595 regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG); 596 regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG); 597 598 /* ppe static */ 599 regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 600 regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 601 regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 602 regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 603 regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 604 regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 605 regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 606 regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 607 regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 608 regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 609 regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 610 regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 611 612 regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG); 613 regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG); 614 regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG); 615 regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG); 616 regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG); 617 regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG); 618 regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG); 619 regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG); 620 regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG); 621 regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG); 622 regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG); 623 regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG); 624 regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG); 625 regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG); 626 627 /* mark end of ppe regs */ 628 for (i = 572; i < 576; i++) 629 regs[i] = 0xeeeeeeee; 630 } 631