1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2014-2015 Hisilicon Limited.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 
16 #include "hns_dsaf_ppe.h"
17 
18 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value)
19 {
20 	dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
21 }
22 
23 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb,
24 			 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM])
25 {
26 	u32 key_item;
27 
28 	for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++)
29 		dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
30 			       rss_key[key_item]);
31 }
32 
33 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb,
34 			     const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE])
35 {
36 	int i;
37 	int reg_value;
38 
39 	for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) {
40 		reg_value = dsaf_read_dev(ppe_cb,
41 					  PPEV2_INDRECTION_TBL_REG + i * 0x4);
42 
43 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
44 			       PPEV2_CFG_RSS_TBL_4N0_S,
45 			       rss_tab[i * 4 + 0] & 0x1F);
46 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
47 			       PPEV2_CFG_RSS_TBL_4N1_S,
48 				rss_tab[i * 4 + 1] & 0x1F);
49 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
50 			       PPEV2_CFG_RSS_TBL_4N2_S,
51 				rss_tab[i * 4 + 2] & 0x1F);
52 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
53 			       PPEV2_CFG_RSS_TBL_4N3_S,
54 				rss_tab[i * 4 + 3] & 0x1F);
55 		dsaf_write_dev(
56 			ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
57 	}
58 }
59 
60 static u8 __iomem *
61 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common)
62 {
63 	return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET;
64 }
65 
66 /**
67  * hns_ppe_common_get_cfg - get ppe common config
68  * @dsaf_dev: dasf device
69  * @comm_index: common index
70  * return 0 - success , negative --fail
71  */
72 static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index)
73 {
74 	struct ppe_common_cb *ppe_common;
75 	int ppe_num;
76 
77 	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
78 		ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM;
79 	else
80 		ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM;
81 
82 	ppe_common = devm_kzalloc(dsaf_dev->dev,
83 				  struct_size(ppe_common, ppe_cb, ppe_num),
84 				  GFP_KERNEL);
85 	if (!ppe_common)
86 		return -ENOMEM;
87 
88 	ppe_common->ppe_num = ppe_num;
89 	ppe_common->dsaf_dev = dsaf_dev;
90 	ppe_common->comm_index = comm_index;
91 	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
92 		ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE;
93 	else
94 		ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG;
95 	ppe_common->dev = dsaf_dev->dev;
96 
97 	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
98 
99 	dsaf_dev->ppe_common[comm_index] = ppe_common;
100 
101 	return 0;
102 }
103 
104 static void
105 hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index)
106 {
107 	dsaf_dev->ppe_common[comm_index] = NULL;
108 }
109 
110 static u8 __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common,
111 				      int ppe_idx)
112 {
113 	return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET;
114 }
115 
116 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common)
117 {
118 	u32 i;
119 	struct hns_ppe_cb *ppe_cb;
120 	u32 ppe_num = ppe_common->ppe_num;
121 
122 	for (i = 0; i < ppe_num; i++) {
123 		ppe_cb = &ppe_common->ppe_cb[i];
124 		ppe_cb->dev = ppe_common->dev;
125 		ppe_cb->next = NULL;
126 		ppe_cb->ppe_common_cb = ppe_common;
127 		ppe_cb->index = i;
128 		ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
129 		ppe_cb->virq = 0;
130 	}
131 }
132 
133 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb)
134 {
135 	dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
136 			 PPE_CNT_CLR_CE_B, 1);
137 }
138 
139 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en)
140 {
141 	dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
142 }
143 
144 /**
145  * hns_ppe_checksum_hw - set ppe checksum caculate
146  * @ppe_cb: ppe device
147  * @value: value
148  */
149 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value)
150 {
151 	dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
152 			   0xfffffff, 0, value);
153 }
154 
155 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common,
156 				 enum ppe_qid_mode qid_mdoe)
157 {
158 	dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
159 			   PPE_CFG_QID_MODE_CF_QID_MODE_M,
160 			   PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe);
161 }
162 
163 /**
164  * hns_ppe_set_qid - set ppe qid
165  * @ppe_common: ppe common device
166  * @qid: queue id
167  */
168 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid)
169 {
170 	u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
171 
172 	if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
173 			    PPE_CFG_QID_MODE_DEF_QID_S)) {
174 		dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
175 			       PPE_CFG_QID_MODE_DEF_QID_S, qid);
176 		dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
177 	}
178 }
179 
180 /**
181  * hns_ppe_set_port_mode - set port mode
182  * @ppe_cb: ppe device
183  * @mode: port mode
184  */
185 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb,
186 				  enum ppe_port_mode mode)
187 {
188 	dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
189 }
190 
191 /**
192  * hns_ppe_common_init_hw - init ppe common device
193  * @ppe_common: ppe common device
194  *
195  * Return 0 on success, negative on failure
196  */
197 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common)
198 {
199 	enum ppe_qid_mode qid_mode;
200 	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
201 	enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
202 
203 	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0);
204 	msleep(100);
205 	dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1);
206 	msleep(100);
207 
208 	if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) {
209 		switch (dsaf_mode) {
210 		case DSAF_MODE_ENABLE_FIX:
211 		case DSAF_MODE_DISABLE_FIX:
212 			qid_mode = PPE_QID_MODE0;
213 			hns_ppe_set_qid(ppe_common, 0);
214 			break;
215 		case DSAF_MODE_ENABLE_0VM:
216 		case DSAF_MODE_DISABLE_2PORT_64VM:
217 			qid_mode = PPE_QID_MODE3;
218 			break;
219 		case DSAF_MODE_ENABLE_8VM:
220 		case DSAF_MODE_DISABLE_2PORT_16VM:
221 			qid_mode = PPE_QID_MODE4;
222 			break;
223 		case DSAF_MODE_ENABLE_16VM:
224 		case DSAF_MODE_DISABLE_6PORT_0VM:
225 			qid_mode = PPE_QID_MODE5;
226 			break;
227 		case DSAF_MODE_ENABLE_32VM:
228 		case DSAF_MODE_DISABLE_6PORT_16VM:
229 			qid_mode = PPE_QID_MODE2;
230 			break;
231 		case DSAF_MODE_ENABLE_128VM:
232 		case DSAF_MODE_DISABLE_6PORT_4VM:
233 			qid_mode = PPE_QID_MODE1;
234 			break;
235 		case DSAF_MODE_DISABLE_2PORT_8VM:
236 			qid_mode = PPE_QID_MODE7;
237 			break;
238 		case DSAF_MODE_DISABLE_6PORT_2VM:
239 			qid_mode = PPE_QID_MODE6;
240 			break;
241 		default:
242 			dev_err(ppe_common->dev,
243 				"get ppe queue mode failed! dsaf_mode=%d\n",
244 				dsaf_mode);
245 			return -EINVAL;
246 		}
247 		hns_ppe_set_qid_mode(ppe_common, qid_mode);
248 	}
249 
250 	dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
251 			 PPE_COMMON_CNT_CLR_CE_B, 1);
252 
253 	return 0;
254 }
255 
256 /*clr ppe exception irq*/
257 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en)
258 {
259 	u32 clr_vlue = 0xfffffffful;
260 	u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/
261 	u32 vld_msk = 0;
262 
263 	/*only care bit 0,1,7*/
264 	dsaf_set_bit(vld_msk, 0, 1);
265 	dsaf_set_bit(vld_msk, 1, 1);
266 	dsaf_set_bit(vld_msk, 7, 1);
267 
268 	/*clr sts**/
269 	dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
270 
271 	/*for some reserved bits, so set 0**/
272 	dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
273 }
274 
275 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb)
276 {
277 	int wait_cnt;
278 	u32 val;
279 
280 	wait_cnt = 0;
281 	while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
282 		val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU;
283 		if (!val)
284 			break;
285 
286 		usleep_range(100, 200);
287 	}
288 
289 	if (wait_cnt >= HNS_MAX_WAIT_CNT) {
290 		dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n",
291 			val);
292 		return -EBUSY;
293 	}
294 
295 	return 0;
296 }
297 
298 /**
299  * ppe_init_hw - init ppe
300  * @ppe_cb: ppe device
301  */
302 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb)
303 {
304 	struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb;
305 	u32 port = ppe_cb->index;
306 	struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev;
307 	int i;
308 
309 	/* get default RSS key */
310 	netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE);
311 
312 	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
313 	mdelay(10);
314 	dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1);
315 
316 	/* clr and msk except irq*/
317 	hns_ppe_exc_irq_en(ppe_cb, 0);
318 
319 	if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) {
320 		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE);
321 		dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
322 	} else {
323 		hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE);
324 	}
325 
326 	hns_ppe_checksum_hw(ppe_cb, 0xffffffff);
327 	hns_ppe_cnt_clr_ce(ppe_cb);
328 
329 	if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
330 		hns_ppe_set_vlan_strip(ppe_cb, 0);
331 
332 		dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
333 			       HNS_PPEV2_MAX_FRAME_LEN);
334 
335 		/* set default RSS key in h/w */
336 		hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key);
337 
338 		/* Set default indrection table in h/w */
339 		for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++)
340 			ppe_cb->rss_indir_table[i] = i;
341 		hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table);
342 	}
343 }
344 
345 /**
346  * ppe_uninit_hw - uninit ppe
347  * @ppe_cb: ppe device
348  */
349 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb)
350 {
351 	u32 port;
352 
353 	if (ppe_cb->ppe_common_cb) {
354 		struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev;
355 
356 		port = ppe_cb->index;
357 		dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0);
358 	}
359 }
360 
361 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common)
362 {
363 	u32 i;
364 
365 	for (i = 0; i < ppe_common->ppe_num; i++) {
366 		if (ppe_common->dsaf_dev->mac_cb[i])
367 			hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]);
368 		memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb));
369 	}
370 }
371 
372 void hns_ppe_uninit(struct dsaf_device *dsaf_dev)
373 {
374 	u32 i;
375 
376 	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
377 		if (dsaf_dev->ppe_common[i])
378 			hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]);
379 		hns_rcb_common_free_cfg(dsaf_dev, i);
380 		hns_ppe_common_free_cfg(dsaf_dev, i);
381 	}
382 }
383 
384 /**
385  * hns_ppe_reset - reinit ppe/rcb hw
386  * @dsaf_dev: dasf device
387  * @ppe_common_index: the index
388  * return void
389  */
390 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index)
391 {
392 	u32 i;
393 	int ret;
394 	struct ppe_common_cb *ppe_common;
395 
396 	ppe_common = dsaf_dev->ppe_common[ppe_common_index];
397 	ret = hns_ppe_common_init_hw(ppe_common);
398 	if (ret)
399 		return;
400 
401 	for (i = 0; i < ppe_common->ppe_num; i++) {
402 		/* We only need to initiate ppe when the port exists */
403 		if (dsaf_dev->mac_cb[i])
404 			hns_ppe_init_hw(&ppe_common->ppe_cb[i]);
405 	}
406 
407 	ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]);
408 	if (ret)
409 		return;
410 
411 	hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]);
412 }
413 
414 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
415 {
416 	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
417 
418 	hw_stats->rx_pkts_from_sw
419 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
420 	hw_stats->rx_pkts
421 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
422 	hw_stats->rx_drop_no_bd
423 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
424 	hw_stats->rx_alloc_buf_fail
425 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
426 	hw_stats->rx_alloc_buf_wait
427 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
428 	hw_stats->rx_drop_no_buf
429 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
430 	hw_stats->rx_err_fifo_full
431 		+= dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
432 
433 	hw_stats->tx_bd_form_rcb
434 		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
435 	hw_stats->tx_pkts_from_rcb
436 		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
437 	hw_stats->tx_pkts
438 		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
439 	hw_stats->tx_err_fifo_empty
440 		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
441 	hw_stats->tx_err_checksum
442 		+= dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
443 }
444 
445 int hns_ppe_get_sset_count(int stringset)
446 {
447 	if (stringset == ETH_SS_STATS)
448 		return ETH_PPE_STATIC_NUM;
449 	return 0;
450 }
451 
452 int hns_ppe_get_regs_count(void)
453 {
454 	return ETH_PPE_DUMP_NUM;
455 }
456 
457 /**
458  * ppe_get_strings - get ppe srting
459  * @ppe_cb: ppe device
460  * @stringset: string set type
461  * @data: output string
462  */
463 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data)
464 {
465 	char *buff = (char *)data;
466 	int index = ppe_cb->index;
467 
468 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index);
469 	buff = buff + ETH_GSTRING_LEN;
470 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index);
471 	buff = buff + ETH_GSTRING_LEN;
472 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index);
473 	buff = buff + ETH_GSTRING_LEN;
474 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index);
475 	buff = buff + ETH_GSTRING_LEN;
476 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index);
477 	buff = buff + ETH_GSTRING_LEN;
478 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index);
479 	buff = buff + ETH_GSTRING_LEN;
480 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index);
481 	buff = buff + ETH_GSTRING_LEN;
482 
483 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index);
484 	buff = buff + ETH_GSTRING_LEN;
485 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index);
486 	buff = buff + ETH_GSTRING_LEN;
487 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index);
488 	buff = buff + ETH_GSTRING_LEN;
489 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index);
490 	buff = buff + ETH_GSTRING_LEN;
491 	snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index);
492 }
493 
494 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data)
495 {
496 	u64 *regs_buff = data;
497 	struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats;
498 
499 	regs_buff[0] = hw_stats->rx_pkts_from_sw;
500 	regs_buff[1] = hw_stats->rx_pkts;
501 	regs_buff[2] = hw_stats->rx_drop_no_bd;
502 	regs_buff[3] = hw_stats->rx_alloc_buf_fail;
503 	regs_buff[4] = hw_stats->rx_alloc_buf_wait;
504 	regs_buff[5] = hw_stats->rx_drop_no_buf;
505 	regs_buff[6] = hw_stats->rx_err_fifo_full;
506 
507 	regs_buff[7] = hw_stats->tx_bd_form_rcb;
508 	regs_buff[8] = hw_stats->tx_pkts_from_rcb;
509 	regs_buff[9] = hw_stats->tx_pkts;
510 	regs_buff[10] = hw_stats->tx_err_fifo_empty;
511 	regs_buff[11] = hw_stats->tx_err_checksum;
512 }
513 
514 /**
515  * hns_ppe_init - init ppe device
516  * @dsaf_dev: dasf device
517  * return 0 - success , negative --fail
518  */
519 int hns_ppe_init(struct dsaf_device *dsaf_dev)
520 {
521 	int ret;
522 	int i;
523 
524 	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
525 		ret = hns_ppe_common_get_cfg(dsaf_dev, i);
526 		if (ret)
527 			goto get_cfg_fail;
528 
529 		ret = hns_rcb_common_get_cfg(dsaf_dev, i);
530 		if (ret)
531 			goto get_cfg_fail;
532 
533 		hns_ppe_get_cfg(dsaf_dev->ppe_common[i]);
534 
535 		ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]);
536 		if (ret)
537 			goto get_cfg_fail;
538 	}
539 
540 	for (i = 0; i < HNS_PPE_COM_NUM; i++)
541 		hns_ppe_reset_common(dsaf_dev, i);
542 
543 	return 0;
544 
545 get_cfg_fail:
546 	for (i = 0; i < HNS_PPE_COM_NUM; i++) {
547 		hns_rcb_common_free_cfg(dsaf_dev, i);
548 		hns_ppe_common_free_cfg(dsaf_dev, i);
549 	}
550 
551 	return ret;
552 }
553 
554 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data)
555 {
556 	struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb;
557 	u32 *regs = data;
558 	u32 i;
559 	u32 offset;
560 
561 	/* ppe common registers */
562 	regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG);
563 	regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG);
564 	regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG);
565 	regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG);
566 	regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG);
567 
568 	for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) {
569 		offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i;
570 		regs[5 + i] = dsaf_read_dev(ppe_common, offset);
571 		offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i;
572 		regs[5 + i + DSAF_TOTAL_QUEUE_NUM]
573 				= dsaf_read_dev(ppe_common, offset);
574 		offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i;
575 		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2]
576 				= dsaf_read_dev(ppe_common, offset);
577 		offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i;
578 		regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3]
579 				= dsaf_read_dev(ppe_common, offset);
580 	}
581 
582 	/* mark end of ppe regs */
583 	for (i = 521; i < 524; i++)
584 		regs[i] = 0xeeeeeeee;
585 
586 	/* ppe channel registers */
587 	regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG);
588 	regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG);
589 	regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG);
590 	regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG);
591 	regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG);
592 	regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG);
593 	regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG);
594 	regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG);
595 
596 	regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG);
597 	regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG);
598 	regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG);
599 	regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG);
600 	regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG);
601 	regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG);
602 	regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG);
603 
604 	regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG);
605 	regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG);
606 	regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG);
607 	regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG);
608 
609 	regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG);
610 	regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG);
611 
612 	/* ppe static */
613 	regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG);
614 	regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG);
615 	regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG);
616 	regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG);
617 	regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG);
618 	regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG);
619 	regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG);
620 	regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG);
621 	regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG);
622 	regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG);
623 	regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG);
624 	regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG);
625 
626 	regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG);
627 	regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG);
628 	regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG);
629 	regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG);
630 	regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG);
631 	regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG);
632 	regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG);
633 	regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG);
634 	regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG);
635 	regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG);
636 	regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG);
637 	regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG);
638 	regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG);
639 	regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG);
640 
641 	/* mark end of ppe regs */
642 	for (i = 572; i < 576; i++)
643 		regs[i] = 0xeeeeeeee;
644 }
645