1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_platform.h> 19 20 #include "hns_dsaf_ppe.h" 21 22 void hns_ppe_set_tso_enable(struct hns_ppe_cb *ppe_cb, u32 value) 23 { 24 dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value); 25 } 26 27 void hns_ppe_set_rss_key(struct hns_ppe_cb *ppe_cb, 28 const u32 rss_key[HNS_PPEV2_RSS_KEY_NUM]) 29 { 30 u32 key_item; 31 32 for (key_item = 0; key_item < HNS_PPEV2_RSS_KEY_NUM; key_item++) 33 dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4, 34 rss_key[key_item]); 35 } 36 37 void hns_ppe_set_indir_table(struct hns_ppe_cb *ppe_cb, 38 const u32 rss_tab[HNS_PPEV2_RSS_IND_TBL_SIZE]) 39 { 40 int i; 41 int reg_value; 42 43 for (i = 0; i < (HNS_PPEV2_RSS_IND_TBL_SIZE / 4); i++) { 44 reg_value = dsaf_read_dev(ppe_cb, 45 PPEV2_INDRECTION_TBL_REG + i * 0x4); 46 47 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M, 48 PPEV2_CFG_RSS_TBL_4N0_S, 49 rss_tab[i * 4 + 0] & 0x1F); 50 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M, 51 PPEV2_CFG_RSS_TBL_4N1_S, 52 rss_tab[i * 4 + 1] & 0x1F); 53 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M, 54 PPEV2_CFG_RSS_TBL_4N2_S, 55 rss_tab[i * 4 + 2] & 0x1F); 56 dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M, 57 PPEV2_CFG_RSS_TBL_4N3_S, 58 rss_tab[i * 4 + 3] & 0x1F); 59 dsaf_write_dev( 60 ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value); 61 } 62 } 63 64 static void __iomem * 65 hns_ppe_common_get_ioaddr(struct ppe_common_cb *ppe_common) 66 { 67 return ppe_common->dsaf_dev->ppe_base + PPE_COMMON_REG_OFFSET; 68 } 69 70 /** 71 * hns_ppe_common_get_cfg - get ppe common config 72 * @dsaf_dev: dasf device 73 * comm_index: common index 74 * retuen 0 - success , negative --fail 75 */ 76 static int hns_ppe_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index) 77 { 78 struct ppe_common_cb *ppe_common; 79 int ppe_num; 80 81 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 82 ppe_num = HNS_PPE_SERVICE_NW_ENGINE_NUM; 83 else 84 ppe_num = HNS_PPE_DEBUG_NW_ENGINE_NUM; 85 86 ppe_common = devm_kzalloc(dsaf_dev->dev, 87 struct_size(ppe_common, ppe_cb, ppe_num), 88 GFP_KERNEL); 89 if (!ppe_common) 90 return -ENOMEM; 91 92 ppe_common->ppe_num = ppe_num; 93 ppe_common->dsaf_dev = dsaf_dev; 94 ppe_common->comm_index = comm_index; 95 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 96 ppe_common->ppe_mode = PPE_COMMON_MODE_SERVICE; 97 else 98 ppe_common->ppe_mode = PPE_COMMON_MODE_DEBUG; 99 ppe_common->dev = dsaf_dev->dev; 100 101 ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common); 102 103 dsaf_dev->ppe_common[comm_index] = ppe_common; 104 105 return 0; 106 } 107 108 static void 109 hns_ppe_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index) 110 { 111 dsaf_dev->ppe_common[comm_index] = NULL; 112 } 113 114 static void __iomem *hns_ppe_get_iobase(struct ppe_common_cb *ppe_common, 115 int ppe_idx) 116 { 117 return ppe_common->dsaf_dev->ppe_base + ppe_idx * PPE_REG_OFFSET; 118 } 119 120 static void hns_ppe_get_cfg(struct ppe_common_cb *ppe_common) 121 { 122 u32 i; 123 struct hns_ppe_cb *ppe_cb; 124 u32 ppe_num = ppe_common->ppe_num; 125 126 for (i = 0; i < ppe_num; i++) { 127 ppe_cb = &ppe_common->ppe_cb[i]; 128 ppe_cb->dev = ppe_common->dev; 129 ppe_cb->next = NULL; 130 ppe_cb->ppe_common_cb = ppe_common; 131 ppe_cb->index = i; 132 ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i); 133 ppe_cb->virq = 0; 134 } 135 } 136 137 static void hns_ppe_cnt_clr_ce(struct hns_ppe_cb *ppe_cb) 138 { 139 dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG, 140 PPE_CNT_CLR_CE_B, 1); 141 } 142 143 static void hns_ppe_set_vlan_strip(struct hns_ppe_cb *ppe_cb, int en) 144 { 145 dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en); 146 } 147 148 /** 149 * hns_ppe_checksum_hw - set ppe checksum caculate 150 * @ppe_device: ppe device 151 * @value: value 152 */ 153 static void hns_ppe_checksum_hw(struct hns_ppe_cb *ppe_cb, u32 value) 154 { 155 dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG, 156 0xfffffff, 0, value); 157 } 158 159 static void hns_ppe_set_qid_mode(struct ppe_common_cb *ppe_common, 160 enum ppe_qid_mode qid_mdoe) 161 { 162 dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG, 163 PPE_CFG_QID_MODE_CF_QID_MODE_M, 164 PPE_CFG_QID_MODE_CF_QID_MODE_S, qid_mdoe); 165 } 166 167 /** 168 * hns_ppe_set_qid - set ppe qid 169 * @ppe_common: ppe common device 170 * @qid: queue id 171 */ 172 static void hns_ppe_set_qid(struct ppe_common_cb *ppe_common, u32 qid) 173 { 174 u32 qid_mod = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 175 176 if (!dsaf_get_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 177 PPE_CFG_QID_MODE_DEF_QID_S)) { 178 dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M, 179 PPE_CFG_QID_MODE_DEF_QID_S, qid); 180 dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod); 181 } 182 } 183 184 /** 185 * hns_ppe_set_port_mode - set port mode 186 * @ppe_device: ppe device 187 * @mode: port mode 188 */ 189 static void hns_ppe_set_port_mode(struct hns_ppe_cb *ppe_cb, 190 enum ppe_port_mode mode) 191 { 192 dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode); 193 } 194 195 /** 196 * hns_ppe_common_init_hw - init ppe common device 197 * @ppe_common: ppe common device 198 * 199 * Return 0 on success, negative on failure 200 */ 201 static int hns_ppe_common_init_hw(struct ppe_common_cb *ppe_common) 202 { 203 enum ppe_qid_mode qid_mode; 204 struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev; 205 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode; 206 207 dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 0); 208 msleep(100); 209 dsaf_dev->misc_op->ppe_comm_srst(dsaf_dev, 1); 210 msleep(100); 211 212 if (ppe_common->ppe_mode == PPE_COMMON_MODE_SERVICE) { 213 switch (dsaf_mode) { 214 case DSAF_MODE_ENABLE_FIX: 215 case DSAF_MODE_DISABLE_FIX: 216 qid_mode = PPE_QID_MODE0; 217 hns_ppe_set_qid(ppe_common, 0); 218 break; 219 case DSAF_MODE_ENABLE_0VM: 220 case DSAF_MODE_DISABLE_2PORT_64VM: 221 qid_mode = PPE_QID_MODE3; 222 break; 223 case DSAF_MODE_ENABLE_8VM: 224 case DSAF_MODE_DISABLE_2PORT_16VM: 225 qid_mode = PPE_QID_MODE4; 226 break; 227 case DSAF_MODE_ENABLE_16VM: 228 case DSAF_MODE_DISABLE_6PORT_0VM: 229 qid_mode = PPE_QID_MODE5; 230 break; 231 case DSAF_MODE_ENABLE_32VM: 232 case DSAF_MODE_DISABLE_6PORT_16VM: 233 qid_mode = PPE_QID_MODE2; 234 break; 235 case DSAF_MODE_ENABLE_128VM: 236 case DSAF_MODE_DISABLE_6PORT_4VM: 237 qid_mode = PPE_QID_MODE1; 238 break; 239 case DSAF_MODE_DISABLE_2PORT_8VM: 240 qid_mode = PPE_QID_MODE7; 241 break; 242 case DSAF_MODE_DISABLE_6PORT_2VM: 243 qid_mode = PPE_QID_MODE6; 244 break; 245 default: 246 dev_err(ppe_common->dev, 247 "get ppe queue mode failed! dsaf_mode=%d\n", 248 dsaf_mode); 249 return -EINVAL; 250 } 251 hns_ppe_set_qid_mode(ppe_common, qid_mode); 252 } 253 254 dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG, 255 PPE_COMMON_CNT_CLR_CE_B, 1); 256 257 return 0; 258 } 259 260 /*clr ppe exception irq*/ 261 static void hns_ppe_exc_irq_en(struct hns_ppe_cb *ppe_cb, int en) 262 { 263 u32 clr_vlue = 0xfffffffful; 264 u32 msk_vlue = en ? 0xfffffffful : 0; /*1 is en, 0 is dis*/ 265 u32 vld_msk = 0; 266 267 /*only care bit 0,1,7*/ 268 dsaf_set_bit(vld_msk, 0, 1); 269 dsaf_set_bit(vld_msk, 1, 1); 270 dsaf_set_bit(vld_msk, 7, 1); 271 272 /*clr sts**/ 273 dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue); 274 275 /*for some reserved bits, so set 0**/ 276 dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk); 277 } 278 279 int hns_ppe_wait_tx_fifo_clean(struct hns_ppe_cb *ppe_cb) 280 { 281 int wait_cnt; 282 u32 val; 283 284 wait_cnt = 0; 285 while (wait_cnt++ < HNS_MAX_WAIT_CNT) { 286 val = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG) & 0x3ffU; 287 if (!val) 288 break; 289 290 usleep_range(100, 200); 291 } 292 293 if (wait_cnt >= HNS_MAX_WAIT_CNT) { 294 dev_err(ppe_cb->dev, "hns ppe tx fifo clean wait timeout, still has %u pkt.\n", 295 val); 296 return -EBUSY; 297 } 298 299 return 0; 300 } 301 302 /** 303 * ppe_init_hw - init ppe 304 * @ppe_cb: ppe device 305 */ 306 static void hns_ppe_init_hw(struct hns_ppe_cb *ppe_cb) 307 { 308 struct ppe_common_cb *ppe_common_cb = ppe_cb->ppe_common_cb; 309 u32 port = ppe_cb->index; 310 struct dsaf_device *dsaf_dev = ppe_common_cb->dsaf_dev; 311 int i; 312 313 /* get default RSS key */ 314 netdev_rss_key_fill(ppe_cb->rss_key, HNS_PPEV2_RSS_KEY_SIZE); 315 316 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0); 317 mdelay(10); 318 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 1); 319 320 /* clr and msk except irq*/ 321 hns_ppe_exc_irq_en(ppe_cb, 0); 322 323 if (ppe_common_cb->ppe_mode == PPE_COMMON_MODE_DEBUG) { 324 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_GE); 325 dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0); 326 } else { 327 hns_ppe_set_port_mode(ppe_cb, PPE_MODE_XGE); 328 } 329 330 hns_ppe_checksum_hw(ppe_cb, 0xffffffff); 331 hns_ppe_cnt_clr_ce(ppe_cb); 332 333 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 334 hns_ppe_set_vlan_strip(ppe_cb, 0); 335 336 dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG, 337 HNS_PPEV2_MAX_FRAME_LEN); 338 339 /* set default RSS key in h/w */ 340 hns_ppe_set_rss_key(ppe_cb, ppe_cb->rss_key); 341 342 /* Set default indrection table in h/w */ 343 for (i = 0; i < HNS_PPEV2_RSS_IND_TBL_SIZE; i++) 344 ppe_cb->rss_indir_table[i] = i; 345 hns_ppe_set_indir_table(ppe_cb, ppe_cb->rss_indir_table); 346 } 347 } 348 349 /** 350 * ppe_uninit_hw - uninit ppe 351 * @ppe_device: ppe device 352 */ 353 static void hns_ppe_uninit_hw(struct hns_ppe_cb *ppe_cb) 354 { 355 u32 port; 356 357 if (ppe_cb->ppe_common_cb) { 358 struct dsaf_device *dsaf_dev = ppe_cb->ppe_common_cb->dsaf_dev; 359 360 port = ppe_cb->index; 361 dsaf_dev->misc_op->ppe_srst(dsaf_dev, port, 0); 362 } 363 } 364 365 static void hns_ppe_uninit_ex(struct ppe_common_cb *ppe_common) 366 { 367 u32 i; 368 369 for (i = 0; i < ppe_common->ppe_num; i++) { 370 if (ppe_common->dsaf_dev->mac_cb[i]) 371 hns_ppe_uninit_hw(&ppe_common->ppe_cb[i]); 372 memset(&ppe_common->ppe_cb[i], 0, sizeof(struct hns_ppe_cb)); 373 } 374 } 375 376 void hns_ppe_uninit(struct dsaf_device *dsaf_dev) 377 { 378 u32 i; 379 380 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 381 if (dsaf_dev->ppe_common[i]) 382 hns_ppe_uninit_ex(dsaf_dev->ppe_common[i]); 383 hns_rcb_common_free_cfg(dsaf_dev, i); 384 hns_ppe_common_free_cfg(dsaf_dev, i); 385 } 386 } 387 388 /** 389 * hns_ppe_reset - reinit ppe/rcb hw 390 * @dsaf_dev: dasf device 391 * retuen void 392 */ 393 void hns_ppe_reset_common(struct dsaf_device *dsaf_dev, u8 ppe_common_index) 394 { 395 u32 i; 396 int ret; 397 struct ppe_common_cb *ppe_common; 398 399 ppe_common = dsaf_dev->ppe_common[ppe_common_index]; 400 ret = hns_ppe_common_init_hw(ppe_common); 401 if (ret) 402 return; 403 404 for (i = 0; i < ppe_common->ppe_num; i++) { 405 /* We only need to initiate ppe when the port exists */ 406 if (dsaf_dev->mac_cb[i]) 407 hns_ppe_init_hw(&ppe_common->ppe_cb[i]); 408 } 409 410 ret = hns_rcb_common_init_hw(dsaf_dev->rcb_common[ppe_common_index]); 411 if (ret) 412 return; 413 414 hns_rcb_common_init_commit_hw(dsaf_dev->rcb_common[ppe_common_index]); 415 } 416 417 void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb) 418 { 419 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 420 421 hw_stats->rx_pkts_from_sw 422 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 423 hw_stats->rx_pkts 424 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 425 hw_stats->rx_drop_no_bd 426 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 427 hw_stats->rx_alloc_buf_fail 428 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 429 hw_stats->rx_alloc_buf_wait 430 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 431 hw_stats->rx_drop_no_buf 432 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 433 hw_stats->rx_err_fifo_full 434 += dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 435 436 hw_stats->tx_bd_form_rcb 437 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 438 hw_stats->tx_pkts_from_rcb 439 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 440 hw_stats->tx_pkts 441 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 442 hw_stats->tx_err_fifo_empty 443 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 444 hw_stats->tx_err_checksum 445 += dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 446 } 447 448 int hns_ppe_get_sset_count(int stringset) 449 { 450 if (stringset == ETH_SS_STATS) 451 return ETH_PPE_STATIC_NUM; 452 return 0; 453 } 454 455 int hns_ppe_get_regs_count(void) 456 { 457 return ETH_PPE_DUMP_NUM; 458 } 459 460 /** 461 * ppe_get_strings - get ppe srting 462 * @ppe_device: ppe device 463 * @stringset: string set type 464 * @data: output string 465 */ 466 void hns_ppe_get_strings(struct hns_ppe_cb *ppe_cb, int stringset, u8 *data) 467 { 468 char *buff = (char *)data; 469 int index = ppe_cb->index; 470 471 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_sw_pkt", index); 472 buff = buff + ETH_GSTRING_LEN; 473 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_ok", index); 474 buff = buff + ETH_GSTRING_LEN; 475 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_drop_pkt_no_bd", index); 476 buff = buff + ETH_GSTRING_LEN; 477 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_fail", index); 478 buff = buff + ETH_GSTRING_LEN; 479 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_alloc_buf_wait", index); 480 buff = buff + ETH_GSTRING_LEN; 481 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_drop_no_buf", index); 482 buff = buff + ETH_GSTRING_LEN; 483 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_rx_pkt_err_fifo_full", index); 484 buff = buff + ETH_GSTRING_LEN; 485 486 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_bd", index); 487 buff = buff + ETH_GSTRING_LEN; 488 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt", index); 489 buff = buff + ETH_GSTRING_LEN; 490 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_ok", index); 491 buff = buff + ETH_GSTRING_LEN; 492 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_fifo_empty", index); 493 buff = buff + ETH_GSTRING_LEN; 494 snprintf(buff, ETH_GSTRING_LEN, "ppe%d_tx_pkt_err_csum_fail", index); 495 } 496 497 void hns_ppe_get_stats(struct hns_ppe_cb *ppe_cb, u64 *data) 498 { 499 u64 *regs_buff = data; 500 struct hns_ppe_hw_stats *hw_stats = &ppe_cb->hw_stats; 501 502 regs_buff[0] = hw_stats->rx_pkts_from_sw; 503 regs_buff[1] = hw_stats->rx_pkts; 504 regs_buff[2] = hw_stats->rx_drop_no_bd; 505 regs_buff[3] = hw_stats->rx_alloc_buf_fail; 506 regs_buff[4] = hw_stats->rx_alloc_buf_wait; 507 regs_buff[5] = hw_stats->rx_drop_no_buf; 508 regs_buff[6] = hw_stats->rx_err_fifo_full; 509 510 regs_buff[7] = hw_stats->tx_bd_form_rcb; 511 regs_buff[8] = hw_stats->tx_pkts_from_rcb; 512 regs_buff[9] = hw_stats->tx_pkts; 513 regs_buff[10] = hw_stats->tx_err_fifo_empty; 514 regs_buff[11] = hw_stats->tx_err_checksum; 515 } 516 517 /** 518 * hns_ppe_init - init ppe device 519 * @dsaf_dev: dasf device 520 * retuen 0 - success , negative --fail 521 */ 522 int hns_ppe_init(struct dsaf_device *dsaf_dev) 523 { 524 int ret; 525 int i; 526 527 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 528 ret = hns_ppe_common_get_cfg(dsaf_dev, i); 529 if (ret) 530 goto get_cfg_fail; 531 532 ret = hns_rcb_common_get_cfg(dsaf_dev, i); 533 if (ret) 534 goto get_cfg_fail; 535 536 hns_ppe_get_cfg(dsaf_dev->ppe_common[i]); 537 538 ret = hns_rcb_get_cfg(dsaf_dev->rcb_common[i]); 539 if (ret) 540 goto get_cfg_fail; 541 } 542 543 for (i = 0; i < HNS_PPE_COM_NUM; i++) 544 hns_ppe_reset_common(dsaf_dev, i); 545 546 return 0; 547 548 get_cfg_fail: 549 for (i = 0; i < HNS_PPE_COM_NUM; i++) { 550 hns_rcb_common_free_cfg(dsaf_dev, i); 551 hns_ppe_common_free_cfg(dsaf_dev, i); 552 } 553 554 return ret; 555 } 556 557 void hns_ppe_get_regs(struct hns_ppe_cb *ppe_cb, void *data) 558 { 559 struct ppe_common_cb *ppe_common = ppe_cb->ppe_common_cb; 560 u32 *regs = data; 561 u32 i; 562 u32 offset; 563 564 /* ppe common registers */ 565 regs[0] = dsaf_read_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG); 566 regs[1] = dsaf_read_dev(ppe_common, PPE_COM_INTEN_REG); 567 regs[2] = dsaf_read_dev(ppe_common, PPE_COM_RINT_REG); 568 regs[3] = dsaf_read_dev(ppe_common, PPE_COM_INTSTS_REG); 569 regs[4] = dsaf_read_dev(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG); 570 571 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) { 572 offset = PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 0x4 * i; 573 regs[5 + i] = dsaf_read_dev(ppe_common, offset); 574 offset = PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 0x4 * i; 575 regs[5 + i + DSAF_TOTAL_QUEUE_NUM] 576 = dsaf_read_dev(ppe_common, offset); 577 offset = PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 0x4 * i; 578 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 2] 579 = dsaf_read_dev(ppe_common, offset); 580 offset = PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 0x4 * i; 581 regs[5 + i + DSAF_TOTAL_QUEUE_NUM * 3] 582 = dsaf_read_dev(ppe_common, offset); 583 } 584 585 /* mark end of ppe regs */ 586 for (i = 521; i < 524; i++) 587 regs[i] = 0xeeeeeeee; 588 589 /* ppe channel registers */ 590 regs[525] = dsaf_read_dev(ppe_cb, PPE_CFG_TX_FIFO_THRSLD_REG); 591 regs[526] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_THRSLD_REG); 592 regs[527] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG); 593 regs[528] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG); 594 regs[529] = dsaf_read_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG); 595 regs[530] = dsaf_read_dev(ppe_cb, PPE_CFG_BUS_CTRL_REG); 596 regs[531] = dsaf_read_dev(ppe_cb, PPE_CFG_TNL_TO_BE_RST_REG); 597 regs[532] = dsaf_read_dev(ppe_cb, PPE_CURR_TNL_CAN_RST_REG); 598 599 regs[533] = dsaf_read_dev(ppe_cb, PPE_CFG_XGE_MODE_REG); 600 regs[534] = dsaf_read_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG); 601 regs[535] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_MODE_REG); 602 regs[536] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_VLAN_TAG_REG); 603 regs[537] = dsaf_read_dev(ppe_cb, PPE_CFG_TAG_GEN_REG); 604 regs[538] = dsaf_read_dev(ppe_cb, PPE_CFG_PARSE_TAG_REG); 605 regs[539] = dsaf_read_dev(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG); 606 607 regs[540] = dsaf_read_dev(ppe_cb, PPE_INTEN_REG); 608 regs[541] = dsaf_read_dev(ppe_cb, PPE_RINT_REG); 609 regs[542] = dsaf_read_dev(ppe_cb, PPE_INTSTS_REG); 610 regs[543] = dsaf_read_dev(ppe_cb, PPE_CFG_RX_PKT_INT_REG); 611 612 regs[544] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME0_REG); 613 regs[545] = dsaf_read_dev(ppe_cb, PPE_CFG_HEAT_DECT_TIME1_REG); 614 615 /* ppe static */ 616 regs[546] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_SW_PKT_CNT_REG); 617 regs[547] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG); 618 regs[548] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_NO_BUF_CNT_REG); 619 regs[549] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_BD_CNT_REG); 620 regs[550] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CNT_REG); 621 regs[551] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_OK_CNT_REG); 622 regs[552] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_EPT_CNT_REG); 623 regs[553] = dsaf_read_dev(ppe_cb, PPE_HIS_TX_PKT_CS_FAIL_CNT_REG); 624 regs[554] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_FAIL_CNT_REG); 625 regs[555] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_APP_BUF_WAIT_CNT_REG); 626 regs[556] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_FUL_CNT_REG); 627 regs[557] = dsaf_read_dev(ppe_cb, PPE_HIS_RX_PKT_DROP_PRT_CNT_REG); 628 629 regs[558] = dsaf_read_dev(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG); 630 regs[559] = dsaf_read_dev(ppe_cb, PPE_CFG_AXI_DBG_REG); 631 regs[560] = dsaf_read_dev(ppe_cb, PPE_HIS_PRO_ERR_REG); 632 regs[561] = dsaf_read_dev(ppe_cb, PPE_HIS_TNL_FIFO_ERR_REG); 633 regs[562] = dsaf_read_dev(ppe_cb, PPE_CURR_CFF_DATA_NUM_REG); 634 regs[563] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_ST_REG); 635 regs[564] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_ST_REG); 636 regs[565] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO0_REG); 637 regs[566] = dsaf_read_dev(ppe_cb, PPE_CURR_RX_FIFO1_REG); 638 regs[567] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO0_REG); 639 regs[568] = dsaf_read_dev(ppe_cb, PPE_CURR_TX_FIFO1_REG); 640 regs[569] = dsaf_read_dev(ppe_cb, PPE_ECO0_REG); 641 regs[570] = dsaf_read_dev(ppe_cb, PPE_ECO1_REG); 642 regs[571] = dsaf_read_dev(ppe_cb, PPE_ECO2_REG); 643 644 /* mark end of ppe regs */ 645 for (i = 572; i < 576; i++) 646 regs[i] = 0xeeeeeeee; 647 } 648