1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include "hns_dsaf_mac.h" 11 #include "hns_dsaf_misc.h" 12 #include "hns_dsaf_ppe.h" 13 #include "hns_dsaf_reg.h" 14 15 enum _dsm_op_index { 16 HNS_OP_RESET_FUNC = 0x1, 17 HNS_OP_SERDES_LP_FUNC = 0x2, 18 HNS_OP_LED_SET_FUNC = 0x3, 19 HNS_OP_GET_PORT_TYPE_FUNC = 0x4, 20 HNS_OP_GET_SFP_STAT_FUNC = 0x5, 21 }; 22 23 enum _dsm_rst_type { 24 HNS_DSAF_RESET_FUNC = 0x1, 25 HNS_PPE_RESET_FUNC = 0x2, 26 HNS_XGE_CORE_RESET_FUNC = 0x3, 27 HNS_XGE_RESET_FUNC = 0x4, 28 HNS_GE_RESET_FUNC = 0x5, 29 }; 30 31 const u8 hns_dsaf_acpi_dsm_uuid[] = { 32 0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41, 33 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A 34 }; 35 36 static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val) 37 { 38 if (dsaf_dev->sub_ctrl) 39 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); 40 else 41 dsaf_write_reg(dsaf_dev->sc_base, reg, val); 42 } 43 44 static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg) 45 { 46 u32 ret; 47 48 if (dsaf_dev->sub_ctrl) 49 ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg); 50 else 51 ret = dsaf_read_reg(dsaf_dev->sc_base, reg); 52 53 return ret; 54 } 55 56 static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status, 57 u16 speed, int data) 58 { 59 int speed_reg = 0; 60 u8 value; 61 62 if (!mac_cb) { 63 pr_err("sfp_led_opt mac_dev is null!\n"); 64 return; 65 } 66 if (!mac_cb->cpld_ctrl) { 67 dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n", 68 mac_cb->mac_id); 69 return; 70 } 71 72 if (speed == MAC_SPEED_10000) 73 speed_reg = 1; 74 75 value = mac_cb->cpld_led_value; 76 77 if (link_status) { 78 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status); 79 dsaf_set_field(value, DSAF_LED_SPEED_M, 80 DSAF_LED_SPEED_S, speed_reg); 81 dsaf_set_bit(value, DSAF_LED_DATA_B, data); 82 83 if (value != mac_cb->cpld_led_value) { 84 dsaf_write_syscon(mac_cb->cpld_ctrl, 85 mac_cb->cpld_ctrl_reg, value); 86 mac_cb->cpld_led_value = value; 87 } 88 } else { 89 value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B); 90 dsaf_write_syscon(mac_cb->cpld_ctrl, 91 mac_cb->cpld_ctrl_reg, value); 92 mac_cb->cpld_led_value = value; 93 } 94 } 95 96 static void cpld_led_reset(struct hns_mac_cb *mac_cb) 97 { 98 if (!mac_cb || !mac_cb->cpld_ctrl) 99 return; 100 101 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, 102 CPLD_LED_DEFAULT_VALUE); 103 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE; 104 } 105 106 static int cpld_set_led_id(struct hns_mac_cb *mac_cb, 107 enum hnae_led_state status) 108 { 109 switch (status) { 110 case HNAE_LED_ACTIVE: 111 mac_cb->cpld_led_value = 112 dsaf_read_syscon(mac_cb->cpld_ctrl, 113 mac_cb->cpld_ctrl_reg); 114 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, 115 CPLD_LED_ON_VALUE); 116 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, 117 mac_cb->cpld_led_value); 118 break; 119 case HNAE_LED_INACTIVE: 120 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B, 121 CPLD_LED_DEFAULT_VALUE); 122 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg, 123 mac_cb->cpld_led_value); 124 break; 125 default: 126 dev_err(mac_cb->dev, "invalid led state: %d!", status); 127 return -EINVAL; 128 } 129 130 return 0; 131 } 132 133 #define RESET_REQ_OR_DREQ 1 134 135 static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type, 136 u32 port_type, u32 port, u32 val) 137 { 138 union acpi_object *obj; 139 union acpi_object obj_args[3], argv4; 140 141 obj_args[0].integer.type = ACPI_TYPE_INTEGER; 142 obj_args[0].integer.value = port_type; 143 obj_args[1].integer.type = ACPI_TYPE_INTEGER; 144 obj_args[1].integer.value = port; 145 obj_args[2].integer.type = ACPI_TYPE_INTEGER; 146 obj_args[2].integer.value = val; 147 148 argv4.type = ACPI_TYPE_PACKAGE; 149 argv4.package.count = 3; 150 argv4.package.elements = obj_args; 151 152 obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev), 153 hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4); 154 if (!obj) { 155 dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!", 156 port_type, port); 157 return; 158 } 159 160 ACPI_FREE(obj); 161 } 162 163 static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset) 164 { 165 u32 xbar_reg_addr; 166 u32 nt_reg_addr; 167 168 if (!dereset) { 169 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG; 170 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG; 171 } else { 172 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG; 173 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG; 174 } 175 176 dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ); 177 dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ); 178 } 179 180 static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset) 181 { 182 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 183 HNS_DSAF_RESET_FUNC, 184 0, dereset); 185 } 186 187 static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, 188 bool dereset) 189 { 190 u32 reg_val = 0; 191 u32 reg_addr; 192 193 if (port >= DSAF_XGE_NUM) 194 return; 195 196 reg_val |= RESET_REQ_OR_DREQ; 197 reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off; 198 199 if (!dereset) 200 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; 201 else 202 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; 203 204 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); 205 } 206 207 static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, 208 u32 port, bool dereset) 209 { 210 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 211 HNS_XGE_RESET_FUNC, port, dereset); 212 } 213 214 static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev, 215 u32 port, bool dereset) 216 { 217 u32 reg_val = 0; 218 u32 reg_addr; 219 220 if (port >= DSAF_XGE_NUM) 221 return; 222 223 reg_val |= XGMAC_TRX_CORE_SRST_M 224 << dsaf_dev->mac_cb[port]->port_rst_off; 225 226 if (!dereset) 227 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; 228 else 229 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; 230 231 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); 232 } 233 234 static void 235 hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev, 236 u32 port, bool dereset) 237 { 238 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 239 HNS_XGE_CORE_RESET_FUNC, port, dereset); 240 } 241 242 static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, 243 bool dereset) 244 { 245 u32 reg_val_1; 246 u32 reg_val_2; 247 u32 port_rst_off; 248 249 if (port >= DSAF_GE_NUM) 250 return; 251 252 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 253 reg_val_1 = 0x1 << port; 254 port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off; 255 /* there is difference between V1 and V2 in register.*/ 256 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 257 0x1041041 : 0x2082082; 258 reg_val_2 <<= port_rst_off; 259 260 if (!dereset) { 261 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, 262 reg_val_1); 263 264 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG, 265 reg_val_2); 266 } else { 267 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG, 268 reg_val_2); 269 270 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, 271 reg_val_1); 272 } 273 } else { 274 reg_val_1 = 0x15540; 275 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; 276 277 reg_val_1 <<= dsaf_dev->reset_offset; 278 reg_val_2 <<= dsaf_dev->reset_offset; 279 280 if (!dereset) { 281 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG, 282 reg_val_1); 283 284 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG, 285 reg_val_2); 286 } else { 287 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG, 288 reg_val_1); 289 290 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG, 291 reg_val_2); 292 } 293 } 294 } 295 296 static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev, 297 u32 port, bool dereset) 298 { 299 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 300 HNS_GE_RESET_FUNC, port, dereset); 301 } 302 303 static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, 304 bool dereset) 305 { 306 u32 reg_val = 0; 307 u32 reg_addr; 308 309 reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off; 310 311 if (!dereset) 312 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; 313 else 314 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; 315 316 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); 317 } 318 319 static void 320 hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset) 321 { 322 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 323 HNS_PPE_RESET_FUNC, port, dereset); 324 } 325 326 static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset) 327 { 328 u32 reg_val; 329 u32 reg_addr; 330 331 if (!(dev_of_node(dsaf_dev->dev))) 332 return; 333 334 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 335 reg_val = RESET_REQ_OR_DREQ; 336 if (!dereset) 337 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG; 338 else 339 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG; 340 341 } else { 342 reg_val = 0x100 << dsaf_dev->reset_offset; 343 344 if (!dereset) 345 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; 346 else 347 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG; 348 } 349 350 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); 351 } 352 353 /** 354 * hns_mac_get_sds_mode - get phy ifterface form serdes mode 355 * @mac_cb: mac control block 356 * retuen phy interface 357 */ 358 static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb) 359 { 360 u32 mode; 361 u32 reg; 362 bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver); 363 int mac_id = mac_cb->mac_id; 364 phy_interface_t phy_if; 365 366 if (is_ver1) { 367 if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) 368 return PHY_INTERFACE_MODE_SGMII; 369 370 if (mac_id >= 0 && mac_id <= 3) 371 reg = HNS_MAC_HILINK4_REG; 372 else 373 reg = HNS_MAC_HILINK3_REG; 374 } else{ 375 if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3) 376 reg = HNS_MAC_HILINK4V2_REG; 377 else 378 reg = HNS_MAC_HILINK3V2_REG; 379 } 380 381 mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); 382 if (dsaf_get_bit(mode, mac_cb->port_mode_off)) 383 phy_if = PHY_INTERFACE_MODE_XGMII; 384 else 385 phy_if = PHY_INTERFACE_MODE_SGMII; 386 387 return phy_if; 388 } 389 390 static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb) 391 { 392 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA; 393 union acpi_object *obj; 394 union acpi_object obj_args, argv4; 395 396 obj_args.integer.type = ACPI_TYPE_INTEGER; 397 obj_args.integer.value = mac_cb->mac_id; 398 399 argv4.type = ACPI_TYPE_PACKAGE, 400 argv4.package.count = 1, 401 argv4.package.elements = &obj_args, 402 403 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev), 404 hns_dsaf_acpi_dsm_uuid, 0, 405 HNS_OP_GET_PORT_TYPE_FUNC, &argv4); 406 407 if (!obj || obj->type != ACPI_TYPE_INTEGER) 408 return phy_if; 409 410 phy_if = obj->integer.value ? 411 PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII; 412 413 dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if); 414 415 ACPI_FREE(obj); 416 417 return phy_if; 418 } 419 420 int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt) 421 { 422 if (!mac_cb->cpld_ctrl) 423 return -ENODEV; 424 425 *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg 426 + MAC_SFP_PORT_OFFSET); 427 428 return 0; 429 } 430 431 /** 432 * hns_mac_config_sds_loopback - set loop back for serdes 433 * @mac_cb: mac control block 434 * retuen 0 == success 435 */ 436 static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en) 437 { 438 const u8 lane_id[] = { 439 0, /* mac 0 -> lane 0 */ 440 1, /* mac 1 -> lane 1 */ 441 2, /* mac 2 -> lane 2 */ 442 3, /* mac 3 -> lane 3 */ 443 2, /* mac 4 -> lane 2 */ 444 3, /* mac 5 -> lane 3 */ 445 0, /* mac 6 -> lane 0 */ 446 1 /* mac 7 -> lane 1 */ 447 }; 448 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2) 449 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0); 450 451 int sfp_prsnt; 452 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt); 453 454 if (!mac_cb->phy_dev) { 455 if (ret) 456 pr_info("please confirm sfp is present or not\n"); 457 else 458 if (!sfp_prsnt) 459 pr_info("no sfp in this eth\n"); 460 } 461 462 if (mac_cb->serdes_ctrl) { 463 u32 origin; 464 465 if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) { 466 #define HILINK_ACCESS_SEL_CFG 0x40008 467 /* hilink4 & hilink3 use the same xge training and 468 * xge u adaptor. There is a hilink access sel cfg 469 * register to select which one to be configed 470 */ 471 if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) && 472 (mac_cb->mac_id <= 3)) 473 dsaf_write_syscon(mac_cb->serdes_ctrl, 474 HILINK_ACCESS_SEL_CFG, 0); 475 else 476 dsaf_write_syscon(mac_cb->serdes_ctrl, 477 HILINK_ACCESS_SEL_CFG, 3); 478 } 479 480 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset); 481 482 dsaf_set_field(origin, 1ull << 10, 10, en); 483 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin); 484 } else { 485 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr + 486 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000); 487 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en); 488 } 489 490 return 0; 491 } 492 493 static int 494 hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en) 495 { 496 union acpi_object *obj; 497 union acpi_object obj_args[3], argv4; 498 499 obj_args[0].integer.type = ACPI_TYPE_INTEGER; 500 obj_args[0].integer.value = mac_cb->mac_id; 501 obj_args[1].integer.type = ACPI_TYPE_INTEGER; 502 obj_args[1].integer.value = !!en; 503 504 argv4.type = ACPI_TYPE_PACKAGE; 505 argv4.package.count = 2; 506 argv4.package.elements = obj_args; 507 508 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev), 509 hns_dsaf_acpi_dsm_uuid, 0, 510 HNS_OP_SERDES_LP_FUNC, &argv4); 511 if (!obj) { 512 dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!", 513 mac_cb->mac_id); 514 515 return -ENOTSUPP; 516 } 517 518 ACPI_FREE(obj); 519 520 return 0; 521 } 522 523 struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev) 524 { 525 struct dsaf_misc_op *misc_op; 526 527 misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL); 528 if (!misc_op) 529 return NULL; 530 531 if (dev_of_node(dsaf_dev->dev)) { 532 misc_op->cpld_set_led = hns_cpld_set_led; 533 misc_op->cpld_reset_led = cpld_led_reset; 534 misc_op->cpld_set_led_id = cpld_set_led_id; 535 536 misc_op->dsaf_reset = hns_dsaf_rst; 537 misc_op->xge_srst = hns_dsaf_xge_srst_by_port; 538 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port; 539 misc_op->ge_srst = hns_dsaf_ge_srst_by_port; 540 misc_op->ppe_srst = hns_ppe_srst_by_port; 541 misc_op->ppe_comm_srst = hns_ppe_com_srst; 542 543 misc_op->get_phy_if = hns_mac_get_phy_if; 544 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; 545 546 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback; 547 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { 548 misc_op->cpld_set_led = hns_cpld_set_led; 549 misc_op->cpld_reset_led = cpld_led_reset; 550 misc_op->cpld_set_led_id = cpld_set_led_id; 551 552 misc_op->dsaf_reset = hns_dsaf_rst_acpi; 553 misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi; 554 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi; 555 misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi; 556 misc_op->ppe_srst = hns_ppe_srst_by_port_acpi; 557 misc_op->ppe_comm_srst = hns_ppe_com_srst; 558 559 misc_op->get_phy_if = hns_mac_get_phy_if_acpi; 560 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; 561 562 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi; 563 } else { 564 devm_kfree(dsaf_dev->dev, (void *)misc_op); 565 misc_op = NULL; 566 } 567 568 return (void *)misc_op; 569 } 570