1 /*
2  * Copyright (c) 2014-2015 Hisilicon Limited.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  */
9 
10 #include "hns_dsaf_misc.h"
11 #include "hns_dsaf_mac.h"
12 #include "hns_dsaf_reg.h"
13 #include "hns_dsaf_ppe.h"
14 
15 void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
16 		      u16 speed, int data)
17 {
18 	int speed_reg = 0;
19 	u8 value;
20 
21 	if (!mac_cb) {
22 		pr_err("sfp_led_opt mac_dev is null!\n");
23 		return;
24 	}
25 	if (!mac_cb->cpld_vaddr) {
26 		dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
27 			mac_cb->mac_id);
28 		return;
29 	}
30 
31 	if (speed == MAC_SPEED_10000)
32 		speed_reg = 1;
33 
34 	value = mac_cb->cpld_led_value;
35 
36 	if (link_status) {
37 		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
38 		dsaf_set_field(value, DSAF_LED_SPEED_M,
39 			       DSAF_LED_SPEED_S, speed_reg);
40 		dsaf_set_bit(value, DSAF_LED_DATA_B, data);
41 
42 		if (value != mac_cb->cpld_led_value) {
43 			dsaf_write_b(mac_cb->cpld_vaddr, value);
44 			mac_cb->cpld_led_value = value;
45 		}
46 	} else {
47 		dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
48 		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
49 	}
50 }
51 
52 void cpld_led_reset(struct hns_mac_cb *mac_cb)
53 {
54 	if (!mac_cb || !mac_cb->cpld_vaddr)
55 		return;
56 
57 	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
58 	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
59 }
60 
61 int cpld_set_led_id(struct hns_mac_cb *mac_cb,
62 		    enum hnae_led_state status)
63 {
64 	switch (status) {
65 	case HNAE_LED_ACTIVE:
66 		mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
67 		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
68 			     CPLD_LED_ON_VALUE);
69 		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
70 		return 2;
71 	case HNAE_LED_INACTIVE:
72 		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
73 			     CPLD_LED_DEFAULT_VALUE);
74 		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
75 		break;
76 	default:
77 		break;
78 	}
79 
80 	return 0;
81 }
82 
83 #define RESET_REQ_OR_DREQ 1
84 
85 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
86 {
87 	u32 xbar_reg_addr;
88 	u32 nt_reg_addr;
89 
90 	if (!val) {
91 		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
92 		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
93 	} else {
94 		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
95 		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
96 	}
97 
98 	dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
99 		       RESET_REQ_OR_DREQ);
100 	dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
101 		       RESET_REQ_OR_DREQ);
102 }
103 
104 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
105 {
106 	u32 reg_val = 0;
107 	u32 reg_addr;
108 
109 	if (port >= DSAF_XGE_NUM)
110 		return;
111 
112 	reg_val |= RESET_REQ_OR_DREQ;
113 	reg_val |= 0x2082082 << port;
114 
115 	if (val == 0)
116 		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
117 	else
118 		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
119 
120 	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
121 }
122 
123 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
124 				    u32 port, u32 val)
125 {
126 	u32 reg_val = 0;
127 	u32 reg_addr;
128 
129 	if (port >= DSAF_XGE_NUM)
130 		return;
131 
132 	reg_val |= XGMAC_TRX_CORE_SRST_M << port;
133 
134 	if (val == 0)
135 		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
136 	else
137 		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
138 
139 	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
140 }
141 
142 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
143 {
144 	u32 reg_val_1;
145 	u32 reg_val_2;
146 
147 	if (port >= DSAF_GE_NUM)
148 		return;
149 
150 	if (port < DSAF_SERVICE_NW_NUM) {
151 		reg_val_1  = 0x1 << port;
152 		/* there is difference between V1 and V2 in register.*/
153 		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
154 			reg_val_2  = 0x1041041 << port;
155 		else
156 			reg_val_2  = 0x2082082 << port;
157 
158 		if (val == 0) {
159 			dsaf_write_reg(dsaf_dev->sc_base,
160 				       DSAF_SUB_SC_GE_RESET_REQ1_REG,
161 				       reg_val_1);
162 
163 			dsaf_write_reg(dsaf_dev->sc_base,
164 				       DSAF_SUB_SC_GE_RESET_REQ0_REG,
165 				       reg_val_2);
166 		} else {
167 			dsaf_write_reg(dsaf_dev->sc_base,
168 				       DSAF_SUB_SC_GE_RESET_DREQ0_REG,
169 				       reg_val_2);
170 
171 			dsaf_write_reg(dsaf_dev->sc_base,
172 				       DSAF_SUB_SC_GE_RESET_DREQ1_REG,
173 				       reg_val_1);
174 		}
175 	} else {
176 		reg_val_1 = 0x15540 << (port - 6);
177 		reg_val_2 = 0x100 << (port - 6);
178 
179 		if (val == 0) {
180 			dsaf_write_reg(dsaf_dev->sc_base,
181 				       DSAF_SUB_SC_GE_RESET_REQ1_REG,
182 				       reg_val_1);
183 
184 			dsaf_write_reg(dsaf_dev->sc_base,
185 				       DSAF_SUB_SC_PPE_RESET_REQ_REG,
186 				       reg_val_2);
187 		} else {
188 			dsaf_write_reg(dsaf_dev->sc_base,
189 				       DSAF_SUB_SC_GE_RESET_DREQ1_REG,
190 				       reg_val_1);
191 
192 			dsaf_write_reg(dsaf_dev->sc_base,
193 				       DSAF_SUB_SC_PPE_RESET_DREQ_REG,
194 				       reg_val_2);
195 		}
196 	}
197 }
198 
199 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
200 {
201 	u32 reg_val = 0;
202 	u32 reg_addr;
203 
204 	reg_val |= RESET_REQ_OR_DREQ << port;
205 
206 	if (val == 0)
207 		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
208 	else
209 		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
210 
211 	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
212 }
213 
214 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
215 {
216 	int comm_index = ppe_common->comm_index;
217 	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
218 	u32 reg_val;
219 	u32 reg_addr;
220 
221 	if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
222 		reg_val = RESET_REQ_OR_DREQ;
223 		if (val == 0)
224 			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
225 		else
226 			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
227 
228 	} else {
229 		reg_val = 0x100 << (comm_index - 1);
230 
231 		if (val == 0)
232 			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
233 		else
234 			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
235 	}
236 
237 	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
238 }
239 
240 /**
241  * hns_mac_get_sds_mode - get phy ifterface form serdes mode
242  * @mac_cb: mac control block
243  * retuen phy interface
244  */
245 phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
246 {
247 	u32 hilink3_mode;
248 	u32 hilink4_mode;
249 	void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
250 	int dev_id = mac_cb->mac_id;
251 	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
252 
253 	hilink3_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK3_REG);
254 	hilink4_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK4_REG);
255 	if (dev_id >= 0 && dev_id <= 3) {
256 		if (hilink4_mode == 0)
257 			phy_if = PHY_INTERFACE_MODE_SGMII;
258 		else
259 			phy_if = PHY_INTERFACE_MODE_XGMII;
260 	} else if (dev_id >= 4 && dev_id <= 5) {
261 		if (hilink3_mode == 0)
262 			phy_if = PHY_INTERFACE_MODE_SGMII;
263 		else
264 			phy_if = PHY_INTERFACE_MODE_XGMII;
265 	} else {
266 		phy_if = PHY_INTERFACE_MODE_SGMII;
267 	}
268 
269 	dev_dbg(mac_cb->dev,
270 		"hilink3_mode=%d, hilink4_mode=%d dev_id=%d, phy_if=%d\n",
271 		hilink3_mode, hilink4_mode, dev_id, phy_if);
272 	return phy_if;
273 }
274 
275 /**
276  * hns_mac_config_sds_loopback - set loop back for serdes
277  * @mac_cb: mac control block
278  * retuen 0 == success
279  */
280 int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
281 {
282 	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
283 	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
284 	 */
285 	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
286 		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
287 	const u8 lane_id[] = {
288 		0,	/* mac 0 -> lane 0 */
289 		1,	/* mac 1 -> lane 1 */
290 		2,	/* mac 2 -> lane 2 */
291 		3,	/* mac 3 -> lane 3 */
292 		2,	/* mac 4 -> lane 2 */
293 		3,	/* mac 5 -> lane 3 */
294 		0,	/* mac 6 -> lane 0 */
295 		1	/* mac 7 -> lane 1 */
296 	};
297 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
298 	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
299 
300 	int sfp_prsnt;
301 	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
302 
303 	if (!mac_cb->phy_node) {
304 		if (ret)
305 			pr_info("please confirm sfp is present or not\n");
306 		else
307 			if (!sfp_prsnt)
308 				pr_info("no sfp in this eth\n");
309 	}
310 
311 	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
312 
313 	return 0;
314 }
315