1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS_DSAF_MAIN_H 11 #define __HNS_DSAF_MAIN_H 12 #include "hnae.h" 13 14 #include "hns_dsaf_reg.h" 15 #include "hns_dsaf_mac.h" 16 17 struct hns_mac_cb; 18 19 #define DSAF_DRV_NAME "hns_dsaf" 20 #define DSAF_MOD_VERSION "v1.0" 21 #define DSAF_DEVICE_NAME "dsaf" 22 23 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000 24 25 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/ 26 27 #define DSAF_MAX_CHIP_NUM 2 /*max 2 chips */ 28 29 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22 30 31 #define HNS_DSAF_MAX_DESC_CNT 1024 32 #define HNS_DSAF_MIN_DESC_CNT 16 33 34 #define DSAF_INVALID_ENTRY_IDX 0xffff 35 36 #define DSAF_CFG_READ_CNT 30 37 38 #define MAC_NUM_OCTETS_PER_ADDR 6 39 40 #define DSAF_DUMP_REGS_NUM 504 41 #define DSAF_STATIC_NUM 28 42 43 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 44 45 enum hal_dsaf_mode { 46 HRD_DSAF_NO_DSAF_MODE = 0x0, 47 HRD_DSAF_MODE = 0x1, 48 }; 49 50 enum hal_dsaf_tc_mode { 51 HRD_DSAF_4TC_MODE = 0X0, 52 HRD_DSAF_8TC_MODE = 0X1, 53 }; 54 55 struct dsaf_vm_def_vlan { 56 u32 vm_def_vlan_id; 57 u32 vm_def_vlan_cfi; 58 u32 vm_def_vlan_pri; 59 }; 60 61 struct dsaf_tbl_tcam_data { 62 u32 tbl_tcam_data_high; 63 u32 tbl_tcam_data_low; 64 }; 65 66 #define DSAF_PORT_MSK_NUM \ 67 ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1) 68 struct dsaf_tbl_tcam_mcast_cfg { 69 u8 tbl_mcast_old_en; 70 u8 tbl_mcast_item_vld; 71 u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM]; 72 }; 73 74 struct dsaf_tbl_tcam_ucast_cfg { 75 u32 tbl_ucast_old_en; 76 u32 tbl_ucast_item_vld; 77 u32 tbl_ucast_mac_discard; 78 u32 tbl_ucast_dvc; 79 u32 tbl_ucast_out_port; 80 }; 81 82 struct dsaf_tbl_line_cfg { 83 u32 tbl_line_mac_discard; 84 u32 tbl_line_dvc; 85 u32 tbl_line_out_port; 86 }; 87 88 enum dsaf_port_rate_mode { 89 DSAF_PORT_RATE_1000 = 0, 90 DSAF_PORT_RATE_2500, 91 DSAF_PORT_RATE_10000 92 }; 93 94 enum dsaf_stp_port_type { 95 DSAF_STP_PORT_TYPE_DISCARD = 0, 96 DSAF_STP_PORT_TYPE_BLOCK = 1, 97 DSAF_STP_PORT_TYPE_LISTEN = 2, 98 DSAF_STP_PORT_TYPE_LEARN = 3, 99 DSAF_STP_PORT_TYPE_FORWARD = 4 100 }; 101 102 enum dsaf_sw_port_type { 103 DSAF_SW_PORT_TYPE_NON_VLAN = 0, 104 DSAF_SW_PORT_TYPE_ACCESS = 1, 105 DSAF_SW_PORT_TYPE_TRUNK = 2, 106 }; 107 108 #define DSAF_SUB_BASE_SIZE (0x10000) 109 110 /* dsaf mode define */ 111 enum dsaf_mode { 112 DSAF_MODE_INVALID = 0, /**< Invalid dsaf mode */ 113 DSAF_MODE_ENABLE_FIX, /**< en DSAF-mode, fixed to queue*/ 114 DSAF_MODE_ENABLE_0VM, /**< en DSAF-mode, support 0 VM */ 115 DSAF_MODE_ENABLE_8VM, /**< en DSAF-mode, support 8 VM */ 116 DSAF_MODE_ENABLE_16VM, /**< en DSAF-mode, support 16 VM */ 117 DSAF_MODE_ENABLE_32VM, /**< en DSAF-mode, support 32 VM */ 118 DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */ 119 DSAF_MODE_ENABLE, /**< before is enable DSAF mode*/ 120 DSAF_MODE_DISABLE_FIX, /**< non-dasf, fixed to queue*/ 121 DSAF_MODE_DISABLE_2PORT_8VM, /**< non-dasf, 2port 8VM */ 122 DSAF_MODE_DISABLE_2PORT_16VM, /**< non-dasf, 2port 16VM */ 123 DSAF_MODE_DISABLE_2PORT_64VM, /**< non-dasf, 2port 64VM */ 124 DSAF_MODE_DISABLE_6PORT_0VM, /**< non-dasf, 6port 0VM */ 125 DSAF_MODE_DISABLE_6PORT_2VM, /**< non-dasf, 6port 2VM */ 126 DSAF_MODE_DISABLE_6PORT_4VM, /**< non-dasf, 6port 4VM */ 127 DSAF_MODE_DISABLE_6PORT_16VM, /**< non-dasf, 6port 16VM */ 128 DSAF_MODE_MAX /**< the last one, use as the num */ 129 }; 130 131 #define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */ 132 #define DSAF_WORD_BIT_CNT 32 /* the num bit of word */ 133 134 /*mac entry, mc or uc entry*/ 135 struct dsaf_drv_mac_single_dest_entry { 136 /* mac addr, match the entry*/ 137 u8 addr[MAC_NUM_OCTETS_PER_ADDR]; 138 u16 in_vlan_id; /* value of VlanId */ 139 140 /* the vld input port num, dsaf-mode fix 0, */ 141 /* non-dasf is the entry whitch port vld*/ 142 u8 in_port_num; 143 144 u8 port_num; /*output port num*/ 145 u8 rsv[6]; 146 }; 147 148 /*only mc entry*/ 149 struct dsaf_drv_mac_multi_dest_entry { 150 /* mac addr, match the entry*/ 151 u8 addr[MAC_NUM_OCTETS_PER_ADDR]; 152 u16 in_vlan_id; 153 /* this mac addr output port,*/ 154 /* bit0-bit5 means Port0-Port5(1bit is vld)**/ 155 u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT]; 156 157 /* the vld input port num, dsaf-mode fix 0,*/ 158 /* non-dasf is the entry whitch port vld*/ 159 u8 in_port_num; 160 u8 rsv[7]; 161 }; 162 163 struct dsaf_hw_stats { 164 u64 pad_drop; 165 u64 man_pkts; 166 u64 rx_pkts; 167 u64 rx_pkt_id; 168 u64 rx_pause_frame; 169 u64 release_buf_num; 170 u64 sbm_drop; 171 u64 crc_false; 172 u64 bp_drop; 173 u64 rslt_drop; 174 u64 local_addr_false; 175 u64 vlan_drop; 176 u64 stp_drop; 177 u64 tx_pkts; 178 }; 179 180 struct hnae_vf_cb { 181 u8 port_index; 182 struct hns_mac_cb *mac_cb; 183 struct dsaf_device *dsaf_dev; 184 struct hnae_handle ae_handle; /* must be the last number */ 185 }; 186 187 struct dsaf_int_xge_src { 188 u32 xid_xge_ecc_err_int_src; 189 u32 xid_xge_fsm_timout_int_src; 190 u32 sbm_xge_lnk_fsm_timout_int_src; 191 u32 sbm_xge_lnk_ecc_2bit_int_src; 192 u32 sbm_xge_mib_req_failed_int_src; 193 u32 sbm_xge_mib_req_fsm_timout_int_src; 194 u32 sbm_xge_mib_rels_fsm_timout_int_src; 195 u32 sbm_xge_sram_ecc_2bit_int_src; 196 u32 sbm_xge_mib_buf_sum_err_int_src; 197 u32 sbm_xge_mib_req_extra_int_src; 198 u32 sbm_xge_mib_rels_extra_int_src; 199 u32 voq_xge_start_to_over_0_int_src; 200 u32 voq_xge_start_to_over_1_int_src; 201 u32 voq_xge_ecc_err_int_src; 202 }; 203 204 struct dsaf_int_ppe_src { 205 u32 xid_ppe_fsm_timout_int_src; 206 u32 sbm_ppe_lnk_fsm_timout_int_src; 207 u32 sbm_ppe_lnk_ecc_2bit_int_src; 208 u32 sbm_ppe_mib_req_failed_int_src; 209 u32 sbm_ppe_mib_req_fsm_timout_int_src; 210 u32 sbm_ppe_mib_rels_fsm_timout_int_src; 211 u32 sbm_ppe_sram_ecc_2bit_int_src; 212 u32 sbm_ppe_mib_buf_sum_err_int_src; 213 u32 sbm_ppe_mib_req_extra_int_src; 214 u32 sbm_ppe_mib_rels_extra_int_src; 215 u32 voq_ppe_start_to_over_0_int_src; 216 u32 voq_ppe_ecc_err_int_src; 217 u32 xod_ppe_fifo_rd_empty_int_src; 218 u32 xod_ppe_fifo_wr_full_int_src; 219 }; 220 221 struct dsaf_int_rocee_src { 222 u32 xid_rocee_fsm_timout_int_src; 223 u32 sbm_rocee_lnk_fsm_timout_int_src; 224 u32 sbm_rocee_lnk_ecc_2bit_int_src; 225 u32 sbm_rocee_mib_req_failed_int_src; 226 u32 sbm_rocee_mib_req_fsm_timout_int_src; 227 u32 sbm_rocee_mib_rels_fsm_timout_int_src; 228 u32 sbm_rocee_sram_ecc_2bit_int_src; 229 u32 sbm_rocee_mib_buf_sum_err_int_src; 230 u32 sbm_rocee_mib_req_extra_int_src; 231 u32 sbm_rocee_mib_rels_extra_int_src; 232 u32 voq_rocee_start_to_over_0_int_src; 233 u32 voq_rocee_ecc_err_int_src; 234 }; 235 236 struct dsaf_int_tbl_src { 237 u32 tbl_da0_mis_src; 238 u32 tbl_da1_mis_src; 239 u32 tbl_da2_mis_src; 240 u32 tbl_da3_mis_src; 241 u32 tbl_da4_mis_src; 242 u32 tbl_da5_mis_src; 243 u32 tbl_da6_mis_src; 244 u32 tbl_da7_mis_src; 245 u32 tbl_sa_mis_src; 246 u32 tbl_old_sech_end_src; 247 u32 lram_ecc_err1_src; 248 u32 lram_ecc_err2_src; 249 u32 tram_ecc_err1_src; 250 u32 tram_ecc_err2_src; 251 u32 tbl_ucast_bcast_xge0_src; 252 u32 tbl_ucast_bcast_xge1_src; 253 u32 tbl_ucast_bcast_xge2_src; 254 u32 tbl_ucast_bcast_xge3_src; 255 u32 tbl_ucast_bcast_xge4_src; 256 u32 tbl_ucast_bcast_xge5_src; 257 u32 tbl_ucast_bcast_ppe_src; 258 u32 tbl_ucast_bcast_rocee_src; 259 }; 260 261 struct dsaf_int_stat { 262 struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN]; 263 struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN]; 264 struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN]; 265 struct dsaf_int_tbl_src dsaf_int_tbl_stat[1]; 266 267 }; 268 269 /* Dsaf device struct define ,and mac -> dsaf */ 270 struct dsaf_device { 271 struct device *dev; 272 struct hnae_ae_dev ae_dev; 273 274 u8 __iomem *sc_base; 275 u8 __iomem *sds_base; 276 u8 __iomem *ppe_base; 277 u8 __iomem *io_base; 278 u8 __iomem *cpld_base; 279 280 u32 desc_num; /* desc num per queue*/ 281 u32 buf_size; /* ring buffer size */ 282 int buf_size_type; /* ring buffer size-type */ 283 enum dsaf_mode dsaf_mode; /* dsaf mode */ 284 enum hal_dsaf_mode dsaf_en; 285 enum hal_dsaf_tc_mode dsaf_tc_mode; 286 u32 dsaf_ver; 287 288 struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM]; 289 struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM]; 290 struct hns_mac_cb *mac_cb; 291 292 struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM]; 293 struct dsaf_int_stat int_stat; 294 }; 295 296 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev) 297 { 298 return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev)); 299 } 300 301 struct dsaf_drv_tbl_tcam_key { 302 union { 303 struct { 304 u8 mac_3; 305 u8 mac_2; 306 u8 mac_1; 307 u8 mac_0; 308 } bits; 309 310 u32 val; 311 } high; 312 union { 313 struct { 314 u32 port:4; /* port id, */ 315 /* dsaf-mode fixed 0, non-dsaf-mode port id*/ 316 u32 vlan:12; /* vlan id */ 317 u32 mac_5:8; 318 u32 mac_4:8; 319 } bits; 320 321 u32 val; 322 } low; 323 }; 324 325 struct dsaf_drv_soft_mac_tbl { 326 struct dsaf_drv_tbl_tcam_key tcam_key; 327 u16 index; /*the entry's index in tcam tab*/ 328 }; 329 330 struct dsaf_drv_priv { 331 /* soft tab Mac key, for hardware tab*/ 332 struct dsaf_drv_soft_mac_tbl *soft_mac_tbl; 333 }; 334 335 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev, 336 u32 tab_tcam_addr) 337 { 338 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG, 339 DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S, 340 tab_tcam_addr); 341 } 342 343 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev) 344 { 345 u32 o_tbl_pul; 346 347 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 348 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1); 349 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 350 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0); 351 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 352 } 353 354 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev, 355 u32 tab_line_addr) 356 { 357 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG, 358 DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S, 359 tab_line_addr); 360 } 361 362 static inline int hns_dsaf_get_comm_idx_by_port(int port) 363 { 364 if ((port < DSAF_COMM_CHN) || (port == DSAF_MAX_PORT_NUM_PER_CHIP)) 365 return 0; 366 else 367 return (port - DSAF_COMM_CHN + 1); 368 } 369 370 static inline struct hnae_vf_cb *hns_ae_get_vf_cb( 371 struct hnae_handle *handle) 372 { 373 return container_of(handle, struct hnae_vf_cb, ae_handle); 374 } 375 376 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev, 377 struct dsaf_drv_mac_single_dest_entry *mac_entry); 378 int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev, 379 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 380 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 381 struct dsaf_drv_mac_single_dest_entry *mac_entry); 382 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 383 u8 in_port_num, u8 *addr); 384 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 385 struct dsaf_drv_mac_single_dest_entry *mac_entry); 386 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev, 387 struct dsaf_drv_mac_single_dest_entry *mac_entry); 388 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev, 389 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 390 int hns_dsaf_get_mac_entry_by_index( 391 struct dsaf_device *dsaf_dev, 392 u16 entry_index, 393 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 394 395 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val); 396 397 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val); 398 399 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val); 400 401 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb); 402 403 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev); 404 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev); 405 406 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val); 407 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val); 408 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev, 409 u32 port, u32 val); 410 411 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num); 412 413 int hns_dsaf_get_sset_count(int stringset); 414 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port); 415 void hns_dsaf_get_strings(int stringset, u8 *data, int port); 416 417 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data); 418 int hns_dsaf_get_regs_count(void); 419 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en); 420 void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en); 421 422 #endif /* __HNS_DSAF_MAIN_H__ */ 423