1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS_DSAF_MAIN_H 11 #define __HNS_DSAF_MAIN_H 12 #include "hnae.h" 13 14 #include "hns_dsaf_reg.h" 15 #include "hns_dsaf_mac.h" 16 17 struct hns_mac_cb; 18 19 #define DSAF_DRV_NAME "hns_dsaf" 20 #define DSAF_MOD_VERSION "v1.0" 21 #define DSAF_DEVICE_NAME "dsaf" 22 23 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000 24 25 #define DSAF_BASE_INNER_PORT_NUM 127/* mac tbl qid*/ 26 27 #define DSAF_MAX_CHIP_NUM 2 /*max 2 chips */ 28 29 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22 30 31 #define HNS_DSAF_MAX_DESC_CNT 1024 32 #define HNS_DSAF_MIN_DESC_CNT 16 33 34 #define DSAF_INVALID_ENTRY_IDX 0xffff 35 36 #define DSAF_CFG_READ_CNT 30 37 38 #define MAC_NUM_OCTETS_PER_ADDR 6 39 40 #define DSAF_DUMP_REGS_NUM 504 41 #define DSAF_STATIC_NUM 28 42 #define DSAF_V2_STATIC_NUM 44 43 #define DSAF_PRIO_NR 8 44 #define DSAF_REG_PER_ZONE 3 45 46 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 47 #define HNS_DSAF_IS_DEBUG(dev) (dev->dsaf_mode == DSAF_MODE_DISABLE_SP) 48 49 enum hal_dsaf_mode { 50 HRD_DSAF_NO_DSAF_MODE = 0x0, 51 HRD_DSAF_MODE = 0x1, 52 }; 53 54 enum hal_dsaf_tc_mode { 55 HRD_DSAF_4TC_MODE = 0X0, 56 HRD_DSAF_8TC_MODE = 0X1, 57 }; 58 59 struct dsaf_vm_def_vlan { 60 u32 vm_def_vlan_id; 61 u32 vm_def_vlan_cfi; 62 u32 vm_def_vlan_pri; 63 }; 64 65 struct dsaf_tbl_tcam_data { 66 u32 tbl_tcam_data_high; 67 u32 tbl_tcam_data_low; 68 }; 69 70 #define DSAF_PORT_MSK_NUM \ 71 ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1) 72 struct dsaf_tbl_tcam_mcast_cfg { 73 u8 tbl_mcast_old_en; 74 u8 tbl_mcast_item_vld; 75 u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM]; 76 }; 77 78 struct dsaf_tbl_tcam_ucast_cfg { 79 u32 tbl_ucast_old_en; 80 u32 tbl_ucast_item_vld; 81 u32 tbl_ucast_mac_discard; 82 u32 tbl_ucast_dvc; 83 u32 tbl_ucast_out_port; 84 }; 85 86 struct dsaf_tbl_line_cfg { 87 u32 tbl_line_mac_discard; 88 u32 tbl_line_dvc; 89 u32 tbl_line_out_port; 90 }; 91 92 enum dsaf_port_rate_mode { 93 DSAF_PORT_RATE_1000 = 0, 94 DSAF_PORT_RATE_2500, 95 DSAF_PORT_RATE_10000 96 }; 97 98 enum dsaf_stp_port_type { 99 DSAF_STP_PORT_TYPE_DISCARD = 0, 100 DSAF_STP_PORT_TYPE_BLOCK = 1, 101 DSAF_STP_PORT_TYPE_LISTEN = 2, 102 DSAF_STP_PORT_TYPE_LEARN = 3, 103 DSAF_STP_PORT_TYPE_FORWARD = 4 104 }; 105 106 enum dsaf_sw_port_type { 107 DSAF_SW_PORT_TYPE_NON_VLAN = 0, 108 DSAF_SW_PORT_TYPE_ACCESS = 1, 109 DSAF_SW_PORT_TYPE_TRUNK = 2, 110 }; 111 112 #define DSAF_SUB_BASE_SIZE (0x10000) 113 114 /* dsaf mode define */ 115 enum dsaf_mode { 116 DSAF_MODE_INVALID = 0, /**< Invalid dsaf mode */ 117 DSAF_MODE_ENABLE_FIX, /**< en DSAF-mode, fixed to queue*/ 118 DSAF_MODE_ENABLE_0VM, /**< en DSAF-mode, support 0 VM */ 119 DSAF_MODE_ENABLE_8VM, /**< en DSAF-mode, support 8 VM */ 120 DSAF_MODE_ENABLE_16VM, /**< en DSAF-mode, support 16 VM */ 121 DSAF_MODE_ENABLE_32VM, /**< en DSAF-mode, support 32 VM */ 122 DSAF_MODE_ENABLE_128VM, /**< en DSAF-mode, support 128 VM */ 123 DSAF_MODE_ENABLE, /**< before is enable DSAF mode*/ 124 DSAF_MODE_DISABLE_SP, /* <non-dsaf, single port mode */ 125 DSAF_MODE_DISABLE_FIX, /**< non-dasf, fixed to queue*/ 126 DSAF_MODE_DISABLE_2PORT_8VM, /**< non-dasf, 2port 8VM */ 127 DSAF_MODE_DISABLE_2PORT_16VM, /**< non-dasf, 2port 16VM */ 128 DSAF_MODE_DISABLE_2PORT_64VM, /**< non-dasf, 2port 64VM */ 129 DSAF_MODE_DISABLE_6PORT_0VM, /**< non-dasf, 6port 0VM */ 130 DSAF_MODE_DISABLE_6PORT_2VM, /**< non-dasf, 6port 2VM */ 131 DSAF_MODE_DISABLE_6PORT_4VM, /**< non-dasf, 6port 4VM */ 132 DSAF_MODE_DISABLE_6PORT_16VM, /**< non-dasf, 6port 16VM */ 133 DSAF_MODE_MAX /**< the last one, use as the num */ 134 }; 135 136 #define DSAF_DEST_PORT_NUM 256 /* DSAF max port num */ 137 #define DSAF_WORD_BIT_CNT 32 /* the num bit of word */ 138 139 /*mac entry, mc or uc entry*/ 140 struct dsaf_drv_mac_single_dest_entry { 141 /* mac addr, match the entry*/ 142 u8 addr[MAC_NUM_OCTETS_PER_ADDR]; 143 u16 in_vlan_id; /* value of VlanId */ 144 145 /* the vld input port num, dsaf-mode fix 0, */ 146 /* non-dasf is the entry whitch port vld*/ 147 u8 in_port_num; 148 149 u8 port_num; /*output port num*/ 150 u8 rsv[6]; 151 }; 152 153 /*only mc entry*/ 154 struct dsaf_drv_mac_multi_dest_entry { 155 /* mac addr, match the entry*/ 156 u8 addr[MAC_NUM_OCTETS_PER_ADDR]; 157 u16 in_vlan_id; 158 /* this mac addr output port,*/ 159 /* bit0-bit5 means Port0-Port5(1bit is vld)**/ 160 u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT]; 161 162 /* the vld input port num, dsaf-mode fix 0,*/ 163 /* non-dasf is the entry whitch port vld*/ 164 u8 in_port_num; 165 u8 rsv[7]; 166 }; 167 168 struct dsaf_hw_stats { 169 u64 pad_drop; 170 u64 man_pkts; 171 u64 rx_pkts; 172 u64 rx_pkt_id; 173 u64 rx_pause_frame; 174 u64 release_buf_num; 175 u64 sbm_drop; 176 u64 crc_false; 177 u64 bp_drop; 178 u64 rslt_drop; 179 u64 local_addr_false; 180 u64 vlan_drop; 181 u64 stp_drop; 182 u64 rx_pfc[DSAF_PRIO_NR]; 183 u64 tx_pfc[DSAF_PRIO_NR]; 184 u64 tx_pkts; 185 }; 186 187 struct hnae_vf_cb { 188 u8 port_index; 189 struct hns_mac_cb *mac_cb; 190 struct dsaf_device *dsaf_dev; 191 struct hnae_handle ae_handle; /* must be the last number */ 192 }; 193 194 struct dsaf_int_xge_src { 195 u32 xid_xge_ecc_err_int_src; 196 u32 xid_xge_fsm_timout_int_src; 197 u32 sbm_xge_lnk_fsm_timout_int_src; 198 u32 sbm_xge_lnk_ecc_2bit_int_src; 199 u32 sbm_xge_mib_req_failed_int_src; 200 u32 sbm_xge_mib_req_fsm_timout_int_src; 201 u32 sbm_xge_mib_rels_fsm_timout_int_src; 202 u32 sbm_xge_sram_ecc_2bit_int_src; 203 u32 sbm_xge_mib_buf_sum_err_int_src; 204 u32 sbm_xge_mib_req_extra_int_src; 205 u32 sbm_xge_mib_rels_extra_int_src; 206 u32 voq_xge_start_to_over_0_int_src; 207 u32 voq_xge_start_to_over_1_int_src; 208 u32 voq_xge_ecc_err_int_src; 209 }; 210 211 struct dsaf_int_ppe_src { 212 u32 xid_ppe_fsm_timout_int_src; 213 u32 sbm_ppe_lnk_fsm_timout_int_src; 214 u32 sbm_ppe_lnk_ecc_2bit_int_src; 215 u32 sbm_ppe_mib_req_failed_int_src; 216 u32 sbm_ppe_mib_req_fsm_timout_int_src; 217 u32 sbm_ppe_mib_rels_fsm_timout_int_src; 218 u32 sbm_ppe_sram_ecc_2bit_int_src; 219 u32 sbm_ppe_mib_buf_sum_err_int_src; 220 u32 sbm_ppe_mib_req_extra_int_src; 221 u32 sbm_ppe_mib_rels_extra_int_src; 222 u32 voq_ppe_start_to_over_0_int_src; 223 u32 voq_ppe_ecc_err_int_src; 224 u32 xod_ppe_fifo_rd_empty_int_src; 225 u32 xod_ppe_fifo_wr_full_int_src; 226 }; 227 228 struct dsaf_int_rocee_src { 229 u32 xid_rocee_fsm_timout_int_src; 230 u32 sbm_rocee_lnk_fsm_timout_int_src; 231 u32 sbm_rocee_lnk_ecc_2bit_int_src; 232 u32 sbm_rocee_mib_req_failed_int_src; 233 u32 sbm_rocee_mib_req_fsm_timout_int_src; 234 u32 sbm_rocee_mib_rels_fsm_timout_int_src; 235 u32 sbm_rocee_sram_ecc_2bit_int_src; 236 u32 sbm_rocee_mib_buf_sum_err_int_src; 237 u32 sbm_rocee_mib_req_extra_int_src; 238 u32 sbm_rocee_mib_rels_extra_int_src; 239 u32 voq_rocee_start_to_over_0_int_src; 240 u32 voq_rocee_ecc_err_int_src; 241 }; 242 243 struct dsaf_int_tbl_src { 244 u32 tbl_da0_mis_src; 245 u32 tbl_da1_mis_src; 246 u32 tbl_da2_mis_src; 247 u32 tbl_da3_mis_src; 248 u32 tbl_da4_mis_src; 249 u32 tbl_da5_mis_src; 250 u32 tbl_da6_mis_src; 251 u32 tbl_da7_mis_src; 252 u32 tbl_sa_mis_src; 253 u32 tbl_old_sech_end_src; 254 u32 lram_ecc_err1_src; 255 u32 lram_ecc_err2_src; 256 u32 tram_ecc_err1_src; 257 u32 tram_ecc_err2_src; 258 u32 tbl_ucast_bcast_xge0_src; 259 u32 tbl_ucast_bcast_xge1_src; 260 u32 tbl_ucast_bcast_xge2_src; 261 u32 tbl_ucast_bcast_xge3_src; 262 u32 tbl_ucast_bcast_xge4_src; 263 u32 tbl_ucast_bcast_xge5_src; 264 u32 tbl_ucast_bcast_ppe_src; 265 u32 tbl_ucast_bcast_rocee_src; 266 }; 267 268 struct dsaf_int_stat { 269 struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN]; 270 struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN]; 271 struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN]; 272 struct dsaf_int_tbl_src dsaf_int_tbl_stat[1]; 273 274 }; 275 276 struct dsaf_misc_op { 277 void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status, 278 u16 speed, int data); 279 void (*cpld_reset_led)(struct hns_mac_cb *mac_cb); 280 int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb, 281 enum hnae_led_state status); 282 /* reset seris function, it will be reset if the dereseet is 0 */ 283 void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset); 284 void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 285 void (*xge_core_srst)(struct dsaf_device *dsaf_dev, u32 port, 286 bool dereset); 287 void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 288 void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 289 void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset); 290 291 phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb); 292 int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt); 293 294 int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en); 295 }; 296 297 /* Dsaf device struct define ,and mac -> dsaf */ 298 struct dsaf_device { 299 struct device *dev; 300 struct hnae_ae_dev ae_dev; 301 302 u8 __iomem *sc_base; 303 u8 __iomem *sds_base; 304 u8 __iomem *ppe_base; 305 u8 __iomem *io_base; 306 struct regmap *sub_ctrl; 307 phys_addr_t ppe_paddr; 308 309 u32 desc_num; /* desc num per queue*/ 310 u32 buf_size; /* ring buffer size */ 311 u32 reset_offset; /* reset field offset in sub sysctrl */ 312 int buf_size_type; /* ring buffer size-type */ 313 enum dsaf_mode dsaf_mode; /* dsaf mode */ 314 enum hal_dsaf_mode dsaf_en; 315 enum hal_dsaf_tc_mode dsaf_tc_mode; 316 u32 dsaf_ver; 317 318 struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM]; 319 struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM]; 320 struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM]; 321 struct dsaf_misc_op *misc_op; 322 323 struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM]; 324 struct dsaf_int_stat int_stat; 325 /* make sure tcam table config spinlock */ 326 spinlock_t tcam_lock; 327 }; 328 329 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev) 330 { 331 return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev)); 332 } 333 334 struct dsaf_drv_tbl_tcam_key { 335 union { 336 struct { 337 u8 mac_3; 338 u8 mac_2; 339 u8 mac_1; 340 u8 mac_0; 341 } bits; 342 343 u32 val; 344 } high; 345 union { 346 struct { 347 u32 port:4; /* port id, */ 348 /* dsaf-mode fixed 0, non-dsaf-mode port id*/ 349 u32 vlan:12; /* vlan id */ 350 u32 mac_5:8; 351 u32 mac_4:8; 352 } bits; 353 354 u32 val; 355 } low; 356 }; 357 358 struct dsaf_drv_soft_mac_tbl { 359 struct dsaf_drv_tbl_tcam_key tcam_key; 360 u16 index; /*the entry's index in tcam tab*/ 361 }; 362 363 struct dsaf_drv_priv { 364 /* soft tab Mac key, for hardware tab*/ 365 struct dsaf_drv_soft_mac_tbl *soft_mac_tbl; 366 }; 367 368 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev, 369 u32 tab_tcam_addr) 370 { 371 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG, 372 DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S, 373 tab_tcam_addr); 374 } 375 376 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev) 377 { 378 u32 o_tbl_pul; 379 380 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 381 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1); 382 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 383 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0); 384 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 385 } 386 387 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev, 388 u32 tab_line_addr) 389 { 390 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG, 391 DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S, 392 tab_line_addr); 393 } 394 395 static inline struct hnae_vf_cb *hns_ae_get_vf_cb( 396 struct hnae_handle *handle) 397 { 398 return container_of(handle, struct hnae_vf_cb, ae_handle); 399 } 400 401 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev, 402 struct dsaf_drv_mac_single_dest_entry *mac_entry); 403 int hns_dsaf_set_mac_mc_entry(struct dsaf_device *dsaf_dev, 404 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 405 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 406 struct dsaf_drv_mac_single_dest_entry *mac_entry); 407 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 408 u8 in_port_num, u8 *addr); 409 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 410 struct dsaf_drv_mac_single_dest_entry *mac_entry); 411 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev, 412 struct dsaf_drv_mac_single_dest_entry *mac_entry); 413 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev, 414 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 415 int hns_dsaf_get_mac_entry_by_index( 416 struct dsaf_device *dsaf_dev, 417 u16 entry_index, 418 struct dsaf_drv_mac_multi_dest_entry *mac_entry); 419 420 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb); 421 422 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev); 423 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev); 424 425 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num); 426 427 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset); 428 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port); 429 void hns_dsaf_get_strings(int stringset, u8 *data, int port, 430 struct dsaf_device *dsaf_dev); 431 432 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data); 433 int hns_dsaf_get_regs_count(void); 434 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en); 435 436 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 437 u32 *en); 438 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 439 u32 en); 440 void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en); 441 442 #endif /* __HNS_DSAF_MAIN_H__ */ 443