1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/vmalloc.h> 24 25 #include "hns_dsaf_mac.h" 26 #include "hns_dsaf_main.h" 27 #include "hns_dsaf_ppe.h" 28 #include "hns_dsaf_rcb.h" 29 #include "hns_dsaf_misc.h" 30 31 const static char *g_dsaf_mode_match[DSAF_MODE_MAX] = { 32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf", 33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss", 34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf", 35 [DSAF_MODE_DISABLE_SP] = "single-port", 36 }; 37 38 static const struct acpi_device_id hns_dsaf_acpi_match[] = { 39 { "HISI00B1", 0 }, 40 { "HISI00B2", 0 }, 41 { }, 42 }; 43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match); 44 45 static int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 46 { 47 int ret, i; 48 u32 desc_num; 49 u32 buf_size; 50 u32 reset_offset = 0; 51 u32 res_idx = 0; 52 const char *mode_str; 53 struct regmap *syscon; 54 struct resource *res; 55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp; 56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev); 57 58 if (dev_of_node(dsaf_dev->dev)) { 59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1")) 60 dsaf_dev->dsaf_ver = AE_VERSION_1; 61 else 62 dsaf_dev->dsaf_ver = AE_VERSION_2; 63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { 64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id)) 65 dsaf_dev->dsaf_ver = AE_VERSION_1; 66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id)) 67 dsaf_dev->dsaf_ver = AE_VERSION_2; 68 else 69 return -ENXIO; 70 } else { 71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n"); 72 return -ENXIO; 73 } 74 75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str); 76 if (ret) { 77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret); 78 return ret; 79 } 80 for (i = 0; i < DSAF_MODE_MAX; i++) { 81 if (g_dsaf_mode_match[i] && 82 !strcmp(mode_str, g_dsaf_mode_match[i])) 83 break; 84 } 85 if (i >= DSAF_MODE_MAX || 86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) { 87 dev_err(dsaf_dev->dev, 88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name); 89 return -EINVAL; 90 } 91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i; 92 93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE) 94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE; 95 else 96 dsaf_dev->dsaf_en = HRD_DSAF_MODE; 97 98 if ((i == DSAF_MODE_ENABLE_16VM) || 99 (i == DSAF_MODE_DISABLE_2PORT_8VM) || 100 (i == DSAF_MODE_DISABLE_6PORT_2VM)) 101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE; 102 else 103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE; 104 105 if (dev_of_node(dsaf_dev->dev)) { 106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0); 107 syscon = syscon_node_to_regmap(np_temp); 108 of_node_put(np_temp); 109 if (IS_ERR_OR_NULL(syscon)) { 110 res = platform_get_resource(pdev, IORESOURCE_MEM, 111 res_idx++); 112 if (!res) { 113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n"); 114 return -ENOMEM; 115 } 116 117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev, 118 res); 119 if (IS_ERR(dsaf_dev->sc_base)) 120 return PTR_ERR(dsaf_dev->sc_base); 121 122 res = platform_get_resource(pdev, IORESOURCE_MEM, 123 res_idx++); 124 if (!res) { 125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n"); 126 return -ENOMEM; 127 } 128 129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev, 130 res); 131 if (IS_ERR(dsaf_dev->sds_base)) 132 return PTR_ERR(dsaf_dev->sds_base); 133 } else { 134 dsaf_dev->sub_ctrl = syscon; 135 } 136 } 137 138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base"); 139 if (!res) { 140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++); 141 if (!res) { 142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n"); 143 return -ENOMEM; 144 } 145 } 146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res); 147 if (IS_ERR(dsaf_dev->ppe_base)) 148 return PTR_ERR(dsaf_dev->ppe_base); 149 dsaf_dev->ppe_paddr = res->start; 150 151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 153 "dsaf-base"); 154 if (!res) { 155 res = platform_get_resource(pdev, IORESOURCE_MEM, 156 res_idx); 157 if (!res) { 158 dev_err(dsaf_dev->dev, 159 "dsaf-base info is needed!\n"); 160 return -ENOMEM; 161 } 162 } 163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res); 164 if (IS_ERR(dsaf_dev->io_base)) 165 return PTR_ERR(dsaf_dev->io_base); 166 } 167 168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num); 169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT || 170 desc_num > HNS_DSAF_MAX_DESC_CNT) { 171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n", 172 desc_num, ret); 173 return -EINVAL; 174 } 175 dsaf_dev->desc_num = desc_num; 176 177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset", 178 &reset_offset); 179 if (ret < 0) { 180 dev_dbg(dsaf_dev->dev, 181 "get reset-field-offset fail, ret=%d!\r\n", ret); 182 } 183 dsaf_dev->reset_offset = reset_offset; 184 185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size); 186 if (ret < 0) { 187 dev_err(dsaf_dev->dev, 188 "get buf-size fail, ret=%d!\r\n", ret); 189 return ret; 190 } 191 dsaf_dev->buf_size = buf_size; 192 193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size); 194 if (dsaf_dev->buf_size_type < 0) { 195 dev_err(dsaf_dev->dev, 196 "buf_size(%d) is wrong!\n", buf_size); 197 return -EINVAL; 198 } 199 200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev); 201 if (!dsaf_dev->misc_op) 202 return -ENOMEM; 203 204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL))) 205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n"); 206 else 207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n"); 208 209 return 0; 210 } 211 212 /** 213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en 214 * @dsaf_id: dsa fabric id 215 */ 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev) 217 { 218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1); 219 } 220 221 /** 222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce 223 * @dsaf_id: dsa fabric id 224 * @hns_dsaf_reg_cnt_clr_ce: config value 225 */ 226 static void 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce) 228 { 229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG, 230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce); 231 } 232 233 /** 234 * hns_ppe_qid_cfg - config ppe qid 235 * @dsaf_id: dsa fabric id 236 * @pppe_qid_cfg: value array 237 */ 238 static void 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg) 240 { 241 u32 i; 242 243 for (i = 0; i < DSAF_COMM_CHN; i++) { 244 dsaf_set_dev_field(dsaf_dev, 245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i, 246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S, 247 qid_cfg); 248 } 249 } 250 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev) 252 { 253 u16 max_q_per_vf, max_vfn; 254 u32 q_id, q_num_per_port; 255 u32 i; 256 257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 258 q_num_per_port = max_vfn * max_q_per_vf; 259 260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) { 261 dsaf_set_dev_field(dsaf_dev, 262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i, 263 0xff, 0, q_id); 264 q_id += q_num_per_port; 265 } 266 } 267 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev) 269 { 270 u16 max_q_per_vf, max_vfn; 271 u32 q_id, q_num_per_port; 272 u32 mac_id; 273 274 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 275 return; 276 277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 278 q_num_per_port = max_vfn * max_q_per_vf; 279 280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) { 281 dsaf_set_dev_field(dsaf_dev, 282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 283 DSAFV2_SERDES_LBK_QID_M, 284 DSAFV2_SERDES_LBK_QID_S, 285 q_id); 286 q_id += q_num_per_port; 287 } 288 } 289 290 /** 291 * hns_dsaf_sw_port_type_cfg - cfg sw type 292 * @dsaf_id: dsa fabric id 293 * @psw_port_type: array 294 */ 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev, 296 enum dsaf_sw_port_type port_type) 297 { 298 u32 i; 299 300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 301 dsaf_set_dev_field(dsaf_dev, 302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i, 303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S, 304 port_type); 305 } 306 } 307 308 /** 309 * hns_dsaf_stp_port_type_cfg - cfg stp type 310 * @dsaf_id: dsa fabric id 311 * @pstp_port_type: array 312 */ 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev, 314 enum dsaf_stp_port_type port_type) 315 { 316 u32 i; 317 318 for (i = 0; i < DSAF_COMM_CHN; i++) { 319 dsaf_set_dev_field(dsaf_dev, 320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i, 321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S, 322 port_type); 323 } 324 } 325 326 #define HNS_DSAF_SBM_NUM(dev) \ 327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM) 328 /** 329 * hns_dsaf_sbm_cfg - config sbm 330 * @dsaf_id: dsa fabric id 331 */ 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev) 333 { 334 u32 o_sbm_cfg; 335 u32 i; 336 337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 338 o_sbm_cfg = dsaf_read_dev(dsaf_dev, 339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i); 340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1); 341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0); 342 dsaf_write_dev(dsaf_dev, 343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg); 344 } 345 } 346 347 /** 348 * hns_dsaf_sbm_cfg_mib_en - config sbm 349 * @dsaf_id: dsa fabric id 350 */ 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev) 352 { 353 u32 sbm_cfg_mib_en; 354 u32 i; 355 u32 reg; 356 u32 read_cnt; 357 358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */ 359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); 362 } 363 364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1); 367 } 368 369 /* waitint for all sbm enable finished */ 370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 371 read_cnt = 0; 372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 373 do { 374 udelay(1); 375 sbm_cfg_mib_en = dsaf_get_dev_bit( 376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S); 377 read_cnt++; 378 } while (sbm_cfg_mib_en == 0 && 379 read_cnt < DSAF_CFG_READ_CNT); 380 381 if (sbm_cfg_mib_en == 0) { 382 dev_err(dsaf_dev->dev, 383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n", 384 dsaf_dev->ae_dev.name, i); 385 return -ENODEV; 386 } 387 } 388 389 return 0; 390 } 391 392 /** 393 * hns_dsaf_sbm_bp_wl_cfg - config sbm 394 * @dsaf_id: dsa fabric id 395 */ 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 397 { 398 u32 o_sbm_bp_cfg; 399 u32 reg; 400 u32 i; 401 402 /* XGE */ 403 for (i = 0; i < DSAF_XGE_NUM; i++) { 404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M, 407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512); 408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M, 409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M, 411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 413 414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M, 417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M, 419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 421 422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104); 426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128); 428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 429 430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 432 dsaf_set_field(o_sbm_bp_cfg, 433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110); 435 dsaf_set_field(o_sbm_bp_cfg, 436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160); 438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 439 440 /* for no enable pfc mode */ 441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 443 dsaf_set_field(o_sbm_bp_cfg, 444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128); 446 dsaf_set_field(o_sbm_bp_cfg, 447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192); 449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 450 } 451 452 /* PPE */ 453 for (i = 0; i < DSAF_COMM_CHN; i++) { 454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10); 458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12); 460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 461 } 462 463 /* RoCEE */ 464 for (i = 0; i < DSAF_COMM_CHN; i++) { 465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2); 469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4); 471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 472 } 473 } 474 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 476 { 477 u32 o_sbm_bp_cfg; 478 u32 reg; 479 u32 i; 480 481 /* XGE */ 482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) { 483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M, 486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256); 487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M, 488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M, 490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 492 493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M, 496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M, 498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 500 501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M, 504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104); 505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M, 506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128); 507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 508 509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 511 dsaf_set_field(o_sbm_bp_cfg, 512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55); 514 dsaf_set_field(o_sbm_bp_cfg, 515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110); 517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 518 519 /* for no enable pfc mode */ 520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 522 dsaf_set_field(o_sbm_bp_cfg, 523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M, 524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128); 525 dsaf_set_field(o_sbm_bp_cfg, 526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M, 527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192); 528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 529 } 530 531 /* PPE */ 532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) { 533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 535 dsaf_set_field(o_sbm_bp_cfg, 536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M, 537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2); 538 dsaf_set_field(o_sbm_bp_cfg, 539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M, 540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3); 541 dsaf_set_field(o_sbm_bp_cfg, 542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M, 543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52); 544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 545 } 546 547 /* RoCEE */ 548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) { 549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 551 dsaf_set_field(o_sbm_bp_cfg, 552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M, 553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2); 554 dsaf_set_field(o_sbm_bp_cfg, 555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M, 556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4); 557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 558 } 559 } 560 561 /** 562 * hns_dsaf_voq_bp_all_thrd_cfg - voq 563 * @dsaf_id: dsa fabric id 564 */ 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev) 566 { 567 u32 voq_bp_all_thrd; 568 u32 i; 569 570 for (i = 0; i < DSAF_VOQ_NUM; i++) { 571 voq_bp_all_thrd = dsaf_read_dev( 572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i); 573 if (i < DSAF_XGE_NUM) { 574 dsaf_set_field(voq_bp_all_thrd, 575 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930); 577 dsaf_set_field(voq_bp_all_thrd, 578 DSAF_VOQ_BP_ALL_UPTHRD_M, 579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950); 580 } else { 581 dsaf_set_field(voq_bp_all_thrd, 582 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220); 584 dsaf_set_field(voq_bp_all_thrd, 585 DSAF_VOQ_BP_ALL_UPTHRD_M, 586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230); 587 } 588 dsaf_write_dev( 589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i, 590 voq_bp_all_thrd); 591 } 592 } 593 594 static void hns_dsaf_tbl_tcam_match_cfg( 595 struct dsaf_device *dsaf_dev, 596 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 597 { 598 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG, 599 ptbl_tcam_data->tbl_tcam_data_low); 600 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG, 601 ptbl_tcam_data->tbl_tcam_data_high); 602 } 603 604 /** 605 * hns_dsaf_tbl_tcam_data_cfg - tbl 606 * @dsaf_id: dsa fabric id 607 * @ptbl_tcam_data: addr 608 */ 609 static void hns_dsaf_tbl_tcam_data_cfg( 610 struct dsaf_device *dsaf_dev, 611 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 612 { 613 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG, 614 ptbl_tcam_data->tbl_tcam_data_low); 615 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG, 616 ptbl_tcam_data->tbl_tcam_data_high); 617 } 618 619 /** 620 * dsaf_tbl_tcam_mcast_cfg - tbl 621 * @dsaf_id: dsa fabric id 622 * @ptbl_tcam_mcast: addr 623 */ 624 static void hns_dsaf_tbl_tcam_mcast_cfg( 625 struct dsaf_device *dsaf_dev, 626 struct dsaf_tbl_tcam_mcast_cfg *mcast) 627 { 628 u32 mcast_cfg4; 629 630 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 631 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S, 632 mcast->tbl_mcast_item_vld); 633 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S, 634 mcast->tbl_mcast_old_en); 635 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M, 636 DSAF_TBL_MCAST_CFG4_VM128_112_S, 637 mcast->tbl_mcast_port_msk[4]); 638 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4); 639 640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 641 mcast->tbl_mcast_port_msk[3]); 642 643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 644 mcast->tbl_mcast_port_msk[2]); 645 646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 647 mcast->tbl_mcast_port_msk[1]); 648 649 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 650 mcast->tbl_mcast_port_msk[0]); 651 } 652 653 /** 654 * hns_dsaf_tbl_tcam_ucast_cfg - tbl 655 * @dsaf_id: dsa fabric id 656 * @ptbl_tcam_ucast: addr 657 */ 658 static void hns_dsaf_tbl_tcam_ucast_cfg( 659 struct dsaf_device *dsaf_dev, 660 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast) 661 { 662 u32 ucast_cfg1; 663 664 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 665 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S, 666 tbl_tcam_ucast->tbl_ucast_mac_discard); 667 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S, 668 tbl_tcam_ucast->tbl_ucast_item_vld); 669 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S, 670 tbl_tcam_ucast->tbl_ucast_old_en); 671 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S, 672 tbl_tcam_ucast->tbl_ucast_dvc); 673 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 674 DSAF_TBL_UCAST_CFG1_OUT_PORT_S, 675 tbl_tcam_ucast->tbl_ucast_out_port); 676 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1); 677 } 678 679 /** 680 * hns_dsaf_tbl_line_cfg - tbl 681 * @dsaf_id: dsa fabric id 682 * @ptbl_lin: addr 683 */ 684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev, 685 struct dsaf_tbl_line_cfg *tbl_lin) 686 { 687 u32 tbl_line; 688 689 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG); 690 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S, 691 tbl_lin->tbl_line_mac_discard); 692 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S, 693 tbl_lin->tbl_line_dvc); 694 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M, 695 DSAF_TBL_LINE_CFG_OUT_PORT_S, 696 tbl_lin->tbl_line_out_port); 697 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line); 698 } 699 700 /** 701 * hns_dsaf_tbl_tcam_mcast_pul - tbl 702 * @dsaf_id: dsa fabric id 703 */ 704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev) 705 { 706 u32 o_tbl_pul; 707 708 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 709 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 710 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 711 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 712 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 713 } 714 715 /** 716 * hns_dsaf_tbl_line_pul - tbl 717 * @dsaf_id: dsa fabric id 718 */ 719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev) 720 { 721 u32 tbl_pul; 722 723 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 724 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1); 725 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 726 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0); 727 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 728 } 729 730 /** 731 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl 732 * @dsaf_id: dsa fabric id 733 */ 734 static void hns_dsaf_tbl_tcam_data_mcast_pul( 735 struct dsaf_device *dsaf_dev) 736 { 737 u32 o_tbl_pul; 738 739 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 743 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 744 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 745 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 746 } 747 748 /** 749 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl 750 * @dsaf_id: dsa fabric id 751 */ 752 static void hns_dsaf_tbl_tcam_data_ucast_pul( 753 struct dsaf_device *dsaf_dev) 754 { 755 u32 o_tbl_pul; 756 757 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1); 760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 761 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 762 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0); 763 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 764 } 765 766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en) 767 { 768 if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev)) 769 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, 770 DSAF_CFG_MIX_MODE_S, !!en); 771 } 772 773 /** 774 * hns_dsaf_tbl_stat_en - tbl 775 * @dsaf_id: dsa fabric id 776 * @ptbl_stat_en: addr 777 */ 778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev) 779 { 780 u32 o_tbl_ctrl; 781 782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG); 783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1); 784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1); 785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1); 786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1); 787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl); 788 } 789 790 /** 791 * hns_dsaf_rocee_bp_en - rocee back press enable 792 * @dsaf_id: dsa fabric id 793 */ 794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev) 795 { 796 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG, 798 DSAF_FC_XGE_TX_PAUSE_S, 1); 799 } 800 801 /* set msk for dsaf exception irq*/ 802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev, 803 u32 chnn_num, u32 mask_set) 804 { 805 dsaf_write_dev(dsaf_dev, 806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set); 807 } 808 809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev, 810 u32 chnn_num, u32 msk_set) 811 { 812 dsaf_write_dev(dsaf_dev, 813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set); 814 } 815 816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev, 817 u32 chnn, u32 msk_set) 818 { 819 dsaf_write_dev(dsaf_dev, 820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set); 821 } 822 823 static void 824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set) 825 { 826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set); 827 } 828 829 /* clr dsaf exception irq*/ 830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev, 831 u32 chnn_num, u32 int_src) 832 { 833 dsaf_write_dev(dsaf_dev, 834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src); 835 } 836 837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev, 838 u32 chnn, u32 int_src) 839 { 840 dsaf_write_dev(dsaf_dev, 841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src); 842 } 843 844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev, 845 u32 chnn, u32 int_src) 846 { 847 dsaf_write_dev(dsaf_dev, 848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src); 849 } 850 851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev, 852 u32 int_src) 853 { 854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src); 855 } 856 857 /** 858 * hns_dsaf_single_line_tbl_cfg - INT 859 * @dsaf_id: dsa fabric id 860 * @address: 861 * @ptbl_line: 862 */ 863 static void hns_dsaf_single_line_tbl_cfg( 864 struct dsaf_device *dsaf_dev, 865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line) 866 { 867 spin_lock_bh(&dsaf_dev->tcam_lock); 868 869 /*Write Addr*/ 870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address); 871 872 /*Write Line*/ 873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line); 874 875 /*Write Plus*/ 876 hns_dsaf_tbl_line_pul(dsaf_dev); 877 878 spin_unlock_bh(&dsaf_dev->tcam_lock); 879 } 880 881 /** 882 * hns_dsaf_tcam_uc_cfg - INT 883 * @dsaf_id: dsa fabric id 884 * @address, 885 * @ptbl_tcam_data, 886 */ 887 static void hns_dsaf_tcam_uc_cfg( 888 struct dsaf_device *dsaf_dev, u32 address, 889 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 891 { 892 spin_lock_bh(&dsaf_dev->tcam_lock); 893 894 /*Write Addr*/ 895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 896 /*Write Tcam Data*/ 897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 898 /*Write Tcam Ucast*/ 899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast); 900 /*Write Plus*/ 901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev); 902 903 spin_unlock_bh(&dsaf_dev->tcam_lock); 904 } 905 906 /** 907 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc 908 * @dsaf_dev: dsa fabric device struct pointer 909 * @address: tcam index 910 * @ptbl_tcam_data: tcam data struct pointer 911 * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1 912 */ 913 static void hns_dsaf_tcam_mc_cfg( 914 struct dsaf_device *dsaf_dev, u32 address, 915 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 916 struct dsaf_tbl_tcam_data *ptbl_tcam_mask, 917 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 918 { 919 spin_lock_bh(&dsaf_dev->tcam_lock); 920 921 /*Write Addr*/ 922 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 923 /*Write Tcam Data*/ 924 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 925 /*Write Tcam Mcast*/ 926 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast); 927 /* Write Match Data */ 928 if (ptbl_tcam_mask) 929 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask); 930 931 /* Write Puls */ 932 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev); 933 934 spin_unlock_bh(&dsaf_dev->tcam_lock); 935 } 936 937 /** 938 * hns_dsaf_tcam_uc_cfg_vague - INT 939 * @dsaf_dev: dsa fabric device struct pointer 940 * @address, 941 * @ptbl_tcam_data, 942 */ 943 static void hns_dsaf_tcam_uc_cfg_vague(struct dsaf_device *dsaf_dev, 944 u32 address, 945 struct dsaf_tbl_tcam_data *tcam_data, 946 struct dsaf_tbl_tcam_data *tcam_mask, 947 struct dsaf_tbl_tcam_ucast_cfg *tcam_uc) 948 { 949 spin_lock_bh(&dsaf_dev->tcam_lock); 950 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 951 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data); 952 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, tcam_uc); 953 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask); 954 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev); 955 956 /*Restore Match Data*/ 957 tcam_mask->tbl_tcam_data_high = 0xffffffff; 958 tcam_mask->tbl_tcam_data_low = 0xffffffff; 959 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask); 960 961 spin_unlock_bh(&dsaf_dev->tcam_lock); 962 } 963 964 /** 965 * hns_dsaf_tcam_mc_cfg_vague - INT 966 * @dsaf_dev: dsa fabric device struct pointer 967 * @address, 968 * @ptbl_tcam_data, 969 * @ptbl_tcam_mask 970 * @ptbl_tcam_mcast 971 */ 972 static void hns_dsaf_tcam_mc_cfg_vague(struct dsaf_device *dsaf_dev, 973 u32 address, 974 struct dsaf_tbl_tcam_data *tcam_data, 975 struct dsaf_tbl_tcam_data *tcam_mask, 976 struct dsaf_tbl_tcam_mcast_cfg *tcam_mc) 977 { 978 spin_lock_bh(&dsaf_dev->tcam_lock); 979 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 980 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data); 981 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, tcam_mc); 982 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask); 983 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev); 984 985 /*Restore Match Data*/ 986 tcam_mask->tbl_tcam_data_high = 0xffffffff; 987 tcam_mask->tbl_tcam_data_low = 0xffffffff; 988 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask); 989 990 spin_unlock_bh(&dsaf_dev->tcam_lock); 991 } 992 993 /** 994 * hns_dsaf_tcam_mc_invld - INT 995 * @dsaf_id: dsa fabric id 996 * @address 997 */ 998 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address) 999 { 1000 spin_lock_bh(&dsaf_dev->tcam_lock); 1001 1002 /*Write Addr*/ 1003 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1004 1005 /*write tcam mcast*/ 1006 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0); 1007 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0); 1008 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0); 1009 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0); 1010 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0); 1011 1012 /*Write Plus*/ 1013 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev); 1014 1015 spin_unlock_bh(&dsaf_dev->tcam_lock); 1016 } 1017 1018 static void 1019 hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr) 1020 { 1021 addr[0] = mac_key->high.bits.mac_0; 1022 addr[1] = mac_key->high.bits.mac_1; 1023 addr[2] = mac_key->high.bits.mac_2; 1024 addr[3] = mac_key->high.bits.mac_3; 1025 addr[4] = mac_key->low.bits.mac_4; 1026 addr[5] = mac_key->low.bits.mac_5; 1027 } 1028 1029 /** 1030 * hns_dsaf_tcam_uc_get - INT 1031 * @dsaf_id: dsa fabric id 1032 * @address 1033 * @ptbl_tcam_data 1034 * @ptbl_tcam_ucast 1035 */ 1036 static void hns_dsaf_tcam_uc_get( 1037 struct dsaf_device *dsaf_dev, u32 address, 1038 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 1039 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 1040 { 1041 u32 tcam_read_data0; 1042 u32 tcam_read_data4; 1043 1044 spin_lock_bh(&dsaf_dev->tcam_lock); 1045 1046 /*Write Addr*/ 1047 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1048 1049 /*read tcam item puls*/ 1050 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 1051 1052 /*read tcam data*/ 1053 ptbl_tcam_data->tbl_tcam_data_high 1054 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 1055 ptbl_tcam_data->tbl_tcam_data_low 1056 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1057 1058 /*read tcam mcast*/ 1059 tcam_read_data0 = dsaf_read_dev(dsaf_dev, 1060 DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1061 tcam_read_data4 = dsaf_read_dev(dsaf_dev, 1062 DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1063 1064 ptbl_tcam_ucast->tbl_ucast_item_vld 1065 = dsaf_get_bit(tcam_read_data4, 1066 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1067 ptbl_tcam_ucast->tbl_ucast_old_en 1068 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1069 ptbl_tcam_ucast->tbl_ucast_mac_discard 1070 = dsaf_get_bit(tcam_read_data0, 1071 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S); 1072 ptbl_tcam_ucast->tbl_ucast_out_port 1073 = dsaf_get_field(tcam_read_data0, 1074 DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 1075 DSAF_TBL_UCAST_CFG1_OUT_PORT_S); 1076 ptbl_tcam_ucast->tbl_ucast_dvc 1077 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S); 1078 1079 spin_unlock_bh(&dsaf_dev->tcam_lock); 1080 } 1081 1082 /** 1083 * hns_dsaf_tcam_mc_get - INT 1084 * @dsaf_id: dsa fabric id 1085 * @address 1086 * @ptbl_tcam_data 1087 * @ptbl_tcam_ucast 1088 */ 1089 static void hns_dsaf_tcam_mc_get( 1090 struct dsaf_device *dsaf_dev, u32 address, 1091 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 1092 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 1093 { 1094 u32 data_tmp; 1095 1096 spin_lock_bh(&dsaf_dev->tcam_lock); 1097 1098 /*Write Addr*/ 1099 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1100 1101 /*read tcam item puls*/ 1102 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 1103 1104 /*read tcam data*/ 1105 ptbl_tcam_data->tbl_tcam_data_high = 1106 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 1107 ptbl_tcam_data->tbl_tcam_data_low = 1108 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1109 1110 /*read tcam mcast*/ 1111 ptbl_tcam_mcast->tbl_mcast_port_msk[0] = 1112 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1113 ptbl_tcam_mcast->tbl_mcast_port_msk[1] = 1114 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 1115 ptbl_tcam_mcast->tbl_mcast_port_msk[2] = 1116 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 1117 ptbl_tcam_mcast->tbl_mcast_port_msk[3] = 1118 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 1119 1120 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1121 ptbl_tcam_mcast->tbl_mcast_item_vld = 1122 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1123 ptbl_tcam_mcast->tbl_mcast_old_en = 1124 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1125 ptbl_tcam_mcast->tbl_mcast_port_msk[4] = 1126 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M, 1127 DSAF_TBL_MCAST_CFG4_VM128_112_S); 1128 1129 spin_unlock_bh(&dsaf_dev->tcam_lock); 1130 } 1131 1132 /** 1133 * hns_dsaf_tbl_line_init - INT 1134 * @dsaf_id: dsa fabric id 1135 */ 1136 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev) 1137 { 1138 u32 i; 1139 /* defaultly set all lineal mac table entry resulting discard */ 1140 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} }; 1141 1142 for (i = 0; i < DSAF_LINE_SUM; i++) 1143 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line); 1144 } 1145 1146 /** 1147 * hns_dsaf_tbl_tcam_init - INT 1148 * @dsaf_id: dsa fabric id 1149 */ 1150 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev) 1151 { 1152 u32 i; 1153 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} }; 1154 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} }; 1155 1156 /*tcam tbl*/ 1157 for (i = 0; i < DSAF_TCAM_SUM; i++) 1158 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast); 1159 } 1160 1161 /** 1162 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg 1163 * @mac_cb: mac contrl block 1164 */ 1165 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev, 1166 int mac_id, int tc_en) 1167 { 1168 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en); 1169 } 1170 1171 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev, 1172 int mac_id, int tx_en, int rx_en) 1173 { 1174 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1175 if (!tx_en || !rx_en) 1176 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n"); 1177 1178 return; 1179 } 1180 1181 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1182 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en); 1183 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1184 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en); 1185 } 1186 1187 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1188 u32 en) 1189 { 1190 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1191 if (!en) { 1192 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n"); 1193 return -EINVAL; 1194 } 1195 } 1196 1197 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1198 DSAF_MAC_PAUSE_RX_EN_B, !!en); 1199 1200 return 0; 1201 } 1202 1203 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1204 u32 *en) 1205 { 1206 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1207 *en = 1; 1208 else 1209 *en = dsaf_get_dev_bit(dsaf_dev, 1210 DSAF_PAUSE_CFG_REG + mac_id * 4, 1211 DSAF_MAC_PAUSE_RX_EN_B); 1212 } 1213 1214 /** 1215 * hns_dsaf_tbl_tcam_init - INT 1216 * @dsaf_id: dsa fabric id 1217 * @dsaf_mode 1218 */ 1219 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev) 1220 { 1221 u32 i; 1222 u32 o_dsaf_cfg; 1223 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 1224 1225 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG); 1226 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en); 1227 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode); 1228 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0); 1229 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0); 1230 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0); 1231 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg); 1232 1233 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1); 1234 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD); 1235 1236 /* set 22 queue per tx ppe engine, only used in switch mode */ 1237 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE); 1238 1239 /* set promisc def queue id */ 1240 hns_dsaf_mix_def_qid_cfg(dsaf_dev); 1241 1242 /* set inner loopback queue id */ 1243 hns_dsaf_inner_qid_cfg(dsaf_dev); 1244 1245 /* in non switch mode, set all port to access mode */ 1246 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN); 1247 1248 /*set dsaf pfc to 0 for parseing rx pause*/ 1249 for (i = 0; i < DSAF_COMM_CHN; i++) { 1250 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0); 1251 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1); 1252 } 1253 1254 /*msk and clr exception irqs */ 1255 for (i = 0; i < DSAF_COMM_CHN; i++) { 1256 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful); 1257 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful); 1258 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful); 1259 1260 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful); 1261 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful); 1262 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful); 1263 } 1264 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful); 1265 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful); 1266 } 1267 1268 /** 1269 * hns_dsaf_inode_init - INT 1270 * @dsaf_id: dsa fabric id 1271 */ 1272 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev) 1273 { 1274 u32 reg; 1275 u32 tc_cfg; 1276 u32 i; 1277 1278 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE) 1279 tc_cfg = HNS_DSAF_I4TC_CFG; 1280 else 1281 tc_cfg = HNS_DSAF_I8TC_CFG; 1282 1283 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1284 for (i = 0; i < DSAF_INODE_NUM; i++) { 1285 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1286 dsaf_set_dev_field(dsaf_dev, reg, 1287 DSAF_INODE_IN_PORT_NUM_M, 1288 DSAF_INODE_IN_PORT_NUM_S, 1289 i % DSAF_XGE_NUM); 1290 } 1291 } else { 1292 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) { 1293 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1294 dsaf_set_dev_field(dsaf_dev, reg, 1295 DSAF_INODE_IN_PORT_NUM_M, 1296 DSAF_INODE_IN_PORT_NUM_S, 0); 1297 dsaf_set_dev_field(dsaf_dev, reg, 1298 DSAFV2_INODE_IN_PORT1_NUM_M, 1299 DSAFV2_INODE_IN_PORT1_NUM_S, 1); 1300 dsaf_set_dev_field(dsaf_dev, reg, 1301 DSAFV2_INODE_IN_PORT2_NUM_M, 1302 DSAFV2_INODE_IN_PORT2_NUM_S, 2); 1303 dsaf_set_dev_field(dsaf_dev, reg, 1304 DSAFV2_INODE_IN_PORT3_NUM_M, 1305 DSAFV2_INODE_IN_PORT3_NUM_S, 3); 1306 dsaf_set_dev_field(dsaf_dev, reg, 1307 DSAFV2_INODE_IN_PORT4_NUM_M, 1308 DSAFV2_INODE_IN_PORT4_NUM_S, 4); 1309 dsaf_set_dev_field(dsaf_dev, reg, 1310 DSAFV2_INODE_IN_PORT5_NUM_M, 1311 DSAFV2_INODE_IN_PORT5_NUM_S, 5); 1312 } 1313 } 1314 for (i = 0; i < DSAF_INODE_NUM; i++) { 1315 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; 1316 dsaf_write_dev(dsaf_dev, reg, tc_cfg); 1317 } 1318 } 1319 1320 /** 1321 * hns_dsaf_sbm_init - INT 1322 * @dsaf_id: dsa fabric id 1323 */ 1324 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev) 1325 { 1326 u32 flag; 1327 u32 finish_msk; 1328 u32 cnt = 0; 1329 int ret; 1330 1331 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1332 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev); 1333 finish_msk = DSAF_SRAM_INIT_OVER_M; 1334 } else { 1335 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev); 1336 finish_msk = DSAFV2_SRAM_INIT_OVER_M; 1337 } 1338 1339 /* enable sbm chanel, disable sbm chanel shcut function*/ 1340 hns_dsaf_sbm_cfg(dsaf_dev); 1341 1342 /* enable sbm mib */ 1343 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev); 1344 if (ret) { 1345 dev_err(dsaf_dev->dev, 1346 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n", 1347 dsaf_dev->ae_dev.name, ret); 1348 return ret; 1349 } 1350 1351 /* enable sbm initial link sram */ 1352 hns_dsaf_sbm_link_sram_init_en(dsaf_dev); 1353 1354 do { 1355 usleep_range(200, 210);/*udelay(200);*/ 1356 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG, 1357 finish_msk, DSAF_SRAM_INIT_OVER_S); 1358 cnt++; 1359 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) && 1360 cnt < DSAF_CFG_READ_CNT); 1361 1362 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) { 1363 dev_err(dsaf_dev->dev, 1364 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n", 1365 dsaf_dev->ae_dev.name, flag, cnt); 1366 return -ENODEV; 1367 } 1368 1369 hns_dsaf_rocee_bp_en(dsaf_dev); 1370 1371 return 0; 1372 } 1373 1374 /** 1375 * hns_dsaf_tbl_init - INT 1376 * @dsaf_id: dsa fabric id 1377 */ 1378 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev) 1379 { 1380 hns_dsaf_tbl_stat_en(dsaf_dev); 1381 1382 hns_dsaf_tbl_tcam_init(dsaf_dev); 1383 hns_dsaf_tbl_line_init(dsaf_dev); 1384 } 1385 1386 /** 1387 * hns_dsaf_voq_init - INT 1388 * @dsaf_id: dsa fabric id 1389 */ 1390 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev) 1391 { 1392 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev); 1393 } 1394 1395 /** 1396 * hns_dsaf_init_hw - init dsa fabric hardware 1397 * @dsaf_dev: dsa fabric device struct pointer 1398 */ 1399 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev) 1400 { 1401 int ret; 1402 1403 dev_dbg(dsaf_dev->dev, 1404 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name); 1405 1406 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1407 mdelay(10); 1408 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1); 1409 1410 hns_dsaf_comm_init(dsaf_dev); 1411 1412 /*init XBAR_INODE*/ 1413 hns_dsaf_inode_init(dsaf_dev); 1414 1415 /*init SBM*/ 1416 ret = hns_dsaf_sbm_init(dsaf_dev); 1417 if (ret) 1418 return ret; 1419 1420 /*init TBL*/ 1421 hns_dsaf_tbl_init(dsaf_dev); 1422 1423 /*init VOQ*/ 1424 hns_dsaf_voq_init(dsaf_dev); 1425 1426 return 0; 1427 } 1428 1429 /** 1430 * hns_dsaf_remove_hw - uninit dsa fabric hardware 1431 * @dsaf_dev: dsa fabric device struct pointer 1432 */ 1433 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev) 1434 { 1435 /*reset*/ 1436 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1437 } 1438 1439 /** 1440 * hns_dsaf_init - init dsa fabric 1441 * @dsaf_dev: dsa fabric device struct pointer 1442 * retuen 0 - success , negative --fail 1443 */ 1444 static int hns_dsaf_init(struct dsaf_device *dsaf_dev) 1445 { 1446 struct dsaf_drv_priv *priv = 1447 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1448 u32 i; 1449 int ret; 1450 1451 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 1452 return 0; 1453 1454 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1455 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM; 1456 else 1457 dsaf_dev->tcam_max_num = 1458 DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; 1459 1460 spin_lock_init(&dsaf_dev->tcam_lock); 1461 ret = hns_dsaf_init_hw(dsaf_dev); 1462 if (ret) 1463 return ret; 1464 1465 /* malloc mem for tcam mac key(vlan+mac) */ 1466 priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM, 1467 sizeof(*priv->soft_mac_tbl))); 1468 if (!priv->soft_mac_tbl) { 1469 ret = -ENOMEM; 1470 goto remove_hw; 1471 } 1472 1473 /*all entry invall */ 1474 for (i = 0; i < DSAF_TCAM_SUM; i++) 1475 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX; 1476 1477 return 0; 1478 1479 remove_hw: 1480 hns_dsaf_remove_hw(dsaf_dev); 1481 return ret; 1482 } 1483 1484 /** 1485 * hns_dsaf_free - free dsa fabric 1486 * @dsaf_dev: dsa fabric device struct pointer 1487 */ 1488 static void hns_dsaf_free(struct dsaf_device *dsaf_dev) 1489 { 1490 struct dsaf_drv_priv *priv = 1491 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1492 1493 hns_dsaf_remove_hw(dsaf_dev); 1494 1495 /* free all mac mem */ 1496 vfree(priv->soft_mac_tbl); 1497 priv->soft_mac_tbl = NULL; 1498 } 1499 1500 /** 1501 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry 1502 * @dsaf_dev: dsa fabric device struct pointer 1503 * @mac_key: mac entry struct pointer 1504 */ 1505 static u16 hns_dsaf_find_soft_mac_entry( 1506 struct dsaf_device *dsaf_dev, 1507 struct dsaf_drv_tbl_tcam_key *mac_key) 1508 { 1509 struct dsaf_drv_priv *priv = 1510 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1511 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1512 u32 i; 1513 1514 soft_mac_entry = priv->soft_mac_tbl; 1515 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { 1516 /* invall tab entry */ 1517 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) && 1518 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) && 1519 (soft_mac_entry->tcam_key.low.val == mac_key->low.val)) 1520 /* return find result --soft index */ 1521 return soft_mac_entry->index; 1522 1523 soft_mac_entry++; 1524 } 1525 return DSAF_INVALID_ENTRY_IDX; 1526 } 1527 1528 /** 1529 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry 1530 * @dsaf_dev: dsa fabric device struct pointer 1531 */ 1532 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev) 1533 { 1534 struct dsaf_drv_priv *priv = 1535 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1536 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1537 u32 i; 1538 1539 soft_mac_entry = priv->soft_mac_tbl; 1540 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { 1541 /* inv all entry */ 1542 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX) 1543 /* return find result --soft index */ 1544 return i; 1545 1546 soft_mac_entry++; 1547 } 1548 return DSAF_INVALID_ENTRY_IDX; 1549 } 1550 1551 /** 1552 * hns_dsaf_find_empty_mac_entry_reverse 1553 * search dsa fabric soft empty-entry from the end 1554 * @dsaf_dev: dsa fabric device struct pointer 1555 */ 1556 static u16 hns_dsaf_find_empty_mac_entry_reverse(struct dsaf_device *dsaf_dev) 1557 { 1558 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1559 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1560 int i; 1561 1562 soft_mac_entry = priv->soft_mac_tbl + (DSAF_TCAM_SUM - 1); 1563 for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) { 1564 /* search all entry from end to start.*/ 1565 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX) 1566 return i; 1567 soft_mac_entry--; 1568 } 1569 return DSAF_INVALID_ENTRY_IDX; 1570 } 1571 1572 /** 1573 * hns_dsaf_set_mac_key - set mac key 1574 * @dsaf_dev: dsa fabric device struct pointer 1575 * @mac_key: tcam key pointer 1576 * @vlan_id: vlan id 1577 * @in_port_num: input port num 1578 * @addr: mac addr 1579 */ 1580 static void hns_dsaf_set_mac_key( 1581 struct dsaf_device *dsaf_dev, 1582 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num, 1583 u8 *addr) 1584 { 1585 u8 port; 1586 1587 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE) 1588 /*DSAF mode : in port id fixed 0*/ 1589 port = 0; 1590 else 1591 /*non-dsaf mode*/ 1592 port = in_port_num; 1593 1594 mac_key->high.bits.mac_0 = addr[0]; 1595 mac_key->high.bits.mac_1 = addr[1]; 1596 mac_key->high.bits.mac_2 = addr[2]; 1597 mac_key->high.bits.mac_3 = addr[3]; 1598 mac_key->low.bits.mac_4 = addr[4]; 1599 mac_key->low.bits.mac_5 = addr[5]; 1600 mac_key->low.bits.port_vlan = 0; 1601 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M, 1602 DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id); 1603 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M, 1604 DSAF_TBL_TCAM_KEY_PORT_S, port); 1605 1606 mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan); 1607 } 1608 1609 /** 1610 * hns_dsaf_set_mac_uc_entry - set mac uc-entry 1611 * @dsaf_dev: dsa fabric device struct pointer 1612 * @mac_entry: uc-mac entry 1613 */ 1614 int hns_dsaf_set_mac_uc_entry( 1615 struct dsaf_device *dsaf_dev, 1616 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1617 { 1618 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1619 struct dsaf_drv_tbl_tcam_key mac_key; 1620 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1621 struct dsaf_drv_priv *priv = 1622 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1623 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1624 struct dsaf_tbl_tcam_data tcam_data; 1625 1626 /* mac addr check */ 1627 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1628 MAC_IS_BROADCAST(mac_entry->addr) || 1629 MAC_IS_MULTICAST(mac_entry->addr)) { 1630 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n", 1631 dsaf_dev->ae_dev.name, mac_entry->addr); 1632 return -EINVAL; 1633 } 1634 1635 /* config key */ 1636 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1637 mac_entry->in_port_num, mac_entry->addr); 1638 1639 /* entry ie exist? */ 1640 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1641 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1642 /*if has not inv entry,find a empty entry */ 1643 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1644 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1645 /* has not empty,return error */ 1646 dev_err(dsaf_dev->dev, 1647 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1648 dsaf_dev->ae_dev.name, 1649 mac_key.high.val, mac_key.low.val); 1650 return -EINVAL; 1651 } 1652 } 1653 1654 dev_dbg(dsaf_dev->dev, 1655 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1656 dsaf_dev->ae_dev.name, mac_key.high.val, 1657 mac_key.low.val, entry_index); 1658 1659 /* config hardware entry */ 1660 mac_data.tbl_ucast_item_vld = 1; 1661 mac_data.tbl_ucast_mac_discard = 0; 1662 mac_data.tbl_ucast_old_en = 0; 1663 /* default config dvc to 0 */ 1664 mac_data.tbl_ucast_dvc = 0; 1665 mac_data.tbl_ucast_out_port = mac_entry->port_num; 1666 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 1667 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 1668 1669 hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data); 1670 1671 /* config software entry */ 1672 soft_mac_entry += entry_index; 1673 soft_mac_entry->index = entry_index; 1674 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1675 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1676 1677 return 0; 1678 } 1679 1680 int hns_dsaf_rm_mac_addr( 1681 struct dsaf_device *dsaf_dev, 1682 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1683 { 1684 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1685 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1686 struct dsaf_drv_tbl_tcam_key mac_key; 1687 1688 /* mac addr check */ 1689 if (!is_valid_ether_addr(mac_entry->addr)) { 1690 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n", 1691 dsaf_dev->ae_dev.name, mac_entry->addr); 1692 return -EINVAL; 1693 } 1694 1695 /* config key */ 1696 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1697 mac_entry->in_port_num, mac_entry->addr); 1698 1699 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1700 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1701 /* can not find the tcam entry, return 0 */ 1702 dev_info(dsaf_dev->dev, 1703 "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n", 1704 dsaf_dev->ae_dev.name, 1705 mac_key.high.val, mac_key.low.val); 1706 return 0; 1707 } 1708 1709 dev_dbg(dsaf_dev->dev, 1710 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n", 1711 dsaf_dev->ae_dev.name, mac_key.high.val, 1712 mac_key.low.val, entry_index); 1713 1714 hns_dsaf_tcam_uc_get( 1715 dsaf_dev, entry_index, 1716 (struct dsaf_tbl_tcam_data *)&mac_key, 1717 &mac_data); 1718 1719 /* unicast entry not used locally should not clear */ 1720 if (mac_entry->port_num != mac_data.tbl_ucast_out_port) 1721 return -EFAULT; 1722 1723 return hns_dsaf_del_mac_entry(dsaf_dev, 1724 mac_entry->in_vlan_id, 1725 mac_entry->in_port_num, 1726 mac_entry->addr); 1727 } 1728 1729 static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev, 1730 u8 port_num, u8 *mask, u8 *addr) 1731 { 1732 if (MAC_IS_BROADCAST(addr)) 1733 memset(mask, 0xff, ETH_ALEN); 1734 else 1735 memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN); 1736 } 1737 1738 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src) 1739 { 1740 u16 *a = (u16 *)dst; 1741 const u16 *b = (const u16 *)src; 1742 1743 a[0] &= b[0]; 1744 a[1] &= b[1]; 1745 a[2] &= b[2]; 1746 } 1747 1748 /** 1749 * hns_dsaf_add_mac_mc_port - add mac mc-port 1750 * @dsaf_dev: dsa fabric device struct pointer 1751 * @mac_entry: mc-mac entry 1752 */ 1753 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 1754 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1755 { 1756 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1757 struct dsaf_drv_tbl_tcam_key mac_key; 1758 struct dsaf_drv_tbl_tcam_key mask_key; 1759 struct dsaf_tbl_tcam_data *pmask_key = NULL; 1760 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1761 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1762 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1763 struct dsaf_tbl_tcam_data tcam_data; 1764 u8 mc_addr[ETH_ALEN]; 1765 int mskid; 1766 1767 /*chechk mac addr */ 1768 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1769 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n", 1770 mac_entry->addr); 1771 return -EINVAL; 1772 } 1773 1774 ether_addr_copy(mc_addr, mac_entry->addr); 1775 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1776 u8 mc_mask[ETH_ALEN]; 1777 1778 /* prepare for key data setting */ 1779 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num, 1780 mc_mask, mac_entry->addr); 1781 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask); 1782 1783 /* config key mask */ 1784 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 1785 0x0, 1786 0xff, 1787 mc_mask); 1788 1789 mask_key.high.val = le32_to_cpu(mask_key.high.val); 1790 mask_key.low.val = le32_to_cpu(mask_key.low.val); 1791 1792 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key); 1793 } 1794 1795 /*config key */ 1796 hns_dsaf_set_mac_key( 1797 dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1798 mac_entry->in_port_num, mc_addr); 1799 1800 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg)); 1801 1802 /* check if the tcam is exist */ 1803 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1804 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1805 /*if hasnot , find a empty*/ 1806 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1807 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1808 /*if hasnot empty, error*/ 1809 dev_err(dsaf_dev->dev, 1810 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1811 dsaf_dev->ae_dev.name, mac_key.high.val, 1812 mac_key.low.val); 1813 return -EINVAL; 1814 } 1815 } else { 1816 /* if exist, add in */ 1817 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, 1818 &mac_data); 1819 } 1820 1821 /* config hardware entry */ 1822 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1823 mskid = mac_entry->port_num; 1824 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1825 mskid = mac_entry->port_num - 1826 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1827 } else { 1828 dev_err(dsaf_dev->dev, 1829 "%s,pnum(%d)error,key(%#x:%#x)\n", 1830 dsaf_dev->ae_dev.name, mac_entry->port_num, 1831 mac_key.high.val, mac_key.low.val); 1832 return -EINVAL; 1833 } 1834 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1); 1835 mac_data.tbl_mcast_old_en = 0; 1836 mac_data.tbl_mcast_item_vld = 1; 1837 1838 dev_dbg(dsaf_dev->dev, 1839 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1840 dsaf_dev->ae_dev.name, mac_key.high.val, 1841 mac_key.low.val, entry_index); 1842 1843 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 1844 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 1845 1846 /* config mc entry with mask */ 1847 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data, 1848 pmask_key, &mac_data); 1849 1850 /*config software entry */ 1851 soft_mac_entry += entry_index; 1852 soft_mac_entry->index = entry_index; 1853 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1854 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1855 1856 return 0; 1857 } 1858 1859 /** 1860 * hns_dsaf_del_mac_entry - del mac mc-port 1861 * @dsaf_dev: dsa fabric device struct pointer 1862 * @vlan_id: vlian id 1863 * @in_port_num: input port num 1864 * @addr : mac addr 1865 */ 1866 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 1867 u8 in_port_num, u8 *addr) 1868 { 1869 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1870 struct dsaf_drv_tbl_tcam_key mac_key; 1871 struct dsaf_drv_priv *priv = 1872 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1873 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1874 1875 /*check mac addr */ 1876 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) { 1877 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n", 1878 addr); 1879 return -EINVAL; 1880 } 1881 1882 /*config key */ 1883 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr); 1884 1885 /*exist ?*/ 1886 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1887 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1888 /*not exist, error */ 1889 dev_err(dsaf_dev->dev, 1890 "del_mac_entry failed, %s Mac key(%#x:%#x)\n", 1891 dsaf_dev->ae_dev.name, 1892 mac_key.high.val, mac_key.low.val); 1893 return -EINVAL; 1894 } 1895 dev_dbg(dsaf_dev->dev, 1896 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1897 dsaf_dev->ae_dev.name, mac_key.high.val, 1898 mac_key.low.val, entry_index); 1899 1900 /*do del opt*/ 1901 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1902 1903 /*del soft emtry */ 1904 soft_mac_entry += entry_index; 1905 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1906 1907 return 0; 1908 } 1909 1910 /** 1911 * hns_dsaf_del_mac_mc_port - del mac mc- port 1912 * @dsaf_dev: dsa fabric device struct pointer 1913 * @mac_entry: mac entry 1914 */ 1915 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 1916 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1917 { 1918 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1919 struct dsaf_drv_tbl_tcam_key mac_key; 1920 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1921 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1922 u16 vlan_id; 1923 u8 in_port_num; 1924 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1925 struct dsaf_tbl_tcam_data tcam_data; 1926 int mskid; 1927 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0}; 1928 struct dsaf_drv_tbl_tcam_key mask_key; 1929 struct dsaf_tbl_tcam_data *pmask_key = NULL; 1930 u8 mc_addr[ETH_ALEN]; 1931 1932 if (!(void *)mac_entry) { 1933 dev_err(dsaf_dev->dev, 1934 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n"); 1935 return -EINVAL; 1936 } 1937 1938 /*check mac addr */ 1939 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1940 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n", 1941 mac_entry->addr); 1942 return -EINVAL; 1943 } 1944 1945 /* always mask vlan_id field */ 1946 ether_addr_copy(mc_addr, mac_entry->addr); 1947 1948 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1949 u8 mc_mask[ETH_ALEN]; 1950 1951 /* prepare for key data setting */ 1952 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num, 1953 mc_mask, mac_entry->addr); 1954 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask); 1955 1956 /* config key mask */ 1957 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask); 1958 1959 mask_key.high.val = le32_to_cpu(mask_key.high.val); 1960 mask_key.low.val = le32_to_cpu(mask_key.low.val); 1961 1962 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key); 1963 } 1964 1965 /* get key info */ 1966 vlan_id = mac_entry->in_vlan_id; 1967 in_port_num = mac_entry->in_port_num; 1968 1969 /* config key */ 1970 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr); 1971 1972 /* check if the tcam entry is exist */ 1973 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1974 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1975 /*find none */ 1976 dev_err(dsaf_dev->dev, 1977 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n", 1978 dsaf_dev->ae_dev.name, 1979 mac_key.high.val, mac_key.low.val); 1980 return -EINVAL; 1981 } 1982 1983 dev_dbg(dsaf_dev->dev, 1984 "del_mac_mc_port, %s key(%#x:%#x) index%d\n", 1985 dsaf_dev->ae_dev.name, mac_key.high.val, 1986 mac_key.low.val, entry_index); 1987 1988 /* read entry */ 1989 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data); 1990 1991 /*del the port*/ 1992 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1993 mskid = mac_entry->port_num; 1994 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1995 mskid = mac_entry->port_num - 1996 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1997 } else { 1998 dev_err(dsaf_dev->dev, 1999 "%s,pnum(%d)error,key(%#x:%#x)\n", 2000 dsaf_dev->ae_dev.name, mac_entry->port_num, 2001 mac_key.high.val, mac_key.low.val); 2002 return -EINVAL; 2003 } 2004 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0); 2005 2006 /*check non port, do del entry */ 2007 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 2008 sizeof(mac_data.tbl_mcast_port_msk))) { 2009 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 2010 2011 /* del soft entry */ 2012 soft_mac_entry += entry_index; 2013 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 2014 } else { /* not zero, just del port, update */ 2015 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 2016 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 2017 2018 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, 2019 &tcam_data, 2020 pmask_key, &mac_data); 2021 } 2022 2023 return 0; 2024 } 2025 2026 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id, 2027 u8 port_num) 2028 { 2029 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 2030 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 2031 struct dsaf_tbl_tcam_mcast_cfg mac_data; 2032 int ret = 0, i; 2033 2034 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 2035 return 0; 2036 2037 for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) { 2038 u8 addr[ETH_ALEN]; 2039 u8 port; 2040 2041 soft_mac_entry = priv->soft_mac_tbl + i; 2042 2043 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr); 2044 port = dsaf_get_field( 2045 soft_mac_entry->tcam_key.low.bits.port_vlan, 2046 DSAF_TBL_TCAM_KEY_PORT_M, 2047 DSAF_TBL_TCAM_KEY_PORT_S); 2048 /* check valid tcam mc entry */ 2049 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX && 2050 port == mac_id && 2051 is_multicast_ether_addr(addr) && 2052 !is_broadcast_ether_addr(addr)) { 2053 const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0}; 2054 struct dsaf_drv_mac_single_dest_entry mac_entry; 2055 2056 /* disable receiving of this multicast address for 2057 * the VF. 2058 */ 2059 ether_addr_copy(mac_entry.addr, addr); 2060 mac_entry.in_vlan_id = dsaf_get_field( 2061 soft_mac_entry->tcam_key.low.bits.port_vlan, 2062 DSAF_TBL_TCAM_KEY_VLAN_M, 2063 DSAF_TBL_TCAM_KEY_VLAN_S); 2064 mac_entry.in_port_num = mac_id; 2065 mac_entry.port_num = port_num; 2066 if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) { 2067 ret = -EINVAL; 2068 continue; 2069 } 2070 2071 /* disable receiving of this multicast address for 2072 * the mac port if all VF are disable 2073 */ 2074 hns_dsaf_tcam_mc_get(dsaf_dev, i, 2075 (struct dsaf_tbl_tcam_data *) 2076 (&soft_mac_entry->tcam_key), 2077 &mac_data); 2078 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32], 2079 mac_id % 32, 0); 2080 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 2081 sizeof(u32) * DSAF_PORT_MSK_NUM)) { 2082 mac_entry.port_num = mac_id; 2083 if (hns_dsaf_del_mac_mc_port(dsaf_dev, 2084 &mac_entry)) { 2085 ret = -EINVAL; 2086 continue; 2087 } 2088 } 2089 } 2090 } 2091 2092 return ret; 2093 } 2094 2095 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev, 2096 size_t sizeof_priv) 2097 { 2098 struct dsaf_device *dsaf_dev; 2099 2100 dsaf_dev = devm_kzalloc(dev, 2101 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL); 2102 if (unlikely(!dsaf_dev)) { 2103 dsaf_dev = ERR_PTR(-ENOMEM); 2104 } else { 2105 dsaf_dev->dev = dev; 2106 dev_set_drvdata(dev, dsaf_dev); 2107 } 2108 2109 return dsaf_dev; 2110 } 2111 2112 /** 2113 * hns_dsaf_free_dev - free dev mem 2114 * @dev: struct device pointer 2115 */ 2116 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev) 2117 { 2118 (void)dev_set_drvdata(dsaf_dev->dev, NULL); 2119 } 2120 2121 /** 2122 * dsaf_pfc_unit_cnt - set pfc unit count 2123 * @dsaf_id: dsa fabric id 2124 * @pport_rate: value array 2125 * @pdsaf_pfc_unit_cnt: value array 2126 */ 2127 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id, 2128 enum dsaf_port_rate_mode rate) 2129 { 2130 u32 unit_cnt; 2131 2132 switch (rate) { 2133 case DSAF_PORT_RATE_10000: 2134 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2135 break; 2136 case DSAF_PORT_RATE_1000: 2137 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2138 break; 2139 case DSAF_PORT_RATE_2500: 2140 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2141 break; 2142 default: 2143 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2144 } 2145 2146 dsaf_set_dev_field(dsaf_dev, 2147 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id), 2148 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S, 2149 unit_cnt); 2150 } 2151 2152 /** 2153 * dsaf_port_work_rate_cfg - fifo 2154 * @dsaf_id: dsa fabric id 2155 * @xge_ge_work_mode 2156 */ 2157 static void 2158 hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id, 2159 enum dsaf_port_rate_mode rate_mode) 2160 { 2161 u32 port_work_mode; 2162 2163 port_work_mode = dsaf_read_dev( 2164 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id); 2165 2166 if (rate_mode == DSAF_PORT_RATE_10000) 2167 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1); 2168 else 2169 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0); 2170 2171 dsaf_write_dev(dsaf_dev, 2172 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id, 2173 port_work_mode); 2174 2175 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode); 2176 } 2177 2178 /** 2179 * hns_dsaf_fix_mac_mode - dsaf modify mac mode 2180 * @mac_cb: mac contrl block 2181 */ 2182 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb) 2183 { 2184 enum dsaf_port_rate_mode mode; 2185 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev; 2186 int mac_id = mac_cb->mac_id; 2187 2188 if (mac_cb->mac_type != HNAE_PORT_SERVICE) 2189 return; 2190 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII) 2191 mode = DSAF_PORT_RATE_10000; 2192 else 2193 mode = DSAF_PORT_RATE_1000; 2194 2195 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode); 2196 } 2197 2198 static u32 hns_dsaf_get_inode_prio_reg(int index) 2199 { 2200 int base_index, offset; 2201 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG; 2202 2203 base_index = (index + 1) / DSAF_REG_PER_ZONE; 2204 offset = (index + 1) % DSAF_REG_PER_ZONE; 2205 2206 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index + 2207 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset; 2208 } 2209 2210 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num) 2211 { 2212 struct dsaf_hw_stats *hw_stats 2213 = &dsaf_dev->hw_stats[node_num]; 2214 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2215 int i; 2216 u32 reg_tmp; 2217 2218 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev, 2219 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2220 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev, 2221 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num); 2222 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev, 2223 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num); 2224 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev, 2225 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num); 2226 2227 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2228 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2229 hw_stats->rx_pause_frame += 2230 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num); 2231 2232 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev, 2233 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num); 2234 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev, 2235 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num); 2236 hw_stats->crc_false += dsaf_read_dev(dsaf_dev, 2237 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2238 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev, 2239 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2240 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev, 2241 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2242 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev, 2243 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2244 2245 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev, 2246 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num); 2247 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev, 2248 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num); 2249 2250 /* pfc pause frame statistics stored in dsaf inode*/ 2251 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) { 2252 for (i = 0; i < DSAF_PRIO_NR; i++) { 2253 reg_tmp = hns_dsaf_get_inode_prio_reg(i); 2254 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev, 2255 reg_tmp + 0x4 * (u64)node_num); 2256 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev, 2257 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG + 2258 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i + 2259 0xF0 * (u64)node_num); 2260 } 2261 } 2262 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev, 2263 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num); 2264 } 2265 2266 /** 2267 *hns_dsaf_get_regs - dump dsaf regs 2268 *@dsaf_dev: dsaf device 2269 *@data:data for value of regs 2270 */ 2271 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data) 2272 { 2273 u32 i = 0; 2274 u32 j; 2275 u32 *p = data; 2276 u32 reg_tmp; 2277 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2278 2279 /* dsaf common registers */ 2280 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG); 2281 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG); 2282 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG); 2283 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG); 2284 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG); 2285 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG); 2286 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG); 2287 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG); 2288 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG); 2289 2290 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4); 2291 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4); 2292 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2293 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2294 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2295 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2296 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4); 2297 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4); 2298 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2299 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4); 2300 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4); 2301 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2302 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4); 2303 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4); 2304 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4); 2305 2306 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2307 p[24 + i] = dsaf_read_dev(ddev, 2308 DSAF_SW_PORT_TYPE_0_REG + i * 4); 2309 2310 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4); 2311 2312 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2313 p[33 + i] = dsaf_read_dev(ddev, 2314 DSAF_PORT_DEF_VLAN_0_REG + i * 4); 2315 2316 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) 2317 p[41 + i] = dsaf_read_dev(ddev, 2318 DSAF_VM_DEF_VLAN_0_REG + i * 4); 2319 2320 /* dsaf inode registers */ 2321 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG); 2322 2323 p[171] = dsaf_read_dev(ddev, 2324 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80); 2325 2326 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2327 j = i * DSAF_COMM_CHN + port; 2328 p[172 + i] = dsaf_read_dev(ddev, 2329 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80); 2330 p[175 + i] = dsaf_read_dev(ddev, 2331 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80); 2332 p[178 + i] = dsaf_read_dev(ddev, 2333 DSAF_INODE_BP_STATUS_0_REG + j * 0x80); 2334 p[181 + i] = dsaf_read_dev(ddev, 2335 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80); 2336 p[184 + i] = dsaf_read_dev(ddev, 2337 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80); 2338 p[187 + i] = dsaf_read_dev(ddev, 2339 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80); 2340 p[190 + i] = dsaf_read_dev(ddev, 2341 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80); 2342 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2343 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2344 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80); 2345 p[196 + i] = dsaf_read_dev(ddev, 2346 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80); 2347 p[199 + i] = dsaf_read_dev(ddev, 2348 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80); 2349 p[202 + i] = dsaf_read_dev(ddev, 2350 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80); 2351 p[205 + i] = dsaf_read_dev(ddev, 2352 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80); 2353 p[208 + i] = dsaf_read_dev(ddev, 2354 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80); 2355 p[211 + i] = dsaf_read_dev(ddev, 2356 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80); 2357 p[214 + i] = dsaf_read_dev(ddev, 2358 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80); 2359 p[217 + i] = dsaf_read_dev(ddev, 2360 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4); 2361 p[220 + i] = dsaf_read_dev(ddev, 2362 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4); 2363 p[223 + i] = dsaf_read_dev(ddev, 2364 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4); 2365 p[226 + i] = dsaf_read_dev(ddev, 2366 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4); 2367 } 2368 2369 p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4); 2370 2371 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2372 j = i * DSAF_COMM_CHN + port; 2373 p[230 + i] = dsaf_read_dev(ddev, 2374 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4); 2375 } 2376 2377 p[233] = dsaf_read_dev(ddev, 2378 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80); 2379 2380 /* dsaf inode registers */ 2381 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) { 2382 j = i * DSAF_COMM_CHN + port; 2383 p[234 + i] = dsaf_read_dev(ddev, 2384 DSAF_SBM_CFG_REG_0_REG + j * 0x80); 2385 p[237 + i] = dsaf_read_dev(ddev, 2386 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80); 2387 p[240 + i] = dsaf_read_dev(ddev, 2388 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80); 2389 p[243 + i] = dsaf_read_dev(ddev, 2390 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80); 2391 p[246 + i] = dsaf_read_dev(ddev, 2392 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80); 2393 p[249 + i] = dsaf_read_dev(ddev, 2394 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80); 2395 p[252 + i] = dsaf_read_dev(ddev, 2396 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80); 2397 p[255 + i] = dsaf_read_dev(ddev, 2398 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80); 2399 p[258 + i] = dsaf_read_dev(ddev, 2400 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80); 2401 p[261 + i] = dsaf_read_dev(ddev, 2402 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80); 2403 p[264 + i] = dsaf_read_dev(ddev, 2404 DSAF_SBM_INER_ST_0_REG + j * 0x80); 2405 p[267 + i] = dsaf_read_dev(ddev, 2406 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80); 2407 p[270 + i] = dsaf_read_dev(ddev, 2408 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80); 2409 p[273 + i] = dsaf_read_dev(ddev, 2410 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80); 2411 p[276 + i] = dsaf_read_dev(ddev, 2412 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80); 2413 p[279 + i] = dsaf_read_dev(ddev, 2414 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80); 2415 p[282 + i] = dsaf_read_dev(ddev, 2416 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80); 2417 p[285 + i] = dsaf_read_dev(ddev, 2418 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80); 2419 p[288 + i] = dsaf_read_dev(ddev, 2420 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80); 2421 p[291 + i] = dsaf_read_dev(ddev, 2422 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80); 2423 p[294 + i] = dsaf_read_dev(ddev, 2424 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80); 2425 p[297 + i] = dsaf_read_dev(ddev, 2426 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80); 2427 p[300 + i] = dsaf_read_dev(ddev, 2428 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80); 2429 p[303 + i] = dsaf_read_dev(ddev, 2430 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80); 2431 p[306 + i] = dsaf_read_dev(ddev, 2432 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80); 2433 p[309 + i] = dsaf_read_dev(ddev, 2434 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80); 2435 p[312 + i] = dsaf_read_dev(ddev, 2436 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80); 2437 } 2438 2439 /* dsaf onode registers */ 2440 for (i = 0; i < DSAF_XOD_NUM; i++) { 2441 p[315 + i] = dsaf_read_dev(ddev, 2442 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90); 2443 p[323 + i] = dsaf_read_dev(ddev, 2444 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90); 2445 p[331 + i] = dsaf_read_dev(ddev, 2446 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90); 2447 p[339 + i] = dsaf_read_dev(ddev, 2448 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90); 2449 p[347 + i] = dsaf_read_dev(ddev, 2450 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90); 2451 p[355 + i] = dsaf_read_dev(ddev, 2452 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90); 2453 } 2454 2455 p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90); 2456 p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90); 2457 p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90); 2458 2459 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) { 2460 j = i * DSAF_COMM_CHN + port; 2461 p[366 + i] = dsaf_read_dev(ddev, 2462 DSAF_XOD_GNT_L_0_REG + j * 0x90); 2463 p[369 + i] = dsaf_read_dev(ddev, 2464 DSAF_XOD_GNT_H_0_REG + j * 0x90); 2465 p[372 + i] = dsaf_read_dev(ddev, 2466 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90); 2467 p[375 + i] = dsaf_read_dev(ddev, 2468 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90); 2469 p[378 + i] = dsaf_read_dev(ddev, 2470 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90); 2471 p[381 + i] = dsaf_read_dev(ddev, 2472 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90); 2473 p[384 + i] = dsaf_read_dev(ddev, 2474 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90); 2475 p[387 + i] = dsaf_read_dev(ddev, 2476 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90); 2477 p[390 + i] = dsaf_read_dev(ddev, 2478 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90); 2479 p[393 + i] = dsaf_read_dev(ddev, 2480 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90); 2481 } 2482 2483 p[396] = dsaf_read_dev(ddev, 2484 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90); 2485 p[397] = dsaf_read_dev(ddev, 2486 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90); 2487 p[398] = dsaf_read_dev(ddev, 2488 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90); 2489 p[399] = dsaf_read_dev(ddev, 2490 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90); 2491 p[400] = dsaf_read_dev(ddev, 2492 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90); 2493 p[401] = dsaf_read_dev(ddev, 2494 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90); 2495 p[402] = dsaf_read_dev(ddev, 2496 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90); 2497 p[403] = dsaf_read_dev(ddev, 2498 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90); 2499 p[404] = dsaf_read_dev(ddev, 2500 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90); 2501 p[405] = dsaf_read_dev(ddev, 2502 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90); 2503 p[406] = dsaf_read_dev(ddev, 2504 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90); 2505 p[407] = dsaf_read_dev(ddev, 2506 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90); 2507 p[408] = dsaf_read_dev(ddev, 2508 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90); 2509 2510 /* dsaf voq registers */ 2511 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) { 2512 j = (i * DSAF_COMM_CHN + port) * 0x90; 2513 p[409 + i] = dsaf_read_dev(ddev, 2514 DSAF_VOQ_ECC_INVERT_EN_0_REG + j); 2515 p[412 + i] = dsaf_read_dev(ddev, 2516 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j); 2517 p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j); 2518 p[418 + i] = dsaf_read_dev(ddev, 2519 DSAF_VOQ_OUT_PKT_NUM_0_REG + j); 2520 p[421 + i] = dsaf_read_dev(ddev, 2521 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j); 2522 p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j); 2523 p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j); 2524 p[430 + i] = dsaf_read_dev(ddev, 2525 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j); 2526 p[433 + i] = dsaf_read_dev(ddev, 2527 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j); 2528 p[436 + i] = dsaf_read_dev(ddev, 2529 DSAF_VOQ_PPE_XOD_REQ_0_REG + j); 2530 p[439 + i] = dsaf_read_dev(ddev, 2531 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j); 2532 p[442 + i] = dsaf_read_dev(ddev, 2533 DSAF_VOQ_BP_ALL_THRD_0_REG + j); 2534 } 2535 2536 /* dsaf tbl registers */ 2537 p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG); 2538 p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG); 2539 p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG); 2540 p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG); 2541 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG); 2542 p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG); 2543 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG); 2544 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG); 2545 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 2546 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG); 2547 p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG); 2548 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG); 2549 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG); 2550 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 2551 p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG); 2552 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 2553 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 2554 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 2555 p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 2556 p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 2557 p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 2558 p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 2559 p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG); 2560 2561 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 2562 j = i * 0x8; 2563 p[468 + 2 * i] = dsaf_read_dev(ddev, 2564 DSAF_TBL_DA0_MIS_INFO1_0_REG + j); 2565 p[469 + 2 * i] = dsaf_read_dev(ddev, 2566 DSAF_TBL_DA0_MIS_INFO0_0_REG + j); 2567 } 2568 2569 p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG); 2570 p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG); 2571 p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG); 2572 p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG); 2573 p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG); 2574 p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG); 2575 p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG); 2576 p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG); 2577 p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG); 2578 p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG); 2579 p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG); 2580 p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG); 2581 2582 /* dsaf other registers */ 2583 p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4); 2584 p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4); 2585 p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4); 2586 p[499] = dsaf_read_dev(ddev, 2587 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4); 2588 p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4); 2589 p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4); 2590 2591 if (!is_ver1) 2592 p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4); 2593 2594 /* mark end of dsaf regs */ 2595 for (i = 503; i < 504; i++) 2596 p[i] = 0xdddddddd; 2597 } 2598 2599 static char *hns_dsaf_get_node_stats_strings(char *data, int node, 2600 struct dsaf_device *dsaf_dev) 2601 { 2602 char *buff = data; 2603 int i; 2604 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2605 2606 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node); 2607 buff += ETH_GSTRING_LEN; 2608 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node); 2609 buff += ETH_GSTRING_LEN; 2610 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node); 2611 buff += ETH_GSTRING_LEN; 2612 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node); 2613 buff += ETH_GSTRING_LEN; 2614 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node); 2615 buff += ETH_GSTRING_LEN; 2616 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node); 2617 buff += ETH_GSTRING_LEN; 2618 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node); 2619 buff += ETH_GSTRING_LEN; 2620 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node); 2621 buff += ETH_GSTRING_LEN; 2622 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node); 2623 buff += ETH_GSTRING_LEN; 2624 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node); 2625 buff += ETH_GSTRING_LEN; 2626 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node); 2627 buff += ETH_GSTRING_LEN; 2628 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node); 2629 buff += ETH_GSTRING_LEN; 2630 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node); 2631 buff += ETH_GSTRING_LEN; 2632 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) { 2633 for (i = 0; i < DSAF_PRIO_NR; i++) { 2634 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2635 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts", 2636 node, i); 2637 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2638 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts", 2639 node, i); 2640 buff += ETH_GSTRING_LEN; 2641 } 2642 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN; 2643 } 2644 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node); 2645 buff += ETH_GSTRING_LEN; 2646 2647 return buff; 2648 } 2649 2650 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data, 2651 int node_num) 2652 { 2653 u64 *p = data; 2654 int i; 2655 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num]; 2656 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2657 2658 p[0] = hw_stats->pad_drop; 2659 p[1] = hw_stats->man_pkts; 2660 p[2] = hw_stats->rx_pkts; 2661 p[3] = hw_stats->rx_pkt_id; 2662 p[4] = hw_stats->rx_pause_frame; 2663 p[5] = hw_stats->release_buf_num; 2664 p[6] = hw_stats->sbm_drop; 2665 p[7] = hw_stats->crc_false; 2666 p[8] = hw_stats->bp_drop; 2667 p[9] = hw_stats->rslt_drop; 2668 p[10] = hw_stats->local_addr_false; 2669 p[11] = hw_stats->vlan_drop; 2670 p[12] = hw_stats->stp_drop; 2671 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) { 2672 for (i = 0; i < DSAF_PRIO_NR; i++) { 2673 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i]; 2674 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i]; 2675 } 2676 p[29] = hw_stats->tx_pkts; 2677 return &p[30]; 2678 } 2679 2680 p[13] = hw_stats->tx_pkts; 2681 return &p[14]; 2682 } 2683 2684 /** 2685 *hns_dsaf_get_stats - get dsaf statistic 2686 *@ddev: dsaf device 2687 *@data:statistic value 2688 *@port: port num 2689 */ 2690 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port) 2691 { 2692 u64 *p = data; 2693 int node_num = port; 2694 2695 /* for ge/xge node info */ 2696 p = hns_dsaf_get_node_stats(ddev, p, node_num); 2697 2698 /* for ppe node info */ 2699 node_num = port + DSAF_PPE_INODE_BASE; 2700 (void)hns_dsaf_get_node_stats(ddev, p, node_num); 2701 } 2702 2703 /** 2704 *hns_dsaf_get_sset_count - get dsaf string set count 2705 *@stringset: type of values in data 2706 *return dsaf string name count 2707 */ 2708 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset) 2709 { 2710 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2711 2712 if (stringset == ETH_SS_STATS) { 2713 if (is_ver1) 2714 return DSAF_STATIC_NUM; 2715 else 2716 return DSAF_V2_STATIC_NUM; 2717 } 2718 return 0; 2719 } 2720 2721 /** 2722 *hns_dsaf_get_strings - get dsaf string set 2723 *@stringset:srting set index 2724 *@data:strings name value 2725 *@port:port index 2726 */ 2727 void hns_dsaf_get_strings(int stringset, u8 *data, int port, 2728 struct dsaf_device *dsaf_dev) 2729 { 2730 char *buff = (char *)data; 2731 int node = port; 2732 2733 if (stringset != ETH_SS_STATS) 2734 return; 2735 2736 /* for ge/xge node info */ 2737 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2738 2739 /* for ppe node info */ 2740 node = port + DSAF_PPE_INODE_BASE; 2741 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2742 } 2743 2744 /** 2745 *hns_dsaf_get_sset_count - get dsaf regs count 2746 *return dsaf regs count 2747 */ 2748 int hns_dsaf_get_regs_count(void) 2749 { 2750 return DSAF_DUMP_REGS_NUM; 2751 } 2752 2753 static void set_promisc_tcam_enable(struct dsaf_device *dsaf_dev, u32 port) 2754 { 2755 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80}; 2756 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port}; 2757 struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf}; 2758 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} }; 2759 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 2760 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port}; 2761 struct dsaf_drv_mac_single_dest_entry mask_entry; 2762 struct dsaf_drv_tbl_tcam_key temp_key, mask_key; 2763 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 2764 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 2765 struct dsaf_drv_tbl_tcam_key mac_key; 2766 struct hns_mac_cb *mac_cb; 2767 u8 addr[ETH_ALEN] = {0}; 2768 u8 port_num; 2769 u16 mskid; 2770 2771 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */ 2772 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); 2773 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 2774 if (entry_index != DSAF_INVALID_ENTRY_IDX) 2775 return; 2776 2777 /* put promisc tcam entry in the end. */ 2778 /* 1. set promisc unicast vague tcam entry. */ 2779 entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev); 2780 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 2781 dev_err(dsaf_dev->dev, 2782 "enable uc promisc failed (port:%#x)\n", 2783 port); 2784 return; 2785 } 2786 2787 mac_cb = dsaf_dev->mac_cb[port]; 2788 (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num); 2789 tbl_tcam_ucast.tbl_ucast_out_port = port_num; 2790 2791 /* config uc vague table */ 2792 hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc, 2793 &tbl_tcam_mask_uc, &tbl_tcam_ucast); 2794 2795 /* update software entry */ 2796 soft_mac_entry = priv->soft_mac_tbl; 2797 soft_mac_entry += entry_index; 2798 soft_mac_entry->index = entry_index; 2799 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 2800 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 2801 /* step back to the START for mc. */ 2802 soft_mac_entry = priv->soft_mac_tbl; 2803 2804 /* 2. set promisc multicast vague tcam entry. */ 2805 entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev); 2806 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 2807 dev_err(dsaf_dev->dev, 2808 "enable mc promisc failed (port:%#x)\n", 2809 port); 2810 return; 2811 } 2812 2813 memset(&mask_entry, 0x0, sizeof(mask_entry)); 2814 memset(&mask_key, 0x0, sizeof(mask_key)); 2815 memset(&temp_key, 0x0, sizeof(temp_key)); 2816 mask_entry.addr[0] = 0x01; 2817 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, mask_entry.in_vlan_id, 2818 port, mask_entry.addr); 2819 tbl_tcam_mcast.tbl_mcast_item_vld = 1; 2820 tbl_tcam_mcast.tbl_mcast_old_en = 0; 2821 2822 if (port < DSAF_SERVICE_NW_NUM) { 2823 mskid = port; 2824 } else if (port >= DSAF_BASE_INNER_PORT_NUM) { 2825 mskid = port - DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 2826 } else { 2827 dev_err(dsaf_dev->dev, "%s,pnum(%d)error,key(%#x:%#x)\n", 2828 dsaf_dev->ae_dev.name, port, 2829 mask_key.high.val, mask_key.low.val); 2830 return; 2831 } 2832 2833 dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32], 2834 mskid % 32, 1); 2835 memcpy(&temp_key, &mask_key, sizeof(mask_key)); 2836 hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc, 2837 (struct dsaf_tbl_tcam_data *)(&mask_key), 2838 &tbl_tcam_mcast); 2839 2840 /* update software entry */ 2841 soft_mac_entry += entry_index; 2842 soft_mac_entry->index = entry_index; 2843 soft_mac_entry->tcam_key.high.val = temp_key.high.val; 2844 soft_mac_entry->tcam_key.low.val = temp_key.low.val; 2845 } 2846 2847 static void set_promisc_tcam_disable(struct dsaf_device *dsaf_dev, u32 port) 2848 { 2849 struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port}; 2850 struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0}; 2851 struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} }; 2852 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 2853 struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0}; 2854 struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0}; 2855 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 2856 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 2857 struct dsaf_drv_tbl_tcam_key mac_key; 2858 u8 addr[ETH_ALEN] = {0}; 2859 2860 /* 1. delete uc vague tcam entry. */ 2861 /* promisc use vague table match with vlanid = 0 & macaddr = 0 */ 2862 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); 2863 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 2864 2865 if (entry_index == DSAF_INVALID_ENTRY_IDX) 2866 return; 2867 2868 /* config uc vague table */ 2869 hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc, 2870 &tbl_tcam_mask, &tbl_tcam_ucast); 2871 /* update soft management table. */ 2872 soft_mac_entry = priv->soft_mac_tbl; 2873 soft_mac_entry += entry_index; 2874 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 2875 /* step back to the START for mc. */ 2876 soft_mac_entry = priv->soft_mac_tbl; 2877 2878 /* 2. delete mc vague tcam entry. */ 2879 addr[0] = 0x01; 2880 memset(&mac_key, 0x0, sizeof(mac_key)); 2881 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr); 2882 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 2883 2884 if (entry_index == DSAF_INVALID_ENTRY_IDX) 2885 return; 2886 2887 /* config mc vague table */ 2888 hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc, 2889 &tbl_tcam_mask, &tbl_tcam_mcast); 2890 /* update soft management table. */ 2891 soft_mac_entry += entry_index; 2892 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 2893 } 2894 2895 /* Reserve the last TCAM entry for promisc support */ 2896 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev, 2897 u32 port, bool enable) 2898 { 2899 if (enable) 2900 set_promisc_tcam_enable(dsaf_dev, port); 2901 else 2902 set_promisc_tcam_disable(dsaf_dev, port); 2903 } 2904 2905 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port) 2906 { 2907 u32 val, val_tmp; 2908 int wait_cnt; 2909 2910 if (port >= DSAF_SERVICE_NW_NUM) 2911 return 0; 2912 2913 wait_cnt = 0; 2914 while (wait_cnt++ < HNS_MAX_WAIT_CNT) { 2915 val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG + 2916 (port + DSAF_XGE_NUM) * 0x40); 2917 val_tmp = dsaf_read_dev(dsaf_dev, DSAF_VOQ_OUT_PKT_NUM_0_REG + 2918 (port + DSAF_XGE_NUM) * 0x40); 2919 if (val == val_tmp) 2920 break; 2921 2922 usleep_range(100, 200); 2923 } 2924 2925 if (wait_cnt >= HNS_MAX_WAIT_CNT) { 2926 dev_err(dsaf_dev->dev, "hns dsaf clean wait timeout(%u - %u).\n", 2927 val, val_tmp); 2928 return -EBUSY; 2929 } 2930 2931 return 0; 2932 } 2933 2934 /** 2935 * dsaf_probe - probo dsaf dev 2936 * @pdev: dasf platform device 2937 * retuen 0 - success , negative --fail 2938 */ 2939 static int hns_dsaf_probe(struct platform_device *pdev) 2940 { 2941 struct dsaf_device *dsaf_dev; 2942 int ret; 2943 2944 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv)); 2945 if (IS_ERR(dsaf_dev)) { 2946 ret = PTR_ERR(dsaf_dev); 2947 dev_err(&pdev->dev, 2948 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret); 2949 return ret; 2950 } 2951 2952 ret = hns_dsaf_get_cfg(dsaf_dev); 2953 if (ret) 2954 goto free_dev; 2955 2956 ret = hns_dsaf_init(dsaf_dev); 2957 if (ret) 2958 goto free_dev; 2959 2960 ret = hns_mac_init(dsaf_dev); 2961 if (ret) 2962 goto uninit_dsaf; 2963 2964 ret = hns_ppe_init(dsaf_dev); 2965 if (ret) 2966 goto uninit_mac; 2967 2968 ret = hns_dsaf_ae_init(dsaf_dev); 2969 if (ret) 2970 goto uninit_ppe; 2971 2972 return 0; 2973 2974 uninit_ppe: 2975 hns_ppe_uninit(dsaf_dev); 2976 2977 uninit_mac: 2978 hns_mac_uninit(dsaf_dev); 2979 2980 uninit_dsaf: 2981 hns_dsaf_free(dsaf_dev); 2982 2983 free_dev: 2984 hns_dsaf_free_dev(dsaf_dev); 2985 2986 return ret; 2987 } 2988 2989 /** 2990 * dsaf_remove - remove dsaf dev 2991 * @pdev: dasf platform device 2992 */ 2993 static int hns_dsaf_remove(struct platform_device *pdev) 2994 { 2995 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev); 2996 2997 hns_dsaf_ae_uninit(dsaf_dev); 2998 2999 hns_ppe_uninit(dsaf_dev); 3000 3001 hns_mac_uninit(dsaf_dev); 3002 3003 hns_dsaf_free(dsaf_dev); 3004 3005 hns_dsaf_free_dev(dsaf_dev); 3006 3007 return 0; 3008 } 3009 3010 static const struct of_device_id g_dsaf_match[] = { 3011 {.compatible = "hisilicon,hns-dsaf-v1"}, 3012 {.compatible = "hisilicon,hns-dsaf-v2"}, 3013 {} 3014 }; 3015 MODULE_DEVICE_TABLE(of, g_dsaf_match); 3016 3017 static struct platform_driver g_dsaf_driver = { 3018 .probe = hns_dsaf_probe, 3019 .remove = hns_dsaf_remove, 3020 .driver = { 3021 .name = DSAF_DRV_NAME, 3022 .of_match_table = g_dsaf_match, 3023 .acpi_match_table = hns_dsaf_acpi_match, 3024 }, 3025 }; 3026 3027 module_platform_driver(g_dsaf_driver); 3028 3029 /** 3030 * hns_dsaf_roce_reset - reset dsaf and roce 3031 * @dsaf_fwnode: Pointer to framework node for the dasf 3032 * @enable: false - request reset , true - drop reset 3033 * retuen 0 - success , negative -fail 3034 */ 3035 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset) 3036 { 3037 struct dsaf_device *dsaf_dev; 3038 struct platform_device *pdev; 3039 u32 mp; 3040 u32 sl; 3041 u32 credit; 3042 int i; 3043 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 3044 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 3045 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 3046 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 3047 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 3048 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 3049 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 3050 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 3051 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 3052 }; 3053 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 3054 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 3055 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 3056 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 3057 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 3058 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 3059 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 3060 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 3061 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 3062 }; 3063 3064 /* find the platform device corresponding to fwnode */ 3065 if (is_of_node(dsaf_fwnode)) { 3066 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode)); 3067 } else if (is_acpi_device_node(dsaf_fwnode)) { 3068 pdev = hns_dsaf_find_platform_device(dsaf_fwnode); 3069 } else { 3070 pr_err("fwnode is neither OF or ACPI type\n"); 3071 return -EINVAL; 3072 } 3073 3074 /* check if we were a success in fetching pdev */ 3075 if (!pdev) { 3076 pr_err("couldn't find platform device for node\n"); 3077 return -ENODEV; 3078 } 3079 3080 /* retrieve the dsaf_device from the driver data */ 3081 dsaf_dev = dev_get_drvdata(&pdev->dev); 3082 if (!dsaf_dev) { 3083 dev_err(&pdev->dev, "dsaf_dev is NULL\n"); 3084 put_device(&pdev->dev); 3085 return -ENODEV; 3086 } 3087 3088 /* now, make sure we are running on compatible SoC */ 3089 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 3090 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n", 3091 dsaf_dev->ae_dev.name); 3092 put_device(&pdev->dev); 3093 return -ENODEV; 3094 } 3095 3096 /* do reset or de-reset according to the flag */ 3097 if (!dereset) { 3098 /* reset rocee-channels in dsaf and rocee */ 3099 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 3100 false); 3101 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false); 3102 } else { 3103 /* configure dsaf tx roce correspond to port map and sl map */ 3104 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG); 3105 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 3106 dsaf_set_field(mp, 7 << i * 3, i * 3, 3107 port_map[i][DSAF_ROCE_6PORT_MODE]); 3108 dsaf_set_field(mp, 3 << i * 3, i * 3, 0); 3109 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp); 3110 3111 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG); 3112 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 3113 dsaf_set_field(sl, 3 << i * 2, i * 2, 3114 sl_map[i][DSAF_ROCE_6PORT_MODE]); 3115 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl); 3116 3117 /* de-reset rocee-channels in dsaf and rocee */ 3118 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 3119 true); 3120 msleep(SRST_TIME_INTERVAL); 3121 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true); 3122 3123 /* enable dsaf channel rocee credit */ 3124 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG); 3125 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0); 3126 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 3127 3128 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1); 3129 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 3130 } 3131 3132 put_device(&pdev->dev); 3133 3134 return 0; 3135 } 3136 EXPORT_SYMBOL(hns_dsaf_roce_reset); 3137 3138 MODULE_LICENSE("GPL"); 3139 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3140 MODULE_DESCRIPTION("HNS DSAF driver"); 3141 MODULE_VERSION(DSAF_MOD_VERSION); 3142