1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/vmalloc.h> 23 24 #include "hns_dsaf_mac.h" 25 #include "hns_dsaf_main.h" 26 #include "hns_dsaf_ppe.h" 27 #include "hns_dsaf_rcb.h" 28 #include "hns_dsaf_misc.h" 29 30 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = { 31 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf", 32 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss", 33 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf", 34 [DSAF_MODE_DISABLE_SP] = "single-port", 35 }; 36 37 static const struct acpi_device_id hns_dsaf_acpi_match[] = { 38 { "HISI00B1", 0 }, 39 { "HISI00B2", 0 }, 40 { }, 41 }; 42 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match); 43 44 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 45 { 46 int ret, i; 47 u32 desc_num; 48 u32 buf_size; 49 u32 reset_offset = 0; 50 u32 res_idx = 0; 51 const char *mode_str; 52 struct regmap *syscon; 53 struct resource *res; 54 struct device_node *np = dsaf_dev->dev->of_node, *np_temp; 55 struct platform_device *pdev = to_platform_device(dsaf_dev->dev); 56 57 if (dev_of_node(dsaf_dev->dev)) { 58 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1")) 59 dsaf_dev->dsaf_ver = AE_VERSION_1; 60 else 61 dsaf_dev->dsaf_ver = AE_VERSION_2; 62 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { 63 if (acpi_dev_found(hns_dsaf_acpi_match[0].id)) 64 dsaf_dev->dsaf_ver = AE_VERSION_1; 65 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id)) 66 dsaf_dev->dsaf_ver = AE_VERSION_2; 67 else 68 return -ENXIO; 69 } else { 70 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n"); 71 return -ENXIO; 72 } 73 74 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str); 75 if (ret) { 76 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret); 77 return ret; 78 } 79 for (i = 0; i < DSAF_MODE_MAX; i++) { 80 if (g_dsaf_mode_match[i] && 81 !strcmp(mode_str, g_dsaf_mode_match[i])) 82 break; 83 } 84 if (i >= DSAF_MODE_MAX || 85 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) { 86 dev_err(dsaf_dev->dev, 87 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name); 88 return -EINVAL; 89 } 90 dsaf_dev->dsaf_mode = (enum dsaf_mode)i; 91 92 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE) 93 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE; 94 else 95 dsaf_dev->dsaf_en = HRD_DSAF_MODE; 96 97 if ((i == DSAF_MODE_ENABLE_16VM) || 98 (i == DSAF_MODE_DISABLE_2PORT_8VM) || 99 (i == DSAF_MODE_DISABLE_6PORT_2VM)) 100 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE; 101 else 102 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE; 103 104 if (dev_of_node(dsaf_dev->dev)) { 105 np_temp = of_parse_phandle(np, "subctrl-syscon", 0); 106 syscon = syscon_node_to_regmap(np_temp); 107 of_node_put(np_temp); 108 if (IS_ERR_OR_NULL(syscon)) { 109 res = platform_get_resource(pdev, IORESOURCE_MEM, 110 res_idx++); 111 if (!res) { 112 dev_err(dsaf_dev->dev, "subctrl info is needed!\n"); 113 return -ENOMEM; 114 } 115 116 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev, 117 res); 118 if (IS_ERR(dsaf_dev->sc_base)) { 119 dev_err(dsaf_dev->dev, "subctrl can not map!\n"); 120 return PTR_ERR(dsaf_dev->sc_base); 121 } 122 123 res = platform_get_resource(pdev, IORESOURCE_MEM, 124 res_idx++); 125 if (!res) { 126 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n"); 127 return -ENOMEM; 128 } 129 130 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev, 131 res); 132 if (IS_ERR(dsaf_dev->sds_base)) { 133 dev_err(dsaf_dev->dev, "serdes-ctrl can not map!\n"); 134 return PTR_ERR(dsaf_dev->sds_base); 135 } 136 } else { 137 dsaf_dev->sub_ctrl = syscon; 138 } 139 } 140 141 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base"); 142 if (!res) { 143 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++); 144 if (!res) { 145 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n"); 146 return -ENOMEM; 147 } 148 } 149 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res); 150 if (IS_ERR(dsaf_dev->ppe_base)) { 151 dev_err(dsaf_dev->dev, "ppe-base resource can not map!\n"); 152 return PTR_ERR(dsaf_dev->ppe_base); 153 } 154 dsaf_dev->ppe_paddr = res->start; 155 156 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 157 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 158 "dsaf-base"); 159 if (!res) { 160 res = platform_get_resource(pdev, IORESOURCE_MEM, 161 res_idx); 162 if (!res) { 163 dev_err(dsaf_dev->dev, 164 "dsaf-base info is needed!\n"); 165 return -ENOMEM; 166 } 167 } 168 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res); 169 if (IS_ERR(dsaf_dev->io_base)) { 170 dev_err(dsaf_dev->dev, "dsaf-base resource can not map!\n"); 171 return PTR_ERR(dsaf_dev->io_base); 172 } 173 } 174 175 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num); 176 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT || 177 desc_num > HNS_DSAF_MAX_DESC_CNT) { 178 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n", 179 desc_num, ret); 180 return -EINVAL; 181 } 182 dsaf_dev->desc_num = desc_num; 183 184 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset", 185 &reset_offset); 186 if (ret < 0) { 187 dev_dbg(dsaf_dev->dev, 188 "get reset-field-offset fail, ret=%d!\r\n", ret); 189 } 190 dsaf_dev->reset_offset = reset_offset; 191 192 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size); 193 if (ret < 0) { 194 dev_err(dsaf_dev->dev, 195 "get buf-size fail, ret=%d!\r\n", ret); 196 return ret; 197 } 198 dsaf_dev->buf_size = buf_size; 199 200 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size); 201 if (dsaf_dev->buf_size_type < 0) { 202 dev_err(dsaf_dev->dev, 203 "buf_size(%d) is wrong!\n", buf_size); 204 return -EINVAL; 205 } 206 207 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev); 208 if (!dsaf_dev->misc_op) 209 return -ENOMEM; 210 211 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL))) 212 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n"); 213 else 214 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n"); 215 216 return 0; 217 } 218 219 /** 220 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en 221 * @dsaf_id: dsa fabric id 222 */ 223 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev) 224 { 225 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1); 226 } 227 228 /** 229 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce 230 * @dsaf_id: dsa fabric id 231 * @hns_dsaf_reg_cnt_clr_ce: config value 232 */ 233 static void 234 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce) 235 { 236 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG, 237 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce); 238 } 239 240 /** 241 * hns_ppe_qid_cfg - config ppe qid 242 * @dsaf_id: dsa fabric id 243 * @pppe_qid_cfg: value array 244 */ 245 static void 246 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg) 247 { 248 u32 i; 249 250 for (i = 0; i < DSAF_COMM_CHN; i++) { 251 dsaf_set_dev_field(dsaf_dev, 252 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i, 253 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S, 254 qid_cfg); 255 } 256 } 257 258 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev) 259 { 260 u16 max_q_per_vf, max_vfn; 261 u32 q_id, q_num_per_port; 262 u32 i; 263 264 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 265 q_num_per_port = max_vfn * max_q_per_vf; 266 267 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) { 268 dsaf_set_dev_field(dsaf_dev, 269 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i, 270 0xff, 0, q_id); 271 q_id += q_num_per_port; 272 } 273 } 274 275 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev) 276 { 277 u16 max_q_per_vf, max_vfn; 278 u32 q_id, q_num_per_port; 279 u32 mac_id; 280 281 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 282 return; 283 284 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 285 q_num_per_port = max_vfn * max_q_per_vf; 286 287 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) { 288 dsaf_set_dev_field(dsaf_dev, 289 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 290 DSAFV2_SERDES_LBK_QID_M, 291 DSAFV2_SERDES_LBK_QID_S, 292 q_id); 293 q_id += q_num_per_port; 294 } 295 } 296 297 /** 298 * hns_dsaf_sw_port_type_cfg - cfg sw type 299 * @dsaf_id: dsa fabric id 300 * @psw_port_type: array 301 */ 302 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev, 303 enum dsaf_sw_port_type port_type) 304 { 305 u32 i; 306 307 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 308 dsaf_set_dev_field(dsaf_dev, 309 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i, 310 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S, 311 port_type); 312 } 313 } 314 315 /** 316 * hns_dsaf_stp_port_type_cfg - cfg stp type 317 * @dsaf_id: dsa fabric id 318 * @pstp_port_type: array 319 */ 320 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev, 321 enum dsaf_stp_port_type port_type) 322 { 323 u32 i; 324 325 for (i = 0; i < DSAF_COMM_CHN; i++) { 326 dsaf_set_dev_field(dsaf_dev, 327 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i, 328 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S, 329 port_type); 330 } 331 } 332 333 #define HNS_DSAF_SBM_NUM(dev) \ 334 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM) 335 /** 336 * hns_dsaf_sbm_cfg - config sbm 337 * @dsaf_id: dsa fabric id 338 */ 339 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev) 340 { 341 u32 o_sbm_cfg; 342 u32 i; 343 344 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 345 o_sbm_cfg = dsaf_read_dev(dsaf_dev, 346 DSAF_SBM_CFG_REG_0_REG + 0x80 * i); 347 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1); 348 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0); 349 dsaf_write_dev(dsaf_dev, 350 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg); 351 } 352 } 353 354 /** 355 * hns_dsaf_sbm_cfg_mib_en - config sbm 356 * @dsaf_id: dsa fabric id 357 */ 358 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev) 359 { 360 u32 sbm_cfg_mib_en; 361 u32 i; 362 u32 reg; 363 u32 read_cnt; 364 365 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */ 366 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 367 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 368 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); 369 } 370 371 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 373 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1); 374 } 375 376 /* waitint for all sbm enable finished */ 377 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 378 read_cnt = 0; 379 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 380 do { 381 udelay(1); 382 sbm_cfg_mib_en = dsaf_get_dev_bit( 383 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S); 384 read_cnt++; 385 } while (sbm_cfg_mib_en == 0 && 386 read_cnt < DSAF_CFG_READ_CNT); 387 388 if (sbm_cfg_mib_en == 0) { 389 dev_err(dsaf_dev->dev, 390 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n", 391 dsaf_dev->ae_dev.name, i); 392 return -ENODEV; 393 } 394 } 395 396 return 0; 397 } 398 399 /** 400 * hns_dsaf_sbm_bp_wl_cfg - config sbm 401 * @dsaf_id: dsa fabric id 402 */ 403 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 404 { 405 u32 o_sbm_bp_cfg; 406 u32 reg; 407 u32 i; 408 409 /* XGE */ 410 for (i = 0; i < DSAF_XGE_NUM; i++) { 411 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 412 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 413 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M, 414 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512); 415 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M, 416 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 417 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M, 418 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 419 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 420 421 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 422 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 423 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M, 424 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 425 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M, 426 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 427 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 428 429 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 430 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 431 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 432 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104); 433 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 434 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128); 435 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 436 437 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 438 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 439 dsaf_set_field(o_sbm_bp_cfg, 440 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 441 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110); 442 dsaf_set_field(o_sbm_bp_cfg, 443 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 444 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160); 445 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 446 447 /* for no enable pfc mode */ 448 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 449 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 450 dsaf_set_field(o_sbm_bp_cfg, 451 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 452 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128); 453 dsaf_set_field(o_sbm_bp_cfg, 454 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 455 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192); 456 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 457 } 458 459 /* PPE */ 460 for (i = 0; i < DSAF_COMM_CHN; i++) { 461 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 462 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 463 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 464 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10); 465 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 466 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12); 467 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 468 } 469 470 /* RoCEE */ 471 for (i = 0; i < DSAF_COMM_CHN; i++) { 472 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 473 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 474 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 475 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2); 476 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 477 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4); 478 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 479 } 480 } 481 482 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 483 { 484 u32 o_sbm_bp_cfg; 485 u32 reg; 486 u32 i; 487 488 /* XGE */ 489 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) { 490 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 491 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 492 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M, 493 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256); 494 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M, 495 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 496 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M, 497 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 498 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 499 500 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 501 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 502 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M, 503 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 504 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M, 505 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 506 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 507 508 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 509 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 510 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M, 511 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104); 512 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M, 513 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128); 514 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 515 516 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 517 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 518 dsaf_set_field(o_sbm_bp_cfg, 519 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 520 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 48); 521 dsaf_set_field(o_sbm_bp_cfg, 522 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 523 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 80); 524 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 525 526 /* for no enable pfc mode */ 527 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 528 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 529 dsaf_set_field(o_sbm_bp_cfg, 530 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M, 531 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 192); 532 dsaf_set_field(o_sbm_bp_cfg, 533 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M, 534 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 240); 535 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 536 } 537 538 /* PPE */ 539 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) { 540 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 541 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 542 dsaf_set_field(o_sbm_bp_cfg, 543 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M, 544 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2); 545 dsaf_set_field(o_sbm_bp_cfg, 546 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M, 547 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3); 548 dsaf_set_field(o_sbm_bp_cfg, 549 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M, 550 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52); 551 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 552 } 553 554 /* RoCEE */ 555 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) { 556 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 557 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 558 dsaf_set_field(o_sbm_bp_cfg, 559 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M, 560 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2); 561 dsaf_set_field(o_sbm_bp_cfg, 562 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M, 563 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4); 564 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 565 } 566 } 567 568 /** 569 * hns_dsaf_voq_bp_all_thrd_cfg - voq 570 * @dsaf_id: dsa fabric id 571 */ 572 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev) 573 { 574 u32 voq_bp_all_thrd; 575 u32 i; 576 577 for (i = 0; i < DSAF_VOQ_NUM; i++) { 578 voq_bp_all_thrd = dsaf_read_dev( 579 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i); 580 if (i < DSAF_XGE_NUM) { 581 dsaf_set_field(voq_bp_all_thrd, 582 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930); 584 dsaf_set_field(voq_bp_all_thrd, 585 DSAF_VOQ_BP_ALL_UPTHRD_M, 586 DSAF_VOQ_BP_ALL_UPTHRD_S, 950); 587 } else { 588 dsaf_set_field(voq_bp_all_thrd, 589 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 590 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220); 591 dsaf_set_field(voq_bp_all_thrd, 592 DSAF_VOQ_BP_ALL_UPTHRD_M, 593 DSAF_VOQ_BP_ALL_UPTHRD_S, 230); 594 } 595 dsaf_write_dev( 596 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i, 597 voq_bp_all_thrd); 598 } 599 } 600 601 /** 602 * hns_dsaf_tbl_tcam_data_cfg - tbl 603 * @dsaf_id: dsa fabric id 604 * @ptbl_tcam_data: addr 605 */ 606 static void hns_dsaf_tbl_tcam_data_cfg( 607 struct dsaf_device *dsaf_dev, 608 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 609 { 610 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG, 611 ptbl_tcam_data->tbl_tcam_data_low); 612 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG, 613 ptbl_tcam_data->tbl_tcam_data_high); 614 } 615 616 /** 617 * dsaf_tbl_tcam_mcast_cfg - tbl 618 * @dsaf_id: dsa fabric id 619 * @ptbl_tcam_mcast: addr 620 */ 621 static void hns_dsaf_tbl_tcam_mcast_cfg( 622 struct dsaf_device *dsaf_dev, 623 struct dsaf_tbl_tcam_mcast_cfg *mcast) 624 { 625 u32 mcast_cfg4; 626 627 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 628 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S, 629 mcast->tbl_mcast_item_vld); 630 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S, 631 mcast->tbl_mcast_old_en); 632 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M, 633 DSAF_TBL_MCAST_CFG4_VM128_112_S, 634 mcast->tbl_mcast_port_msk[4]); 635 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4); 636 637 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 638 mcast->tbl_mcast_port_msk[3]); 639 640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 641 mcast->tbl_mcast_port_msk[2]); 642 643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 644 mcast->tbl_mcast_port_msk[1]); 645 646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 647 mcast->tbl_mcast_port_msk[0]); 648 } 649 650 /** 651 * hns_dsaf_tbl_tcam_ucast_cfg - tbl 652 * @dsaf_id: dsa fabric id 653 * @ptbl_tcam_ucast: addr 654 */ 655 static void hns_dsaf_tbl_tcam_ucast_cfg( 656 struct dsaf_device *dsaf_dev, 657 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast) 658 { 659 u32 ucast_cfg1; 660 661 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 662 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S, 663 tbl_tcam_ucast->tbl_ucast_mac_discard); 664 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S, 665 tbl_tcam_ucast->tbl_ucast_item_vld); 666 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S, 667 tbl_tcam_ucast->tbl_ucast_old_en); 668 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S, 669 tbl_tcam_ucast->tbl_ucast_dvc); 670 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 671 DSAF_TBL_UCAST_CFG1_OUT_PORT_S, 672 tbl_tcam_ucast->tbl_ucast_out_port); 673 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1); 674 } 675 676 /** 677 * hns_dsaf_tbl_line_cfg - tbl 678 * @dsaf_id: dsa fabric id 679 * @ptbl_lin: addr 680 */ 681 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev, 682 struct dsaf_tbl_line_cfg *tbl_lin) 683 { 684 u32 tbl_line; 685 686 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG); 687 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S, 688 tbl_lin->tbl_line_mac_discard); 689 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S, 690 tbl_lin->tbl_line_dvc); 691 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M, 692 DSAF_TBL_LINE_CFG_OUT_PORT_S, 693 tbl_lin->tbl_line_out_port); 694 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line); 695 } 696 697 /** 698 * hns_dsaf_tbl_tcam_mcast_pul - tbl 699 * @dsaf_id: dsa fabric id 700 */ 701 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev) 702 { 703 u32 o_tbl_pul; 704 705 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 706 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 707 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 708 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 709 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 710 } 711 712 /** 713 * hns_dsaf_tbl_line_pul - tbl 714 * @dsaf_id: dsa fabric id 715 */ 716 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev) 717 { 718 u32 tbl_pul; 719 720 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 721 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1); 722 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 723 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0); 724 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 725 } 726 727 /** 728 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl 729 * @dsaf_id: dsa fabric id 730 */ 731 static void hns_dsaf_tbl_tcam_data_mcast_pul( 732 struct dsaf_device *dsaf_dev) 733 { 734 u32 o_tbl_pul; 735 736 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 737 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 738 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 739 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 743 } 744 745 /** 746 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl 747 * @dsaf_id: dsa fabric id 748 */ 749 static void hns_dsaf_tbl_tcam_data_ucast_pul( 750 struct dsaf_device *dsaf_dev) 751 { 752 u32 o_tbl_pul; 753 754 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 755 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 756 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1); 757 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0); 760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 761 } 762 763 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en) 764 { 765 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) 766 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, 767 DSAF_CFG_MIX_MODE_S, !!en); 768 } 769 770 void hns_dsaf_set_inner_lb(struct dsaf_device *dsaf_dev, u32 mac_id, u32 en) 771 { 772 if (AE_IS_VER1(dsaf_dev->dsaf_ver) || 773 dsaf_dev->mac_cb[mac_id]->mac_type == HNAE_PORT_DEBUG) 774 return; 775 776 dsaf_set_dev_bit(dsaf_dev, DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 777 DSAFV2_SERDES_LBK_EN_B, !!en); 778 } 779 780 /** 781 * hns_dsaf_tbl_stat_en - tbl 782 * @dsaf_id: dsa fabric id 783 * @ptbl_stat_en: addr 784 */ 785 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev) 786 { 787 u32 o_tbl_ctrl; 788 789 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG); 790 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1); 791 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1); 792 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1); 793 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1); 794 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl); 795 } 796 797 /** 798 * hns_dsaf_rocee_bp_en - rocee back press enable 799 * @dsaf_id: dsa fabric id 800 */ 801 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev) 802 { 803 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 804 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG, 805 DSAF_FC_XGE_TX_PAUSE_S, 1); 806 } 807 808 /* set msk for dsaf exception irq*/ 809 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev, 810 u32 chnn_num, u32 mask_set) 811 { 812 dsaf_write_dev(dsaf_dev, 813 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set); 814 } 815 816 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev, 817 u32 chnn_num, u32 msk_set) 818 { 819 dsaf_write_dev(dsaf_dev, 820 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set); 821 } 822 823 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev, 824 u32 chnn, u32 msk_set) 825 { 826 dsaf_write_dev(dsaf_dev, 827 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set); 828 } 829 830 static void 831 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set) 832 { 833 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set); 834 } 835 836 /* clr dsaf exception irq*/ 837 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev, 838 u32 chnn_num, u32 int_src) 839 { 840 dsaf_write_dev(dsaf_dev, 841 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src); 842 } 843 844 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev, 845 u32 chnn, u32 int_src) 846 { 847 dsaf_write_dev(dsaf_dev, 848 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src); 849 } 850 851 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev, 852 u32 chnn, u32 int_src) 853 { 854 dsaf_write_dev(dsaf_dev, 855 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src); 856 } 857 858 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev, 859 u32 int_src) 860 { 861 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src); 862 } 863 864 /** 865 * hns_dsaf_single_line_tbl_cfg - INT 866 * @dsaf_id: dsa fabric id 867 * @address: 868 * @ptbl_line: 869 */ 870 static void hns_dsaf_single_line_tbl_cfg( 871 struct dsaf_device *dsaf_dev, 872 u32 address, struct dsaf_tbl_line_cfg *ptbl_line) 873 { 874 spin_lock_bh(&dsaf_dev->tcam_lock); 875 876 /*Write Addr*/ 877 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address); 878 879 /*Write Line*/ 880 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line); 881 882 /*Write Plus*/ 883 hns_dsaf_tbl_line_pul(dsaf_dev); 884 885 spin_unlock_bh(&dsaf_dev->tcam_lock); 886 } 887 888 /** 889 * hns_dsaf_tcam_uc_cfg - INT 890 * @dsaf_id: dsa fabric id 891 * @address, 892 * @ptbl_tcam_data, 893 */ 894 static void hns_dsaf_tcam_uc_cfg( 895 struct dsaf_device *dsaf_dev, u32 address, 896 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 897 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 898 { 899 spin_lock_bh(&dsaf_dev->tcam_lock); 900 901 /*Write Addr*/ 902 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 903 /*Write Tcam Data*/ 904 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 905 /*Write Tcam Ucast*/ 906 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast); 907 /*Write Plus*/ 908 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev); 909 910 spin_unlock_bh(&dsaf_dev->tcam_lock); 911 } 912 913 /** 914 * hns_dsaf_tcam_mc_cfg - INT 915 * @dsaf_id: dsa fabric id 916 * @address, 917 * @ptbl_tcam_data, 918 * @ptbl_tcam_mcast, 919 */ 920 static void hns_dsaf_tcam_mc_cfg( 921 struct dsaf_device *dsaf_dev, u32 address, 922 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 923 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 924 { 925 spin_lock_bh(&dsaf_dev->tcam_lock); 926 927 /*Write Addr*/ 928 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 929 /*Write Tcam Data*/ 930 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 931 /*Write Tcam Mcast*/ 932 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast); 933 /*Write Plus*/ 934 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev); 935 936 spin_unlock_bh(&dsaf_dev->tcam_lock); 937 } 938 939 /** 940 * hns_dsaf_tcam_mc_invld - INT 941 * @dsaf_id: dsa fabric id 942 * @address 943 */ 944 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address) 945 { 946 spin_lock_bh(&dsaf_dev->tcam_lock); 947 948 /*Write Addr*/ 949 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 950 951 /*write tcam mcast*/ 952 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0); 953 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0); 954 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0); 955 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0); 956 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0); 957 958 /*Write Plus*/ 959 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev); 960 961 spin_unlock_bh(&dsaf_dev->tcam_lock); 962 } 963 964 /** 965 * hns_dsaf_tcam_uc_get - INT 966 * @dsaf_id: dsa fabric id 967 * @address 968 * @ptbl_tcam_data 969 * @ptbl_tcam_ucast 970 */ 971 static void hns_dsaf_tcam_uc_get( 972 struct dsaf_device *dsaf_dev, u32 address, 973 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 974 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 975 { 976 u32 tcam_read_data0; 977 u32 tcam_read_data4; 978 979 spin_lock_bh(&dsaf_dev->tcam_lock); 980 981 /*Write Addr*/ 982 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 983 984 /*read tcam item puls*/ 985 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 986 987 /*read tcam data*/ 988 ptbl_tcam_data->tbl_tcam_data_high 989 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 990 ptbl_tcam_data->tbl_tcam_data_low 991 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 992 993 /*read tcam mcast*/ 994 tcam_read_data0 = dsaf_read_dev(dsaf_dev, 995 DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 996 tcam_read_data4 = dsaf_read_dev(dsaf_dev, 997 DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 998 999 ptbl_tcam_ucast->tbl_ucast_item_vld 1000 = dsaf_get_bit(tcam_read_data4, 1001 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1002 ptbl_tcam_ucast->tbl_ucast_old_en 1003 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1004 ptbl_tcam_ucast->tbl_ucast_mac_discard 1005 = dsaf_get_bit(tcam_read_data0, 1006 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S); 1007 ptbl_tcam_ucast->tbl_ucast_out_port 1008 = dsaf_get_field(tcam_read_data0, 1009 DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 1010 DSAF_TBL_UCAST_CFG1_OUT_PORT_S); 1011 ptbl_tcam_ucast->tbl_ucast_dvc 1012 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S); 1013 1014 spin_unlock_bh(&dsaf_dev->tcam_lock); 1015 } 1016 1017 /** 1018 * hns_dsaf_tcam_mc_get - INT 1019 * @dsaf_id: dsa fabric id 1020 * @address 1021 * @ptbl_tcam_data 1022 * @ptbl_tcam_ucast 1023 */ 1024 static void hns_dsaf_tcam_mc_get( 1025 struct dsaf_device *dsaf_dev, u32 address, 1026 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 1027 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 1028 { 1029 u32 data_tmp; 1030 1031 spin_lock_bh(&dsaf_dev->tcam_lock); 1032 1033 /*Write Addr*/ 1034 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1035 1036 /*read tcam item puls*/ 1037 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 1038 1039 /*read tcam data*/ 1040 ptbl_tcam_data->tbl_tcam_data_high = 1041 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 1042 ptbl_tcam_data->tbl_tcam_data_low = 1043 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1044 1045 /*read tcam mcast*/ 1046 ptbl_tcam_mcast->tbl_mcast_port_msk[0] = 1047 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1048 ptbl_tcam_mcast->tbl_mcast_port_msk[1] = 1049 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 1050 ptbl_tcam_mcast->tbl_mcast_port_msk[2] = 1051 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 1052 ptbl_tcam_mcast->tbl_mcast_port_msk[3] = 1053 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 1054 1055 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1056 ptbl_tcam_mcast->tbl_mcast_item_vld = 1057 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1058 ptbl_tcam_mcast->tbl_mcast_old_en = 1059 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1060 ptbl_tcam_mcast->tbl_mcast_port_msk[4] = 1061 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M, 1062 DSAF_TBL_MCAST_CFG4_VM128_112_S); 1063 1064 spin_unlock_bh(&dsaf_dev->tcam_lock); 1065 } 1066 1067 /** 1068 * hns_dsaf_tbl_line_init - INT 1069 * @dsaf_id: dsa fabric id 1070 */ 1071 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev) 1072 { 1073 u32 i; 1074 /* defaultly set all lineal mac table entry resulting discard */ 1075 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} }; 1076 1077 for (i = 0; i < DSAF_LINE_SUM; i++) 1078 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line); 1079 } 1080 1081 /** 1082 * hns_dsaf_tbl_tcam_init - INT 1083 * @dsaf_id: dsa fabric id 1084 */ 1085 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev) 1086 { 1087 u32 i; 1088 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} }; 1089 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} }; 1090 1091 /*tcam tbl*/ 1092 for (i = 0; i < DSAF_TCAM_SUM; i++) 1093 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast); 1094 } 1095 1096 /** 1097 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg 1098 * @mac_cb: mac contrl block 1099 */ 1100 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev, 1101 int mac_id, int tc_en) 1102 { 1103 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en); 1104 } 1105 1106 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev, 1107 int mac_id, int tx_en, int rx_en) 1108 { 1109 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1110 if (!tx_en || !rx_en) 1111 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n"); 1112 1113 return; 1114 } 1115 1116 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1117 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en); 1118 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1119 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en); 1120 } 1121 1122 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1123 u32 en) 1124 { 1125 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1126 if (!en) { 1127 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n"); 1128 return -EINVAL; 1129 } 1130 } 1131 1132 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1133 DSAF_MAC_PAUSE_RX_EN_B, !!en); 1134 1135 return 0; 1136 } 1137 1138 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1139 u32 *en) 1140 { 1141 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1142 *en = 1; 1143 else 1144 *en = dsaf_get_dev_bit(dsaf_dev, 1145 DSAF_PAUSE_CFG_REG + mac_id * 4, 1146 DSAF_MAC_PAUSE_RX_EN_B); 1147 } 1148 1149 /** 1150 * hns_dsaf_tbl_tcam_init - INT 1151 * @dsaf_id: dsa fabric id 1152 * @dsaf_mode 1153 */ 1154 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev) 1155 { 1156 u32 i; 1157 u32 o_dsaf_cfg; 1158 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 1159 1160 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG); 1161 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en); 1162 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode); 1163 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0); 1164 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0); 1165 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0); 1166 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg); 1167 1168 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1); 1169 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD); 1170 1171 /* set 22 queue per tx ppe engine, only used in switch mode */ 1172 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE); 1173 1174 /* set promisc def queue id */ 1175 hns_dsaf_mix_def_qid_cfg(dsaf_dev); 1176 1177 /* set inner loopback queue id */ 1178 hns_dsaf_inner_qid_cfg(dsaf_dev); 1179 1180 /* in non switch mode, set all port to access mode */ 1181 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN); 1182 1183 /*set dsaf pfc to 0 for parseing rx pause*/ 1184 for (i = 0; i < DSAF_COMM_CHN; i++) { 1185 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0); 1186 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1); 1187 } 1188 1189 /*msk and clr exception irqs */ 1190 for (i = 0; i < DSAF_COMM_CHN; i++) { 1191 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful); 1192 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful); 1193 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful); 1194 1195 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful); 1196 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful); 1197 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful); 1198 } 1199 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful); 1200 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful); 1201 } 1202 1203 /** 1204 * hns_dsaf_inode_init - INT 1205 * @dsaf_id: dsa fabric id 1206 */ 1207 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev) 1208 { 1209 u32 reg; 1210 u32 tc_cfg; 1211 u32 i; 1212 1213 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE) 1214 tc_cfg = HNS_DSAF_I4TC_CFG; 1215 else 1216 tc_cfg = HNS_DSAF_I8TC_CFG; 1217 1218 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1219 for (i = 0; i < DSAF_INODE_NUM; i++) { 1220 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1221 dsaf_set_dev_field(dsaf_dev, reg, 1222 DSAF_INODE_IN_PORT_NUM_M, 1223 DSAF_INODE_IN_PORT_NUM_S, 1224 i % DSAF_XGE_NUM); 1225 } 1226 } else { 1227 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) { 1228 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1229 dsaf_set_dev_field(dsaf_dev, reg, 1230 DSAF_INODE_IN_PORT_NUM_M, 1231 DSAF_INODE_IN_PORT_NUM_S, 0); 1232 dsaf_set_dev_field(dsaf_dev, reg, 1233 DSAFV2_INODE_IN_PORT1_NUM_M, 1234 DSAFV2_INODE_IN_PORT1_NUM_S, 1); 1235 dsaf_set_dev_field(dsaf_dev, reg, 1236 DSAFV2_INODE_IN_PORT2_NUM_M, 1237 DSAFV2_INODE_IN_PORT2_NUM_S, 2); 1238 dsaf_set_dev_field(dsaf_dev, reg, 1239 DSAFV2_INODE_IN_PORT3_NUM_M, 1240 DSAFV2_INODE_IN_PORT3_NUM_S, 3); 1241 dsaf_set_dev_field(dsaf_dev, reg, 1242 DSAFV2_INODE_IN_PORT4_NUM_M, 1243 DSAFV2_INODE_IN_PORT4_NUM_S, 4); 1244 dsaf_set_dev_field(dsaf_dev, reg, 1245 DSAFV2_INODE_IN_PORT5_NUM_M, 1246 DSAFV2_INODE_IN_PORT5_NUM_S, 5); 1247 } 1248 } 1249 for (i = 0; i < DSAF_INODE_NUM; i++) { 1250 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; 1251 dsaf_write_dev(dsaf_dev, reg, tc_cfg); 1252 } 1253 } 1254 1255 /** 1256 * hns_dsaf_sbm_init - INT 1257 * @dsaf_id: dsa fabric id 1258 */ 1259 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev) 1260 { 1261 u32 flag; 1262 u32 finish_msk; 1263 u32 cnt = 0; 1264 int ret; 1265 1266 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1267 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev); 1268 finish_msk = DSAF_SRAM_INIT_OVER_M; 1269 } else { 1270 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev); 1271 finish_msk = DSAFV2_SRAM_INIT_OVER_M; 1272 } 1273 1274 /* enable sbm chanel, disable sbm chanel shcut function*/ 1275 hns_dsaf_sbm_cfg(dsaf_dev); 1276 1277 /* enable sbm mib */ 1278 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev); 1279 if (ret) { 1280 dev_err(dsaf_dev->dev, 1281 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n", 1282 dsaf_dev->ae_dev.name, ret); 1283 return ret; 1284 } 1285 1286 /* enable sbm initial link sram */ 1287 hns_dsaf_sbm_link_sram_init_en(dsaf_dev); 1288 1289 do { 1290 usleep_range(200, 210);/*udelay(200);*/ 1291 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG, 1292 finish_msk, DSAF_SRAM_INIT_OVER_S); 1293 cnt++; 1294 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) && 1295 cnt < DSAF_CFG_READ_CNT); 1296 1297 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) { 1298 dev_err(dsaf_dev->dev, 1299 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n", 1300 dsaf_dev->ae_dev.name, flag, cnt); 1301 return -ENODEV; 1302 } 1303 1304 hns_dsaf_rocee_bp_en(dsaf_dev); 1305 1306 return 0; 1307 } 1308 1309 /** 1310 * hns_dsaf_tbl_init - INT 1311 * @dsaf_id: dsa fabric id 1312 */ 1313 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev) 1314 { 1315 hns_dsaf_tbl_stat_en(dsaf_dev); 1316 1317 hns_dsaf_tbl_tcam_init(dsaf_dev); 1318 hns_dsaf_tbl_line_init(dsaf_dev); 1319 } 1320 1321 /** 1322 * hns_dsaf_voq_init - INT 1323 * @dsaf_id: dsa fabric id 1324 */ 1325 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev) 1326 { 1327 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev); 1328 } 1329 1330 /** 1331 * hns_dsaf_init_hw - init dsa fabric hardware 1332 * @dsaf_dev: dsa fabric device struct pointer 1333 */ 1334 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev) 1335 { 1336 int ret; 1337 1338 dev_dbg(dsaf_dev->dev, 1339 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name); 1340 1341 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1342 mdelay(10); 1343 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1); 1344 1345 hns_dsaf_comm_init(dsaf_dev); 1346 1347 /*init XBAR_INODE*/ 1348 hns_dsaf_inode_init(dsaf_dev); 1349 1350 /*init SBM*/ 1351 ret = hns_dsaf_sbm_init(dsaf_dev); 1352 if (ret) 1353 return ret; 1354 1355 /*init TBL*/ 1356 hns_dsaf_tbl_init(dsaf_dev); 1357 1358 /*init VOQ*/ 1359 hns_dsaf_voq_init(dsaf_dev); 1360 1361 return 0; 1362 } 1363 1364 /** 1365 * hns_dsaf_remove_hw - uninit dsa fabric hardware 1366 * @dsaf_dev: dsa fabric device struct pointer 1367 */ 1368 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev) 1369 { 1370 /*reset*/ 1371 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1372 } 1373 1374 /** 1375 * hns_dsaf_init - init dsa fabric 1376 * @dsaf_dev: dsa fabric device struct pointer 1377 * retuen 0 - success , negative --fail 1378 */ 1379 static int hns_dsaf_init(struct dsaf_device *dsaf_dev) 1380 { 1381 struct dsaf_drv_priv *priv = 1382 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1383 u32 i; 1384 int ret; 1385 1386 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 1387 return 0; 1388 1389 spin_lock_init(&dsaf_dev->tcam_lock); 1390 ret = hns_dsaf_init_hw(dsaf_dev); 1391 if (ret) 1392 return ret; 1393 1394 /* malloc mem for tcam mac key(vlan+mac) */ 1395 priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl) 1396 * DSAF_TCAM_SUM); 1397 if (!priv->soft_mac_tbl) { 1398 ret = -ENOMEM; 1399 goto remove_hw; 1400 } 1401 1402 /*all entry invall */ 1403 for (i = 0; i < DSAF_TCAM_SUM; i++) 1404 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX; 1405 1406 return 0; 1407 1408 remove_hw: 1409 hns_dsaf_remove_hw(dsaf_dev); 1410 return ret; 1411 } 1412 1413 /** 1414 * hns_dsaf_free - free dsa fabric 1415 * @dsaf_dev: dsa fabric device struct pointer 1416 */ 1417 static void hns_dsaf_free(struct dsaf_device *dsaf_dev) 1418 { 1419 struct dsaf_drv_priv *priv = 1420 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1421 1422 hns_dsaf_remove_hw(dsaf_dev); 1423 1424 /* free all mac mem */ 1425 vfree(priv->soft_mac_tbl); 1426 priv->soft_mac_tbl = NULL; 1427 } 1428 1429 /** 1430 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry 1431 * @dsaf_dev: dsa fabric device struct pointer 1432 * @mac_key: mac entry struct pointer 1433 */ 1434 static u16 hns_dsaf_find_soft_mac_entry( 1435 struct dsaf_device *dsaf_dev, 1436 struct dsaf_drv_tbl_tcam_key *mac_key) 1437 { 1438 struct dsaf_drv_priv *priv = 1439 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1440 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1441 u32 i; 1442 1443 soft_mac_entry = priv->soft_mac_tbl; 1444 for (i = 0; i < DSAF_TCAM_SUM; i++) { 1445 /* invall tab entry */ 1446 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) && 1447 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) && 1448 (soft_mac_entry->tcam_key.low.val == mac_key->low.val)) 1449 /* return find result --soft index */ 1450 return soft_mac_entry->index; 1451 1452 soft_mac_entry++; 1453 } 1454 return DSAF_INVALID_ENTRY_IDX; 1455 } 1456 1457 /** 1458 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry 1459 * @dsaf_dev: dsa fabric device struct pointer 1460 */ 1461 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev) 1462 { 1463 struct dsaf_drv_priv *priv = 1464 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1465 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1466 u32 i; 1467 1468 soft_mac_entry = priv->soft_mac_tbl; 1469 for (i = 0; i < DSAF_TCAM_SUM; i++) { 1470 /* inv all entry */ 1471 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX) 1472 /* return find result --soft index */ 1473 return i; 1474 1475 soft_mac_entry++; 1476 } 1477 return DSAF_INVALID_ENTRY_IDX; 1478 } 1479 1480 /** 1481 * hns_dsaf_set_mac_key - set mac key 1482 * @dsaf_dev: dsa fabric device struct pointer 1483 * @mac_key: tcam key pointer 1484 * @vlan_id: vlan id 1485 * @in_port_num: input port num 1486 * @addr: mac addr 1487 */ 1488 static void hns_dsaf_set_mac_key( 1489 struct dsaf_device *dsaf_dev, 1490 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num, 1491 u8 *addr) 1492 { 1493 u8 port; 1494 1495 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE) 1496 /*DSAF mode : in port id fixed 0*/ 1497 port = 0; 1498 else 1499 /*non-dsaf mode*/ 1500 port = in_port_num; 1501 1502 mac_key->high.bits.mac_0 = addr[0]; 1503 mac_key->high.bits.mac_1 = addr[1]; 1504 mac_key->high.bits.mac_2 = addr[2]; 1505 mac_key->high.bits.mac_3 = addr[3]; 1506 mac_key->low.bits.mac_4 = addr[4]; 1507 mac_key->low.bits.mac_5 = addr[5]; 1508 mac_key->low.bits.vlan = vlan_id; 1509 mac_key->low.bits.port = port; 1510 } 1511 1512 /** 1513 * hns_dsaf_set_mac_uc_entry - set mac uc-entry 1514 * @dsaf_dev: dsa fabric device struct pointer 1515 * @mac_entry: uc-mac entry 1516 */ 1517 int hns_dsaf_set_mac_uc_entry( 1518 struct dsaf_device *dsaf_dev, 1519 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1520 { 1521 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1522 struct dsaf_drv_tbl_tcam_key mac_key; 1523 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1524 struct dsaf_drv_priv *priv = 1525 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1526 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1527 1528 /* mac addr check */ 1529 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1530 MAC_IS_BROADCAST(mac_entry->addr) || 1531 MAC_IS_MULTICAST(mac_entry->addr)) { 1532 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n", 1533 dsaf_dev->ae_dev.name, mac_entry->addr); 1534 return -EINVAL; 1535 } 1536 1537 /* config key */ 1538 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1539 mac_entry->in_port_num, mac_entry->addr); 1540 1541 /* entry ie exist? */ 1542 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1543 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1544 /*if has not inv entry,find a empty entry */ 1545 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1546 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1547 /* has not empty,return error */ 1548 dev_err(dsaf_dev->dev, 1549 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1550 dsaf_dev->ae_dev.name, 1551 mac_key.high.val, mac_key.low.val); 1552 return -EINVAL; 1553 } 1554 } 1555 1556 dev_dbg(dsaf_dev->dev, 1557 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1558 dsaf_dev->ae_dev.name, mac_key.high.val, 1559 mac_key.low.val, entry_index); 1560 1561 /* config hardware entry */ 1562 mac_data.tbl_ucast_item_vld = 1; 1563 mac_data.tbl_ucast_mac_discard = 0; 1564 mac_data.tbl_ucast_old_en = 0; 1565 /* default config dvc to 0 */ 1566 mac_data.tbl_ucast_dvc = 0; 1567 mac_data.tbl_ucast_out_port = mac_entry->port_num; 1568 hns_dsaf_tcam_uc_cfg( 1569 dsaf_dev, entry_index, 1570 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1571 1572 /* config software entry */ 1573 soft_mac_entry += entry_index; 1574 soft_mac_entry->index = entry_index; 1575 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1576 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1577 1578 return 0; 1579 } 1580 1581 /** 1582 * hns_dsaf_set_mac_mc_entry - set mac mc-entry 1583 * @dsaf_dev: dsa fabric device struct pointer 1584 * @mac_entry: mc-mac entry 1585 */ 1586 int hns_dsaf_set_mac_mc_entry( 1587 struct dsaf_device *dsaf_dev, 1588 struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1589 { 1590 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1591 struct dsaf_drv_tbl_tcam_key mac_key; 1592 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1593 struct dsaf_drv_priv *priv = 1594 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1595 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1596 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1597 1598 /* mac addr check */ 1599 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1600 dev_err(dsaf_dev->dev, "set uc %s Mac %pM err!\n", 1601 dsaf_dev->ae_dev.name, mac_entry->addr); 1602 return -EINVAL; 1603 } 1604 1605 /*config key */ 1606 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 1607 mac_entry->in_vlan_id, 1608 mac_entry->in_port_num, mac_entry->addr); 1609 1610 /* entry ie exist? */ 1611 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1612 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1613 /*if hasnot, find enpty entry*/ 1614 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1615 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1616 /*if hasnot empty, error*/ 1617 dev_err(dsaf_dev->dev, 1618 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1619 dsaf_dev->ae_dev.name, 1620 mac_key.high.val, mac_key.low.val); 1621 return -EINVAL; 1622 } 1623 1624 /* config hardware entry */ 1625 memset(mac_data.tbl_mcast_port_msk, 1626 0, sizeof(mac_data.tbl_mcast_port_msk)); 1627 } else { 1628 /* config hardware entry */ 1629 hns_dsaf_tcam_mc_get( 1630 dsaf_dev, entry_index, 1631 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1632 } 1633 mac_data.tbl_mcast_old_en = 0; 1634 mac_data.tbl_mcast_item_vld = 1; 1635 dsaf_set_field(mac_data.tbl_mcast_port_msk[0], 1636 0x3F, 0, mac_entry->port_mask[0]); 1637 1638 dev_dbg(dsaf_dev->dev, 1639 "set_uc_entry, %s key(%#x:%#x) entry_index%d\n", 1640 dsaf_dev->ae_dev.name, mac_key.high.val, 1641 mac_key.low.val, entry_index); 1642 1643 hns_dsaf_tcam_mc_cfg( 1644 dsaf_dev, entry_index, 1645 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1646 1647 /* config software entry */ 1648 soft_mac_entry += entry_index; 1649 soft_mac_entry->index = entry_index; 1650 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1651 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1652 1653 return 0; 1654 } 1655 1656 /** 1657 * hns_dsaf_add_mac_mc_port - add mac mc-port 1658 * @dsaf_dev: dsa fabric device struct pointer 1659 * @mac_entry: mc-mac entry 1660 */ 1661 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 1662 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1663 { 1664 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1665 struct dsaf_drv_tbl_tcam_key mac_key; 1666 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1667 struct dsaf_drv_priv *priv = 1668 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1669 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1670 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1671 int mskid; 1672 1673 /*chechk mac addr */ 1674 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1675 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n", 1676 mac_entry->addr); 1677 return -EINVAL; 1678 } 1679 1680 /*config key */ 1681 hns_dsaf_set_mac_key( 1682 dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1683 mac_entry->in_port_num, mac_entry->addr); 1684 1685 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg)); 1686 1687 /*check exist? */ 1688 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1689 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1690 /*if hasnot , find a empty*/ 1691 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1692 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1693 /*if hasnot empty, error*/ 1694 dev_err(dsaf_dev->dev, 1695 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1696 dsaf_dev->ae_dev.name, mac_key.high.val, 1697 mac_key.low.val); 1698 return -EINVAL; 1699 } 1700 } else { 1701 /*if exist, add in */ 1702 hns_dsaf_tcam_mc_get( 1703 dsaf_dev, entry_index, 1704 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1705 } 1706 /* config hardware entry */ 1707 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1708 mskid = mac_entry->port_num; 1709 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1710 mskid = mac_entry->port_num - 1711 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1712 } else { 1713 dev_err(dsaf_dev->dev, 1714 "%s,pnum(%d)error,key(%#x:%#x)\n", 1715 dsaf_dev->ae_dev.name, mac_entry->port_num, 1716 mac_key.high.val, mac_key.low.val); 1717 return -EINVAL; 1718 } 1719 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1); 1720 mac_data.tbl_mcast_old_en = 0; 1721 mac_data.tbl_mcast_item_vld = 1; 1722 1723 dev_dbg(dsaf_dev->dev, 1724 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1725 dsaf_dev->ae_dev.name, mac_key.high.val, 1726 mac_key.low.val, entry_index); 1727 1728 hns_dsaf_tcam_mc_cfg( 1729 dsaf_dev, entry_index, 1730 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1731 1732 /*config software entry */ 1733 soft_mac_entry += entry_index; 1734 soft_mac_entry->index = entry_index; 1735 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1736 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1737 1738 return 0; 1739 } 1740 1741 /** 1742 * hns_dsaf_del_mac_entry - del mac mc-port 1743 * @dsaf_dev: dsa fabric device struct pointer 1744 * @vlan_id: vlian id 1745 * @in_port_num: input port num 1746 * @addr : mac addr 1747 */ 1748 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 1749 u8 in_port_num, u8 *addr) 1750 { 1751 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1752 struct dsaf_drv_tbl_tcam_key mac_key; 1753 struct dsaf_drv_priv *priv = 1754 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1755 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1756 1757 /*check mac addr */ 1758 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) { 1759 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n", 1760 addr); 1761 return -EINVAL; 1762 } 1763 1764 /*config key */ 1765 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr); 1766 1767 /*exist ?*/ 1768 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1769 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1770 /*not exist, error */ 1771 dev_err(dsaf_dev->dev, 1772 "del_mac_entry failed, %s Mac key(%#x:%#x)\n", 1773 dsaf_dev->ae_dev.name, 1774 mac_key.high.val, mac_key.low.val); 1775 return -EINVAL; 1776 } 1777 dev_dbg(dsaf_dev->dev, 1778 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1779 dsaf_dev->ae_dev.name, mac_key.high.val, 1780 mac_key.low.val, entry_index); 1781 1782 /*do del opt*/ 1783 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1784 1785 /*del soft emtry */ 1786 soft_mac_entry += entry_index; 1787 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1788 1789 return 0; 1790 } 1791 1792 /** 1793 * hns_dsaf_del_mac_mc_port - del mac mc- port 1794 * @dsaf_dev: dsa fabric device struct pointer 1795 * @mac_entry: mac entry 1796 */ 1797 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 1798 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1799 { 1800 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1801 struct dsaf_drv_tbl_tcam_key mac_key; 1802 struct dsaf_drv_priv *priv = 1803 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1804 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1805 u16 vlan_id; 1806 u8 in_port_num; 1807 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1808 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1809 int mskid; 1810 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0}; 1811 1812 if (!(void *)mac_entry) { 1813 dev_err(dsaf_dev->dev, 1814 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n"); 1815 return -EINVAL; 1816 } 1817 1818 /*get key info*/ 1819 vlan_id = mac_entry->in_vlan_id; 1820 in_port_num = mac_entry->in_port_num; 1821 1822 /*check mac addr */ 1823 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1824 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n", 1825 mac_entry->addr); 1826 return -EINVAL; 1827 } 1828 1829 /*config key */ 1830 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, 1831 mac_entry->addr); 1832 1833 /*check is exist? */ 1834 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1835 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1836 /*find none */ 1837 dev_err(dsaf_dev->dev, 1838 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n", 1839 dsaf_dev->ae_dev.name, 1840 mac_key.high.val, mac_key.low.val); 1841 return -EINVAL; 1842 } 1843 1844 dev_dbg(dsaf_dev->dev, 1845 "del_mac_mc_port, %s key(%#x:%#x) index%d\n", 1846 dsaf_dev->ae_dev.name, mac_key.high.val, 1847 mac_key.low.val, entry_index); 1848 1849 /*read entry*/ 1850 hns_dsaf_tcam_mc_get( 1851 dsaf_dev, entry_index, 1852 (struct dsaf_tbl_tcam_data *)(&tmp_mac_key), &mac_data); 1853 1854 /*del the port*/ 1855 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1856 mskid = mac_entry->port_num; 1857 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1858 mskid = mac_entry->port_num - 1859 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1860 } else { 1861 dev_err(dsaf_dev->dev, 1862 "%s,pnum(%d)error,key(%#x:%#x)\n", 1863 dsaf_dev->ae_dev.name, mac_entry->port_num, 1864 mac_key.high.val, mac_key.low.val); 1865 return -EINVAL; 1866 } 1867 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0); 1868 1869 /*check non port, do del entry */ 1870 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 1871 sizeof(mac_data.tbl_mcast_port_msk))) { 1872 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1873 1874 /* del soft entry */ 1875 soft_mac_entry += entry_index; 1876 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1877 } else { /* not zer, just del port, updata*/ 1878 hns_dsaf_tcam_mc_cfg( 1879 dsaf_dev, entry_index, 1880 (struct dsaf_tbl_tcam_data *)(&mac_key), &mac_data); 1881 } 1882 1883 return 0; 1884 } 1885 1886 /** 1887 * hns_dsaf_get_mac_uc_entry - get mac uc entry 1888 * @dsaf_dev: dsa fabric device struct pointer 1889 * @mac_entry: mac entry 1890 */ 1891 int hns_dsaf_get_mac_uc_entry(struct dsaf_device *dsaf_dev, 1892 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1893 { 1894 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1895 struct dsaf_drv_tbl_tcam_key mac_key; 1896 1897 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1898 1899 /* check macaddr */ 1900 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1901 MAC_IS_BROADCAST(mac_entry->addr)) { 1902 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n", 1903 mac_entry->addr); 1904 return -EINVAL; 1905 } 1906 1907 /*config key */ 1908 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1909 mac_entry->in_port_num, mac_entry->addr); 1910 1911 /*check exist? */ 1912 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1913 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1914 /*find none, error */ 1915 dev_err(dsaf_dev->dev, 1916 "get_uc_entry failed, %s Mac key(%#x:%#x)\n", 1917 dsaf_dev->ae_dev.name, 1918 mac_key.high.val, mac_key.low.val); 1919 return -EINVAL; 1920 } 1921 dev_dbg(dsaf_dev->dev, 1922 "get_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1923 dsaf_dev->ae_dev.name, mac_key.high.val, 1924 mac_key.low.val, entry_index); 1925 1926 /*read entry*/ 1927 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index, 1928 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 1929 mac_entry->port_num = mac_data.tbl_ucast_out_port; 1930 1931 return 0; 1932 } 1933 1934 /** 1935 * hns_dsaf_get_mac_mc_entry - get mac mc entry 1936 * @dsaf_dev: dsa fabric device struct pointer 1937 * @mac_entry: mac entry 1938 */ 1939 int hns_dsaf_get_mac_mc_entry(struct dsaf_device *dsaf_dev, 1940 struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1941 { 1942 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1943 struct dsaf_drv_tbl_tcam_key mac_key; 1944 1945 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1946 1947 /*check mac addr */ 1948 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1949 MAC_IS_BROADCAST(mac_entry->addr)) { 1950 dev_err(dsaf_dev->dev, "get_entry failed,addr %pM\n", 1951 mac_entry->addr); 1952 return -EINVAL; 1953 } 1954 1955 /*config key */ 1956 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1957 mac_entry->in_port_num, mac_entry->addr); 1958 1959 /*check exist? */ 1960 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1961 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1962 /* find none, error */ 1963 dev_err(dsaf_dev->dev, 1964 "get_mac_uc_entry failed, %s Mac key(%#x:%#x)\n", 1965 dsaf_dev->ae_dev.name, mac_key.high.val, 1966 mac_key.low.val); 1967 return -EINVAL; 1968 } 1969 dev_dbg(dsaf_dev->dev, 1970 "get_mac_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1971 dsaf_dev->ae_dev.name, mac_key.high.val, 1972 mac_key.low.val, entry_index); 1973 1974 /*read entry */ 1975 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, 1976 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 1977 1978 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F; 1979 return 0; 1980 } 1981 1982 /** 1983 * hns_dsaf_get_mac_entry_by_index - get mac entry by tab index 1984 * @dsaf_dev: dsa fabric device struct pointer 1985 * @entry_index: tab entry index 1986 * @mac_entry: mac entry 1987 */ 1988 int hns_dsaf_get_mac_entry_by_index( 1989 struct dsaf_device *dsaf_dev, 1990 u16 entry_index, struct dsaf_drv_mac_multi_dest_entry *mac_entry) 1991 { 1992 struct dsaf_drv_tbl_tcam_key mac_key; 1993 1994 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1995 struct dsaf_tbl_tcam_ucast_cfg mac_uc_data; 1996 char mac_addr[MAC_NUM_OCTETS_PER_ADDR] = {0}; 1997 1998 if (entry_index >= DSAF_TCAM_SUM) { 1999 /* find none, del error */ 2000 dev_err(dsaf_dev->dev, "get_uc_entry failed, %s\n", 2001 dsaf_dev->ae_dev.name); 2002 return -EINVAL; 2003 } 2004 2005 /* mc entry, do read opt */ 2006 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, 2007 (struct dsaf_tbl_tcam_data *)&mac_key, &mac_data); 2008 2009 mac_entry->port_mask[0] = mac_data.tbl_mcast_port_msk[0] & 0x3F; 2010 2011 /***get mac addr*/ 2012 mac_addr[0] = mac_key.high.bits.mac_0; 2013 mac_addr[1] = mac_key.high.bits.mac_1; 2014 mac_addr[2] = mac_key.high.bits.mac_2; 2015 mac_addr[3] = mac_key.high.bits.mac_3; 2016 mac_addr[4] = mac_key.low.bits.mac_4; 2017 mac_addr[5] = mac_key.low.bits.mac_5; 2018 /**is mc or uc*/ 2019 if (MAC_IS_MULTICAST((u8 *)mac_addr) || 2020 MAC_IS_L3_MULTICAST((u8 *)mac_addr)) { 2021 /**mc donot do*/ 2022 } else { 2023 /*is not mc, just uc... */ 2024 hns_dsaf_tcam_uc_get(dsaf_dev, entry_index, 2025 (struct dsaf_tbl_tcam_data *)&mac_key, 2026 &mac_uc_data); 2027 mac_entry->port_mask[0] = (1 << mac_uc_data.tbl_ucast_out_port); 2028 } 2029 2030 return 0; 2031 } 2032 2033 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev, 2034 size_t sizeof_priv) 2035 { 2036 struct dsaf_device *dsaf_dev; 2037 2038 dsaf_dev = devm_kzalloc(dev, 2039 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL); 2040 if (unlikely(!dsaf_dev)) { 2041 dsaf_dev = ERR_PTR(-ENOMEM); 2042 } else { 2043 dsaf_dev->dev = dev; 2044 dev_set_drvdata(dev, dsaf_dev); 2045 } 2046 2047 return dsaf_dev; 2048 } 2049 2050 /** 2051 * hns_dsaf_free_dev - free dev mem 2052 * @dev: struct device pointer 2053 */ 2054 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev) 2055 { 2056 (void)dev_set_drvdata(dsaf_dev->dev, NULL); 2057 } 2058 2059 /** 2060 * dsaf_pfc_unit_cnt - set pfc unit count 2061 * @dsaf_id: dsa fabric id 2062 * @pport_rate: value array 2063 * @pdsaf_pfc_unit_cnt: value array 2064 */ 2065 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id, 2066 enum dsaf_port_rate_mode rate) 2067 { 2068 u32 unit_cnt; 2069 2070 switch (rate) { 2071 case DSAF_PORT_RATE_10000: 2072 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2073 break; 2074 case DSAF_PORT_RATE_1000: 2075 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2076 break; 2077 case DSAF_PORT_RATE_2500: 2078 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2079 break; 2080 default: 2081 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2082 } 2083 2084 dsaf_set_dev_field(dsaf_dev, 2085 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id), 2086 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S, 2087 unit_cnt); 2088 } 2089 2090 /** 2091 * dsaf_port_work_rate_cfg - fifo 2092 * @dsaf_id: dsa fabric id 2093 * @xge_ge_work_mode 2094 */ 2095 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id, 2096 enum dsaf_port_rate_mode rate_mode) 2097 { 2098 u32 port_work_mode; 2099 2100 port_work_mode = dsaf_read_dev( 2101 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id); 2102 2103 if (rate_mode == DSAF_PORT_RATE_10000) 2104 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1); 2105 else 2106 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0); 2107 2108 dsaf_write_dev(dsaf_dev, 2109 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id, 2110 port_work_mode); 2111 2112 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode); 2113 } 2114 2115 /** 2116 * hns_dsaf_fix_mac_mode - dsaf modify mac mode 2117 * @mac_cb: mac contrl block 2118 */ 2119 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb) 2120 { 2121 enum dsaf_port_rate_mode mode; 2122 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev; 2123 int mac_id = mac_cb->mac_id; 2124 2125 if (mac_cb->mac_type != HNAE_PORT_SERVICE) 2126 return; 2127 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII) 2128 mode = DSAF_PORT_RATE_10000; 2129 else 2130 mode = DSAF_PORT_RATE_1000; 2131 2132 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode); 2133 } 2134 2135 static u32 hns_dsaf_get_inode_prio_reg(int index) 2136 { 2137 int base_index, offset; 2138 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG; 2139 2140 base_index = (index + 1) / DSAF_REG_PER_ZONE; 2141 offset = (index + 1) % DSAF_REG_PER_ZONE; 2142 2143 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index + 2144 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset; 2145 } 2146 2147 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num) 2148 { 2149 struct dsaf_hw_stats *hw_stats 2150 = &dsaf_dev->hw_stats[node_num]; 2151 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2152 int i; 2153 u32 reg_tmp; 2154 2155 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev, 2156 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2157 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev, 2158 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num); 2159 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev, 2160 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num); 2161 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev, 2162 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num); 2163 2164 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2165 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2166 hw_stats->rx_pause_frame += 2167 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num); 2168 2169 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev, 2170 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num); 2171 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev, 2172 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num); 2173 hw_stats->crc_false += dsaf_read_dev(dsaf_dev, 2174 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2175 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev, 2176 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2177 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev, 2178 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2179 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev, 2180 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2181 2182 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev, 2183 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num); 2184 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev, 2185 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num); 2186 2187 /* pfc pause frame statistics stored in dsaf inode*/ 2188 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) { 2189 for (i = 0; i < DSAF_PRIO_NR; i++) { 2190 reg_tmp = hns_dsaf_get_inode_prio_reg(i); 2191 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev, 2192 reg_tmp + 0x4 * (u64)node_num); 2193 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev, 2194 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG + 2195 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i + 2196 0xF0 * (u64)node_num); 2197 } 2198 } 2199 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev, 2200 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num); 2201 } 2202 2203 /** 2204 *hns_dsaf_get_regs - dump dsaf regs 2205 *@dsaf_dev: dsaf device 2206 *@data:data for value of regs 2207 */ 2208 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data) 2209 { 2210 u32 i = 0; 2211 u32 j; 2212 u32 *p = data; 2213 u32 reg_tmp; 2214 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2215 2216 /* dsaf common registers */ 2217 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG); 2218 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG); 2219 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG); 2220 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG); 2221 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG); 2222 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG); 2223 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG); 2224 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG); 2225 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG); 2226 2227 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4); 2228 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4); 2229 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2230 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2231 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2232 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2233 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4); 2234 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4); 2235 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2236 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4); 2237 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4); 2238 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2239 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4); 2240 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4); 2241 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4); 2242 2243 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2244 p[24 + i] = dsaf_read_dev(ddev, 2245 DSAF_SW_PORT_TYPE_0_REG + i * 4); 2246 2247 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4); 2248 2249 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2250 p[33 + i] = dsaf_read_dev(ddev, 2251 DSAF_PORT_DEF_VLAN_0_REG + i * 4); 2252 2253 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) 2254 p[41 + i] = dsaf_read_dev(ddev, 2255 DSAF_VM_DEF_VLAN_0_REG + i * 4); 2256 2257 /* dsaf inode registers */ 2258 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG); 2259 2260 p[171] = dsaf_read_dev(ddev, 2261 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80); 2262 2263 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2264 j = i * DSAF_COMM_CHN + port; 2265 p[172 + i] = dsaf_read_dev(ddev, 2266 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80); 2267 p[175 + i] = dsaf_read_dev(ddev, 2268 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80); 2269 p[178 + i] = dsaf_read_dev(ddev, 2270 DSAF_INODE_BP_STATUS_0_REG + j * 0x80); 2271 p[181 + i] = dsaf_read_dev(ddev, 2272 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80); 2273 p[184 + i] = dsaf_read_dev(ddev, 2274 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80); 2275 p[187 + i] = dsaf_read_dev(ddev, 2276 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80); 2277 p[190 + i] = dsaf_read_dev(ddev, 2278 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80); 2279 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2280 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2281 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80); 2282 p[196 + i] = dsaf_read_dev(ddev, 2283 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80); 2284 p[199 + i] = dsaf_read_dev(ddev, 2285 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80); 2286 p[202 + i] = dsaf_read_dev(ddev, 2287 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80); 2288 p[205 + i] = dsaf_read_dev(ddev, 2289 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80); 2290 p[208 + i] = dsaf_read_dev(ddev, 2291 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80); 2292 p[211 + i] = dsaf_read_dev(ddev, 2293 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80); 2294 p[214 + i] = dsaf_read_dev(ddev, 2295 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80); 2296 p[217 + i] = dsaf_read_dev(ddev, 2297 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4); 2298 p[220 + i] = dsaf_read_dev(ddev, 2299 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4); 2300 p[223 + i] = dsaf_read_dev(ddev, 2301 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4); 2302 p[224 + i] = dsaf_read_dev(ddev, 2303 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4); 2304 } 2305 2306 p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4); 2307 2308 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2309 j = i * DSAF_COMM_CHN + port; 2310 p[228 + i] = dsaf_read_dev(ddev, 2311 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4); 2312 } 2313 2314 p[231] = dsaf_read_dev(ddev, 2315 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4); 2316 2317 /* dsaf inode registers */ 2318 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) { 2319 j = i * DSAF_COMM_CHN + port; 2320 p[232 + i] = dsaf_read_dev(ddev, 2321 DSAF_SBM_CFG_REG_0_REG + j * 0x80); 2322 p[235 + i] = dsaf_read_dev(ddev, 2323 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80); 2324 p[238 + i] = dsaf_read_dev(ddev, 2325 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80); 2326 p[241 + i] = dsaf_read_dev(ddev, 2327 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80); 2328 p[244 + i] = dsaf_read_dev(ddev, 2329 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80); 2330 p[245 + i] = dsaf_read_dev(ddev, 2331 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80); 2332 p[248 + i] = dsaf_read_dev(ddev, 2333 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80); 2334 p[251 + i] = dsaf_read_dev(ddev, 2335 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80); 2336 p[254 + i] = dsaf_read_dev(ddev, 2337 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80); 2338 p[257 + i] = dsaf_read_dev(ddev, 2339 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80); 2340 p[260 + i] = dsaf_read_dev(ddev, 2341 DSAF_SBM_INER_ST_0_REG + j * 0x80); 2342 p[263 + i] = dsaf_read_dev(ddev, 2343 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80); 2344 p[266 + i] = dsaf_read_dev(ddev, 2345 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80); 2346 p[269 + i] = dsaf_read_dev(ddev, 2347 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80); 2348 p[272 + i] = dsaf_read_dev(ddev, 2349 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80); 2350 p[275 + i] = dsaf_read_dev(ddev, 2351 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80); 2352 p[278 + i] = dsaf_read_dev(ddev, 2353 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80); 2354 p[281 + i] = dsaf_read_dev(ddev, 2355 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80); 2356 p[284 + i] = dsaf_read_dev(ddev, 2357 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80); 2358 p[287 + i] = dsaf_read_dev(ddev, 2359 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80); 2360 p[290 + i] = dsaf_read_dev(ddev, 2361 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80); 2362 p[293 + i] = dsaf_read_dev(ddev, 2363 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80); 2364 p[296 + i] = dsaf_read_dev(ddev, 2365 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80); 2366 p[299 + i] = dsaf_read_dev(ddev, 2367 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80); 2368 p[302 + i] = dsaf_read_dev(ddev, 2369 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80); 2370 p[305 + i] = dsaf_read_dev(ddev, 2371 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80); 2372 p[308 + i] = dsaf_read_dev(ddev, 2373 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80); 2374 } 2375 2376 /* dsaf onode registers */ 2377 for (i = 0; i < DSAF_XOD_NUM; i++) { 2378 p[311 + i] = dsaf_read_dev(ddev, 2379 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90); 2380 p[319 + i] = dsaf_read_dev(ddev, 2381 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90); 2382 p[327 + i] = dsaf_read_dev(ddev, 2383 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90); 2384 p[335 + i] = dsaf_read_dev(ddev, 2385 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90); 2386 p[343 + i] = dsaf_read_dev(ddev, 2387 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90); 2388 p[351 + i] = dsaf_read_dev(ddev, 2389 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90); 2390 } 2391 2392 p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90); 2393 p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90); 2394 p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90); 2395 2396 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) { 2397 j = i * DSAF_COMM_CHN + port; 2398 p[362 + i] = dsaf_read_dev(ddev, 2399 DSAF_XOD_GNT_L_0_REG + j * 0x90); 2400 p[365 + i] = dsaf_read_dev(ddev, 2401 DSAF_XOD_GNT_H_0_REG + j * 0x90); 2402 p[368 + i] = dsaf_read_dev(ddev, 2403 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90); 2404 p[371 + i] = dsaf_read_dev(ddev, 2405 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90); 2406 p[374 + i] = dsaf_read_dev(ddev, 2407 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90); 2408 p[377 + i] = dsaf_read_dev(ddev, 2409 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90); 2410 p[380 + i] = dsaf_read_dev(ddev, 2411 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90); 2412 p[383 + i] = dsaf_read_dev(ddev, 2413 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90); 2414 p[386 + i] = dsaf_read_dev(ddev, 2415 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90); 2416 p[389 + i] = dsaf_read_dev(ddev, 2417 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90); 2418 } 2419 2420 p[392] = dsaf_read_dev(ddev, 2421 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90); 2422 p[393] = dsaf_read_dev(ddev, 2423 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90); 2424 p[394] = dsaf_read_dev(ddev, 2425 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90); 2426 p[395] = dsaf_read_dev(ddev, 2427 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90); 2428 p[396] = dsaf_read_dev(ddev, 2429 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90); 2430 p[397] = dsaf_read_dev(ddev, 2431 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90); 2432 p[398] = dsaf_read_dev(ddev, 2433 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90); 2434 p[399] = dsaf_read_dev(ddev, 2435 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90); 2436 p[400] = dsaf_read_dev(ddev, 2437 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90); 2438 p[401] = dsaf_read_dev(ddev, 2439 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90); 2440 p[402] = dsaf_read_dev(ddev, 2441 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90); 2442 p[403] = dsaf_read_dev(ddev, 2443 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90); 2444 p[404] = dsaf_read_dev(ddev, 2445 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90); 2446 2447 /* dsaf voq registers */ 2448 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) { 2449 j = (i * DSAF_COMM_CHN + port) * 0x90; 2450 p[405 + i] = dsaf_read_dev(ddev, 2451 DSAF_VOQ_ECC_INVERT_EN_0_REG + j); 2452 p[408 + i] = dsaf_read_dev(ddev, 2453 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j); 2454 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j); 2455 p[414 + i] = dsaf_read_dev(ddev, 2456 DSAF_VOQ_OUT_PKT_NUM_0_REG + j); 2457 p[417 + i] = dsaf_read_dev(ddev, 2458 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j); 2459 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j); 2460 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j); 2461 p[426 + i] = dsaf_read_dev(ddev, 2462 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j); 2463 p[429 + i] = dsaf_read_dev(ddev, 2464 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j); 2465 p[432 + i] = dsaf_read_dev(ddev, 2466 DSAF_VOQ_PPE_XOD_REQ_0_REG + j); 2467 p[435 + i] = dsaf_read_dev(ddev, 2468 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j); 2469 p[438 + i] = dsaf_read_dev(ddev, 2470 DSAF_VOQ_BP_ALL_THRD_0_REG + j); 2471 } 2472 2473 /* dsaf tbl registers */ 2474 p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG); 2475 p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG); 2476 p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG); 2477 p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG); 2478 p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG); 2479 p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG); 2480 p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG); 2481 p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG); 2482 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 2483 p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG); 2484 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG); 2485 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG); 2486 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG); 2487 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 2488 p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG); 2489 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 2490 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 2491 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 2492 p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 2493 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 2494 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 2495 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 2496 p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG); 2497 2498 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 2499 j = i * 0x8; 2500 p[464 + 2 * i] = dsaf_read_dev(ddev, 2501 DSAF_TBL_DA0_MIS_INFO1_0_REG + j); 2502 p[465 + 2 * i] = dsaf_read_dev(ddev, 2503 DSAF_TBL_DA0_MIS_INFO0_0_REG + j); 2504 } 2505 2506 p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG); 2507 p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG); 2508 p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG); 2509 p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG); 2510 p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG); 2511 p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG); 2512 p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG); 2513 p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG); 2514 p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG); 2515 p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG); 2516 p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG); 2517 p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG); 2518 2519 /* dsaf other registers */ 2520 p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4); 2521 p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4); 2522 p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4); 2523 p[495] = dsaf_read_dev(ddev, 2524 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4); 2525 p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4); 2526 p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4); 2527 2528 if (!is_ver1) 2529 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4); 2530 2531 /* mark end of dsaf regs */ 2532 for (i = 499; i < 504; i++) 2533 p[i] = 0xdddddddd; 2534 } 2535 2536 static char *hns_dsaf_get_node_stats_strings(char *data, int node, 2537 struct dsaf_device *dsaf_dev) 2538 { 2539 char *buff = data; 2540 int i; 2541 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2542 2543 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node); 2544 buff += ETH_GSTRING_LEN; 2545 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node); 2546 buff += ETH_GSTRING_LEN; 2547 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node); 2548 buff += ETH_GSTRING_LEN; 2549 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node); 2550 buff += ETH_GSTRING_LEN; 2551 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node); 2552 buff += ETH_GSTRING_LEN; 2553 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node); 2554 buff += ETH_GSTRING_LEN; 2555 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node); 2556 buff += ETH_GSTRING_LEN; 2557 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node); 2558 buff += ETH_GSTRING_LEN; 2559 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node); 2560 buff += ETH_GSTRING_LEN; 2561 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node); 2562 buff += ETH_GSTRING_LEN; 2563 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node); 2564 buff += ETH_GSTRING_LEN; 2565 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node); 2566 buff += ETH_GSTRING_LEN; 2567 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node); 2568 buff += ETH_GSTRING_LEN; 2569 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) { 2570 for (i = 0; i < DSAF_PRIO_NR; i++) { 2571 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2572 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts", 2573 node, i); 2574 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2575 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts", 2576 node, i); 2577 buff += ETH_GSTRING_LEN; 2578 } 2579 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN; 2580 } 2581 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node); 2582 buff += ETH_GSTRING_LEN; 2583 2584 return buff; 2585 } 2586 2587 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data, 2588 int node_num) 2589 { 2590 u64 *p = data; 2591 int i; 2592 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num]; 2593 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2594 2595 p[0] = hw_stats->pad_drop; 2596 p[1] = hw_stats->man_pkts; 2597 p[2] = hw_stats->rx_pkts; 2598 p[3] = hw_stats->rx_pkt_id; 2599 p[4] = hw_stats->rx_pause_frame; 2600 p[5] = hw_stats->release_buf_num; 2601 p[6] = hw_stats->sbm_drop; 2602 p[7] = hw_stats->crc_false; 2603 p[8] = hw_stats->bp_drop; 2604 p[9] = hw_stats->rslt_drop; 2605 p[10] = hw_stats->local_addr_false; 2606 p[11] = hw_stats->vlan_drop; 2607 p[12] = hw_stats->stp_drop; 2608 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) { 2609 for (i = 0; i < DSAF_PRIO_NR; i++) { 2610 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i]; 2611 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i]; 2612 } 2613 p[29] = hw_stats->tx_pkts; 2614 return &p[30]; 2615 } 2616 2617 p[13] = hw_stats->tx_pkts; 2618 return &p[14]; 2619 } 2620 2621 /** 2622 *hns_dsaf_get_stats - get dsaf statistic 2623 *@ddev: dsaf device 2624 *@data:statistic value 2625 *@port: port num 2626 */ 2627 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port) 2628 { 2629 u64 *p = data; 2630 int node_num = port; 2631 2632 /* for ge/xge node info */ 2633 p = hns_dsaf_get_node_stats(ddev, p, node_num); 2634 2635 /* for ppe node info */ 2636 node_num = port + DSAF_PPE_INODE_BASE; 2637 (void)hns_dsaf_get_node_stats(ddev, p, node_num); 2638 } 2639 2640 /** 2641 *hns_dsaf_get_sset_count - get dsaf string set count 2642 *@stringset: type of values in data 2643 *return dsaf string name count 2644 */ 2645 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset) 2646 { 2647 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2648 2649 if (stringset == ETH_SS_STATS) { 2650 if (is_ver1) 2651 return DSAF_STATIC_NUM; 2652 else 2653 return DSAF_V2_STATIC_NUM; 2654 } 2655 return 0; 2656 } 2657 2658 /** 2659 *hns_dsaf_get_strings - get dsaf string set 2660 *@stringset:srting set index 2661 *@data:strings name value 2662 *@port:port index 2663 */ 2664 void hns_dsaf_get_strings(int stringset, u8 *data, int port, 2665 struct dsaf_device *dsaf_dev) 2666 { 2667 char *buff = (char *)data; 2668 int node = port; 2669 2670 if (stringset != ETH_SS_STATS) 2671 return; 2672 2673 /* for ge/xge node info */ 2674 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2675 2676 /* for ppe node info */ 2677 node = port + DSAF_PPE_INODE_BASE; 2678 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2679 } 2680 2681 /** 2682 *hns_dsaf_get_sset_count - get dsaf regs count 2683 *return dsaf regs count 2684 */ 2685 int hns_dsaf_get_regs_count(void) 2686 { 2687 return DSAF_DUMP_REGS_NUM; 2688 } 2689 2690 /** 2691 * dsaf_probe - probo dsaf dev 2692 * @pdev: dasf platform device 2693 * retuen 0 - success , negative --fail 2694 */ 2695 static int hns_dsaf_probe(struct platform_device *pdev) 2696 { 2697 struct dsaf_device *dsaf_dev; 2698 int ret; 2699 2700 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv)); 2701 if (IS_ERR(dsaf_dev)) { 2702 ret = PTR_ERR(dsaf_dev); 2703 dev_err(&pdev->dev, 2704 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret); 2705 return ret; 2706 } 2707 2708 ret = hns_dsaf_get_cfg(dsaf_dev); 2709 if (ret) 2710 goto free_dev; 2711 2712 ret = hns_dsaf_init(dsaf_dev); 2713 if (ret) 2714 goto free_dev; 2715 2716 ret = hns_mac_init(dsaf_dev); 2717 if (ret) 2718 goto uninit_dsaf; 2719 2720 ret = hns_ppe_init(dsaf_dev); 2721 if (ret) 2722 goto uninit_mac; 2723 2724 ret = hns_dsaf_ae_init(dsaf_dev); 2725 if (ret) 2726 goto uninit_ppe; 2727 2728 return 0; 2729 2730 uninit_ppe: 2731 hns_ppe_uninit(dsaf_dev); 2732 2733 uninit_mac: 2734 hns_mac_uninit(dsaf_dev); 2735 2736 uninit_dsaf: 2737 hns_dsaf_free(dsaf_dev); 2738 2739 free_dev: 2740 hns_dsaf_free_dev(dsaf_dev); 2741 2742 return ret; 2743 } 2744 2745 /** 2746 * dsaf_remove - remove dsaf dev 2747 * @pdev: dasf platform device 2748 */ 2749 static int hns_dsaf_remove(struct platform_device *pdev) 2750 { 2751 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev); 2752 2753 hns_dsaf_ae_uninit(dsaf_dev); 2754 2755 hns_ppe_uninit(dsaf_dev); 2756 2757 hns_mac_uninit(dsaf_dev); 2758 2759 hns_dsaf_free(dsaf_dev); 2760 2761 hns_dsaf_free_dev(dsaf_dev); 2762 2763 return 0; 2764 } 2765 2766 static const struct of_device_id g_dsaf_match[] = { 2767 {.compatible = "hisilicon,hns-dsaf-v1"}, 2768 {.compatible = "hisilicon,hns-dsaf-v2"}, 2769 {} 2770 }; 2771 2772 static struct platform_driver g_dsaf_driver = { 2773 .probe = hns_dsaf_probe, 2774 .remove = hns_dsaf_remove, 2775 .driver = { 2776 .name = DSAF_DRV_NAME, 2777 .of_match_table = g_dsaf_match, 2778 .acpi_match_table = hns_dsaf_acpi_match, 2779 }, 2780 }; 2781 2782 module_platform_driver(g_dsaf_driver); 2783 2784 MODULE_LICENSE("GPL"); 2785 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2786 MODULE_DESCRIPTION("HNS DSAF driver"); 2787 MODULE_VERSION(DSAF_MOD_VERSION); 2788