1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/device.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/vmalloc.h> 24 25 #include "hns_dsaf_mac.h" 26 #include "hns_dsaf_main.h" 27 #include "hns_dsaf_ppe.h" 28 #include "hns_dsaf_rcb.h" 29 #include "hns_dsaf_misc.h" 30 31 const static char *g_dsaf_mode_match[DSAF_MODE_MAX] = { 32 [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf", 33 [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss", 34 [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf", 35 [DSAF_MODE_DISABLE_SP] = "single-port", 36 }; 37 38 static const struct acpi_device_id hns_dsaf_acpi_match[] = { 39 { "HISI00B1", 0 }, 40 { "HISI00B2", 0 }, 41 { }, 42 }; 43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match); 44 45 static int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev) 46 { 47 int ret, i; 48 u32 desc_num; 49 u32 buf_size; 50 u32 reset_offset = 0; 51 u32 res_idx = 0; 52 const char *mode_str; 53 struct regmap *syscon; 54 struct resource *res; 55 struct device_node *np = dsaf_dev->dev->of_node, *np_temp; 56 struct platform_device *pdev = to_platform_device(dsaf_dev->dev); 57 58 if (dev_of_node(dsaf_dev->dev)) { 59 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1")) 60 dsaf_dev->dsaf_ver = AE_VERSION_1; 61 else 62 dsaf_dev->dsaf_ver = AE_VERSION_2; 63 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) { 64 if (acpi_dev_found(hns_dsaf_acpi_match[0].id)) 65 dsaf_dev->dsaf_ver = AE_VERSION_1; 66 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id)) 67 dsaf_dev->dsaf_ver = AE_VERSION_2; 68 else 69 return -ENXIO; 70 } else { 71 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n"); 72 return -ENXIO; 73 } 74 75 ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str); 76 if (ret) { 77 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret); 78 return ret; 79 } 80 for (i = 0; i < DSAF_MODE_MAX; i++) { 81 if (g_dsaf_mode_match[i] && 82 !strcmp(mode_str, g_dsaf_mode_match[i])) 83 break; 84 } 85 if (i >= DSAF_MODE_MAX || 86 i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) { 87 dev_err(dsaf_dev->dev, 88 "%s prs mode str fail!\n", dsaf_dev->ae_dev.name); 89 return -EINVAL; 90 } 91 dsaf_dev->dsaf_mode = (enum dsaf_mode)i; 92 93 if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE) 94 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE; 95 else 96 dsaf_dev->dsaf_en = HRD_DSAF_MODE; 97 98 if ((i == DSAF_MODE_ENABLE_16VM) || 99 (i == DSAF_MODE_DISABLE_2PORT_8VM) || 100 (i == DSAF_MODE_DISABLE_6PORT_2VM)) 101 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE; 102 else 103 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE; 104 105 if (dev_of_node(dsaf_dev->dev)) { 106 np_temp = of_parse_phandle(np, "subctrl-syscon", 0); 107 syscon = syscon_node_to_regmap(np_temp); 108 of_node_put(np_temp); 109 if (IS_ERR_OR_NULL(syscon)) { 110 res = platform_get_resource(pdev, IORESOURCE_MEM, 111 res_idx++); 112 if (!res) { 113 dev_err(dsaf_dev->dev, "subctrl info is needed!\n"); 114 return -ENOMEM; 115 } 116 117 dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev, 118 res); 119 if (IS_ERR(dsaf_dev->sc_base)) 120 return PTR_ERR(dsaf_dev->sc_base); 121 122 res = platform_get_resource(pdev, IORESOURCE_MEM, 123 res_idx++); 124 if (!res) { 125 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n"); 126 return -ENOMEM; 127 } 128 129 dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev, 130 res); 131 if (IS_ERR(dsaf_dev->sds_base)) 132 return PTR_ERR(dsaf_dev->sds_base); 133 } else { 134 dsaf_dev->sub_ctrl = syscon; 135 } 136 } 137 138 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base"); 139 if (!res) { 140 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++); 141 if (!res) { 142 dev_err(dsaf_dev->dev, "ppe-base info is needed!\n"); 143 return -ENOMEM; 144 } 145 } 146 dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res); 147 if (IS_ERR(dsaf_dev->ppe_base)) 148 return PTR_ERR(dsaf_dev->ppe_base); 149 dsaf_dev->ppe_paddr = res->start; 150 151 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) { 152 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 153 "dsaf-base"); 154 if (!res) { 155 res = platform_get_resource(pdev, IORESOURCE_MEM, 156 res_idx); 157 if (!res) { 158 dev_err(dsaf_dev->dev, 159 "dsaf-base info is needed!\n"); 160 return -ENOMEM; 161 } 162 } 163 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res); 164 if (IS_ERR(dsaf_dev->io_base)) 165 return PTR_ERR(dsaf_dev->io_base); 166 } 167 168 ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num); 169 if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT || 170 desc_num > HNS_DSAF_MAX_DESC_CNT) { 171 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n", 172 desc_num, ret); 173 return -EINVAL; 174 } 175 dsaf_dev->desc_num = desc_num; 176 177 ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset", 178 &reset_offset); 179 if (ret < 0) { 180 dev_dbg(dsaf_dev->dev, 181 "get reset-field-offset fail, ret=%d!\r\n", ret); 182 } 183 dsaf_dev->reset_offset = reset_offset; 184 185 ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size); 186 if (ret < 0) { 187 dev_err(dsaf_dev->dev, 188 "get buf-size fail, ret=%d!\r\n", ret); 189 return ret; 190 } 191 dsaf_dev->buf_size = buf_size; 192 193 dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size); 194 if (dsaf_dev->buf_size_type < 0) { 195 dev_err(dsaf_dev->dev, 196 "buf_size(%d) is wrong!\n", buf_size); 197 return -EINVAL; 198 } 199 200 dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev); 201 if (!dsaf_dev->misc_op) 202 return -ENOMEM; 203 204 if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL))) 205 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n"); 206 else 207 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n"); 208 209 return 0; 210 } 211 212 /** 213 * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en 214 * @dsaf_id: dsa fabric id 215 */ 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev) 217 { 218 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1); 219 } 220 221 /** 222 * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce 223 * @dsaf_id: dsa fabric id 224 * @hns_dsaf_reg_cnt_clr_ce: config value 225 */ 226 static void 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce) 228 { 229 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG, 230 DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce); 231 } 232 233 /** 234 * hns_ppe_qid_cfg - config ppe qid 235 * @dsaf_id: dsa fabric id 236 * @pppe_qid_cfg: value array 237 */ 238 static void 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg) 240 { 241 u32 i; 242 243 for (i = 0; i < DSAF_COMM_CHN; i++) { 244 dsaf_set_dev_field(dsaf_dev, 245 DSAF_PPE_QID_CFG_0_REG + 0x0004 * i, 246 DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S, 247 qid_cfg); 248 } 249 } 250 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev) 252 { 253 u16 max_q_per_vf, max_vfn; 254 u32 q_id, q_num_per_port; 255 u32 i; 256 257 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 258 q_num_per_port = max_vfn * max_q_per_vf; 259 260 for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) { 261 dsaf_set_dev_field(dsaf_dev, 262 DSAF_MIX_DEF_QID_0_REG + 0x0004 * i, 263 0xff, 0, q_id); 264 q_id += q_num_per_port; 265 } 266 } 267 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev) 269 { 270 u16 max_q_per_vf, max_vfn; 271 u32 q_id, q_num_per_port; 272 u32 mac_id; 273 274 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 275 return; 276 277 hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf); 278 q_num_per_port = max_vfn * max_q_per_vf; 279 280 for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) { 281 dsaf_set_dev_field(dsaf_dev, 282 DSAFV2_SERDES_LBK_0_REG + 4 * mac_id, 283 DSAFV2_SERDES_LBK_QID_M, 284 DSAFV2_SERDES_LBK_QID_S, 285 q_id); 286 q_id += q_num_per_port; 287 } 288 } 289 290 /** 291 * hns_dsaf_sw_port_type_cfg - cfg sw type 292 * @dsaf_id: dsa fabric id 293 * @psw_port_type: array 294 */ 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev, 296 enum dsaf_sw_port_type port_type) 297 { 298 u32 i; 299 300 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 301 dsaf_set_dev_field(dsaf_dev, 302 DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i, 303 DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S, 304 port_type); 305 } 306 } 307 308 /** 309 * hns_dsaf_stp_port_type_cfg - cfg stp type 310 * @dsaf_id: dsa fabric id 311 * @pstp_port_type: array 312 */ 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev, 314 enum dsaf_stp_port_type port_type) 315 { 316 u32 i; 317 318 for (i = 0; i < DSAF_COMM_CHN; i++) { 319 dsaf_set_dev_field(dsaf_dev, 320 DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i, 321 DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S, 322 port_type); 323 } 324 } 325 326 #define HNS_DSAF_SBM_NUM(dev) \ 327 (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM) 328 /** 329 * hns_dsaf_sbm_cfg - config sbm 330 * @dsaf_id: dsa fabric id 331 */ 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev) 333 { 334 u32 o_sbm_cfg; 335 u32 i; 336 337 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 338 o_sbm_cfg = dsaf_read_dev(dsaf_dev, 339 DSAF_SBM_CFG_REG_0_REG + 0x80 * i); 340 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1); 341 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0); 342 dsaf_write_dev(dsaf_dev, 343 DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg); 344 } 345 } 346 347 /** 348 * hns_dsaf_sbm_cfg_mib_en - config sbm 349 * @dsaf_id: dsa fabric id 350 */ 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev) 352 { 353 u32 sbm_cfg_mib_en; 354 u32 i; 355 u32 reg; 356 u32 read_cnt; 357 358 /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */ 359 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 360 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 361 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); 362 } 363 364 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 365 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 366 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1); 367 } 368 369 /* waitint for all sbm enable finished */ 370 for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) { 371 read_cnt = 0; 372 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; 373 do { 374 udelay(1); 375 sbm_cfg_mib_en = dsaf_get_dev_bit( 376 dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S); 377 read_cnt++; 378 } while (sbm_cfg_mib_en == 0 && 379 read_cnt < DSAF_CFG_READ_CNT); 380 381 if (sbm_cfg_mib_en == 0) { 382 dev_err(dsaf_dev->dev, 383 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n", 384 dsaf_dev->ae_dev.name, i); 385 return -ENODEV; 386 } 387 } 388 389 return 0; 390 } 391 392 /** 393 * hns_dsaf_sbm_bp_wl_cfg - config sbm 394 * @dsaf_id: dsa fabric id 395 */ 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 397 { 398 u32 o_sbm_bp_cfg; 399 u32 reg; 400 u32 i; 401 402 /* XGE */ 403 for (i = 0; i < DSAF_XGE_NUM; i++) { 404 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 405 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 406 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M, 407 DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512); 408 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M, 409 DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 410 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M, 411 DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 412 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 413 414 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 415 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 416 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M, 417 DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 418 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M, 419 DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 420 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 421 422 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 423 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 424 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 425 DSAF_SBM_CFG2_SET_BUF_NUM_S, 104); 426 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 427 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128); 428 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 429 430 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 431 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 432 dsaf_set_field(o_sbm_bp_cfg, 433 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 434 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110); 435 dsaf_set_field(o_sbm_bp_cfg, 436 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 437 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160); 438 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 439 440 /* for no enable pfc mode */ 441 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 442 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 443 dsaf_set_field(o_sbm_bp_cfg, 444 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 445 DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128); 446 dsaf_set_field(o_sbm_bp_cfg, 447 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 448 DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192); 449 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 450 } 451 452 /* PPE */ 453 for (i = 0; i < DSAF_COMM_CHN; i++) { 454 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 455 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 456 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 457 DSAF_SBM_CFG2_SET_BUF_NUM_S, 10); 458 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 459 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12); 460 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 461 } 462 463 /* RoCEE */ 464 for (i = 0; i < DSAF_COMM_CHN; i++) { 465 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 466 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 467 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M, 468 DSAF_SBM_CFG2_SET_BUF_NUM_S, 2); 469 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M, 470 DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4); 471 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 472 } 473 } 474 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev) 476 { 477 u32 o_sbm_bp_cfg; 478 u32 reg; 479 u32 i; 480 481 /* XGE */ 482 for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) { 483 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; 484 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 485 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M, 486 DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256); 487 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M, 488 DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0); 489 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M, 490 DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0); 491 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 492 493 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; 494 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 495 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M, 496 DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0); 497 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M, 498 DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0); 499 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 500 501 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; 502 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 503 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M, 504 DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104); 505 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M, 506 DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128); 507 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 508 509 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; 510 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 511 dsaf_set_field(o_sbm_bp_cfg, 512 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M, 513 DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55); 514 dsaf_set_field(o_sbm_bp_cfg, 515 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M, 516 DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110); 517 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 518 519 /* for no enable pfc mode */ 520 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; 521 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 522 dsaf_set_field(o_sbm_bp_cfg, 523 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M, 524 DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128); 525 dsaf_set_field(o_sbm_bp_cfg, 526 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M, 527 DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192); 528 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 529 } 530 531 /* PPE */ 532 for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) { 533 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; 534 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 535 dsaf_set_field(o_sbm_bp_cfg, 536 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M, 537 DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2); 538 dsaf_set_field(o_sbm_bp_cfg, 539 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M, 540 DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3); 541 dsaf_set_field(o_sbm_bp_cfg, 542 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M, 543 DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52); 544 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 545 } 546 547 /* RoCEE */ 548 for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) { 549 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; 550 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); 551 dsaf_set_field(o_sbm_bp_cfg, 552 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M, 553 DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2); 554 dsaf_set_field(o_sbm_bp_cfg, 555 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M, 556 DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4); 557 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); 558 } 559 } 560 561 /** 562 * hns_dsaf_voq_bp_all_thrd_cfg - voq 563 * @dsaf_id: dsa fabric id 564 */ 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev) 566 { 567 u32 voq_bp_all_thrd; 568 u32 i; 569 570 for (i = 0; i < DSAF_VOQ_NUM; i++) { 571 voq_bp_all_thrd = dsaf_read_dev( 572 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i); 573 if (i < DSAF_XGE_NUM) { 574 dsaf_set_field(voq_bp_all_thrd, 575 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 576 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930); 577 dsaf_set_field(voq_bp_all_thrd, 578 DSAF_VOQ_BP_ALL_UPTHRD_M, 579 DSAF_VOQ_BP_ALL_UPTHRD_S, 950); 580 } else { 581 dsaf_set_field(voq_bp_all_thrd, 582 DSAF_VOQ_BP_ALL_DOWNTHRD_M, 583 DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220); 584 dsaf_set_field(voq_bp_all_thrd, 585 DSAF_VOQ_BP_ALL_UPTHRD_M, 586 DSAF_VOQ_BP_ALL_UPTHRD_S, 230); 587 } 588 dsaf_write_dev( 589 dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i, 590 voq_bp_all_thrd); 591 } 592 } 593 594 static void hns_dsaf_tbl_tcam_match_cfg( 595 struct dsaf_device *dsaf_dev, 596 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 597 { 598 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG, 599 ptbl_tcam_data->tbl_tcam_data_low); 600 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG, 601 ptbl_tcam_data->tbl_tcam_data_high); 602 } 603 604 /** 605 * hns_dsaf_tbl_tcam_data_cfg - tbl 606 * @dsaf_id: dsa fabric id 607 * @ptbl_tcam_data: addr 608 */ 609 static void hns_dsaf_tbl_tcam_data_cfg( 610 struct dsaf_device *dsaf_dev, 611 struct dsaf_tbl_tcam_data *ptbl_tcam_data) 612 { 613 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG, 614 ptbl_tcam_data->tbl_tcam_data_low); 615 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG, 616 ptbl_tcam_data->tbl_tcam_data_high); 617 } 618 619 /** 620 * dsaf_tbl_tcam_mcast_cfg - tbl 621 * @dsaf_id: dsa fabric id 622 * @ptbl_tcam_mcast: addr 623 */ 624 static void hns_dsaf_tbl_tcam_mcast_cfg( 625 struct dsaf_device *dsaf_dev, 626 struct dsaf_tbl_tcam_mcast_cfg *mcast) 627 { 628 u32 mcast_cfg4; 629 630 mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 631 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S, 632 mcast->tbl_mcast_item_vld); 633 dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S, 634 mcast->tbl_mcast_old_en); 635 dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M, 636 DSAF_TBL_MCAST_CFG4_VM128_112_S, 637 mcast->tbl_mcast_port_msk[4]); 638 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4); 639 640 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 641 mcast->tbl_mcast_port_msk[3]); 642 643 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 644 mcast->tbl_mcast_port_msk[2]); 645 646 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 647 mcast->tbl_mcast_port_msk[1]); 648 649 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 650 mcast->tbl_mcast_port_msk[0]); 651 } 652 653 /** 654 * hns_dsaf_tbl_tcam_ucast_cfg - tbl 655 * @dsaf_id: dsa fabric id 656 * @ptbl_tcam_ucast: addr 657 */ 658 static void hns_dsaf_tbl_tcam_ucast_cfg( 659 struct dsaf_device *dsaf_dev, 660 struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast) 661 { 662 u32 ucast_cfg1; 663 664 ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 665 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S, 666 tbl_tcam_ucast->tbl_ucast_mac_discard); 667 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S, 668 tbl_tcam_ucast->tbl_ucast_item_vld); 669 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S, 670 tbl_tcam_ucast->tbl_ucast_old_en); 671 dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S, 672 tbl_tcam_ucast->tbl_ucast_dvc); 673 dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 674 DSAF_TBL_UCAST_CFG1_OUT_PORT_S, 675 tbl_tcam_ucast->tbl_ucast_out_port); 676 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1); 677 } 678 679 /** 680 * hns_dsaf_tbl_line_cfg - tbl 681 * @dsaf_id: dsa fabric id 682 * @ptbl_lin: addr 683 */ 684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev, 685 struct dsaf_tbl_line_cfg *tbl_lin) 686 { 687 u32 tbl_line; 688 689 tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG); 690 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S, 691 tbl_lin->tbl_line_mac_discard); 692 dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S, 693 tbl_lin->tbl_line_dvc); 694 dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M, 695 DSAF_TBL_LINE_CFG_OUT_PORT_S, 696 tbl_lin->tbl_line_out_port); 697 dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line); 698 } 699 700 /** 701 * hns_dsaf_tbl_tcam_mcast_pul - tbl 702 * @dsaf_id: dsa fabric id 703 */ 704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev) 705 { 706 u32 o_tbl_pul; 707 708 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 709 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 710 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 711 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 712 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 713 } 714 715 /** 716 * hns_dsaf_tbl_line_pul - tbl 717 * @dsaf_id: dsa fabric id 718 */ 719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev) 720 { 721 u32 tbl_pul; 722 723 tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 724 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1); 725 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 726 dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0); 727 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul); 728 } 729 730 /** 731 * hns_dsaf_tbl_tcam_data_mcast_pul - tbl 732 * @dsaf_id: dsa fabric id 733 */ 734 static void hns_dsaf_tbl_tcam_data_mcast_pul( 735 struct dsaf_device *dsaf_dev) 736 { 737 u32 o_tbl_pul; 738 739 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 740 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 741 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1); 742 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 743 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 744 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0); 745 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 746 } 747 748 /** 749 * hns_dsaf_tbl_tcam_data_ucast_pul - tbl 750 * @dsaf_id: dsa fabric id 751 */ 752 static void hns_dsaf_tbl_tcam_data_ucast_pul( 753 struct dsaf_device *dsaf_dev) 754 { 755 u32 o_tbl_pul; 756 757 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG); 758 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1); 759 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1); 760 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 761 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0); 762 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0); 763 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul); 764 } 765 766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en) 767 { 768 if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev)) 769 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, 770 DSAF_CFG_MIX_MODE_S, !!en); 771 } 772 773 /** 774 * hns_dsaf_tbl_stat_en - tbl 775 * @dsaf_id: dsa fabric id 776 * @ptbl_stat_en: addr 777 */ 778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev) 779 { 780 u32 o_tbl_ctrl; 781 782 o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG); 783 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1); 784 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1); 785 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1); 786 dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1); 787 dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl); 788 } 789 790 /** 791 * hns_dsaf_rocee_bp_en - rocee back press enable 792 * @dsaf_id: dsa fabric id 793 */ 794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev) 795 { 796 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 797 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG, 798 DSAF_FC_XGE_TX_PAUSE_S, 1); 799 } 800 801 /* set msk for dsaf exception irq*/ 802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev, 803 u32 chnn_num, u32 mask_set) 804 { 805 dsaf_write_dev(dsaf_dev, 806 DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set); 807 } 808 809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev, 810 u32 chnn_num, u32 msk_set) 811 { 812 dsaf_write_dev(dsaf_dev, 813 DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set); 814 } 815 816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev, 817 u32 chnn, u32 msk_set) 818 { 819 dsaf_write_dev(dsaf_dev, 820 DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set); 821 } 822 823 static void 824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set) 825 { 826 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set); 827 } 828 829 /* clr dsaf exception irq*/ 830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev, 831 u32 chnn_num, u32 int_src) 832 { 833 dsaf_write_dev(dsaf_dev, 834 DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src); 835 } 836 837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev, 838 u32 chnn, u32 int_src) 839 { 840 dsaf_write_dev(dsaf_dev, 841 DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src); 842 } 843 844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev, 845 u32 chnn, u32 int_src) 846 { 847 dsaf_write_dev(dsaf_dev, 848 DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src); 849 } 850 851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev, 852 u32 int_src) 853 { 854 dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src); 855 } 856 857 /** 858 * hns_dsaf_single_line_tbl_cfg - INT 859 * @dsaf_id: dsa fabric id 860 * @address: 861 * @ptbl_line: 862 */ 863 static void hns_dsaf_single_line_tbl_cfg( 864 struct dsaf_device *dsaf_dev, 865 u32 address, struct dsaf_tbl_line_cfg *ptbl_line) 866 { 867 spin_lock_bh(&dsaf_dev->tcam_lock); 868 869 /*Write Addr*/ 870 hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address); 871 872 /*Write Line*/ 873 hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line); 874 875 /*Write Plus*/ 876 hns_dsaf_tbl_line_pul(dsaf_dev); 877 878 spin_unlock_bh(&dsaf_dev->tcam_lock); 879 } 880 881 /** 882 * hns_dsaf_tcam_uc_cfg - INT 883 * @dsaf_id: dsa fabric id 884 * @address, 885 * @ptbl_tcam_data, 886 */ 887 static void hns_dsaf_tcam_uc_cfg( 888 struct dsaf_device *dsaf_dev, u32 address, 889 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 890 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 891 { 892 spin_lock_bh(&dsaf_dev->tcam_lock); 893 894 /*Write Addr*/ 895 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 896 /*Write Tcam Data*/ 897 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 898 /*Write Tcam Ucast*/ 899 hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast); 900 /*Write Plus*/ 901 hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev); 902 903 spin_unlock_bh(&dsaf_dev->tcam_lock); 904 } 905 906 /** 907 * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc 908 * @dsaf_dev: dsa fabric device struct pointer 909 * @address: tcam index 910 * @ptbl_tcam_data: tcam data struct pointer 911 * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1 912 */ 913 static void hns_dsaf_tcam_mc_cfg( 914 struct dsaf_device *dsaf_dev, u32 address, 915 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 916 struct dsaf_tbl_tcam_data *ptbl_tcam_mask, 917 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 918 { 919 spin_lock_bh(&dsaf_dev->tcam_lock); 920 921 /*Write Addr*/ 922 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 923 /*Write Tcam Data*/ 924 hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data); 925 /*Write Tcam Mcast*/ 926 hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast); 927 /* Write Match Data */ 928 if (ptbl_tcam_mask) 929 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask); 930 931 /* Write Puls */ 932 hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev); 933 934 spin_unlock_bh(&dsaf_dev->tcam_lock); 935 } 936 937 /** 938 * hns_dsaf_tcam_mc_invld - INT 939 * @dsaf_id: dsa fabric id 940 * @address 941 */ 942 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address) 943 { 944 spin_lock_bh(&dsaf_dev->tcam_lock); 945 946 /*Write Addr*/ 947 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 948 949 /*write tcam mcast*/ 950 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0); 951 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0); 952 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0); 953 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0); 954 dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0); 955 956 /*Write Plus*/ 957 hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev); 958 959 spin_unlock_bh(&dsaf_dev->tcam_lock); 960 } 961 962 static void 963 hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr) 964 { 965 addr[0] = mac_key->high.bits.mac_0; 966 addr[1] = mac_key->high.bits.mac_1; 967 addr[2] = mac_key->high.bits.mac_2; 968 addr[3] = mac_key->high.bits.mac_3; 969 addr[4] = mac_key->low.bits.mac_4; 970 addr[5] = mac_key->low.bits.mac_5; 971 } 972 973 /** 974 * hns_dsaf_tcam_uc_get - INT 975 * @dsaf_id: dsa fabric id 976 * @address 977 * @ptbl_tcam_data 978 * @ptbl_tcam_ucast 979 */ 980 static void hns_dsaf_tcam_uc_get( 981 struct dsaf_device *dsaf_dev, u32 address, 982 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 983 struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast) 984 { 985 u32 tcam_read_data0; 986 u32 tcam_read_data4; 987 988 spin_lock_bh(&dsaf_dev->tcam_lock); 989 990 /*Write Addr*/ 991 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 992 993 /*read tcam item puls*/ 994 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 995 996 /*read tcam data*/ 997 ptbl_tcam_data->tbl_tcam_data_high 998 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 999 ptbl_tcam_data->tbl_tcam_data_low 1000 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1001 1002 /*read tcam mcast*/ 1003 tcam_read_data0 = dsaf_read_dev(dsaf_dev, 1004 DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1005 tcam_read_data4 = dsaf_read_dev(dsaf_dev, 1006 DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1007 1008 ptbl_tcam_ucast->tbl_ucast_item_vld 1009 = dsaf_get_bit(tcam_read_data4, 1010 DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1011 ptbl_tcam_ucast->tbl_ucast_old_en 1012 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1013 ptbl_tcam_ucast->tbl_ucast_mac_discard 1014 = dsaf_get_bit(tcam_read_data0, 1015 DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S); 1016 ptbl_tcam_ucast->tbl_ucast_out_port 1017 = dsaf_get_field(tcam_read_data0, 1018 DSAF_TBL_UCAST_CFG1_OUT_PORT_M, 1019 DSAF_TBL_UCAST_CFG1_OUT_PORT_S); 1020 ptbl_tcam_ucast->tbl_ucast_dvc 1021 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S); 1022 1023 spin_unlock_bh(&dsaf_dev->tcam_lock); 1024 } 1025 1026 /** 1027 * hns_dsaf_tcam_mc_get - INT 1028 * @dsaf_id: dsa fabric id 1029 * @address 1030 * @ptbl_tcam_data 1031 * @ptbl_tcam_ucast 1032 */ 1033 static void hns_dsaf_tcam_mc_get( 1034 struct dsaf_device *dsaf_dev, u32 address, 1035 struct dsaf_tbl_tcam_data *ptbl_tcam_data, 1036 struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast) 1037 { 1038 u32 data_tmp; 1039 1040 spin_lock_bh(&dsaf_dev->tcam_lock); 1041 1042 /*Write Addr*/ 1043 hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address); 1044 1045 /*read tcam item puls*/ 1046 hns_dsaf_tbl_tcam_load_pul(dsaf_dev); 1047 1048 /*read tcam data*/ 1049 ptbl_tcam_data->tbl_tcam_data_high = 1050 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 1051 ptbl_tcam_data->tbl_tcam_data_low = 1052 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 1053 1054 /*read tcam mcast*/ 1055 ptbl_tcam_mcast->tbl_mcast_port_msk[0] = 1056 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 1057 ptbl_tcam_mcast->tbl_mcast_port_msk[1] = 1058 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 1059 ptbl_tcam_mcast->tbl_mcast_port_msk[2] = 1060 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 1061 ptbl_tcam_mcast->tbl_mcast_port_msk[3] = 1062 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 1063 1064 data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 1065 ptbl_tcam_mcast->tbl_mcast_item_vld = 1066 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S); 1067 ptbl_tcam_mcast->tbl_mcast_old_en = 1068 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S); 1069 ptbl_tcam_mcast->tbl_mcast_port_msk[4] = 1070 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M, 1071 DSAF_TBL_MCAST_CFG4_VM128_112_S); 1072 1073 spin_unlock_bh(&dsaf_dev->tcam_lock); 1074 } 1075 1076 /** 1077 * hns_dsaf_tbl_line_init - INT 1078 * @dsaf_id: dsa fabric id 1079 */ 1080 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev) 1081 { 1082 u32 i; 1083 /* defaultly set all lineal mac table entry resulting discard */ 1084 struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} }; 1085 1086 for (i = 0; i < DSAF_LINE_SUM; i++) 1087 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line); 1088 } 1089 1090 /** 1091 * hns_dsaf_tbl_tcam_init - INT 1092 * @dsaf_id: dsa fabric id 1093 */ 1094 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev) 1095 { 1096 u32 i; 1097 struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} }; 1098 struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} }; 1099 1100 /*tcam tbl*/ 1101 for (i = 0; i < DSAF_TCAM_SUM; i++) 1102 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast); 1103 } 1104 1105 /** 1106 * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg 1107 * @mac_cb: mac contrl block 1108 */ 1109 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev, 1110 int mac_id, int tc_en) 1111 { 1112 dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en); 1113 } 1114 1115 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev, 1116 int mac_id, int tx_en, int rx_en) 1117 { 1118 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1119 if (!tx_en || !rx_en) 1120 dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n"); 1121 1122 return; 1123 } 1124 1125 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1126 DSAF_PFC_PAUSE_RX_EN_B, !!rx_en); 1127 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1128 DSAF_PFC_PAUSE_TX_EN_B, !!tx_en); 1129 } 1130 1131 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1132 u32 en) 1133 { 1134 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1135 if (!en) { 1136 dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n"); 1137 return -EINVAL; 1138 } 1139 } 1140 1141 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4, 1142 DSAF_MAC_PAUSE_RX_EN_B, !!en); 1143 1144 return 0; 1145 } 1146 1147 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id, 1148 u32 *en) 1149 { 1150 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1151 *en = 1; 1152 else 1153 *en = dsaf_get_dev_bit(dsaf_dev, 1154 DSAF_PAUSE_CFG_REG + mac_id * 4, 1155 DSAF_MAC_PAUSE_RX_EN_B); 1156 } 1157 1158 /** 1159 * hns_dsaf_tbl_tcam_init - INT 1160 * @dsaf_id: dsa fabric id 1161 * @dsaf_mode 1162 */ 1163 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev) 1164 { 1165 u32 i; 1166 u32 o_dsaf_cfg; 1167 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 1168 1169 o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG); 1170 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en); 1171 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode); 1172 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0); 1173 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0); 1174 dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0); 1175 dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg); 1176 1177 hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1); 1178 hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD); 1179 1180 /* set 22 queue per tx ppe engine, only used in switch mode */ 1181 hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE); 1182 1183 /* set promisc def queue id */ 1184 hns_dsaf_mix_def_qid_cfg(dsaf_dev); 1185 1186 /* set inner loopback queue id */ 1187 hns_dsaf_inner_qid_cfg(dsaf_dev); 1188 1189 /* in non switch mode, set all port to access mode */ 1190 hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN); 1191 1192 /*set dsaf pfc to 0 for parseing rx pause*/ 1193 for (i = 0; i < DSAF_COMM_CHN; i++) { 1194 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0); 1195 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1); 1196 } 1197 1198 /*msk and clr exception irqs */ 1199 for (i = 0; i < DSAF_COMM_CHN; i++) { 1200 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful); 1201 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful); 1202 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful); 1203 1204 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful); 1205 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful); 1206 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful); 1207 } 1208 hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful); 1209 hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful); 1210 } 1211 1212 /** 1213 * hns_dsaf_inode_init - INT 1214 * @dsaf_id: dsa fabric id 1215 */ 1216 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev) 1217 { 1218 u32 reg; 1219 u32 tc_cfg; 1220 u32 i; 1221 1222 if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE) 1223 tc_cfg = HNS_DSAF_I4TC_CFG; 1224 else 1225 tc_cfg = HNS_DSAF_I8TC_CFG; 1226 1227 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1228 for (i = 0; i < DSAF_INODE_NUM; i++) { 1229 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1230 dsaf_set_dev_field(dsaf_dev, reg, 1231 DSAF_INODE_IN_PORT_NUM_M, 1232 DSAF_INODE_IN_PORT_NUM_S, 1233 i % DSAF_XGE_NUM); 1234 } 1235 } else { 1236 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) { 1237 reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; 1238 dsaf_set_dev_field(dsaf_dev, reg, 1239 DSAF_INODE_IN_PORT_NUM_M, 1240 DSAF_INODE_IN_PORT_NUM_S, 0); 1241 dsaf_set_dev_field(dsaf_dev, reg, 1242 DSAFV2_INODE_IN_PORT1_NUM_M, 1243 DSAFV2_INODE_IN_PORT1_NUM_S, 1); 1244 dsaf_set_dev_field(dsaf_dev, reg, 1245 DSAFV2_INODE_IN_PORT2_NUM_M, 1246 DSAFV2_INODE_IN_PORT2_NUM_S, 2); 1247 dsaf_set_dev_field(dsaf_dev, reg, 1248 DSAFV2_INODE_IN_PORT3_NUM_M, 1249 DSAFV2_INODE_IN_PORT3_NUM_S, 3); 1250 dsaf_set_dev_field(dsaf_dev, reg, 1251 DSAFV2_INODE_IN_PORT4_NUM_M, 1252 DSAFV2_INODE_IN_PORT4_NUM_S, 4); 1253 dsaf_set_dev_field(dsaf_dev, reg, 1254 DSAFV2_INODE_IN_PORT5_NUM_M, 1255 DSAFV2_INODE_IN_PORT5_NUM_S, 5); 1256 } 1257 } 1258 for (i = 0; i < DSAF_INODE_NUM; i++) { 1259 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; 1260 dsaf_write_dev(dsaf_dev, reg, tc_cfg); 1261 } 1262 } 1263 1264 /** 1265 * hns_dsaf_sbm_init - INT 1266 * @dsaf_id: dsa fabric id 1267 */ 1268 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev) 1269 { 1270 u32 flag; 1271 u32 finish_msk; 1272 u32 cnt = 0; 1273 int ret; 1274 1275 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1276 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev); 1277 finish_msk = DSAF_SRAM_INIT_OVER_M; 1278 } else { 1279 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev); 1280 finish_msk = DSAFV2_SRAM_INIT_OVER_M; 1281 } 1282 1283 /* enable sbm chanel, disable sbm chanel shcut function*/ 1284 hns_dsaf_sbm_cfg(dsaf_dev); 1285 1286 /* enable sbm mib */ 1287 ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev); 1288 if (ret) { 1289 dev_err(dsaf_dev->dev, 1290 "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n", 1291 dsaf_dev->ae_dev.name, ret); 1292 return ret; 1293 } 1294 1295 /* enable sbm initial link sram */ 1296 hns_dsaf_sbm_link_sram_init_en(dsaf_dev); 1297 1298 do { 1299 usleep_range(200, 210);/*udelay(200);*/ 1300 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG, 1301 finish_msk, DSAF_SRAM_INIT_OVER_S); 1302 cnt++; 1303 } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) && 1304 cnt < DSAF_CFG_READ_CNT); 1305 1306 if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) { 1307 dev_err(dsaf_dev->dev, 1308 "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n", 1309 dsaf_dev->ae_dev.name, flag, cnt); 1310 return -ENODEV; 1311 } 1312 1313 hns_dsaf_rocee_bp_en(dsaf_dev); 1314 1315 return 0; 1316 } 1317 1318 /** 1319 * hns_dsaf_tbl_init - INT 1320 * @dsaf_id: dsa fabric id 1321 */ 1322 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev) 1323 { 1324 hns_dsaf_tbl_stat_en(dsaf_dev); 1325 1326 hns_dsaf_tbl_tcam_init(dsaf_dev); 1327 hns_dsaf_tbl_line_init(dsaf_dev); 1328 } 1329 1330 /** 1331 * hns_dsaf_voq_init - INT 1332 * @dsaf_id: dsa fabric id 1333 */ 1334 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev) 1335 { 1336 hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev); 1337 } 1338 1339 /** 1340 * hns_dsaf_init_hw - init dsa fabric hardware 1341 * @dsaf_dev: dsa fabric device struct pointer 1342 */ 1343 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev) 1344 { 1345 int ret; 1346 1347 dev_dbg(dsaf_dev->dev, 1348 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name); 1349 1350 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1351 mdelay(10); 1352 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1); 1353 1354 hns_dsaf_comm_init(dsaf_dev); 1355 1356 /*init XBAR_INODE*/ 1357 hns_dsaf_inode_init(dsaf_dev); 1358 1359 /*init SBM*/ 1360 ret = hns_dsaf_sbm_init(dsaf_dev); 1361 if (ret) 1362 return ret; 1363 1364 /*init TBL*/ 1365 hns_dsaf_tbl_init(dsaf_dev); 1366 1367 /*init VOQ*/ 1368 hns_dsaf_voq_init(dsaf_dev); 1369 1370 return 0; 1371 } 1372 1373 /** 1374 * hns_dsaf_remove_hw - uninit dsa fabric hardware 1375 * @dsaf_dev: dsa fabric device struct pointer 1376 */ 1377 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev) 1378 { 1379 /*reset*/ 1380 dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0); 1381 } 1382 1383 /** 1384 * hns_dsaf_init - init dsa fabric 1385 * @dsaf_dev: dsa fabric device struct pointer 1386 * retuen 0 - success , negative --fail 1387 */ 1388 static int hns_dsaf_init(struct dsaf_device *dsaf_dev) 1389 { 1390 struct dsaf_drv_priv *priv = 1391 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1392 u32 i; 1393 int ret; 1394 1395 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 1396 return 0; 1397 1398 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) 1399 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM; 1400 else 1401 dsaf_dev->tcam_max_num = 1402 DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; 1403 1404 spin_lock_init(&dsaf_dev->tcam_lock); 1405 ret = hns_dsaf_init_hw(dsaf_dev); 1406 if (ret) 1407 return ret; 1408 1409 /* malloc mem for tcam mac key(vlan+mac) */ 1410 priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM, 1411 sizeof(*priv->soft_mac_tbl))); 1412 if (!priv->soft_mac_tbl) { 1413 ret = -ENOMEM; 1414 goto remove_hw; 1415 } 1416 1417 /*all entry invall */ 1418 for (i = 0; i < DSAF_TCAM_SUM; i++) 1419 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX; 1420 1421 return 0; 1422 1423 remove_hw: 1424 hns_dsaf_remove_hw(dsaf_dev); 1425 return ret; 1426 } 1427 1428 /** 1429 * hns_dsaf_free - free dsa fabric 1430 * @dsaf_dev: dsa fabric device struct pointer 1431 */ 1432 static void hns_dsaf_free(struct dsaf_device *dsaf_dev) 1433 { 1434 struct dsaf_drv_priv *priv = 1435 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1436 1437 hns_dsaf_remove_hw(dsaf_dev); 1438 1439 /* free all mac mem */ 1440 vfree(priv->soft_mac_tbl); 1441 priv->soft_mac_tbl = NULL; 1442 } 1443 1444 /** 1445 * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry 1446 * @dsaf_dev: dsa fabric device struct pointer 1447 * @mac_key: mac entry struct pointer 1448 */ 1449 static u16 hns_dsaf_find_soft_mac_entry( 1450 struct dsaf_device *dsaf_dev, 1451 struct dsaf_drv_tbl_tcam_key *mac_key) 1452 { 1453 struct dsaf_drv_priv *priv = 1454 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1455 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1456 u32 i; 1457 1458 soft_mac_entry = priv->soft_mac_tbl; 1459 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { 1460 /* invall tab entry */ 1461 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) && 1462 (soft_mac_entry->tcam_key.high.val == mac_key->high.val) && 1463 (soft_mac_entry->tcam_key.low.val == mac_key->low.val)) 1464 /* return find result --soft index */ 1465 return soft_mac_entry->index; 1466 1467 soft_mac_entry++; 1468 } 1469 return DSAF_INVALID_ENTRY_IDX; 1470 } 1471 1472 /** 1473 * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry 1474 * @dsaf_dev: dsa fabric device struct pointer 1475 */ 1476 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev) 1477 { 1478 struct dsaf_drv_priv *priv = 1479 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1480 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1481 u32 i; 1482 1483 soft_mac_entry = priv->soft_mac_tbl; 1484 for (i = 0; i < dsaf_dev->tcam_max_num; i++) { 1485 /* inv all entry */ 1486 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX) 1487 /* return find result --soft index */ 1488 return i; 1489 1490 soft_mac_entry++; 1491 } 1492 return DSAF_INVALID_ENTRY_IDX; 1493 } 1494 1495 /** 1496 * hns_dsaf_set_mac_key - set mac key 1497 * @dsaf_dev: dsa fabric device struct pointer 1498 * @mac_key: tcam key pointer 1499 * @vlan_id: vlan id 1500 * @in_port_num: input port num 1501 * @addr: mac addr 1502 */ 1503 static void hns_dsaf_set_mac_key( 1504 struct dsaf_device *dsaf_dev, 1505 struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num, 1506 u8 *addr) 1507 { 1508 u8 port; 1509 1510 if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE) 1511 /*DSAF mode : in port id fixed 0*/ 1512 port = 0; 1513 else 1514 /*non-dsaf mode*/ 1515 port = in_port_num; 1516 1517 mac_key->high.bits.mac_0 = addr[0]; 1518 mac_key->high.bits.mac_1 = addr[1]; 1519 mac_key->high.bits.mac_2 = addr[2]; 1520 mac_key->high.bits.mac_3 = addr[3]; 1521 mac_key->low.bits.mac_4 = addr[4]; 1522 mac_key->low.bits.mac_5 = addr[5]; 1523 mac_key->low.bits.port_vlan = 0; 1524 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M, 1525 DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id); 1526 dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M, 1527 DSAF_TBL_TCAM_KEY_PORT_S, port); 1528 1529 mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan); 1530 } 1531 1532 /** 1533 * hns_dsaf_set_mac_uc_entry - set mac uc-entry 1534 * @dsaf_dev: dsa fabric device struct pointer 1535 * @mac_entry: uc-mac entry 1536 */ 1537 int hns_dsaf_set_mac_uc_entry( 1538 struct dsaf_device *dsaf_dev, 1539 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1540 { 1541 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1542 struct dsaf_drv_tbl_tcam_key mac_key; 1543 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1544 struct dsaf_drv_priv *priv = 1545 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1546 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1547 struct dsaf_tbl_tcam_data tcam_data; 1548 1549 /* mac addr check */ 1550 if (MAC_IS_ALL_ZEROS(mac_entry->addr) || 1551 MAC_IS_BROADCAST(mac_entry->addr) || 1552 MAC_IS_MULTICAST(mac_entry->addr)) { 1553 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n", 1554 dsaf_dev->ae_dev.name, mac_entry->addr); 1555 return -EINVAL; 1556 } 1557 1558 /* config key */ 1559 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1560 mac_entry->in_port_num, mac_entry->addr); 1561 1562 /* entry ie exist? */ 1563 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1564 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1565 /*if has not inv entry,find a empty entry */ 1566 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1567 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1568 /* has not empty,return error */ 1569 dev_err(dsaf_dev->dev, 1570 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1571 dsaf_dev->ae_dev.name, 1572 mac_key.high.val, mac_key.low.val); 1573 return -EINVAL; 1574 } 1575 } 1576 1577 dev_dbg(dsaf_dev->dev, 1578 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1579 dsaf_dev->ae_dev.name, mac_key.high.val, 1580 mac_key.low.val, entry_index); 1581 1582 /* config hardware entry */ 1583 mac_data.tbl_ucast_item_vld = 1; 1584 mac_data.tbl_ucast_mac_discard = 0; 1585 mac_data.tbl_ucast_old_en = 0; 1586 /* default config dvc to 0 */ 1587 mac_data.tbl_ucast_dvc = 0; 1588 mac_data.tbl_ucast_out_port = mac_entry->port_num; 1589 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 1590 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 1591 1592 hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data); 1593 1594 /* config software entry */ 1595 soft_mac_entry += entry_index; 1596 soft_mac_entry->index = entry_index; 1597 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1598 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1599 1600 return 0; 1601 } 1602 1603 int hns_dsaf_rm_mac_addr( 1604 struct dsaf_device *dsaf_dev, 1605 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1606 { 1607 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1608 struct dsaf_tbl_tcam_ucast_cfg mac_data; 1609 struct dsaf_drv_tbl_tcam_key mac_key; 1610 1611 /* mac addr check */ 1612 if (!is_valid_ether_addr(mac_entry->addr)) { 1613 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n", 1614 dsaf_dev->ae_dev.name, mac_entry->addr); 1615 return -EINVAL; 1616 } 1617 1618 /* config key */ 1619 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1620 mac_entry->in_port_num, mac_entry->addr); 1621 1622 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1623 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1624 /* can not find the tcam entry, return 0 */ 1625 dev_info(dsaf_dev->dev, 1626 "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n", 1627 dsaf_dev->ae_dev.name, 1628 mac_key.high.val, mac_key.low.val); 1629 return 0; 1630 } 1631 1632 dev_dbg(dsaf_dev->dev, 1633 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n", 1634 dsaf_dev->ae_dev.name, mac_key.high.val, 1635 mac_key.low.val, entry_index); 1636 1637 hns_dsaf_tcam_uc_get( 1638 dsaf_dev, entry_index, 1639 (struct dsaf_tbl_tcam_data *)&mac_key, 1640 &mac_data); 1641 1642 /* unicast entry not used locally should not clear */ 1643 if (mac_entry->port_num != mac_data.tbl_ucast_out_port) 1644 return -EFAULT; 1645 1646 return hns_dsaf_del_mac_entry(dsaf_dev, 1647 mac_entry->in_vlan_id, 1648 mac_entry->in_port_num, 1649 mac_entry->addr); 1650 } 1651 1652 static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev, 1653 u8 port_num, u8 *mask, u8 *addr) 1654 { 1655 if (MAC_IS_BROADCAST(addr)) 1656 memset(mask, 0xff, ETH_ALEN); 1657 else 1658 memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN); 1659 } 1660 1661 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src) 1662 { 1663 u16 *a = (u16 *)dst; 1664 const u16 *b = (const u16 *)src; 1665 1666 a[0] &= b[0]; 1667 a[1] &= b[1]; 1668 a[2] &= b[2]; 1669 } 1670 1671 /** 1672 * hns_dsaf_add_mac_mc_port - add mac mc-port 1673 * @dsaf_dev: dsa fabric device struct pointer 1674 * @mac_entry: mc-mac entry 1675 */ 1676 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev, 1677 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1678 { 1679 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1680 struct dsaf_drv_tbl_tcam_key mac_key; 1681 struct dsaf_drv_tbl_tcam_key mask_key; 1682 struct dsaf_tbl_tcam_data *pmask_key = NULL; 1683 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1684 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1685 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1686 struct dsaf_drv_tbl_tcam_key tmp_mac_key; 1687 struct dsaf_tbl_tcam_data tcam_data; 1688 u8 mc_addr[ETH_ALEN]; 1689 int mskid; 1690 1691 /*chechk mac addr */ 1692 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1693 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n", 1694 mac_entry->addr); 1695 return -EINVAL; 1696 } 1697 1698 ether_addr_copy(mc_addr, mac_entry->addr); 1699 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1700 u8 mc_mask[ETH_ALEN]; 1701 1702 /* prepare for key data setting */ 1703 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num, 1704 mc_mask, mac_entry->addr); 1705 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask); 1706 1707 /* config key mask */ 1708 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 1709 0x0, 1710 0xff, 1711 mc_mask); 1712 1713 mask_key.high.val = le32_to_cpu(mask_key.high.val); 1714 mask_key.low.val = le32_to_cpu(mask_key.low.val); 1715 1716 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key); 1717 } 1718 1719 /*config key */ 1720 hns_dsaf_set_mac_key( 1721 dsaf_dev, &mac_key, mac_entry->in_vlan_id, 1722 mac_entry->in_port_num, mc_addr); 1723 1724 memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg)); 1725 1726 /* check if the tcam is exist */ 1727 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1728 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1729 /*if hasnot , find a empty*/ 1730 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev); 1731 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1732 /*if hasnot empty, error*/ 1733 dev_err(dsaf_dev->dev, 1734 "set_uc_entry failed, %s Mac key(%#x:%#x)\n", 1735 dsaf_dev->ae_dev.name, mac_key.high.val, 1736 mac_key.low.val); 1737 return -EINVAL; 1738 } 1739 } else { 1740 /* if exist, add in */ 1741 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, 1742 &mac_data); 1743 1744 tmp_mac_key.high.val = 1745 le32_to_cpu(tcam_data.tbl_tcam_data_high); 1746 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low); 1747 } 1748 1749 /* config hardware entry */ 1750 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1751 mskid = mac_entry->port_num; 1752 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1753 mskid = mac_entry->port_num - 1754 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1755 } else { 1756 dev_err(dsaf_dev->dev, 1757 "%s,pnum(%d)error,key(%#x:%#x)\n", 1758 dsaf_dev->ae_dev.name, mac_entry->port_num, 1759 mac_key.high.val, mac_key.low.val); 1760 return -EINVAL; 1761 } 1762 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1); 1763 mac_data.tbl_mcast_old_en = 0; 1764 mac_data.tbl_mcast_item_vld = 1; 1765 1766 dev_dbg(dsaf_dev->dev, 1767 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1768 dsaf_dev->ae_dev.name, mac_key.high.val, 1769 mac_key.low.val, entry_index); 1770 1771 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 1772 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 1773 1774 /* config mc entry with mask */ 1775 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data, 1776 pmask_key, &mac_data); 1777 1778 /*config software entry */ 1779 soft_mac_entry += entry_index; 1780 soft_mac_entry->index = entry_index; 1781 soft_mac_entry->tcam_key.high.val = mac_key.high.val; 1782 soft_mac_entry->tcam_key.low.val = mac_key.low.val; 1783 1784 return 0; 1785 } 1786 1787 /** 1788 * hns_dsaf_del_mac_entry - del mac mc-port 1789 * @dsaf_dev: dsa fabric device struct pointer 1790 * @vlan_id: vlian id 1791 * @in_port_num: input port num 1792 * @addr : mac addr 1793 */ 1794 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id, 1795 u8 in_port_num, u8 *addr) 1796 { 1797 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1798 struct dsaf_drv_tbl_tcam_key mac_key; 1799 struct dsaf_drv_priv *priv = 1800 (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev); 1801 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1802 1803 /*check mac addr */ 1804 if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) { 1805 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n", 1806 addr); 1807 return -EINVAL; 1808 } 1809 1810 /*config key */ 1811 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr); 1812 1813 /*exist ?*/ 1814 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1815 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1816 /*not exist, error */ 1817 dev_err(dsaf_dev->dev, 1818 "del_mac_entry failed, %s Mac key(%#x:%#x)\n", 1819 dsaf_dev->ae_dev.name, 1820 mac_key.high.val, mac_key.low.val); 1821 return -EINVAL; 1822 } 1823 dev_dbg(dsaf_dev->dev, 1824 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n", 1825 dsaf_dev->ae_dev.name, mac_key.high.val, 1826 mac_key.low.val, entry_index); 1827 1828 /*do del opt*/ 1829 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1830 1831 /*del soft emtry */ 1832 soft_mac_entry += entry_index; 1833 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1834 1835 return 0; 1836 } 1837 1838 /** 1839 * hns_dsaf_del_mac_mc_port - del mac mc- port 1840 * @dsaf_dev: dsa fabric device struct pointer 1841 * @mac_entry: mac entry 1842 */ 1843 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev, 1844 struct dsaf_drv_mac_single_dest_entry *mac_entry) 1845 { 1846 u16 entry_index = DSAF_INVALID_ENTRY_IDX; 1847 struct dsaf_drv_tbl_tcam_key mac_key; 1848 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1849 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 1850 u16 vlan_id; 1851 u8 in_port_num; 1852 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1853 struct dsaf_tbl_tcam_data tcam_data; 1854 int mskid; 1855 const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0}; 1856 struct dsaf_drv_tbl_tcam_key mask_key, tmp_mac_key; 1857 struct dsaf_tbl_tcam_data *pmask_key = NULL; 1858 u8 mc_addr[ETH_ALEN]; 1859 1860 if (!(void *)mac_entry) { 1861 dev_err(dsaf_dev->dev, 1862 "hns_dsaf_del_mac_mc_port mac_entry is NULL\n"); 1863 return -EINVAL; 1864 } 1865 1866 /*check mac addr */ 1867 if (MAC_IS_ALL_ZEROS(mac_entry->addr)) { 1868 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n", 1869 mac_entry->addr); 1870 return -EINVAL; 1871 } 1872 1873 /* always mask vlan_id field */ 1874 ether_addr_copy(mc_addr, mac_entry->addr); 1875 1876 if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) { 1877 u8 mc_mask[ETH_ALEN]; 1878 1879 /* prepare for key data setting */ 1880 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num, 1881 mc_mask, mac_entry->addr); 1882 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask); 1883 1884 /* config key mask */ 1885 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask); 1886 1887 mask_key.high.val = le32_to_cpu(mask_key.high.val); 1888 mask_key.low.val = le32_to_cpu(mask_key.low.val); 1889 1890 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key); 1891 } 1892 1893 /* get key info */ 1894 vlan_id = mac_entry->in_vlan_id; 1895 in_port_num = mac_entry->in_port_num; 1896 1897 /* config key */ 1898 hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr); 1899 1900 /* check if the tcam entry is exist */ 1901 entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key); 1902 if (entry_index == DSAF_INVALID_ENTRY_IDX) { 1903 /*find none */ 1904 dev_err(dsaf_dev->dev, 1905 "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n", 1906 dsaf_dev->ae_dev.name, 1907 mac_key.high.val, mac_key.low.val); 1908 return -EINVAL; 1909 } 1910 1911 dev_dbg(dsaf_dev->dev, 1912 "del_mac_mc_port, %s key(%#x:%#x) index%d\n", 1913 dsaf_dev->ae_dev.name, mac_key.high.val, 1914 mac_key.low.val, entry_index); 1915 1916 /* read entry */ 1917 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data); 1918 1919 tmp_mac_key.high.val = le32_to_cpu(tcam_data.tbl_tcam_data_high); 1920 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low); 1921 1922 /*del the port*/ 1923 if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) { 1924 mskid = mac_entry->port_num; 1925 } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) { 1926 mskid = mac_entry->port_num - 1927 DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM; 1928 } else { 1929 dev_err(dsaf_dev->dev, 1930 "%s,pnum(%d)error,key(%#x:%#x)\n", 1931 dsaf_dev->ae_dev.name, mac_entry->port_num, 1932 mac_key.high.val, mac_key.low.val); 1933 return -EINVAL; 1934 } 1935 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0); 1936 1937 /*check non port, do del entry */ 1938 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 1939 sizeof(mac_data.tbl_mcast_port_msk))) { 1940 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index); 1941 1942 /* del soft entry */ 1943 soft_mac_entry += entry_index; 1944 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX; 1945 } else { /* not zero, just del port, update */ 1946 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val); 1947 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val); 1948 1949 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, 1950 &tcam_data, 1951 pmask_key, &mac_data); 1952 } 1953 1954 return 0; 1955 } 1956 1957 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id, 1958 u8 port_num) 1959 { 1960 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 1961 struct dsaf_drv_soft_mac_tbl *soft_mac_entry; 1962 struct dsaf_tbl_tcam_mcast_cfg mac_data; 1963 int ret = 0, i; 1964 1965 if (HNS_DSAF_IS_DEBUG(dsaf_dev)) 1966 return 0; 1967 1968 for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) { 1969 u8 addr[ETH_ALEN]; 1970 u8 port; 1971 1972 soft_mac_entry = priv->soft_mac_tbl + i; 1973 1974 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr); 1975 port = dsaf_get_field( 1976 soft_mac_entry->tcam_key.low.bits.port_vlan, 1977 DSAF_TBL_TCAM_KEY_PORT_M, 1978 DSAF_TBL_TCAM_KEY_PORT_S); 1979 /* check valid tcam mc entry */ 1980 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX && 1981 port == mac_id && 1982 is_multicast_ether_addr(addr) && 1983 !is_broadcast_ether_addr(addr)) { 1984 const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0}; 1985 struct dsaf_drv_mac_single_dest_entry mac_entry; 1986 1987 /* disable receiving of this multicast address for 1988 * the VF. 1989 */ 1990 ether_addr_copy(mac_entry.addr, addr); 1991 mac_entry.in_vlan_id = dsaf_get_field( 1992 soft_mac_entry->tcam_key.low.bits.port_vlan, 1993 DSAF_TBL_TCAM_KEY_VLAN_M, 1994 DSAF_TBL_TCAM_KEY_VLAN_S); 1995 mac_entry.in_port_num = mac_id; 1996 mac_entry.port_num = port_num; 1997 if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) { 1998 ret = -EINVAL; 1999 continue; 2000 } 2001 2002 /* disable receiving of this multicast address for 2003 * the mac port if all VF are disable 2004 */ 2005 hns_dsaf_tcam_mc_get(dsaf_dev, i, 2006 (struct dsaf_tbl_tcam_data *) 2007 (&soft_mac_entry->tcam_key), 2008 &mac_data); 2009 dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32], 2010 mac_id % 32, 0); 2011 if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk, 2012 sizeof(u32) * DSAF_PORT_MSK_NUM)) { 2013 mac_entry.port_num = mac_id; 2014 if (hns_dsaf_del_mac_mc_port(dsaf_dev, 2015 &mac_entry)) { 2016 ret = -EINVAL; 2017 continue; 2018 } 2019 } 2020 } 2021 } 2022 2023 return ret; 2024 } 2025 2026 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev, 2027 size_t sizeof_priv) 2028 { 2029 struct dsaf_device *dsaf_dev; 2030 2031 dsaf_dev = devm_kzalloc(dev, 2032 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL); 2033 if (unlikely(!dsaf_dev)) { 2034 dsaf_dev = ERR_PTR(-ENOMEM); 2035 } else { 2036 dsaf_dev->dev = dev; 2037 dev_set_drvdata(dev, dsaf_dev); 2038 } 2039 2040 return dsaf_dev; 2041 } 2042 2043 /** 2044 * hns_dsaf_free_dev - free dev mem 2045 * @dev: struct device pointer 2046 */ 2047 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev) 2048 { 2049 (void)dev_set_drvdata(dsaf_dev->dev, NULL); 2050 } 2051 2052 /** 2053 * dsaf_pfc_unit_cnt - set pfc unit count 2054 * @dsaf_id: dsa fabric id 2055 * @pport_rate: value array 2056 * @pdsaf_pfc_unit_cnt: value array 2057 */ 2058 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int mac_id, 2059 enum dsaf_port_rate_mode rate) 2060 { 2061 u32 unit_cnt; 2062 2063 switch (rate) { 2064 case DSAF_PORT_RATE_10000: 2065 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2066 break; 2067 case DSAF_PORT_RATE_1000: 2068 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2069 break; 2070 case DSAF_PORT_RATE_2500: 2071 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000; 2072 break; 2073 default: 2074 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE; 2075 } 2076 2077 dsaf_set_dev_field(dsaf_dev, 2078 (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id), 2079 DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S, 2080 unit_cnt); 2081 } 2082 2083 /** 2084 * dsaf_port_work_rate_cfg - fifo 2085 * @dsaf_id: dsa fabric id 2086 * @xge_ge_work_mode 2087 */ 2088 static void 2089 hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id, 2090 enum dsaf_port_rate_mode rate_mode) 2091 { 2092 u32 port_work_mode; 2093 2094 port_work_mode = dsaf_read_dev( 2095 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id); 2096 2097 if (rate_mode == DSAF_PORT_RATE_10000) 2098 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1); 2099 else 2100 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0); 2101 2102 dsaf_write_dev(dsaf_dev, 2103 DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id, 2104 port_work_mode); 2105 2106 hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode); 2107 } 2108 2109 /** 2110 * hns_dsaf_fix_mac_mode - dsaf modify mac mode 2111 * @mac_cb: mac contrl block 2112 */ 2113 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb) 2114 { 2115 enum dsaf_port_rate_mode mode; 2116 struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev; 2117 int mac_id = mac_cb->mac_id; 2118 2119 if (mac_cb->mac_type != HNAE_PORT_SERVICE) 2120 return; 2121 if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII) 2122 mode = DSAF_PORT_RATE_10000; 2123 else 2124 mode = DSAF_PORT_RATE_1000; 2125 2126 hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode); 2127 } 2128 2129 static u32 hns_dsaf_get_inode_prio_reg(int index) 2130 { 2131 int base_index, offset; 2132 u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG; 2133 2134 base_index = (index + 1) / DSAF_REG_PER_ZONE; 2135 offset = (index + 1) % DSAF_REG_PER_ZONE; 2136 2137 return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index + 2138 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset; 2139 } 2140 2141 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num) 2142 { 2143 struct dsaf_hw_stats *hw_stats 2144 = &dsaf_dev->hw_stats[node_num]; 2145 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2146 int i; 2147 u32 reg_tmp; 2148 2149 hw_stats->pad_drop += dsaf_read_dev(dsaf_dev, 2150 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2151 hw_stats->man_pkts += dsaf_read_dev(dsaf_dev, 2152 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num); 2153 hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev, 2154 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num); 2155 hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev, 2156 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num); 2157 2158 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2159 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2160 hw_stats->rx_pause_frame += 2161 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num); 2162 2163 hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev, 2164 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num); 2165 hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev, 2166 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num); 2167 hw_stats->crc_false += dsaf_read_dev(dsaf_dev, 2168 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2169 hw_stats->bp_drop += dsaf_read_dev(dsaf_dev, 2170 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2171 hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev, 2172 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num); 2173 hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev, 2174 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num); 2175 2176 hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev, 2177 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num); 2178 hw_stats->stp_drop += dsaf_read_dev(dsaf_dev, 2179 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num); 2180 2181 /* pfc pause frame statistics stored in dsaf inode*/ 2182 if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) { 2183 for (i = 0; i < DSAF_PRIO_NR; i++) { 2184 reg_tmp = hns_dsaf_get_inode_prio_reg(i); 2185 hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev, 2186 reg_tmp + 0x4 * (u64)node_num); 2187 hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev, 2188 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG + 2189 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i + 2190 0xF0 * (u64)node_num); 2191 } 2192 } 2193 hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev, 2194 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num); 2195 } 2196 2197 /** 2198 *hns_dsaf_get_regs - dump dsaf regs 2199 *@dsaf_dev: dsaf device 2200 *@data:data for value of regs 2201 */ 2202 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data) 2203 { 2204 u32 i = 0; 2205 u32 j; 2206 u32 *p = data; 2207 u32 reg_tmp; 2208 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2209 2210 /* dsaf common registers */ 2211 p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG); 2212 p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG); 2213 p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG); 2214 p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG); 2215 p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG); 2216 p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG); 2217 p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG); 2218 p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG); 2219 p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG); 2220 2221 p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4); 2222 p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4); 2223 p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2224 p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2225 p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2226 p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4); 2227 p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4); 2228 p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4); 2229 p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4); 2230 p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4); 2231 p[19] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4); 2232 p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4); 2233 p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4); 2234 p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4); 2235 p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4); 2236 2237 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2238 p[24 + i] = dsaf_read_dev(ddev, 2239 DSAF_SW_PORT_TYPE_0_REG + i * 4); 2240 2241 p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4); 2242 2243 for (i = 0; i < DSAF_SW_PORT_NUM; i++) 2244 p[33 + i] = dsaf_read_dev(ddev, 2245 DSAF_PORT_DEF_VLAN_0_REG + i * 4); 2246 2247 for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++) 2248 p[41 + i] = dsaf_read_dev(ddev, 2249 DSAF_VM_DEF_VLAN_0_REG + i * 4); 2250 2251 /* dsaf inode registers */ 2252 p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG); 2253 2254 p[171] = dsaf_read_dev(ddev, 2255 DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80); 2256 2257 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2258 j = i * DSAF_COMM_CHN + port; 2259 p[172 + i] = dsaf_read_dev(ddev, 2260 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80); 2261 p[175 + i] = dsaf_read_dev(ddev, 2262 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80); 2263 p[178 + i] = dsaf_read_dev(ddev, 2264 DSAF_INODE_BP_STATUS_0_REG + j * 0x80); 2265 p[181 + i] = dsaf_read_dev(ddev, 2266 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80); 2267 p[184 + i] = dsaf_read_dev(ddev, 2268 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80); 2269 p[187 + i] = dsaf_read_dev(ddev, 2270 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80); 2271 p[190 + i] = dsaf_read_dev(ddev, 2272 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80); 2273 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG : 2274 DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG; 2275 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80); 2276 p[196 + i] = dsaf_read_dev(ddev, 2277 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80); 2278 p[199 + i] = dsaf_read_dev(ddev, 2279 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80); 2280 p[202 + i] = dsaf_read_dev(ddev, 2281 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80); 2282 p[205 + i] = dsaf_read_dev(ddev, 2283 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80); 2284 p[208 + i] = dsaf_read_dev(ddev, 2285 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80); 2286 p[211 + i] = dsaf_read_dev(ddev, 2287 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80); 2288 p[214 + i] = dsaf_read_dev(ddev, 2289 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80); 2290 p[217 + i] = dsaf_read_dev(ddev, 2291 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4); 2292 p[220 + i] = dsaf_read_dev(ddev, 2293 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4); 2294 p[223 + i] = dsaf_read_dev(ddev, 2295 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4); 2296 p[224 + i] = dsaf_read_dev(ddev, 2297 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4); 2298 } 2299 2300 p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4); 2301 2302 for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) { 2303 j = i * DSAF_COMM_CHN + port; 2304 p[228 + i] = dsaf_read_dev(ddev, 2305 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4); 2306 } 2307 2308 p[231] = dsaf_read_dev(ddev, 2309 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4); 2310 2311 /* dsaf inode registers */ 2312 for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) { 2313 j = i * DSAF_COMM_CHN + port; 2314 p[232 + i] = dsaf_read_dev(ddev, 2315 DSAF_SBM_CFG_REG_0_REG + j * 0x80); 2316 p[235 + i] = dsaf_read_dev(ddev, 2317 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80); 2318 p[238 + i] = dsaf_read_dev(ddev, 2319 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80); 2320 p[241 + i] = dsaf_read_dev(ddev, 2321 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80); 2322 p[244 + i] = dsaf_read_dev(ddev, 2323 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80); 2324 p[245 + i] = dsaf_read_dev(ddev, 2325 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80); 2326 p[248 + i] = dsaf_read_dev(ddev, 2327 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80); 2328 p[251 + i] = dsaf_read_dev(ddev, 2329 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80); 2330 p[254 + i] = dsaf_read_dev(ddev, 2331 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80); 2332 p[257 + i] = dsaf_read_dev(ddev, 2333 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80); 2334 p[260 + i] = dsaf_read_dev(ddev, 2335 DSAF_SBM_INER_ST_0_REG + j * 0x80); 2336 p[263 + i] = dsaf_read_dev(ddev, 2337 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80); 2338 p[266 + i] = dsaf_read_dev(ddev, 2339 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80); 2340 p[269 + i] = dsaf_read_dev(ddev, 2341 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80); 2342 p[272 + i] = dsaf_read_dev(ddev, 2343 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80); 2344 p[275 + i] = dsaf_read_dev(ddev, 2345 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80); 2346 p[278 + i] = dsaf_read_dev(ddev, 2347 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80); 2348 p[281 + i] = dsaf_read_dev(ddev, 2349 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80); 2350 p[284 + i] = dsaf_read_dev(ddev, 2351 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80); 2352 p[287 + i] = dsaf_read_dev(ddev, 2353 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80); 2354 p[290 + i] = dsaf_read_dev(ddev, 2355 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80); 2356 p[293 + i] = dsaf_read_dev(ddev, 2357 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80); 2358 p[296 + i] = dsaf_read_dev(ddev, 2359 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80); 2360 p[299 + i] = dsaf_read_dev(ddev, 2361 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80); 2362 p[302 + i] = dsaf_read_dev(ddev, 2363 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80); 2364 p[305 + i] = dsaf_read_dev(ddev, 2365 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80); 2366 p[308 + i] = dsaf_read_dev(ddev, 2367 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80); 2368 } 2369 2370 /* dsaf onode registers */ 2371 for (i = 0; i < DSAF_XOD_NUM; i++) { 2372 p[311 + i] = dsaf_read_dev(ddev, 2373 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90); 2374 p[319 + i] = dsaf_read_dev(ddev, 2375 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90); 2376 p[327 + i] = dsaf_read_dev(ddev, 2377 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90); 2378 p[335 + i] = dsaf_read_dev(ddev, 2379 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90); 2380 p[343 + i] = dsaf_read_dev(ddev, 2381 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90); 2382 p[351 + i] = dsaf_read_dev(ddev, 2383 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90); 2384 } 2385 2386 p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90); 2387 p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90); 2388 p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90); 2389 2390 for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) { 2391 j = i * DSAF_COMM_CHN + port; 2392 p[362 + i] = dsaf_read_dev(ddev, 2393 DSAF_XOD_GNT_L_0_REG + j * 0x90); 2394 p[365 + i] = dsaf_read_dev(ddev, 2395 DSAF_XOD_GNT_H_0_REG + j * 0x90); 2396 p[368 + i] = dsaf_read_dev(ddev, 2397 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90); 2398 p[371 + i] = dsaf_read_dev(ddev, 2399 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90); 2400 p[374 + i] = dsaf_read_dev(ddev, 2401 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90); 2402 p[377 + i] = dsaf_read_dev(ddev, 2403 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90); 2404 p[380 + i] = dsaf_read_dev(ddev, 2405 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90); 2406 p[383 + i] = dsaf_read_dev(ddev, 2407 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90); 2408 p[386 + i] = dsaf_read_dev(ddev, 2409 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90); 2410 p[389 + i] = dsaf_read_dev(ddev, 2411 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90); 2412 } 2413 2414 p[392] = dsaf_read_dev(ddev, 2415 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90); 2416 p[393] = dsaf_read_dev(ddev, 2417 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90); 2418 p[394] = dsaf_read_dev(ddev, 2419 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90); 2420 p[395] = dsaf_read_dev(ddev, 2421 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90); 2422 p[396] = dsaf_read_dev(ddev, 2423 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90); 2424 p[397] = dsaf_read_dev(ddev, 2425 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90); 2426 p[398] = dsaf_read_dev(ddev, 2427 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90); 2428 p[399] = dsaf_read_dev(ddev, 2429 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90); 2430 p[400] = dsaf_read_dev(ddev, 2431 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90); 2432 p[401] = dsaf_read_dev(ddev, 2433 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90); 2434 p[402] = dsaf_read_dev(ddev, 2435 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90); 2436 p[403] = dsaf_read_dev(ddev, 2437 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90); 2438 p[404] = dsaf_read_dev(ddev, 2439 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90); 2440 2441 /* dsaf voq registers */ 2442 for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) { 2443 j = (i * DSAF_COMM_CHN + port) * 0x90; 2444 p[405 + i] = dsaf_read_dev(ddev, 2445 DSAF_VOQ_ECC_INVERT_EN_0_REG + j); 2446 p[408 + i] = dsaf_read_dev(ddev, 2447 DSAF_VOQ_SRAM_PKT_NUM_0_REG + j); 2448 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j); 2449 p[414 + i] = dsaf_read_dev(ddev, 2450 DSAF_VOQ_OUT_PKT_NUM_0_REG + j); 2451 p[417 + i] = dsaf_read_dev(ddev, 2452 DSAF_VOQ_ECC_ERR_ADDR_0_REG + j); 2453 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j); 2454 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j); 2455 p[426 + i] = dsaf_read_dev(ddev, 2456 DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j); 2457 p[429 + i] = dsaf_read_dev(ddev, 2458 DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j); 2459 p[432 + i] = dsaf_read_dev(ddev, 2460 DSAF_VOQ_PPE_XOD_REQ_0_REG + j); 2461 p[435 + i] = dsaf_read_dev(ddev, 2462 DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j); 2463 p[438 + i] = dsaf_read_dev(ddev, 2464 DSAF_VOQ_BP_ALL_THRD_0_REG + j); 2465 } 2466 2467 /* dsaf tbl registers */ 2468 p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG); 2469 p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG); 2470 p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG); 2471 p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG); 2472 p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG); 2473 p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG); 2474 p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG); 2475 p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG); 2476 p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG); 2477 p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG); 2478 p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG); 2479 p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG); 2480 p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG); 2481 p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG); 2482 p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG); 2483 p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG); 2484 p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG); 2485 p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG); 2486 p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG); 2487 p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG); 2488 p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG); 2489 p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG); 2490 p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG); 2491 2492 for (i = 0; i < DSAF_SW_PORT_NUM; i++) { 2493 j = i * 0x8; 2494 p[464 + 2 * i] = dsaf_read_dev(ddev, 2495 DSAF_TBL_DA0_MIS_INFO1_0_REG + j); 2496 p[465 + 2 * i] = dsaf_read_dev(ddev, 2497 DSAF_TBL_DA0_MIS_INFO0_0_REG + j); 2498 } 2499 2500 p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG); 2501 p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG); 2502 p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG); 2503 p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG); 2504 p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG); 2505 p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG); 2506 p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG); 2507 p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG); 2508 p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG); 2509 p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG); 2510 p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG); 2511 p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG); 2512 2513 /* dsaf other registers */ 2514 p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4); 2515 p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4); 2516 p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4); 2517 p[495] = dsaf_read_dev(ddev, 2518 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4); 2519 p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4); 2520 p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4); 2521 2522 if (!is_ver1) 2523 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4); 2524 2525 /* mark end of dsaf regs */ 2526 for (i = 499; i < 504; i++) 2527 p[i] = 0xdddddddd; 2528 } 2529 2530 static char *hns_dsaf_get_node_stats_strings(char *data, int node, 2531 struct dsaf_device *dsaf_dev) 2532 { 2533 char *buff = data; 2534 int i; 2535 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2536 2537 snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node); 2538 buff += ETH_GSTRING_LEN; 2539 snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node); 2540 buff += ETH_GSTRING_LEN; 2541 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node); 2542 buff += ETH_GSTRING_LEN; 2543 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node); 2544 buff += ETH_GSTRING_LEN; 2545 snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node); 2546 buff += ETH_GSTRING_LEN; 2547 snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node); 2548 buff += ETH_GSTRING_LEN; 2549 snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node); 2550 buff += ETH_GSTRING_LEN; 2551 snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node); 2552 buff += ETH_GSTRING_LEN; 2553 snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node); 2554 buff += ETH_GSTRING_LEN; 2555 snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node); 2556 buff += ETH_GSTRING_LEN; 2557 snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node); 2558 buff += ETH_GSTRING_LEN; 2559 snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node); 2560 buff += ETH_GSTRING_LEN; 2561 snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node); 2562 buff += ETH_GSTRING_LEN; 2563 if (node < DSAF_SERVICE_NW_NUM && !is_ver1) { 2564 for (i = 0; i < DSAF_PRIO_NR; i++) { 2565 snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2566 ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts", 2567 node, i); 2568 snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR, 2569 ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts", 2570 node, i); 2571 buff += ETH_GSTRING_LEN; 2572 } 2573 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN; 2574 } 2575 snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node); 2576 buff += ETH_GSTRING_LEN; 2577 2578 return buff; 2579 } 2580 2581 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data, 2582 int node_num) 2583 { 2584 u64 *p = data; 2585 int i; 2586 struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num]; 2587 bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver); 2588 2589 p[0] = hw_stats->pad_drop; 2590 p[1] = hw_stats->man_pkts; 2591 p[2] = hw_stats->rx_pkts; 2592 p[3] = hw_stats->rx_pkt_id; 2593 p[4] = hw_stats->rx_pause_frame; 2594 p[5] = hw_stats->release_buf_num; 2595 p[6] = hw_stats->sbm_drop; 2596 p[7] = hw_stats->crc_false; 2597 p[8] = hw_stats->bp_drop; 2598 p[9] = hw_stats->rslt_drop; 2599 p[10] = hw_stats->local_addr_false; 2600 p[11] = hw_stats->vlan_drop; 2601 p[12] = hw_stats->stp_drop; 2602 if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) { 2603 for (i = 0; i < DSAF_PRIO_NR; i++) { 2604 p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i]; 2605 p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i]; 2606 } 2607 p[29] = hw_stats->tx_pkts; 2608 return &p[30]; 2609 } 2610 2611 p[13] = hw_stats->tx_pkts; 2612 return &p[14]; 2613 } 2614 2615 /** 2616 *hns_dsaf_get_stats - get dsaf statistic 2617 *@ddev: dsaf device 2618 *@data:statistic value 2619 *@port: port num 2620 */ 2621 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port) 2622 { 2623 u64 *p = data; 2624 int node_num = port; 2625 2626 /* for ge/xge node info */ 2627 p = hns_dsaf_get_node_stats(ddev, p, node_num); 2628 2629 /* for ppe node info */ 2630 node_num = port + DSAF_PPE_INODE_BASE; 2631 (void)hns_dsaf_get_node_stats(ddev, p, node_num); 2632 } 2633 2634 /** 2635 *hns_dsaf_get_sset_count - get dsaf string set count 2636 *@stringset: type of values in data 2637 *return dsaf string name count 2638 */ 2639 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset) 2640 { 2641 bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver); 2642 2643 if (stringset == ETH_SS_STATS) { 2644 if (is_ver1) 2645 return DSAF_STATIC_NUM; 2646 else 2647 return DSAF_V2_STATIC_NUM; 2648 } 2649 return 0; 2650 } 2651 2652 /** 2653 *hns_dsaf_get_strings - get dsaf string set 2654 *@stringset:srting set index 2655 *@data:strings name value 2656 *@port:port index 2657 */ 2658 void hns_dsaf_get_strings(int stringset, u8 *data, int port, 2659 struct dsaf_device *dsaf_dev) 2660 { 2661 char *buff = (char *)data; 2662 int node = port; 2663 2664 if (stringset != ETH_SS_STATS) 2665 return; 2666 2667 /* for ge/xge node info */ 2668 buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2669 2670 /* for ppe node info */ 2671 node = port + DSAF_PPE_INODE_BASE; 2672 (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev); 2673 } 2674 2675 /** 2676 *hns_dsaf_get_sset_count - get dsaf regs count 2677 *return dsaf regs count 2678 */ 2679 int hns_dsaf_get_regs_count(void) 2680 { 2681 return DSAF_DUMP_REGS_NUM; 2682 } 2683 2684 /* Reserve the last TCAM entry for promisc support */ 2685 #define dsaf_promisc_tcam_entry(port) \ 2686 (DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM + (port)) 2687 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev, 2688 u32 port, bool enable) 2689 { 2690 struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev); 2691 struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl; 2692 u16 entry_index; 2693 struct dsaf_drv_tbl_tcam_key tbl_tcam_data, tbl_tcam_mask; 2694 struct dsaf_tbl_tcam_mcast_cfg mac_data = {0}; 2695 2696 if ((AE_IS_VER1(dsaf_dev->dsaf_ver)) || HNS_DSAF_IS_DEBUG(dsaf_dev)) 2697 return; 2698 2699 /* find the tcam entry index for promisc */ 2700 entry_index = dsaf_promisc_tcam_entry(port); 2701 2702 memset(&tbl_tcam_data, 0, sizeof(tbl_tcam_data)); 2703 memset(&tbl_tcam_mask, 0, sizeof(tbl_tcam_mask)); 2704 2705 /* config key mask */ 2706 if (enable) { 2707 dsaf_set_field(tbl_tcam_data.low.bits.port_vlan, 2708 DSAF_TBL_TCAM_KEY_PORT_M, 2709 DSAF_TBL_TCAM_KEY_PORT_S, port); 2710 dsaf_set_field(tbl_tcam_mask.low.bits.port_vlan, 2711 DSAF_TBL_TCAM_KEY_PORT_M, 2712 DSAF_TBL_TCAM_KEY_PORT_S, 0xf); 2713 2714 /* SUB_QID */ 2715 dsaf_set_bit(mac_data.tbl_mcast_port_msk[0], 2716 DSAF_SERVICE_NW_NUM, true); 2717 mac_data.tbl_mcast_item_vld = true; /* item_vld bit */ 2718 } else { 2719 mac_data.tbl_mcast_item_vld = false; /* item_vld bit */ 2720 } 2721 2722 dev_dbg(dsaf_dev->dev, 2723 "set_promisc_entry, %s Mac key(%#x:%#x) entry_index%d\n", 2724 dsaf_dev->ae_dev.name, tbl_tcam_data.high.val, 2725 tbl_tcam_data.low.val, entry_index); 2726 2727 /* config promisc entry with mask */ 2728 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, 2729 (struct dsaf_tbl_tcam_data *)&tbl_tcam_data, 2730 (struct dsaf_tbl_tcam_data *)&tbl_tcam_mask, 2731 &mac_data); 2732 2733 /* config software entry */ 2734 soft_mac_entry += entry_index; 2735 soft_mac_entry->index = enable ? entry_index : DSAF_INVALID_ENTRY_IDX; 2736 } 2737 2738 /** 2739 * dsaf_probe - probo dsaf dev 2740 * @pdev: dasf platform device 2741 * retuen 0 - success , negative --fail 2742 */ 2743 static int hns_dsaf_probe(struct platform_device *pdev) 2744 { 2745 struct dsaf_device *dsaf_dev; 2746 int ret; 2747 2748 dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv)); 2749 if (IS_ERR(dsaf_dev)) { 2750 ret = PTR_ERR(dsaf_dev); 2751 dev_err(&pdev->dev, 2752 "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret); 2753 return ret; 2754 } 2755 2756 ret = hns_dsaf_get_cfg(dsaf_dev); 2757 if (ret) 2758 goto free_dev; 2759 2760 ret = hns_dsaf_init(dsaf_dev); 2761 if (ret) 2762 goto free_dev; 2763 2764 ret = hns_mac_init(dsaf_dev); 2765 if (ret) 2766 goto uninit_dsaf; 2767 2768 ret = hns_ppe_init(dsaf_dev); 2769 if (ret) 2770 goto uninit_mac; 2771 2772 ret = hns_dsaf_ae_init(dsaf_dev); 2773 if (ret) 2774 goto uninit_ppe; 2775 2776 return 0; 2777 2778 uninit_ppe: 2779 hns_ppe_uninit(dsaf_dev); 2780 2781 uninit_mac: 2782 hns_mac_uninit(dsaf_dev); 2783 2784 uninit_dsaf: 2785 hns_dsaf_free(dsaf_dev); 2786 2787 free_dev: 2788 hns_dsaf_free_dev(dsaf_dev); 2789 2790 return ret; 2791 } 2792 2793 /** 2794 * dsaf_remove - remove dsaf dev 2795 * @pdev: dasf platform device 2796 */ 2797 static int hns_dsaf_remove(struct platform_device *pdev) 2798 { 2799 struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev); 2800 2801 hns_dsaf_ae_uninit(dsaf_dev); 2802 2803 hns_ppe_uninit(dsaf_dev); 2804 2805 hns_mac_uninit(dsaf_dev); 2806 2807 hns_dsaf_free(dsaf_dev); 2808 2809 hns_dsaf_free_dev(dsaf_dev); 2810 2811 return 0; 2812 } 2813 2814 static const struct of_device_id g_dsaf_match[] = { 2815 {.compatible = "hisilicon,hns-dsaf-v1"}, 2816 {.compatible = "hisilicon,hns-dsaf-v2"}, 2817 {} 2818 }; 2819 MODULE_DEVICE_TABLE(of, g_dsaf_match); 2820 2821 static struct platform_driver g_dsaf_driver = { 2822 .probe = hns_dsaf_probe, 2823 .remove = hns_dsaf_remove, 2824 .driver = { 2825 .name = DSAF_DRV_NAME, 2826 .of_match_table = g_dsaf_match, 2827 .acpi_match_table = hns_dsaf_acpi_match, 2828 }, 2829 }; 2830 2831 module_platform_driver(g_dsaf_driver); 2832 2833 /** 2834 * hns_dsaf_roce_reset - reset dsaf and roce 2835 * @dsaf_fwnode: Pointer to framework node for the dasf 2836 * @enable: false - request reset , true - drop reset 2837 * retuen 0 - success , negative -fail 2838 */ 2839 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset) 2840 { 2841 struct dsaf_device *dsaf_dev; 2842 struct platform_device *pdev; 2843 u32 mp; 2844 u32 sl; 2845 u32 credit; 2846 int i; 2847 const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 2848 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 2849 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 2850 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 2851 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 2852 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 2853 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 2854 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 2855 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 2856 }; 2857 const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 2858 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 2859 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 2860 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 2861 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 2862 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 2863 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 2864 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 2865 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 2866 }; 2867 2868 /* find the platform device corresponding to fwnode */ 2869 if (is_of_node(dsaf_fwnode)) { 2870 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode)); 2871 } else if (is_acpi_device_node(dsaf_fwnode)) { 2872 pdev = hns_dsaf_find_platform_device(dsaf_fwnode); 2873 } else { 2874 pr_err("fwnode is neither OF or ACPI type\n"); 2875 return -EINVAL; 2876 } 2877 2878 /* check if we were a success in fetching pdev */ 2879 if (!pdev) { 2880 pr_err("couldn't find platform device for node\n"); 2881 return -ENODEV; 2882 } 2883 2884 /* retrieve the dsaf_device from the driver data */ 2885 dsaf_dev = dev_get_drvdata(&pdev->dev); 2886 if (!dsaf_dev) { 2887 dev_err(&pdev->dev, "dsaf_dev is NULL\n"); 2888 return -ENODEV; 2889 } 2890 2891 /* now, make sure we are running on compatible SoC */ 2892 if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 2893 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n", 2894 dsaf_dev->ae_dev.name); 2895 return -ENODEV; 2896 } 2897 2898 /* do reset or de-reset according to the flag */ 2899 if (!dereset) { 2900 /* reset rocee-channels in dsaf and rocee */ 2901 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 2902 false); 2903 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false); 2904 } else { 2905 /* configure dsaf tx roce correspond to port map and sl map */ 2906 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG); 2907 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 2908 dsaf_set_field(mp, 7 << i * 3, i * 3, 2909 port_map[i][DSAF_ROCE_6PORT_MODE]); 2910 dsaf_set_field(mp, 3 << i * 3, i * 3, 0); 2911 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp); 2912 2913 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG); 2914 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 2915 dsaf_set_field(sl, 3 << i * 2, i * 2, 2916 sl_map[i][DSAF_ROCE_6PORT_MODE]); 2917 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl); 2918 2919 /* de-reset rocee-channels in dsaf and rocee */ 2920 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 2921 true); 2922 msleep(SRST_TIME_INTERVAL); 2923 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true); 2924 2925 /* enable dsaf channel rocee credit */ 2926 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG); 2927 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0); 2928 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 2929 2930 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1); 2931 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 2932 } 2933 return 0; 2934 } 2935 EXPORT_SYMBOL(hns_dsaf_roce_reset); 2936 2937 MODULE_LICENSE("GPL"); 2938 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 2939 MODULE_DESCRIPTION("HNS DSAF driver"); 2940 MODULE_VERSION(DSAF_MOD_VERSION); 2941