1 /* 2 * Copyright (c) 2014-2015 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/of_mdio.h> 12 #include "hns_dsaf_main.h" 13 #include "hns_dsaf_mac.h" 14 #include "hns_dsaf_gmac.h" 15 16 static const struct mac_stats_string g_gmac_stats_string[] = { 17 {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)}, 18 {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)}, 19 {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)}, 20 {"gmac_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)}, 21 {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)}, 22 {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)}, 23 {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)}, 24 {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)}, 25 {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)}, 26 {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)}, 27 {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)}, 28 {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)}, 29 {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)}, 30 {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)}, 31 {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)}, 32 {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)}, 33 {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)}, 34 {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)}, 35 {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)}, 36 {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)}, 37 {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)}, 38 {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)}, 39 {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)}, 40 {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_pkts)}, 41 {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_bytes)}, 42 {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)}, 43 {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)}, 44 {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)}, 45 46 {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)}, 47 {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)}, 48 {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)}, 49 {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)}, 50 {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)}, 51 {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)}, 52 {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)}, 53 {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)}, 54 {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)}, 55 {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)}, 56 {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)}, 57 {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)}, 58 {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)}, 59 {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)}, 60 {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)}, 61 {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)}, 62 {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)} 63 }; 64 65 static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode) 66 { 67 struct mac_driver *drv = (struct mac_driver *)mac_drv; 68 69 /*enable GE rX/tX */ 70 if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX)) 71 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1); 72 73 if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX)) 74 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1); 75 } 76 77 static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode) 78 { 79 struct mac_driver *drv = (struct mac_driver *)mac_drv; 80 81 /*disable GE rX/tX */ 82 if ((mode == MAC_COMM_MODE_TX) || (mode == MAC_COMM_MODE_RX_AND_TX)) 83 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0); 84 85 if ((mode == MAC_COMM_MODE_RX) || (mode == MAC_COMM_MODE_RX_AND_TX)) 86 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0); 87 } 88 89 /* hns_gmac_get_en - get port enable 90 * @mac_drv:mac device 91 * @rx:rx enable 92 * @tx:tx enable 93 */ 94 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx) 95 { 96 struct mac_driver *drv = (struct mac_driver *)mac_drv; 97 u32 porten; 98 99 porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG); 100 *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B); 101 *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B); 102 } 103 104 static void hns_gmac_free(void *mac_drv) 105 { 106 struct mac_driver *drv = (struct mac_driver *)mac_drv; 107 struct dsaf_device *dsaf_dev 108 = (struct dsaf_device *)dev_get_drvdata(drv->dev); 109 110 u32 mac_id = drv->mac_id; 111 112 dsaf_dev->misc_op->ge_srst(dsaf_dev, mac_id, 0); 113 } 114 115 static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval) 116 { 117 struct mac_driver *drv = (struct mac_driver *)mac_drv; 118 119 dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M, 120 GMAC_FC_TX_TIMER_S, newval); 121 } 122 123 static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval) 124 { 125 struct mac_driver *drv = (struct mac_driver *)mac_drv; 126 127 *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG, 128 GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S); 129 } 130 131 static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval) 132 { 133 struct mac_driver *drv = (struct mac_driver *)mac_drv; 134 135 dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG, 136 GMAC_PAUSE_EN_RX_FDFC_B, !!newval); 137 } 138 139 static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval) 140 { 141 struct mac_driver *drv = (struct mac_driver *)mac_drv; 142 143 dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M, 144 GMAC_MAX_FRM_SIZE_S, newval); 145 146 dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M, 147 GMAC_MAX_FRM_SIZE_S, newval); 148 } 149 150 static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval) 151 { 152 u32 tx_ctrl; 153 struct mac_driver *drv = (struct mac_driver *)mac_drv; 154 155 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); 156 dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval); 157 dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval); 158 dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); 159 } 160 161 static void hns_gmac_config_an_mode(void *mac_drv, u8 newval) 162 { 163 struct mac_driver *drv = (struct mac_driver *)mac_drv; 164 165 dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG, 166 GMAC_TX_AN_EN_B, !!newval); 167 } 168 169 static void hns_gmac_tx_loop_pkt_dis(void *mac_drv) 170 { 171 u32 tx_loop_pkt_pri; 172 struct mac_driver *drv = (struct mac_driver *)mac_drv; 173 174 tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG); 175 dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1); 176 dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0); 177 dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri); 178 } 179 180 static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval) 181 { 182 struct mac_driver *drv = (struct mac_driver *)mac_drv; 183 184 dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, 185 GMAC_DUPLEX_TYPE_B, !!newval); 186 } 187 188 static void hns_gmac_get_duplex_type(void *mac_drv, 189 enum hns_gmac_duplex_mdoe *duplex_mode) 190 { 191 struct mac_driver *drv = (struct mac_driver *)mac_drv; 192 193 *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit( 194 drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B); 195 } 196 197 static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode) 198 { 199 struct mac_driver *drv = (struct mac_driver *)mac_drv; 200 201 *port_mode = (enum hns_port_mode)dsaf_get_dev_field( 202 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S); 203 } 204 205 static void hns_gmac_port_mode_get(void *mac_drv, 206 struct hns_gmac_port_mode_cfg *port_mode) 207 { 208 u32 tx_ctrl; 209 u32 recv_ctrl; 210 struct mac_driver *drv = (struct mac_driver *)mac_drv; 211 212 port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field( 213 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S); 214 215 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); 216 recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG); 217 218 port_mode->max_frm_size = 219 dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, 220 GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S); 221 port_mode->short_runts_thr = 222 dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG, 223 GMAC_SHORT_RUNTS_THR_M, 224 GMAC_SHORT_RUNTS_THR_S); 225 226 port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B); 227 port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B); 228 port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B); 229 230 port_mode->runt_pkt_en = 231 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B); 232 port_mode->strip_pad_en = 233 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B); 234 } 235 236 static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en, 237 u32 tx_pause_en) 238 { 239 u32 pause_en; 240 struct mac_driver *drv = (struct mac_driver *)mac_drv; 241 242 pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); 243 dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en); 244 dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en); 245 dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en); 246 } 247 248 static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en, 249 u32 *tx_pause_en) 250 { 251 u32 pause_en; 252 struct mac_driver *drv = (struct mac_driver *)mac_drv; 253 254 pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); 255 256 *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B); 257 *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B); 258 } 259 260 static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed, 261 u32 full_duplex) 262 { 263 struct mac_driver *drv = (struct mac_driver *)mac_drv; 264 265 dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG, 266 GMAC_DUPLEX_TYPE_B, !!full_duplex); 267 268 switch (speed) { 269 case MAC_SPEED_10: 270 dsaf_set_dev_field( 271 drv, GMAC_PORT_MODE_REG, 272 GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6); 273 break; 274 case MAC_SPEED_100: 275 dsaf_set_dev_field( 276 drv, GMAC_PORT_MODE_REG, 277 GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7); 278 break; 279 case MAC_SPEED_1000: 280 dsaf_set_dev_field( 281 drv, GMAC_PORT_MODE_REG, 282 GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8); 283 break; 284 default: 285 dev_err(drv->dev, 286 "hns_gmac_adjust_link fail, speed%d mac%d\n", 287 speed, drv->mac_id); 288 return -EINVAL; 289 } 290 291 return 0; 292 } 293 294 static void hns_gmac_set_uc_match(void *mac_drv, u16 en) 295 { 296 struct mac_driver *drv = mac_drv; 297 298 dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG, 299 GMAC_UC_MATCH_EN_B, !en); 300 dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG, 301 GMAC_ADDR_EN_B, !en); 302 } 303 304 static void hns_gmac_set_promisc(void *mac_drv, u8 en) 305 { 306 struct mac_driver *drv = mac_drv; 307 308 if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG) 309 hns_gmac_set_uc_match(mac_drv, en); 310 } 311 312 static void hns_gmac_init(void *mac_drv) 313 { 314 u32 port; 315 struct mac_driver *drv = (struct mac_driver *)mac_drv; 316 struct dsaf_device *dsaf_dev 317 = (struct dsaf_device *)dev_get_drvdata(drv->dev); 318 319 port = drv->mac_id; 320 321 dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0); 322 mdelay(10); 323 dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1); 324 mdelay(10); 325 hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX); 326 hns_gmac_tx_loop_pkt_dis(mac_drv); 327 if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG) 328 hns_gmac_set_uc_match(mac_drv, 0); 329 330 hns_gmac_config_pad_and_crc(mac_drv, 1); 331 332 dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG, 333 GMAC_MODE_CHANGE_EB_B, 1); 334 335 /* reduce gmac tx water line to avoid gmac hang-up 336 * in speed 100M and duplex half. 337 */ 338 dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK, 339 GMAC_TX_WATER_LINE_SHIFT, 8); 340 } 341 342 static void hns_gmac_update_stats(void *mac_drv) 343 { 344 struct mac_hw_stats *hw_stats = NULL; 345 struct mac_driver *drv = (struct mac_driver *)mac_drv; 346 347 hw_stats = &drv->mac_cb->hw_stats; 348 349 /* RX */ 350 hw_stats->rx_good_bytes 351 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG); 352 hw_stats->rx_bad_bytes 353 += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG); 354 hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG); 355 hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG); 356 hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG); 357 hw_stats->rx_64bytes 358 += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG); 359 hw_stats->rx_65to127 360 += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG); 361 hw_stats->rx_128to255 362 += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG); 363 hw_stats->rx_256to511 364 += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG); 365 hw_stats->rx_512to1023 366 += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG); 367 hw_stats->rx_1024to1518 368 += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG); 369 hw_stats->rx_1519tomax 370 += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG); 371 hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG); 372 hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG); 373 hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG); 374 hw_stats->rx_align_err 375 += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG); 376 hw_stats->rx_oversize 377 += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG); 378 hw_stats->rx_jabber_err 379 += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG); 380 hw_stats->rx_pfc_tc0 381 += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG); 382 hw_stats->rx_unknown_ctrl 383 += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG); 384 hw_stats->rx_long_err 385 += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG); 386 hw_stats->rx_minto64 387 += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG); 388 hw_stats->rx_under_min 389 += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG); 390 hw_stats->rx_filter_pkts 391 += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG); 392 hw_stats->rx_filter_bytes 393 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG); 394 hw_stats->rx_fifo_overrun_err 395 += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG); 396 hw_stats->rx_len_err 397 += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG); 398 hw_stats->rx_comma_err 399 += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG); 400 401 /* TX */ 402 hw_stats->tx_good_bytes 403 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG); 404 hw_stats->tx_bad_bytes 405 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG); 406 hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG); 407 hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG); 408 hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG); 409 hw_stats->tx_64bytes 410 += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG); 411 hw_stats->tx_65to127 412 += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG); 413 hw_stats->tx_128to255 414 += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG); 415 hw_stats->tx_256to511 416 += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG); 417 hw_stats->tx_512to1023 418 += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG); 419 hw_stats->tx_1024to1518 420 += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG); 421 hw_stats->tx_1519tomax 422 += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG); 423 hw_stats->tx_jabber_err 424 += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG); 425 hw_stats->tx_underrun_err 426 += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG); 427 hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG); 428 hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG); 429 hw_stats->tx_pfc_tc0 430 += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG); 431 } 432 433 static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr) 434 { 435 struct mac_driver *drv = (struct mac_driver *)mac_drv; 436 437 u32 high_val = mac_addr[1] | (mac_addr[0] << 8); 438 439 u32 low_val = mac_addr[5] | (mac_addr[4] << 8) 440 | (mac_addr[3] << 16) | (mac_addr[2] << 24); 441 442 u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG); 443 u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B); 444 445 dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val); 446 dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG, 447 high_val | (sta_addr_en << GMAC_ADDR_EN_B)); 448 } 449 450 static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode, 451 u8 enable) 452 { 453 struct mac_driver *drv = (struct mac_driver *)mac_drv; 454 455 switch (loop_mode) { 456 case MAC_INTERNALLOOP_MAC: 457 dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B, 458 !!enable); 459 break; 460 default: 461 dev_err(drv->dev, "loop_mode error\n"); 462 return -EINVAL; 463 } 464 465 return 0; 466 } 467 468 static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info) 469 { 470 enum hns_gmac_duplex_mdoe duplex; 471 enum hns_port_mode speed; 472 u32 rx_pause; 473 u32 tx_pause; 474 u32 rx; 475 u32 tx; 476 u16 fc_tx_timer; 477 struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 }; 478 479 hns_gmac_port_mode_get(mac_drv, &port_mode); 480 mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable; 481 mac_info->auto_neg = port_mode.an_enable; 482 483 hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer); 484 mac_info->tx_pause_time = fc_tx_timer; 485 486 hns_gmac_get_en(mac_drv, &rx, &tx); 487 mac_info->port_en = rx && tx; 488 489 hns_gmac_get_duplex_type(mac_drv, &duplex); 490 mac_info->duplex = duplex; 491 492 hns_gmac_get_port_mode(mac_drv, &speed); 493 switch (speed) { 494 case GMAC_10M_SGMII: 495 mac_info->speed = MAC_SPEED_10; 496 break; 497 case GMAC_100M_SGMII: 498 mac_info->speed = MAC_SPEED_100; 499 break; 500 case GMAC_1000M_SGMII: 501 mac_info->speed = MAC_SPEED_1000; 502 break; 503 default: 504 mac_info->speed = 0; 505 break; 506 } 507 508 hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause); 509 mac_info->rx_pause_en = rx_pause; 510 mac_info->tx_pause_en = tx_pause; 511 } 512 513 static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable) 514 { 515 struct mac_driver *drv = (struct mac_driver *)mac_drv; 516 517 *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG, 518 GMAC_TX_AN_EN_B); 519 } 520 521 static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat) 522 { 523 struct mac_driver *drv = (struct mac_driver *)mac_drv; 524 525 *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG, 526 GMAC_AN_NEG_STAT_RX_SYNC_OK_B); 527 } 528 529 static void hns_gmac_get_regs(void *mac_drv, void *data) 530 { 531 u32 *regs = data; 532 int i; 533 struct mac_driver *drv = (struct mac_driver *)mac_drv; 534 535 /* base config registers */ 536 regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG); 537 regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG); 538 regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG); 539 regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG); 540 regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG); 541 regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG); 542 regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG); 543 regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG); 544 regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG); 545 regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG); 546 regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG); 547 regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG); 548 regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG); 549 regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG); 550 regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); 551 regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG); 552 regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG); 553 554 /* rx static registers */ 555 regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG); 556 regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG); 557 regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG); 558 regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG); 559 regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG); 560 regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG); 561 regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG); 562 regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG); 563 regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG); 564 regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG); 565 regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG); 566 regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG); 567 regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG); 568 regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG); 569 regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG); 570 regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG); 571 regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG); 572 regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG); 573 regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG); 574 regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG); 575 regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG); 576 regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG); 577 regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG); 578 regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG); 579 regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG); 580 581 /* tx static registers */ 582 regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG); 583 regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG); 584 regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG); 585 regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG); 586 regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG); 587 regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG); 588 regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG); 589 regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG); 590 regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG); 591 regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG); 592 regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG); 593 regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG); 594 regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG); 595 regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG); 596 regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG); 597 regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG); 598 regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG); 599 600 regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME); 601 regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG); 602 regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG); 603 regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG); 604 regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG); 605 regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG); 606 regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG); 607 regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG); 608 regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG); 609 regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG); 610 regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG); 611 regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG); 612 613 regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG); 614 regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG); 615 regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG); 616 regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG); 617 regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG); 618 regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG); 619 regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG); 620 regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG); 621 regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG); 622 regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG); 623 regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG); 624 regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG); 625 regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG); 626 regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG); 627 regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG); 628 regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG); 629 regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG); 630 regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG); 631 632 /* mark end of mac regs */ 633 for (i = 89; i < 96; i++) 634 regs[i] = 0xaaaaaaaa; 635 } 636 637 static void hns_gmac_get_stats(void *mac_drv, u64 *data) 638 { 639 u32 i; 640 u64 *buf = data; 641 struct mac_driver *drv = (struct mac_driver *)mac_drv; 642 struct mac_hw_stats *hw_stats = NULL; 643 644 hw_stats = &drv->mac_cb->hw_stats; 645 646 for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) { 647 buf[i] = DSAF_STATS_READ(hw_stats, 648 g_gmac_stats_string[i].offset); 649 } 650 } 651 652 static void hns_gmac_get_strings(u32 stringset, u8 *data) 653 { 654 char *buff = (char *)data; 655 u32 i; 656 657 if (stringset != ETH_SS_STATS) 658 return; 659 660 for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) { 661 snprintf(buff, ETH_GSTRING_LEN, "%s", 662 g_gmac_stats_string[i].desc); 663 buff = buff + ETH_GSTRING_LEN; 664 } 665 } 666 667 static int hns_gmac_get_sset_count(int stringset) 668 { 669 if (stringset == ETH_SS_STATS) 670 return ARRAY_SIZE(g_gmac_stats_string); 671 672 return 0; 673 } 674 675 static int hns_gmac_get_regs_count(void) 676 { 677 return ETH_GMAC_DUMP_NUM; 678 } 679 680 void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param) 681 { 682 struct mac_driver *mac_drv; 683 684 mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL); 685 if (!mac_drv) 686 return NULL; 687 688 mac_drv->mac_init = hns_gmac_init; 689 mac_drv->mac_enable = hns_gmac_enable; 690 mac_drv->mac_disable = hns_gmac_disable; 691 mac_drv->mac_free = hns_gmac_free; 692 mac_drv->adjust_link = hns_gmac_adjust_link; 693 mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames; 694 mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length; 695 mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg; 696 697 mac_drv->mac_id = mac_param->mac_id; 698 mac_drv->mac_mode = mac_param->mac_mode; 699 mac_drv->io_base = mac_param->vaddr; 700 mac_drv->dev = mac_param->dev; 701 mac_drv->mac_cb = mac_cb; 702 703 mac_drv->set_mac_addr = hns_gmac_set_mac_addr; 704 mac_drv->set_an_mode = hns_gmac_config_an_mode; 705 mac_drv->config_loopback = hns_gmac_config_loopback; 706 mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc; 707 mac_drv->config_half_duplex = hns_gmac_set_duplex_type; 708 mac_drv->set_rx_ignore_pause_frames = hns_gmac_set_rx_auto_pause_frames; 709 mac_drv->get_info = hns_gmac_get_info; 710 mac_drv->autoneg_stat = hns_gmac_autoneg_stat; 711 mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg; 712 mac_drv->get_link_status = hns_gmac_get_link_status; 713 mac_drv->get_regs = hns_gmac_get_regs; 714 mac_drv->get_regs_count = hns_gmac_get_regs_count; 715 mac_drv->get_ethtool_stats = hns_gmac_get_stats; 716 mac_drv->get_sset_count = hns_gmac_get_sset_count; 717 mac_drv->get_strings = hns_gmac_get_strings; 718 mac_drv->update_stats = hns_gmac_update_stats; 719 mac_drv->set_promiscuous = hns_gmac_set_promisc; 720 721 return (void *)mac_drv; 722 } 723