1 /* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/stddef.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mii.h> 32 #include <linux/phy.h> 33 #include <linux/workqueue.h> 34 #include <linux/of_mdio.h> 35 #include <linux/of_net.h> 36 #include <linux/of_platform.h> 37 38 #include <asm/uaccess.h> 39 #include <asm/irq.h> 40 #include <asm/io.h> 41 #include <asm/immap_qe.h> 42 #include <asm/qe.h> 43 #include <asm/ucc.h> 44 #include <asm/ucc_fast.h> 45 #include <asm/machdep.h> 46 47 #include "ucc_geth.h" 48 49 #undef DEBUG 50 51 #define ugeth_printk(level, format, arg...) \ 52 printk(level format "\n", ## arg) 53 54 #define ugeth_dbg(format, arg...) \ 55 ugeth_printk(KERN_DEBUG , format , ## arg) 56 57 #ifdef UGETH_VERBOSE_DEBUG 58 #define ugeth_vdbg ugeth_dbg 59 #else 60 #define ugeth_vdbg(fmt, args...) do { } while (0) 61 #endif /* UGETH_VERBOSE_DEBUG */ 62 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 63 64 65 static DEFINE_SPINLOCK(ugeth_lock); 66 67 static struct { 68 u32 msg_enable; 69 } debug = { -1 }; 70 71 module_param_named(debug, debug.msg_enable, int, 0); 72 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 73 74 static struct ucc_geth_info ugeth_primary_info = { 75 .uf_info = { 76 .bd_mem_part = MEM_PART_SYSTEM, 77 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 78 .max_rx_buf_length = 1536, 79 /* adjusted at startup if max-speed 1000 */ 80 .urfs = UCC_GETH_URFS_INIT, 81 .urfet = UCC_GETH_URFET_INIT, 82 .urfset = UCC_GETH_URFSET_INIT, 83 .utfs = UCC_GETH_UTFS_INIT, 84 .utfet = UCC_GETH_UTFET_INIT, 85 .utftt = UCC_GETH_UTFTT_INIT, 86 .ufpt = 256, 87 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 88 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 89 .tenc = UCC_FAST_TX_ENCODING_NRZ, 90 .renc = UCC_FAST_RX_ENCODING_NRZ, 91 .tcrc = UCC_FAST_16_BIT_CRC, 92 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 93 }, 94 .numQueuesTx = 1, 95 .numQueuesRx = 1, 96 .extendedFilteringChainPointer = ((uint32_t) NULL), 97 .typeorlen = 3072 /*1536 */ , 98 .nonBackToBackIfgPart1 = 0x40, 99 .nonBackToBackIfgPart2 = 0x60, 100 .miminumInterFrameGapEnforcement = 0x50, 101 .backToBackInterFrameGap = 0x60, 102 .mblinterval = 128, 103 .nortsrbytetime = 5, 104 .fracsiz = 1, 105 .strictpriorityq = 0xff, 106 .altBebTruncation = 0xa, 107 .excessDefer = 1, 108 .maxRetransmission = 0xf, 109 .collisionWindow = 0x37, 110 .receiveFlowControl = 1, 111 .transmitFlowControl = 1, 112 .maxGroupAddrInHash = 4, 113 .maxIndAddrInHash = 4, 114 .prel = 7, 115 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 116 .minFrameLength = 64, 117 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 118 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 119 .vlantype = 0x8100, 120 .ecamptr = ((uint32_t) NULL), 121 .eventRegMask = UCCE_OTHER, 122 .pausePeriod = 0xf000, 123 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 124 .bdRingLenTx = { 125 TX_BD_RING_LEN, 126 TX_BD_RING_LEN, 127 TX_BD_RING_LEN, 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN}, 133 134 .bdRingLenRx = { 135 RX_BD_RING_LEN, 136 RX_BD_RING_LEN, 137 RX_BD_RING_LEN, 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN}, 143 144 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 145 .largestexternallookupkeysize = 146 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 147 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 148 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 150 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 151 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 152 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 153 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 154 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 155 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 156 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 157 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 158 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 159 }; 160 161 static struct ucc_geth_info ugeth_info[8]; 162 163 #ifdef DEBUG 164 static void mem_disp(u8 *addr, int size) 165 { 166 u8 *i; 167 int size16Aling = (size >> 4) << 4; 168 int size4Aling = (size >> 2) << 2; 169 int notAlign = 0; 170 if (size % 16) 171 notAlign = 1; 172 173 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 174 printk("0x%08x: %08x %08x %08x %08x\r\n", 175 (u32) i, 176 *((u32 *) (i)), 177 *((u32 *) (i + 4)), 178 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 179 if (notAlign == 1) 180 printk("0x%08x: ", (u32) i); 181 for (; (u32) i < (u32) addr + size4Aling; i += 4) 182 printk("%08x ", *((u32 *) (i))); 183 for (; (u32) i < (u32) addr + size; i++) 184 printk("%02x", *((i))); 185 if (notAlign == 1) 186 printk("\r\n"); 187 } 188 #endif /* DEBUG */ 189 190 static struct list_head *dequeue(struct list_head *lh) 191 { 192 unsigned long flags; 193 194 spin_lock_irqsave(&ugeth_lock, flags); 195 if (!list_empty(lh)) { 196 struct list_head *node = lh->next; 197 list_del(node); 198 spin_unlock_irqrestore(&ugeth_lock, flags); 199 return node; 200 } else { 201 spin_unlock_irqrestore(&ugeth_lock, flags); 202 return NULL; 203 } 204 } 205 206 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 207 u8 __iomem *bd) 208 { 209 struct sk_buff *skb; 210 211 skb = netdev_alloc_skb(ugeth->ndev, 212 ugeth->ug_info->uf_info.max_rx_buf_length + 213 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 214 if (!skb) 215 return NULL; 216 217 /* We need the data buffer to be aligned properly. We will reserve 218 * as many bytes as needed to align the data properly 219 */ 220 skb_reserve(skb, 221 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 222 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 223 1))); 224 225 out_be32(&((struct qe_bd __iomem *)bd)->buf, 226 dma_map_single(ugeth->dev, 227 skb->data, 228 ugeth->ug_info->uf_info.max_rx_buf_length + 229 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 230 DMA_FROM_DEVICE)); 231 232 out_be32((u32 __iomem *)bd, 233 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 234 235 return skb; 236 } 237 238 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 239 { 240 u8 __iomem *bd; 241 u32 bd_status; 242 struct sk_buff *skb; 243 int i; 244 245 bd = ugeth->p_rx_bd_ring[rxQ]; 246 i = 0; 247 248 do { 249 bd_status = in_be32((u32 __iomem *)bd); 250 skb = get_new_skb(ugeth, bd); 251 252 if (!skb) /* If can not allocate data buffer, 253 abort. Cleanup will be elsewhere */ 254 return -ENOMEM; 255 256 ugeth->rx_skbuff[rxQ][i] = skb; 257 258 /* advance the BD pointer */ 259 bd += sizeof(struct qe_bd); 260 i++; 261 } while (!(bd_status & R_W)); 262 263 return 0; 264 } 265 266 static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 267 u32 *p_start, 268 u8 num_entries, 269 u32 thread_size, 270 u32 thread_alignment, 271 unsigned int risc, 272 int skip_page_for_first_entry) 273 { 274 u32 init_enet_offset; 275 u8 i; 276 int snum; 277 278 for (i = 0; i < num_entries; i++) { 279 if ((snum = qe_get_snum()) < 0) { 280 if (netif_msg_ifup(ugeth)) 281 pr_err("Can not get SNUM\n"); 282 return snum; 283 } 284 if ((i == 0) && skip_page_for_first_entry) 285 /* First entry of Rx does not have page */ 286 init_enet_offset = 0; 287 else { 288 init_enet_offset = 289 qe_muram_alloc(thread_size, thread_alignment); 290 if (IS_ERR_VALUE(init_enet_offset)) { 291 if (netif_msg_ifup(ugeth)) 292 pr_err("Can not allocate DPRAM memory\n"); 293 qe_put_snum((u8) snum); 294 return -ENOMEM; 295 } 296 } 297 *(p_start++) = 298 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 299 | risc; 300 } 301 302 return 0; 303 } 304 305 static int return_init_enet_entries(struct ucc_geth_private *ugeth, 306 u32 *p_start, 307 u8 num_entries, 308 unsigned int risc, 309 int skip_page_for_first_entry) 310 { 311 u32 init_enet_offset; 312 u8 i; 313 int snum; 314 315 for (i = 0; i < num_entries; i++) { 316 u32 val = *p_start; 317 318 /* Check that this entry was actually valid -- 319 needed in case failed in allocations */ 320 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 321 snum = 322 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 323 ENET_INIT_PARAM_SNUM_SHIFT; 324 qe_put_snum((u8) snum); 325 if (!((i == 0) && skip_page_for_first_entry)) { 326 /* First entry of Rx does not have page */ 327 init_enet_offset = 328 (val & ENET_INIT_PARAM_PTR_MASK); 329 qe_muram_free(init_enet_offset); 330 } 331 *p_start++ = 0; 332 } 333 } 334 335 return 0; 336 } 337 338 #ifdef DEBUG 339 static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 340 u32 __iomem *p_start, 341 u8 num_entries, 342 u32 thread_size, 343 unsigned int risc, 344 int skip_page_for_first_entry) 345 { 346 u32 init_enet_offset; 347 u8 i; 348 int snum; 349 350 for (i = 0; i < num_entries; i++) { 351 u32 val = in_be32(p_start); 352 353 /* Check that this entry was actually valid -- 354 needed in case failed in allocations */ 355 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 356 snum = 357 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 358 ENET_INIT_PARAM_SNUM_SHIFT; 359 qe_put_snum((u8) snum); 360 if (!((i == 0) && skip_page_for_first_entry)) { 361 /* First entry of Rx does not have page */ 362 init_enet_offset = 363 (in_be32(p_start) & 364 ENET_INIT_PARAM_PTR_MASK); 365 pr_info("Init enet entry %d:\n", i); 366 pr_info("Base address: 0x%08x\n", 367 (u32)qe_muram_addr(init_enet_offset)); 368 mem_disp(qe_muram_addr(init_enet_offset), 369 thread_size); 370 } 371 p_start++; 372 } 373 } 374 375 return 0; 376 } 377 #endif 378 379 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 380 { 381 kfree(enet_addr_cont); 382 } 383 384 static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 385 { 386 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 387 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 388 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 389 } 390 391 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 392 { 393 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 394 395 if (paddr_num >= NUM_OF_PADDRS) { 396 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 397 return -EINVAL; 398 } 399 400 p_82xx_addr_filt = 401 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 402 addressfiltering; 403 404 /* Writing address ff.ff.ff.ff.ff.ff disables address 405 recognition for this register */ 406 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 407 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 409 410 return 0; 411 } 412 413 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 414 u8 *p_enet_addr) 415 { 416 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 417 u32 cecr_subblock; 418 419 p_82xx_addr_filt = 420 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 421 addressfiltering; 422 423 cecr_subblock = 424 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 425 426 /* Ethernet frames are defined in Little Endian mode, 427 therefore to insert */ 428 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 429 430 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 431 432 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 433 QE_CR_PROTOCOL_ETHERNET, 0); 434 } 435 436 static inline int compare_addr(u8 **addr1, u8 **addr2) 437 { 438 return memcmp(addr1, addr2, ETH_ALEN); 439 } 440 441 #ifdef DEBUG 442 static void get_statistics(struct ucc_geth_private *ugeth, 443 struct ucc_geth_tx_firmware_statistics * 444 tx_firmware_statistics, 445 struct ucc_geth_rx_firmware_statistics * 446 rx_firmware_statistics, 447 struct ucc_geth_hardware_statistics *hardware_statistics) 448 { 449 struct ucc_fast __iomem *uf_regs; 450 struct ucc_geth __iomem *ug_regs; 451 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 452 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 453 454 ug_regs = ugeth->ug_regs; 455 uf_regs = (struct ucc_fast __iomem *) ug_regs; 456 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 457 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 458 459 /* Tx firmware only if user handed pointer and driver actually 460 gathers Tx firmware statistics */ 461 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 462 tx_firmware_statistics->sicoltx = 463 in_be32(&p_tx_fw_statistics_pram->sicoltx); 464 tx_firmware_statistics->mulcoltx = 465 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 466 tx_firmware_statistics->latecoltxfr = 467 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 468 tx_firmware_statistics->frabortduecol = 469 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 470 tx_firmware_statistics->frlostinmactxer = 471 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 472 tx_firmware_statistics->carriersenseertx = 473 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 474 tx_firmware_statistics->frtxok = 475 in_be32(&p_tx_fw_statistics_pram->frtxok); 476 tx_firmware_statistics->txfrexcessivedefer = 477 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 478 tx_firmware_statistics->txpkts256 = 479 in_be32(&p_tx_fw_statistics_pram->txpkts256); 480 tx_firmware_statistics->txpkts512 = 481 in_be32(&p_tx_fw_statistics_pram->txpkts512); 482 tx_firmware_statistics->txpkts1024 = 483 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 484 tx_firmware_statistics->txpktsjumbo = 485 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 486 } 487 488 /* Rx firmware only if user handed pointer and driver actually 489 * gathers Rx firmware statistics */ 490 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 491 int i; 492 rx_firmware_statistics->frrxfcser = 493 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 494 rx_firmware_statistics->fraligner = 495 in_be32(&p_rx_fw_statistics_pram->fraligner); 496 rx_firmware_statistics->inrangelenrxer = 497 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 498 rx_firmware_statistics->outrangelenrxer = 499 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 500 rx_firmware_statistics->frtoolong = 501 in_be32(&p_rx_fw_statistics_pram->frtoolong); 502 rx_firmware_statistics->runt = 503 in_be32(&p_rx_fw_statistics_pram->runt); 504 rx_firmware_statistics->verylongevent = 505 in_be32(&p_rx_fw_statistics_pram->verylongevent); 506 rx_firmware_statistics->symbolerror = 507 in_be32(&p_rx_fw_statistics_pram->symbolerror); 508 rx_firmware_statistics->dropbsy = 509 in_be32(&p_rx_fw_statistics_pram->dropbsy); 510 for (i = 0; i < 0x8; i++) 511 rx_firmware_statistics->res0[i] = 512 p_rx_fw_statistics_pram->res0[i]; 513 rx_firmware_statistics->mismatchdrop = 514 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 515 rx_firmware_statistics->underpkts = 516 in_be32(&p_rx_fw_statistics_pram->underpkts); 517 rx_firmware_statistics->pkts256 = 518 in_be32(&p_rx_fw_statistics_pram->pkts256); 519 rx_firmware_statistics->pkts512 = 520 in_be32(&p_rx_fw_statistics_pram->pkts512); 521 rx_firmware_statistics->pkts1024 = 522 in_be32(&p_rx_fw_statistics_pram->pkts1024); 523 rx_firmware_statistics->pktsjumbo = 524 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 525 rx_firmware_statistics->frlossinmacer = 526 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 527 rx_firmware_statistics->pausefr = 528 in_be32(&p_rx_fw_statistics_pram->pausefr); 529 for (i = 0; i < 0x4; i++) 530 rx_firmware_statistics->res1[i] = 531 p_rx_fw_statistics_pram->res1[i]; 532 rx_firmware_statistics->removevlan = 533 in_be32(&p_rx_fw_statistics_pram->removevlan); 534 rx_firmware_statistics->replacevlan = 535 in_be32(&p_rx_fw_statistics_pram->replacevlan); 536 rx_firmware_statistics->insertvlan = 537 in_be32(&p_rx_fw_statistics_pram->insertvlan); 538 } 539 540 /* Hardware only if user handed pointer and driver actually 541 gathers hardware statistics */ 542 if (hardware_statistics && 543 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 544 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 545 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 546 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 547 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 548 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 549 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 550 hardware_statistics->txok = in_be32(&ug_regs->txok); 551 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 552 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 553 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 554 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 555 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 556 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 557 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 558 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 559 } 560 } 561 562 static void dump_bds(struct ucc_geth_private *ugeth) 563 { 564 int i; 565 int length; 566 567 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 568 if (ugeth->p_tx_bd_ring[i]) { 569 length = 570 (ugeth->ug_info->bdRingLenTx[i] * 571 sizeof(struct qe_bd)); 572 pr_info("TX BDs[%d]\n", i); 573 mem_disp(ugeth->p_tx_bd_ring[i], length); 574 } 575 } 576 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 577 if (ugeth->p_rx_bd_ring[i]) { 578 length = 579 (ugeth->ug_info->bdRingLenRx[i] * 580 sizeof(struct qe_bd)); 581 pr_info("RX BDs[%d]\n", i); 582 mem_disp(ugeth->p_rx_bd_ring[i], length); 583 } 584 } 585 } 586 587 static void dump_regs(struct ucc_geth_private *ugeth) 588 { 589 int i; 590 591 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 592 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 593 594 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 595 (u32)&ugeth->ug_regs->maccfg1, 596 in_be32(&ugeth->ug_regs->maccfg1)); 597 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 598 (u32)&ugeth->ug_regs->maccfg2, 599 in_be32(&ugeth->ug_regs->maccfg2)); 600 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 601 (u32)&ugeth->ug_regs->ipgifg, 602 in_be32(&ugeth->ug_regs->ipgifg)); 603 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 604 (u32)&ugeth->ug_regs->hafdup, 605 in_be32(&ugeth->ug_regs->hafdup)); 606 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 607 (u32)&ugeth->ug_regs->ifctl, 608 in_be32(&ugeth->ug_regs->ifctl)); 609 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 610 (u32)&ugeth->ug_regs->ifstat, 611 in_be32(&ugeth->ug_regs->ifstat)); 612 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 613 (u32)&ugeth->ug_regs->macstnaddr1, 614 in_be32(&ugeth->ug_regs->macstnaddr1)); 615 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 616 (u32)&ugeth->ug_regs->macstnaddr2, 617 in_be32(&ugeth->ug_regs->macstnaddr2)); 618 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 619 (u32)&ugeth->ug_regs->uempr, 620 in_be32(&ugeth->ug_regs->uempr)); 621 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 622 (u32)&ugeth->ug_regs->utbipar, 623 in_be32(&ugeth->ug_regs->utbipar)); 624 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 625 (u32)&ugeth->ug_regs->uescr, 626 in_be16(&ugeth->ug_regs->uescr)); 627 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 628 (u32)&ugeth->ug_regs->tx64, 629 in_be32(&ugeth->ug_regs->tx64)); 630 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 631 (u32)&ugeth->ug_regs->tx127, 632 in_be32(&ugeth->ug_regs->tx127)); 633 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 634 (u32)&ugeth->ug_regs->tx255, 635 in_be32(&ugeth->ug_regs->tx255)); 636 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 637 (u32)&ugeth->ug_regs->rx64, 638 in_be32(&ugeth->ug_regs->rx64)); 639 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 640 (u32)&ugeth->ug_regs->rx127, 641 in_be32(&ugeth->ug_regs->rx127)); 642 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 643 (u32)&ugeth->ug_regs->rx255, 644 in_be32(&ugeth->ug_regs->rx255)); 645 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 646 (u32)&ugeth->ug_regs->txok, 647 in_be32(&ugeth->ug_regs->txok)); 648 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 649 (u32)&ugeth->ug_regs->txcf, 650 in_be16(&ugeth->ug_regs->txcf)); 651 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 652 (u32)&ugeth->ug_regs->tmca, 653 in_be32(&ugeth->ug_regs->tmca)); 654 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 655 (u32)&ugeth->ug_regs->tbca, 656 in_be32(&ugeth->ug_regs->tbca)); 657 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 658 (u32)&ugeth->ug_regs->rxfok, 659 in_be32(&ugeth->ug_regs->rxfok)); 660 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 661 (u32)&ugeth->ug_regs->rxbok, 662 in_be32(&ugeth->ug_regs->rxbok)); 663 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 664 (u32)&ugeth->ug_regs->rbyt, 665 in_be32(&ugeth->ug_regs->rbyt)); 666 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 667 (u32)&ugeth->ug_regs->rmca, 668 in_be32(&ugeth->ug_regs->rmca)); 669 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 670 (u32)&ugeth->ug_regs->rbca, 671 in_be32(&ugeth->ug_regs->rbca)); 672 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 673 (u32)&ugeth->ug_regs->scar, 674 in_be32(&ugeth->ug_regs->scar)); 675 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 676 (u32)&ugeth->ug_regs->scam, 677 in_be32(&ugeth->ug_regs->scam)); 678 679 if (ugeth->p_thread_data_tx) { 680 int numThreadsTxNumerical; 681 switch (ugeth->ug_info->numThreadsTx) { 682 case UCC_GETH_NUM_OF_THREADS_1: 683 numThreadsTxNumerical = 1; 684 break; 685 case UCC_GETH_NUM_OF_THREADS_2: 686 numThreadsTxNumerical = 2; 687 break; 688 case UCC_GETH_NUM_OF_THREADS_4: 689 numThreadsTxNumerical = 4; 690 break; 691 case UCC_GETH_NUM_OF_THREADS_6: 692 numThreadsTxNumerical = 6; 693 break; 694 case UCC_GETH_NUM_OF_THREADS_8: 695 numThreadsTxNumerical = 8; 696 break; 697 default: 698 numThreadsTxNumerical = 0; 699 break; 700 } 701 702 pr_info("Thread data TXs:\n"); 703 pr_info("Base address: 0x%08x\n", 704 (u32)ugeth->p_thread_data_tx); 705 for (i = 0; i < numThreadsTxNumerical; i++) { 706 pr_info("Thread data TX[%d]:\n", i); 707 pr_info("Base address: 0x%08x\n", 708 (u32)&ugeth->p_thread_data_tx[i]); 709 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 710 sizeof(struct ucc_geth_thread_data_tx)); 711 } 712 } 713 if (ugeth->p_thread_data_rx) { 714 int numThreadsRxNumerical; 715 switch (ugeth->ug_info->numThreadsRx) { 716 case UCC_GETH_NUM_OF_THREADS_1: 717 numThreadsRxNumerical = 1; 718 break; 719 case UCC_GETH_NUM_OF_THREADS_2: 720 numThreadsRxNumerical = 2; 721 break; 722 case UCC_GETH_NUM_OF_THREADS_4: 723 numThreadsRxNumerical = 4; 724 break; 725 case UCC_GETH_NUM_OF_THREADS_6: 726 numThreadsRxNumerical = 6; 727 break; 728 case UCC_GETH_NUM_OF_THREADS_8: 729 numThreadsRxNumerical = 8; 730 break; 731 default: 732 numThreadsRxNumerical = 0; 733 break; 734 } 735 736 pr_info("Thread data RX:\n"); 737 pr_info("Base address: 0x%08x\n", 738 (u32)ugeth->p_thread_data_rx); 739 for (i = 0; i < numThreadsRxNumerical; i++) { 740 pr_info("Thread data RX[%d]:\n", i); 741 pr_info("Base address: 0x%08x\n", 742 (u32)&ugeth->p_thread_data_rx[i]); 743 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 744 sizeof(struct ucc_geth_thread_data_rx)); 745 } 746 } 747 if (ugeth->p_exf_glbl_param) { 748 pr_info("EXF global param:\n"); 749 pr_info("Base address: 0x%08x\n", 750 (u32)ugeth->p_exf_glbl_param); 751 mem_disp((u8 *) ugeth->p_exf_glbl_param, 752 sizeof(*ugeth->p_exf_glbl_param)); 753 } 754 if (ugeth->p_tx_glbl_pram) { 755 pr_info("TX global param:\n"); 756 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 757 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 758 (u32)&ugeth->p_tx_glbl_pram->temoder, 759 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 760 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 761 (u32)&ugeth->p_tx_glbl_pram->sqptr, 762 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 763 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 764 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 765 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 766 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 767 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 768 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 769 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 770 (u32)&ugeth->p_tx_glbl_pram->tstate, 771 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 772 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 773 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 774 ugeth->p_tx_glbl_pram->iphoffset[0]); 775 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 776 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 777 ugeth->p_tx_glbl_pram->iphoffset[1]); 778 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 779 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 780 ugeth->p_tx_glbl_pram->iphoffset[2]); 781 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 782 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 783 ugeth->p_tx_glbl_pram->iphoffset[3]); 784 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 785 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 786 ugeth->p_tx_glbl_pram->iphoffset[4]); 787 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 788 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 789 ugeth->p_tx_glbl_pram->iphoffset[5]); 790 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 791 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 792 ugeth->p_tx_glbl_pram->iphoffset[6]); 793 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 794 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 795 ugeth->p_tx_glbl_pram->iphoffset[7]); 796 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 797 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 798 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 799 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 800 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 801 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 802 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 803 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 805 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 806 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 808 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 809 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 811 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 812 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 814 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 815 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 817 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 818 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 819 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 820 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 821 (u32)&ugeth->p_tx_glbl_pram->tqptr, 822 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 823 } 824 if (ugeth->p_rx_glbl_pram) { 825 pr_info("RX global param:\n"); 826 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 827 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 828 (u32)&ugeth->p_rx_glbl_pram->remoder, 829 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 830 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 831 (u32)&ugeth->p_rx_glbl_pram->rqptr, 832 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 833 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 834 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 835 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 836 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 837 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 838 ugeth->p_rx_glbl_pram->rxgstpack); 839 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 840 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 841 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 842 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 843 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 844 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 845 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 846 (u32)&ugeth->p_rx_glbl_pram->rstate, 847 ugeth->p_rx_glbl_pram->rstate); 848 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 849 (u32)&ugeth->p_rx_glbl_pram->mrblr, 850 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 851 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 852 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 853 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 854 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 855 (u32)&ugeth->p_rx_glbl_pram->mflr, 856 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 857 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 858 (u32)&ugeth->p_rx_glbl_pram->minflr, 859 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 860 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 861 (u32)&ugeth->p_rx_glbl_pram->maxd1, 862 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 863 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 864 (u32)&ugeth->p_rx_glbl_pram->maxd2, 865 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 866 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 867 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 868 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 869 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 870 (u32)&ugeth->p_rx_glbl_pram->l2qt, 871 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 872 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 873 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 874 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 875 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 876 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 877 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 878 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 879 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 881 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 882 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 884 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 885 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 887 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 888 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 890 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 891 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 893 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 894 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 895 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 896 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 897 (u32)&ugeth->p_rx_glbl_pram->vlantype, 898 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 899 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 900 (u32)&ugeth->p_rx_glbl_pram->vlantci, 901 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 902 for (i = 0; i < 64; i++) 903 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 904 i, 905 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 906 ugeth->p_rx_glbl_pram->addressfiltering[i]); 907 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 908 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 909 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 910 } 911 if (ugeth->p_send_q_mem_reg) { 912 pr_info("Send Q memory registers:\n"); 913 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 914 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 915 pr_info("SQQD[%d]:\n", i); 916 pr_info("Base address: 0x%08x\n", 917 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 918 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 919 sizeof(struct ucc_geth_send_queue_qd)); 920 } 921 } 922 if (ugeth->p_scheduler) { 923 pr_info("Scheduler:\n"); 924 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 925 mem_disp((u8 *) ugeth->p_scheduler, 926 sizeof(*ugeth->p_scheduler)); 927 } 928 if (ugeth->p_tx_fw_statistics_pram) { 929 pr_info("TX FW statistics pram:\n"); 930 pr_info("Base address: 0x%08x\n", 931 (u32)ugeth->p_tx_fw_statistics_pram); 932 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 933 sizeof(*ugeth->p_tx_fw_statistics_pram)); 934 } 935 if (ugeth->p_rx_fw_statistics_pram) { 936 pr_info("RX FW statistics pram:\n"); 937 pr_info("Base address: 0x%08x\n", 938 (u32)ugeth->p_rx_fw_statistics_pram); 939 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 940 sizeof(*ugeth->p_rx_fw_statistics_pram)); 941 } 942 if (ugeth->p_rx_irq_coalescing_tbl) { 943 pr_info("RX IRQ coalescing tables:\n"); 944 pr_info("Base address: 0x%08x\n", 945 (u32)ugeth->p_rx_irq_coalescing_tbl); 946 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 947 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 948 pr_info("Base address: 0x%08x\n", 949 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 950 coalescingentry[i]); 951 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 952 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 953 coalescingentry[i].interruptcoalescingmaxvalue, 954 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 955 coalescingentry[i]. 956 interruptcoalescingmaxvalue)); 957 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 958 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 959 coalescingentry[i].interruptcoalescingcounter, 960 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 961 coalescingentry[i]. 962 interruptcoalescingcounter)); 963 } 964 } 965 if (ugeth->p_rx_bd_qs_tbl) { 966 pr_info("RX BD QS tables:\n"); 967 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 968 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 969 pr_info("RX BD QS table[%d]:\n", i); 970 pr_info("Base address: 0x%08x\n", 971 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 972 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 973 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 974 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 975 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 976 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 977 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 978 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 979 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 980 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 981 externalbdbaseptr)); 982 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 983 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 984 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 985 pr_info("ucode RX Prefetched BDs:\n"); 986 pr_info("Base address: 0x%08x\n", 987 (u32)qe_muram_addr(in_be32 988 (&ugeth->p_rx_bd_qs_tbl[i]. 989 bdbaseptr))); 990 mem_disp((u8 *) 991 qe_muram_addr(in_be32 992 (&ugeth->p_rx_bd_qs_tbl[i]. 993 bdbaseptr)), 994 sizeof(struct ucc_geth_rx_prefetched_bds)); 995 } 996 } 997 if (ugeth->p_init_enet_param_shadow) { 998 int size; 999 pr_info("Init enet param shadow:\n"); 1000 pr_info("Base address: 0x%08x\n", 1001 (u32) ugeth->p_init_enet_param_shadow); 1002 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1003 sizeof(*ugeth->p_init_enet_param_shadow)); 1004 1005 size = sizeof(struct ucc_geth_thread_rx_pram); 1006 if (ugeth->ug_info->rxExtendedFiltering) { 1007 size += 1008 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1009 if (ugeth->ug_info->largestexternallookupkeysize == 1010 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1011 size += 1012 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1013 if (ugeth->ug_info->largestexternallookupkeysize == 1014 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1015 size += 1016 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1017 } 1018 1019 dump_init_enet_entries(ugeth, 1020 &(ugeth->p_init_enet_param_shadow-> 1021 txthread[0]), 1022 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1023 sizeof(struct ucc_geth_thread_tx_pram), 1024 ugeth->ug_info->riscTx, 0); 1025 dump_init_enet_entries(ugeth, 1026 &(ugeth->p_init_enet_param_shadow-> 1027 rxthread[0]), 1028 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1029 ugeth->ug_info->riscRx, 1); 1030 } 1031 } 1032 #endif /* DEBUG */ 1033 1034 static void init_default_reg_vals(u32 __iomem *upsmr_register, 1035 u32 __iomem *maccfg1_register, 1036 u32 __iomem *maccfg2_register) 1037 { 1038 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1039 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1040 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1041 } 1042 1043 static int init_half_duplex_params(int alt_beb, 1044 int back_pressure_no_backoff, 1045 int no_backoff, 1046 int excess_defer, 1047 u8 alt_beb_truncation, 1048 u8 max_retransmissions, 1049 u8 collision_window, 1050 u32 __iomem *hafdup_register) 1051 { 1052 u32 value = 0; 1053 1054 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1055 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1056 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1057 return -EINVAL; 1058 1059 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1060 1061 if (alt_beb) 1062 value |= HALFDUP_ALT_BEB; 1063 if (back_pressure_no_backoff) 1064 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1065 if (no_backoff) 1066 value |= HALFDUP_NO_BACKOFF; 1067 if (excess_defer) 1068 value |= HALFDUP_EXCESSIVE_DEFER; 1069 1070 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1071 1072 value |= collision_window; 1073 1074 out_be32(hafdup_register, value); 1075 return 0; 1076 } 1077 1078 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1079 u8 non_btb_ipg, 1080 u8 min_ifg, 1081 u8 btb_ipg, 1082 u32 __iomem *ipgifg_register) 1083 { 1084 u32 value = 0; 1085 1086 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1087 IPG part 2 */ 1088 if (non_btb_cs_ipg > non_btb_ipg) 1089 return -EINVAL; 1090 1091 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1092 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1093 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1094 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1095 return -EINVAL; 1096 1097 value |= 1098 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1099 IPGIFG_NBTB_CS_IPG_MASK); 1100 value |= 1101 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1102 IPGIFG_NBTB_IPG_MASK); 1103 value |= 1104 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1105 IPGIFG_MIN_IFG_MASK); 1106 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1107 1108 out_be32(ipgifg_register, value); 1109 return 0; 1110 } 1111 1112 int init_flow_control_params(u32 automatic_flow_control_mode, 1113 int rx_flow_control_enable, 1114 int tx_flow_control_enable, 1115 u16 pause_period, 1116 u16 extension_field, 1117 u32 __iomem *upsmr_register, 1118 u32 __iomem *uempr_register, 1119 u32 __iomem *maccfg1_register) 1120 { 1121 u32 value = 0; 1122 1123 /* Set UEMPR register */ 1124 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1125 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1126 out_be32(uempr_register, value); 1127 1128 /* Set UPSMR register */ 1129 setbits32(upsmr_register, automatic_flow_control_mode); 1130 1131 value = in_be32(maccfg1_register); 1132 if (rx_flow_control_enable) 1133 value |= MACCFG1_FLOW_RX; 1134 if (tx_flow_control_enable) 1135 value |= MACCFG1_FLOW_TX; 1136 out_be32(maccfg1_register, value); 1137 1138 return 0; 1139 } 1140 1141 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1142 int auto_zero_hardware_statistics, 1143 u32 __iomem *upsmr_register, 1144 u16 __iomem *uescr_register) 1145 { 1146 u16 uescr_value = 0; 1147 1148 /* Enable hardware statistics gathering if requested */ 1149 if (enable_hardware_statistics) 1150 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1151 1152 /* Clear hardware statistics counters */ 1153 uescr_value = in_be16(uescr_register); 1154 uescr_value |= UESCR_CLRCNT; 1155 /* Automatically zero hardware statistics counters on read, 1156 if requested */ 1157 if (auto_zero_hardware_statistics) 1158 uescr_value |= UESCR_AUTOZ; 1159 out_be16(uescr_register, uescr_value); 1160 1161 return 0; 1162 } 1163 1164 static int init_firmware_statistics_gathering_mode(int 1165 enable_tx_firmware_statistics, 1166 int enable_rx_firmware_statistics, 1167 u32 __iomem *tx_rmon_base_ptr, 1168 u32 tx_firmware_statistics_structure_address, 1169 u32 __iomem *rx_rmon_base_ptr, 1170 u32 rx_firmware_statistics_structure_address, 1171 u16 __iomem *temoder_register, 1172 u32 __iomem *remoder_register) 1173 { 1174 /* Note: this function does not check if */ 1175 /* the parameters it receives are NULL */ 1176 1177 if (enable_tx_firmware_statistics) { 1178 out_be32(tx_rmon_base_ptr, 1179 tx_firmware_statistics_structure_address); 1180 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1181 } 1182 1183 if (enable_rx_firmware_statistics) { 1184 out_be32(rx_rmon_base_ptr, 1185 rx_firmware_statistics_structure_address); 1186 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1187 } 1188 1189 return 0; 1190 } 1191 1192 static int init_mac_station_addr_regs(u8 address_byte_0, 1193 u8 address_byte_1, 1194 u8 address_byte_2, 1195 u8 address_byte_3, 1196 u8 address_byte_4, 1197 u8 address_byte_5, 1198 u32 __iomem *macstnaddr1_register, 1199 u32 __iomem *macstnaddr2_register) 1200 { 1201 u32 value = 0; 1202 1203 /* Example: for a station address of 0x12345678ABCD, */ 1204 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1205 1206 /* MACSTNADDR1 Register: */ 1207 1208 /* 0 7 8 15 */ 1209 /* station address byte 5 station address byte 4 */ 1210 /* 16 23 24 31 */ 1211 /* station address byte 3 station address byte 2 */ 1212 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1213 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1214 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1215 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1216 1217 out_be32(macstnaddr1_register, value); 1218 1219 /* MACSTNADDR2 Register: */ 1220 1221 /* 0 7 8 15 */ 1222 /* station address byte 1 station address byte 0 */ 1223 /* 16 23 24 31 */ 1224 /* reserved reserved */ 1225 value = 0; 1226 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1227 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1228 1229 out_be32(macstnaddr2_register, value); 1230 1231 return 0; 1232 } 1233 1234 static int init_check_frame_length_mode(int length_check, 1235 u32 __iomem *maccfg2_register) 1236 { 1237 u32 value = 0; 1238 1239 value = in_be32(maccfg2_register); 1240 1241 if (length_check) 1242 value |= MACCFG2_LC; 1243 else 1244 value &= ~MACCFG2_LC; 1245 1246 out_be32(maccfg2_register, value); 1247 return 0; 1248 } 1249 1250 static int init_preamble_length(u8 preamble_length, 1251 u32 __iomem *maccfg2_register) 1252 { 1253 if ((preamble_length < 3) || (preamble_length > 7)) 1254 return -EINVAL; 1255 1256 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1257 preamble_length << MACCFG2_PREL_SHIFT); 1258 1259 return 0; 1260 } 1261 1262 static int init_rx_parameters(int reject_broadcast, 1263 int receive_short_frames, 1264 int promiscuous, u32 __iomem *upsmr_register) 1265 { 1266 u32 value = 0; 1267 1268 value = in_be32(upsmr_register); 1269 1270 if (reject_broadcast) 1271 value |= UCC_GETH_UPSMR_BRO; 1272 else 1273 value &= ~UCC_GETH_UPSMR_BRO; 1274 1275 if (receive_short_frames) 1276 value |= UCC_GETH_UPSMR_RSH; 1277 else 1278 value &= ~UCC_GETH_UPSMR_RSH; 1279 1280 if (promiscuous) 1281 value |= UCC_GETH_UPSMR_PRO; 1282 else 1283 value &= ~UCC_GETH_UPSMR_PRO; 1284 1285 out_be32(upsmr_register, value); 1286 1287 return 0; 1288 } 1289 1290 static int init_max_rx_buff_len(u16 max_rx_buf_len, 1291 u16 __iomem *mrblr_register) 1292 { 1293 /* max_rx_buf_len value must be a multiple of 128 */ 1294 if ((max_rx_buf_len == 0) || 1295 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1296 return -EINVAL; 1297 1298 out_be16(mrblr_register, max_rx_buf_len); 1299 return 0; 1300 } 1301 1302 static int init_min_frame_len(u16 min_frame_length, 1303 u16 __iomem *minflr_register, 1304 u16 __iomem *mrblr_register) 1305 { 1306 u16 mrblr_value = 0; 1307 1308 mrblr_value = in_be16(mrblr_register); 1309 if (min_frame_length >= (mrblr_value - 4)) 1310 return -EINVAL; 1311 1312 out_be16(minflr_register, min_frame_length); 1313 return 0; 1314 } 1315 1316 static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1317 { 1318 struct ucc_geth_info *ug_info; 1319 struct ucc_geth __iomem *ug_regs; 1320 struct ucc_fast __iomem *uf_regs; 1321 int ret_val; 1322 u32 upsmr, maccfg2; 1323 u16 value; 1324 1325 ugeth_vdbg("%s: IN", __func__); 1326 1327 ug_info = ugeth->ug_info; 1328 ug_regs = ugeth->ug_regs; 1329 uf_regs = ugeth->uccf->uf_regs; 1330 1331 /* Set MACCFG2 */ 1332 maccfg2 = in_be32(&ug_regs->maccfg2); 1333 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1334 if ((ugeth->max_speed == SPEED_10) || 1335 (ugeth->max_speed == SPEED_100)) 1336 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1337 else if (ugeth->max_speed == SPEED_1000) 1338 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1339 maccfg2 |= ug_info->padAndCrc; 1340 out_be32(&ug_regs->maccfg2, maccfg2); 1341 1342 /* Set UPSMR */ 1343 upsmr = in_be32(&uf_regs->upsmr); 1344 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1345 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1346 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1349 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1350 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1351 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1352 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1353 upsmr |= UCC_GETH_UPSMR_RPM; 1354 switch (ugeth->max_speed) { 1355 case SPEED_10: 1356 upsmr |= UCC_GETH_UPSMR_R10M; 1357 /* FALLTHROUGH */ 1358 case SPEED_100: 1359 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1360 upsmr |= UCC_GETH_UPSMR_RMM; 1361 } 1362 } 1363 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1365 upsmr |= UCC_GETH_UPSMR_TBIM; 1366 } 1367 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1368 upsmr |= UCC_GETH_UPSMR_SGMM; 1369 1370 out_be32(&uf_regs->upsmr, upsmr); 1371 1372 /* Disable autonegotiation in tbi mode, because by default it 1373 comes up in autonegotiation mode. */ 1374 /* Note that this depends on proper setting in utbipar register. */ 1375 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1376 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1377 struct ucc_geth_info *ug_info = ugeth->ug_info; 1378 struct phy_device *tbiphy; 1379 1380 if (!ug_info->tbi_node) 1381 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1382 1383 tbiphy = of_phy_find_device(ug_info->tbi_node); 1384 if (!tbiphy) 1385 pr_warn("Could not get TBI device\n"); 1386 1387 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1388 value &= ~0x1000; /* Turn off autonegotiation */ 1389 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1390 } 1391 1392 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1393 1394 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1395 if (ret_val != 0) { 1396 if (netif_msg_probe(ugeth)) 1397 pr_err("Preamble length must be between 3 and 7 inclusive\n"); 1398 return ret_val; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1405 { 1406 struct ucc_fast_private *uccf; 1407 u32 cecr_subblock; 1408 u32 temp; 1409 int i = 10; 1410 1411 uccf = ugeth->uccf; 1412 1413 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1414 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1415 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1416 1417 /* Issue host command */ 1418 cecr_subblock = 1419 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1420 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1421 QE_CR_PROTOCOL_ETHERNET, 0); 1422 1423 /* Wait for command to complete */ 1424 do { 1425 msleep(10); 1426 temp = in_be32(uccf->p_ucce); 1427 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1428 1429 uccf->stopped_tx = 1; 1430 1431 return 0; 1432 } 1433 1434 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1435 { 1436 struct ucc_fast_private *uccf; 1437 u32 cecr_subblock; 1438 u8 temp; 1439 int i = 10; 1440 1441 uccf = ugeth->uccf; 1442 1443 /* Clear acknowledge bit */ 1444 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1445 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1446 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1447 1448 /* Keep issuing command and checking acknowledge bit until 1449 it is asserted, according to spec */ 1450 do { 1451 /* Issue host command */ 1452 cecr_subblock = 1453 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1454 ucc_num); 1455 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1456 QE_CR_PROTOCOL_ETHERNET, 0); 1457 msleep(10); 1458 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1459 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1460 1461 uccf->stopped_rx = 1; 1462 1463 return 0; 1464 } 1465 1466 static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1467 { 1468 struct ucc_fast_private *uccf; 1469 u32 cecr_subblock; 1470 1471 uccf = ugeth->uccf; 1472 1473 cecr_subblock = 1474 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1475 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1476 uccf->stopped_tx = 0; 1477 1478 return 0; 1479 } 1480 1481 static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1482 { 1483 struct ucc_fast_private *uccf; 1484 u32 cecr_subblock; 1485 1486 uccf = ugeth->uccf; 1487 1488 cecr_subblock = 1489 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1490 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1491 0); 1492 uccf->stopped_rx = 0; 1493 1494 return 0; 1495 } 1496 1497 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1498 { 1499 struct ucc_fast_private *uccf; 1500 int enabled_tx, enabled_rx; 1501 1502 uccf = ugeth->uccf; 1503 1504 /* check if the UCC number is in range. */ 1505 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1506 if (netif_msg_probe(ugeth)) 1507 pr_err("ucc_num out of range\n"); 1508 return -EINVAL; 1509 } 1510 1511 enabled_tx = uccf->enabled_tx; 1512 enabled_rx = uccf->enabled_rx; 1513 1514 /* Get Tx and Rx going again, in case this channel was actively 1515 disabled. */ 1516 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1517 ugeth_restart_tx(ugeth); 1518 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1519 ugeth_restart_rx(ugeth); 1520 1521 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1522 1523 return 0; 1524 1525 } 1526 1527 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1528 { 1529 struct ucc_fast_private *uccf; 1530 1531 uccf = ugeth->uccf; 1532 1533 /* check if the UCC number is in range. */ 1534 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1535 if (netif_msg_probe(ugeth)) 1536 pr_err("ucc_num out of range\n"); 1537 return -EINVAL; 1538 } 1539 1540 /* Stop any transmissions */ 1541 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1542 ugeth_graceful_stop_tx(ugeth); 1543 1544 /* Stop any receptions */ 1545 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1546 ugeth_graceful_stop_rx(ugeth); 1547 1548 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1549 1550 return 0; 1551 } 1552 1553 static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1554 { 1555 /* Prevent any further xmits, plus detach the device. */ 1556 netif_device_detach(ugeth->ndev); 1557 1558 /* Wait for any current xmits to finish. */ 1559 netif_tx_disable(ugeth->ndev); 1560 1561 /* Disable the interrupt to avoid NAPI rescheduling. */ 1562 disable_irq(ugeth->ug_info->uf_info.irq); 1563 1564 /* Stop NAPI, and possibly wait for its completion. */ 1565 napi_disable(&ugeth->napi); 1566 } 1567 1568 static void ugeth_activate(struct ucc_geth_private *ugeth) 1569 { 1570 napi_enable(&ugeth->napi); 1571 enable_irq(ugeth->ug_info->uf_info.irq); 1572 netif_device_attach(ugeth->ndev); 1573 } 1574 1575 /* Called every time the controller might need to be made 1576 * aware of new link state. The PHY code conveys this 1577 * information through variables in the ugeth structure, and this 1578 * function converts those variables into the appropriate 1579 * register values, and can bring down the device if needed. 1580 */ 1581 1582 static void adjust_link(struct net_device *dev) 1583 { 1584 struct ucc_geth_private *ugeth = netdev_priv(dev); 1585 struct ucc_geth __iomem *ug_regs; 1586 struct ucc_fast __iomem *uf_regs; 1587 struct phy_device *phydev = ugeth->phydev; 1588 int new_state = 0; 1589 1590 ug_regs = ugeth->ug_regs; 1591 uf_regs = ugeth->uccf->uf_regs; 1592 1593 if (phydev->link) { 1594 u32 tempval = in_be32(&ug_regs->maccfg2); 1595 u32 upsmr = in_be32(&uf_regs->upsmr); 1596 /* Now we make sure that we can be in full duplex mode. 1597 * If not, we operate in half-duplex mode. */ 1598 if (phydev->duplex != ugeth->oldduplex) { 1599 new_state = 1; 1600 if (!(phydev->duplex)) 1601 tempval &= ~(MACCFG2_FDX); 1602 else 1603 tempval |= MACCFG2_FDX; 1604 ugeth->oldduplex = phydev->duplex; 1605 } 1606 1607 if (phydev->speed != ugeth->oldspeed) { 1608 new_state = 1; 1609 switch (phydev->speed) { 1610 case SPEED_1000: 1611 tempval = ((tempval & 1612 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1613 MACCFG2_INTERFACE_MODE_BYTE); 1614 break; 1615 case SPEED_100: 1616 case SPEED_10: 1617 tempval = ((tempval & 1618 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1619 MACCFG2_INTERFACE_MODE_NIBBLE); 1620 /* if reduced mode, re-set UPSMR.R10M */ 1621 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1626 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1627 if (phydev->speed == SPEED_10) 1628 upsmr |= UCC_GETH_UPSMR_R10M; 1629 else 1630 upsmr &= ~UCC_GETH_UPSMR_R10M; 1631 } 1632 break; 1633 default: 1634 if (netif_msg_link(ugeth)) 1635 pr_warn( 1636 "%s: Ack! Speed (%d) is not 10/100/1000!", 1637 dev->name, phydev->speed); 1638 break; 1639 } 1640 ugeth->oldspeed = phydev->speed; 1641 } 1642 1643 if (!ugeth->oldlink) { 1644 new_state = 1; 1645 ugeth->oldlink = 1; 1646 } 1647 1648 if (new_state) { 1649 /* 1650 * To change the MAC configuration we need to disable 1651 * the controller. To do so, we have to either grab 1652 * ugeth->lock, which is a bad idea since 'graceful 1653 * stop' commands might take quite a while, or we can 1654 * quiesce driver's activity. 1655 */ 1656 ugeth_quiesce(ugeth); 1657 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1658 1659 out_be32(&ug_regs->maccfg2, tempval); 1660 out_be32(&uf_regs->upsmr, upsmr); 1661 1662 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1663 ugeth_activate(ugeth); 1664 } 1665 } else if (ugeth->oldlink) { 1666 new_state = 1; 1667 ugeth->oldlink = 0; 1668 ugeth->oldspeed = 0; 1669 ugeth->oldduplex = -1; 1670 } 1671 1672 if (new_state && netif_msg_link(ugeth)) 1673 phy_print_status(phydev); 1674 } 1675 1676 /* Initialize TBI PHY interface for communicating with the 1677 * SERDES lynx PHY on the chip. We communicate with this PHY 1678 * through the MDIO bus on each controller, treating it as a 1679 * "normal" PHY at the address found in the UTBIPA register. We assume 1680 * that the UTBIPA register is valid. Either the MDIO bus code will set 1681 * it to a value that doesn't conflict with other PHYs on the bus, or the 1682 * value doesn't matter, as there are no other PHYs on the bus. 1683 */ 1684 static void uec_configure_serdes(struct net_device *dev) 1685 { 1686 struct ucc_geth_private *ugeth = netdev_priv(dev); 1687 struct ucc_geth_info *ug_info = ugeth->ug_info; 1688 struct phy_device *tbiphy; 1689 1690 if (!ug_info->tbi_node) { 1691 dev_warn(&dev->dev, "SGMII mode requires that the device " 1692 "tree specify a tbi-handle\n"); 1693 return; 1694 } 1695 1696 tbiphy = of_phy_find_device(ug_info->tbi_node); 1697 if (!tbiphy) { 1698 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1699 return; 1700 } 1701 1702 /* 1703 * If the link is already up, we must already be ok, and don't need to 1704 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1705 * everything for us? Resetting it takes the link down and requires 1706 * several seconds for it to come back. 1707 */ 1708 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) 1709 return; 1710 1711 /* Single clk mode, mii mode off(for serdes communication) */ 1712 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1713 1714 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1715 1716 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1717 } 1718 1719 /* Configure the PHY for dev. 1720 * returns 0 if success. -1 if failure 1721 */ 1722 static int init_phy(struct net_device *dev) 1723 { 1724 struct ucc_geth_private *priv = netdev_priv(dev); 1725 struct ucc_geth_info *ug_info = priv->ug_info; 1726 struct phy_device *phydev; 1727 1728 priv->oldlink = 0; 1729 priv->oldspeed = 0; 1730 priv->oldduplex = -1; 1731 1732 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1733 priv->phy_interface); 1734 if (!phydev) 1735 phydev = of_phy_connect_fixed_link(dev, &adjust_link, 1736 priv->phy_interface); 1737 if (!phydev) { 1738 dev_err(&dev->dev, "Could not attach to PHY\n"); 1739 return -ENODEV; 1740 } 1741 1742 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1743 uec_configure_serdes(dev); 1744 1745 phydev->supported &= (SUPPORTED_MII | 1746 SUPPORTED_Autoneg | 1747 ADVERTISED_10baseT_Half | 1748 ADVERTISED_10baseT_Full | 1749 ADVERTISED_100baseT_Half | 1750 ADVERTISED_100baseT_Full); 1751 1752 if (priv->max_speed == SPEED_1000) 1753 phydev->supported |= ADVERTISED_1000baseT_Full; 1754 1755 phydev->advertising = phydev->supported; 1756 1757 priv->phydev = phydev; 1758 1759 return 0; 1760 } 1761 1762 static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1763 { 1764 #ifdef DEBUG 1765 ucc_fast_dump_regs(ugeth->uccf); 1766 dump_regs(ugeth); 1767 dump_bds(ugeth); 1768 #endif 1769 } 1770 1771 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1772 ugeth, 1773 enum enet_addr_type 1774 enet_addr_type) 1775 { 1776 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1777 struct ucc_fast_private *uccf; 1778 enum comm_dir comm_dir; 1779 struct list_head *p_lh; 1780 u16 i, num; 1781 u32 __iomem *addr_h; 1782 u32 __iomem *addr_l; 1783 u8 *p_counter; 1784 1785 uccf = ugeth->uccf; 1786 1787 p_82xx_addr_filt = 1788 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1789 ugeth->p_rx_glbl_pram->addressfiltering; 1790 1791 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1792 addr_h = &(p_82xx_addr_filt->gaddr_h); 1793 addr_l = &(p_82xx_addr_filt->gaddr_l); 1794 p_lh = &ugeth->group_hash_q; 1795 p_counter = &(ugeth->numGroupAddrInHash); 1796 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1797 addr_h = &(p_82xx_addr_filt->iaddr_h); 1798 addr_l = &(p_82xx_addr_filt->iaddr_l); 1799 p_lh = &ugeth->ind_hash_q; 1800 p_counter = &(ugeth->numIndAddrInHash); 1801 } else 1802 return -EINVAL; 1803 1804 comm_dir = 0; 1805 if (uccf->enabled_tx) 1806 comm_dir |= COMM_DIR_TX; 1807 if (uccf->enabled_rx) 1808 comm_dir |= COMM_DIR_RX; 1809 if (comm_dir) 1810 ugeth_disable(ugeth, comm_dir); 1811 1812 /* Clear the hash table. */ 1813 out_be32(addr_h, 0x00000000); 1814 out_be32(addr_l, 0x00000000); 1815 1816 if (!p_lh) 1817 return 0; 1818 1819 num = *p_counter; 1820 1821 /* Delete all remaining CQ elements */ 1822 for (i = 0; i < num; i++) 1823 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1824 1825 *p_counter = 0; 1826 1827 if (comm_dir) 1828 ugeth_enable(ugeth, comm_dir); 1829 1830 return 0; 1831 } 1832 1833 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1834 u8 paddr_num) 1835 { 1836 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1837 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1838 } 1839 1840 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1841 { 1842 struct ucc_geth_info *ug_info; 1843 struct ucc_fast_info *uf_info; 1844 u16 i, j; 1845 u8 __iomem *bd; 1846 1847 1848 ug_info = ugeth->ug_info; 1849 uf_info = &ug_info->uf_info; 1850 1851 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1852 if (ugeth->p_rx_bd_ring[i]) { 1853 /* Return existing data buffers in ring */ 1854 bd = ugeth->p_rx_bd_ring[i]; 1855 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1856 if (ugeth->rx_skbuff[i][j]) { 1857 dma_unmap_single(ugeth->dev, 1858 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1859 ugeth->ug_info-> 1860 uf_info.max_rx_buf_length + 1861 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1862 DMA_FROM_DEVICE); 1863 dev_kfree_skb_any( 1864 ugeth->rx_skbuff[i][j]); 1865 ugeth->rx_skbuff[i][j] = NULL; 1866 } 1867 bd += sizeof(struct qe_bd); 1868 } 1869 1870 kfree(ugeth->rx_skbuff[i]); 1871 1872 if (ugeth->ug_info->uf_info.bd_mem_part == 1873 MEM_PART_SYSTEM) 1874 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1875 else if (ugeth->ug_info->uf_info.bd_mem_part == 1876 MEM_PART_MURAM) 1877 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1878 ugeth->p_rx_bd_ring[i] = NULL; 1879 } 1880 } 1881 1882 } 1883 1884 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1885 { 1886 struct ucc_geth_info *ug_info; 1887 struct ucc_fast_info *uf_info; 1888 u16 i, j; 1889 u8 __iomem *bd; 1890 1891 ug_info = ugeth->ug_info; 1892 uf_info = &ug_info->uf_info; 1893 1894 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1895 bd = ugeth->p_tx_bd_ring[i]; 1896 if (!bd) 1897 continue; 1898 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1899 if (ugeth->tx_skbuff[i][j]) { 1900 dma_unmap_single(ugeth->dev, 1901 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1902 (in_be32((u32 __iomem *)bd) & 1903 BD_LENGTH_MASK), 1904 DMA_TO_DEVICE); 1905 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1906 ugeth->tx_skbuff[i][j] = NULL; 1907 } 1908 } 1909 1910 kfree(ugeth->tx_skbuff[i]); 1911 1912 if (ugeth->p_tx_bd_ring[i]) { 1913 if (ugeth->ug_info->uf_info.bd_mem_part == 1914 MEM_PART_SYSTEM) 1915 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1916 else if (ugeth->ug_info->uf_info.bd_mem_part == 1917 MEM_PART_MURAM) 1918 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1919 ugeth->p_tx_bd_ring[i] = NULL; 1920 } 1921 } 1922 1923 } 1924 1925 static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1926 { 1927 if (!ugeth) 1928 return; 1929 1930 if (ugeth->uccf) { 1931 ucc_fast_free(ugeth->uccf); 1932 ugeth->uccf = NULL; 1933 } 1934 1935 if (ugeth->p_thread_data_tx) { 1936 qe_muram_free(ugeth->thread_dat_tx_offset); 1937 ugeth->p_thread_data_tx = NULL; 1938 } 1939 if (ugeth->p_thread_data_rx) { 1940 qe_muram_free(ugeth->thread_dat_rx_offset); 1941 ugeth->p_thread_data_rx = NULL; 1942 } 1943 if (ugeth->p_exf_glbl_param) { 1944 qe_muram_free(ugeth->exf_glbl_param_offset); 1945 ugeth->p_exf_glbl_param = NULL; 1946 } 1947 if (ugeth->p_rx_glbl_pram) { 1948 qe_muram_free(ugeth->rx_glbl_pram_offset); 1949 ugeth->p_rx_glbl_pram = NULL; 1950 } 1951 if (ugeth->p_tx_glbl_pram) { 1952 qe_muram_free(ugeth->tx_glbl_pram_offset); 1953 ugeth->p_tx_glbl_pram = NULL; 1954 } 1955 if (ugeth->p_send_q_mem_reg) { 1956 qe_muram_free(ugeth->send_q_mem_reg_offset); 1957 ugeth->p_send_q_mem_reg = NULL; 1958 } 1959 if (ugeth->p_scheduler) { 1960 qe_muram_free(ugeth->scheduler_offset); 1961 ugeth->p_scheduler = NULL; 1962 } 1963 if (ugeth->p_tx_fw_statistics_pram) { 1964 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1965 ugeth->p_tx_fw_statistics_pram = NULL; 1966 } 1967 if (ugeth->p_rx_fw_statistics_pram) { 1968 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1969 ugeth->p_rx_fw_statistics_pram = NULL; 1970 } 1971 if (ugeth->p_rx_irq_coalescing_tbl) { 1972 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1973 ugeth->p_rx_irq_coalescing_tbl = NULL; 1974 } 1975 if (ugeth->p_rx_bd_qs_tbl) { 1976 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1977 ugeth->p_rx_bd_qs_tbl = NULL; 1978 } 1979 if (ugeth->p_init_enet_param_shadow) { 1980 return_init_enet_entries(ugeth, 1981 &(ugeth->p_init_enet_param_shadow-> 1982 rxthread[0]), 1983 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1984 ugeth->ug_info->riscRx, 1); 1985 return_init_enet_entries(ugeth, 1986 &(ugeth->p_init_enet_param_shadow-> 1987 txthread[0]), 1988 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1989 ugeth->ug_info->riscTx, 0); 1990 kfree(ugeth->p_init_enet_param_shadow); 1991 ugeth->p_init_enet_param_shadow = NULL; 1992 } 1993 ucc_geth_free_tx(ugeth); 1994 ucc_geth_free_rx(ugeth); 1995 while (!list_empty(&ugeth->group_hash_q)) 1996 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1997 (dequeue(&ugeth->group_hash_q))); 1998 while (!list_empty(&ugeth->ind_hash_q)) 1999 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 2000 (dequeue(&ugeth->ind_hash_q))); 2001 if (ugeth->ug_regs) { 2002 iounmap(ugeth->ug_regs); 2003 ugeth->ug_regs = NULL; 2004 } 2005 } 2006 2007 static void ucc_geth_set_multi(struct net_device *dev) 2008 { 2009 struct ucc_geth_private *ugeth; 2010 struct netdev_hw_addr *ha; 2011 struct ucc_fast __iomem *uf_regs; 2012 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2013 2014 ugeth = netdev_priv(dev); 2015 2016 uf_regs = ugeth->uccf->uf_regs; 2017 2018 if (dev->flags & IFF_PROMISC) { 2019 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2020 } else { 2021 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2022 2023 p_82xx_addr_filt = 2024 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2025 p_rx_glbl_pram->addressfiltering; 2026 2027 if (dev->flags & IFF_ALLMULTI) { 2028 /* Catch all multicast addresses, so set the 2029 * filter to all 1's. 2030 */ 2031 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2032 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2033 } else { 2034 /* Clear filter and add the addresses in the list. 2035 */ 2036 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2037 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2038 2039 netdev_for_each_mc_addr(ha, dev) { 2040 /* Ask CPM to run CRC and set bit in 2041 * filter mask. 2042 */ 2043 hw_add_addr_in_hash(ugeth, ha->addr); 2044 } 2045 } 2046 } 2047 } 2048 2049 static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2050 { 2051 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2052 struct phy_device *phydev = ugeth->phydev; 2053 2054 ugeth_vdbg("%s: IN", __func__); 2055 2056 /* 2057 * Tell the kernel the link is down. 2058 * Must be done before disabling the controller 2059 * or deadlock may happen. 2060 */ 2061 phy_stop(phydev); 2062 2063 /* Disable the controller */ 2064 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2065 2066 /* Mask all interrupts */ 2067 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2068 2069 /* Clear all interrupts */ 2070 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2071 2072 /* Disable Rx and Tx */ 2073 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2074 2075 ucc_geth_memclean(ugeth); 2076 } 2077 2078 static int ucc_struct_init(struct ucc_geth_private *ugeth) 2079 { 2080 struct ucc_geth_info *ug_info; 2081 struct ucc_fast_info *uf_info; 2082 int i; 2083 2084 ug_info = ugeth->ug_info; 2085 uf_info = &ug_info->uf_info; 2086 2087 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2088 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2089 if (netif_msg_probe(ugeth)) 2090 pr_err("Bad memory partition value\n"); 2091 return -EINVAL; 2092 } 2093 2094 /* Rx BD lengths */ 2095 for (i = 0; i < ug_info->numQueuesRx; i++) { 2096 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2097 (ug_info->bdRingLenRx[i] % 2098 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2099 if (netif_msg_probe(ugeth)) 2100 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 2101 return -EINVAL; 2102 } 2103 } 2104 2105 /* Tx BD lengths */ 2106 for (i = 0; i < ug_info->numQueuesTx; i++) { 2107 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2108 if (netif_msg_probe(ugeth)) 2109 pr_err("Tx BD ring length must be no smaller than 2\n"); 2110 return -EINVAL; 2111 } 2112 } 2113 2114 /* mrblr */ 2115 if ((uf_info->max_rx_buf_length == 0) || 2116 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2117 if (netif_msg_probe(ugeth)) 2118 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 2119 return -EINVAL; 2120 } 2121 2122 /* num Tx queues */ 2123 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2124 if (netif_msg_probe(ugeth)) 2125 pr_err("number of tx queues too large\n"); 2126 return -EINVAL; 2127 } 2128 2129 /* num Rx queues */ 2130 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2131 if (netif_msg_probe(ugeth)) 2132 pr_err("number of rx queues too large\n"); 2133 return -EINVAL; 2134 } 2135 2136 /* l2qt */ 2137 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2138 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2139 if (netif_msg_probe(ugeth)) 2140 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 2141 return -EINVAL; 2142 } 2143 } 2144 2145 /* l3qt */ 2146 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2147 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2148 if (netif_msg_probe(ugeth)) 2149 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 2150 return -EINVAL; 2151 } 2152 } 2153 2154 if (ug_info->cam && !ug_info->ecamptr) { 2155 if (netif_msg_probe(ugeth)) 2156 pr_err("If cam mode is chosen, must supply cam ptr\n"); 2157 return -EINVAL; 2158 } 2159 2160 if ((ug_info->numStationAddresses != 2161 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2162 ug_info->rxExtendedFiltering) { 2163 if (netif_msg_probe(ugeth)) 2164 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2165 return -EINVAL; 2166 } 2167 2168 /* Generate uccm_mask for receive */ 2169 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2170 for (i = 0; i < ug_info->numQueuesRx; i++) 2171 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2172 2173 for (i = 0; i < ug_info->numQueuesTx; i++) 2174 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2175 /* Initialize the general fast UCC block. */ 2176 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2177 if (netif_msg_probe(ugeth)) 2178 pr_err("Failed to init uccf\n"); 2179 return -ENOMEM; 2180 } 2181 2182 /* read the number of risc engines, update the riscTx and riscRx 2183 * if there are 4 riscs in QE 2184 */ 2185 if (qe_get_num_of_risc() == 4) { 2186 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2187 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2188 } 2189 2190 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2191 if (!ugeth->ug_regs) { 2192 if (netif_msg_probe(ugeth)) 2193 pr_err("Failed to ioremap regs\n"); 2194 return -ENOMEM; 2195 } 2196 2197 return 0; 2198 } 2199 2200 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2201 { 2202 struct ucc_geth_info *ug_info; 2203 struct ucc_fast_info *uf_info; 2204 int length; 2205 u16 i, j; 2206 u8 __iomem *bd; 2207 2208 ug_info = ugeth->ug_info; 2209 uf_info = &ug_info->uf_info; 2210 2211 /* Allocate Tx bds */ 2212 for (j = 0; j < ug_info->numQueuesTx; j++) { 2213 /* Allocate in multiple of 2214 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2215 according to spec */ 2216 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2217 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2218 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2219 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2220 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2221 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2222 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2223 u32 align = 4; 2224 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2225 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2226 ugeth->tx_bd_ring_offset[j] = 2227 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2228 2229 if (ugeth->tx_bd_ring_offset[j] != 0) 2230 ugeth->p_tx_bd_ring[j] = 2231 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2232 align) & ~(align - 1)); 2233 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2234 ugeth->tx_bd_ring_offset[j] = 2235 qe_muram_alloc(length, 2236 UCC_GETH_TX_BD_RING_ALIGNMENT); 2237 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2238 ugeth->p_tx_bd_ring[j] = 2239 (u8 __iomem *) qe_muram_addr(ugeth-> 2240 tx_bd_ring_offset[j]); 2241 } 2242 if (!ugeth->p_tx_bd_ring[j]) { 2243 if (netif_msg_ifup(ugeth)) 2244 pr_err("Can not allocate memory for Tx bd rings\n"); 2245 return -ENOMEM; 2246 } 2247 /* Zero unused end of bd ring, according to spec */ 2248 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2249 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2250 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2251 } 2252 2253 /* Init Tx bds */ 2254 for (j = 0; j < ug_info->numQueuesTx; j++) { 2255 /* Setup the skbuff rings */ 2256 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2257 ugeth->ug_info->bdRingLenTx[j], 2258 GFP_KERNEL); 2259 2260 if (ugeth->tx_skbuff[j] == NULL) { 2261 if (netif_msg_ifup(ugeth)) 2262 pr_err("Could not allocate tx_skbuff\n"); 2263 return -ENOMEM; 2264 } 2265 2266 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2267 ugeth->tx_skbuff[j][i] = NULL; 2268 2269 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2270 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2271 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2272 /* clear bd buffer */ 2273 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2274 /* set bd status and length */ 2275 out_be32((u32 __iomem *)bd, 0); 2276 bd += sizeof(struct qe_bd); 2277 } 2278 bd -= sizeof(struct qe_bd); 2279 /* set bd status and length */ 2280 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2281 } 2282 2283 return 0; 2284 } 2285 2286 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2287 { 2288 struct ucc_geth_info *ug_info; 2289 struct ucc_fast_info *uf_info; 2290 int length; 2291 u16 i, j; 2292 u8 __iomem *bd; 2293 2294 ug_info = ugeth->ug_info; 2295 uf_info = &ug_info->uf_info; 2296 2297 /* Allocate Rx bds */ 2298 for (j = 0; j < ug_info->numQueuesRx; j++) { 2299 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2300 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2301 u32 align = 4; 2302 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2303 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2304 ugeth->rx_bd_ring_offset[j] = 2305 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2306 if (ugeth->rx_bd_ring_offset[j] != 0) 2307 ugeth->p_rx_bd_ring[j] = 2308 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2309 align) & ~(align - 1)); 2310 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2311 ugeth->rx_bd_ring_offset[j] = 2312 qe_muram_alloc(length, 2313 UCC_GETH_RX_BD_RING_ALIGNMENT); 2314 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2315 ugeth->p_rx_bd_ring[j] = 2316 (u8 __iomem *) qe_muram_addr(ugeth-> 2317 rx_bd_ring_offset[j]); 2318 } 2319 if (!ugeth->p_rx_bd_ring[j]) { 2320 if (netif_msg_ifup(ugeth)) 2321 pr_err("Can not allocate memory for Rx bd rings\n"); 2322 return -ENOMEM; 2323 } 2324 } 2325 2326 /* Init Rx bds */ 2327 for (j = 0; j < ug_info->numQueuesRx; j++) { 2328 /* Setup the skbuff rings */ 2329 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2330 ugeth->ug_info->bdRingLenRx[j], 2331 GFP_KERNEL); 2332 2333 if (ugeth->rx_skbuff[j] == NULL) { 2334 if (netif_msg_ifup(ugeth)) 2335 pr_err("Could not allocate rx_skbuff\n"); 2336 return -ENOMEM; 2337 } 2338 2339 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2340 ugeth->rx_skbuff[j][i] = NULL; 2341 2342 ugeth->skb_currx[j] = 0; 2343 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2344 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2345 /* set bd status and length */ 2346 out_be32((u32 __iomem *)bd, R_I); 2347 /* clear bd buffer */ 2348 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2349 bd += sizeof(struct qe_bd); 2350 } 2351 bd -= sizeof(struct qe_bd); 2352 /* set bd status and length */ 2353 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2360 { 2361 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2362 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2363 struct ucc_fast_private *uccf; 2364 struct ucc_geth_info *ug_info; 2365 struct ucc_fast_info *uf_info; 2366 struct ucc_fast __iomem *uf_regs; 2367 struct ucc_geth __iomem *ug_regs; 2368 int ret_val = -EINVAL; 2369 u32 remoder = UCC_GETH_REMODER_INIT; 2370 u32 init_enet_pram_offset, cecr_subblock, command; 2371 u32 ifstat, i, j, size, l2qt, l3qt; 2372 u16 temoder = UCC_GETH_TEMODER_INIT; 2373 u16 test; 2374 u8 function_code = 0; 2375 u8 __iomem *endOfRing; 2376 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2377 2378 ugeth_vdbg("%s: IN", __func__); 2379 uccf = ugeth->uccf; 2380 ug_info = ugeth->ug_info; 2381 uf_info = &ug_info->uf_info; 2382 uf_regs = uccf->uf_regs; 2383 ug_regs = ugeth->ug_regs; 2384 2385 switch (ug_info->numThreadsRx) { 2386 case UCC_GETH_NUM_OF_THREADS_1: 2387 numThreadsRxNumerical = 1; 2388 break; 2389 case UCC_GETH_NUM_OF_THREADS_2: 2390 numThreadsRxNumerical = 2; 2391 break; 2392 case UCC_GETH_NUM_OF_THREADS_4: 2393 numThreadsRxNumerical = 4; 2394 break; 2395 case UCC_GETH_NUM_OF_THREADS_6: 2396 numThreadsRxNumerical = 6; 2397 break; 2398 case UCC_GETH_NUM_OF_THREADS_8: 2399 numThreadsRxNumerical = 8; 2400 break; 2401 default: 2402 if (netif_msg_ifup(ugeth)) 2403 pr_err("Bad number of Rx threads value\n"); 2404 return -EINVAL; 2405 break; 2406 } 2407 2408 switch (ug_info->numThreadsTx) { 2409 case UCC_GETH_NUM_OF_THREADS_1: 2410 numThreadsTxNumerical = 1; 2411 break; 2412 case UCC_GETH_NUM_OF_THREADS_2: 2413 numThreadsTxNumerical = 2; 2414 break; 2415 case UCC_GETH_NUM_OF_THREADS_4: 2416 numThreadsTxNumerical = 4; 2417 break; 2418 case UCC_GETH_NUM_OF_THREADS_6: 2419 numThreadsTxNumerical = 6; 2420 break; 2421 case UCC_GETH_NUM_OF_THREADS_8: 2422 numThreadsTxNumerical = 8; 2423 break; 2424 default: 2425 if (netif_msg_ifup(ugeth)) 2426 pr_err("Bad number of Tx threads value\n"); 2427 return -EINVAL; 2428 break; 2429 } 2430 2431 /* Calculate rx_extended_features */ 2432 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2433 ug_info->ipAddressAlignment || 2434 (ug_info->numStationAddresses != 2435 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2436 2437 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2438 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2439 (ug_info->vlanOperationNonTagged != 2440 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2441 2442 init_default_reg_vals(&uf_regs->upsmr, 2443 &ug_regs->maccfg1, &ug_regs->maccfg2); 2444 2445 /* Set UPSMR */ 2446 /* For more details see the hardware spec. */ 2447 init_rx_parameters(ug_info->bro, 2448 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2449 2450 /* We're going to ignore other registers for now, */ 2451 /* except as needed to get up and running */ 2452 2453 /* Set MACCFG1 */ 2454 /* For more details see the hardware spec. */ 2455 init_flow_control_params(ug_info->aufc, 2456 ug_info->receiveFlowControl, 2457 ug_info->transmitFlowControl, 2458 ug_info->pausePeriod, 2459 ug_info->extensionField, 2460 &uf_regs->upsmr, 2461 &ug_regs->uempr, &ug_regs->maccfg1); 2462 2463 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2464 2465 /* Set IPGIFG */ 2466 /* For more details see the hardware spec. */ 2467 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2468 ug_info->nonBackToBackIfgPart2, 2469 ug_info-> 2470 miminumInterFrameGapEnforcement, 2471 ug_info->backToBackInterFrameGap, 2472 &ug_regs->ipgifg); 2473 if (ret_val != 0) { 2474 if (netif_msg_ifup(ugeth)) 2475 pr_err("IPGIFG initialization parameter too large\n"); 2476 return ret_val; 2477 } 2478 2479 /* Set HAFDUP */ 2480 /* For more details see the hardware spec. */ 2481 ret_val = init_half_duplex_params(ug_info->altBeb, 2482 ug_info->backPressureNoBackoff, 2483 ug_info->noBackoff, 2484 ug_info->excessDefer, 2485 ug_info->altBebTruncation, 2486 ug_info->maxRetransmission, 2487 ug_info->collisionWindow, 2488 &ug_regs->hafdup); 2489 if (ret_val != 0) { 2490 if (netif_msg_ifup(ugeth)) 2491 pr_err("Half Duplex initialization parameter too large\n"); 2492 return ret_val; 2493 } 2494 2495 /* Set IFSTAT */ 2496 /* For more details see the hardware spec. */ 2497 /* Read only - resets upon read */ 2498 ifstat = in_be32(&ug_regs->ifstat); 2499 2500 /* Clear UEMPR */ 2501 /* For more details see the hardware spec. */ 2502 out_be32(&ug_regs->uempr, 0); 2503 2504 /* Set UESCR */ 2505 /* For more details see the hardware spec. */ 2506 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2507 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2508 0, &uf_regs->upsmr, &ug_regs->uescr); 2509 2510 ret_val = ucc_geth_alloc_tx(ugeth); 2511 if (ret_val != 0) 2512 return ret_val; 2513 2514 ret_val = ucc_geth_alloc_rx(ugeth); 2515 if (ret_val != 0) 2516 return ret_val; 2517 2518 /* 2519 * Global PRAM 2520 */ 2521 /* Tx global PRAM */ 2522 /* Allocate global tx parameter RAM page */ 2523 ugeth->tx_glbl_pram_offset = 2524 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2525 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2526 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2527 if (netif_msg_ifup(ugeth)) 2528 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2529 return -ENOMEM; 2530 } 2531 ugeth->p_tx_glbl_pram = 2532 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2533 tx_glbl_pram_offset); 2534 /* Zero out p_tx_glbl_pram */ 2535 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2536 2537 /* Fill global PRAM */ 2538 2539 /* TQPTR */ 2540 /* Size varies with number of Tx threads */ 2541 ugeth->thread_dat_tx_offset = 2542 qe_muram_alloc(numThreadsTxNumerical * 2543 sizeof(struct ucc_geth_thread_data_tx) + 2544 32 * (numThreadsTxNumerical == 1), 2545 UCC_GETH_THREAD_DATA_ALIGNMENT); 2546 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2547 if (netif_msg_ifup(ugeth)) 2548 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2549 return -ENOMEM; 2550 } 2551 2552 ugeth->p_thread_data_tx = 2553 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2554 thread_dat_tx_offset); 2555 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2556 2557 /* vtagtable */ 2558 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2559 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2560 ug_info->vtagtable[i]); 2561 2562 /* iphoffset */ 2563 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2564 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2565 ug_info->iphoffset[i]); 2566 2567 /* SQPTR */ 2568 /* Size varies with number of Tx queues */ 2569 ugeth->send_q_mem_reg_offset = 2570 qe_muram_alloc(ug_info->numQueuesTx * 2571 sizeof(struct ucc_geth_send_queue_qd), 2572 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2573 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2574 if (netif_msg_ifup(ugeth)) 2575 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2576 return -ENOMEM; 2577 } 2578 2579 ugeth->p_send_q_mem_reg = 2580 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2581 send_q_mem_reg_offset); 2582 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2583 2584 /* Setup the table */ 2585 /* Assume BD rings are already established */ 2586 for (i = 0; i < ug_info->numQueuesTx; i++) { 2587 endOfRing = 2588 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2589 1) * sizeof(struct qe_bd); 2590 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2591 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2592 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2594 last_bd_completed_address, 2595 (u32) virt_to_phys(endOfRing)); 2596 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2597 MEM_PART_MURAM) { 2598 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2599 (u32) immrbar_virt_to_phys(ugeth-> 2600 p_tx_bd_ring[i])); 2601 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2602 last_bd_completed_address, 2603 (u32) immrbar_virt_to_phys(endOfRing)); 2604 } 2605 } 2606 2607 /* schedulerbasepointer */ 2608 2609 if (ug_info->numQueuesTx > 1) { 2610 /* scheduler exists only if more than 1 tx queue */ 2611 ugeth->scheduler_offset = 2612 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2613 UCC_GETH_SCHEDULER_ALIGNMENT); 2614 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2615 if (netif_msg_ifup(ugeth)) 2616 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2617 return -ENOMEM; 2618 } 2619 2620 ugeth->p_scheduler = 2621 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2622 scheduler_offset); 2623 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2624 ugeth->scheduler_offset); 2625 /* Zero out p_scheduler */ 2626 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2627 2628 /* Set values in scheduler */ 2629 out_be32(&ugeth->p_scheduler->mblinterval, 2630 ug_info->mblinterval); 2631 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2632 ug_info->nortsrbytetime); 2633 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2634 out_8(&ugeth->p_scheduler->strictpriorityq, 2635 ug_info->strictpriorityq); 2636 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2637 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2638 for (i = 0; i < NUM_TX_QUEUES; i++) 2639 out_8(&ugeth->p_scheduler->weightfactor[i], 2640 ug_info->weightfactor[i]); 2641 2642 /* Set pointers to cpucount registers in scheduler */ 2643 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2644 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2645 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2646 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2647 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2648 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2649 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2650 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2651 } 2652 2653 /* schedulerbasepointer */ 2654 /* TxRMON_PTR (statistics) */ 2655 if (ug_info-> 2656 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2657 ugeth->tx_fw_statistics_pram_offset = 2658 qe_muram_alloc(sizeof 2659 (struct ucc_geth_tx_firmware_statistics_pram), 2660 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2661 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2662 if (netif_msg_ifup(ugeth)) 2663 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2664 return -ENOMEM; 2665 } 2666 ugeth->p_tx_fw_statistics_pram = 2667 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2668 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2669 /* Zero out p_tx_fw_statistics_pram */ 2670 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2671 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2672 } 2673 2674 /* temoder */ 2675 /* Already has speed set */ 2676 2677 if (ug_info->numQueuesTx > 1) 2678 temoder |= TEMODER_SCHEDULER_ENABLE; 2679 if (ug_info->ipCheckSumGenerate) 2680 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2681 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2682 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2683 2684 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2685 2686 /* Function code register value to be used later */ 2687 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2688 /* Required for QE */ 2689 2690 /* function code register */ 2691 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2692 2693 /* Rx global PRAM */ 2694 /* Allocate global rx parameter RAM page */ 2695 ugeth->rx_glbl_pram_offset = 2696 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2697 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2698 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2699 if (netif_msg_ifup(ugeth)) 2700 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2701 return -ENOMEM; 2702 } 2703 ugeth->p_rx_glbl_pram = 2704 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2705 rx_glbl_pram_offset); 2706 /* Zero out p_rx_glbl_pram */ 2707 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2708 2709 /* Fill global PRAM */ 2710 2711 /* RQPTR */ 2712 /* Size varies with number of Rx threads */ 2713 ugeth->thread_dat_rx_offset = 2714 qe_muram_alloc(numThreadsRxNumerical * 2715 sizeof(struct ucc_geth_thread_data_rx), 2716 UCC_GETH_THREAD_DATA_ALIGNMENT); 2717 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2718 if (netif_msg_ifup(ugeth)) 2719 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2720 return -ENOMEM; 2721 } 2722 2723 ugeth->p_thread_data_rx = 2724 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2725 thread_dat_rx_offset); 2726 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2727 2728 /* typeorlen */ 2729 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2730 2731 /* rxrmonbaseptr (statistics) */ 2732 if (ug_info-> 2733 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2734 ugeth->rx_fw_statistics_pram_offset = 2735 qe_muram_alloc(sizeof 2736 (struct ucc_geth_rx_firmware_statistics_pram), 2737 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2738 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2739 if (netif_msg_ifup(ugeth)) 2740 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2741 return -ENOMEM; 2742 } 2743 ugeth->p_rx_fw_statistics_pram = 2744 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2745 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2746 /* Zero out p_rx_fw_statistics_pram */ 2747 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2748 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2749 } 2750 2751 /* intCoalescingPtr */ 2752 2753 /* Size varies with number of Rx queues */ 2754 ugeth->rx_irq_coalescing_tbl_offset = 2755 qe_muram_alloc(ug_info->numQueuesRx * 2756 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2757 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2758 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2759 if (netif_msg_ifup(ugeth)) 2760 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2761 return -ENOMEM; 2762 } 2763 2764 ugeth->p_rx_irq_coalescing_tbl = 2765 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2766 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2767 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2768 ugeth->rx_irq_coalescing_tbl_offset); 2769 2770 /* Fill interrupt coalescing table */ 2771 for (i = 0; i < ug_info->numQueuesRx; i++) { 2772 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2773 interruptcoalescingmaxvalue, 2774 ug_info->interruptcoalescingmaxvalue[i]); 2775 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2776 interruptcoalescingcounter, 2777 ug_info->interruptcoalescingmaxvalue[i]); 2778 } 2779 2780 /* MRBLR */ 2781 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2782 &ugeth->p_rx_glbl_pram->mrblr); 2783 /* MFLR */ 2784 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2785 /* MINFLR */ 2786 init_min_frame_len(ug_info->minFrameLength, 2787 &ugeth->p_rx_glbl_pram->minflr, 2788 &ugeth->p_rx_glbl_pram->mrblr); 2789 /* MAXD1 */ 2790 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2791 /* MAXD2 */ 2792 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2793 2794 /* l2qt */ 2795 l2qt = 0; 2796 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2797 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2798 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2799 2800 /* l3qt */ 2801 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2802 l3qt = 0; 2803 for (i = 0; i < 8; i++) 2804 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2805 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2806 } 2807 2808 /* vlantype */ 2809 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2810 2811 /* vlantci */ 2812 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2813 2814 /* ecamptr */ 2815 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2816 2817 /* RBDQPTR */ 2818 /* Size varies with number of Rx queues */ 2819 ugeth->rx_bd_qs_tbl_offset = 2820 qe_muram_alloc(ug_info->numQueuesRx * 2821 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2822 sizeof(struct ucc_geth_rx_prefetched_bds)), 2823 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2824 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2825 if (netif_msg_ifup(ugeth)) 2826 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2827 return -ENOMEM; 2828 } 2829 2830 ugeth->p_rx_bd_qs_tbl = 2831 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2832 rx_bd_qs_tbl_offset); 2833 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2834 /* Zero out p_rx_bd_qs_tbl */ 2835 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2836 0, 2837 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2838 sizeof(struct ucc_geth_rx_prefetched_bds))); 2839 2840 /* Setup the table */ 2841 /* Assume BD rings are already established */ 2842 for (i = 0; i < ug_info->numQueuesRx; i++) { 2843 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2844 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2845 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2846 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2847 MEM_PART_MURAM) { 2848 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2849 (u32) immrbar_virt_to_phys(ugeth-> 2850 p_rx_bd_ring[i])); 2851 } 2852 /* rest of fields handled by QE */ 2853 } 2854 2855 /* remoder */ 2856 /* Already has speed set */ 2857 2858 if (ugeth->rx_extended_features) 2859 remoder |= REMODER_RX_EXTENDED_FEATURES; 2860 if (ug_info->rxExtendedFiltering) 2861 remoder |= REMODER_RX_EXTENDED_FILTERING; 2862 if (ug_info->dynamicMaxFrameLength) 2863 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2864 if (ug_info->dynamicMinFrameLength) 2865 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2866 remoder |= 2867 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2868 remoder |= 2869 ug_info-> 2870 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2871 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2872 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2873 if (ug_info->ipCheckSumCheck) 2874 remoder |= REMODER_IP_CHECKSUM_CHECK; 2875 if (ug_info->ipAddressAlignment) 2876 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2877 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2878 2879 /* Note that this function must be called */ 2880 /* ONLY AFTER p_tx_fw_statistics_pram */ 2881 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2882 init_firmware_statistics_gathering_mode((ug_info-> 2883 statisticsMode & 2884 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2885 (ug_info->statisticsMode & 2886 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2887 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2888 ugeth->tx_fw_statistics_pram_offset, 2889 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2890 ugeth->rx_fw_statistics_pram_offset, 2891 &ugeth->p_tx_glbl_pram->temoder, 2892 &ugeth->p_rx_glbl_pram->remoder); 2893 2894 /* function code register */ 2895 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2896 2897 /* initialize extended filtering */ 2898 if (ug_info->rxExtendedFiltering) { 2899 if (!ug_info->extendedFilteringChainPointer) { 2900 if (netif_msg_ifup(ugeth)) 2901 pr_err("Null Extended Filtering Chain Pointer\n"); 2902 return -EINVAL; 2903 } 2904 2905 /* Allocate memory for extended filtering Mode Global 2906 Parameters */ 2907 ugeth->exf_glbl_param_offset = 2908 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2909 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2910 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2911 if (netif_msg_ifup(ugeth)) 2912 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2913 return -ENOMEM; 2914 } 2915 2916 ugeth->p_exf_glbl_param = 2917 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2918 exf_glbl_param_offset); 2919 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2920 ugeth->exf_glbl_param_offset); 2921 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2922 (u32) ug_info->extendedFilteringChainPointer); 2923 2924 } else { /* initialize 82xx style address filtering */ 2925 2926 /* Init individual address recognition registers to disabled */ 2927 2928 for (j = 0; j < NUM_OF_PADDRS; j++) 2929 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2930 2931 p_82xx_addr_filt = 2932 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2933 p_rx_glbl_pram->addressfiltering; 2934 2935 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2936 ENET_ADDR_TYPE_GROUP); 2937 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2938 ENET_ADDR_TYPE_INDIVIDUAL); 2939 } 2940 2941 /* 2942 * Initialize UCC at QE level 2943 */ 2944 2945 command = QE_INIT_TX_RX; 2946 2947 /* Allocate shadow InitEnet command parameter structure. 2948 * This is needed because after the InitEnet command is executed, 2949 * the structure in DPRAM is released, because DPRAM is a premium 2950 * resource. 2951 * This shadow structure keeps a copy of what was done so that the 2952 * allocated resources can be released when the channel is freed. 2953 */ 2954 if (!(ugeth->p_init_enet_param_shadow = 2955 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2956 if (netif_msg_ifup(ugeth)) 2957 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2958 return -ENOMEM; 2959 } 2960 /* Zero out *p_init_enet_param_shadow */ 2961 memset((char *)ugeth->p_init_enet_param_shadow, 2962 0, sizeof(struct ucc_geth_init_pram)); 2963 2964 /* Fill shadow InitEnet command parameter structure */ 2965 2966 ugeth->p_init_enet_param_shadow->resinit1 = 2967 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2968 ugeth->p_init_enet_param_shadow->resinit2 = 2969 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2970 ugeth->p_init_enet_param_shadow->resinit3 = 2971 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2972 ugeth->p_init_enet_param_shadow->resinit4 = 2973 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2974 ugeth->p_init_enet_param_shadow->resinit5 = 2975 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2976 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2977 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2978 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2979 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2980 2981 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2982 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2983 if ((ug_info->largestexternallookupkeysize != 2984 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2985 (ug_info->largestexternallookupkeysize != 2986 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2987 (ug_info->largestexternallookupkeysize != 2988 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2989 if (netif_msg_ifup(ugeth)) 2990 pr_err("Invalid largest External Lookup Key Size\n"); 2991 return -EINVAL; 2992 } 2993 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2994 ug_info->largestexternallookupkeysize; 2995 size = sizeof(struct ucc_geth_thread_rx_pram); 2996 if (ug_info->rxExtendedFiltering) { 2997 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 2998 if (ug_info->largestexternallookupkeysize == 2999 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 3000 size += 3001 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 3002 if (ug_info->largestexternallookupkeysize == 3003 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 3004 size += 3005 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 3006 } 3007 3008 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 3009 p_init_enet_param_shadow->rxthread[0]), 3010 (u8) (numThreadsRxNumerical + 1) 3011 /* Rx needs one extra for terminator */ 3012 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3013 ug_info->riscRx, 1)) != 0) { 3014 if (netif_msg_ifup(ugeth)) 3015 pr_err("Can not fill p_init_enet_param_shadow\n"); 3016 return ret_val; 3017 } 3018 3019 ugeth->p_init_enet_param_shadow->txglobal = 3020 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3021 if ((ret_val = 3022 fill_init_enet_entries(ugeth, 3023 &(ugeth->p_init_enet_param_shadow-> 3024 txthread[0]), numThreadsTxNumerical, 3025 sizeof(struct ucc_geth_thread_tx_pram), 3026 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3027 ug_info->riscTx, 0)) != 0) { 3028 if (netif_msg_ifup(ugeth)) 3029 pr_err("Can not fill p_init_enet_param_shadow\n"); 3030 return ret_val; 3031 } 3032 3033 /* Load Rx bds with buffers */ 3034 for (i = 0; i < ug_info->numQueuesRx; i++) { 3035 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3036 if (netif_msg_ifup(ugeth)) 3037 pr_err("Can not fill Rx bds with buffers\n"); 3038 return ret_val; 3039 } 3040 } 3041 3042 /* Allocate InitEnet command parameter structure */ 3043 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3044 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3045 if (netif_msg_ifup(ugeth)) 3046 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 3047 return -ENOMEM; 3048 } 3049 p_init_enet_pram = 3050 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3051 3052 /* Copy shadow InitEnet command parameter structure into PRAM */ 3053 out_8(&p_init_enet_pram->resinit1, 3054 ugeth->p_init_enet_param_shadow->resinit1); 3055 out_8(&p_init_enet_pram->resinit2, 3056 ugeth->p_init_enet_param_shadow->resinit2); 3057 out_8(&p_init_enet_pram->resinit3, 3058 ugeth->p_init_enet_param_shadow->resinit3); 3059 out_8(&p_init_enet_pram->resinit4, 3060 ugeth->p_init_enet_param_shadow->resinit4); 3061 out_be16(&p_init_enet_pram->resinit5, 3062 ugeth->p_init_enet_param_shadow->resinit5); 3063 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3064 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3065 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3066 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3067 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3068 out_be32(&p_init_enet_pram->rxthread[i], 3069 ugeth->p_init_enet_param_shadow->rxthread[i]); 3070 out_be32(&p_init_enet_pram->txglobal, 3071 ugeth->p_init_enet_param_shadow->txglobal); 3072 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3073 out_be32(&p_init_enet_pram->txthread[i], 3074 ugeth->p_init_enet_param_shadow->txthread[i]); 3075 3076 /* Issue QE command */ 3077 cecr_subblock = 3078 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3079 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3080 init_enet_pram_offset); 3081 3082 /* Free InitEnet command parameter */ 3083 qe_muram_free(init_enet_pram_offset); 3084 3085 return 0; 3086 } 3087 3088 /* This is called by the kernel when a frame is ready for transmission. */ 3089 /* It is pointed to by the dev->hard_start_xmit function pointer */ 3090 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3091 { 3092 struct ucc_geth_private *ugeth = netdev_priv(dev); 3093 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3094 struct ucc_fast_private *uccf; 3095 #endif 3096 u8 __iomem *bd; /* BD pointer */ 3097 u32 bd_status; 3098 u8 txQ = 0; 3099 unsigned long flags; 3100 3101 ugeth_vdbg("%s: IN", __func__); 3102 3103 spin_lock_irqsave(&ugeth->lock, flags); 3104 3105 dev->stats.tx_bytes += skb->len; 3106 3107 /* Start from the next BD that should be filled */ 3108 bd = ugeth->txBd[txQ]; 3109 bd_status = in_be32((u32 __iomem *)bd); 3110 /* Save the skb pointer so we can free it later */ 3111 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3112 3113 /* Update the current skb pointer (wrapping if this was the last) */ 3114 ugeth->skb_curtx[txQ] = 3115 (ugeth->skb_curtx[txQ] + 3116 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3117 3118 /* set up the buffer descriptor */ 3119 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3120 dma_map_single(ugeth->dev, skb->data, 3121 skb->len, DMA_TO_DEVICE)); 3122 3123 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3124 3125 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3126 3127 /* set bd status and length */ 3128 out_be32((u32 __iomem *)bd, bd_status); 3129 3130 /* Move to next BD in the ring */ 3131 if (!(bd_status & T_W)) 3132 bd += sizeof(struct qe_bd); 3133 else 3134 bd = ugeth->p_tx_bd_ring[txQ]; 3135 3136 /* If the next BD still needs to be cleaned up, then the bds 3137 are full. We need to tell the kernel to stop sending us stuff. */ 3138 if (bd == ugeth->confBd[txQ]) { 3139 if (!netif_queue_stopped(dev)) 3140 netif_stop_queue(dev); 3141 } 3142 3143 ugeth->txBd[txQ] = bd; 3144 3145 skb_tx_timestamp(skb); 3146 3147 if (ugeth->p_scheduler) { 3148 ugeth->cpucount[txQ]++; 3149 /* Indicate to QE that there are more Tx bds ready for 3150 transmission */ 3151 /* This is done by writing a running counter of the bd 3152 count to the scheduler PRAM. */ 3153 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3154 } 3155 3156 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3157 uccf = ugeth->uccf; 3158 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3159 #endif 3160 spin_unlock_irqrestore(&ugeth->lock, flags); 3161 3162 return NETDEV_TX_OK; 3163 } 3164 3165 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3166 { 3167 struct sk_buff *skb; 3168 u8 __iomem *bd; 3169 u16 length, howmany = 0; 3170 u32 bd_status; 3171 u8 *bdBuffer; 3172 struct net_device *dev; 3173 3174 ugeth_vdbg("%s: IN", __func__); 3175 3176 dev = ugeth->ndev; 3177 3178 /* collect received buffers */ 3179 bd = ugeth->rxBd[rxQ]; 3180 3181 bd_status = in_be32((u32 __iomem *)bd); 3182 3183 /* while there are received buffers and BD is full (~R_E) */ 3184 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3185 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3186 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3187 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3188 3189 /* determine whether buffer is first, last, first and last 3190 (single buffer frame) or middle (not first and not last) */ 3191 if (!skb || 3192 (!(bd_status & (R_F | R_L))) || 3193 (bd_status & R_ERRORS_FATAL)) { 3194 if (netif_msg_rx_err(ugeth)) 3195 pr_err("%d: ERROR!!! skb - 0x%08x\n", 3196 __LINE__, (u32)skb); 3197 dev_kfree_skb(skb); 3198 3199 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3200 dev->stats.rx_dropped++; 3201 } else { 3202 dev->stats.rx_packets++; 3203 howmany++; 3204 3205 /* Prep the skb for the packet */ 3206 skb_put(skb, length); 3207 3208 /* Tell the skb what kind of packet this is */ 3209 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3210 3211 dev->stats.rx_bytes += length; 3212 /* Send the packet up the stack */ 3213 netif_receive_skb(skb); 3214 } 3215 3216 skb = get_new_skb(ugeth, bd); 3217 if (!skb) { 3218 if (netif_msg_rx_err(ugeth)) 3219 pr_warn("No Rx Data Buffer\n"); 3220 dev->stats.rx_dropped++; 3221 break; 3222 } 3223 3224 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3225 3226 /* update to point at the next skb */ 3227 ugeth->skb_currx[rxQ] = 3228 (ugeth->skb_currx[rxQ] + 3229 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3230 3231 if (bd_status & R_W) 3232 bd = ugeth->p_rx_bd_ring[rxQ]; 3233 else 3234 bd += sizeof(struct qe_bd); 3235 3236 bd_status = in_be32((u32 __iomem *)bd); 3237 } 3238 3239 ugeth->rxBd[rxQ] = bd; 3240 return howmany; 3241 } 3242 3243 static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3244 { 3245 /* Start from the next BD that should be filled */ 3246 struct ucc_geth_private *ugeth = netdev_priv(dev); 3247 u8 __iomem *bd; /* BD pointer */ 3248 u32 bd_status; 3249 3250 bd = ugeth->confBd[txQ]; 3251 bd_status = in_be32((u32 __iomem *)bd); 3252 3253 /* Normal processing. */ 3254 while ((bd_status & T_R) == 0) { 3255 struct sk_buff *skb; 3256 3257 /* BD contains already transmitted buffer. */ 3258 /* Handle the transmitted buffer and release */ 3259 /* the BD to be used with the current frame */ 3260 3261 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3262 if (!skb) 3263 break; 3264 3265 dev->stats.tx_packets++; 3266 3267 dev_kfree_skb(skb); 3268 3269 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3270 ugeth->skb_dirtytx[txQ] = 3271 (ugeth->skb_dirtytx[txQ] + 3272 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3273 3274 /* We freed a buffer, so now we can restart transmission */ 3275 if (netif_queue_stopped(dev)) 3276 netif_wake_queue(dev); 3277 3278 /* Advance the confirmation BD pointer */ 3279 if (!(bd_status & T_W)) 3280 bd += sizeof(struct qe_bd); 3281 else 3282 bd = ugeth->p_tx_bd_ring[txQ]; 3283 bd_status = in_be32((u32 __iomem *)bd); 3284 } 3285 ugeth->confBd[txQ] = bd; 3286 return 0; 3287 } 3288 3289 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3290 { 3291 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3292 struct ucc_geth_info *ug_info; 3293 int howmany, i; 3294 3295 ug_info = ugeth->ug_info; 3296 3297 /* Tx event processing */ 3298 spin_lock(&ugeth->lock); 3299 for (i = 0; i < ug_info->numQueuesTx; i++) 3300 ucc_geth_tx(ugeth->ndev, i); 3301 spin_unlock(&ugeth->lock); 3302 3303 howmany = 0; 3304 for (i = 0; i < ug_info->numQueuesRx; i++) 3305 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3306 3307 if (howmany < budget) { 3308 napi_complete(napi); 3309 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3310 } 3311 3312 return howmany; 3313 } 3314 3315 static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3316 { 3317 struct net_device *dev = info; 3318 struct ucc_geth_private *ugeth = netdev_priv(dev); 3319 struct ucc_fast_private *uccf; 3320 struct ucc_geth_info *ug_info; 3321 register u32 ucce; 3322 register u32 uccm; 3323 3324 ugeth_vdbg("%s: IN", __func__); 3325 3326 uccf = ugeth->uccf; 3327 ug_info = ugeth->ug_info; 3328 3329 /* read and clear events */ 3330 ucce = (u32) in_be32(uccf->p_ucce); 3331 uccm = (u32) in_be32(uccf->p_uccm); 3332 ucce &= uccm; 3333 out_be32(uccf->p_ucce, ucce); 3334 3335 /* check for receive events that require processing */ 3336 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3337 if (napi_schedule_prep(&ugeth->napi)) { 3338 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3339 out_be32(uccf->p_uccm, uccm); 3340 __napi_schedule(&ugeth->napi); 3341 } 3342 } 3343 3344 /* Errors and other events */ 3345 if (ucce & UCCE_OTHER) { 3346 if (ucce & UCC_GETH_UCCE_BSY) 3347 dev->stats.rx_errors++; 3348 if (ucce & UCC_GETH_UCCE_TXE) 3349 dev->stats.tx_errors++; 3350 } 3351 3352 return IRQ_HANDLED; 3353 } 3354 3355 #ifdef CONFIG_NET_POLL_CONTROLLER 3356 /* 3357 * Polling 'interrupt' - used by things like netconsole to send skbs 3358 * without having to re-enable interrupts. It's not called while 3359 * the interrupt routine is executing. 3360 */ 3361 static void ucc_netpoll(struct net_device *dev) 3362 { 3363 struct ucc_geth_private *ugeth = netdev_priv(dev); 3364 int irq = ugeth->ug_info->uf_info.irq; 3365 3366 disable_irq(irq); 3367 ucc_geth_irq_handler(irq, dev); 3368 enable_irq(irq); 3369 } 3370 #endif /* CONFIG_NET_POLL_CONTROLLER */ 3371 3372 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3373 { 3374 struct ucc_geth_private *ugeth = netdev_priv(dev); 3375 struct sockaddr *addr = p; 3376 3377 if (!is_valid_ether_addr(addr->sa_data)) 3378 return -EADDRNOTAVAIL; 3379 3380 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3381 3382 /* 3383 * If device is not running, we will set mac addr register 3384 * when opening the device. 3385 */ 3386 if (!netif_running(dev)) 3387 return 0; 3388 3389 spin_lock_irq(&ugeth->lock); 3390 init_mac_station_addr_regs(dev->dev_addr[0], 3391 dev->dev_addr[1], 3392 dev->dev_addr[2], 3393 dev->dev_addr[3], 3394 dev->dev_addr[4], 3395 dev->dev_addr[5], 3396 &ugeth->ug_regs->macstnaddr1, 3397 &ugeth->ug_regs->macstnaddr2); 3398 spin_unlock_irq(&ugeth->lock); 3399 3400 return 0; 3401 } 3402 3403 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3404 { 3405 struct net_device *dev = ugeth->ndev; 3406 int err; 3407 3408 err = ucc_struct_init(ugeth); 3409 if (err) { 3410 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3411 goto err; 3412 } 3413 3414 err = ucc_geth_startup(ugeth); 3415 if (err) { 3416 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3417 goto err; 3418 } 3419 3420 err = adjust_enet_interface(ugeth); 3421 if (err) { 3422 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3423 goto err; 3424 } 3425 3426 /* Set MACSTNADDR1, MACSTNADDR2 */ 3427 /* For more details see the hardware spec. */ 3428 init_mac_station_addr_regs(dev->dev_addr[0], 3429 dev->dev_addr[1], 3430 dev->dev_addr[2], 3431 dev->dev_addr[3], 3432 dev->dev_addr[4], 3433 dev->dev_addr[5], 3434 &ugeth->ug_regs->macstnaddr1, 3435 &ugeth->ug_regs->macstnaddr2); 3436 3437 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3438 if (err) { 3439 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n"); 3440 goto err; 3441 } 3442 3443 return 0; 3444 err: 3445 ucc_geth_stop(ugeth); 3446 return err; 3447 } 3448 3449 /* Called when something needs to use the ethernet device */ 3450 /* Returns 0 for success. */ 3451 static int ucc_geth_open(struct net_device *dev) 3452 { 3453 struct ucc_geth_private *ugeth = netdev_priv(dev); 3454 int err; 3455 3456 ugeth_vdbg("%s: IN", __func__); 3457 3458 /* Test station address */ 3459 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3460 netif_err(ugeth, ifup, dev, 3461 "Multicast address used for station address - is this what you wanted?\n"); 3462 return -EINVAL; 3463 } 3464 3465 err = init_phy(dev); 3466 if (err) { 3467 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n"); 3468 return err; 3469 } 3470 3471 err = ucc_geth_init_mac(ugeth); 3472 if (err) { 3473 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3474 goto err; 3475 } 3476 3477 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3478 0, "UCC Geth", dev); 3479 if (err) { 3480 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3481 goto err; 3482 } 3483 3484 phy_start(ugeth->phydev); 3485 napi_enable(&ugeth->napi); 3486 netif_start_queue(dev); 3487 3488 device_set_wakeup_capable(&dev->dev, 3489 qe_alive_during_sleep() || ugeth->phydev->irq); 3490 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3491 3492 return err; 3493 3494 err: 3495 ucc_geth_stop(ugeth); 3496 return err; 3497 } 3498 3499 /* Stops the kernel queue, and halts the controller */ 3500 static int ucc_geth_close(struct net_device *dev) 3501 { 3502 struct ucc_geth_private *ugeth = netdev_priv(dev); 3503 3504 ugeth_vdbg("%s: IN", __func__); 3505 3506 napi_disable(&ugeth->napi); 3507 3508 cancel_work_sync(&ugeth->timeout_work); 3509 ucc_geth_stop(ugeth); 3510 phy_disconnect(ugeth->phydev); 3511 ugeth->phydev = NULL; 3512 3513 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3514 3515 netif_stop_queue(dev); 3516 3517 return 0; 3518 } 3519 3520 /* Reopen device. This will reset the MAC and PHY. */ 3521 static void ucc_geth_timeout_work(struct work_struct *work) 3522 { 3523 struct ucc_geth_private *ugeth; 3524 struct net_device *dev; 3525 3526 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3527 dev = ugeth->ndev; 3528 3529 ugeth_vdbg("%s: IN", __func__); 3530 3531 dev->stats.tx_errors++; 3532 3533 ugeth_dump_regs(ugeth); 3534 3535 if (dev->flags & IFF_UP) { 3536 /* 3537 * Must reset MAC *and* PHY. This is done by reopening 3538 * the device. 3539 */ 3540 netif_tx_stop_all_queues(dev); 3541 ucc_geth_stop(ugeth); 3542 ucc_geth_init_mac(ugeth); 3543 /* Must start PHY here */ 3544 phy_start(ugeth->phydev); 3545 netif_tx_start_all_queues(dev); 3546 } 3547 3548 netif_tx_schedule_all(dev); 3549 } 3550 3551 /* 3552 * ucc_geth_timeout gets called when a packet has not been 3553 * transmitted after a set amount of time. 3554 */ 3555 static void ucc_geth_timeout(struct net_device *dev) 3556 { 3557 struct ucc_geth_private *ugeth = netdev_priv(dev); 3558 3559 schedule_work(&ugeth->timeout_work); 3560 } 3561 3562 3563 #ifdef CONFIG_PM 3564 3565 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3566 { 3567 struct net_device *ndev = platform_get_drvdata(ofdev); 3568 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3569 3570 if (!netif_running(ndev)) 3571 return 0; 3572 3573 netif_device_detach(ndev); 3574 napi_disable(&ugeth->napi); 3575 3576 /* 3577 * Disable the controller, otherwise we'll wakeup on any network 3578 * activity. 3579 */ 3580 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3581 3582 if (ugeth->wol_en & WAKE_MAGIC) { 3583 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3584 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3585 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3586 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3587 phy_stop(ugeth->phydev); 3588 } 3589 3590 return 0; 3591 } 3592 3593 static int ucc_geth_resume(struct platform_device *ofdev) 3594 { 3595 struct net_device *ndev = platform_get_drvdata(ofdev); 3596 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3597 int err; 3598 3599 if (!netif_running(ndev)) 3600 return 0; 3601 3602 if (qe_alive_during_sleep()) { 3603 if (ugeth->wol_en & WAKE_MAGIC) { 3604 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3605 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3606 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3607 } 3608 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3609 } else { 3610 /* 3611 * Full reinitialization is required if QE shuts down 3612 * during sleep. 3613 */ 3614 ucc_geth_memclean(ugeth); 3615 3616 err = ucc_geth_init_mac(ugeth); 3617 if (err) { 3618 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3619 return err; 3620 } 3621 } 3622 3623 ugeth->oldlink = 0; 3624 ugeth->oldspeed = 0; 3625 ugeth->oldduplex = -1; 3626 3627 phy_stop(ugeth->phydev); 3628 phy_start(ugeth->phydev); 3629 3630 napi_enable(&ugeth->napi); 3631 netif_device_attach(ndev); 3632 3633 return 0; 3634 } 3635 3636 #else 3637 #define ucc_geth_suspend NULL 3638 #define ucc_geth_resume NULL 3639 #endif 3640 3641 static phy_interface_t to_phy_interface(const char *phy_connection_type) 3642 { 3643 if (strcasecmp(phy_connection_type, "mii") == 0) 3644 return PHY_INTERFACE_MODE_MII; 3645 if (strcasecmp(phy_connection_type, "gmii") == 0) 3646 return PHY_INTERFACE_MODE_GMII; 3647 if (strcasecmp(phy_connection_type, "tbi") == 0) 3648 return PHY_INTERFACE_MODE_TBI; 3649 if (strcasecmp(phy_connection_type, "rmii") == 0) 3650 return PHY_INTERFACE_MODE_RMII; 3651 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3652 return PHY_INTERFACE_MODE_RGMII; 3653 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3654 return PHY_INTERFACE_MODE_RGMII_ID; 3655 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3656 return PHY_INTERFACE_MODE_RGMII_TXID; 3657 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3658 return PHY_INTERFACE_MODE_RGMII_RXID; 3659 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3660 return PHY_INTERFACE_MODE_RTBI; 3661 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3662 return PHY_INTERFACE_MODE_SGMII; 3663 3664 return PHY_INTERFACE_MODE_MII; 3665 } 3666 3667 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3668 { 3669 struct ucc_geth_private *ugeth = netdev_priv(dev); 3670 3671 if (!netif_running(dev)) 3672 return -EINVAL; 3673 3674 if (!ugeth->phydev) 3675 return -ENODEV; 3676 3677 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3678 } 3679 3680 static const struct net_device_ops ucc_geth_netdev_ops = { 3681 .ndo_open = ucc_geth_open, 3682 .ndo_stop = ucc_geth_close, 3683 .ndo_start_xmit = ucc_geth_start_xmit, 3684 .ndo_validate_addr = eth_validate_addr, 3685 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3686 .ndo_change_mtu = eth_change_mtu, 3687 .ndo_set_rx_mode = ucc_geth_set_multi, 3688 .ndo_tx_timeout = ucc_geth_timeout, 3689 .ndo_do_ioctl = ucc_geth_ioctl, 3690 #ifdef CONFIG_NET_POLL_CONTROLLER 3691 .ndo_poll_controller = ucc_netpoll, 3692 #endif 3693 }; 3694 3695 static int ucc_geth_probe(struct platform_device* ofdev) 3696 { 3697 struct device *device = &ofdev->dev; 3698 struct device_node *np = ofdev->dev.of_node; 3699 struct net_device *dev = NULL; 3700 struct ucc_geth_private *ugeth = NULL; 3701 struct ucc_geth_info *ug_info; 3702 struct resource res; 3703 int err, ucc_num, max_speed = 0; 3704 const unsigned int *prop; 3705 const char *sprop; 3706 const void *mac_addr; 3707 phy_interface_t phy_interface; 3708 static const int enet_to_speed[] = { 3709 SPEED_10, SPEED_10, SPEED_10, 3710 SPEED_100, SPEED_100, SPEED_100, 3711 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3712 }; 3713 static const phy_interface_t enet_to_phy_interface[] = { 3714 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3715 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3716 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3717 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3718 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3719 PHY_INTERFACE_MODE_SGMII, 3720 }; 3721 3722 ugeth_vdbg("%s: IN", __func__); 3723 3724 prop = of_get_property(np, "cell-index", NULL); 3725 if (!prop) { 3726 prop = of_get_property(np, "device-id", NULL); 3727 if (!prop) 3728 return -ENODEV; 3729 } 3730 3731 ucc_num = *prop - 1; 3732 if ((ucc_num < 0) || (ucc_num > 7)) 3733 return -ENODEV; 3734 3735 ug_info = &ugeth_info[ucc_num]; 3736 if (ug_info == NULL) { 3737 if (netif_msg_probe(&debug)) 3738 pr_err("[%d] Missing additional data!\n", ucc_num); 3739 return -ENODEV; 3740 } 3741 3742 ug_info->uf_info.ucc_num = ucc_num; 3743 3744 sprop = of_get_property(np, "rx-clock-name", NULL); 3745 if (sprop) { 3746 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3747 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3748 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3749 pr_err("invalid rx-clock-name property\n"); 3750 return -EINVAL; 3751 } 3752 } else { 3753 prop = of_get_property(np, "rx-clock", NULL); 3754 if (!prop) { 3755 /* If both rx-clock-name and rx-clock are missing, 3756 we want to tell people to use rx-clock-name. */ 3757 pr_err("missing rx-clock-name property\n"); 3758 return -EINVAL; 3759 } 3760 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3761 pr_err("invalid rx-clock propperty\n"); 3762 return -EINVAL; 3763 } 3764 ug_info->uf_info.rx_clock = *prop; 3765 } 3766 3767 sprop = of_get_property(np, "tx-clock-name", NULL); 3768 if (sprop) { 3769 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3770 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3771 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3772 pr_err("invalid tx-clock-name property\n"); 3773 return -EINVAL; 3774 } 3775 } else { 3776 prop = of_get_property(np, "tx-clock", NULL); 3777 if (!prop) { 3778 pr_err("missing tx-clock-name property\n"); 3779 return -EINVAL; 3780 } 3781 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3782 pr_err("invalid tx-clock property\n"); 3783 return -EINVAL; 3784 } 3785 ug_info->uf_info.tx_clock = *prop; 3786 } 3787 3788 err = of_address_to_resource(np, 0, &res); 3789 if (err) 3790 return -EINVAL; 3791 3792 ug_info->uf_info.regs = res.start; 3793 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3794 3795 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3796 3797 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3798 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3799 3800 /* get the phy interface type, or default to MII */ 3801 prop = of_get_property(np, "phy-connection-type", NULL); 3802 if (!prop) { 3803 /* handle interface property present in old trees */ 3804 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3805 if (prop != NULL) { 3806 phy_interface = enet_to_phy_interface[*prop]; 3807 max_speed = enet_to_speed[*prop]; 3808 } else 3809 phy_interface = PHY_INTERFACE_MODE_MII; 3810 } else { 3811 phy_interface = to_phy_interface((const char *)prop); 3812 } 3813 3814 /* get speed, or derive from PHY interface */ 3815 if (max_speed == 0) 3816 switch (phy_interface) { 3817 case PHY_INTERFACE_MODE_GMII: 3818 case PHY_INTERFACE_MODE_RGMII: 3819 case PHY_INTERFACE_MODE_RGMII_ID: 3820 case PHY_INTERFACE_MODE_RGMII_RXID: 3821 case PHY_INTERFACE_MODE_RGMII_TXID: 3822 case PHY_INTERFACE_MODE_TBI: 3823 case PHY_INTERFACE_MODE_RTBI: 3824 case PHY_INTERFACE_MODE_SGMII: 3825 max_speed = SPEED_1000; 3826 break; 3827 default: 3828 max_speed = SPEED_100; 3829 break; 3830 } 3831 3832 if (max_speed == SPEED_1000) { 3833 unsigned int snums = qe_get_num_of_snums(); 3834 3835 /* configure muram FIFOs for gigabit operation */ 3836 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3837 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3838 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3839 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3840 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3841 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3842 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3843 3844 /* If QE's snum number is 46/76 which means we need to support 3845 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3846 * more Threads to Rx. 3847 */ 3848 if ((snums == 76) || (snums == 46)) 3849 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3850 else 3851 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3852 } 3853 3854 if (netif_msg_probe(&debug)) 3855 pr_info("UCC%1d at 0x%8x (irq = %d)\n", 3856 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs, 3857 ug_info->uf_info.irq); 3858 3859 /* Create an ethernet device instance */ 3860 dev = alloc_etherdev(sizeof(*ugeth)); 3861 3862 if (dev == NULL) 3863 return -ENOMEM; 3864 3865 ugeth = netdev_priv(dev); 3866 spin_lock_init(&ugeth->lock); 3867 3868 /* Create CQs for hash tables */ 3869 INIT_LIST_HEAD(&ugeth->group_hash_q); 3870 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3871 3872 dev_set_drvdata(device, dev); 3873 3874 /* Set the dev->base_addr to the gfar reg region */ 3875 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3876 3877 SET_NETDEV_DEV(dev, device); 3878 3879 /* Fill in the dev structure */ 3880 uec_set_ethtool_ops(dev); 3881 dev->netdev_ops = &ucc_geth_netdev_ops; 3882 dev->watchdog_timeo = TX_TIMEOUT; 3883 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3884 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3885 dev->mtu = 1500; 3886 3887 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3888 ugeth->phy_interface = phy_interface; 3889 ugeth->max_speed = max_speed; 3890 3891 err = register_netdev(dev); 3892 if (err) { 3893 if (netif_msg_probe(ugeth)) 3894 pr_err("%s: Cannot register net device, aborting\n", 3895 dev->name); 3896 free_netdev(dev); 3897 return err; 3898 } 3899 3900 mac_addr = of_get_mac_address(np); 3901 if (mac_addr) 3902 memcpy(dev->dev_addr, mac_addr, 6); 3903 3904 ugeth->ug_info = ug_info; 3905 ugeth->dev = device; 3906 ugeth->ndev = dev; 3907 ugeth->node = np; 3908 3909 return 0; 3910 } 3911 3912 static int ucc_geth_remove(struct platform_device* ofdev) 3913 { 3914 struct net_device *dev = platform_get_drvdata(ofdev); 3915 struct ucc_geth_private *ugeth = netdev_priv(dev); 3916 3917 unregister_netdev(dev); 3918 free_netdev(dev); 3919 ucc_geth_memclean(ugeth); 3920 3921 return 0; 3922 } 3923 3924 static struct of_device_id ucc_geth_match[] = { 3925 { 3926 .type = "network", 3927 .compatible = "ucc_geth", 3928 }, 3929 {}, 3930 }; 3931 3932 MODULE_DEVICE_TABLE(of, ucc_geth_match); 3933 3934 static struct platform_driver ucc_geth_driver = { 3935 .driver = { 3936 .name = DRV_NAME, 3937 .owner = THIS_MODULE, 3938 .of_match_table = ucc_geth_match, 3939 }, 3940 .probe = ucc_geth_probe, 3941 .remove = ucc_geth_remove, 3942 .suspend = ucc_geth_suspend, 3943 .resume = ucc_geth_resume, 3944 }; 3945 3946 static int __init ucc_geth_init(void) 3947 { 3948 int i, ret; 3949 3950 if (netif_msg_drv(&debug)) 3951 pr_info(DRV_DESC "\n"); 3952 for (i = 0; i < 8; i++) 3953 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 3954 sizeof(ugeth_primary_info)); 3955 3956 ret = platform_driver_register(&ucc_geth_driver); 3957 3958 return ret; 3959 } 3960 3961 static void __exit ucc_geth_exit(void) 3962 { 3963 platform_driver_unregister(&ucc_geth_driver); 3964 } 3965 3966 module_init(ucc_geth_init); 3967 module_exit(ucc_geth_exit); 3968 3969 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3970 MODULE_DESCRIPTION(DRV_DESC); 3971 MODULE_VERSION(DRV_VERSION); 3972 MODULE_LICENSE("GPL"); 3973