1 /* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/stddef.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mii.h> 32 #include <linux/phy.h> 33 #include <linux/workqueue.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_mdio.h> 37 #include <linux/of_net.h> 38 #include <linux/of_platform.h> 39 40 #include <linux/uaccess.h> 41 #include <asm/irq.h> 42 #include <asm/io.h> 43 #include <soc/fsl/qe/immap_qe.h> 44 #include <soc/fsl/qe/qe.h> 45 #include <soc/fsl/qe/ucc.h> 46 #include <soc/fsl/qe/ucc_fast.h> 47 #include <asm/machdep.h> 48 49 #include "ucc_geth.h" 50 51 #undef DEBUG 52 53 #define ugeth_printk(level, format, arg...) \ 54 printk(level format "\n", ## arg) 55 56 #define ugeth_dbg(format, arg...) \ 57 ugeth_printk(KERN_DEBUG , format , ## arg) 58 59 #ifdef UGETH_VERBOSE_DEBUG 60 #define ugeth_vdbg ugeth_dbg 61 #else 62 #define ugeth_vdbg(fmt, args...) do { } while (0) 63 #endif /* UGETH_VERBOSE_DEBUG */ 64 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 65 66 67 static DEFINE_SPINLOCK(ugeth_lock); 68 69 static struct { 70 u32 msg_enable; 71 } debug = { -1 }; 72 73 module_param_named(debug, debug.msg_enable, int, 0); 74 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 75 76 static struct ucc_geth_info ugeth_primary_info = { 77 .uf_info = { 78 .bd_mem_part = MEM_PART_SYSTEM, 79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 80 .max_rx_buf_length = 1536, 81 /* adjusted at startup if max-speed 1000 */ 82 .urfs = UCC_GETH_URFS_INIT, 83 .urfet = UCC_GETH_URFET_INIT, 84 .urfset = UCC_GETH_URFSET_INIT, 85 .utfs = UCC_GETH_UTFS_INIT, 86 .utfet = UCC_GETH_UTFET_INIT, 87 .utftt = UCC_GETH_UTFTT_INIT, 88 .ufpt = 256, 89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 91 .tenc = UCC_FAST_TX_ENCODING_NRZ, 92 .renc = UCC_FAST_RX_ENCODING_NRZ, 93 .tcrc = UCC_FAST_16_BIT_CRC, 94 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 95 }, 96 .numQueuesTx = 1, 97 .numQueuesRx = 1, 98 .extendedFilteringChainPointer = ((uint32_t) NULL), 99 .typeorlen = 3072 /*1536 */ , 100 .nonBackToBackIfgPart1 = 0x40, 101 .nonBackToBackIfgPart2 = 0x60, 102 .miminumInterFrameGapEnforcement = 0x50, 103 .backToBackInterFrameGap = 0x60, 104 .mblinterval = 128, 105 .nortsrbytetime = 5, 106 .fracsiz = 1, 107 .strictpriorityq = 0xff, 108 .altBebTruncation = 0xa, 109 .excessDefer = 1, 110 .maxRetransmission = 0xf, 111 .collisionWindow = 0x37, 112 .receiveFlowControl = 1, 113 .transmitFlowControl = 1, 114 .maxGroupAddrInHash = 4, 115 .maxIndAddrInHash = 4, 116 .prel = 7, 117 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 118 .minFrameLength = 64, 119 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 120 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 121 .vlantype = 0x8100, 122 .ecamptr = ((uint32_t) NULL), 123 .eventRegMask = UCCE_OTHER, 124 .pausePeriod = 0xf000, 125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 126 .bdRingLenTx = { 127 TX_BD_RING_LEN, 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN, 133 TX_BD_RING_LEN, 134 TX_BD_RING_LEN}, 135 136 .bdRingLenRx = { 137 RX_BD_RING_LEN, 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN, 143 RX_BD_RING_LEN, 144 RX_BD_RING_LEN}, 145 146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 147 .largestexternallookupkeysize = 148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 161 }; 162 163 static struct ucc_geth_info ugeth_info[8]; 164 165 #ifdef DEBUG 166 static void mem_disp(u8 *addr, int size) 167 { 168 u8 *i; 169 int size16Aling = (size >> 4) << 4; 170 int size4Aling = (size >> 2) << 2; 171 int notAlign = 0; 172 if (size % 16) 173 notAlign = 1; 174 175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 176 printk("0x%08x: %08x %08x %08x %08x\r\n", 177 (u32) i, 178 *((u32 *) (i)), 179 *((u32 *) (i + 4)), 180 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 181 if (notAlign == 1) 182 printk("0x%08x: ", (u32) i); 183 for (; (u32) i < (u32) addr + size4Aling; i += 4) 184 printk("%08x ", *((u32 *) (i))); 185 for (; (u32) i < (u32) addr + size; i++) 186 printk("%02x", *((i))); 187 if (notAlign == 1) 188 printk("\r\n"); 189 } 190 #endif /* DEBUG */ 191 192 static struct list_head *dequeue(struct list_head *lh) 193 { 194 unsigned long flags; 195 196 spin_lock_irqsave(&ugeth_lock, flags); 197 if (!list_empty(lh)) { 198 struct list_head *node = lh->next; 199 list_del(node); 200 spin_unlock_irqrestore(&ugeth_lock, flags); 201 return node; 202 } else { 203 spin_unlock_irqrestore(&ugeth_lock, flags); 204 return NULL; 205 } 206 } 207 208 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 209 u8 __iomem *bd) 210 { 211 struct sk_buff *skb; 212 213 skb = netdev_alloc_skb(ugeth->ndev, 214 ugeth->ug_info->uf_info.max_rx_buf_length + 215 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 216 if (!skb) 217 return NULL; 218 219 /* We need the data buffer to be aligned properly. We will reserve 220 * as many bytes as needed to align the data properly 221 */ 222 skb_reserve(skb, 223 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 225 1))); 226 227 out_be32(&((struct qe_bd __iomem *)bd)->buf, 228 dma_map_single(ugeth->dev, 229 skb->data, 230 ugeth->ug_info->uf_info.max_rx_buf_length + 231 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 232 DMA_FROM_DEVICE)); 233 234 out_be32((u32 __iomem *)bd, 235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 236 237 return skb; 238 } 239 240 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 241 { 242 u8 __iomem *bd; 243 u32 bd_status; 244 struct sk_buff *skb; 245 int i; 246 247 bd = ugeth->p_rx_bd_ring[rxQ]; 248 i = 0; 249 250 do { 251 bd_status = in_be32((u32 __iomem *)bd); 252 skb = get_new_skb(ugeth, bd); 253 254 if (!skb) /* If can not allocate data buffer, 255 abort. Cleanup will be elsewhere */ 256 return -ENOMEM; 257 258 ugeth->rx_skbuff[rxQ][i] = skb; 259 260 /* advance the BD pointer */ 261 bd += sizeof(struct qe_bd); 262 i++; 263 } while (!(bd_status & R_W)); 264 265 return 0; 266 } 267 268 static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 269 u32 *p_start, 270 u8 num_entries, 271 u32 thread_size, 272 u32 thread_alignment, 273 unsigned int risc, 274 int skip_page_for_first_entry) 275 { 276 u32 init_enet_offset; 277 u8 i; 278 int snum; 279 280 for (i = 0; i < num_entries; i++) { 281 if ((snum = qe_get_snum()) < 0) { 282 if (netif_msg_ifup(ugeth)) 283 pr_err("Can not get SNUM\n"); 284 return snum; 285 } 286 if ((i == 0) && skip_page_for_first_entry) 287 /* First entry of Rx does not have page */ 288 init_enet_offset = 0; 289 else { 290 init_enet_offset = 291 qe_muram_alloc(thread_size, thread_alignment); 292 if (IS_ERR_VALUE(init_enet_offset)) { 293 if (netif_msg_ifup(ugeth)) 294 pr_err("Can not allocate DPRAM memory\n"); 295 qe_put_snum((u8) snum); 296 return -ENOMEM; 297 } 298 } 299 *(p_start++) = 300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 301 | risc; 302 } 303 304 return 0; 305 } 306 307 static int return_init_enet_entries(struct ucc_geth_private *ugeth, 308 u32 *p_start, 309 u8 num_entries, 310 unsigned int risc, 311 int skip_page_for_first_entry) 312 { 313 u32 init_enet_offset; 314 u8 i; 315 int snum; 316 317 for (i = 0; i < num_entries; i++) { 318 u32 val = *p_start; 319 320 /* Check that this entry was actually valid -- 321 needed in case failed in allocations */ 322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 323 snum = 324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 325 ENET_INIT_PARAM_SNUM_SHIFT; 326 qe_put_snum((u8) snum); 327 if (!((i == 0) && skip_page_for_first_entry)) { 328 /* First entry of Rx does not have page */ 329 init_enet_offset = 330 (val & ENET_INIT_PARAM_PTR_MASK); 331 qe_muram_free(init_enet_offset); 332 } 333 *p_start++ = 0; 334 } 335 } 336 337 return 0; 338 } 339 340 #ifdef DEBUG 341 static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 342 u32 __iomem *p_start, 343 u8 num_entries, 344 u32 thread_size, 345 unsigned int risc, 346 int skip_page_for_first_entry) 347 { 348 u32 init_enet_offset; 349 u8 i; 350 int snum; 351 352 for (i = 0; i < num_entries; i++) { 353 u32 val = in_be32(p_start); 354 355 /* Check that this entry was actually valid -- 356 needed in case failed in allocations */ 357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 358 snum = 359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 360 ENET_INIT_PARAM_SNUM_SHIFT; 361 qe_put_snum((u8) snum); 362 if (!((i == 0) && skip_page_for_first_entry)) { 363 /* First entry of Rx does not have page */ 364 init_enet_offset = 365 (in_be32(p_start) & 366 ENET_INIT_PARAM_PTR_MASK); 367 pr_info("Init enet entry %d:\n", i); 368 pr_info("Base address: 0x%08x\n", 369 (u32)qe_muram_addr(init_enet_offset)); 370 mem_disp(qe_muram_addr(init_enet_offset), 371 thread_size); 372 } 373 p_start++; 374 } 375 } 376 377 return 0; 378 } 379 #endif 380 381 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 382 { 383 kfree(enet_addr_cont); 384 } 385 386 static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 387 { 388 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 389 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 390 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 391 } 392 393 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 394 { 395 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 396 397 if (paddr_num >= NUM_OF_PADDRS) { 398 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 399 return -EINVAL; 400 } 401 402 p_82xx_addr_filt = 403 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 404 addressfiltering; 405 406 /* Writing address ff.ff.ff.ff.ff.ff disables address 407 recognition for this register */ 408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 411 412 return 0; 413 } 414 415 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 416 u8 *p_enet_addr) 417 { 418 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 419 u32 cecr_subblock; 420 421 p_82xx_addr_filt = 422 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 423 addressfiltering; 424 425 cecr_subblock = 426 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 427 428 /* Ethernet frames are defined in Little Endian mode, 429 therefore to insert */ 430 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 431 432 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 433 434 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 435 QE_CR_PROTOCOL_ETHERNET, 0); 436 } 437 438 #ifdef DEBUG 439 static void get_statistics(struct ucc_geth_private *ugeth, 440 struct ucc_geth_tx_firmware_statistics * 441 tx_firmware_statistics, 442 struct ucc_geth_rx_firmware_statistics * 443 rx_firmware_statistics, 444 struct ucc_geth_hardware_statistics *hardware_statistics) 445 { 446 struct ucc_fast __iomem *uf_regs; 447 struct ucc_geth __iomem *ug_regs; 448 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 449 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 450 451 ug_regs = ugeth->ug_regs; 452 uf_regs = (struct ucc_fast __iomem *) ug_regs; 453 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 454 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 455 456 /* Tx firmware only if user handed pointer and driver actually 457 gathers Tx firmware statistics */ 458 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 459 tx_firmware_statistics->sicoltx = 460 in_be32(&p_tx_fw_statistics_pram->sicoltx); 461 tx_firmware_statistics->mulcoltx = 462 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 463 tx_firmware_statistics->latecoltxfr = 464 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 465 tx_firmware_statistics->frabortduecol = 466 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 467 tx_firmware_statistics->frlostinmactxer = 468 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 469 tx_firmware_statistics->carriersenseertx = 470 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 471 tx_firmware_statistics->frtxok = 472 in_be32(&p_tx_fw_statistics_pram->frtxok); 473 tx_firmware_statistics->txfrexcessivedefer = 474 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 475 tx_firmware_statistics->txpkts256 = 476 in_be32(&p_tx_fw_statistics_pram->txpkts256); 477 tx_firmware_statistics->txpkts512 = 478 in_be32(&p_tx_fw_statistics_pram->txpkts512); 479 tx_firmware_statistics->txpkts1024 = 480 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 481 tx_firmware_statistics->txpktsjumbo = 482 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 483 } 484 485 /* Rx firmware only if user handed pointer and driver actually 486 * gathers Rx firmware statistics */ 487 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 488 int i; 489 rx_firmware_statistics->frrxfcser = 490 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 491 rx_firmware_statistics->fraligner = 492 in_be32(&p_rx_fw_statistics_pram->fraligner); 493 rx_firmware_statistics->inrangelenrxer = 494 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 495 rx_firmware_statistics->outrangelenrxer = 496 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 497 rx_firmware_statistics->frtoolong = 498 in_be32(&p_rx_fw_statistics_pram->frtoolong); 499 rx_firmware_statistics->runt = 500 in_be32(&p_rx_fw_statistics_pram->runt); 501 rx_firmware_statistics->verylongevent = 502 in_be32(&p_rx_fw_statistics_pram->verylongevent); 503 rx_firmware_statistics->symbolerror = 504 in_be32(&p_rx_fw_statistics_pram->symbolerror); 505 rx_firmware_statistics->dropbsy = 506 in_be32(&p_rx_fw_statistics_pram->dropbsy); 507 for (i = 0; i < 0x8; i++) 508 rx_firmware_statistics->res0[i] = 509 p_rx_fw_statistics_pram->res0[i]; 510 rx_firmware_statistics->mismatchdrop = 511 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 512 rx_firmware_statistics->underpkts = 513 in_be32(&p_rx_fw_statistics_pram->underpkts); 514 rx_firmware_statistics->pkts256 = 515 in_be32(&p_rx_fw_statistics_pram->pkts256); 516 rx_firmware_statistics->pkts512 = 517 in_be32(&p_rx_fw_statistics_pram->pkts512); 518 rx_firmware_statistics->pkts1024 = 519 in_be32(&p_rx_fw_statistics_pram->pkts1024); 520 rx_firmware_statistics->pktsjumbo = 521 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 522 rx_firmware_statistics->frlossinmacer = 523 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 524 rx_firmware_statistics->pausefr = 525 in_be32(&p_rx_fw_statistics_pram->pausefr); 526 for (i = 0; i < 0x4; i++) 527 rx_firmware_statistics->res1[i] = 528 p_rx_fw_statistics_pram->res1[i]; 529 rx_firmware_statistics->removevlan = 530 in_be32(&p_rx_fw_statistics_pram->removevlan); 531 rx_firmware_statistics->replacevlan = 532 in_be32(&p_rx_fw_statistics_pram->replacevlan); 533 rx_firmware_statistics->insertvlan = 534 in_be32(&p_rx_fw_statistics_pram->insertvlan); 535 } 536 537 /* Hardware only if user handed pointer and driver actually 538 gathers hardware statistics */ 539 if (hardware_statistics && 540 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 541 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 542 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 543 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 544 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 545 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 546 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 547 hardware_statistics->txok = in_be32(&ug_regs->txok); 548 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 549 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 550 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 551 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 552 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 553 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 554 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 555 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 556 } 557 } 558 559 static void dump_bds(struct ucc_geth_private *ugeth) 560 { 561 int i; 562 int length; 563 564 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 565 if (ugeth->p_tx_bd_ring[i]) { 566 length = 567 (ugeth->ug_info->bdRingLenTx[i] * 568 sizeof(struct qe_bd)); 569 pr_info("TX BDs[%d]\n", i); 570 mem_disp(ugeth->p_tx_bd_ring[i], length); 571 } 572 } 573 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 574 if (ugeth->p_rx_bd_ring[i]) { 575 length = 576 (ugeth->ug_info->bdRingLenRx[i] * 577 sizeof(struct qe_bd)); 578 pr_info("RX BDs[%d]\n", i); 579 mem_disp(ugeth->p_rx_bd_ring[i], length); 580 } 581 } 582 } 583 584 static void dump_regs(struct ucc_geth_private *ugeth) 585 { 586 int i; 587 588 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 589 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 590 591 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 592 (u32)&ugeth->ug_regs->maccfg1, 593 in_be32(&ugeth->ug_regs->maccfg1)); 594 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 595 (u32)&ugeth->ug_regs->maccfg2, 596 in_be32(&ugeth->ug_regs->maccfg2)); 597 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 598 (u32)&ugeth->ug_regs->ipgifg, 599 in_be32(&ugeth->ug_regs->ipgifg)); 600 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 601 (u32)&ugeth->ug_regs->hafdup, 602 in_be32(&ugeth->ug_regs->hafdup)); 603 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 604 (u32)&ugeth->ug_regs->ifctl, 605 in_be32(&ugeth->ug_regs->ifctl)); 606 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 607 (u32)&ugeth->ug_regs->ifstat, 608 in_be32(&ugeth->ug_regs->ifstat)); 609 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 610 (u32)&ugeth->ug_regs->macstnaddr1, 611 in_be32(&ugeth->ug_regs->macstnaddr1)); 612 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 613 (u32)&ugeth->ug_regs->macstnaddr2, 614 in_be32(&ugeth->ug_regs->macstnaddr2)); 615 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 616 (u32)&ugeth->ug_regs->uempr, 617 in_be32(&ugeth->ug_regs->uempr)); 618 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 619 (u32)&ugeth->ug_regs->utbipar, 620 in_be32(&ugeth->ug_regs->utbipar)); 621 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 622 (u32)&ugeth->ug_regs->uescr, 623 in_be16(&ugeth->ug_regs->uescr)); 624 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 625 (u32)&ugeth->ug_regs->tx64, 626 in_be32(&ugeth->ug_regs->tx64)); 627 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 628 (u32)&ugeth->ug_regs->tx127, 629 in_be32(&ugeth->ug_regs->tx127)); 630 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 631 (u32)&ugeth->ug_regs->tx255, 632 in_be32(&ugeth->ug_regs->tx255)); 633 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 634 (u32)&ugeth->ug_regs->rx64, 635 in_be32(&ugeth->ug_regs->rx64)); 636 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 637 (u32)&ugeth->ug_regs->rx127, 638 in_be32(&ugeth->ug_regs->rx127)); 639 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 640 (u32)&ugeth->ug_regs->rx255, 641 in_be32(&ugeth->ug_regs->rx255)); 642 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 643 (u32)&ugeth->ug_regs->txok, 644 in_be32(&ugeth->ug_regs->txok)); 645 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 646 (u32)&ugeth->ug_regs->txcf, 647 in_be16(&ugeth->ug_regs->txcf)); 648 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 649 (u32)&ugeth->ug_regs->tmca, 650 in_be32(&ugeth->ug_regs->tmca)); 651 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 652 (u32)&ugeth->ug_regs->tbca, 653 in_be32(&ugeth->ug_regs->tbca)); 654 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 655 (u32)&ugeth->ug_regs->rxfok, 656 in_be32(&ugeth->ug_regs->rxfok)); 657 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 658 (u32)&ugeth->ug_regs->rxbok, 659 in_be32(&ugeth->ug_regs->rxbok)); 660 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 661 (u32)&ugeth->ug_regs->rbyt, 662 in_be32(&ugeth->ug_regs->rbyt)); 663 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 664 (u32)&ugeth->ug_regs->rmca, 665 in_be32(&ugeth->ug_regs->rmca)); 666 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 667 (u32)&ugeth->ug_regs->rbca, 668 in_be32(&ugeth->ug_regs->rbca)); 669 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 670 (u32)&ugeth->ug_regs->scar, 671 in_be32(&ugeth->ug_regs->scar)); 672 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 673 (u32)&ugeth->ug_regs->scam, 674 in_be32(&ugeth->ug_regs->scam)); 675 676 if (ugeth->p_thread_data_tx) { 677 int numThreadsTxNumerical; 678 switch (ugeth->ug_info->numThreadsTx) { 679 case UCC_GETH_NUM_OF_THREADS_1: 680 numThreadsTxNumerical = 1; 681 break; 682 case UCC_GETH_NUM_OF_THREADS_2: 683 numThreadsTxNumerical = 2; 684 break; 685 case UCC_GETH_NUM_OF_THREADS_4: 686 numThreadsTxNumerical = 4; 687 break; 688 case UCC_GETH_NUM_OF_THREADS_6: 689 numThreadsTxNumerical = 6; 690 break; 691 case UCC_GETH_NUM_OF_THREADS_8: 692 numThreadsTxNumerical = 8; 693 break; 694 default: 695 numThreadsTxNumerical = 0; 696 break; 697 } 698 699 pr_info("Thread data TXs:\n"); 700 pr_info("Base address: 0x%08x\n", 701 (u32)ugeth->p_thread_data_tx); 702 for (i = 0; i < numThreadsTxNumerical; i++) { 703 pr_info("Thread data TX[%d]:\n", i); 704 pr_info("Base address: 0x%08x\n", 705 (u32)&ugeth->p_thread_data_tx[i]); 706 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 707 sizeof(struct ucc_geth_thread_data_tx)); 708 } 709 } 710 if (ugeth->p_thread_data_rx) { 711 int numThreadsRxNumerical; 712 switch (ugeth->ug_info->numThreadsRx) { 713 case UCC_GETH_NUM_OF_THREADS_1: 714 numThreadsRxNumerical = 1; 715 break; 716 case UCC_GETH_NUM_OF_THREADS_2: 717 numThreadsRxNumerical = 2; 718 break; 719 case UCC_GETH_NUM_OF_THREADS_4: 720 numThreadsRxNumerical = 4; 721 break; 722 case UCC_GETH_NUM_OF_THREADS_6: 723 numThreadsRxNumerical = 6; 724 break; 725 case UCC_GETH_NUM_OF_THREADS_8: 726 numThreadsRxNumerical = 8; 727 break; 728 default: 729 numThreadsRxNumerical = 0; 730 break; 731 } 732 733 pr_info("Thread data RX:\n"); 734 pr_info("Base address: 0x%08x\n", 735 (u32)ugeth->p_thread_data_rx); 736 for (i = 0; i < numThreadsRxNumerical; i++) { 737 pr_info("Thread data RX[%d]:\n", i); 738 pr_info("Base address: 0x%08x\n", 739 (u32)&ugeth->p_thread_data_rx[i]); 740 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 741 sizeof(struct ucc_geth_thread_data_rx)); 742 } 743 } 744 if (ugeth->p_exf_glbl_param) { 745 pr_info("EXF global param:\n"); 746 pr_info("Base address: 0x%08x\n", 747 (u32)ugeth->p_exf_glbl_param); 748 mem_disp((u8 *) ugeth->p_exf_glbl_param, 749 sizeof(*ugeth->p_exf_glbl_param)); 750 } 751 if (ugeth->p_tx_glbl_pram) { 752 pr_info("TX global param:\n"); 753 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 754 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 755 (u32)&ugeth->p_tx_glbl_pram->temoder, 756 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 757 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 758 (u32)&ugeth->p_tx_glbl_pram->sqptr, 759 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 760 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 761 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 762 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 763 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 764 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 765 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 766 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 767 (u32)&ugeth->p_tx_glbl_pram->tstate, 768 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 769 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 770 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 771 ugeth->p_tx_glbl_pram->iphoffset[0]); 772 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 773 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 774 ugeth->p_tx_glbl_pram->iphoffset[1]); 775 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 776 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 777 ugeth->p_tx_glbl_pram->iphoffset[2]); 778 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 779 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 780 ugeth->p_tx_glbl_pram->iphoffset[3]); 781 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 782 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 783 ugeth->p_tx_glbl_pram->iphoffset[4]); 784 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 785 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 786 ugeth->p_tx_glbl_pram->iphoffset[5]); 787 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 788 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 789 ugeth->p_tx_glbl_pram->iphoffset[6]); 790 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 791 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 792 ugeth->p_tx_glbl_pram->iphoffset[7]); 793 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 794 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 795 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 796 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 797 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 798 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 799 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 800 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 801 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 802 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 803 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 805 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 806 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 808 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 809 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 811 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 812 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 814 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 815 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 817 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 818 (u32)&ugeth->p_tx_glbl_pram->tqptr, 819 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 820 } 821 if (ugeth->p_rx_glbl_pram) { 822 pr_info("RX global param:\n"); 823 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 824 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 825 (u32)&ugeth->p_rx_glbl_pram->remoder, 826 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 827 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 828 (u32)&ugeth->p_rx_glbl_pram->rqptr, 829 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 830 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 831 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 832 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 833 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 834 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 835 ugeth->p_rx_glbl_pram->rxgstpack); 836 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 837 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 838 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 839 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 840 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 841 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 842 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 843 (u32)&ugeth->p_rx_glbl_pram->rstate, 844 ugeth->p_rx_glbl_pram->rstate); 845 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 846 (u32)&ugeth->p_rx_glbl_pram->mrblr, 847 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 848 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 849 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 850 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 851 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 852 (u32)&ugeth->p_rx_glbl_pram->mflr, 853 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 854 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 855 (u32)&ugeth->p_rx_glbl_pram->minflr, 856 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 857 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 858 (u32)&ugeth->p_rx_glbl_pram->maxd1, 859 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 860 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 861 (u32)&ugeth->p_rx_glbl_pram->maxd2, 862 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 863 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 864 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 865 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 866 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 867 (u32)&ugeth->p_rx_glbl_pram->l2qt, 868 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 869 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 870 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 871 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 872 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 873 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 874 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 875 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 876 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 877 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 878 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 879 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 881 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 882 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 884 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 885 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 887 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 888 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 890 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 891 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 893 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 894 (u32)&ugeth->p_rx_glbl_pram->vlantype, 895 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 896 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 897 (u32)&ugeth->p_rx_glbl_pram->vlantci, 898 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 899 for (i = 0; i < 64; i++) 900 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 901 i, 902 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 903 ugeth->p_rx_glbl_pram->addressfiltering[i]); 904 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 905 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 906 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 907 } 908 if (ugeth->p_send_q_mem_reg) { 909 pr_info("Send Q memory registers:\n"); 910 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 911 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 912 pr_info("SQQD[%d]:\n", i); 913 pr_info("Base address: 0x%08x\n", 914 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 915 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 916 sizeof(struct ucc_geth_send_queue_qd)); 917 } 918 } 919 if (ugeth->p_scheduler) { 920 pr_info("Scheduler:\n"); 921 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 922 mem_disp((u8 *) ugeth->p_scheduler, 923 sizeof(*ugeth->p_scheduler)); 924 } 925 if (ugeth->p_tx_fw_statistics_pram) { 926 pr_info("TX FW statistics pram:\n"); 927 pr_info("Base address: 0x%08x\n", 928 (u32)ugeth->p_tx_fw_statistics_pram); 929 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 930 sizeof(*ugeth->p_tx_fw_statistics_pram)); 931 } 932 if (ugeth->p_rx_fw_statistics_pram) { 933 pr_info("RX FW statistics pram:\n"); 934 pr_info("Base address: 0x%08x\n", 935 (u32)ugeth->p_rx_fw_statistics_pram); 936 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 937 sizeof(*ugeth->p_rx_fw_statistics_pram)); 938 } 939 if (ugeth->p_rx_irq_coalescing_tbl) { 940 pr_info("RX IRQ coalescing tables:\n"); 941 pr_info("Base address: 0x%08x\n", 942 (u32)ugeth->p_rx_irq_coalescing_tbl); 943 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 944 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 945 pr_info("Base address: 0x%08x\n", 946 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 947 coalescingentry[i]); 948 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 949 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 950 coalescingentry[i].interruptcoalescingmaxvalue, 951 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 952 coalescingentry[i]. 953 interruptcoalescingmaxvalue)); 954 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 955 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 956 coalescingentry[i].interruptcoalescingcounter, 957 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 958 coalescingentry[i]. 959 interruptcoalescingcounter)); 960 } 961 } 962 if (ugeth->p_rx_bd_qs_tbl) { 963 pr_info("RX BD QS tables:\n"); 964 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 965 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 966 pr_info("RX BD QS table[%d]:\n", i); 967 pr_info("Base address: 0x%08x\n", 968 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 969 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 970 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 971 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 972 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 973 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 974 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 975 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 976 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 977 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 978 externalbdbaseptr)); 979 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 980 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 981 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 982 pr_info("ucode RX Prefetched BDs:\n"); 983 pr_info("Base address: 0x%08x\n", 984 (u32)qe_muram_addr(in_be32 985 (&ugeth->p_rx_bd_qs_tbl[i]. 986 bdbaseptr))); 987 mem_disp((u8 *) 988 qe_muram_addr(in_be32 989 (&ugeth->p_rx_bd_qs_tbl[i]. 990 bdbaseptr)), 991 sizeof(struct ucc_geth_rx_prefetched_bds)); 992 } 993 } 994 if (ugeth->p_init_enet_param_shadow) { 995 int size; 996 pr_info("Init enet param shadow:\n"); 997 pr_info("Base address: 0x%08x\n", 998 (u32) ugeth->p_init_enet_param_shadow); 999 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1000 sizeof(*ugeth->p_init_enet_param_shadow)); 1001 1002 size = sizeof(struct ucc_geth_thread_rx_pram); 1003 if (ugeth->ug_info->rxExtendedFiltering) { 1004 size += 1005 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1006 if (ugeth->ug_info->largestexternallookupkeysize == 1007 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1008 size += 1009 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1010 if (ugeth->ug_info->largestexternallookupkeysize == 1011 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1012 size += 1013 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1014 } 1015 1016 dump_init_enet_entries(ugeth, 1017 &(ugeth->p_init_enet_param_shadow-> 1018 txthread[0]), 1019 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1020 sizeof(struct ucc_geth_thread_tx_pram), 1021 ugeth->ug_info->riscTx, 0); 1022 dump_init_enet_entries(ugeth, 1023 &(ugeth->p_init_enet_param_shadow-> 1024 rxthread[0]), 1025 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1026 ugeth->ug_info->riscRx, 1); 1027 } 1028 } 1029 #endif /* DEBUG */ 1030 1031 static void init_default_reg_vals(u32 __iomem *upsmr_register, 1032 u32 __iomem *maccfg1_register, 1033 u32 __iomem *maccfg2_register) 1034 { 1035 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1036 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1037 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1038 } 1039 1040 static int init_half_duplex_params(int alt_beb, 1041 int back_pressure_no_backoff, 1042 int no_backoff, 1043 int excess_defer, 1044 u8 alt_beb_truncation, 1045 u8 max_retransmissions, 1046 u8 collision_window, 1047 u32 __iomem *hafdup_register) 1048 { 1049 u32 value = 0; 1050 1051 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1052 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1053 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1054 return -EINVAL; 1055 1056 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1057 1058 if (alt_beb) 1059 value |= HALFDUP_ALT_BEB; 1060 if (back_pressure_no_backoff) 1061 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1062 if (no_backoff) 1063 value |= HALFDUP_NO_BACKOFF; 1064 if (excess_defer) 1065 value |= HALFDUP_EXCESSIVE_DEFER; 1066 1067 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1068 1069 value |= collision_window; 1070 1071 out_be32(hafdup_register, value); 1072 return 0; 1073 } 1074 1075 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1076 u8 non_btb_ipg, 1077 u8 min_ifg, 1078 u8 btb_ipg, 1079 u32 __iomem *ipgifg_register) 1080 { 1081 u32 value = 0; 1082 1083 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1084 IPG part 2 */ 1085 if (non_btb_cs_ipg > non_btb_ipg) 1086 return -EINVAL; 1087 1088 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1089 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1090 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1091 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1092 return -EINVAL; 1093 1094 value |= 1095 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1096 IPGIFG_NBTB_CS_IPG_MASK); 1097 value |= 1098 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1099 IPGIFG_NBTB_IPG_MASK); 1100 value |= 1101 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1102 IPGIFG_MIN_IFG_MASK); 1103 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1104 1105 out_be32(ipgifg_register, value); 1106 return 0; 1107 } 1108 1109 int init_flow_control_params(u32 automatic_flow_control_mode, 1110 int rx_flow_control_enable, 1111 int tx_flow_control_enable, 1112 u16 pause_period, 1113 u16 extension_field, 1114 u32 __iomem *upsmr_register, 1115 u32 __iomem *uempr_register, 1116 u32 __iomem *maccfg1_register) 1117 { 1118 u32 value = 0; 1119 1120 /* Set UEMPR register */ 1121 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1122 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1123 out_be32(uempr_register, value); 1124 1125 /* Set UPSMR register */ 1126 setbits32(upsmr_register, automatic_flow_control_mode); 1127 1128 value = in_be32(maccfg1_register); 1129 if (rx_flow_control_enable) 1130 value |= MACCFG1_FLOW_RX; 1131 if (tx_flow_control_enable) 1132 value |= MACCFG1_FLOW_TX; 1133 out_be32(maccfg1_register, value); 1134 1135 return 0; 1136 } 1137 1138 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1139 int auto_zero_hardware_statistics, 1140 u32 __iomem *upsmr_register, 1141 u16 __iomem *uescr_register) 1142 { 1143 u16 uescr_value = 0; 1144 1145 /* Enable hardware statistics gathering if requested */ 1146 if (enable_hardware_statistics) 1147 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1148 1149 /* Clear hardware statistics counters */ 1150 uescr_value = in_be16(uescr_register); 1151 uescr_value |= UESCR_CLRCNT; 1152 /* Automatically zero hardware statistics counters on read, 1153 if requested */ 1154 if (auto_zero_hardware_statistics) 1155 uescr_value |= UESCR_AUTOZ; 1156 out_be16(uescr_register, uescr_value); 1157 1158 return 0; 1159 } 1160 1161 static int init_firmware_statistics_gathering_mode(int 1162 enable_tx_firmware_statistics, 1163 int enable_rx_firmware_statistics, 1164 u32 __iomem *tx_rmon_base_ptr, 1165 u32 tx_firmware_statistics_structure_address, 1166 u32 __iomem *rx_rmon_base_ptr, 1167 u32 rx_firmware_statistics_structure_address, 1168 u16 __iomem *temoder_register, 1169 u32 __iomem *remoder_register) 1170 { 1171 /* Note: this function does not check if */ 1172 /* the parameters it receives are NULL */ 1173 1174 if (enable_tx_firmware_statistics) { 1175 out_be32(tx_rmon_base_ptr, 1176 tx_firmware_statistics_structure_address); 1177 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1178 } 1179 1180 if (enable_rx_firmware_statistics) { 1181 out_be32(rx_rmon_base_ptr, 1182 rx_firmware_statistics_structure_address); 1183 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1184 } 1185 1186 return 0; 1187 } 1188 1189 static int init_mac_station_addr_regs(u8 address_byte_0, 1190 u8 address_byte_1, 1191 u8 address_byte_2, 1192 u8 address_byte_3, 1193 u8 address_byte_4, 1194 u8 address_byte_5, 1195 u32 __iomem *macstnaddr1_register, 1196 u32 __iomem *macstnaddr2_register) 1197 { 1198 u32 value = 0; 1199 1200 /* Example: for a station address of 0x12345678ABCD, */ 1201 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1202 1203 /* MACSTNADDR1 Register: */ 1204 1205 /* 0 7 8 15 */ 1206 /* station address byte 5 station address byte 4 */ 1207 /* 16 23 24 31 */ 1208 /* station address byte 3 station address byte 2 */ 1209 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1210 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1211 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1212 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1213 1214 out_be32(macstnaddr1_register, value); 1215 1216 /* MACSTNADDR2 Register: */ 1217 1218 /* 0 7 8 15 */ 1219 /* station address byte 1 station address byte 0 */ 1220 /* 16 23 24 31 */ 1221 /* reserved reserved */ 1222 value = 0; 1223 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1224 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1225 1226 out_be32(macstnaddr2_register, value); 1227 1228 return 0; 1229 } 1230 1231 static int init_check_frame_length_mode(int length_check, 1232 u32 __iomem *maccfg2_register) 1233 { 1234 u32 value = 0; 1235 1236 value = in_be32(maccfg2_register); 1237 1238 if (length_check) 1239 value |= MACCFG2_LC; 1240 else 1241 value &= ~MACCFG2_LC; 1242 1243 out_be32(maccfg2_register, value); 1244 return 0; 1245 } 1246 1247 static int init_preamble_length(u8 preamble_length, 1248 u32 __iomem *maccfg2_register) 1249 { 1250 if ((preamble_length < 3) || (preamble_length > 7)) 1251 return -EINVAL; 1252 1253 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1254 preamble_length << MACCFG2_PREL_SHIFT); 1255 1256 return 0; 1257 } 1258 1259 static int init_rx_parameters(int reject_broadcast, 1260 int receive_short_frames, 1261 int promiscuous, u32 __iomem *upsmr_register) 1262 { 1263 u32 value = 0; 1264 1265 value = in_be32(upsmr_register); 1266 1267 if (reject_broadcast) 1268 value |= UCC_GETH_UPSMR_BRO; 1269 else 1270 value &= ~UCC_GETH_UPSMR_BRO; 1271 1272 if (receive_short_frames) 1273 value |= UCC_GETH_UPSMR_RSH; 1274 else 1275 value &= ~UCC_GETH_UPSMR_RSH; 1276 1277 if (promiscuous) 1278 value |= UCC_GETH_UPSMR_PRO; 1279 else 1280 value &= ~UCC_GETH_UPSMR_PRO; 1281 1282 out_be32(upsmr_register, value); 1283 1284 return 0; 1285 } 1286 1287 static int init_max_rx_buff_len(u16 max_rx_buf_len, 1288 u16 __iomem *mrblr_register) 1289 { 1290 /* max_rx_buf_len value must be a multiple of 128 */ 1291 if ((max_rx_buf_len == 0) || 1292 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1293 return -EINVAL; 1294 1295 out_be16(mrblr_register, max_rx_buf_len); 1296 return 0; 1297 } 1298 1299 static int init_min_frame_len(u16 min_frame_length, 1300 u16 __iomem *minflr_register, 1301 u16 __iomem *mrblr_register) 1302 { 1303 u16 mrblr_value = 0; 1304 1305 mrblr_value = in_be16(mrblr_register); 1306 if (min_frame_length >= (mrblr_value - 4)) 1307 return -EINVAL; 1308 1309 out_be16(minflr_register, min_frame_length); 1310 return 0; 1311 } 1312 1313 static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1314 { 1315 struct ucc_geth_info *ug_info; 1316 struct ucc_geth __iomem *ug_regs; 1317 struct ucc_fast __iomem *uf_regs; 1318 int ret_val; 1319 u32 upsmr, maccfg2; 1320 u16 value; 1321 1322 ugeth_vdbg("%s: IN", __func__); 1323 1324 ug_info = ugeth->ug_info; 1325 ug_regs = ugeth->ug_regs; 1326 uf_regs = ugeth->uccf->uf_regs; 1327 1328 /* Set MACCFG2 */ 1329 maccfg2 = in_be32(&ug_regs->maccfg2); 1330 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1331 if ((ugeth->max_speed == SPEED_10) || 1332 (ugeth->max_speed == SPEED_100)) 1333 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1334 else if (ugeth->max_speed == SPEED_1000) 1335 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1336 maccfg2 |= ug_info->padAndCrc; 1337 out_be32(&ug_regs->maccfg2, maccfg2); 1338 1339 /* Set UPSMR */ 1340 upsmr = in_be32(&uf_regs->upsmr); 1341 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1342 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1343 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1344 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1349 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1350 upsmr |= UCC_GETH_UPSMR_RPM; 1351 switch (ugeth->max_speed) { 1352 case SPEED_10: 1353 upsmr |= UCC_GETH_UPSMR_R10M; 1354 /* FALLTHROUGH */ 1355 case SPEED_100: 1356 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1357 upsmr |= UCC_GETH_UPSMR_RMM; 1358 } 1359 } 1360 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1361 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1362 upsmr |= UCC_GETH_UPSMR_TBIM; 1363 } 1364 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1365 upsmr |= UCC_GETH_UPSMR_SGMM; 1366 1367 out_be32(&uf_regs->upsmr, upsmr); 1368 1369 /* Disable autonegotiation in tbi mode, because by default it 1370 comes up in autonegotiation mode. */ 1371 /* Note that this depends on proper setting in utbipar register. */ 1372 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1373 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1374 struct ucc_geth_info *ug_info = ugeth->ug_info; 1375 struct phy_device *tbiphy; 1376 1377 if (!ug_info->tbi_node) 1378 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1379 1380 tbiphy = of_phy_find_device(ug_info->tbi_node); 1381 if (!tbiphy) 1382 pr_warn("Could not get TBI device\n"); 1383 1384 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1385 value &= ~0x1000; /* Turn off autonegotiation */ 1386 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1387 1388 put_device(&tbiphy->mdio.dev); 1389 } 1390 1391 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1392 1393 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1394 if (ret_val != 0) { 1395 if (netif_msg_probe(ugeth)) 1396 pr_err("Preamble length must be between 3 and 7 inclusive\n"); 1397 return ret_val; 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1404 { 1405 struct ucc_fast_private *uccf; 1406 u32 cecr_subblock; 1407 u32 temp; 1408 int i = 10; 1409 1410 uccf = ugeth->uccf; 1411 1412 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1413 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1414 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1415 1416 /* Issue host command */ 1417 cecr_subblock = 1418 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1419 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1420 QE_CR_PROTOCOL_ETHERNET, 0); 1421 1422 /* Wait for command to complete */ 1423 do { 1424 msleep(10); 1425 temp = in_be32(uccf->p_ucce); 1426 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1427 1428 uccf->stopped_tx = 1; 1429 1430 return 0; 1431 } 1432 1433 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1434 { 1435 struct ucc_fast_private *uccf; 1436 u32 cecr_subblock; 1437 u8 temp; 1438 int i = 10; 1439 1440 uccf = ugeth->uccf; 1441 1442 /* Clear acknowledge bit */ 1443 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1444 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1445 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1446 1447 /* Keep issuing command and checking acknowledge bit until 1448 it is asserted, according to spec */ 1449 do { 1450 /* Issue host command */ 1451 cecr_subblock = 1452 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1453 ucc_num); 1454 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1455 QE_CR_PROTOCOL_ETHERNET, 0); 1456 msleep(10); 1457 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1458 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1459 1460 uccf->stopped_rx = 1; 1461 1462 return 0; 1463 } 1464 1465 static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1466 { 1467 struct ucc_fast_private *uccf; 1468 u32 cecr_subblock; 1469 1470 uccf = ugeth->uccf; 1471 1472 cecr_subblock = 1473 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1474 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1475 uccf->stopped_tx = 0; 1476 1477 return 0; 1478 } 1479 1480 static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1481 { 1482 struct ucc_fast_private *uccf; 1483 u32 cecr_subblock; 1484 1485 uccf = ugeth->uccf; 1486 1487 cecr_subblock = 1488 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1489 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1490 0); 1491 uccf->stopped_rx = 0; 1492 1493 return 0; 1494 } 1495 1496 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1497 { 1498 struct ucc_fast_private *uccf; 1499 int enabled_tx, enabled_rx; 1500 1501 uccf = ugeth->uccf; 1502 1503 /* check if the UCC number is in range. */ 1504 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1505 if (netif_msg_probe(ugeth)) 1506 pr_err("ucc_num out of range\n"); 1507 return -EINVAL; 1508 } 1509 1510 enabled_tx = uccf->enabled_tx; 1511 enabled_rx = uccf->enabled_rx; 1512 1513 /* Get Tx and Rx going again, in case this channel was actively 1514 disabled. */ 1515 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1516 ugeth_restart_tx(ugeth); 1517 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1518 ugeth_restart_rx(ugeth); 1519 1520 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1521 1522 return 0; 1523 1524 } 1525 1526 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1527 { 1528 struct ucc_fast_private *uccf; 1529 1530 uccf = ugeth->uccf; 1531 1532 /* check if the UCC number is in range. */ 1533 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1534 if (netif_msg_probe(ugeth)) 1535 pr_err("ucc_num out of range\n"); 1536 return -EINVAL; 1537 } 1538 1539 /* Stop any transmissions */ 1540 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1541 ugeth_graceful_stop_tx(ugeth); 1542 1543 /* Stop any receptions */ 1544 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1545 ugeth_graceful_stop_rx(ugeth); 1546 1547 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1548 1549 return 0; 1550 } 1551 1552 static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1553 { 1554 /* Prevent any further xmits, plus detach the device. */ 1555 netif_device_detach(ugeth->ndev); 1556 1557 /* Wait for any current xmits to finish. */ 1558 netif_tx_disable(ugeth->ndev); 1559 1560 /* Disable the interrupt to avoid NAPI rescheduling. */ 1561 disable_irq(ugeth->ug_info->uf_info.irq); 1562 1563 /* Stop NAPI, and possibly wait for its completion. */ 1564 napi_disable(&ugeth->napi); 1565 } 1566 1567 static void ugeth_activate(struct ucc_geth_private *ugeth) 1568 { 1569 napi_enable(&ugeth->napi); 1570 enable_irq(ugeth->ug_info->uf_info.irq); 1571 netif_device_attach(ugeth->ndev); 1572 } 1573 1574 /* Called every time the controller might need to be made 1575 * aware of new link state. The PHY code conveys this 1576 * information through variables in the ugeth structure, and this 1577 * function converts those variables into the appropriate 1578 * register values, and can bring down the device if needed. 1579 */ 1580 1581 static void adjust_link(struct net_device *dev) 1582 { 1583 struct ucc_geth_private *ugeth = netdev_priv(dev); 1584 struct ucc_geth __iomem *ug_regs; 1585 struct ucc_fast __iomem *uf_regs; 1586 struct phy_device *phydev = ugeth->phydev; 1587 int new_state = 0; 1588 1589 ug_regs = ugeth->ug_regs; 1590 uf_regs = ugeth->uccf->uf_regs; 1591 1592 if (phydev->link) { 1593 u32 tempval = in_be32(&ug_regs->maccfg2); 1594 u32 upsmr = in_be32(&uf_regs->upsmr); 1595 /* Now we make sure that we can be in full duplex mode. 1596 * If not, we operate in half-duplex mode. */ 1597 if (phydev->duplex != ugeth->oldduplex) { 1598 new_state = 1; 1599 if (!(phydev->duplex)) 1600 tempval &= ~(MACCFG2_FDX); 1601 else 1602 tempval |= MACCFG2_FDX; 1603 ugeth->oldduplex = phydev->duplex; 1604 } 1605 1606 if (phydev->speed != ugeth->oldspeed) { 1607 new_state = 1; 1608 switch (phydev->speed) { 1609 case SPEED_1000: 1610 tempval = ((tempval & 1611 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1612 MACCFG2_INTERFACE_MODE_BYTE); 1613 break; 1614 case SPEED_100: 1615 case SPEED_10: 1616 tempval = ((tempval & 1617 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1618 MACCFG2_INTERFACE_MODE_NIBBLE); 1619 /* if reduced mode, re-set UPSMR.R10M */ 1620 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1621 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1626 if (phydev->speed == SPEED_10) 1627 upsmr |= UCC_GETH_UPSMR_R10M; 1628 else 1629 upsmr &= ~UCC_GETH_UPSMR_R10M; 1630 } 1631 break; 1632 default: 1633 if (netif_msg_link(ugeth)) 1634 pr_warn( 1635 "%s: Ack! Speed (%d) is not 10/100/1000!", 1636 dev->name, phydev->speed); 1637 break; 1638 } 1639 ugeth->oldspeed = phydev->speed; 1640 } 1641 1642 if (!ugeth->oldlink) { 1643 new_state = 1; 1644 ugeth->oldlink = 1; 1645 } 1646 1647 if (new_state) { 1648 /* 1649 * To change the MAC configuration we need to disable 1650 * the controller. To do so, we have to either grab 1651 * ugeth->lock, which is a bad idea since 'graceful 1652 * stop' commands might take quite a while, or we can 1653 * quiesce driver's activity. 1654 */ 1655 ugeth_quiesce(ugeth); 1656 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1657 1658 out_be32(&ug_regs->maccfg2, tempval); 1659 out_be32(&uf_regs->upsmr, upsmr); 1660 1661 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1662 ugeth_activate(ugeth); 1663 } 1664 } else if (ugeth->oldlink) { 1665 new_state = 1; 1666 ugeth->oldlink = 0; 1667 ugeth->oldspeed = 0; 1668 ugeth->oldduplex = -1; 1669 } 1670 1671 if (new_state && netif_msg_link(ugeth)) 1672 phy_print_status(phydev); 1673 } 1674 1675 /* Initialize TBI PHY interface for communicating with the 1676 * SERDES lynx PHY on the chip. We communicate with this PHY 1677 * through the MDIO bus on each controller, treating it as a 1678 * "normal" PHY at the address found in the UTBIPA register. We assume 1679 * that the UTBIPA register is valid. Either the MDIO bus code will set 1680 * it to a value that doesn't conflict with other PHYs on the bus, or the 1681 * value doesn't matter, as there are no other PHYs on the bus. 1682 */ 1683 static void uec_configure_serdes(struct net_device *dev) 1684 { 1685 struct ucc_geth_private *ugeth = netdev_priv(dev); 1686 struct ucc_geth_info *ug_info = ugeth->ug_info; 1687 struct phy_device *tbiphy; 1688 1689 if (!ug_info->tbi_node) { 1690 dev_warn(&dev->dev, "SGMII mode requires that the device " 1691 "tree specify a tbi-handle\n"); 1692 return; 1693 } 1694 1695 tbiphy = of_phy_find_device(ug_info->tbi_node); 1696 if (!tbiphy) { 1697 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1698 return; 1699 } 1700 1701 /* 1702 * If the link is already up, we must already be ok, and don't need to 1703 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1704 * everything for us? Resetting it takes the link down and requires 1705 * several seconds for it to come back. 1706 */ 1707 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) { 1708 put_device(&tbiphy->mdio.dev); 1709 return; 1710 } 1711 1712 /* Single clk mode, mii mode off(for serdes communication) */ 1713 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1714 1715 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1716 1717 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1718 1719 put_device(&tbiphy->mdio.dev); 1720 } 1721 1722 /* Configure the PHY for dev. 1723 * returns 0 if success. -1 if failure 1724 */ 1725 static int init_phy(struct net_device *dev) 1726 { 1727 struct ucc_geth_private *priv = netdev_priv(dev); 1728 struct ucc_geth_info *ug_info = priv->ug_info; 1729 struct phy_device *phydev; 1730 1731 priv->oldlink = 0; 1732 priv->oldspeed = 0; 1733 priv->oldduplex = -1; 1734 1735 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1736 priv->phy_interface); 1737 if (!phydev) { 1738 dev_err(&dev->dev, "Could not attach to PHY\n"); 1739 return -ENODEV; 1740 } 1741 1742 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1743 uec_configure_serdes(dev); 1744 1745 phy_set_max_speed(phydev, SPEED_100); 1746 1747 if (priv->max_speed == SPEED_1000) 1748 phydev->supported |= ADVERTISED_1000baseT_Full; 1749 1750 phydev->advertising = phydev->supported; 1751 1752 priv->phydev = phydev; 1753 1754 return 0; 1755 } 1756 1757 static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1758 { 1759 #ifdef DEBUG 1760 ucc_fast_dump_regs(ugeth->uccf); 1761 dump_regs(ugeth); 1762 dump_bds(ugeth); 1763 #endif 1764 } 1765 1766 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1767 ugeth, 1768 enum enet_addr_type 1769 enet_addr_type) 1770 { 1771 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1772 struct ucc_fast_private *uccf; 1773 enum comm_dir comm_dir; 1774 struct list_head *p_lh; 1775 u16 i, num; 1776 u32 __iomem *addr_h; 1777 u32 __iomem *addr_l; 1778 u8 *p_counter; 1779 1780 uccf = ugeth->uccf; 1781 1782 p_82xx_addr_filt = 1783 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1784 ugeth->p_rx_glbl_pram->addressfiltering; 1785 1786 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1787 addr_h = &(p_82xx_addr_filt->gaddr_h); 1788 addr_l = &(p_82xx_addr_filt->gaddr_l); 1789 p_lh = &ugeth->group_hash_q; 1790 p_counter = &(ugeth->numGroupAddrInHash); 1791 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1792 addr_h = &(p_82xx_addr_filt->iaddr_h); 1793 addr_l = &(p_82xx_addr_filt->iaddr_l); 1794 p_lh = &ugeth->ind_hash_q; 1795 p_counter = &(ugeth->numIndAddrInHash); 1796 } else 1797 return -EINVAL; 1798 1799 comm_dir = 0; 1800 if (uccf->enabled_tx) 1801 comm_dir |= COMM_DIR_TX; 1802 if (uccf->enabled_rx) 1803 comm_dir |= COMM_DIR_RX; 1804 if (comm_dir) 1805 ugeth_disable(ugeth, comm_dir); 1806 1807 /* Clear the hash table. */ 1808 out_be32(addr_h, 0x00000000); 1809 out_be32(addr_l, 0x00000000); 1810 1811 if (!p_lh) 1812 return 0; 1813 1814 num = *p_counter; 1815 1816 /* Delete all remaining CQ elements */ 1817 for (i = 0; i < num; i++) 1818 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1819 1820 *p_counter = 0; 1821 1822 if (comm_dir) 1823 ugeth_enable(ugeth, comm_dir); 1824 1825 return 0; 1826 } 1827 1828 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1829 u8 paddr_num) 1830 { 1831 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1832 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1833 } 1834 1835 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1836 { 1837 struct ucc_geth_info *ug_info; 1838 struct ucc_fast_info *uf_info; 1839 u16 i, j; 1840 u8 __iomem *bd; 1841 1842 1843 ug_info = ugeth->ug_info; 1844 uf_info = &ug_info->uf_info; 1845 1846 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1847 if (ugeth->p_rx_bd_ring[i]) { 1848 /* Return existing data buffers in ring */ 1849 bd = ugeth->p_rx_bd_ring[i]; 1850 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1851 if (ugeth->rx_skbuff[i][j]) { 1852 dma_unmap_single(ugeth->dev, 1853 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1854 ugeth->ug_info-> 1855 uf_info.max_rx_buf_length + 1856 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1857 DMA_FROM_DEVICE); 1858 dev_kfree_skb_any( 1859 ugeth->rx_skbuff[i][j]); 1860 ugeth->rx_skbuff[i][j] = NULL; 1861 } 1862 bd += sizeof(struct qe_bd); 1863 } 1864 1865 kfree(ugeth->rx_skbuff[i]); 1866 1867 if (ugeth->ug_info->uf_info.bd_mem_part == 1868 MEM_PART_SYSTEM) 1869 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1870 else if (ugeth->ug_info->uf_info.bd_mem_part == 1871 MEM_PART_MURAM) 1872 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1873 ugeth->p_rx_bd_ring[i] = NULL; 1874 } 1875 } 1876 1877 } 1878 1879 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1880 { 1881 struct ucc_geth_info *ug_info; 1882 struct ucc_fast_info *uf_info; 1883 u16 i, j; 1884 u8 __iomem *bd; 1885 1886 ug_info = ugeth->ug_info; 1887 uf_info = &ug_info->uf_info; 1888 1889 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1890 bd = ugeth->p_tx_bd_ring[i]; 1891 if (!bd) 1892 continue; 1893 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1894 if (ugeth->tx_skbuff[i][j]) { 1895 dma_unmap_single(ugeth->dev, 1896 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1897 (in_be32((u32 __iomem *)bd) & 1898 BD_LENGTH_MASK), 1899 DMA_TO_DEVICE); 1900 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1901 ugeth->tx_skbuff[i][j] = NULL; 1902 } 1903 } 1904 1905 kfree(ugeth->tx_skbuff[i]); 1906 1907 if (ugeth->p_tx_bd_ring[i]) { 1908 if (ugeth->ug_info->uf_info.bd_mem_part == 1909 MEM_PART_SYSTEM) 1910 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1911 else if (ugeth->ug_info->uf_info.bd_mem_part == 1912 MEM_PART_MURAM) 1913 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1914 ugeth->p_tx_bd_ring[i] = NULL; 1915 } 1916 } 1917 1918 } 1919 1920 static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1921 { 1922 if (!ugeth) 1923 return; 1924 1925 if (ugeth->uccf) { 1926 ucc_fast_free(ugeth->uccf); 1927 ugeth->uccf = NULL; 1928 } 1929 1930 if (ugeth->p_thread_data_tx) { 1931 qe_muram_free(ugeth->thread_dat_tx_offset); 1932 ugeth->p_thread_data_tx = NULL; 1933 } 1934 if (ugeth->p_thread_data_rx) { 1935 qe_muram_free(ugeth->thread_dat_rx_offset); 1936 ugeth->p_thread_data_rx = NULL; 1937 } 1938 if (ugeth->p_exf_glbl_param) { 1939 qe_muram_free(ugeth->exf_glbl_param_offset); 1940 ugeth->p_exf_glbl_param = NULL; 1941 } 1942 if (ugeth->p_rx_glbl_pram) { 1943 qe_muram_free(ugeth->rx_glbl_pram_offset); 1944 ugeth->p_rx_glbl_pram = NULL; 1945 } 1946 if (ugeth->p_tx_glbl_pram) { 1947 qe_muram_free(ugeth->tx_glbl_pram_offset); 1948 ugeth->p_tx_glbl_pram = NULL; 1949 } 1950 if (ugeth->p_send_q_mem_reg) { 1951 qe_muram_free(ugeth->send_q_mem_reg_offset); 1952 ugeth->p_send_q_mem_reg = NULL; 1953 } 1954 if (ugeth->p_scheduler) { 1955 qe_muram_free(ugeth->scheduler_offset); 1956 ugeth->p_scheduler = NULL; 1957 } 1958 if (ugeth->p_tx_fw_statistics_pram) { 1959 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1960 ugeth->p_tx_fw_statistics_pram = NULL; 1961 } 1962 if (ugeth->p_rx_fw_statistics_pram) { 1963 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1964 ugeth->p_rx_fw_statistics_pram = NULL; 1965 } 1966 if (ugeth->p_rx_irq_coalescing_tbl) { 1967 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1968 ugeth->p_rx_irq_coalescing_tbl = NULL; 1969 } 1970 if (ugeth->p_rx_bd_qs_tbl) { 1971 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1972 ugeth->p_rx_bd_qs_tbl = NULL; 1973 } 1974 if (ugeth->p_init_enet_param_shadow) { 1975 return_init_enet_entries(ugeth, 1976 &(ugeth->p_init_enet_param_shadow-> 1977 rxthread[0]), 1978 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1979 ugeth->ug_info->riscRx, 1); 1980 return_init_enet_entries(ugeth, 1981 &(ugeth->p_init_enet_param_shadow-> 1982 txthread[0]), 1983 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1984 ugeth->ug_info->riscTx, 0); 1985 kfree(ugeth->p_init_enet_param_shadow); 1986 ugeth->p_init_enet_param_shadow = NULL; 1987 } 1988 ucc_geth_free_tx(ugeth); 1989 ucc_geth_free_rx(ugeth); 1990 while (!list_empty(&ugeth->group_hash_q)) 1991 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1992 (dequeue(&ugeth->group_hash_q))); 1993 while (!list_empty(&ugeth->ind_hash_q)) 1994 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1995 (dequeue(&ugeth->ind_hash_q))); 1996 if (ugeth->ug_regs) { 1997 iounmap(ugeth->ug_regs); 1998 ugeth->ug_regs = NULL; 1999 } 2000 } 2001 2002 static void ucc_geth_set_multi(struct net_device *dev) 2003 { 2004 struct ucc_geth_private *ugeth; 2005 struct netdev_hw_addr *ha; 2006 struct ucc_fast __iomem *uf_regs; 2007 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2008 2009 ugeth = netdev_priv(dev); 2010 2011 uf_regs = ugeth->uccf->uf_regs; 2012 2013 if (dev->flags & IFF_PROMISC) { 2014 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2015 } else { 2016 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2017 2018 p_82xx_addr_filt = 2019 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2020 p_rx_glbl_pram->addressfiltering; 2021 2022 if (dev->flags & IFF_ALLMULTI) { 2023 /* Catch all multicast addresses, so set the 2024 * filter to all 1's. 2025 */ 2026 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2027 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2028 } else { 2029 /* Clear filter and add the addresses in the list. 2030 */ 2031 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2032 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2033 2034 netdev_for_each_mc_addr(ha, dev) { 2035 /* Ask CPM to run CRC and set bit in 2036 * filter mask. 2037 */ 2038 hw_add_addr_in_hash(ugeth, ha->addr); 2039 } 2040 } 2041 } 2042 } 2043 2044 static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2045 { 2046 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2047 struct phy_device *phydev = ugeth->phydev; 2048 2049 ugeth_vdbg("%s: IN", __func__); 2050 2051 /* 2052 * Tell the kernel the link is down. 2053 * Must be done before disabling the controller 2054 * or deadlock may happen. 2055 */ 2056 phy_stop(phydev); 2057 2058 /* Disable the controller */ 2059 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2060 2061 /* Mask all interrupts */ 2062 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2063 2064 /* Clear all interrupts */ 2065 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2066 2067 /* Disable Rx and Tx */ 2068 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2069 2070 ucc_geth_memclean(ugeth); 2071 } 2072 2073 static int ucc_struct_init(struct ucc_geth_private *ugeth) 2074 { 2075 struct ucc_geth_info *ug_info; 2076 struct ucc_fast_info *uf_info; 2077 int i; 2078 2079 ug_info = ugeth->ug_info; 2080 uf_info = &ug_info->uf_info; 2081 2082 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2083 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2084 if (netif_msg_probe(ugeth)) 2085 pr_err("Bad memory partition value\n"); 2086 return -EINVAL; 2087 } 2088 2089 /* Rx BD lengths */ 2090 for (i = 0; i < ug_info->numQueuesRx; i++) { 2091 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2092 (ug_info->bdRingLenRx[i] % 2093 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2094 if (netif_msg_probe(ugeth)) 2095 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 2096 return -EINVAL; 2097 } 2098 } 2099 2100 /* Tx BD lengths */ 2101 for (i = 0; i < ug_info->numQueuesTx; i++) { 2102 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2103 if (netif_msg_probe(ugeth)) 2104 pr_err("Tx BD ring length must be no smaller than 2\n"); 2105 return -EINVAL; 2106 } 2107 } 2108 2109 /* mrblr */ 2110 if ((uf_info->max_rx_buf_length == 0) || 2111 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2112 if (netif_msg_probe(ugeth)) 2113 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 2114 return -EINVAL; 2115 } 2116 2117 /* num Tx queues */ 2118 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2119 if (netif_msg_probe(ugeth)) 2120 pr_err("number of tx queues too large\n"); 2121 return -EINVAL; 2122 } 2123 2124 /* num Rx queues */ 2125 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2126 if (netif_msg_probe(ugeth)) 2127 pr_err("number of rx queues too large\n"); 2128 return -EINVAL; 2129 } 2130 2131 /* l2qt */ 2132 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2133 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2134 if (netif_msg_probe(ugeth)) 2135 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 2136 return -EINVAL; 2137 } 2138 } 2139 2140 /* l3qt */ 2141 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2142 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2143 if (netif_msg_probe(ugeth)) 2144 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 2145 return -EINVAL; 2146 } 2147 } 2148 2149 if (ug_info->cam && !ug_info->ecamptr) { 2150 if (netif_msg_probe(ugeth)) 2151 pr_err("If cam mode is chosen, must supply cam ptr\n"); 2152 return -EINVAL; 2153 } 2154 2155 if ((ug_info->numStationAddresses != 2156 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2157 ug_info->rxExtendedFiltering) { 2158 if (netif_msg_probe(ugeth)) 2159 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2160 return -EINVAL; 2161 } 2162 2163 /* Generate uccm_mask for receive */ 2164 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2165 for (i = 0; i < ug_info->numQueuesRx; i++) 2166 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2167 2168 for (i = 0; i < ug_info->numQueuesTx; i++) 2169 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2170 /* Initialize the general fast UCC block. */ 2171 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2172 if (netif_msg_probe(ugeth)) 2173 pr_err("Failed to init uccf\n"); 2174 return -ENOMEM; 2175 } 2176 2177 /* read the number of risc engines, update the riscTx and riscRx 2178 * if there are 4 riscs in QE 2179 */ 2180 if (qe_get_num_of_risc() == 4) { 2181 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2182 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2183 } 2184 2185 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2186 if (!ugeth->ug_regs) { 2187 if (netif_msg_probe(ugeth)) 2188 pr_err("Failed to ioremap regs\n"); 2189 return -ENOMEM; 2190 } 2191 2192 return 0; 2193 } 2194 2195 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2196 { 2197 struct ucc_geth_info *ug_info; 2198 struct ucc_fast_info *uf_info; 2199 int length; 2200 u16 i, j; 2201 u8 __iomem *bd; 2202 2203 ug_info = ugeth->ug_info; 2204 uf_info = &ug_info->uf_info; 2205 2206 /* Allocate Tx bds */ 2207 for (j = 0; j < ug_info->numQueuesTx; j++) { 2208 /* Allocate in multiple of 2209 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2210 according to spec */ 2211 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2212 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2213 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2214 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2215 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2216 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2217 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2218 u32 align = 4; 2219 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2220 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2221 ugeth->tx_bd_ring_offset[j] = 2222 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2223 2224 if (ugeth->tx_bd_ring_offset[j] != 0) 2225 ugeth->p_tx_bd_ring[j] = 2226 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2227 align) & ~(align - 1)); 2228 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2229 ugeth->tx_bd_ring_offset[j] = 2230 qe_muram_alloc(length, 2231 UCC_GETH_TX_BD_RING_ALIGNMENT); 2232 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2233 ugeth->p_tx_bd_ring[j] = 2234 (u8 __iomem *) qe_muram_addr(ugeth-> 2235 tx_bd_ring_offset[j]); 2236 } 2237 if (!ugeth->p_tx_bd_ring[j]) { 2238 if (netif_msg_ifup(ugeth)) 2239 pr_err("Can not allocate memory for Tx bd rings\n"); 2240 return -ENOMEM; 2241 } 2242 /* Zero unused end of bd ring, according to spec */ 2243 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2244 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2245 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2246 } 2247 2248 /* Init Tx bds */ 2249 for (j = 0; j < ug_info->numQueuesTx; j++) { 2250 /* Setup the skbuff rings */ 2251 ugeth->tx_skbuff[j] = 2252 kmalloc_array(ugeth->ug_info->bdRingLenTx[j], 2253 sizeof(struct sk_buff *), GFP_KERNEL); 2254 2255 if (ugeth->tx_skbuff[j] == NULL) { 2256 if (netif_msg_ifup(ugeth)) 2257 pr_err("Could not allocate tx_skbuff\n"); 2258 return -ENOMEM; 2259 } 2260 2261 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2262 ugeth->tx_skbuff[j][i] = NULL; 2263 2264 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2265 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2266 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2267 /* clear bd buffer */ 2268 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2269 /* set bd status and length */ 2270 out_be32((u32 __iomem *)bd, 0); 2271 bd += sizeof(struct qe_bd); 2272 } 2273 bd -= sizeof(struct qe_bd); 2274 /* set bd status and length */ 2275 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2282 { 2283 struct ucc_geth_info *ug_info; 2284 struct ucc_fast_info *uf_info; 2285 int length; 2286 u16 i, j; 2287 u8 __iomem *bd; 2288 2289 ug_info = ugeth->ug_info; 2290 uf_info = &ug_info->uf_info; 2291 2292 /* Allocate Rx bds */ 2293 for (j = 0; j < ug_info->numQueuesRx; j++) { 2294 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2295 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2296 u32 align = 4; 2297 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2298 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2299 ugeth->rx_bd_ring_offset[j] = 2300 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2301 if (ugeth->rx_bd_ring_offset[j] != 0) 2302 ugeth->p_rx_bd_ring[j] = 2303 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2304 align) & ~(align - 1)); 2305 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2306 ugeth->rx_bd_ring_offset[j] = 2307 qe_muram_alloc(length, 2308 UCC_GETH_RX_BD_RING_ALIGNMENT); 2309 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2310 ugeth->p_rx_bd_ring[j] = 2311 (u8 __iomem *) qe_muram_addr(ugeth-> 2312 rx_bd_ring_offset[j]); 2313 } 2314 if (!ugeth->p_rx_bd_ring[j]) { 2315 if (netif_msg_ifup(ugeth)) 2316 pr_err("Can not allocate memory for Rx bd rings\n"); 2317 return -ENOMEM; 2318 } 2319 } 2320 2321 /* Init Rx bds */ 2322 for (j = 0; j < ug_info->numQueuesRx; j++) { 2323 /* Setup the skbuff rings */ 2324 ugeth->rx_skbuff[j] = 2325 kmalloc_array(ugeth->ug_info->bdRingLenRx[j], 2326 sizeof(struct sk_buff *), GFP_KERNEL); 2327 2328 if (ugeth->rx_skbuff[j] == NULL) { 2329 if (netif_msg_ifup(ugeth)) 2330 pr_err("Could not allocate rx_skbuff\n"); 2331 return -ENOMEM; 2332 } 2333 2334 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2335 ugeth->rx_skbuff[j][i] = NULL; 2336 2337 ugeth->skb_currx[j] = 0; 2338 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2339 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2340 /* set bd status and length */ 2341 out_be32((u32 __iomem *)bd, R_I); 2342 /* clear bd buffer */ 2343 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2344 bd += sizeof(struct qe_bd); 2345 } 2346 bd -= sizeof(struct qe_bd); 2347 /* set bd status and length */ 2348 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2349 } 2350 2351 return 0; 2352 } 2353 2354 static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2355 { 2356 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2357 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2358 struct ucc_fast_private *uccf; 2359 struct ucc_geth_info *ug_info; 2360 struct ucc_fast_info *uf_info; 2361 struct ucc_fast __iomem *uf_regs; 2362 struct ucc_geth __iomem *ug_regs; 2363 int ret_val = -EINVAL; 2364 u32 remoder = UCC_GETH_REMODER_INIT; 2365 u32 init_enet_pram_offset, cecr_subblock, command; 2366 u32 ifstat, i, j, size, l2qt, l3qt; 2367 u16 temoder = UCC_GETH_TEMODER_INIT; 2368 u16 test; 2369 u8 function_code = 0; 2370 u8 __iomem *endOfRing; 2371 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2372 2373 ugeth_vdbg("%s: IN", __func__); 2374 uccf = ugeth->uccf; 2375 ug_info = ugeth->ug_info; 2376 uf_info = &ug_info->uf_info; 2377 uf_regs = uccf->uf_regs; 2378 ug_regs = ugeth->ug_regs; 2379 2380 switch (ug_info->numThreadsRx) { 2381 case UCC_GETH_NUM_OF_THREADS_1: 2382 numThreadsRxNumerical = 1; 2383 break; 2384 case UCC_GETH_NUM_OF_THREADS_2: 2385 numThreadsRxNumerical = 2; 2386 break; 2387 case UCC_GETH_NUM_OF_THREADS_4: 2388 numThreadsRxNumerical = 4; 2389 break; 2390 case UCC_GETH_NUM_OF_THREADS_6: 2391 numThreadsRxNumerical = 6; 2392 break; 2393 case UCC_GETH_NUM_OF_THREADS_8: 2394 numThreadsRxNumerical = 8; 2395 break; 2396 default: 2397 if (netif_msg_ifup(ugeth)) 2398 pr_err("Bad number of Rx threads value\n"); 2399 return -EINVAL; 2400 } 2401 2402 switch (ug_info->numThreadsTx) { 2403 case UCC_GETH_NUM_OF_THREADS_1: 2404 numThreadsTxNumerical = 1; 2405 break; 2406 case UCC_GETH_NUM_OF_THREADS_2: 2407 numThreadsTxNumerical = 2; 2408 break; 2409 case UCC_GETH_NUM_OF_THREADS_4: 2410 numThreadsTxNumerical = 4; 2411 break; 2412 case UCC_GETH_NUM_OF_THREADS_6: 2413 numThreadsTxNumerical = 6; 2414 break; 2415 case UCC_GETH_NUM_OF_THREADS_8: 2416 numThreadsTxNumerical = 8; 2417 break; 2418 default: 2419 if (netif_msg_ifup(ugeth)) 2420 pr_err("Bad number of Tx threads value\n"); 2421 return -EINVAL; 2422 } 2423 2424 /* Calculate rx_extended_features */ 2425 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2426 ug_info->ipAddressAlignment || 2427 (ug_info->numStationAddresses != 2428 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2429 2430 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2431 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2432 (ug_info->vlanOperationNonTagged != 2433 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2434 2435 init_default_reg_vals(&uf_regs->upsmr, 2436 &ug_regs->maccfg1, &ug_regs->maccfg2); 2437 2438 /* Set UPSMR */ 2439 /* For more details see the hardware spec. */ 2440 init_rx_parameters(ug_info->bro, 2441 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2442 2443 /* We're going to ignore other registers for now, */ 2444 /* except as needed to get up and running */ 2445 2446 /* Set MACCFG1 */ 2447 /* For more details see the hardware spec. */ 2448 init_flow_control_params(ug_info->aufc, 2449 ug_info->receiveFlowControl, 2450 ug_info->transmitFlowControl, 2451 ug_info->pausePeriod, 2452 ug_info->extensionField, 2453 &uf_regs->upsmr, 2454 &ug_regs->uempr, &ug_regs->maccfg1); 2455 2456 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2457 2458 /* Set IPGIFG */ 2459 /* For more details see the hardware spec. */ 2460 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2461 ug_info->nonBackToBackIfgPart2, 2462 ug_info-> 2463 miminumInterFrameGapEnforcement, 2464 ug_info->backToBackInterFrameGap, 2465 &ug_regs->ipgifg); 2466 if (ret_val != 0) { 2467 if (netif_msg_ifup(ugeth)) 2468 pr_err("IPGIFG initialization parameter too large\n"); 2469 return ret_val; 2470 } 2471 2472 /* Set HAFDUP */ 2473 /* For more details see the hardware spec. */ 2474 ret_val = init_half_duplex_params(ug_info->altBeb, 2475 ug_info->backPressureNoBackoff, 2476 ug_info->noBackoff, 2477 ug_info->excessDefer, 2478 ug_info->altBebTruncation, 2479 ug_info->maxRetransmission, 2480 ug_info->collisionWindow, 2481 &ug_regs->hafdup); 2482 if (ret_val != 0) { 2483 if (netif_msg_ifup(ugeth)) 2484 pr_err("Half Duplex initialization parameter too large\n"); 2485 return ret_val; 2486 } 2487 2488 /* Set IFSTAT */ 2489 /* For more details see the hardware spec. */ 2490 /* Read only - resets upon read */ 2491 ifstat = in_be32(&ug_regs->ifstat); 2492 2493 /* Clear UEMPR */ 2494 /* For more details see the hardware spec. */ 2495 out_be32(&ug_regs->uempr, 0); 2496 2497 /* Set UESCR */ 2498 /* For more details see the hardware spec. */ 2499 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2500 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2501 0, &uf_regs->upsmr, &ug_regs->uescr); 2502 2503 ret_val = ucc_geth_alloc_tx(ugeth); 2504 if (ret_val != 0) 2505 return ret_val; 2506 2507 ret_val = ucc_geth_alloc_rx(ugeth); 2508 if (ret_val != 0) 2509 return ret_val; 2510 2511 /* 2512 * Global PRAM 2513 */ 2514 /* Tx global PRAM */ 2515 /* Allocate global tx parameter RAM page */ 2516 ugeth->tx_glbl_pram_offset = 2517 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2518 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2519 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2520 if (netif_msg_ifup(ugeth)) 2521 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2522 return -ENOMEM; 2523 } 2524 ugeth->p_tx_glbl_pram = 2525 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2526 tx_glbl_pram_offset); 2527 /* Zero out p_tx_glbl_pram */ 2528 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2529 2530 /* Fill global PRAM */ 2531 2532 /* TQPTR */ 2533 /* Size varies with number of Tx threads */ 2534 ugeth->thread_dat_tx_offset = 2535 qe_muram_alloc(numThreadsTxNumerical * 2536 sizeof(struct ucc_geth_thread_data_tx) + 2537 32 * (numThreadsTxNumerical == 1), 2538 UCC_GETH_THREAD_DATA_ALIGNMENT); 2539 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2540 if (netif_msg_ifup(ugeth)) 2541 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2542 return -ENOMEM; 2543 } 2544 2545 ugeth->p_thread_data_tx = 2546 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2547 thread_dat_tx_offset); 2548 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2549 2550 /* vtagtable */ 2551 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2552 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2553 ug_info->vtagtable[i]); 2554 2555 /* iphoffset */ 2556 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2557 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2558 ug_info->iphoffset[i]); 2559 2560 /* SQPTR */ 2561 /* Size varies with number of Tx queues */ 2562 ugeth->send_q_mem_reg_offset = 2563 qe_muram_alloc(ug_info->numQueuesTx * 2564 sizeof(struct ucc_geth_send_queue_qd), 2565 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2566 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2567 if (netif_msg_ifup(ugeth)) 2568 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2569 return -ENOMEM; 2570 } 2571 2572 ugeth->p_send_q_mem_reg = 2573 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2574 send_q_mem_reg_offset); 2575 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2576 2577 /* Setup the table */ 2578 /* Assume BD rings are already established */ 2579 for (i = 0; i < ug_info->numQueuesTx; i++) { 2580 endOfRing = 2581 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2582 1) * sizeof(struct qe_bd); 2583 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2584 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2585 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2586 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2587 last_bd_completed_address, 2588 (u32) virt_to_phys(endOfRing)); 2589 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2590 MEM_PART_MURAM) { 2591 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2592 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i])); 2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2594 last_bd_completed_address, 2595 (u32)qe_muram_dma(endOfRing)); 2596 } 2597 } 2598 2599 /* schedulerbasepointer */ 2600 2601 if (ug_info->numQueuesTx > 1) { 2602 /* scheduler exists only if more than 1 tx queue */ 2603 ugeth->scheduler_offset = 2604 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2605 UCC_GETH_SCHEDULER_ALIGNMENT); 2606 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2607 if (netif_msg_ifup(ugeth)) 2608 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2609 return -ENOMEM; 2610 } 2611 2612 ugeth->p_scheduler = 2613 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2614 scheduler_offset); 2615 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2616 ugeth->scheduler_offset); 2617 /* Zero out p_scheduler */ 2618 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2619 2620 /* Set values in scheduler */ 2621 out_be32(&ugeth->p_scheduler->mblinterval, 2622 ug_info->mblinterval); 2623 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2624 ug_info->nortsrbytetime); 2625 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2626 out_8(&ugeth->p_scheduler->strictpriorityq, 2627 ug_info->strictpriorityq); 2628 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2629 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2630 for (i = 0; i < NUM_TX_QUEUES; i++) 2631 out_8(&ugeth->p_scheduler->weightfactor[i], 2632 ug_info->weightfactor[i]); 2633 2634 /* Set pointers to cpucount registers in scheduler */ 2635 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2636 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2637 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2638 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2639 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2640 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2641 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2642 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2643 } 2644 2645 /* schedulerbasepointer */ 2646 /* TxRMON_PTR (statistics) */ 2647 if (ug_info-> 2648 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2649 ugeth->tx_fw_statistics_pram_offset = 2650 qe_muram_alloc(sizeof 2651 (struct ucc_geth_tx_firmware_statistics_pram), 2652 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2653 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2654 if (netif_msg_ifup(ugeth)) 2655 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2656 return -ENOMEM; 2657 } 2658 ugeth->p_tx_fw_statistics_pram = 2659 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2660 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2661 /* Zero out p_tx_fw_statistics_pram */ 2662 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2663 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2664 } 2665 2666 /* temoder */ 2667 /* Already has speed set */ 2668 2669 if (ug_info->numQueuesTx > 1) 2670 temoder |= TEMODER_SCHEDULER_ENABLE; 2671 if (ug_info->ipCheckSumGenerate) 2672 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2673 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2674 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2675 2676 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2677 2678 /* Function code register value to be used later */ 2679 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2680 /* Required for QE */ 2681 2682 /* function code register */ 2683 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2684 2685 /* Rx global PRAM */ 2686 /* Allocate global rx parameter RAM page */ 2687 ugeth->rx_glbl_pram_offset = 2688 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2689 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2690 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2691 if (netif_msg_ifup(ugeth)) 2692 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2693 return -ENOMEM; 2694 } 2695 ugeth->p_rx_glbl_pram = 2696 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2697 rx_glbl_pram_offset); 2698 /* Zero out p_rx_glbl_pram */ 2699 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2700 2701 /* Fill global PRAM */ 2702 2703 /* RQPTR */ 2704 /* Size varies with number of Rx threads */ 2705 ugeth->thread_dat_rx_offset = 2706 qe_muram_alloc(numThreadsRxNumerical * 2707 sizeof(struct ucc_geth_thread_data_rx), 2708 UCC_GETH_THREAD_DATA_ALIGNMENT); 2709 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2710 if (netif_msg_ifup(ugeth)) 2711 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2712 return -ENOMEM; 2713 } 2714 2715 ugeth->p_thread_data_rx = 2716 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2717 thread_dat_rx_offset); 2718 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2719 2720 /* typeorlen */ 2721 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2722 2723 /* rxrmonbaseptr (statistics) */ 2724 if (ug_info-> 2725 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2726 ugeth->rx_fw_statistics_pram_offset = 2727 qe_muram_alloc(sizeof 2728 (struct ucc_geth_rx_firmware_statistics_pram), 2729 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2730 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2731 if (netif_msg_ifup(ugeth)) 2732 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2733 return -ENOMEM; 2734 } 2735 ugeth->p_rx_fw_statistics_pram = 2736 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2737 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2738 /* Zero out p_rx_fw_statistics_pram */ 2739 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2740 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2741 } 2742 2743 /* intCoalescingPtr */ 2744 2745 /* Size varies with number of Rx queues */ 2746 ugeth->rx_irq_coalescing_tbl_offset = 2747 qe_muram_alloc(ug_info->numQueuesRx * 2748 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2749 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2750 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2751 if (netif_msg_ifup(ugeth)) 2752 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2753 return -ENOMEM; 2754 } 2755 2756 ugeth->p_rx_irq_coalescing_tbl = 2757 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2758 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2759 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2760 ugeth->rx_irq_coalescing_tbl_offset); 2761 2762 /* Fill interrupt coalescing table */ 2763 for (i = 0; i < ug_info->numQueuesRx; i++) { 2764 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2765 interruptcoalescingmaxvalue, 2766 ug_info->interruptcoalescingmaxvalue[i]); 2767 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2768 interruptcoalescingcounter, 2769 ug_info->interruptcoalescingmaxvalue[i]); 2770 } 2771 2772 /* MRBLR */ 2773 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2774 &ugeth->p_rx_glbl_pram->mrblr); 2775 /* MFLR */ 2776 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2777 /* MINFLR */ 2778 init_min_frame_len(ug_info->minFrameLength, 2779 &ugeth->p_rx_glbl_pram->minflr, 2780 &ugeth->p_rx_glbl_pram->mrblr); 2781 /* MAXD1 */ 2782 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2783 /* MAXD2 */ 2784 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2785 2786 /* l2qt */ 2787 l2qt = 0; 2788 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2789 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2790 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2791 2792 /* l3qt */ 2793 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2794 l3qt = 0; 2795 for (i = 0; i < 8; i++) 2796 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2797 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2798 } 2799 2800 /* vlantype */ 2801 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2802 2803 /* vlantci */ 2804 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2805 2806 /* ecamptr */ 2807 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2808 2809 /* RBDQPTR */ 2810 /* Size varies with number of Rx queues */ 2811 ugeth->rx_bd_qs_tbl_offset = 2812 qe_muram_alloc(ug_info->numQueuesRx * 2813 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2814 sizeof(struct ucc_geth_rx_prefetched_bds)), 2815 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2816 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2817 if (netif_msg_ifup(ugeth)) 2818 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2819 return -ENOMEM; 2820 } 2821 2822 ugeth->p_rx_bd_qs_tbl = 2823 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2824 rx_bd_qs_tbl_offset); 2825 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2826 /* Zero out p_rx_bd_qs_tbl */ 2827 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2828 0, 2829 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2830 sizeof(struct ucc_geth_rx_prefetched_bds))); 2831 2832 /* Setup the table */ 2833 /* Assume BD rings are already established */ 2834 for (i = 0; i < ug_info->numQueuesRx; i++) { 2835 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2836 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2837 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2838 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2839 MEM_PART_MURAM) { 2840 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2841 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i])); 2842 } 2843 /* rest of fields handled by QE */ 2844 } 2845 2846 /* remoder */ 2847 /* Already has speed set */ 2848 2849 if (ugeth->rx_extended_features) 2850 remoder |= REMODER_RX_EXTENDED_FEATURES; 2851 if (ug_info->rxExtendedFiltering) 2852 remoder |= REMODER_RX_EXTENDED_FILTERING; 2853 if (ug_info->dynamicMaxFrameLength) 2854 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2855 if (ug_info->dynamicMinFrameLength) 2856 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2857 remoder |= 2858 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2859 remoder |= 2860 ug_info-> 2861 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2862 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2863 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2864 if (ug_info->ipCheckSumCheck) 2865 remoder |= REMODER_IP_CHECKSUM_CHECK; 2866 if (ug_info->ipAddressAlignment) 2867 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2868 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2869 2870 /* Note that this function must be called */ 2871 /* ONLY AFTER p_tx_fw_statistics_pram */ 2872 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2873 init_firmware_statistics_gathering_mode((ug_info-> 2874 statisticsMode & 2875 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2876 (ug_info->statisticsMode & 2877 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2878 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2879 ugeth->tx_fw_statistics_pram_offset, 2880 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2881 ugeth->rx_fw_statistics_pram_offset, 2882 &ugeth->p_tx_glbl_pram->temoder, 2883 &ugeth->p_rx_glbl_pram->remoder); 2884 2885 /* function code register */ 2886 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2887 2888 /* initialize extended filtering */ 2889 if (ug_info->rxExtendedFiltering) { 2890 if (!ug_info->extendedFilteringChainPointer) { 2891 if (netif_msg_ifup(ugeth)) 2892 pr_err("Null Extended Filtering Chain Pointer\n"); 2893 return -EINVAL; 2894 } 2895 2896 /* Allocate memory for extended filtering Mode Global 2897 Parameters */ 2898 ugeth->exf_glbl_param_offset = 2899 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2900 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2901 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2902 if (netif_msg_ifup(ugeth)) 2903 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2904 return -ENOMEM; 2905 } 2906 2907 ugeth->p_exf_glbl_param = 2908 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2909 exf_glbl_param_offset); 2910 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2911 ugeth->exf_glbl_param_offset); 2912 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2913 (u32) ug_info->extendedFilteringChainPointer); 2914 2915 } else { /* initialize 82xx style address filtering */ 2916 2917 /* Init individual address recognition registers to disabled */ 2918 2919 for (j = 0; j < NUM_OF_PADDRS; j++) 2920 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2921 2922 p_82xx_addr_filt = 2923 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2924 p_rx_glbl_pram->addressfiltering; 2925 2926 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2927 ENET_ADDR_TYPE_GROUP); 2928 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2929 ENET_ADDR_TYPE_INDIVIDUAL); 2930 } 2931 2932 /* 2933 * Initialize UCC at QE level 2934 */ 2935 2936 command = QE_INIT_TX_RX; 2937 2938 /* Allocate shadow InitEnet command parameter structure. 2939 * This is needed because after the InitEnet command is executed, 2940 * the structure in DPRAM is released, because DPRAM is a premium 2941 * resource. 2942 * This shadow structure keeps a copy of what was done so that the 2943 * allocated resources can be released when the channel is freed. 2944 */ 2945 if (!(ugeth->p_init_enet_param_shadow = 2946 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2947 if (netif_msg_ifup(ugeth)) 2948 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2949 return -ENOMEM; 2950 } 2951 /* Zero out *p_init_enet_param_shadow */ 2952 memset((char *)ugeth->p_init_enet_param_shadow, 2953 0, sizeof(struct ucc_geth_init_pram)); 2954 2955 /* Fill shadow InitEnet command parameter structure */ 2956 2957 ugeth->p_init_enet_param_shadow->resinit1 = 2958 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2959 ugeth->p_init_enet_param_shadow->resinit2 = 2960 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2961 ugeth->p_init_enet_param_shadow->resinit3 = 2962 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2963 ugeth->p_init_enet_param_shadow->resinit4 = 2964 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2965 ugeth->p_init_enet_param_shadow->resinit5 = 2966 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2967 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2968 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2969 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2970 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2971 2972 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2973 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2974 if ((ug_info->largestexternallookupkeysize != 2975 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2976 (ug_info->largestexternallookupkeysize != 2977 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2978 (ug_info->largestexternallookupkeysize != 2979 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2980 if (netif_msg_ifup(ugeth)) 2981 pr_err("Invalid largest External Lookup Key Size\n"); 2982 return -EINVAL; 2983 } 2984 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2985 ug_info->largestexternallookupkeysize; 2986 size = sizeof(struct ucc_geth_thread_rx_pram); 2987 if (ug_info->rxExtendedFiltering) { 2988 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 2989 if (ug_info->largestexternallookupkeysize == 2990 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 2991 size += 2992 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 2993 if (ug_info->largestexternallookupkeysize == 2994 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 2995 size += 2996 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 2997 } 2998 2999 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 3000 p_init_enet_param_shadow->rxthread[0]), 3001 (u8) (numThreadsRxNumerical + 1) 3002 /* Rx needs one extra for terminator */ 3003 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3004 ug_info->riscRx, 1)) != 0) { 3005 if (netif_msg_ifup(ugeth)) 3006 pr_err("Can not fill p_init_enet_param_shadow\n"); 3007 return ret_val; 3008 } 3009 3010 ugeth->p_init_enet_param_shadow->txglobal = 3011 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3012 if ((ret_val = 3013 fill_init_enet_entries(ugeth, 3014 &(ugeth->p_init_enet_param_shadow-> 3015 txthread[0]), numThreadsTxNumerical, 3016 sizeof(struct ucc_geth_thread_tx_pram), 3017 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3018 ug_info->riscTx, 0)) != 0) { 3019 if (netif_msg_ifup(ugeth)) 3020 pr_err("Can not fill p_init_enet_param_shadow\n"); 3021 return ret_val; 3022 } 3023 3024 /* Load Rx bds with buffers */ 3025 for (i = 0; i < ug_info->numQueuesRx; i++) { 3026 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3027 if (netif_msg_ifup(ugeth)) 3028 pr_err("Can not fill Rx bds with buffers\n"); 3029 return ret_val; 3030 } 3031 } 3032 3033 /* Allocate InitEnet command parameter structure */ 3034 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3035 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3036 if (netif_msg_ifup(ugeth)) 3037 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 3038 return -ENOMEM; 3039 } 3040 p_init_enet_pram = 3041 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3042 3043 /* Copy shadow InitEnet command parameter structure into PRAM */ 3044 out_8(&p_init_enet_pram->resinit1, 3045 ugeth->p_init_enet_param_shadow->resinit1); 3046 out_8(&p_init_enet_pram->resinit2, 3047 ugeth->p_init_enet_param_shadow->resinit2); 3048 out_8(&p_init_enet_pram->resinit3, 3049 ugeth->p_init_enet_param_shadow->resinit3); 3050 out_8(&p_init_enet_pram->resinit4, 3051 ugeth->p_init_enet_param_shadow->resinit4); 3052 out_be16(&p_init_enet_pram->resinit5, 3053 ugeth->p_init_enet_param_shadow->resinit5); 3054 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3055 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3056 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3057 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3058 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3059 out_be32(&p_init_enet_pram->rxthread[i], 3060 ugeth->p_init_enet_param_shadow->rxthread[i]); 3061 out_be32(&p_init_enet_pram->txglobal, 3062 ugeth->p_init_enet_param_shadow->txglobal); 3063 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3064 out_be32(&p_init_enet_pram->txthread[i], 3065 ugeth->p_init_enet_param_shadow->txthread[i]); 3066 3067 /* Issue QE command */ 3068 cecr_subblock = 3069 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3070 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3071 init_enet_pram_offset); 3072 3073 /* Free InitEnet command parameter */ 3074 qe_muram_free(init_enet_pram_offset); 3075 3076 return 0; 3077 } 3078 3079 /* This is called by the kernel when a frame is ready for transmission. */ 3080 /* It is pointed to by the dev->hard_start_xmit function pointer */ 3081 static netdev_tx_t 3082 ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3083 { 3084 struct ucc_geth_private *ugeth = netdev_priv(dev); 3085 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3086 struct ucc_fast_private *uccf; 3087 #endif 3088 u8 __iomem *bd; /* BD pointer */ 3089 u32 bd_status; 3090 u8 txQ = 0; 3091 unsigned long flags; 3092 3093 ugeth_vdbg("%s: IN", __func__); 3094 3095 netdev_sent_queue(dev, skb->len); 3096 spin_lock_irqsave(&ugeth->lock, flags); 3097 3098 dev->stats.tx_bytes += skb->len; 3099 3100 /* Start from the next BD that should be filled */ 3101 bd = ugeth->txBd[txQ]; 3102 bd_status = in_be32((u32 __iomem *)bd); 3103 /* Save the skb pointer so we can free it later */ 3104 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3105 3106 /* Update the current skb pointer (wrapping if this was the last) */ 3107 ugeth->skb_curtx[txQ] = 3108 (ugeth->skb_curtx[txQ] + 3109 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3110 3111 /* set up the buffer descriptor */ 3112 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3113 dma_map_single(ugeth->dev, skb->data, 3114 skb->len, DMA_TO_DEVICE)); 3115 3116 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3117 3118 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3119 3120 /* set bd status and length */ 3121 out_be32((u32 __iomem *)bd, bd_status); 3122 3123 /* Move to next BD in the ring */ 3124 if (!(bd_status & T_W)) 3125 bd += sizeof(struct qe_bd); 3126 else 3127 bd = ugeth->p_tx_bd_ring[txQ]; 3128 3129 /* If the next BD still needs to be cleaned up, then the bds 3130 are full. We need to tell the kernel to stop sending us stuff. */ 3131 if (bd == ugeth->confBd[txQ]) { 3132 if (!netif_queue_stopped(dev)) 3133 netif_stop_queue(dev); 3134 } 3135 3136 ugeth->txBd[txQ] = bd; 3137 3138 skb_tx_timestamp(skb); 3139 3140 if (ugeth->p_scheduler) { 3141 ugeth->cpucount[txQ]++; 3142 /* Indicate to QE that there are more Tx bds ready for 3143 transmission */ 3144 /* This is done by writing a running counter of the bd 3145 count to the scheduler PRAM. */ 3146 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3147 } 3148 3149 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3150 uccf = ugeth->uccf; 3151 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3152 #endif 3153 spin_unlock_irqrestore(&ugeth->lock, flags); 3154 3155 return NETDEV_TX_OK; 3156 } 3157 3158 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3159 { 3160 struct sk_buff *skb; 3161 u8 __iomem *bd; 3162 u16 length, howmany = 0; 3163 u32 bd_status; 3164 u8 *bdBuffer; 3165 struct net_device *dev; 3166 3167 ugeth_vdbg("%s: IN", __func__); 3168 3169 dev = ugeth->ndev; 3170 3171 /* collect received buffers */ 3172 bd = ugeth->rxBd[rxQ]; 3173 3174 bd_status = in_be32((u32 __iomem *)bd); 3175 3176 /* while there are received buffers and BD is full (~R_E) */ 3177 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3178 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3179 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3180 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3181 3182 /* determine whether buffer is first, last, first and last 3183 (single buffer frame) or middle (not first and not last) */ 3184 if (!skb || 3185 (!(bd_status & (R_F | R_L))) || 3186 (bd_status & R_ERRORS_FATAL)) { 3187 if (netif_msg_rx_err(ugeth)) 3188 pr_err("%d: ERROR!!! skb - 0x%08x\n", 3189 __LINE__, (u32)skb); 3190 dev_kfree_skb(skb); 3191 3192 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3193 dev->stats.rx_dropped++; 3194 } else { 3195 dev->stats.rx_packets++; 3196 howmany++; 3197 3198 /* Prep the skb for the packet */ 3199 skb_put(skb, length); 3200 3201 /* Tell the skb what kind of packet this is */ 3202 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3203 3204 dev->stats.rx_bytes += length; 3205 /* Send the packet up the stack */ 3206 netif_receive_skb(skb); 3207 } 3208 3209 skb = get_new_skb(ugeth, bd); 3210 if (!skb) { 3211 if (netif_msg_rx_err(ugeth)) 3212 pr_warn("No Rx Data Buffer\n"); 3213 dev->stats.rx_dropped++; 3214 break; 3215 } 3216 3217 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3218 3219 /* update to point at the next skb */ 3220 ugeth->skb_currx[rxQ] = 3221 (ugeth->skb_currx[rxQ] + 3222 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3223 3224 if (bd_status & R_W) 3225 bd = ugeth->p_rx_bd_ring[rxQ]; 3226 else 3227 bd += sizeof(struct qe_bd); 3228 3229 bd_status = in_be32((u32 __iomem *)bd); 3230 } 3231 3232 ugeth->rxBd[rxQ] = bd; 3233 return howmany; 3234 } 3235 3236 static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3237 { 3238 /* Start from the next BD that should be filled */ 3239 struct ucc_geth_private *ugeth = netdev_priv(dev); 3240 unsigned int bytes_sent = 0; 3241 int howmany = 0; 3242 u8 __iomem *bd; /* BD pointer */ 3243 u32 bd_status; 3244 3245 bd = ugeth->confBd[txQ]; 3246 bd_status = in_be32((u32 __iomem *)bd); 3247 3248 /* Normal processing. */ 3249 while ((bd_status & T_R) == 0) { 3250 struct sk_buff *skb; 3251 3252 /* BD contains already transmitted buffer. */ 3253 /* Handle the transmitted buffer and release */ 3254 /* the BD to be used with the current frame */ 3255 3256 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3257 if (!skb) 3258 break; 3259 howmany++; 3260 bytes_sent += skb->len; 3261 dev->stats.tx_packets++; 3262 3263 dev_consume_skb_any(skb); 3264 3265 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3266 ugeth->skb_dirtytx[txQ] = 3267 (ugeth->skb_dirtytx[txQ] + 3268 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3269 3270 /* We freed a buffer, so now we can restart transmission */ 3271 if (netif_queue_stopped(dev)) 3272 netif_wake_queue(dev); 3273 3274 /* Advance the confirmation BD pointer */ 3275 if (!(bd_status & T_W)) 3276 bd += sizeof(struct qe_bd); 3277 else 3278 bd = ugeth->p_tx_bd_ring[txQ]; 3279 bd_status = in_be32((u32 __iomem *)bd); 3280 } 3281 ugeth->confBd[txQ] = bd; 3282 netdev_completed_queue(dev, howmany, bytes_sent); 3283 return 0; 3284 } 3285 3286 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3287 { 3288 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3289 struct ucc_geth_info *ug_info; 3290 int howmany, i; 3291 3292 ug_info = ugeth->ug_info; 3293 3294 /* Tx event processing */ 3295 spin_lock(&ugeth->lock); 3296 for (i = 0; i < ug_info->numQueuesTx; i++) 3297 ucc_geth_tx(ugeth->ndev, i); 3298 spin_unlock(&ugeth->lock); 3299 3300 howmany = 0; 3301 for (i = 0; i < ug_info->numQueuesRx; i++) 3302 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3303 3304 if (howmany < budget) { 3305 napi_complete_done(napi, howmany); 3306 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3307 } 3308 3309 return howmany; 3310 } 3311 3312 static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3313 { 3314 struct net_device *dev = info; 3315 struct ucc_geth_private *ugeth = netdev_priv(dev); 3316 struct ucc_fast_private *uccf; 3317 struct ucc_geth_info *ug_info; 3318 register u32 ucce; 3319 register u32 uccm; 3320 3321 ugeth_vdbg("%s: IN", __func__); 3322 3323 uccf = ugeth->uccf; 3324 ug_info = ugeth->ug_info; 3325 3326 /* read and clear events */ 3327 ucce = (u32) in_be32(uccf->p_ucce); 3328 uccm = (u32) in_be32(uccf->p_uccm); 3329 ucce &= uccm; 3330 out_be32(uccf->p_ucce, ucce); 3331 3332 /* check for receive events that require processing */ 3333 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3334 if (napi_schedule_prep(&ugeth->napi)) { 3335 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3336 out_be32(uccf->p_uccm, uccm); 3337 __napi_schedule(&ugeth->napi); 3338 } 3339 } 3340 3341 /* Errors and other events */ 3342 if (ucce & UCCE_OTHER) { 3343 if (ucce & UCC_GETH_UCCE_BSY) 3344 dev->stats.rx_errors++; 3345 if (ucce & UCC_GETH_UCCE_TXE) 3346 dev->stats.tx_errors++; 3347 } 3348 3349 return IRQ_HANDLED; 3350 } 3351 3352 #ifdef CONFIG_NET_POLL_CONTROLLER 3353 /* 3354 * Polling 'interrupt' - used by things like netconsole to send skbs 3355 * without having to re-enable interrupts. It's not called while 3356 * the interrupt routine is executing. 3357 */ 3358 static void ucc_netpoll(struct net_device *dev) 3359 { 3360 struct ucc_geth_private *ugeth = netdev_priv(dev); 3361 int irq = ugeth->ug_info->uf_info.irq; 3362 3363 disable_irq(irq); 3364 ucc_geth_irq_handler(irq, dev); 3365 enable_irq(irq); 3366 } 3367 #endif /* CONFIG_NET_POLL_CONTROLLER */ 3368 3369 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3370 { 3371 struct ucc_geth_private *ugeth = netdev_priv(dev); 3372 struct sockaddr *addr = p; 3373 3374 if (!is_valid_ether_addr(addr->sa_data)) 3375 return -EADDRNOTAVAIL; 3376 3377 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3378 3379 /* 3380 * If device is not running, we will set mac addr register 3381 * when opening the device. 3382 */ 3383 if (!netif_running(dev)) 3384 return 0; 3385 3386 spin_lock_irq(&ugeth->lock); 3387 init_mac_station_addr_regs(dev->dev_addr[0], 3388 dev->dev_addr[1], 3389 dev->dev_addr[2], 3390 dev->dev_addr[3], 3391 dev->dev_addr[4], 3392 dev->dev_addr[5], 3393 &ugeth->ug_regs->macstnaddr1, 3394 &ugeth->ug_regs->macstnaddr2); 3395 spin_unlock_irq(&ugeth->lock); 3396 3397 return 0; 3398 } 3399 3400 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3401 { 3402 struct net_device *dev = ugeth->ndev; 3403 int err; 3404 3405 err = ucc_struct_init(ugeth); 3406 if (err) { 3407 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3408 goto err; 3409 } 3410 3411 err = ucc_geth_startup(ugeth); 3412 if (err) { 3413 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3414 goto err; 3415 } 3416 3417 err = adjust_enet_interface(ugeth); 3418 if (err) { 3419 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3420 goto err; 3421 } 3422 3423 /* Set MACSTNADDR1, MACSTNADDR2 */ 3424 /* For more details see the hardware spec. */ 3425 init_mac_station_addr_regs(dev->dev_addr[0], 3426 dev->dev_addr[1], 3427 dev->dev_addr[2], 3428 dev->dev_addr[3], 3429 dev->dev_addr[4], 3430 dev->dev_addr[5], 3431 &ugeth->ug_regs->macstnaddr1, 3432 &ugeth->ug_regs->macstnaddr2); 3433 3434 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3435 if (err) { 3436 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n"); 3437 goto err; 3438 } 3439 3440 return 0; 3441 err: 3442 ucc_geth_stop(ugeth); 3443 return err; 3444 } 3445 3446 /* Called when something needs to use the ethernet device */ 3447 /* Returns 0 for success. */ 3448 static int ucc_geth_open(struct net_device *dev) 3449 { 3450 struct ucc_geth_private *ugeth = netdev_priv(dev); 3451 int err; 3452 3453 ugeth_vdbg("%s: IN", __func__); 3454 3455 /* Test station address */ 3456 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3457 netif_err(ugeth, ifup, dev, 3458 "Multicast address used for station address - is this what you wanted?\n"); 3459 return -EINVAL; 3460 } 3461 3462 err = init_phy(dev); 3463 if (err) { 3464 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n"); 3465 return err; 3466 } 3467 3468 err = ucc_geth_init_mac(ugeth); 3469 if (err) { 3470 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3471 goto err; 3472 } 3473 3474 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3475 0, "UCC Geth", dev); 3476 if (err) { 3477 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3478 goto err; 3479 } 3480 3481 phy_start(ugeth->phydev); 3482 napi_enable(&ugeth->napi); 3483 netdev_reset_queue(dev); 3484 netif_start_queue(dev); 3485 3486 device_set_wakeup_capable(&dev->dev, 3487 qe_alive_during_sleep() || ugeth->phydev->irq); 3488 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3489 3490 return err; 3491 3492 err: 3493 ucc_geth_stop(ugeth); 3494 return err; 3495 } 3496 3497 /* Stops the kernel queue, and halts the controller */ 3498 static int ucc_geth_close(struct net_device *dev) 3499 { 3500 struct ucc_geth_private *ugeth = netdev_priv(dev); 3501 3502 ugeth_vdbg("%s: IN", __func__); 3503 3504 napi_disable(&ugeth->napi); 3505 3506 cancel_work_sync(&ugeth->timeout_work); 3507 ucc_geth_stop(ugeth); 3508 phy_disconnect(ugeth->phydev); 3509 ugeth->phydev = NULL; 3510 3511 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3512 3513 netif_stop_queue(dev); 3514 netdev_reset_queue(dev); 3515 3516 return 0; 3517 } 3518 3519 /* Reopen device. This will reset the MAC and PHY. */ 3520 static void ucc_geth_timeout_work(struct work_struct *work) 3521 { 3522 struct ucc_geth_private *ugeth; 3523 struct net_device *dev; 3524 3525 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3526 dev = ugeth->ndev; 3527 3528 ugeth_vdbg("%s: IN", __func__); 3529 3530 dev->stats.tx_errors++; 3531 3532 ugeth_dump_regs(ugeth); 3533 3534 if (dev->flags & IFF_UP) { 3535 /* 3536 * Must reset MAC *and* PHY. This is done by reopening 3537 * the device. 3538 */ 3539 netif_tx_stop_all_queues(dev); 3540 ucc_geth_stop(ugeth); 3541 ucc_geth_init_mac(ugeth); 3542 /* Must start PHY here */ 3543 phy_start(ugeth->phydev); 3544 netif_tx_start_all_queues(dev); 3545 } 3546 3547 netif_tx_schedule_all(dev); 3548 } 3549 3550 /* 3551 * ucc_geth_timeout gets called when a packet has not been 3552 * transmitted after a set amount of time. 3553 */ 3554 static void ucc_geth_timeout(struct net_device *dev) 3555 { 3556 struct ucc_geth_private *ugeth = netdev_priv(dev); 3557 3558 schedule_work(&ugeth->timeout_work); 3559 } 3560 3561 3562 #ifdef CONFIG_PM 3563 3564 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3565 { 3566 struct net_device *ndev = platform_get_drvdata(ofdev); 3567 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3568 3569 if (!netif_running(ndev)) 3570 return 0; 3571 3572 netif_device_detach(ndev); 3573 napi_disable(&ugeth->napi); 3574 3575 /* 3576 * Disable the controller, otherwise we'll wakeup on any network 3577 * activity. 3578 */ 3579 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3580 3581 if (ugeth->wol_en & WAKE_MAGIC) { 3582 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3583 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3584 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3585 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3586 phy_stop(ugeth->phydev); 3587 } 3588 3589 return 0; 3590 } 3591 3592 static int ucc_geth_resume(struct platform_device *ofdev) 3593 { 3594 struct net_device *ndev = platform_get_drvdata(ofdev); 3595 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3596 int err; 3597 3598 if (!netif_running(ndev)) 3599 return 0; 3600 3601 if (qe_alive_during_sleep()) { 3602 if (ugeth->wol_en & WAKE_MAGIC) { 3603 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3604 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3605 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3606 } 3607 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3608 } else { 3609 /* 3610 * Full reinitialization is required if QE shuts down 3611 * during sleep. 3612 */ 3613 ucc_geth_memclean(ugeth); 3614 3615 err = ucc_geth_init_mac(ugeth); 3616 if (err) { 3617 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3618 return err; 3619 } 3620 } 3621 3622 ugeth->oldlink = 0; 3623 ugeth->oldspeed = 0; 3624 ugeth->oldduplex = -1; 3625 3626 phy_stop(ugeth->phydev); 3627 phy_start(ugeth->phydev); 3628 3629 napi_enable(&ugeth->napi); 3630 netif_device_attach(ndev); 3631 3632 return 0; 3633 } 3634 3635 #else 3636 #define ucc_geth_suspend NULL 3637 #define ucc_geth_resume NULL 3638 #endif 3639 3640 static phy_interface_t to_phy_interface(const char *phy_connection_type) 3641 { 3642 if (strcasecmp(phy_connection_type, "mii") == 0) 3643 return PHY_INTERFACE_MODE_MII; 3644 if (strcasecmp(phy_connection_type, "gmii") == 0) 3645 return PHY_INTERFACE_MODE_GMII; 3646 if (strcasecmp(phy_connection_type, "tbi") == 0) 3647 return PHY_INTERFACE_MODE_TBI; 3648 if (strcasecmp(phy_connection_type, "rmii") == 0) 3649 return PHY_INTERFACE_MODE_RMII; 3650 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3651 return PHY_INTERFACE_MODE_RGMII; 3652 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3653 return PHY_INTERFACE_MODE_RGMII_ID; 3654 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3655 return PHY_INTERFACE_MODE_RGMII_TXID; 3656 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3657 return PHY_INTERFACE_MODE_RGMII_RXID; 3658 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3659 return PHY_INTERFACE_MODE_RTBI; 3660 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3661 return PHY_INTERFACE_MODE_SGMII; 3662 3663 return PHY_INTERFACE_MODE_MII; 3664 } 3665 3666 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3667 { 3668 struct ucc_geth_private *ugeth = netdev_priv(dev); 3669 3670 if (!netif_running(dev)) 3671 return -EINVAL; 3672 3673 if (!ugeth->phydev) 3674 return -ENODEV; 3675 3676 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3677 } 3678 3679 static const struct net_device_ops ucc_geth_netdev_ops = { 3680 .ndo_open = ucc_geth_open, 3681 .ndo_stop = ucc_geth_close, 3682 .ndo_start_xmit = ucc_geth_start_xmit, 3683 .ndo_validate_addr = eth_validate_addr, 3684 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3685 .ndo_set_rx_mode = ucc_geth_set_multi, 3686 .ndo_tx_timeout = ucc_geth_timeout, 3687 .ndo_do_ioctl = ucc_geth_ioctl, 3688 #ifdef CONFIG_NET_POLL_CONTROLLER 3689 .ndo_poll_controller = ucc_netpoll, 3690 #endif 3691 }; 3692 3693 static int ucc_geth_probe(struct platform_device* ofdev) 3694 { 3695 struct device *device = &ofdev->dev; 3696 struct device_node *np = ofdev->dev.of_node; 3697 struct net_device *dev = NULL; 3698 struct ucc_geth_private *ugeth = NULL; 3699 struct ucc_geth_info *ug_info; 3700 struct resource res; 3701 int err, ucc_num, max_speed = 0; 3702 const unsigned int *prop; 3703 const char *sprop; 3704 const void *mac_addr; 3705 phy_interface_t phy_interface; 3706 static const int enet_to_speed[] = { 3707 SPEED_10, SPEED_10, SPEED_10, 3708 SPEED_100, SPEED_100, SPEED_100, 3709 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3710 }; 3711 static const phy_interface_t enet_to_phy_interface[] = { 3712 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3713 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3714 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3715 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3716 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3717 PHY_INTERFACE_MODE_SGMII, 3718 }; 3719 3720 ugeth_vdbg("%s: IN", __func__); 3721 3722 prop = of_get_property(np, "cell-index", NULL); 3723 if (!prop) { 3724 prop = of_get_property(np, "device-id", NULL); 3725 if (!prop) 3726 return -ENODEV; 3727 } 3728 3729 ucc_num = *prop - 1; 3730 if ((ucc_num < 0) || (ucc_num > 7)) 3731 return -ENODEV; 3732 3733 ug_info = &ugeth_info[ucc_num]; 3734 if (ug_info == NULL) { 3735 if (netif_msg_probe(&debug)) 3736 pr_err("[%d] Missing additional data!\n", ucc_num); 3737 return -ENODEV; 3738 } 3739 3740 ug_info->uf_info.ucc_num = ucc_num; 3741 3742 sprop = of_get_property(np, "rx-clock-name", NULL); 3743 if (sprop) { 3744 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3745 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3746 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3747 pr_err("invalid rx-clock-name property\n"); 3748 return -EINVAL; 3749 } 3750 } else { 3751 prop = of_get_property(np, "rx-clock", NULL); 3752 if (!prop) { 3753 /* If both rx-clock-name and rx-clock are missing, 3754 we want to tell people to use rx-clock-name. */ 3755 pr_err("missing rx-clock-name property\n"); 3756 return -EINVAL; 3757 } 3758 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3759 pr_err("invalid rx-clock property\n"); 3760 return -EINVAL; 3761 } 3762 ug_info->uf_info.rx_clock = *prop; 3763 } 3764 3765 sprop = of_get_property(np, "tx-clock-name", NULL); 3766 if (sprop) { 3767 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3768 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3769 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3770 pr_err("invalid tx-clock-name property\n"); 3771 return -EINVAL; 3772 } 3773 } else { 3774 prop = of_get_property(np, "tx-clock", NULL); 3775 if (!prop) { 3776 pr_err("missing tx-clock-name property\n"); 3777 return -EINVAL; 3778 } 3779 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3780 pr_err("invalid tx-clock property\n"); 3781 return -EINVAL; 3782 } 3783 ug_info->uf_info.tx_clock = *prop; 3784 } 3785 3786 err = of_address_to_resource(np, 0, &res); 3787 if (err) 3788 return -EINVAL; 3789 3790 ug_info->uf_info.regs = res.start; 3791 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3792 3793 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3794 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) { 3795 /* 3796 * In the case of a fixed PHY, the DT node associated 3797 * to the PHY is the Ethernet MAC DT node. 3798 */ 3799 err = of_phy_register_fixed_link(np); 3800 if (err) 3801 return err; 3802 ug_info->phy_node = of_node_get(np); 3803 } 3804 3805 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3806 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3807 3808 /* get the phy interface type, or default to MII */ 3809 prop = of_get_property(np, "phy-connection-type", NULL); 3810 if (!prop) { 3811 /* handle interface property present in old trees */ 3812 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3813 if (prop != NULL) { 3814 phy_interface = enet_to_phy_interface[*prop]; 3815 max_speed = enet_to_speed[*prop]; 3816 } else 3817 phy_interface = PHY_INTERFACE_MODE_MII; 3818 } else { 3819 phy_interface = to_phy_interface((const char *)prop); 3820 } 3821 3822 /* get speed, or derive from PHY interface */ 3823 if (max_speed == 0) 3824 switch (phy_interface) { 3825 case PHY_INTERFACE_MODE_GMII: 3826 case PHY_INTERFACE_MODE_RGMII: 3827 case PHY_INTERFACE_MODE_RGMII_ID: 3828 case PHY_INTERFACE_MODE_RGMII_RXID: 3829 case PHY_INTERFACE_MODE_RGMII_TXID: 3830 case PHY_INTERFACE_MODE_TBI: 3831 case PHY_INTERFACE_MODE_RTBI: 3832 case PHY_INTERFACE_MODE_SGMII: 3833 max_speed = SPEED_1000; 3834 break; 3835 default: 3836 max_speed = SPEED_100; 3837 break; 3838 } 3839 3840 if (max_speed == SPEED_1000) { 3841 unsigned int snums = qe_get_num_of_snums(); 3842 3843 /* configure muram FIFOs for gigabit operation */ 3844 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3845 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3846 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3847 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3848 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3849 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3850 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3851 3852 /* If QE's snum number is 46/76 which means we need to support 3853 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3854 * more Threads to Rx. 3855 */ 3856 if ((snums == 76) || (snums == 46)) 3857 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3858 else 3859 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3860 } 3861 3862 if (netif_msg_probe(&debug)) 3863 pr_info("UCC%1d at 0x%8llx (irq = %d)\n", 3864 ug_info->uf_info.ucc_num + 1, 3865 (u64)ug_info->uf_info.regs, 3866 ug_info->uf_info.irq); 3867 3868 /* Create an ethernet device instance */ 3869 dev = alloc_etherdev(sizeof(*ugeth)); 3870 3871 if (dev == NULL) { 3872 err = -ENOMEM; 3873 goto err_deregister_fixed_link; 3874 } 3875 3876 ugeth = netdev_priv(dev); 3877 spin_lock_init(&ugeth->lock); 3878 3879 /* Create CQs for hash tables */ 3880 INIT_LIST_HEAD(&ugeth->group_hash_q); 3881 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3882 3883 dev_set_drvdata(device, dev); 3884 3885 /* Set the dev->base_addr to the gfar reg region */ 3886 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3887 3888 SET_NETDEV_DEV(dev, device); 3889 3890 /* Fill in the dev structure */ 3891 uec_set_ethtool_ops(dev); 3892 dev->netdev_ops = &ucc_geth_netdev_ops; 3893 dev->watchdog_timeo = TX_TIMEOUT; 3894 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3895 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3896 dev->mtu = 1500; 3897 3898 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3899 ugeth->phy_interface = phy_interface; 3900 ugeth->max_speed = max_speed; 3901 3902 /* Carrier starts down, phylib will bring it up */ 3903 netif_carrier_off(dev); 3904 3905 err = register_netdev(dev); 3906 if (err) { 3907 if (netif_msg_probe(ugeth)) 3908 pr_err("%s: Cannot register net device, aborting\n", 3909 dev->name); 3910 goto err_free_netdev; 3911 } 3912 3913 mac_addr = of_get_mac_address(np); 3914 if (mac_addr) 3915 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 3916 3917 ugeth->ug_info = ug_info; 3918 ugeth->dev = device; 3919 ugeth->ndev = dev; 3920 ugeth->node = np; 3921 3922 return 0; 3923 3924 err_free_netdev: 3925 free_netdev(dev); 3926 err_deregister_fixed_link: 3927 if (of_phy_is_fixed_link(np)) 3928 of_phy_deregister_fixed_link(np); 3929 of_node_put(ug_info->tbi_node); 3930 of_node_put(ug_info->phy_node); 3931 3932 return err; 3933 } 3934 3935 static int ucc_geth_remove(struct platform_device* ofdev) 3936 { 3937 struct net_device *dev = platform_get_drvdata(ofdev); 3938 struct ucc_geth_private *ugeth = netdev_priv(dev); 3939 struct device_node *np = ofdev->dev.of_node; 3940 3941 unregister_netdev(dev); 3942 free_netdev(dev); 3943 ucc_geth_memclean(ugeth); 3944 if (of_phy_is_fixed_link(np)) 3945 of_phy_deregister_fixed_link(np); 3946 of_node_put(ugeth->ug_info->tbi_node); 3947 of_node_put(ugeth->ug_info->phy_node); 3948 3949 return 0; 3950 } 3951 3952 static const struct of_device_id ucc_geth_match[] = { 3953 { 3954 .type = "network", 3955 .compatible = "ucc_geth", 3956 }, 3957 {}, 3958 }; 3959 3960 MODULE_DEVICE_TABLE(of, ucc_geth_match); 3961 3962 static struct platform_driver ucc_geth_driver = { 3963 .driver = { 3964 .name = DRV_NAME, 3965 .of_match_table = ucc_geth_match, 3966 }, 3967 .probe = ucc_geth_probe, 3968 .remove = ucc_geth_remove, 3969 .suspend = ucc_geth_suspend, 3970 .resume = ucc_geth_resume, 3971 }; 3972 3973 static int __init ucc_geth_init(void) 3974 { 3975 int i, ret; 3976 3977 if (netif_msg_drv(&debug)) 3978 pr_info(DRV_DESC "\n"); 3979 for (i = 0; i < 8; i++) 3980 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 3981 sizeof(ugeth_primary_info)); 3982 3983 ret = platform_driver_register(&ucc_geth_driver); 3984 3985 return ret; 3986 } 3987 3988 static void __exit ucc_geth_exit(void) 3989 { 3990 platform_driver_unregister(&ucc_geth_driver); 3991 } 3992 3993 module_init(ucc_geth_init); 3994 module_exit(ucc_geth_exit); 3995 3996 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3997 MODULE_DESCRIPTION(DRV_DESC); 3998 MODULE_VERSION(DRV_VERSION); 3999 MODULE_LICENSE("GPL"); 4000