1 /* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/stddef.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mii.h> 32 #include <linux/phy.h> 33 #include <linux/phy_fixed.h> 34 #include <linux/workqueue.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 41 #include <linux/uaccess.h> 42 #include <asm/irq.h> 43 #include <asm/io.h> 44 #include <soc/fsl/qe/immap_qe.h> 45 #include <soc/fsl/qe/qe.h> 46 #include <soc/fsl/qe/ucc.h> 47 #include <soc/fsl/qe/ucc_fast.h> 48 #include <asm/machdep.h> 49 50 #include "ucc_geth.h" 51 52 #undef DEBUG 53 54 #define ugeth_printk(level, format, arg...) \ 55 printk(level format "\n", ## arg) 56 57 #define ugeth_dbg(format, arg...) \ 58 ugeth_printk(KERN_DEBUG , format , ## arg) 59 60 #ifdef UGETH_VERBOSE_DEBUG 61 #define ugeth_vdbg ugeth_dbg 62 #else 63 #define ugeth_vdbg(fmt, args...) do { } while (0) 64 #endif /* UGETH_VERBOSE_DEBUG */ 65 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 66 67 68 static DEFINE_SPINLOCK(ugeth_lock); 69 70 static struct { 71 u32 msg_enable; 72 } debug = { -1 }; 73 74 module_param_named(debug, debug.msg_enable, int, 0); 75 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 76 77 static struct ucc_geth_info ugeth_primary_info = { 78 .uf_info = { 79 .bd_mem_part = MEM_PART_SYSTEM, 80 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 81 .max_rx_buf_length = 1536, 82 /* adjusted at startup if max-speed 1000 */ 83 .urfs = UCC_GETH_URFS_INIT, 84 .urfet = UCC_GETH_URFET_INIT, 85 .urfset = UCC_GETH_URFSET_INIT, 86 .utfs = UCC_GETH_UTFS_INIT, 87 .utfet = UCC_GETH_UTFET_INIT, 88 .utftt = UCC_GETH_UTFTT_INIT, 89 .ufpt = 256, 90 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 91 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 92 .tenc = UCC_FAST_TX_ENCODING_NRZ, 93 .renc = UCC_FAST_RX_ENCODING_NRZ, 94 .tcrc = UCC_FAST_16_BIT_CRC, 95 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 96 }, 97 .numQueuesTx = 1, 98 .numQueuesRx = 1, 99 .extendedFilteringChainPointer = ((uint32_t) NULL), 100 .typeorlen = 3072 /*1536 */ , 101 .nonBackToBackIfgPart1 = 0x40, 102 .nonBackToBackIfgPart2 = 0x60, 103 .miminumInterFrameGapEnforcement = 0x50, 104 .backToBackInterFrameGap = 0x60, 105 .mblinterval = 128, 106 .nortsrbytetime = 5, 107 .fracsiz = 1, 108 .strictpriorityq = 0xff, 109 .altBebTruncation = 0xa, 110 .excessDefer = 1, 111 .maxRetransmission = 0xf, 112 .collisionWindow = 0x37, 113 .receiveFlowControl = 1, 114 .transmitFlowControl = 1, 115 .maxGroupAddrInHash = 4, 116 .maxIndAddrInHash = 4, 117 .prel = 7, 118 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 119 .minFrameLength = 64, 120 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 121 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 122 .vlantype = 0x8100, 123 .ecamptr = ((uint32_t) NULL), 124 .eventRegMask = UCCE_OTHER, 125 .pausePeriod = 0xf000, 126 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 127 .bdRingLenTx = { 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN, 133 TX_BD_RING_LEN, 134 TX_BD_RING_LEN, 135 TX_BD_RING_LEN}, 136 137 .bdRingLenRx = { 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN, 143 RX_BD_RING_LEN, 144 RX_BD_RING_LEN, 145 RX_BD_RING_LEN}, 146 147 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 148 .largestexternallookupkeysize = 149 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 150 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 152 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 153 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 154 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 155 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 156 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 157 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 158 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 159 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 160 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 161 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 162 }; 163 164 static struct ucc_geth_info ugeth_info[8]; 165 166 #ifdef DEBUG 167 static void mem_disp(u8 *addr, int size) 168 { 169 u8 *i; 170 int size16Aling = (size >> 4) << 4; 171 int size4Aling = (size >> 2) << 2; 172 int notAlign = 0; 173 if (size % 16) 174 notAlign = 1; 175 176 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 177 printk("0x%08x: %08x %08x %08x %08x\r\n", 178 (u32) i, 179 *((u32 *) (i)), 180 *((u32 *) (i + 4)), 181 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 182 if (notAlign == 1) 183 printk("0x%08x: ", (u32) i); 184 for (; (u32) i < (u32) addr + size4Aling; i += 4) 185 printk("%08x ", *((u32 *) (i))); 186 for (; (u32) i < (u32) addr + size; i++) 187 printk("%02x", *((i))); 188 if (notAlign == 1) 189 printk("\r\n"); 190 } 191 #endif /* DEBUG */ 192 193 static struct list_head *dequeue(struct list_head *lh) 194 { 195 unsigned long flags; 196 197 spin_lock_irqsave(&ugeth_lock, flags); 198 if (!list_empty(lh)) { 199 struct list_head *node = lh->next; 200 list_del(node); 201 spin_unlock_irqrestore(&ugeth_lock, flags); 202 return node; 203 } else { 204 spin_unlock_irqrestore(&ugeth_lock, flags); 205 return NULL; 206 } 207 } 208 209 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 210 u8 __iomem *bd) 211 { 212 struct sk_buff *skb; 213 214 skb = netdev_alloc_skb(ugeth->ndev, 215 ugeth->ug_info->uf_info.max_rx_buf_length + 216 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 217 if (!skb) 218 return NULL; 219 220 /* We need the data buffer to be aligned properly. We will reserve 221 * as many bytes as needed to align the data properly 222 */ 223 skb_reserve(skb, 224 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 225 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 226 1))); 227 228 out_be32(&((struct qe_bd __iomem *)bd)->buf, 229 dma_map_single(ugeth->dev, 230 skb->data, 231 ugeth->ug_info->uf_info.max_rx_buf_length + 232 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 233 DMA_FROM_DEVICE)); 234 235 out_be32((u32 __iomem *)bd, 236 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 237 238 return skb; 239 } 240 241 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 242 { 243 u8 __iomem *bd; 244 u32 bd_status; 245 struct sk_buff *skb; 246 int i; 247 248 bd = ugeth->p_rx_bd_ring[rxQ]; 249 i = 0; 250 251 do { 252 bd_status = in_be32((u32 __iomem *)bd); 253 skb = get_new_skb(ugeth, bd); 254 255 if (!skb) /* If can not allocate data buffer, 256 abort. Cleanup will be elsewhere */ 257 return -ENOMEM; 258 259 ugeth->rx_skbuff[rxQ][i] = skb; 260 261 /* advance the BD pointer */ 262 bd += sizeof(struct qe_bd); 263 i++; 264 } while (!(bd_status & R_W)); 265 266 return 0; 267 } 268 269 static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 270 u32 *p_start, 271 u8 num_entries, 272 u32 thread_size, 273 u32 thread_alignment, 274 unsigned int risc, 275 int skip_page_for_first_entry) 276 { 277 u32 init_enet_offset; 278 u8 i; 279 int snum; 280 281 for (i = 0; i < num_entries; i++) { 282 if ((snum = qe_get_snum()) < 0) { 283 if (netif_msg_ifup(ugeth)) 284 pr_err("Can not get SNUM\n"); 285 return snum; 286 } 287 if ((i == 0) && skip_page_for_first_entry) 288 /* First entry of Rx does not have page */ 289 init_enet_offset = 0; 290 else { 291 init_enet_offset = 292 qe_muram_alloc(thread_size, thread_alignment); 293 if (IS_ERR_VALUE(init_enet_offset)) { 294 if (netif_msg_ifup(ugeth)) 295 pr_err("Can not allocate DPRAM memory\n"); 296 qe_put_snum((u8) snum); 297 return -ENOMEM; 298 } 299 } 300 *(p_start++) = 301 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 302 | risc; 303 } 304 305 return 0; 306 } 307 308 static int return_init_enet_entries(struct ucc_geth_private *ugeth, 309 u32 *p_start, 310 u8 num_entries, 311 unsigned int risc, 312 int skip_page_for_first_entry) 313 { 314 u32 init_enet_offset; 315 u8 i; 316 int snum; 317 318 for (i = 0; i < num_entries; i++) { 319 u32 val = *p_start; 320 321 /* Check that this entry was actually valid -- 322 needed in case failed in allocations */ 323 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 324 snum = 325 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 326 ENET_INIT_PARAM_SNUM_SHIFT; 327 qe_put_snum((u8) snum); 328 if (!((i == 0) && skip_page_for_first_entry)) { 329 /* First entry of Rx does not have page */ 330 init_enet_offset = 331 (val & ENET_INIT_PARAM_PTR_MASK); 332 qe_muram_free(init_enet_offset); 333 } 334 *p_start++ = 0; 335 } 336 } 337 338 return 0; 339 } 340 341 #ifdef DEBUG 342 static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 343 u32 __iomem *p_start, 344 u8 num_entries, 345 u32 thread_size, 346 unsigned int risc, 347 int skip_page_for_first_entry) 348 { 349 u32 init_enet_offset; 350 u8 i; 351 int snum; 352 353 for (i = 0; i < num_entries; i++) { 354 u32 val = in_be32(p_start); 355 356 /* Check that this entry was actually valid -- 357 needed in case failed in allocations */ 358 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 359 snum = 360 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 361 ENET_INIT_PARAM_SNUM_SHIFT; 362 qe_put_snum((u8) snum); 363 if (!((i == 0) && skip_page_for_first_entry)) { 364 /* First entry of Rx does not have page */ 365 init_enet_offset = 366 (in_be32(p_start) & 367 ENET_INIT_PARAM_PTR_MASK); 368 pr_info("Init enet entry %d:\n", i); 369 pr_info("Base address: 0x%08x\n", 370 (u32)qe_muram_addr(init_enet_offset)); 371 mem_disp(qe_muram_addr(init_enet_offset), 372 thread_size); 373 } 374 p_start++; 375 } 376 } 377 378 return 0; 379 } 380 #endif 381 382 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 383 { 384 kfree(enet_addr_cont); 385 } 386 387 static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 388 { 389 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 390 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 391 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 392 } 393 394 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 395 { 396 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 397 398 if (paddr_num >= NUM_OF_PADDRS) { 399 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 400 return -EINVAL; 401 } 402 403 p_82xx_addr_filt = 404 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 405 addressfiltering; 406 407 /* Writing address ff.ff.ff.ff.ff.ff disables address 408 recognition for this register */ 409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 412 413 return 0; 414 } 415 416 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 417 u8 *p_enet_addr) 418 { 419 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 420 u32 cecr_subblock; 421 422 p_82xx_addr_filt = 423 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 424 addressfiltering; 425 426 cecr_subblock = 427 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 428 429 /* Ethernet frames are defined in Little Endian mode, 430 therefore to insert */ 431 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 432 433 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 434 435 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 436 QE_CR_PROTOCOL_ETHERNET, 0); 437 } 438 439 #ifdef DEBUG 440 static void get_statistics(struct ucc_geth_private *ugeth, 441 struct ucc_geth_tx_firmware_statistics * 442 tx_firmware_statistics, 443 struct ucc_geth_rx_firmware_statistics * 444 rx_firmware_statistics, 445 struct ucc_geth_hardware_statistics *hardware_statistics) 446 { 447 struct ucc_fast __iomem *uf_regs; 448 struct ucc_geth __iomem *ug_regs; 449 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 450 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 451 452 ug_regs = ugeth->ug_regs; 453 uf_regs = (struct ucc_fast __iomem *) ug_regs; 454 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 455 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 456 457 /* Tx firmware only if user handed pointer and driver actually 458 gathers Tx firmware statistics */ 459 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 460 tx_firmware_statistics->sicoltx = 461 in_be32(&p_tx_fw_statistics_pram->sicoltx); 462 tx_firmware_statistics->mulcoltx = 463 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 464 tx_firmware_statistics->latecoltxfr = 465 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 466 tx_firmware_statistics->frabortduecol = 467 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 468 tx_firmware_statistics->frlostinmactxer = 469 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 470 tx_firmware_statistics->carriersenseertx = 471 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 472 tx_firmware_statistics->frtxok = 473 in_be32(&p_tx_fw_statistics_pram->frtxok); 474 tx_firmware_statistics->txfrexcessivedefer = 475 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 476 tx_firmware_statistics->txpkts256 = 477 in_be32(&p_tx_fw_statistics_pram->txpkts256); 478 tx_firmware_statistics->txpkts512 = 479 in_be32(&p_tx_fw_statistics_pram->txpkts512); 480 tx_firmware_statistics->txpkts1024 = 481 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 482 tx_firmware_statistics->txpktsjumbo = 483 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 484 } 485 486 /* Rx firmware only if user handed pointer and driver actually 487 * gathers Rx firmware statistics */ 488 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 489 int i; 490 rx_firmware_statistics->frrxfcser = 491 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 492 rx_firmware_statistics->fraligner = 493 in_be32(&p_rx_fw_statistics_pram->fraligner); 494 rx_firmware_statistics->inrangelenrxer = 495 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 496 rx_firmware_statistics->outrangelenrxer = 497 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 498 rx_firmware_statistics->frtoolong = 499 in_be32(&p_rx_fw_statistics_pram->frtoolong); 500 rx_firmware_statistics->runt = 501 in_be32(&p_rx_fw_statistics_pram->runt); 502 rx_firmware_statistics->verylongevent = 503 in_be32(&p_rx_fw_statistics_pram->verylongevent); 504 rx_firmware_statistics->symbolerror = 505 in_be32(&p_rx_fw_statistics_pram->symbolerror); 506 rx_firmware_statistics->dropbsy = 507 in_be32(&p_rx_fw_statistics_pram->dropbsy); 508 for (i = 0; i < 0x8; i++) 509 rx_firmware_statistics->res0[i] = 510 p_rx_fw_statistics_pram->res0[i]; 511 rx_firmware_statistics->mismatchdrop = 512 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 513 rx_firmware_statistics->underpkts = 514 in_be32(&p_rx_fw_statistics_pram->underpkts); 515 rx_firmware_statistics->pkts256 = 516 in_be32(&p_rx_fw_statistics_pram->pkts256); 517 rx_firmware_statistics->pkts512 = 518 in_be32(&p_rx_fw_statistics_pram->pkts512); 519 rx_firmware_statistics->pkts1024 = 520 in_be32(&p_rx_fw_statistics_pram->pkts1024); 521 rx_firmware_statistics->pktsjumbo = 522 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 523 rx_firmware_statistics->frlossinmacer = 524 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 525 rx_firmware_statistics->pausefr = 526 in_be32(&p_rx_fw_statistics_pram->pausefr); 527 for (i = 0; i < 0x4; i++) 528 rx_firmware_statistics->res1[i] = 529 p_rx_fw_statistics_pram->res1[i]; 530 rx_firmware_statistics->removevlan = 531 in_be32(&p_rx_fw_statistics_pram->removevlan); 532 rx_firmware_statistics->replacevlan = 533 in_be32(&p_rx_fw_statistics_pram->replacevlan); 534 rx_firmware_statistics->insertvlan = 535 in_be32(&p_rx_fw_statistics_pram->insertvlan); 536 } 537 538 /* Hardware only if user handed pointer and driver actually 539 gathers hardware statistics */ 540 if (hardware_statistics && 541 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 542 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 543 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 544 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 545 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 546 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 547 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 548 hardware_statistics->txok = in_be32(&ug_regs->txok); 549 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 550 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 551 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 552 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 553 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 554 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 555 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 556 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 557 } 558 } 559 560 static void dump_bds(struct ucc_geth_private *ugeth) 561 { 562 int i; 563 int length; 564 565 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 566 if (ugeth->p_tx_bd_ring[i]) { 567 length = 568 (ugeth->ug_info->bdRingLenTx[i] * 569 sizeof(struct qe_bd)); 570 pr_info("TX BDs[%d]\n", i); 571 mem_disp(ugeth->p_tx_bd_ring[i], length); 572 } 573 } 574 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 575 if (ugeth->p_rx_bd_ring[i]) { 576 length = 577 (ugeth->ug_info->bdRingLenRx[i] * 578 sizeof(struct qe_bd)); 579 pr_info("RX BDs[%d]\n", i); 580 mem_disp(ugeth->p_rx_bd_ring[i], length); 581 } 582 } 583 } 584 585 static void dump_regs(struct ucc_geth_private *ugeth) 586 { 587 int i; 588 589 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 590 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 591 592 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 593 (u32)&ugeth->ug_regs->maccfg1, 594 in_be32(&ugeth->ug_regs->maccfg1)); 595 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 596 (u32)&ugeth->ug_regs->maccfg2, 597 in_be32(&ugeth->ug_regs->maccfg2)); 598 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 599 (u32)&ugeth->ug_regs->ipgifg, 600 in_be32(&ugeth->ug_regs->ipgifg)); 601 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 602 (u32)&ugeth->ug_regs->hafdup, 603 in_be32(&ugeth->ug_regs->hafdup)); 604 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 605 (u32)&ugeth->ug_regs->ifctl, 606 in_be32(&ugeth->ug_regs->ifctl)); 607 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 608 (u32)&ugeth->ug_regs->ifstat, 609 in_be32(&ugeth->ug_regs->ifstat)); 610 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 611 (u32)&ugeth->ug_regs->macstnaddr1, 612 in_be32(&ugeth->ug_regs->macstnaddr1)); 613 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 614 (u32)&ugeth->ug_regs->macstnaddr2, 615 in_be32(&ugeth->ug_regs->macstnaddr2)); 616 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 617 (u32)&ugeth->ug_regs->uempr, 618 in_be32(&ugeth->ug_regs->uempr)); 619 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 620 (u32)&ugeth->ug_regs->utbipar, 621 in_be32(&ugeth->ug_regs->utbipar)); 622 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 623 (u32)&ugeth->ug_regs->uescr, 624 in_be16(&ugeth->ug_regs->uescr)); 625 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 626 (u32)&ugeth->ug_regs->tx64, 627 in_be32(&ugeth->ug_regs->tx64)); 628 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 629 (u32)&ugeth->ug_regs->tx127, 630 in_be32(&ugeth->ug_regs->tx127)); 631 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 632 (u32)&ugeth->ug_regs->tx255, 633 in_be32(&ugeth->ug_regs->tx255)); 634 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 635 (u32)&ugeth->ug_regs->rx64, 636 in_be32(&ugeth->ug_regs->rx64)); 637 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 638 (u32)&ugeth->ug_regs->rx127, 639 in_be32(&ugeth->ug_regs->rx127)); 640 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 641 (u32)&ugeth->ug_regs->rx255, 642 in_be32(&ugeth->ug_regs->rx255)); 643 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 644 (u32)&ugeth->ug_regs->txok, 645 in_be32(&ugeth->ug_regs->txok)); 646 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 647 (u32)&ugeth->ug_regs->txcf, 648 in_be16(&ugeth->ug_regs->txcf)); 649 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 650 (u32)&ugeth->ug_regs->tmca, 651 in_be32(&ugeth->ug_regs->tmca)); 652 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 653 (u32)&ugeth->ug_regs->tbca, 654 in_be32(&ugeth->ug_regs->tbca)); 655 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 656 (u32)&ugeth->ug_regs->rxfok, 657 in_be32(&ugeth->ug_regs->rxfok)); 658 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 659 (u32)&ugeth->ug_regs->rxbok, 660 in_be32(&ugeth->ug_regs->rxbok)); 661 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 662 (u32)&ugeth->ug_regs->rbyt, 663 in_be32(&ugeth->ug_regs->rbyt)); 664 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 665 (u32)&ugeth->ug_regs->rmca, 666 in_be32(&ugeth->ug_regs->rmca)); 667 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 668 (u32)&ugeth->ug_regs->rbca, 669 in_be32(&ugeth->ug_regs->rbca)); 670 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 671 (u32)&ugeth->ug_regs->scar, 672 in_be32(&ugeth->ug_regs->scar)); 673 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 674 (u32)&ugeth->ug_regs->scam, 675 in_be32(&ugeth->ug_regs->scam)); 676 677 if (ugeth->p_thread_data_tx) { 678 int numThreadsTxNumerical; 679 switch (ugeth->ug_info->numThreadsTx) { 680 case UCC_GETH_NUM_OF_THREADS_1: 681 numThreadsTxNumerical = 1; 682 break; 683 case UCC_GETH_NUM_OF_THREADS_2: 684 numThreadsTxNumerical = 2; 685 break; 686 case UCC_GETH_NUM_OF_THREADS_4: 687 numThreadsTxNumerical = 4; 688 break; 689 case UCC_GETH_NUM_OF_THREADS_6: 690 numThreadsTxNumerical = 6; 691 break; 692 case UCC_GETH_NUM_OF_THREADS_8: 693 numThreadsTxNumerical = 8; 694 break; 695 default: 696 numThreadsTxNumerical = 0; 697 break; 698 } 699 700 pr_info("Thread data TXs:\n"); 701 pr_info("Base address: 0x%08x\n", 702 (u32)ugeth->p_thread_data_tx); 703 for (i = 0; i < numThreadsTxNumerical; i++) { 704 pr_info("Thread data TX[%d]:\n", i); 705 pr_info("Base address: 0x%08x\n", 706 (u32)&ugeth->p_thread_data_tx[i]); 707 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 708 sizeof(struct ucc_geth_thread_data_tx)); 709 } 710 } 711 if (ugeth->p_thread_data_rx) { 712 int numThreadsRxNumerical; 713 switch (ugeth->ug_info->numThreadsRx) { 714 case UCC_GETH_NUM_OF_THREADS_1: 715 numThreadsRxNumerical = 1; 716 break; 717 case UCC_GETH_NUM_OF_THREADS_2: 718 numThreadsRxNumerical = 2; 719 break; 720 case UCC_GETH_NUM_OF_THREADS_4: 721 numThreadsRxNumerical = 4; 722 break; 723 case UCC_GETH_NUM_OF_THREADS_6: 724 numThreadsRxNumerical = 6; 725 break; 726 case UCC_GETH_NUM_OF_THREADS_8: 727 numThreadsRxNumerical = 8; 728 break; 729 default: 730 numThreadsRxNumerical = 0; 731 break; 732 } 733 734 pr_info("Thread data RX:\n"); 735 pr_info("Base address: 0x%08x\n", 736 (u32)ugeth->p_thread_data_rx); 737 for (i = 0; i < numThreadsRxNumerical; i++) { 738 pr_info("Thread data RX[%d]:\n", i); 739 pr_info("Base address: 0x%08x\n", 740 (u32)&ugeth->p_thread_data_rx[i]); 741 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 742 sizeof(struct ucc_geth_thread_data_rx)); 743 } 744 } 745 if (ugeth->p_exf_glbl_param) { 746 pr_info("EXF global param:\n"); 747 pr_info("Base address: 0x%08x\n", 748 (u32)ugeth->p_exf_glbl_param); 749 mem_disp((u8 *) ugeth->p_exf_glbl_param, 750 sizeof(*ugeth->p_exf_glbl_param)); 751 } 752 if (ugeth->p_tx_glbl_pram) { 753 pr_info("TX global param:\n"); 754 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 755 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 756 (u32)&ugeth->p_tx_glbl_pram->temoder, 757 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 758 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 759 (u32)&ugeth->p_tx_glbl_pram->sqptr, 760 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 761 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 762 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 763 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 764 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 765 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 766 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 767 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 768 (u32)&ugeth->p_tx_glbl_pram->tstate, 769 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 770 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 771 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 772 ugeth->p_tx_glbl_pram->iphoffset[0]); 773 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 774 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 775 ugeth->p_tx_glbl_pram->iphoffset[1]); 776 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 777 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 778 ugeth->p_tx_glbl_pram->iphoffset[2]); 779 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 780 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 781 ugeth->p_tx_glbl_pram->iphoffset[3]); 782 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 783 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 784 ugeth->p_tx_glbl_pram->iphoffset[4]); 785 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 786 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 787 ugeth->p_tx_glbl_pram->iphoffset[5]); 788 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 789 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 790 ugeth->p_tx_glbl_pram->iphoffset[6]); 791 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 792 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 793 ugeth->p_tx_glbl_pram->iphoffset[7]); 794 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 795 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 796 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 797 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 798 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 799 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 800 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 801 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 802 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 803 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 804 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 806 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 807 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 809 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 810 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 812 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 813 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 815 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 816 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 817 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 818 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 819 (u32)&ugeth->p_tx_glbl_pram->tqptr, 820 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 821 } 822 if (ugeth->p_rx_glbl_pram) { 823 pr_info("RX global param:\n"); 824 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 825 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 826 (u32)&ugeth->p_rx_glbl_pram->remoder, 827 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 828 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 829 (u32)&ugeth->p_rx_glbl_pram->rqptr, 830 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 831 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 832 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 833 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 834 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 835 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 836 ugeth->p_rx_glbl_pram->rxgstpack); 837 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 838 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 839 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 840 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 841 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 842 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 843 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 844 (u32)&ugeth->p_rx_glbl_pram->rstate, 845 ugeth->p_rx_glbl_pram->rstate); 846 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 847 (u32)&ugeth->p_rx_glbl_pram->mrblr, 848 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 849 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 850 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 851 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 852 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 853 (u32)&ugeth->p_rx_glbl_pram->mflr, 854 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 855 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 856 (u32)&ugeth->p_rx_glbl_pram->minflr, 857 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 858 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 859 (u32)&ugeth->p_rx_glbl_pram->maxd1, 860 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 861 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 862 (u32)&ugeth->p_rx_glbl_pram->maxd2, 863 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 864 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 865 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 866 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 867 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 868 (u32)&ugeth->p_rx_glbl_pram->l2qt, 869 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 870 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 871 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 872 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 873 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 874 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 875 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 876 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 877 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 878 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 879 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 880 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 882 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 883 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 885 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 886 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 888 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 889 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 891 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 892 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 893 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 894 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 895 (u32)&ugeth->p_rx_glbl_pram->vlantype, 896 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 897 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 898 (u32)&ugeth->p_rx_glbl_pram->vlantci, 899 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 900 for (i = 0; i < 64; i++) 901 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 902 i, 903 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 904 ugeth->p_rx_glbl_pram->addressfiltering[i]); 905 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 906 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 907 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 908 } 909 if (ugeth->p_send_q_mem_reg) { 910 pr_info("Send Q memory registers:\n"); 911 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 912 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 913 pr_info("SQQD[%d]:\n", i); 914 pr_info("Base address: 0x%08x\n", 915 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 916 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 917 sizeof(struct ucc_geth_send_queue_qd)); 918 } 919 } 920 if (ugeth->p_scheduler) { 921 pr_info("Scheduler:\n"); 922 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 923 mem_disp((u8 *) ugeth->p_scheduler, 924 sizeof(*ugeth->p_scheduler)); 925 } 926 if (ugeth->p_tx_fw_statistics_pram) { 927 pr_info("TX FW statistics pram:\n"); 928 pr_info("Base address: 0x%08x\n", 929 (u32)ugeth->p_tx_fw_statistics_pram); 930 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 931 sizeof(*ugeth->p_tx_fw_statistics_pram)); 932 } 933 if (ugeth->p_rx_fw_statistics_pram) { 934 pr_info("RX FW statistics pram:\n"); 935 pr_info("Base address: 0x%08x\n", 936 (u32)ugeth->p_rx_fw_statistics_pram); 937 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 938 sizeof(*ugeth->p_rx_fw_statistics_pram)); 939 } 940 if (ugeth->p_rx_irq_coalescing_tbl) { 941 pr_info("RX IRQ coalescing tables:\n"); 942 pr_info("Base address: 0x%08x\n", 943 (u32)ugeth->p_rx_irq_coalescing_tbl); 944 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 945 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 946 pr_info("Base address: 0x%08x\n", 947 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 948 coalescingentry[i]); 949 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 950 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 951 coalescingentry[i].interruptcoalescingmaxvalue, 952 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 953 coalescingentry[i]. 954 interruptcoalescingmaxvalue)); 955 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 956 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 957 coalescingentry[i].interruptcoalescingcounter, 958 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 959 coalescingentry[i]. 960 interruptcoalescingcounter)); 961 } 962 } 963 if (ugeth->p_rx_bd_qs_tbl) { 964 pr_info("RX BD QS tables:\n"); 965 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 966 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 967 pr_info("RX BD QS table[%d]:\n", i); 968 pr_info("Base address: 0x%08x\n", 969 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 970 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 971 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 972 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 973 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 974 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 975 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 976 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 977 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 978 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 979 externalbdbaseptr)); 980 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 981 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 982 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 983 pr_info("ucode RX Prefetched BDs:\n"); 984 pr_info("Base address: 0x%08x\n", 985 (u32)qe_muram_addr(in_be32 986 (&ugeth->p_rx_bd_qs_tbl[i]. 987 bdbaseptr))); 988 mem_disp((u8 *) 989 qe_muram_addr(in_be32 990 (&ugeth->p_rx_bd_qs_tbl[i]. 991 bdbaseptr)), 992 sizeof(struct ucc_geth_rx_prefetched_bds)); 993 } 994 } 995 if (ugeth->p_init_enet_param_shadow) { 996 int size; 997 pr_info("Init enet param shadow:\n"); 998 pr_info("Base address: 0x%08x\n", 999 (u32) ugeth->p_init_enet_param_shadow); 1000 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1001 sizeof(*ugeth->p_init_enet_param_shadow)); 1002 1003 size = sizeof(struct ucc_geth_thread_rx_pram); 1004 if (ugeth->ug_info->rxExtendedFiltering) { 1005 size += 1006 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1007 if (ugeth->ug_info->largestexternallookupkeysize == 1008 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1009 size += 1010 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1011 if (ugeth->ug_info->largestexternallookupkeysize == 1012 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1013 size += 1014 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1015 } 1016 1017 dump_init_enet_entries(ugeth, 1018 &(ugeth->p_init_enet_param_shadow-> 1019 txthread[0]), 1020 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1021 sizeof(struct ucc_geth_thread_tx_pram), 1022 ugeth->ug_info->riscTx, 0); 1023 dump_init_enet_entries(ugeth, 1024 &(ugeth->p_init_enet_param_shadow-> 1025 rxthread[0]), 1026 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1027 ugeth->ug_info->riscRx, 1); 1028 } 1029 } 1030 #endif /* DEBUG */ 1031 1032 static void init_default_reg_vals(u32 __iomem *upsmr_register, 1033 u32 __iomem *maccfg1_register, 1034 u32 __iomem *maccfg2_register) 1035 { 1036 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1037 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1038 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1039 } 1040 1041 static int init_half_duplex_params(int alt_beb, 1042 int back_pressure_no_backoff, 1043 int no_backoff, 1044 int excess_defer, 1045 u8 alt_beb_truncation, 1046 u8 max_retransmissions, 1047 u8 collision_window, 1048 u32 __iomem *hafdup_register) 1049 { 1050 u32 value = 0; 1051 1052 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1053 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1054 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1055 return -EINVAL; 1056 1057 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1058 1059 if (alt_beb) 1060 value |= HALFDUP_ALT_BEB; 1061 if (back_pressure_no_backoff) 1062 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1063 if (no_backoff) 1064 value |= HALFDUP_NO_BACKOFF; 1065 if (excess_defer) 1066 value |= HALFDUP_EXCESSIVE_DEFER; 1067 1068 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1069 1070 value |= collision_window; 1071 1072 out_be32(hafdup_register, value); 1073 return 0; 1074 } 1075 1076 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1077 u8 non_btb_ipg, 1078 u8 min_ifg, 1079 u8 btb_ipg, 1080 u32 __iomem *ipgifg_register) 1081 { 1082 u32 value = 0; 1083 1084 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1085 IPG part 2 */ 1086 if (non_btb_cs_ipg > non_btb_ipg) 1087 return -EINVAL; 1088 1089 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1090 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1091 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1092 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1093 return -EINVAL; 1094 1095 value |= 1096 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1097 IPGIFG_NBTB_CS_IPG_MASK); 1098 value |= 1099 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1100 IPGIFG_NBTB_IPG_MASK); 1101 value |= 1102 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1103 IPGIFG_MIN_IFG_MASK); 1104 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1105 1106 out_be32(ipgifg_register, value); 1107 return 0; 1108 } 1109 1110 int init_flow_control_params(u32 automatic_flow_control_mode, 1111 int rx_flow_control_enable, 1112 int tx_flow_control_enable, 1113 u16 pause_period, 1114 u16 extension_field, 1115 u32 __iomem *upsmr_register, 1116 u32 __iomem *uempr_register, 1117 u32 __iomem *maccfg1_register) 1118 { 1119 u32 value = 0; 1120 1121 /* Set UEMPR register */ 1122 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1123 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1124 out_be32(uempr_register, value); 1125 1126 /* Set UPSMR register */ 1127 setbits32(upsmr_register, automatic_flow_control_mode); 1128 1129 value = in_be32(maccfg1_register); 1130 if (rx_flow_control_enable) 1131 value |= MACCFG1_FLOW_RX; 1132 if (tx_flow_control_enable) 1133 value |= MACCFG1_FLOW_TX; 1134 out_be32(maccfg1_register, value); 1135 1136 return 0; 1137 } 1138 1139 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1140 int auto_zero_hardware_statistics, 1141 u32 __iomem *upsmr_register, 1142 u16 __iomem *uescr_register) 1143 { 1144 u16 uescr_value = 0; 1145 1146 /* Enable hardware statistics gathering if requested */ 1147 if (enable_hardware_statistics) 1148 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1149 1150 /* Clear hardware statistics counters */ 1151 uescr_value = in_be16(uescr_register); 1152 uescr_value |= UESCR_CLRCNT; 1153 /* Automatically zero hardware statistics counters on read, 1154 if requested */ 1155 if (auto_zero_hardware_statistics) 1156 uescr_value |= UESCR_AUTOZ; 1157 out_be16(uescr_register, uescr_value); 1158 1159 return 0; 1160 } 1161 1162 static int init_firmware_statistics_gathering_mode(int 1163 enable_tx_firmware_statistics, 1164 int enable_rx_firmware_statistics, 1165 u32 __iomem *tx_rmon_base_ptr, 1166 u32 tx_firmware_statistics_structure_address, 1167 u32 __iomem *rx_rmon_base_ptr, 1168 u32 rx_firmware_statistics_structure_address, 1169 u16 __iomem *temoder_register, 1170 u32 __iomem *remoder_register) 1171 { 1172 /* Note: this function does not check if */ 1173 /* the parameters it receives are NULL */ 1174 1175 if (enable_tx_firmware_statistics) { 1176 out_be32(tx_rmon_base_ptr, 1177 tx_firmware_statistics_structure_address); 1178 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1179 } 1180 1181 if (enable_rx_firmware_statistics) { 1182 out_be32(rx_rmon_base_ptr, 1183 rx_firmware_statistics_structure_address); 1184 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1185 } 1186 1187 return 0; 1188 } 1189 1190 static int init_mac_station_addr_regs(u8 address_byte_0, 1191 u8 address_byte_1, 1192 u8 address_byte_2, 1193 u8 address_byte_3, 1194 u8 address_byte_4, 1195 u8 address_byte_5, 1196 u32 __iomem *macstnaddr1_register, 1197 u32 __iomem *macstnaddr2_register) 1198 { 1199 u32 value = 0; 1200 1201 /* Example: for a station address of 0x12345678ABCD, */ 1202 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1203 1204 /* MACSTNADDR1 Register: */ 1205 1206 /* 0 7 8 15 */ 1207 /* station address byte 5 station address byte 4 */ 1208 /* 16 23 24 31 */ 1209 /* station address byte 3 station address byte 2 */ 1210 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1211 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1212 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1213 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1214 1215 out_be32(macstnaddr1_register, value); 1216 1217 /* MACSTNADDR2 Register: */ 1218 1219 /* 0 7 8 15 */ 1220 /* station address byte 1 station address byte 0 */ 1221 /* 16 23 24 31 */ 1222 /* reserved reserved */ 1223 value = 0; 1224 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1225 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1226 1227 out_be32(macstnaddr2_register, value); 1228 1229 return 0; 1230 } 1231 1232 static int init_check_frame_length_mode(int length_check, 1233 u32 __iomem *maccfg2_register) 1234 { 1235 u32 value = 0; 1236 1237 value = in_be32(maccfg2_register); 1238 1239 if (length_check) 1240 value |= MACCFG2_LC; 1241 else 1242 value &= ~MACCFG2_LC; 1243 1244 out_be32(maccfg2_register, value); 1245 return 0; 1246 } 1247 1248 static int init_preamble_length(u8 preamble_length, 1249 u32 __iomem *maccfg2_register) 1250 { 1251 if ((preamble_length < 3) || (preamble_length > 7)) 1252 return -EINVAL; 1253 1254 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1255 preamble_length << MACCFG2_PREL_SHIFT); 1256 1257 return 0; 1258 } 1259 1260 static int init_rx_parameters(int reject_broadcast, 1261 int receive_short_frames, 1262 int promiscuous, u32 __iomem *upsmr_register) 1263 { 1264 u32 value = 0; 1265 1266 value = in_be32(upsmr_register); 1267 1268 if (reject_broadcast) 1269 value |= UCC_GETH_UPSMR_BRO; 1270 else 1271 value &= ~UCC_GETH_UPSMR_BRO; 1272 1273 if (receive_short_frames) 1274 value |= UCC_GETH_UPSMR_RSH; 1275 else 1276 value &= ~UCC_GETH_UPSMR_RSH; 1277 1278 if (promiscuous) 1279 value |= UCC_GETH_UPSMR_PRO; 1280 else 1281 value &= ~UCC_GETH_UPSMR_PRO; 1282 1283 out_be32(upsmr_register, value); 1284 1285 return 0; 1286 } 1287 1288 static int init_max_rx_buff_len(u16 max_rx_buf_len, 1289 u16 __iomem *mrblr_register) 1290 { 1291 /* max_rx_buf_len value must be a multiple of 128 */ 1292 if ((max_rx_buf_len == 0) || 1293 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1294 return -EINVAL; 1295 1296 out_be16(mrblr_register, max_rx_buf_len); 1297 return 0; 1298 } 1299 1300 static int init_min_frame_len(u16 min_frame_length, 1301 u16 __iomem *minflr_register, 1302 u16 __iomem *mrblr_register) 1303 { 1304 u16 mrblr_value = 0; 1305 1306 mrblr_value = in_be16(mrblr_register); 1307 if (min_frame_length >= (mrblr_value - 4)) 1308 return -EINVAL; 1309 1310 out_be16(minflr_register, min_frame_length); 1311 return 0; 1312 } 1313 1314 static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1315 { 1316 struct ucc_geth_info *ug_info; 1317 struct ucc_geth __iomem *ug_regs; 1318 struct ucc_fast __iomem *uf_regs; 1319 int ret_val; 1320 u32 upsmr, maccfg2; 1321 u16 value; 1322 1323 ugeth_vdbg("%s: IN", __func__); 1324 1325 ug_info = ugeth->ug_info; 1326 ug_regs = ugeth->ug_regs; 1327 uf_regs = ugeth->uccf->uf_regs; 1328 1329 /* Set MACCFG2 */ 1330 maccfg2 = in_be32(&ug_regs->maccfg2); 1331 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1332 if ((ugeth->max_speed == SPEED_10) || 1333 (ugeth->max_speed == SPEED_100)) 1334 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1335 else if (ugeth->max_speed == SPEED_1000) 1336 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1337 maccfg2 |= ug_info->padAndCrc; 1338 out_be32(&ug_regs->maccfg2, maccfg2); 1339 1340 /* Set UPSMR */ 1341 upsmr = in_be32(&uf_regs->upsmr); 1342 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1343 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1344 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1349 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1350 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1351 upsmr |= UCC_GETH_UPSMR_RPM; 1352 switch (ugeth->max_speed) { 1353 case SPEED_10: 1354 upsmr |= UCC_GETH_UPSMR_R10M; 1355 /* FALLTHROUGH */ 1356 case SPEED_100: 1357 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1358 upsmr |= UCC_GETH_UPSMR_RMM; 1359 } 1360 } 1361 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1362 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1363 upsmr |= UCC_GETH_UPSMR_TBIM; 1364 } 1365 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1366 upsmr |= UCC_GETH_UPSMR_SGMM; 1367 1368 out_be32(&uf_regs->upsmr, upsmr); 1369 1370 /* Disable autonegotiation in tbi mode, because by default it 1371 comes up in autonegotiation mode. */ 1372 /* Note that this depends on proper setting in utbipar register. */ 1373 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1374 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1375 struct ucc_geth_info *ug_info = ugeth->ug_info; 1376 struct phy_device *tbiphy; 1377 1378 if (!ug_info->tbi_node) 1379 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1380 1381 tbiphy = of_phy_find_device(ug_info->tbi_node); 1382 if (!tbiphy) 1383 pr_warn("Could not get TBI device\n"); 1384 1385 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1386 value &= ~0x1000; /* Turn off autonegotiation */ 1387 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1388 1389 put_device(&tbiphy->mdio.dev); 1390 } 1391 1392 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1393 1394 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1395 if (ret_val != 0) { 1396 if (netif_msg_probe(ugeth)) 1397 pr_err("Preamble length must be between 3 and 7 inclusive\n"); 1398 return ret_val; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1405 { 1406 struct ucc_fast_private *uccf; 1407 u32 cecr_subblock; 1408 u32 temp; 1409 int i = 10; 1410 1411 uccf = ugeth->uccf; 1412 1413 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1414 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1415 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1416 1417 /* Issue host command */ 1418 cecr_subblock = 1419 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1420 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1421 QE_CR_PROTOCOL_ETHERNET, 0); 1422 1423 /* Wait for command to complete */ 1424 do { 1425 msleep(10); 1426 temp = in_be32(uccf->p_ucce); 1427 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1428 1429 uccf->stopped_tx = 1; 1430 1431 return 0; 1432 } 1433 1434 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1435 { 1436 struct ucc_fast_private *uccf; 1437 u32 cecr_subblock; 1438 u8 temp; 1439 int i = 10; 1440 1441 uccf = ugeth->uccf; 1442 1443 /* Clear acknowledge bit */ 1444 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1445 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1446 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1447 1448 /* Keep issuing command and checking acknowledge bit until 1449 it is asserted, according to spec */ 1450 do { 1451 /* Issue host command */ 1452 cecr_subblock = 1453 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1454 ucc_num); 1455 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1456 QE_CR_PROTOCOL_ETHERNET, 0); 1457 msleep(10); 1458 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1459 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1460 1461 uccf->stopped_rx = 1; 1462 1463 return 0; 1464 } 1465 1466 static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1467 { 1468 struct ucc_fast_private *uccf; 1469 u32 cecr_subblock; 1470 1471 uccf = ugeth->uccf; 1472 1473 cecr_subblock = 1474 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1475 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1476 uccf->stopped_tx = 0; 1477 1478 return 0; 1479 } 1480 1481 static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1482 { 1483 struct ucc_fast_private *uccf; 1484 u32 cecr_subblock; 1485 1486 uccf = ugeth->uccf; 1487 1488 cecr_subblock = 1489 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1490 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1491 0); 1492 uccf->stopped_rx = 0; 1493 1494 return 0; 1495 } 1496 1497 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1498 { 1499 struct ucc_fast_private *uccf; 1500 int enabled_tx, enabled_rx; 1501 1502 uccf = ugeth->uccf; 1503 1504 /* check if the UCC number is in range. */ 1505 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1506 if (netif_msg_probe(ugeth)) 1507 pr_err("ucc_num out of range\n"); 1508 return -EINVAL; 1509 } 1510 1511 enabled_tx = uccf->enabled_tx; 1512 enabled_rx = uccf->enabled_rx; 1513 1514 /* Get Tx and Rx going again, in case this channel was actively 1515 disabled. */ 1516 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1517 ugeth_restart_tx(ugeth); 1518 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1519 ugeth_restart_rx(ugeth); 1520 1521 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1522 1523 return 0; 1524 1525 } 1526 1527 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1528 { 1529 struct ucc_fast_private *uccf; 1530 1531 uccf = ugeth->uccf; 1532 1533 /* check if the UCC number is in range. */ 1534 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1535 if (netif_msg_probe(ugeth)) 1536 pr_err("ucc_num out of range\n"); 1537 return -EINVAL; 1538 } 1539 1540 /* Stop any transmissions */ 1541 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1542 ugeth_graceful_stop_tx(ugeth); 1543 1544 /* Stop any receptions */ 1545 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1546 ugeth_graceful_stop_rx(ugeth); 1547 1548 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1549 1550 return 0; 1551 } 1552 1553 static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1554 { 1555 /* Prevent any further xmits, plus detach the device. */ 1556 netif_device_detach(ugeth->ndev); 1557 1558 /* Wait for any current xmits to finish. */ 1559 netif_tx_disable(ugeth->ndev); 1560 1561 /* Disable the interrupt to avoid NAPI rescheduling. */ 1562 disable_irq(ugeth->ug_info->uf_info.irq); 1563 1564 /* Stop NAPI, and possibly wait for its completion. */ 1565 napi_disable(&ugeth->napi); 1566 } 1567 1568 static void ugeth_activate(struct ucc_geth_private *ugeth) 1569 { 1570 napi_enable(&ugeth->napi); 1571 enable_irq(ugeth->ug_info->uf_info.irq); 1572 netif_device_attach(ugeth->ndev); 1573 } 1574 1575 /* Called every time the controller might need to be made 1576 * aware of new link state. The PHY code conveys this 1577 * information through variables in the ugeth structure, and this 1578 * function converts those variables into the appropriate 1579 * register values, and can bring down the device if needed. 1580 */ 1581 1582 static void adjust_link(struct net_device *dev) 1583 { 1584 struct ucc_geth_private *ugeth = netdev_priv(dev); 1585 struct ucc_geth __iomem *ug_regs; 1586 struct ucc_fast __iomem *uf_regs; 1587 struct phy_device *phydev = ugeth->phydev; 1588 int new_state = 0; 1589 1590 ug_regs = ugeth->ug_regs; 1591 uf_regs = ugeth->uccf->uf_regs; 1592 1593 if (phydev->link) { 1594 u32 tempval = in_be32(&ug_regs->maccfg2); 1595 u32 upsmr = in_be32(&uf_regs->upsmr); 1596 /* Now we make sure that we can be in full duplex mode. 1597 * If not, we operate in half-duplex mode. */ 1598 if (phydev->duplex != ugeth->oldduplex) { 1599 new_state = 1; 1600 if (!(phydev->duplex)) 1601 tempval &= ~(MACCFG2_FDX); 1602 else 1603 tempval |= MACCFG2_FDX; 1604 ugeth->oldduplex = phydev->duplex; 1605 } 1606 1607 if (phydev->speed != ugeth->oldspeed) { 1608 new_state = 1; 1609 switch (phydev->speed) { 1610 case SPEED_1000: 1611 tempval = ((tempval & 1612 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1613 MACCFG2_INTERFACE_MODE_BYTE); 1614 break; 1615 case SPEED_100: 1616 case SPEED_10: 1617 tempval = ((tempval & 1618 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1619 MACCFG2_INTERFACE_MODE_NIBBLE); 1620 /* if reduced mode, re-set UPSMR.R10M */ 1621 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1626 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1627 if (phydev->speed == SPEED_10) 1628 upsmr |= UCC_GETH_UPSMR_R10M; 1629 else 1630 upsmr &= ~UCC_GETH_UPSMR_R10M; 1631 } 1632 break; 1633 default: 1634 if (netif_msg_link(ugeth)) 1635 pr_warn( 1636 "%s: Ack! Speed (%d) is not 10/100/1000!", 1637 dev->name, phydev->speed); 1638 break; 1639 } 1640 ugeth->oldspeed = phydev->speed; 1641 } 1642 1643 if (!ugeth->oldlink) { 1644 new_state = 1; 1645 ugeth->oldlink = 1; 1646 } 1647 1648 if (new_state) { 1649 /* 1650 * To change the MAC configuration we need to disable 1651 * the controller. To do so, we have to either grab 1652 * ugeth->lock, which is a bad idea since 'graceful 1653 * stop' commands might take quite a while, or we can 1654 * quiesce driver's activity. 1655 */ 1656 ugeth_quiesce(ugeth); 1657 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1658 1659 out_be32(&ug_regs->maccfg2, tempval); 1660 out_be32(&uf_regs->upsmr, upsmr); 1661 1662 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1663 ugeth_activate(ugeth); 1664 } 1665 } else if (ugeth->oldlink) { 1666 new_state = 1; 1667 ugeth->oldlink = 0; 1668 ugeth->oldspeed = 0; 1669 ugeth->oldduplex = -1; 1670 } 1671 1672 if (new_state && netif_msg_link(ugeth)) 1673 phy_print_status(phydev); 1674 } 1675 1676 /* Initialize TBI PHY interface for communicating with the 1677 * SERDES lynx PHY on the chip. We communicate with this PHY 1678 * through the MDIO bus on each controller, treating it as a 1679 * "normal" PHY at the address found in the UTBIPA register. We assume 1680 * that the UTBIPA register is valid. Either the MDIO bus code will set 1681 * it to a value that doesn't conflict with other PHYs on the bus, or the 1682 * value doesn't matter, as there are no other PHYs on the bus. 1683 */ 1684 static void uec_configure_serdes(struct net_device *dev) 1685 { 1686 struct ucc_geth_private *ugeth = netdev_priv(dev); 1687 struct ucc_geth_info *ug_info = ugeth->ug_info; 1688 struct phy_device *tbiphy; 1689 1690 if (!ug_info->tbi_node) { 1691 dev_warn(&dev->dev, "SGMII mode requires that the device " 1692 "tree specify a tbi-handle\n"); 1693 return; 1694 } 1695 1696 tbiphy = of_phy_find_device(ug_info->tbi_node); 1697 if (!tbiphy) { 1698 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1699 return; 1700 } 1701 1702 /* 1703 * If the link is already up, we must already be ok, and don't need to 1704 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1705 * everything for us? Resetting it takes the link down and requires 1706 * several seconds for it to come back. 1707 */ 1708 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) { 1709 put_device(&tbiphy->mdio.dev); 1710 return; 1711 } 1712 1713 /* Single clk mode, mii mode off(for serdes communication) */ 1714 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1715 1716 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1717 1718 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1719 1720 put_device(&tbiphy->mdio.dev); 1721 } 1722 1723 /* Configure the PHY for dev. 1724 * returns 0 if success. -1 if failure 1725 */ 1726 static int init_phy(struct net_device *dev) 1727 { 1728 struct ucc_geth_private *priv = netdev_priv(dev); 1729 struct ucc_geth_info *ug_info = priv->ug_info; 1730 struct phy_device *phydev; 1731 1732 priv->oldlink = 0; 1733 priv->oldspeed = 0; 1734 priv->oldduplex = -1; 1735 1736 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1737 priv->phy_interface); 1738 if (!phydev) { 1739 dev_err(&dev->dev, "Could not attach to PHY\n"); 1740 return -ENODEV; 1741 } 1742 1743 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1744 uec_configure_serdes(dev); 1745 1746 phy_set_max_speed(phydev, priv->max_speed); 1747 1748 priv->phydev = phydev; 1749 1750 return 0; 1751 } 1752 1753 static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1754 { 1755 #ifdef DEBUG 1756 ucc_fast_dump_regs(ugeth->uccf); 1757 dump_regs(ugeth); 1758 dump_bds(ugeth); 1759 #endif 1760 } 1761 1762 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1763 ugeth, 1764 enum enet_addr_type 1765 enet_addr_type) 1766 { 1767 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1768 struct ucc_fast_private *uccf; 1769 enum comm_dir comm_dir; 1770 struct list_head *p_lh; 1771 u16 i, num; 1772 u32 __iomem *addr_h; 1773 u32 __iomem *addr_l; 1774 u8 *p_counter; 1775 1776 uccf = ugeth->uccf; 1777 1778 p_82xx_addr_filt = 1779 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1780 ugeth->p_rx_glbl_pram->addressfiltering; 1781 1782 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1783 addr_h = &(p_82xx_addr_filt->gaddr_h); 1784 addr_l = &(p_82xx_addr_filt->gaddr_l); 1785 p_lh = &ugeth->group_hash_q; 1786 p_counter = &(ugeth->numGroupAddrInHash); 1787 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1788 addr_h = &(p_82xx_addr_filt->iaddr_h); 1789 addr_l = &(p_82xx_addr_filt->iaddr_l); 1790 p_lh = &ugeth->ind_hash_q; 1791 p_counter = &(ugeth->numIndAddrInHash); 1792 } else 1793 return -EINVAL; 1794 1795 comm_dir = 0; 1796 if (uccf->enabled_tx) 1797 comm_dir |= COMM_DIR_TX; 1798 if (uccf->enabled_rx) 1799 comm_dir |= COMM_DIR_RX; 1800 if (comm_dir) 1801 ugeth_disable(ugeth, comm_dir); 1802 1803 /* Clear the hash table. */ 1804 out_be32(addr_h, 0x00000000); 1805 out_be32(addr_l, 0x00000000); 1806 1807 if (!p_lh) 1808 return 0; 1809 1810 num = *p_counter; 1811 1812 /* Delete all remaining CQ elements */ 1813 for (i = 0; i < num; i++) 1814 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1815 1816 *p_counter = 0; 1817 1818 if (comm_dir) 1819 ugeth_enable(ugeth, comm_dir); 1820 1821 return 0; 1822 } 1823 1824 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1825 u8 paddr_num) 1826 { 1827 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1828 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1829 } 1830 1831 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1832 { 1833 struct ucc_geth_info *ug_info; 1834 struct ucc_fast_info *uf_info; 1835 u16 i, j; 1836 u8 __iomem *bd; 1837 1838 1839 ug_info = ugeth->ug_info; 1840 uf_info = &ug_info->uf_info; 1841 1842 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1843 if (ugeth->p_rx_bd_ring[i]) { 1844 /* Return existing data buffers in ring */ 1845 bd = ugeth->p_rx_bd_ring[i]; 1846 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1847 if (ugeth->rx_skbuff[i][j]) { 1848 dma_unmap_single(ugeth->dev, 1849 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1850 ugeth->ug_info-> 1851 uf_info.max_rx_buf_length + 1852 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1853 DMA_FROM_DEVICE); 1854 dev_kfree_skb_any( 1855 ugeth->rx_skbuff[i][j]); 1856 ugeth->rx_skbuff[i][j] = NULL; 1857 } 1858 bd += sizeof(struct qe_bd); 1859 } 1860 1861 kfree(ugeth->rx_skbuff[i]); 1862 1863 if (ugeth->ug_info->uf_info.bd_mem_part == 1864 MEM_PART_SYSTEM) 1865 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1866 else if (ugeth->ug_info->uf_info.bd_mem_part == 1867 MEM_PART_MURAM) 1868 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1869 ugeth->p_rx_bd_ring[i] = NULL; 1870 } 1871 } 1872 1873 } 1874 1875 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1876 { 1877 struct ucc_geth_info *ug_info; 1878 struct ucc_fast_info *uf_info; 1879 u16 i, j; 1880 u8 __iomem *bd; 1881 1882 netdev_reset_queue(ugeth->ndev); 1883 1884 ug_info = ugeth->ug_info; 1885 uf_info = &ug_info->uf_info; 1886 1887 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1888 bd = ugeth->p_tx_bd_ring[i]; 1889 if (!bd) 1890 continue; 1891 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1892 if (ugeth->tx_skbuff[i][j]) { 1893 dma_unmap_single(ugeth->dev, 1894 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1895 (in_be32((u32 __iomem *)bd) & 1896 BD_LENGTH_MASK), 1897 DMA_TO_DEVICE); 1898 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1899 ugeth->tx_skbuff[i][j] = NULL; 1900 } 1901 } 1902 1903 kfree(ugeth->tx_skbuff[i]); 1904 1905 if (ugeth->p_tx_bd_ring[i]) { 1906 if (ugeth->ug_info->uf_info.bd_mem_part == 1907 MEM_PART_SYSTEM) 1908 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1909 else if (ugeth->ug_info->uf_info.bd_mem_part == 1910 MEM_PART_MURAM) 1911 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1912 ugeth->p_tx_bd_ring[i] = NULL; 1913 } 1914 } 1915 1916 } 1917 1918 static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1919 { 1920 if (!ugeth) 1921 return; 1922 1923 if (ugeth->uccf) { 1924 ucc_fast_free(ugeth->uccf); 1925 ugeth->uccf = NULL; 1926 } 1927 1928 if (ugeth->p_thread_data_tx) { 1929 qe_muram_free(ugeth->thread_dat_tx_offset); 1930 ugeth->p_thread_data_tx = NULL; 1931 } 1932 if (ugeth->p_thread_data_rx) { 1933 qe_muram_free(ugeth->thread_dat_rx_offset); 1934 ugeth->p_thread_data_rx = NULL; 1935 } 1936 if (ugeth->p_exf_glbl_param) { 1937 qe_muram_free(ugeth->exf_glbl_param_offset); 1938 ugeth->p_exf_glbl_param = NULL; 1939 } 1940 if (ugeth->p_rx_glbl_pram) { 1941 qe_muram_free(ugeth->rx_glbl_pram_offset); 1942 ugeth->p_rx_glbl_pram = NULL; 1943 } 1944 if (ugeth->p_tx_glbl_pram) { 1945 qe_muram_free(ugeth->tx_glbl_pram_offset); 1946 ugeth->p_tx_glbl_pram = NULL; 1947 } 1948 if (ugeth->p_send_q_mem_reg) { 1949 qe_muram_free(ugeth->send_q_mem_reg_offset); 1950 ugeth->p_send_q_mem_reg = NULL; 1951 } 1952 if (ugeth->p_scheduler) { 1953 qe_muram_free(ugeth->scheduler_offset); 1954 ugeth->p_scheduler = NULL; 1955 } 1956 if (ugeth->p_tx_fw_statistics_pram) { 1957 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1958 ugeth->p_tx_fw_statistics_pram = NULL; 1959 } 1960 if (ugeth->p_rx_fw_statistics_pram) { 1961 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1962 ugeth->p_rx_fw_statistics_pram = NULL; 1963 } 1964 if (ugeth->p_rx_irq_coalescing_tbl) { 1965 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1966 ugeth->p_rx_irq_coalescing_tbl = NULL; 1967 } 1968 if (ugeth->p_rx_bd_qs_tbl) { 1969 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1970 ugeth->p_rx_bd_qs_tbl = NULL; 1971 } 1972 if (ugeth->p_init_enet_param_shadow) { 1973 return_init_enet_entries(ugeth, 1974 &(ugeth->p_init_enet_param_shadow-> 1975 rxthread[0]), 1976 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1977 ugeth->ug_info->riscRx, 1); 1978 return_init_enet_entries(ugeth, 1979 &(ugeth->p_init_enet_param_shadow-> 1980 txthread[0]), 1981 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1982 ugeth->ug_info->riscTx, 0); 1983 kfree(ugeth->p_init_enet_param_shadow); 1984 ugeth->p_init_enet_param_shadow = NULL; 1985 } 1986 ucc_geth_free_tx(ugeth); 1987 ucc_geth_free_rx(ugeth); 1988 while (!list_empty(&ugeth->group_hash_q)) 1989 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1990 (dequeue(&ugeth->group_hash_q))); 1991 while (!list_empty(&ugeth->ind_hash_q)) 1992 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1993 (dequeue(&ugeth->ind_hash_q))); 1994 if (ugeth->ug_regs) { 1995 iounmap(ugeth->ug_regs); 1996 ugeth->ug_regs = NULL; 1997 } 1998 } 1999 2000 static void ucc_geth_set_multi(struct net_device *dev) 2001 { 2002 struct ucc_geth_private *ugeth; 2003 struct netdev_hw_addr *ha; 2004 struct ucc_fast __iomem *uf_regs; 2005 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2006 2007 ugeth = netdev_priv(dev); 2008 2009 uf_regs = ugeth->uccf->uf_regs; 2010 2011 if (dev->flags & IFF_PROMISC) { 2012 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2013 } else { 2014 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2015 2016 p_82xx_addr_filt = 2017 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2018 p_rx_glbl_pram->addressfiltering; 2019 2020 if (dev->flags & IFF_ALLMULTI) { 2021 /* Catch all multicast addresses, so set the 2022 * filter to all 1's. 2023 */ 2024 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2025 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2026 } else { 2027 /* Clear filter and add the addresses in the list. 2028 */ 2029 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2030 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2031 2032 netdev_for_each_mc_addr(ha, dev) { 2033 /* Ask CPM to run CRC and set bit in 2034 * filter mask. 2035 */ 2036 hw_add_addr_in_hash(ugeth, ha->addr); 2037 } 2038 } 2039 } 2040 } 2041 2042 static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2043 { 2044 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2045 struct phy_device *phydev = ugeth->phydev; 2046 2047 ugeth_vdbg("%s: IN", __func__); 2048 2049 /* 2050 * Tell the kernel the link is down. 2051 * Must be done before disabling the controller 2052 * or deadlock may happen. 2053 */ 2054 phy_stop(phydev); 2055 2056 /* Disable the controller */ 2057 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2058 2059 /* Mask all interrupts */ 2060 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2061 2062 /* Clear all interrupts */ 2063 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2064 2065 /* Disable Rx and Tx */ 2066 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2067 2068 ucc_geth_memclean(ugeth); 2069 } 2070 2071 static int ucc_struct_init(struct ucc_geth_private *ugeth) 2072 { 2073 struct ucc_geth_info *ug_info; 2074 struct ucc_fast_info *uf_info; 2075 int i; 2076 2077 ug_info = ugeth->ug_info; 2078 uf_info = &ug_info->uf_info; 2079 2080 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2081 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2082 if (netif_msg_probe(ugeth)) 2083 pr_err("Bad memory partition value\n"); 2084 return -EINVAL; 2085 } 2086 2087 /* Rx BD lengths */ 2088 for (i = 0; i < ug_info->numQueuesRx; i++) { 2089 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2090 (ug_info->bdRingLenRx[i] % 2091 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2092 if (netif_msg_probe(ugeth)) 2093 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 2094 return -EINVAL; 2095 } 2096 } 2097 2098 /* Tx BD lengths */ 2099 for (i = 0; i < ug_info->numQueuesTx; i++) { 2100 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2101 if (netif_msg_probe(ugeth)) 2102 pr_err("Tx BD ring length must be no smaller than 2\n"); 2103 return -EINVAL; 2104 } 2105 } 2106 2107 /* mrblr */ 2108 if ((uf_info->max_rx_buf_length == 0) || 2109 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2110 if (netif_msg_probe(ugeth)) 2111 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 2112 return -EINVAL; 2113 } 2114 2115 /* num Tx queues */ 2116 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2117 if (netif_msg_probe(ugeth)) 2118 pr_err("number of tx queues too large\n"); 2119 return -EINVAL; 2120 } 2121 2122 /* num Rx queues */ 2123 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2124 if (netif_msg_probe(ugeth)) 2125 pr_err("number of rx queues too large\n"); 2126 return -EINVAL; 2127 } 2128 2129 /* l2qt */ 2130 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2131 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2132 if (netif_msg_probe(ugeth)) 2133 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 2134 return -EINVAL; 2135 } 2136 } 2137 2138 /* l3qt */ 2139 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2140 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2141 if (netif_msg_probe(ugeth)) 2142 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 2143 return -EINVAL; 2144 } 2145 } 2146 2147 if (ug_info->cam && !ug_info->ecamptr) { 2148 if (netif_msg_probe(ugeth)) 2149 pr_err("If cam mode is chosen, must supply cam ptr\n"); 2150 return -EINVAL; 2151 } 2152 2153 if ((ug_info->numStationAddresses != 2154 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2155 ug_info->rxExtendedFiltering) { 2156 if (netif_msg_probe(ugeth)) 2157 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2158 return -EINVAL; 2159 } 2160 2161 /* Generate uccm_mask for receive */ 2162 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2163 for (i = 0; i < ug_info->numQueuesRx; i++) 2164 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2165 2166 for (i = 0; i < ug_info->numQueuesTx; i++) 2167 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2168 /* Initialize the general fast UCC block. */ 2169 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2170 if (netif_msg_probe(ugeth)) 2171 pr_err("Failed to init uccf\n"); 2172 return -ENOMEM; 2173 } 2174 2175 /* read the number of risc engines, update the riscTx and riscRx 2176 * if there are 4 riscs in QE 2177 */ 2178 if (qe_get_num_of_risc() == 4) { 2179 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2180 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2181 } 2182 2183 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2184 if (!ugeth->ug_regs) { 2185 if (netif_msg_probe(ugeth)) 2186 pr_err("Failed to ioremap regs\n"); 2187 return -ENOMEM; 2188 } 2189 2190 return 0; 2191 } 2192 2193 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2194 { 2195 struct ucc_geth_info *ug_info; 2196 struct ucc_fast_info *uf_info; 2197 int length; 2198 u16 i, j; 2199 u8 __iomem *bd; 2200 2201 ug_info = ugeth->ug_info; 2202 uf_info = &ug_info->uf_info; 2203 2204 /* Allocate Tx bds */ 2205 for (j = 0; j < ug_info->numQueuesTx; j++) { 2206 /* Allocate in multiple of 2207 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2208 according to spec */ 2209 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2210 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2211 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2212 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2213 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2214 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2215 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2216 u32 align = 4; 2217 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2218 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2219 ugeth->tx_bd_ring_offset[j] = 2220 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2221 2222 if (ugeth->tx_bd_ring_offset[j] != 0) 2223 ugeth->p_tx_bd_ring[j] = 2224 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2225 align) & ~(align - 1)); 2226 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2227 ugeth->tx_bd_ring_offset[j] = 2228 qe_muram_alloc(length, 2229 UCC_GETH_TX_BD_RING_ALIGNMENT); 2230 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2231 ugeth->p_tx_bd_ring[j] = 2232 (u8 __iomem *) qe_muram_addr(ugeth-> 2233 tx_bd_ring_offset[j]); 2234 } 2235 if (!ugeth->p_tx_bd_ring[j]) { 2236 if (netif_msg_ifup(ugeth)) 2237 pr_err("Can not allocate memory for Tx bd rings\n"); 2238 return -ENOMEM; 2239 } 2240 /* Zero unused end of bd ring, according to spec */ 2241 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2242 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2243 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2244 } 2245 2246 /* Init Tx bds */ 2247 for (j = 0; j < ug_info->numQueuesTx; j++) { 2248 /* Setup the skbuff rings */ 2249 ugeth->tx_skbuff[j] = 2250 kmalloc_array(ugeth->ug_info->bdRingLenTx[j], 2251 sizeof(struct sk_buff *), GFP_KERNEL); 2252 2253 if (ugeth->tx_skbuff[j] == NULL) { 2254 if (netif_msg_ifup(ugeth)) 2255 pr_err("Could not allocate tx_skbuff\n"); 2256 return -ENOMEM; 2257 } 2258 2259 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2260 ugeth->tx_skbuff[j][i] = NULL; 2261 2262 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2263 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2264 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2265 /* clear bd buffer */ 2266 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2267 /* set bd status and length */ 2268 out_be32((u32 __iomem *)bd, 0); 2269 bd += sizeof(struct qe_bd); 2270 } 2271 bd -= sizeof(struct qe_bd); 2272 /* set bd status and length */ 2273 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2280 { 2281 struct ucc_geth_info *ug_info; 2282 struct ucc_fast_info *uf_info; 2283 int length; 2284 u16 i, j; 2285 u8 __iomem *bd; 2286 2287 ug_info = ugeth->ug_info; 2288 uf_info = &ug_info->uf_info; 2289 2290 /* Allocate Rx bds */ 2291 for (j = 0; j < ug_info->numQueuesRx; j++) { 2292 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2293 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2294 u32 align = 4; 2295 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2296 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2297 ugeth->rx_bd_ring_offset[j] = 2298 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2299 if (ugeth->rx_bd_ring_offset[j] != 0) 2300 ugeth->p_rx_bd_ring[j] = 2301 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2302 align) & ~(align - 1)); 2303 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2304 ugeth->rx_bd_ring_offset[j] = 2305 qe_muram_alloc(length, 2306 UCC_GETH_RX_BD_RING_ALIGNMENT); 2307 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2308 ugeth->p_rx_bd_ring[j] = 2309 (u8 __iomem *) qe_muram_addr(ugeth-> 2310 rx_bd_ring_offset[j]); 2311 } 2312 if (!ugeth->p_rx_bd_ring[j]) { 2313 if (netif_msg_ifup(ugeth)) 2314 pr_err("Can not allocate memory for Rx bd rings\n"); 2315 return -ENOMEM; 2316 } 2317 } 2318 2319 /* Init Rx bds */ 2320 for (j = 0; j < ug_info->numQueuesRx; j++) { 2321 /* Setup the skbuff rings */ 2322 ugeth->rx_skbuff[j] = 2323 kmalloc_array(ugeth->ug_info->bdRingLenRx[j], 2324 sizeof(struct sk_buff *), GFP_KERNEL); 2325 2326 if (ugeth->rx_skbuff[j] == NULL) { 2327 if (netif_msg_ifup(ugeth)) 2328 pr_err("Could not allocate rx_skbuff\n"); 2329 return -ENOMEM; 2330 } 2331 2332 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2333 ugeth->rx_skbuff[j][i] = NULL; 2334 2335 ugeth->skb_currx[j] = 0; 2336 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2337 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2338 /* set bd status and length */ 2339 out_be32((u32 __iomem *)bd, R_I); 2340 /* clear bd buffer */ 2341 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2342 bd += sizeof(struct qe_bd); 2343 } 2344 bd -= sizeof(struct qe_bd); 2345 /* set bd status and length */ 2346 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2347 } 2348 2349 return 0; 2350 } 2351 2352 static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2353 { 2354 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2355 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2356 struct ucc_fast_private *uccf; 2357 struct ucc_geth_info *ug_info; 2358 struct ucc_fast_info *uf_info; 2359 struct ucc_fast __iomem *uf_regs; 2360 struct ucc_geth __iomem *ug_regs; 2361 int ret_val = -EINVAL; 2362 u32 remoder = UCC_GETH_REMODER_INIT; 2363 u32 init_enet_pram_offset, cecr_subblock, command; 2364 u32 ifstat, i, j, size, l2qt, l3qt; 2365 u16 temoder = UCC_GETH_TEMODER_INIT; 2366 u16 test; 2367 u8 function_code = 0; 2368 u8 __iomem *endOfRing; 2369 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2370 2371 ugeth_vdbg("%s: IN", __func__); 2372 uccf = ugeth->uccf; 2373 ug_info = ugeth->ug_info; 2374 uf_info = &ug_info->uf_info; 2375 uf_regs = uccf->uf_regs; 2376 ug_regs = ugeth->ug_regs; 2377 2378 switch (ug_info->numThreadsRx) { 2379 case UCC_GETH_NUM_OF_THREADS_1: 2380 numThreadsRxNumerical = 1; 2381 break; 2382 case UCC_GETH_NUM_OF_THREADS_2: 2383 numThreadsRxNumerical = 2; 2384 break; 2385 case UCC_GETH_NUM_OF_THREADS_4: 2386 numThreadsRxNumerical = 4; 2387 break; 2388 case UCC_GETH_NUM_OF_THREADS_6: 2389 numThreadsRxNumerical = 6; 2390 break; 2391 case UCC_GETH_NUM_OF_THREADS_8: 2392 numThreadsRxNumerical = 8; 2393 break; 2394 default: 2395 if (netif_msg_ifup(ugeth)) 2396 pr_err("Bad number of Rx threads value\n"); 2397 return -EINVAL; 2398 } 2399 2400 switch (ug_info->numThreadsTx) { 2401 case UCC_GETH_NUM_OF_THREADS_1: 2402 numThreadsTxNumerical = 1; 2403 break; 2404 case UCC_GETH_NUM_OF_THREADS_2: 2405 numThreadsTxNumerical = 2; 2406 break; 2407 case UCC_GETH_NUM_OF_THREADS_4: 2408 numThreadsTxNumerical = 4; 2409 break; 2410 case UCC_GETH_NUM_OF_THREADS_6: 2411 numThreadsTxNumerical = 6; 2412 break; 2413 case UCC_GETH_NUM_OF_THREADS_8: 2414 numThreadsTxNumerical = 8; 2415 break; 2416 default: 2417 if (netif_msg_ifup(ugeth)) 2418 pr_err("Bad number of Tx threads value\n"); 2419 return -EINVAL; 2420 } 2421 2422 /* Calculate rx_extended_features */ 2423 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2424 ug_info->ipAddressAlignment || 2425 (ug_info->numStationAddresses != 2426 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2427 2428 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2429 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2430 (ug_info->vlanOperationNonTagged != 2431 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2432 2433 init_default_reg_vals(&uf_regs->upsmr, 2434 &ug_regs->maccfg1, &ug_regs->maccfg2); 2435 2436 /* Set UPSMR */ 2437 /* For more details see the hardware spec. */ 2438 init_rx_parameters(ug_info->bro, 2439 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2440 2441 /* We're going to ignore other registers for now, */ 2442 /* except as needed to get up and running */ 2443 2444 /* Set MACCFG1 */ 2445 /* For more details see the hardware spec. */ 2446 init_flow_control_params(ug_info->aufc, 2447 ug_info->receiveFlowControl, 2448 ug_info->transmitFlowControl, 2449 ug_info->pausePeriod, 2450 ug_info->extensionField, 2451 &uf_regs->upsmr, 2452 &ug_regs->uempr, &ug_regs->maccfg1); 2453 2454 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2455 2456 /* Set IPGIFG */ 2457 /* For more details see the hardware spec. */ 2458 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2459 ug_info->nonBackToBackIfgPart2, 2460 ug_info-> 2461 miminumInterFrameGapEnforcement, 2462 ug_info->backToBackInterFrameGap, 2463 &ug_regs->ipgifg); 2464 if (ret_val != 0) { 2465 if (netif_msg_ifup(ugeth)) 2466 pr_err("IPGIFG initialization parameter too large\n"); 2467 return ret_val; 2468 } 2469 2470 /* Set HAFDUP */ 2471 /* For more details see the hardware spec. */ 2472 ret_val = init_half_duplex_params(ug_info->altBeb, 2473 ug_info->backPressureNoBackoff, 2474 ug_info->noBackoff, 2475 ug_info->excessDefer, 2476 ug_info->altBebTruncation, 2477 ug_info->maxRetransmission, 2478 ug_info->collisionWindow, 2479 &ug_regs->hafdup); 2480 if (ret_val != 0) { 2481 if (netif_msg_ifup(ugeth)) 2482 pr_err("Half Duplex initialization parameter too large\n"); 2483 return ret_val; 2484 } 2485 2486 /* Set IFSTAT */ 2487 /* For more details see the hardware spec. */ 2488 /* Read only - resets upon read */ 2489 ifstat = in_be32(&ug_regs->ifstat); 2490 2491 /* Clear UEMPR */ 2492 /* For more details see the hardware spec. */ 2493 out_be32(&ug_regs->uempr, 0); 2494 2495 /* Set UESCR */ 2496 /* For more details see the hardware spec. */ 2497 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2498 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2499 0, &uf_regs->upsmr, &ug_regs->uescr); 2500 2501 ret_val = ucc_geth_alloc_tx(ugeth); 2502 if (ret_val != 0) 2503 return ret_val; 2504 2505 ret_val = ucc_geth_alloc_rx(ugeth); 2506 if (ret_val != 0) 2507 return ret_val; 2508 2509 /* 2510 * Global PRAM 2511 */ 2512 /* Tx global PRAM */ 2513 /* Allocate global tx parameter RAM page */ 2514 ugeth->tx_glbl_pram_offset = 2515 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2516 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2517 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2518 if (netif_msg_ifup(ugeth)) 2519 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2520 return -ENOMEM; 2521 } 2522 ugeth->p_tx_glbl_pram = 2523 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2524 tx_glbl_pram_offset); 2525 /* Zero out p_tx_glbl_pram */ 2526 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2527 2528 /* Fill global PRAM */ 2529 2530 /* TQPTR */ 2531 /* Size varies with number of Tx threads */ 2532 ugeth->thread_dat_tx_offset = 2533 qe_muram_alloc(numThreadsTxNumerical * 2534 sizeof(struct ucc_geth_thread_data_tx) + 2535 32 * (numThreadsTxNumerical == 1), 2536 UCC_GETH_THREAD_DATA_ALIGNMENT); 2537 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2538 if (netif_msg_ifup(ugeth)) 2539 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2540 return -ENOMEM; 2541 } 2542 2543 ugeth->p_thread_data_tx = 2544 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2545 thread_dat_tx_offset); 2546 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2547 2548 /* vtagtable */ 2549 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2550 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2551 ug_info->vtagtable[i]); 2552 2553 /* iphoffset */ 2554 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2555 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2556 ug_info->iphoffset[i]); 2557 2558 /* SQPTR */ 2559 /* Size varies with number of Tx queues */ 2560 ugeth->send_q_mem_reg_offset = 2561 qe_muram_alloc(ug_info->numQueuesTx * 2562 sizeof(struct ucc_geth_send_queue_qd), 2563 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2564 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2565 if (netif_msg_ifup(ugeth)) 2566 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2567 return -ENOMEM; 2568 } 2569 2570 ugeth->p_send_q_mem_reg = 2571 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2572 send_q_mem_reg_offset); 2573 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2574 2575 /* Setup the table */ 2576 /* Assume BD rings are already established */ 2577 for (i = 0; i < ug_info->numQueuesTx; i++) { 2578 endOfRing = 2579 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2580 1) * sizeof(struct qe_bd); 2581 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2582 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2583 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2584 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2585 last_bd_completed_address, 2586 (u32) virt_to_phys(endOfRing)); 2587 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2588 MEM_PART_MURAM) { 2589 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2590 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i])); 2591 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2592 last_bd_completed_address, 2593 (u32)qe_muram_dma(endOfRing)); 2594 } 2595 } 2596 2597 /* schedulerbasepointer */ 2598 2599 if (ug_info->numQueuesTx > 1) { 2600 /* scheduler exists only if more than 1 tx queue */ 2601 ugeth->scheduler_offset = 2602 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2603 UCC_GETH_SCHEDULER_ALIGNMENT); 2604 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2605 if (netif_msg_ifup(ugeth)) 2606 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2607 return -ENOMEM; 2608 } 2609 2610 ugeth->p_scheduler = 2611 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2612 scheduler_offset); 2613 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2614 ugeth->scheduler_offset); 2615 /* Zero out p_scheduler */ 2616 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2617 2618 /* Set values in scheduler */ 2619 out_be32(&ugeth->p_scheduler->mblinterval, 2620 ug_info->mblinterval); 2621 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2622 ug_info->nortsrbytetime); 2623 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2624 out_8(&ugeth->p_scheduler->strictpriorityq, 2625 ug_info->strictpriorityq); 2626 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2627 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2628 for (i = 0; i < NUM_TX_QUEUES; i++) 2629 out_8(&ugeth->p_scheduler->weightfactor[i], 2630 ug_info->weightfactor[i]); 2631 2632 /* Set pointers to cpucount registers in scheduler */ 2633 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2634 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2635 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2636 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2637 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2638 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2639 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2640 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2641 } 2642 2643 /* schedulerbasepointer */ 2644 /* TxRMON_PTR (statistics) */ 2645 if (ug_info-> 2646 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2647 ugeth->tx_fw_statistics_pram_offset = 2648 qe_muram_alloc(sizeof 2649 (struct ucc_geth_tx_firmware_statistics_pram), 2650 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2651 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2652 if (netif_msg_ifup(ugeth)) 2653 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2654 return -ENOMEM; 2655 } 2656 ugeth->p_tx_fw_statistics_pram = 2657 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2658 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2659 /* Zero out p_tx_fw_statistics_pram */ 2660 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2661 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2662 } 2663 2664 /* temoder */ 2665 /* Already has speed set */ 2666 2667 if (ug_info->numQueuesTx > 1) 2668 temoder |= TEMODER_SCHEDULER_ENABLE; 2669 if (ug_info->ipCheckSumGenerate) 2670 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2671 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2672 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2673 2674 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2675 2676 /* Function code register value to be used later */ 2677 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2678 /* Required for QE */ 2679 2680 /* function code register */ 2681 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2682 2683 /* Rx global PRAM */ 2684 /* Allocate global rx parameter RAM page */ 2685 ugeth->rx_glbl_pram_offset = 2686 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2687 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2688 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2689 if (netif_msg_ifup(ugeth)) 2690 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2691 return -ENOMEM; 2692 } 2693 ugeth->p_rx_glbl_pram = 2694 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2695 rx_glbl_pram_offset); 2696 /* Zero out p_rx_glbl_pram */ 2697 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2698 2699 /* Fill global PRAM */ 2700 2701 /* RQPTR */ 2702 /* Size varies with number of Rx threads */ 2703 ugeth->thread_dat_rx_offset = 2704 qe_muram_alloc(numThreadsRxNumerical * 2705 sizeof(struct ucc_geth_thread_data_rx), 2706 UCC_GETH_THREAD_DATA_ALIGNMENT); 2707 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2708 if (netif_msg_ifup(ugeth)) 2709 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2710 return -ENOMEM; 2711 } 2712 2713 ugeth->p_thread_data_rx = 2714 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2715 thread_dat_rx_offset); 2716 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2717 2718 /* typeorlen */ 2719 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2720 2721 /* rxrmonbaseptr (statistics) */ 2722 if (ug_info-> 2723 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2724 ugeth->rx_fw_statistics_pram_offset = 2725 qe_muram_alloc(sizeof 2726 (struct ucc_geth_rx_firmware_statistics_pram), 2727 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2728 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2729 if (netif_msg_ifup(ugeth)) 2730 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2731 return -ENOMEM; 2732 } 2733 ugeth->p_rx_fw_statistics_pram = 2734 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2735 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2736 /* Zero out p_rx_fw_statistics_pram */ 2737 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2738 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2739 } 2740 2741 /* intCoalescingPtr */ 2742 2743 /* Size varies with number of Rx queues */ 2744 ugeth->rx_irq_coalescing_tbl_offset = 2745 qe_muram_alloc(ug_info->numQueuesRx * 2746 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2747 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2748 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2749 if (netif_msg_ifup(ugeth)) 2750 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2751 return -ENOMEM; 2752 } 2753 2754 ugeth->p_rx_irq_coalescing_tbl = 2755 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2756 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2757 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2758 ugeth->rx_irq_coalescing_tbl_offset); 2759 2760 /* Fill interrupt coalescing table */ 2761 for (i = 0; i < ug_info->numQueuesRx; i++) { 2762 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2763 interruptcoalescingmaxvalue, 2764 ug_info->interruptcoalescingmaxvalue[i]); 2765 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2766 interruptcoalescingcounter, 2767 ug_info->interruptcoalescingmaxvalue[i]); 2768 } 2769 2770 /* MRBLR */ 2771 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2772 &ugeth->p_rx_glbl_pram->mrblr); 2773 /* MFLR */ 2774 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2775 /* MINFLR */ 2776 init_min_frame_len(ug_info->minFrameLength, 2777 &ugeth->p_rx_glbl_pram->minflr, 2778 &ugeth->p_rx_glbl_pram->mrblr); 2779 /* MAXD1 */ 2780 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2781 /* MAXD2 */ 2782 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2783 2784 /* l2qt */ 2785 l2qt = 0; 2786 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2787 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2788 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2789 2790 /* l3qt */ 2791 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2792 l3qt = 0; 2793 for (i = 0; i < 8; i++) 2794 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2795 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2796 } 2797 2798 /* vlantype */ 2799 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2800 2801 /* vlantci */ 2802 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2803 2804 /* ecamptr */ 2805 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2806 2807 /* RBDQPTR */ 2808 /* Size varies with number of Rx queues */ 2809 ugeth->rx_bd_qs_tbl_offset = 2810 qe_muram_alloc(ug_info->numQueuesRx * 2811 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2812 sizeof(struct ucc_geth_rx_prefetched_bds)), 2813 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2814 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2815 if (netif_msg_ifup(ugeth)) 2816 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2817 return -ENOMEM; 2818 } 2819 2820 ugeth->p_rx_bd_qs_tbl = 2821 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2822 rx_bd_qs_tbl_offset); 2823 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2824 /* Zero out p_rx_bd_qs_tbl */ 2825 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2826 0, 2827 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2828 sizeof(struct ucc_geth_rx_prefetched_bds))); 2829 2830 /* Setup the table */ 2831 /* Assume BD rings are already established */ 2832 for (i = 0; i < ug_info->numQueuesRx; i++) { 2833 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2834 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2835 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2836 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2837 MEM_PART_MURAM) { 2838 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2839 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i])); 2840 } 2841 /* rest of fields handled by QE */ 2842 } 2843 2844 /* remoder */ 2845 /* Already has speed set */ 2846 2847 if (ugeth->rx_extended_features) 2848 remoder |= REMODER_RX_EXTENDED_FEATURES; 2849 if (ug_info->rxExtendedFiltering) 2850 remoder |= REMODER_RX_EXTENDED_FILTERING; 2851 if (ug_info->dynamicMaxFrameLength) 2852 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2853 if (ug_info->dynamicMinFrameLength) 2854 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2855 remoder |= 2856 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2857 remoder |= 2858 ug_info-> 2859 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2860 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2861 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2862 if (ug_info->ipCheckSumCheck) 2863 remoder |= REMODER_IP_CHECKSUM_CHECK; 2864 if (ug_info->ipAddressAlignment) 2865 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2866 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2867 2868 /* Note that this function must be called */ 2869 /* ONLY AFTER p_tx_fw_statistics_pram */ 2870 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2871 init_firmware_statistics_gathering_mode((ug_info-> 2872 statisticsMode & 2873 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2874 (ug_info->statisticsMode & 2875 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2876 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2877 ugeth->tx_fw_statistics_pram_offset, 2878 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2879 ugeth->rx_fw_statistics_pram_offset, 2880 &ugeth->p_tx_glbl_pram->temoder, 2881 &ugeth->p_rx_glbl_pram->remoder); 2882 2883 /* function code register */ 2884 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2885 2886 /* initialize extended filtering */ 2887 if (ug_info->rxExtendedFiltering) { 2888 if (!ug_info->extendedFilteringChainPointer) { 2889 if (netif_msg_ifup(ugeth)) 2890 pr_err("Null Extended Filtering Chain Pointer\n"); 2891 return -EINVAL; 2892 } 2893 2894 /* Allocate memory for extended filtering Mode Global 2895 Parameters */ 2896 ugeth->exf_glbl_param_offset = 2897 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2898 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2899 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2900 if (netif_msg_ifup(ugeth)) 2901 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2902 return -ENOMEM; 2903 } 2904 2905 ugeth->p_exf_glbl_param = 2906 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2907 exf_glbl_param_offset); 2908 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2909 ugeth->exf_glbl_param_offset); 2910 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2911 (u32) ug_info->extendedFilteringChainPointer); 2912 2913 } else { /* initialize 82xx style address filtering */ 2914 2915 /* Init individual address recognition registers to disabled */ 2916 2917 for (j = 0; j < NUM_OF_PADDRS; j++) 2918 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2919 2920 p_82xx_addr_filt = 2921 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2922 p_rx_glbl_pram->addressfiltering; 2923 2924 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2925 ENET_ADDR_TYPE_GROUP); 2926 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2927 ENET_ADDR_TYPE_INDIVIDUAL); 2928 } 2929 2930 /* 2931 * Initialize UCC at QE level 2932 */ 2933 2934 command = QE_INIT_TX_RX; 2935 2936 /* Allocate shadow InitEnet command parameter structure. 2937 * This is needed because after the InitEnet command is executed, 2938 * the structure in DPRAM is released, because DPRAM is a premium 2939 * resource. 2940 * This shadow structure keeps a copy of what was done so that the 2941 * allocated resources can be released when the channel is freed. 2942 */ 2943 if (!(ugeth->p_init_enet_param_shadow = 2944 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2945 if (netif_msg_ifup(ugeth)) 2946 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2947 return -ENOMEM; 2948 } 2949 /* Zero out *p_init_enet_param_shadow */ 2950 memset((char *)ugeth->p_init_enet_param_shadow, 2951 0, sizeof(struct ucc_geth_init_pram)); 2952 2953 /* Fill shadow InitEnet command parameter structure */ 2954 2955 ugeth->p_init_enet_param_shadow->resinit1 = 2956 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2957 ugeth->p_init_enet_param_shadow->resinit2 = 2958 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2959 ugeth->p_init_enet_param_shadow->resinit3 = 2960 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2961 ugeth->p_init_enet_param_shadow->resinit4 = 2962 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2963 ugeth->p_init_enet_param_shadow->resinit5 = 2964 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2965 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2966 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2967 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2968 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2969 2970 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2971 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2972 if ((ug_info->largestexternallookupkeysize != 2973 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2974 (ug_info->largestexternallookupkeysize != 2975 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2976 (ug_info->largestexternallookupkeysize != 2977 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2978 if (netif_msg_ifup(ugeth)) 2979 pr_err("Invalid largest External Lookup Key Size\n"); 2980 return -EINVAL; 2981 } 2982 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2983 ug_info->largestexternallookupkeysize; 2984 size = sizeof(struct ucc_geth_thread_rx_pram); 2985 if (ug_info->rxExtendedFiltering) { 2986 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 2987 if (ug_info->largestexternallookupkeysize == 2988 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 2989 size += 2990 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 2991 if (ug_info->largestexternallookupkeysize == 2992 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 2993 size += 2994 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 2995 } 2996 2997 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 2998 p_init_enet_param_shadow->rxthread[0]), 2999 (u8) (numThreadsRxNumerical + 1) 3000 /* Rx needs one extra for terminator */ 3001 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3002 ug_info->riscRx, 1)) != 0) { 3003 if (netif_msg_ifup(ugeth)) 3004 pr_err("Can not fill p_init_enet_param_shadow\n"); 3005 return ret_val; 3006 } 3007 3008 ugeth->p_init_enet_param_shadow->txglobal = 3009 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3010 if ((ret_val = 3011 fill_init_enet_entries(ugeth, 3012 &(ugeth->p_init_enet_param_shadow-> 3013 txthread[0]), numThreadsTxNumerical, 3014 sizeof(struct ucc_geth_thread_tx_pram), 3015 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3016 ug_info->riscTx, 0)) != 0) { 3017 if (netif_msg_ifup(ugeth)) 3018 pr_err("Can not fill p_init_enet_param_shadow\n"); 3019 return ret_val; 3020 } 3021 3022 /* Load Rx bds with buffers */ 3023 for (i = 0; i < ug_info->numQueuesRx; i++) { 3024 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3025 if (netif_msg_ifup(ugeth)) 3026 pr_err("Can not fill Rx bds with buffers\n"); 3027 return ret_val; 3028 } 3029 } 3030 3031 /* Allocate InitEnet command parameter structure */ 3032 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3033 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3034 if (netif_msg_ifup(ugeth)) 3035 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 3036 return -ENOMEM; 3037 } 3038 p_init_enet_pram = 3039 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3040 3041 /* Copy shadow InitEnet command parameter structure into PRAM */ 3042 out_8(&p_init_enet_pram->resinit1, 3043 ugeth->p_init_enet_param_shadow->resinit1); 3044 out_8(&p_init_enet_pram->resinit2, 3045 ugeth->p_init_enet_param_shadow->resinit2); 3046 out_8(&p_init_enet_pram->resinit3, 3047 ugeth->p_init_enet_param_shadow->resinit3); 3048 out_8(&p_init_enet_pram->resinit4, 3049 ugeth->p_init_enet_param_shadow->resinit4); 3050 out_be16(&p_init_enet_pram->resinit5, 3051 ugeth->p_init_enet_param_shadow->resinit5); 3052 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3053 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3054 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3055 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3056 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3057 out_be32(&p_init_enet_pram->rxthread[i], 3058 ugeth->p_init_enet_param_shadow->rxthread[i]); 3059 out_be32(&p_init_enet_pram->txglobal, 3060 ugeth->p_init_enet_param_shadow->txglobal); 3061 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3062 out_be32(&p_init_enet_pram->txthread[i], 3063 ugeth->p_init_enet_param_shadow->txthread[i]); 3064 3065 /* Issue QE command */ 3066 cecr_subblock = 3067 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3068 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3069 init_enet_pram_offset); 3070 3071 /* Free InitEnet command parameter */ 3072 qe_muram_free(init_enet_pram_offset); 3073 3074 return 0; 3075 } 3076 3077 /* This is called by the kernel when a frame is ready for transmission. */ 3078 /* It is pointed to by the dev->hard_start_xmit function pointer */ 3079 static netdev_tx_t 3080 ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3081 { 3082 struct ucc_geth_private *ugeth = netdev_priv(dev); 3083 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3084 struct ucc_fast_private *uccf; 3085 #endif 3086 u8 __iomem *bd; /* BD pointer */ 3087 u32 bd_status; 3088 u8 txQ = 0; 3089 unsigned long flags; 3090 3091 ugeth_vdbg("%s: IN", __func__); 3092 3093 netdev_sent_queue(dev, skb->len); 3094 spin_lock_irqsave(&ugeth->lock, flags); 3095 3096 dev->stats.tx_bytes += skb->len; 3097 3098 /* Start from the next BD that should be filled */ 3099 bd = ugeth->txBd[txQ]; 3100 bd_status = in_be32((u32 __iomem *)bd); 3101 /* Save the skb pointer so we can free it later */ 3102 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3103 3104 /* Update the current skb pointer (wrapping if this was the last) */ 3105 ugeth->skb_curtx[txQ] = 3106 (ugeth->skb_curtx[txQ] + 3107 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3108 3109 /* set up the buffer descriptor */ 3110 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3111 dma_map_single(ugeth->dev, skb->data, 3112 skb->len, DMA_TO_DEVICE)); 3113 3114 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3115 3116 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3117 3118 /* set bd status and length */ 3119 out_be32((u32 __iomem *)bd, bd_status); 3120 3121 /* Move to next BD in the ring */ 3122 if (!(bd_status & T_W)) 3123 bd += sizeof(struct qe_bd); 3124 else 3125 bd = ugeth->p_tx_bd_ring[txQ]; 3126 3127 /* If the next BD still needs to be cleaned up, then the bds 3128 are full. We need to tell the kernel to stop sending us stuff. */ 3129 if (bd == ugeth->confBd[txQ]) { 3130 if (!netif_queue_stopped(dev)) 3131 netif_stop_queue(dev); 3132 } 3133 3134 ugeth->txBd[txQ] = bd; 3135 3136 skb_tx_timestamp(skb); 3137 3138 if (ugeth->p_scheduler) { 3139 ugeth->cpucount[txQ]++; 3140 /* Indicate to QE that there are more Tx bds ready for 3141 transmission */ 3142 /* This is done by writing a running counter of the bd 3143 count to the scheduler PRAM. */ 3144 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3145 } 3146 3147 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3148 uccf = ugeth->uccf; 3149 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3150 #endif 3151 spin_unlock_irqrestore(&ugeth->lock, flags); 3152 3153 return NETDEV_TX_OK; 3154 } 3155 3156 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3157 { 3158 struct sk_buff *skb; 3159 u8 __iomem *bd; 3160 u16 length, howmany = 0; 3161 u32 bd_status; 3162 u8 *bdBuffer; 3163 struct net_device *dev; 3164 3165 ugeth_vdbg("%s: IN", __func__); 3166 3167 dev = ugeth->ndev; 3168 3169 /* collect received buffers */ 3170 bd = ugeth->rxBd[rxQ]; 3171 3172 bd_status = in_be32((u32 __iomem *)bd); 3173 3174 /* while there are received buffers and BD is full (~R_E) */ 3175 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3176 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3177 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3178 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3179 3180 /* determine whether buffer is first, last, first and last 3181 (single buffer frame) or middle (not first and not last) */ 3182 if (!skb || 3183 (!(bd_status & (R_F | R_L))) || 3184 (bd_status & R_ERRORS_FATAL)) { 3185 if (netif_msg_rx_err(ugeth)) 3186 pr_err("%d: ERROR!!! skb - 0x%08x\n", 3187 __LINE__, (u32)skb); 3188 dev_kfree_skb(skb); 3189 3190 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3191 dev->stats.rx_dropped++; 3192 } else { 3193 dev->stats.rx_packets++; 3194 howmany++; 3195 3196 /* Prep the skb for the packet */ 3197 skb_put(skb, length); 3198 3199 /* Tell the skb what kind of packet this is */ 3200 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3201 3202 dev->stats.rx_bytes += length; 3203 /* Send the packet up the stack */ 3204 netif_receive_skb(skb); 3205 } 3206 3207 skb = get_new_skb(ugeth, bd); 3208 if (!skb) { 3209 if (netif_msg_rx_err(ugeth)) 3210 pr_warn("No Rx Data Buffer\n"); 3211 dev->stats.rx_dropped++; 3212 break; 3213 } 3214 3215 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3216 3217 /* update to point at the next skb */ 3218 ugeth->skb_currx[rxQ] = 3219 (ugeth->skb_currx[rxQ] + 3220 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3221 3222 if (bd_status & R_W) 3223 bd = ugeth->p_rx_bd_ring[rxQ]; 3224 else 3225 bd += sizeof(struct qe_bd); 3226 3227 bd_status = in_be32((u32 __iomem *)bd); 3228 } 3229 3230 ugeth->rxBd[rxQ] = bd; 3231 return howmany; 3232 } 3233 3234 static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3235 { 3236 /* Start from the next BD that should be filled */ 3237 struct ucc_geth_private *ugeth = netdev_priv(dev); 3238 unsigned int bytes_sent = 0; 3239 int howmany = 0; 3240 u8 __iomem *bd; /* BD pointer */ 3241 u32 bd_status; 3242 3243 bd = ugeth->confBd[txQ]; 3244 bd_status = in_be32((u32 __iomem *)bd); 3245 3246 /* Normal processing. */ 3247 while ((bd_status & T_R) == 0) { 3248 struct sk_buff *skb; 3249 3250 /* BD contains already transmitted buffer. */ 3251 /* Handle the transmitted buffer and release */ 3252 /* the BD to be used with the current frame */ 3253 3254 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3255 if (!skb) 3256 break; 3257 howmany++; 3258 bytes_sent += skb->len; 3259 dev->stats.tx_packets++; 3260 3261 dev_consume_skb_any(skb); 3262 3263 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3264 ugeth->skb_dirtytx[txQ] = 3265 (ugeth->skb_dirtytx[txQ] + 3266 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3267 3268 /* We freed a buffer, so now we can restart transmission */ 3269 if (netif_queue_stopped(dev)) 3270 netif_wake_queue(dev); 3271 3272 /* Advance the confirmation BD pointer */ 3273 if (!(bd_status & T_W)) 3274 bd += sizeof(struct qe_bd); 3275 else 3276 bd = ugeth->p_tx_bd_ring[txQ]; 3277 bd_status = in_be32((u32 __iomem *)bd); 3278 } 3279 ugeth->confBd[txQ] = bd; 3280 netdev_completed_queue(dev, howmany, bytes_sent); 3281 return 0; 3282 } 3283 3284 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3285 { 3286 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3287 struct ucc_geth_info *ug_info; 3288 int howmany, i; 3289 3290 ug_info = ugeth->ug_info; 3291 3292 /* Tx event processing */ 3293 spin_lock(&ugeth->lock); 3294 for (i = 0; i < ug_info->numQueuesTx; i++) 3295 ucc_geth_tx(ugeth->ndev, i); 3296 spin_unlock(&ugeth->lock); 3297 3298 howmany = 0; 3299 for (i = 0; i < ug_info->numQueuesRx; i++) 3300 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3301 3302 if (howmany < budget) { 3303 napi_complete_done(napi, howmany); 3304 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3305 } 3306 3307 return howmany; 3308 } 3309 3310 static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3311 { 3312 struct net_device *dev = info; 3313 struct ucc_geth_private *ugeth = netdev_priv(dev); 3314 struct ucc_fast_private *uccf; 3315 struct ucc_geth_info *ug_info; 3316 register u32 ucce; 3317 register u32 uccm; 3318 3319 ugeth_vdbg("%s: IN", __func__); 3320 3321 uccf = ugeth->uccf; 3322 ug_info = ugeth->ug_info; 3323 3324 /* read and clear events */ 3325 ucce = (u32) in_be32(uccf->p_ucce); 3326 uccm = (u32) in_be32(uccf->p_uccm); 3327 ucce &= uccm; 3328 out_be32(uccf->p_ucce, ucce); 3329 3330 /* check for receive events that require processing */ 3331 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3332 if (napi_schedule_prep(&ugeth->napi)) { 3333 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3334 out_be32(uccf->p_uccm, uccm); 3335 __napi_schedule(&ugeth->napi); 3336 } 3337 } 3338 3339 /* Errors and other events */ 3340 if (ucce & UCCE_OTHER) { 3341 if (ucce & UCC_GETH_UCCE_BSY) 3342 dev->stats.rx_errors++; 3343 if (ucce & UCC_GETH_UCCE_TXE) 3344 dev->stats.tx_errors++; 3345 } 3346 3347 return IRQ_HANDLED; 3348 } 3349 3350 #ifdef CONFIG_NET_POLL_CONTROLLER 3351 /* 3352 * Polling 'interrupt' - used by things like netconsole to send skbs 3353 * without having to re-enable interrupts. It's not called while 3354 * the interrupt routine is executing. 3355 */ 3356 static void ucc_netpoll(struct net_device *dev) 3357 { 3358 struct ucc_geth_private *ugeth = netdev_priv(dev); 3359 int irq = ugeth->ug_info->uf_info.irq; 3360 3361 disable_irq(irq); 3362 ucc_geth_irq_handler(irq, dev); 3363 enable_irq(irq); 3364 } 3365 #endif /* CONFIG_NET_POLL_CONTROLLER */ 3366 3367 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3368 { 3369 struct ucc_geth_private *ugeth = netdev_priv(dev); 3370 struct sockaddr *addr = p; 3371 3372 if (!is_valid_ether_addr(addr->sa_data)) 3373 return -EADDRNOTAVAIL; 3374 3375 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3376 3377 /* 3378 * If device is not running, we will set mac addr register 3379 * when opening the device. 3380 */ 3381 if (!netif_running(dev)) 3382 return 0; 3383 3384 spin_lock_irq(&ugeth->lock); 3385 init_mac_station_addr_regs(dev->dev_addr[0], 3386 dev->dev_addr[1], 3387 dev->dev_addr[2], 3388 dev->dev_addr[3], 3389 dev->dev_addr[4], 3390 dev->dev_addr[5], 3391 &ugeth->ug_regs->macstnaddr1, 3392 &ugeth->ug_regs->macstnaddr2); 3393 spin_unlock_irq(&ugeth->lock); 3394 3395 return 0; 3396 } 3397 3398 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3399 { 3400 struct net_device *dev = ugeth->ndev; 3401 int err; 3402 3403 err = ucc_struct_init(ugeth); 3404 if (err) { 3405 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3406 goto err; 3407 } 3408 3409 err = ucc_geth_startup(ugeth); 3410 if (err) { 3411 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3412 goto err; 3413 } 3414 3415 err = adjust_enet_interface(ugeth); 3416 if (err) { 3417 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3418 goto err; 3419 } 3420 3421 /* Set MACSTNADDR1, MACSTNADDR2 */ 3422 /* For more details see the hardware spec. */ 3423 init_mac_station_addr_regs(dev->dev_addr[0], 3424 dev->dev_addr[1], 3425 dev->dev_addr[2], 3426 dev->dev_addr[3], 3427 dev->dev_addr[4], 3428 dev->dev_addr[5], 3429 &ugeth->ug_regs->macstnaddr1, 3430 &ugeth->ug_regs->macstnaddr2); 3431 3432 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3433 if (err) { 3434 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n"); 3435 goto err; 3436 } 3437 3438 return 0; 3439 err: 3440 ucc_geth_stop(ugeth); 3441 return err; 3442 } 3443 3444 /* Called when something needs to use the ethernet device */ 3445 /* Returns 0 for success. */ 3446 static int ucc_geth_open(struct net_device *dev) 3447 { 3448 struct ucc_geth_private *ugeth = netdev_priv(dev); 3449 int err; 3450 3451 ugeth_vdbg("%s: IN", __func__); 3452 3453 /* Test station address */ 3454 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3455 netif_err(ugeth, ifup, dev, 3456 "Multicast address used for station address - is this what you wanted?\n"); 3457 return -EINVAL; 3458 } 3459 3460 err = init_phy(dev); 3461 if (err) { 3462 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n"); 3463 return err; 3464 } 3465 3466 err = ucc_geth_init_mac(ugeth); 3467 if (err) { 3468 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3469 goto err; 3470 } 3471 3472 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3473 0, "UCC Geth", dev); 3474 if (err) { 3475 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3476 goto err; 3477 } 3478 3479 phy_start(ugeth->phydev); 3480 napi_enable(&ugeth->napi); 3481 netdev_reset_queue(dev); 3482 netif_start_queue(dev); 3483 3484 device_set_wakeup_capable(&dev->dev, 3485 qe_alive_during_sleep() || ugeth->phydev->irq); 3486 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3487 3488 return err; 3489 3490 err: 3491 ucc_geth_stop(ugeth); 3492 return err; 3493 } 3494 3495 /* Stops the kernel queue, and halts the controller */ 3496 static int ucc_geth_close(struct net_device *dev) 3497 { 3498 struct ucc_geth_private *ugeth = netdev_priv(dev); 3499 3500 ugeth_vdbg("%s: IN", __func__); 3501 3502 napi_disable(&ugeth->napi); 3503 3504 cancel_work_sync(&ugeth->timeout_work); 3505 ucc_geth_stop(ugeth); 3506 phy_disconnect(ugeth->phydev); 3507 ugeth->phydev = NULL; 3508 3509 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3510 3511 netif_stop_queue(dev); 3512 netdev_reset_queue(dev); 3513 3514 return 0; 3515 } 3516 3517 /* Reopen device. This will reset the MAC and PHY. */ 3518 static void ucc_geth_timeout_work(struct work_struct *work) 3519 { 3520 struct ucc_geth_private *ugeth; 3521 struct net_device *dev; 3522 3523 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3524 dev = ugeth->ndev; 3525 3526 ugeth_vdbg("%s: IN", __func__); 3527 3528 dev->stats.tx_errors++; 3529 3530 ugeth_dump_regs(ugeth); 3531 3532 if (dev->flags & IFF_UP) { 3533 /* 3534 * Must reset MAC *and* PHY. This is done by reopening 3535 * the device. 3536 */ 3537 netif_tx_stop_all_queues(dev); 3538 ucc_geth_stop(ugeth); 3539 ucc_geth_init_mac(ugeth); 3540 /* Must start PHY here */ 3541 phy_start(ugeth->phydev); 3542 netif_tx_start_all_queues(dev); 3543 } 3544 3545 netif_tx_schedule_all(dev); 3546 } 3547 3548 /* 3549 * ucc_geth_timeout gets called when a packet has not been 3550 * transmitted after a set amount of time. 3551 */ 3552 static void ucc_geth_timeout(struct net_device *dev) 3553 { 3554 struct ucc_geth_private *ugeth = netdev_priv(dev); 3555 3556 schedule_work(&ugeth->timeout_work); 3557 } 3558 3559 3560 #ifdef CONFIG_PM 3561 3562 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3563 { 3564 struct net_device *ndev = platform_get_drvdata(ofdev); 3565 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3566 3567 if (!netif_running(ndev)) 3568 return 0; 3569 3570 netif_device_detach(ndev); 3571 napi_disable(&ugeth->napi); 3572 3573 /* 3574 * Disable the controller, otherwise we'll wakeup on any network 3575 * activity. 3576 */ 3577 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3578 3579 if (ugeth->wol_en & WAKE_MAGIC) { 3580 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3581 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3582 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3583 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3584 phy_stop(ugeth->phydev); 3585 } 3586 3587 return 0; 3588 } 3589 3590 static int ucc_geth_resume(struct platform_device *ofdev) 3591 { 3592 struct net_device *ndev = platform_get_drvdata(ofdev); 3593 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3594 int err; 3595 3596 if (!netif_running(ndev)) 3597 return 0; 3598 3599 if (qe_alive_during_sleep()) { 3600 if (ugeth->wol_en & WAKE_MAGIC) { 3601 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3602 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3603 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3604 } 3605 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3606 } else { 3607 /* 3608 * Full reinitialization is required if QE shuts down 3609 * during sleep. 3610 */ 3611 ucc_geth_memclean(ugeth); 3612 3613 err = ucc_geth_init_mac(ugeth); 3614 if (err) { 3615 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3616 return err; 3617 } 3618 } 3619 3620 ugeth->oldlink = 0; 3621 ugeth->oldspeed = 0; 3622 ugeth->oldduplex = -1; 3623 3624 phy_stop(ugeth->phydev); 3625 phy_start(ugeth->phydev); 3626 3627 napi_enable(&ugeth->napi); 3628 netif_device_attach(ndev); 3629 3630 return 0; 3631 } 3632 3633 #else 3634 #define ucc_geth_suspend NULL 3635 #define ucc_geth_resume NULL 3636 #endif 3637 3638 static phy_interface_t to_phy_interface(const char *phy_connection_type) 3639 { 3640 if (strcasecmp(phy_connection_type, "mii") == 0) 3641 return PHY_INTERFACE_MODE_MII; 3642 if (strcasecmp(phy_connection_type, "gmii") == 0) 3643 return PHY_INTERFACE_MODE_GMII; 3644 if (strcasecmp(phy_connection_type, "tbi") == 0) 3645 return PHY_INTERFACE_MODE_TBI; 3646 if (strcasecmp(phy_connection_type, "rmii") == 0) 3647 return PHY_INTERFACE_MODE_RMII; 3648 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3649 return PHY_INTERFACE_MODE_RGMII; 3650 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3651 return PHY_INTERFACE_MODE_RGMII_ID; 3652 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3653 return PHY_INTERFACE_MODE_RGMII_TXID; 3654 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3655 return PHY_INTERFACE_MODE_RGMII_RXID; 3656 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3657 return PHY_INTERFACE_MODE_RTBI; 3658 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3659 return PHY_INTERFACE_MODE_SGMII; 3660 3661 return PHY_INTERFACE_MODE_MII; 3662 } 3663 3664 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3665 { 3666 struct ucc_geth_private *ugeth = netdev_priv(dev); 3667 3668 if (!netif_running(dev)) 3669 return -EINVAL; 3670 3671 if (!ugeth->phydev) 3672 return -ENODEV; 3673 3674 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3675 } 3676 3677 static const struct net_device_ops ucc_geth_netdev_ops = { 3678 .ndo_open = ucc_geth_open, 3679 .ndo_stop = ucc_geth_close, 3680 .ndo_start_xmit = ucc_geth_start_xmit, 3681 .ndo_validate_addr = eth_validate_addr, 3682 .ndo_change_carrier = fixed_phy_change_carrier, 3683 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3684 .ndo_set_rx_mode = ucc_geth_set_multi, 3685 .ndo_tx_timeout = ucc_geth_timeout, 3686 .ndo_do_ioctl = ucc_geth_ioctl, 3687 #ifdef CONFIG_NET_POLL_CONTROLLER 3688 .ndo_poll_controller = ucc_netpoll, 3689 #endif 3690 }; 3691 3692 static int ucc_geth_probe(struct platform_device* ofdev) 3693 { 3694 struct device *device = &ofdev->dev; 3695 struct device_node *np = ofdev->dev.of_node; 3696 struct net_device *dev = NULL; 3697 struct ucc_geth_private *ugeth = NULL; 3698 struct ucc_geth_info *ug_info; 3699 struct resource res; 3700 int err, ucc_num, max_speed = 0; 3701 const unsigned int *prop; 3702 const char *sprop; 3703 const void *mac_addr; 3704 phy_interface_t phy_interface; 3705 static const int enet_to_speed[] = { 3706 SPEED_10, SPEED_10, SPEED_10, 3707 SPEED_100, SPEED_100, SPEED_100, 3708 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3709 }; 3710 static const phy_interface_t enet_to_phy_interface[] = { 3711 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3712 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3713 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3714 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3715 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3716 PHY_INTERFACE_MODE_SGMII, 3717 }; 3718 3719 ugeth_vdbg("%s: IN", __func__); 3720 3721 prop = of_get_property(np, "cell-index", NULL); 3722 if (!prop) { 3723 prop = of_get_property(np, "device-id", NULL); 3724 if (!prop) 3725 return -ENODEV; 3726 } 3727 3728 ucc_num = *prop - 1; 3729 if ((ucc_num < 0) || (ucc_num > 7)) 3730 return -ENODEV; 3731 3732 ug_info = &ugeth_info[ucc_num]; 3733 if (ug_info == NULL) { 3734 if (netif_msg_probe(&debug)) 3735 pr_err("[%d] Missing additional data!\n", ucc_num); 3736 return -ENODEV; 3737 } 3738 3739 ug_info->uf_info.ucc_num = ucc_num; 3740 3741 sprop = of_get_property(np, "rx-clock-name", NULL); 3742 if (sprop) { 3743 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3744 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3745 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3746 pr_err("invalid rx-clock-name property\n"); 3747 return -EINVAL; 3748 } 3749 } else { 3750 prop = of_get_property(np, "rx-clock", NULL); 3751 if (!prop) { 3752 /* If both rx-clock-name and rx-clock are missing, 3753 we want to tell people to use rx-clock-name. */ 3754 pr_err("missing rx-clock-name property\n"); 3755 return -EINVAL; 3756 } 3757 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3758 pr_err("invalid rx-clock property\n"); 3759 return -EINVAL; 3760 } 3761 ug_info->uf_info.rx_clock = *prop; 3762 } 3763 3764 sprop = of_get_property(np, "tx-clock-name", NULL); 3765 if (sprop) { 3766 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3767 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3768 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3769 pr_err("invalid tx-clock-name property\n"); 3770 return -EINVAL; 3771 } 3772 } else { 3773 prop = of_get_property(np, "tx-clock", NULL); 3774 if (!prop) { 3775 pr_err("missing tx-clock-name property\n"); 3776 return -EINVAL; 3777 } 3778 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3779 pr_err("invalid tx-clock property\n"); 3780 return -EINVAL; 3781 } 3782 ug_info->uf_info.tx_clock = *prop; 3783 } 3784 3785 err = of_address_to_resource(np, 0, &res); 3786 if (err) 3787 return -EINVAL; 3788 3789 ug_info->uf_info.regs = res.start; 3790 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3791 3792 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3793 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) { 3794 /* 3795 * In the case of a fixed PHY, the DT node associated 3796 * to the PHY is the Ethernet MAC DT node. 3797 */ 3798 err = of_phy_register_fixed_link(np); 3799 if (err) 3800 return err; 3801 ug_info->phy_node = of_node_get(np); 3802 } 3803 3804 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3805 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3806 3807 /* get the phy interface type, or default to MII */ 3808 prop = of_get_property(np, "phy-connection-type", NULL); 3809 if (!prop) { 3810 /* handle interface property present in old trees */ 3811 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3812 if (prop != NULL) { 3813 phy_interface = enet_to_phy_interface[*prop]; 3814 max_speed = enet_to_speed[*prop]; 3815 } else 3816 phy_interface = PHY_INTERFACE_MODE_MII; 3817 } else { 3818 phy_interface = to_phy_interface((const char *)prop); 3819 } 3820 3821 /* get speed, or derive from PHY interface */ 3822 if (max_speed == 0) 3823 switch (phy_interface) { 3824 case PHY_INTERFACE_MODE_GMII: 3825 case PHY_INTERFACE_MODE_RGMII: 3826 case PHY_INTERFACE_MODE_RGMII_ID: 3827 case PHY_INTERFACE_MODE_RGMII_RXID: 3828 case PHY_INTERFACE_MODE_RGMII_TXID: 3829 case PHY_INTERFACE_MODE_TBI: 3830 case PHY_INTERFACE_MODE_RTBI: 3831 case PHY_INTERFACE_MODE_SGMII: 3832 max_speed = SPEED_1000; 3833 break; 3834 default: 3835 max_speed = SPEED_100; 3836 break; 3837 } 3838 3839 if (max_speed == SPEED_1000) { 3840 unsigned int snums = qe_get_num_of_snums(); 3841 3842 /* configure muram FIFOs for gigabit operation */ 3843 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3844 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3845 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3846 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3847 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3848 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3849 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3850 3851 /* If QE's snum number is 46/76 which means we need to support 3852 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3853 * more Threads to Rx. 3854 */ 3855 if ((snums == 76) || (snums == 46)) 3856 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3857 else 3858 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3859 } 3860 3861 if (netif_msg_probe(&debug)) 3862 pr_info("UCC%1d at 0x%8llx (irq = %d)\n", 3863 ug_info->uf_info.ucc_num + 1, 3864 (u64)ug_info->uf_info.regs, 3865 ug_info->uf_info.irq); 3866 3867 /* Create an ethernet device instance */ 3868 dev = alloc_etherdev(sizeof(*ugeth)); 3869 3870 if (dev == NULL) { 3871 err = -ENOMEM; 3872 goto err_deregister_fixed_link; 3873 } 3874 3875 ugeth = netdev_priv(dev); 3876 spin_lock_init(&ugeth->lock); 3877 3878 /* Create CQs for hash tables */ 3879 INIT_LIST_HEAD(&ugeth->group_hash_q); 3880 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3881 3882 dev_set_drvdata(device, dev); 3883 3884 /* Set the dev->base_addr to the gfar reg region */ 3885 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3886 3887 SET_NETDEV_DEV(dev, device); 3888 3889 /* Fill in the dev structure */ 3890 uec_set_ethtool_ops(dev); 3891 dev->netdev_ops = &ucc_geth_netdev_ops; 3892 dev->watchdog_timeo = TX_TIMEOUT; 3893 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3894 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3895 dev->mtu = 1500; 3896 3897 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3898 ugeth->phy_interface = phy_interface; 3899 ugeth->max_speed = max_speed; 3900 3901 /* Carrier starts down, phylib will bring it up */ 3902 netif_carrier_off(dev); 3903 3904 err = register_netdev(dev); 3905 if (err) { 3906 if (netif_msg_probe(ugeth)) 3907 pr_err("%s: Cannot register net device, aborting\n", 3908 dev->name); 3909 goto err_free_netdev; 3910 } 3911 3912 mac_addr = of_get_mac_address(np); 3913 if (!IS_ERR(mac_addr)) 3914 ether_addr_copy(dev->dev_addr, mac_addr); 3915 3916 ugeth->ug_info = ug_info; 3917 ugeth->dev = device; 3918 ugeth->ndev = dev; 3919 ugeth->node = np; 3920 3921 return 0; 3922 3923 err_free_netdev: 3924 free_netdev(dev); 3925 err_deregister_fixed_link: 3926 if (of_phy_is_fixed_link(np)) 3927 of_phy_deregister_fixed_link(np); 3928 of_node_put(ug_info->tbi_node); 3929 of_node_put(ug_info->phy_node); 3930 3931 return err; 3932 } 3933 3934 static int ucc_geth_remove(struct platform_device* ofdev) 3935 { 3936 struct net_device *dev = platform_get_drvdata(ofdev); 3937 struct ucc_geth_private *ugeth = netdev_priv(dev); 3938 struct device_node *np = ofdev->dev.of_node; 3939 3940 unregister_netdev(dev); 3941 free_netdev(dev); 3942 ucc_geth_memclean(ugeth); 3943 if (of_phy_is_fixed_link(np)) 3944 of_phy_deregister_fixed_link(np); 3945 of_node_put(ugeth->ug_info->tbi_node); 3946 of_node_put(ugeth->ug_info->phy_node); 3947 3948 return 0; 3949 } 3950 3951 static const struct of_device_id ucc_geth_match[] = { 3952 { 3953 .type = "network", 3954 .compatible = "ucc_geth", 3955 }, 3956 {}, 3957 }; 3958 3959 MODULE_DEVICE_TABLE(of, ucc_geth_match); 3960 3961 static struct platform_driver ucc_geth_driver = { 3962 .driver = { 3963 .name = DRV_NAME, 3964 .of_match_table = ucc_geth_match, 3965 }, 3966 .probe = ucc_geth_probe, 3967 .remove = ucc_geth_remove, 3968 .suspend = ucc_geth_suspend, 3969 .resume = ucc_geth_resume, 3970 }; 3971 3972 static int __init ucc_geth_init(void) 3973 { 3974 int i, ret; 3975 3976 if (netif_msg_drv(&debug)) 3977 pr_info(DRV_DESC "\n"); 3978 for (i = 0; i < 8; i++) 3979 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 3980 sizeof(ugeth_primary_info)); 3981 3982 ret = platform_driver_register(&ucc_geth_driver); 3983 3984 return ret; 3985 } 3986 3987 static void __exit ucc_geth_exit(void) 3988 { 3989 platform_driver_unregister(&ucc_geth_driver); 3990 } 3991 3992 module_init(ucc_geth_init); 3993 module_exit(ucc_geth_exit); 3994 3995 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3996 MODULE_DESCRIPTION(DRV_DESC); 3997 MODULE_VERSION(DRV_VERSION); 3998 MODULE_LICENSE("GPL"); 3999