1 /* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/stddef.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mii.h> 32 #include <linux/phy.h> 33 #include <linux/workqueue.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_mdio.h> 37 #include <linux/of_net.h> 38 #include <linux/of_platform.h> 39 40 #include <asm/uaccess.h> 41 #include <asm/irq.h> 42 #include <asm/io.h> 43 #include <asm/immap_qe.h> 44 #include <asm/qe.h> 45 #include <asm/ucc.h> 46 #include <asm/ucc_fast.h> 47 #include <asm/machdep.h> 48 49 #include "ucc_geth.h" 50 51 #undef DEBUG 52 53 #define ugeth_printk(level, format, arg...) \ 54 printk(level format "\n", ## arg) 55 56 #define ugeth_dbg(format, arg...) \ 57 ugeth_printk(KERN_DEBUG , format , ## arg) 58 59 #ifdef UGETH_VERBOSE_DEBUG 60 #define ugeth_vdbg ugeth_dbg 61 #else 62 #define ugeth_vdbg(fmt, args...) do { } while (0) 63 #endif /* UGETH_VERBOSE_DEBUG */ 64 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 65 66 67 static DEFINE_SPINLOCK(ugeth_lock); 68 69 static struct { 70 u32 msg_enable; 71 } debug = { -1 }; 72 73 module_param_named(debug, debug.msg_enable, int, 0); 74 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 75 76 static struct ucc_geth_info ugeth_primary_info = { 77 .uf_info = { 78 .bd_mem_part = MEM_PART_SYSTEM, 79 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 80 .max_rx_buf_length = 1536, 81 /* adjusted at startup if max-speed 1000 */ 82 .urfs = UCC_GETH_URFS_INIT, 83 .urfet = UCC_GETH_URFET_INIT, 84 .urfset = UCC_GETH_URFSET_INIT, 85 .utfs = UCC_GETH_UTFS_INIT, 86 .utfet = UCC_GETH_UTFET_INIT, 87 .utftt = UCC_GETH_UTFTT_INIT, 88 .ufpt = 256, 89 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 90 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 91 .tenc = UCC_FAST_TX_ENCODING_NRZ, 92 .renc = UCC_FAST_RX_ENCODING_NRZ, 93 .tcrc = UCC_FAST_16_BIT_CRC, 94 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 95 }, 96 .numQueuesTx = 1, 97 .numQueuesRx = 1, 98 .extendedFilteringChainPointer = ((uint32_t) NULL), 99 .typeorlen = 3072 /*1536 */ , 100 .nonBackToBackIfgPart1 = 0x40, 101 .nonBackToBackIfgPart2 = 0x60, 102 .miminumInterFrameGapEnforcement = 0x50, 103 .backToBackInterFrameGap = 0x60, 104 .mblinterval = 128, 105 .nortsrbytetime = 5, 106 .fracsiz = 1, 107 .strictpriorityq = 0xff, 108 .altBebTruncation = 0xa, 109 .excessDefer = 1, 110 .maxRetransmission = 0xf, 111 .collisionWindow = 0x37, 112 .receiveFlowControl = 1, 113 .transmitFlowControl = 1, 114 .maxGroupAddrInHash = 4, 115 .maxIndAddrInHash = 4, 116 .prel = 7, 117 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 118 .minFrameLength = 64, 119 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 120 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 121 .vlantype = 0x8100, 122 .ecamptr = ((uint32_t) NULL), 123 .eventRegMask = UCCE_OTHER, 124 .pausePeriod = 0xf000, 125 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 126 .bdRingLenTx = { 127 TX_BD_RING_LEN, 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN, 133 TX_BD_RING_LEN, 134 TX_BD_RING_LEN}, 135 136 .bdRingLenRx = { 137 RX_BD_RING_LEN, 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN, 143 RX_BD_RING_LEN, 144 RX_BD_RING_LEN}, 145 146 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 147 .largestexternallookupkeysize = 148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 149 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 152 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 153 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 154 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 155 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 156 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 157 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 158 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 159 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 160 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 161 }; 162 163 static struct ucc_geth_info ugeth_info[8]; 164 165 #ifdef DEBUG 166 static void mem_disp(u8 *addr, int size) 167 { 168 u8 *i; 169 int size16Aling = (size >> 4) << 4; 170 int size4Aling = (size >> 2) << 2; 171 int notAlign = 0; 172 if (size % 16) 173 notAlign = 1; 174 175 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 176 printk("0x%08x: %08x %08x %08x %08x\r\n", 177 (u32) i, 178 *((u32 *) (i)), 179 *((u32 *) (i + 4)), 180 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 181 if (notAlign == 1) 182 printk("0x%08x: ", (u32) i); 183 for (; (u32) i < (u32) addr + size4Aling; i += 4) 184 printk("%08x ", *((u32 *) (i))); 185 for (; (u32) i < (u32) addr + size; i++) 186 printk("%02x", *((i))); 187 if (notAlign == 1) 188 printk("\r\n"); 189 } 190 #endif /* DEBUG */ 191 192 static struct list_head *dequeue(struct list_head *lh) 193 { 194 unsigned long flags; 195 196 spin_lock_irqsave(&ugeth_lock, flags); 197 if (!list_empty(lh)) { 198 struct list_head *node = lh->next; 199 list_del(node); 200 spin_unlock_irqrestore(&ugeth_lock, flags); 201 return node; 202 } else { 203 spin_unlock_irqrestore(&ugeth_lock, flags); 204 return NULL; 205 } 206 } 207 208 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 209 u8 __iomem *bd) 210 { 211 struct sk_buff *skb; 212 213 skb = netdev_alloc_skb(ugeth->ndev, 214 ugeth->ug_info->uf_info.max_rx_buf_length + 215 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 216 if (!skb) 217 return NULL; 218 219 /* We need the data buffer to be aligned properly. We will reserve 220 * as many bytes as needed to align the data properly 221 */ 222 skb_reserve(skb, 223 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 225 1))); 226 227 out_be32(&((struct qe_bd __iomem *)bd)->buf, 228 dma_map_single(ugeth->dev, 229 skb->data, 230 ugeth->ug_info->uf_info.max_rx_buf_length + 231 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 232 DMA_FROM_DEVICE)); 233 234 out_be32((u32 __iomem *)bd, 235 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 236 237 return skb; 238 } 239 240 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 241 { 242 u8 __iomem *bd; 243 u32 bd_status; 244 struct sk_buff *skb; 245 int i; 246 247 bd = ugeth->p_rx_bd_ring[rxQ]; 248 i = 0; 249 250 do { 251 bd_status = in_be32((u32 __iomem *)bd); 252 skb = get_new_skb(ugeth, bd); 253 254 if (!skb) /* If can not allocate data buffer, 255 abort. Cleanup will be elsewhere */ 256 return -ENOMEM; 257 258 ugeth->rx_skbuff[rxQ][i] = skb; 259 260 /* advance the BD pointer */ 261 bd += sizeof(struct qe_bd); 262 i++; 263 } while (!(bd_status & R_W)); 264 265 return 0; 266 } 267 268 static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 269 u32 *p_start, 270 u8 num_entries, 271 u32 thread_size, 272 u32 thread_alignment, 273 unsigned int risc, 274 int skip_page_for_first_entry) 275 { 276 u32 init_enet_offset; 277 u8 i; 278 int snum; 279 280 for (i = 0; i < num_entries; i++) { 281 if ((snum = qe_get_snum()) < 0) { 282 if (netif_msg_ifup(ugeth)) 283 pr_err("Can not get SNUM\n"); 284 return snum; 285 } 286 if ((i == 0) && skip_page_for_first_entry) 287 /* First entry of Rx does not have page */ 288 init_enet_offset = 0; 289 else { 290 init_enet_offset = 291 qe_muram_alloc(thread_size, thread_alignment); 292 if (IS_ERR_VALUE(init_enet_offset)) { 293 if (netif_msg_ifup(ugeth)) 294 pr_err("Can not allocate DPRAM memory\n"); 295 qe_put_snum((u8) snum); 296 return -ENOMEM; 297 } 298 } 299 *(p_start++) = 300 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 301 | risc; 302 } 303 304 return 0; 305 } 306 307 static int return_init_enet_entries(struct ucc_geth_private *ugeth, 308 u32 *p_start, 309 u8 num_entries, 310 unsigned int risc, 311 int skip_page_for_first_entry) 312 { 313 u32 init_enet_offset; 314 u8 i; 315 int snum; 316 317 for (i = 0; i < num_entries; i++) { 318 u32 val = *p_start; 319 320 /* Check that this entry was actually valid -- 321 needed in case failed in allocations */ 322 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 323 snum = 324 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 325 ENET_INIT_PARAM_SNUM_SHIFT; 326 qe_put_snum((u8) snum); 327 if (!((i == 0) && skip_page_for_first_entry)) { 328 /* First entry of Rx does not have page */ 329 init_enet_offset = 330 (val & ENET_INIT_PARAM_PTR_MASK); 331 qe_muram_free(init_enet_offset); 332 } 333 *p_start++ = 0; 334 } 335 } 336 337 return 0; 338 } 339 340 #ifdef DEBUG 341 static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 342 u32 __iomem *p_start, 343 u8 num_entries, 344 u32 thread_size, 345 unsigned int risc, 346 int skip_page_for_first_entry) 347 { 348 u32 init_enet_offset; 349 u8 i; 350 int snum; 351 352 for (i = 0; i < num_entries; i++) { 353 u32 val = in_be32(p_start); 354 355 /* Check that this entry was actually valid -- 356 needed in case failed in allocations */ 357 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 358 snum = 359 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 360 ENET_INIT_PARAM_SNUM_SHIFT; 361 qe_put_snum((u8) snum); 362 if (!((i == 0) && skip_page_for_first_entry)) { 363 /* First entry of Rx does not have page */ 364 init_enet_offset = 365 (in_be32(p_start) & 366 ENET_INIT_PARAM_PTR_MASK); 367 pr_info("Init enet entry %d:\n", i); 368 pr_info("Base address: 0x%08x\n", 369 (u32)qe_muram_addr(init_enet_offset)); 370 mem_disp(qe_muram_addr(init_enet_offset), 371 thread_size); 372 } 373 p_start++; 374 } 375 } 376 377 return 0; 378 } 379 #endif 380 381 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 382 { 383 kfree(enet_addr_cont); 384 } 385 386 static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 387 { 388 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 389 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 390 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 391 } 392 393 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 394 { 395 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 396 397 if (paddr_num >= NUM_OF_PADDRS) { 398 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 399 return -EINVAL; 400 } 401 402 p_82xx_addr_filt = 403 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 404 addressfiltering; 405 406 /* Writing address ff.ff.ff.ff.ff.ff disables address 407 recognition for this register */ 408 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 411 412 return 0; 413 } 414 415 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 416 u8 *p_enet_addr) 417 { 418 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 419 u32 cecr_subblock; 420 421 p_82xx_addr_filt = 422 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 423 addressfiltering; 424 425 cecr_subblock = 426 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 427 428 /* Ethernet frames are defined in Little Endian mode, 429 therefore to insert */ 430 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 431 432 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 433 434 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 435 QE_CR_PROTOCOL_ETHERNET, 0); 436 } 437 438 static inline int compare_addr(u8 **addr1, u8 **addr2) 439 { 440 return memcmp(addr1, addr2, ETH_ALEN); 441 } 442 443 #ifdef DEBUG 444 static void get_statistics(struct ucc_geth_private *ugeth, 445 struct ucc_geth_tx_firmware_statistics * 446 tx_firmware_statistics, 447 struct ucc_geth_rx_firmware_statistics * 448 rx_firmware_statistics, 449 struct ucc_geth_hardware_statistics *hardware_statistics) 450 { 451 struct ucc_fast __iomem *uf_regs; 452 struct ucc_geth __iomem *ug_regs; 453 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 454 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 455 456 ug_regs = ugeth->ug_regs; 457 uf_regs = (struct ucc_fast __iomem *) ug_regs; 458 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 459 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 460 461 /* Tx firmware only if user handed pointer and driver actually 462 gathers Tx firmware statistics */ 463 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 464 tx_firmware_statistics->sicoltx = 465 in_be32(&p_tx_fw_statistics_pram->sicoltx); 466 tx_firmware_statistics->mulcoltx = 467 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 468 tx_firmware_statistics->latecoltxfr = 469 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 470 tx_firmware_statistics->frabortduecol = 471 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 472 tx_firmware_statistics->frlostinmactxer = 473 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 474 tx_firmware_statistics->carriersenseertx = 475 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 476 tx_firmware_statistics->frtxok = 477 in_be32(&p_tx_fw_statistics_pram->frtxok); 478 tx_firmware_statistics->txfrexcessivedefer = 479 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 480 tx_firmware_statistics->txpkts256 = 481 in_be32(&p_tx_fw_statistics_pram->txpkts256); 482 tx_firmware_statistics->txpkts512 = 483 in_be32(&p_tx_fw_statistics_pram->txpkts512); 484 tx_firmware_statistics->txpkts1024 = 485 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 486 tx_firmware_statistics->txpktsjumbo = 487 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 488 } 489 490 /* Rx firmware only if user handed pointer and driver actually 491 * gathers Rx firmware statistics */ 492 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 493 int i; 494 rx_firmware_statistics->frrxfcser = 495 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 496 rx_firmware_statistics->fraligner = 497 in_be32(&p_rx_fw_statistics_pram->fraligner); 498 rx_firmware_statistics->inrangelenrxer = 499 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 500 rx_firmware_statistics->outrangelenrxer = 501 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 502 rx_firmware_statistics->frtoolong = 503 in_be32(&p_rx_fw_statistics_pram->frtoolong); 504 rx_firmware_statistics->runt = 505 in_be32(&p_rx_fw_statistics_pram->runt); 506 rx_firmware_statistics->verylongevent = 507 in_be32(&p_rx_fw_statistics_pram->verylongevent); 508 rx_firmware_statistics->symbolerror = 509 in_be32(&p_rx_fw_statistics_pram->symbolerror); 510 rx_firmware_statistics->dropbsy = 511 in_be32(&p_rx_fw_statistics_pram->dropbsy); 512 for (i = 0; i < 0x8; i++) 513 rx_firmware_statistics->res0[i] = 514 p_rx_fw_statistics_pram->res0[i]; 515 rx_firmware_statistics->mismatchdrop = 516 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 517 rx_firmware_statistics->underpkts = 518 in_be32(&p_rx_fw_statistics_pram->underpkts); 519 rx_firmware_statistics->pkts256 = 520 in_be32(&p_rx_fw_statistics_pram->pkts256); 521 rx_firmware_statistics->pkts512 = 522 in_be32(&p_rx_fw_statistics_pram->pkts512); 523 rx_firmware_statistics->pkts1024 = 524 in_be32(&p_rx_fw_statistics_pram->pkts1024); 525 rx_firmware_statistics->pktsjumbo = 526 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 527 rx_firmware_statistics->frlossinmacer = 528 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 529 rx_firmware_statistics->pausefr = 530 in_be32(&p_rx_fw_statistics_pram->pausefr); 531 for (i = 0; i < 0x4; i++) 532 rx_firmware_statistics->res1[i] = 533 p_rx_fw_statistics_pram->res1[i]; 534 rx_firmware_statistics->removevlan = 535 in_be32(&p_rx_fw_statistics_pram->removevlan); 536 rx_firmware_statistics->replacevlan = 537 in_be32(&p_rx_fw_statistics_pram->replacevlan); 538 rx_firmware_statistics->insertvlan = 539 in_be32(&p_rx_fw_statistics_pram->insertvlan); 540 } 541 542 /* Hardware only if user handed pointer and driver actually 543 gathers hardware statistics */ 544 if (hardware_statistics && 545 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 546 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 547 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 548 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 549 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 550 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 551 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 552 hardware_statistics->txok = in_be32(&ug_regs->txok); 553 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 554 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 555 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 556 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 557 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 558 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 559 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 560 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 561 } 562 } 563 564 static void dump_bds(struct ucc_geth_private *ugeth) 565 { 566 int i; 567 int length; 568 569 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 570 if (ugeth->p_tx_bd_ring[i]) { 571 length = 572 (ugeth->ug_info->bdRingLenTx[i] * 573 sizeof(struct qe_bd)); 574 pr_info("TX BDs[%d]\n", i); 575 mem_disp(ugeth->p_tx_bd_ring[i], length); 576 } 577 } 578 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 579 if (ugeth->p_rx_bd_ring[i]) { 580 length = 581 (ugeth->ug_info->bdRingLenRx[i] * 582 sizeof(struct qe_bd)); 583 pr_info("RX BDs[%d]\n", i); 584 mem_disp(ugeth->p_rx_bd_ring[i], length); 585 } 586 } 587 } 588 589 static void dump_regs(struct ucc_geth_private *ugeth) 590 { 591 int i; 592 593 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 594 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 595 596 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 597 (u32)&ugeth->ug_regs->maccfg1, 598 in_be32(&ugeth->ug_regs->maccfg1)); 599 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 600 (u32)&ugeth->ug_regs->maccfg2, 601 in_be32(&ugeth->ug_regs->maccfg2)); 602 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 603 (u32)&ugeth->ug_regs->ipgifg, 604 in_be32(&ugeth->ug_regs->ipgifg)); 605 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 606 (u32)&ugeth->ug_regs->hafdup, 607 in_be32(&ugeth->ug_regs->hafdup)); 608 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 609 (u32)&ugeth->ug_regs->ifctl, 610 in_be32(&ugeth->ug_regs->ifctl)); 611 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 612 (u32)&ugeth->ug_regs->ifstat, 613 in_be32(&ugeth->ug_regs->ifstat)); 614 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 615 (u32)&ugeth->ug_regs->macstnaddr1, 616 in_be32(&ugeth->ug_regs->macstnaddr1)); 617 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 618 (u32)&ugeth->ug_regs->macstnaddr2, 619 in_be32(&ugeth->ug_regs->macstnaddr2)); 620 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 621 (u32)&ugeth->ug_regs->uempr, 622 in_be32(&ugeth->ug_regs->uempr)); 623 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 624 (u32)&ugeth->ug_regs->utbipar, 625 in_be32(&ugeth->ug_regs->utbipar)); 626 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 627 (u32)&ugeth->ug_regs->uescr, 628 in_be16(&ugeth->ug_regs->uescr)); 629 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 630 (u32)&ugeth->ug_regs->tx64, 631 in_be32(&ugeth->ug_regs->tx64)); 632 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 633 (u32)&ugeth->ug_regs->tx127, 634 in_be32(&ugeth->ug_regs->tx127)); 635 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 636 (u32)&ugeth->ug_regs->tx255, 637 in_be32(&ugeth->ug_regs->tx255)); 638 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 639 (u32)&ugeth->ug_regs->rx64, 640 in_be32(&ugeth->ug_regs->rx64)); 641 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 642 (u32)&ugeth->ug_regs->rx127, 643 in_be32(&ugeth->ug_regs->rx127)); 644 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 645 (u32)&ugeth->ug_regs->rx255, 646 in_be32(&ugeth->ug_regs->rx255)); 647 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 648 (u32)&ugeth->ug_regs->txok, 649 in_be32(&ugeth->ug_regs->txok)); 650 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 651 (u32)&ugeth->ug_regs->txcf, 652 in_be16(&ugeth->ug_regs->txcf)); 653 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 654 (u32)&ugeth->ug_regs->tmca, 655 in_be32(&ugeth->ug_regs->tmca)); 656 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 657 (u32)&ugeth->ug_regs->tbca, 658 in_be32(&ugeth->ug_regs->tbca)); 659 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 660 (u32)&ugeth->ug_regs->rxfok, 661 in_be32(&ugeth->ug_regs->rxfok)); 662 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 663 (u32)&ugeth->ug_regs->rxbok, 664 in_be32(&ugeth->ug_regs->rxbok)); 665 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 666 (u32)&ugeth->ug_regs->rbyt, 667 in_be32(&ugeth->ug_regs->rbyt)); 668 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 669 (u32)&ugeth->ug_regs->rmca, 670 in_be32(&ugeth->ug_regs->rmca)); 671 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 672 (u32)&ugeth->ug_regs->rbca, 673 in_be32(&ugeth->ug_regs->rbca)); 674 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 675 (u32)&ugeth->ug_regs->scar, 676 in_be32(&ugeth->ug_regs->scar)); 677 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 678 (u32)&ugeth->ug_regs->scam, 679 in_be32(&ugeth->ug_regs->scam)); 680 681 if (ugeth->p_thread_data_tx) { 682 int numThreadsTxNumerical; 683 switch (ugeth->ug_info->numThreadsTx) { 684 case UCC_GETH_NUM_OF_THREADS_1: 685 numThreadsTxNumerical = 1; 686 break; 687 case UCC_GETH_NUM_OF_THREADS_2: 688 numThreadsTxNumerical = 2; 689 break; 690 case UCC_GETH_NUM_OF_THREADS_4: 691 numThreadsTxNumerical = 4; 692 break; 693 case UCC_GETH_NUM_OF_THREADS_6: 694 numThreadsTxNumerical = 6; 695 break; 696 case UCC_GETH_NUM_OF_THREADS_8: 697 numThreadsTxNumerical = 8; 698 break; 699 default: 700 numThreadsTxNumerical = 0; 701 break; 702 } 703 704 pr_info("Thread data TXs:\n"); 705 pr_info("Base address: 0x%08x\n", 706 (u32)ugeth->p_thread_data_tx); 707 for (i = 0; i < numThreadsTxNumerical; i++) { 708 pr_info("Thread data TX[%d]:\n", i); 709 pr_info("Base address: 0x%08x\n", 710 (u32)&ugeth->p_thread_data_tx[i]); 711 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 712 sizeof(struct ucc_geth_thread_data_tx)); 713 } 714 } 715 if (ugeth->p_thread_data_rx) { 716 int numThreadsRxNumerical; 717 switch (ugeth->ug_info->numThreadsRx) { 718 case UCC_GETH_NUM_OF_THREADS_1: 719 numThreadsRxNumerical = 1; 720 break; 721 case UCC_GETH_NUM_OF_THREADS_2: 722 numThreadsRxNumerical = 2; 723 break; 724 case UCC_GETH_NUM_OF_THREADS_4: 725 numThreadsRxNumerical = 4; 726 break; 727 case UCC_GETH_NUM_OF_THREADS_6: 728 numThreadsRxNumerical = 6; 729 break; 730 case UCC_GETH_NUM_OF_THREADS_8: 731 numThreadsRxNumerical = 8; 732 break; 733 default: 734 numThreadsRxNumerical = 0; 735 break; 736 } 737 738 pr_info("Thread data RX:\n"); 739 pr_info("Base address: 0x%08x\n", 740 (u32)ugeth->p_thread_data_rx); 741 for (i = 0; i < numThreadsRxNumerical; i++) { 742 pr_info("Thread data RX[%d]:\n", i); 743 pr_info("Base address: 0x%08x\n", 744 (u32)&ugeth->p_thread_data_rx[i]); 745 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 746 sizeof(struct ucc_geth_thread_data_rx)); 747 } 748 } 749 if (ugeth->p_exf_glbl_param) { 750 pr_info("EXF global param:\n"); 751 pr_info("Base address: 0x%08x\n", 752 (u32)ugeth->p_exf_glbl_param); 753 mem_disp((u8 *) ugeth->p_exf_glbl_param, 754 sizeof(*ugeth->p_exf_glbl_param)); 755 } 756 if (ugeth->p_tx_glbl_pram) { 757 pr_info("TX global param:\n"); 758 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 759 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 760 (u32)&ugeth->p_tx_glbl_pram->temoder, 761 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 762 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 763 (u32)&ugeth->p_tx_glbl_pram->sqptr, 764 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 765 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 766 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 767 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 768 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 769 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 770 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 771 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 772 (u32)&ugeth->p_tx_glbl_pram->tstate, 773 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 774 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 775 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 776 ugeth->p_tx_glbl_pram->iphoffset[0]); 777 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 778 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 779 ugeth->p_tx_glbl_pram->iphoffset[1]); 780 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 781 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 782 ugeth->p_tx_glbl_pram->iphoffset[2]); 783 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 784 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 785 ugeth->p_tx_glbl_pram->iphoffset[3]); 786 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 787 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 788 ugeth->p_tx_glbl_pram->iphoffset[4]); 789 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 790 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 791 ugeth->p_tx_glbl_pram->iphoffset[5]); 792 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 793 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 794 ugeth->p_tx_glbl_pram->iphoffset[6]); 795 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 796 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 797 ugeth->p_tx_glbl_pram->iphoffset[7]); 798 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 799 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 800 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 801 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 802 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 803 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 804 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 805 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 806 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 807 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 808 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 809 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 810 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 811 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 812 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 813 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 814 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 815 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 816 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 817 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 818 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 819 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 820 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 821 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 822 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 823 (u32)&ugeth->p_tx_glbl_pram->tqptr, 824 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 825 } 826 if (ugeth->p_rx_glbl_pram) { 827 pr_info("RX global param:\n"); 828 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 829 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 830 (u32)&ugeth->p_rx_glbl_pram->remoder, 831 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 832 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 833 (u32)&ugeth->p_rx_glbl_pram->rqptr, 834 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 835 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 836 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 837 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 838 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 839 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 840 ugeth->p_rx_glbl_pram->rxgstpack); 841 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 842 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 843 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 844 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 845 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 846 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 847 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 848 (u32)&ugeth->p_rx_glbl_pram->rstate, 849 ugeth->p_rx_glbl_pram->rstate); 850 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 851 (u32)&ugeth->p_rx_glbl_pram->mrblr, 852 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 853 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 854 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 855 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 856 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 857 (u32)&ugeth->p_rx_glbl_pram->mflr, 858 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 859 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 860 (u32)&ugeth->p_rx_glbl_pram->minflr, 861 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 862 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 863 (u32)&ugeth->p_rx_glbl_pram->maxd1, 864 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 865 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 866 (u32)&ugeth->p_rx_glbl_pram->maxd2, 867 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 868 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 869 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 870 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 871 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 872 (u32)&ugeth->p_rx_glbl_pram->l2qt, 873 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 874 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 875 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 876 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 877 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 878 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 879 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 880 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 881 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 882 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 883 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 884 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 885 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 886 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 887 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 888 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 889 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 890 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 891 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 892 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 893 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 894 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 895 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 896 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 897 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 898 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 899 (u32)&ugeth->p_rx_glbl_pram->vlantype, 900 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 901 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 902 (u32)&ugeth->p_rx_glbl_pram->vlantci, 903 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 904 for (i = 0; i < 64; i++) 905 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 906 i, 907 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 908 ugeth->p_rx_glbl_pram->addressfiltering[i]); 909 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 910 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 911 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 912 } 913 if (ugeth->p_send_q_mem_reg) { 914 pr_info("Send Q memory registers:\n"); 915 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 916 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 917 pr_info("SQQD[%d]:\n", i); 918 pr_info("Base address: 0x%08x\n", 919 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 920 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 921 sizeof(struct ucc_geth_send_queue_qd)); 922 } 923 } 924 if (ugeth->p_scheduler) { 925 pr_info("Scheduler:\n"); 926 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 927 mem_disp((u8 *) ugeth->p_scheduler, 928 sizeof(*ugeth->p_scheduler)); 929 } 930 if (ugeth->p_tx_fw_statistics_pram) { 931 pr_info("TX FW statistics pram:\n"); 932 pr_info("Base address: 0x%08x\n", 933 (u32)ugeth->p_tx_fw_statistics_pram); 934 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 935 sizeof(*ugeth->p_tx_fw_statistics_pram)); 936 } 937 if (ugeth->p_rx_fw_statistics_pram) { 938 pr_info("RX FW statistics pram:\n"); 939 pr_info("Base address: 0x%08x\n", 940 (u32)ugeth->p_rx_fw_statistics_pram); 941 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 942 sizeof(*ugeth->p_rx_fw_statistics_pram)); 943 } 944 if (ugeth->p_rx_irq_coalescing_tbl) { 945 pr_info("RX IRQ coalescing tables:\n"); 946 pr_info("Base address: 0x%08x\n", 947 (u32)ugeth->p_rx_irq_coalescing_tbl); 948 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 949 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 950 pr_info("Base address: 0x%08x\n", 951 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 952 coalescingentry[i]); 953 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 954 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 955 coalescingentry[i].interruptcoalescingmaxvalue, 956 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 957 coalescingentry[i]. 958 interruptcoalescingmaxvalue)); 959 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 960 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 961 coalescingentry[i].interruptcoalescingcounter, 962 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 963 coalescingentry[i]. 964 interruptcoalescingcounter)); 965 } 966 } 967 if (ugeth->p_rx_bd_qs_tbl) { 968 pr_info("RX BD QS tables:\n"); 969 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 970 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 971 pr_info("RX BD QS table[%d]:\n", i); 972 pr_info("Base address: 0x%08x\n", 973 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 974 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 975 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 976 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 977 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 978 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 979 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 980 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 981 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 982 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 983 externalbdbaseptr)); 984 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 985 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 986 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 987 pr_info("ucode RX Prefetched BDs:\n"); 988 pr_info("Base address: 0x%08x\n", 989 (u32)qe_muram_addr(in_be32 990 (&ugeth->p_rx_bd_qs_tbl[i]. 991 bdbaseptr))); 992 mem_disp((u8 *) 993 qe_muram_addr(in_be32 994 (&ugeth->p_rx_bd_qs_tbl[i]. 995 bdbaseptr)), 996 sizeof(struct ucc_geth_rx_prefetched_bds)); 997 } 998 } 999 if (ugeth->p_init_enet_param_shadow) { 1000 int size; 1001 pr_info("Init enet param shadow:\n"); 1002 pr_info("Base address: 0x%08x\n", 1003 (u32) ugeth->p_init_enet_param_shadow); 1004 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1005 sizeof(*ugeth->p_init_enet_param_shadow)); 1006 1007 size = sizeof(struct ucc_geth_thread_rx_pram); 1008 if (ugeth->ug_info->rxExtendedFiltering) { 1009 size += 1010 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1011 if (ugeth->ug_info->largestexternallookupkeysize == 1012 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1013 size += 1014 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1015 if (ugeth->ug_info->largestexternallookupkeysize == 1016 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1017 size += 1018 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1019 } 1020 1021 dump_init_enet_entries(ugeth, 1022 &(ugeth->p_init_enet_param_shadow-> 1023 txthread[0]), 1024 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1025 sizeof(struct ucc_geth_thread_tx_pram), 1026 ugeth->ug_info->riscTx, 0); 1027 dump_init_enet_entries(ugeth, 1028 &(ugeth->p_init_enet_param_shadow-> 1029 rxthread[0]), 1030 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1031 ugeth->ug_info->riscRx, 1); 1032 } 1033 } 1034 #endif /* DEBUG */ 1035 1036 static void init_default_reg_vals(u32 __iomem *upsmr_register, 1037 u32 __iomem *maccfg1_register, 1038 u32 __iomem *maccfg2_register) 1039 { 1040 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1041 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1042 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1043 } 1044 1045 static int init_half_duplex_params(int alt_beb, 1046 int back_pressure_no_backoff, 1047 int no_backoff, 1048 int excess_defer, 1049 u8 alt_beb_truncation, 1050 u8 max_retransmissions, 1051 u8 collision_window, 1052 u32 __iomem *hafdup_register) 1053 { 1054 u32 value = 0; 1055 1056 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1057 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1058 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1059 return -EINVAL; 1060 1061 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1062 1063 if (alt_beb) 1064 value |= HALFDUP_ALT_BEB; 1065 if (back_pressure_no_backoff) 1066 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1067 if (no_backoff) 1068 value |= HALFDUP_NO_BACKOFF; 1069 if (excess_defer) 1070 value |= HALFDUP_EXCESSIVE_DEFER; 1071 1072 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1073 1074 value |= collision_window; 1075 1076 out_be32(hafdup_register, value); 1077 return 0; 1078 } 1079 1080 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1081 u8 non_btb_ipg, 1082 u8 min_ifg, 1083 u8 btb_ipg, 1084 u32 __iomem *ipgifg_register) 1085 { 1086 u32 value = 0; 1087 1088 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1089 IPG part 2 */ 1090 if (non_btb_cs_ipg > non_btb_ipg) 1091 return -EINVAL; 1092 1093 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1094 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1095 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1096 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1097 return -EINVAL; 1098 1099 value |= 1100 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1101 IPGIFG_NBTB_CS_IPG_MASK); 1102 value |= 1103 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1104 IPGIFG_NBTB_IPG_MASK); 1105 value |= 1106 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1107 IPGIFG_MIN_IFG_MASK); 1108 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1109 1110 out_be32(ipgifg_register, value); 1111 return 0; 1112 } 1113 1114 int init_flow_control_params(u32 automatic_flow_control_mode, 1115 int rx_flow_control_enable, 1116 int tx_flow_control_enable, 1117 u16 pause_period, 1118 u16 extension_field, 1119 u32 __iomem *upsmr_register, 1120 u32 __iomem *uempr_register, 1121 u32 __iomem *maccfg1_register) 1122 { 1123 u32 value = 0; 1124 1125 /* Set UEMPR register */ 1126 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1127 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1128 out_be32(uempr_register, value); 1129 1130 /* Set UPSMR register */ 1131 setbits32(upsmr_register, automatic_flow_control_mode); 1132 1133 value = in_be32(maccfg1_register); 1134 if (rx_flow_control_enable) 1135 value |= MACCFG1_FLOW_RX; 1136 if (tx_flow_control_enable) 1137 value |= MACCFG1_FLOW_TX; 1138 out_be32(maccfg1_register, value); 1139 1140 return 0; 1141 } 1142 1143 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1144 int auto_zero_hardware_statistics, 1145 u32 __iomem *upsmr_register, 1146 u16 __iomem *uescr_register) 1147 { 1148 u16 uescr_value = 0; 1149 1150 /* Enable hardware statistics gathering if requested */ 1151 if (enable_hardware_statistics) 1152 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1153 1154 /* Clear hardware statistics counters */ 1155 uescr_value = in_be16(uescr_register); 1156 uescr_value |= UESCR_CLRCNT; 1157 /* Automatically zero hardware statistics counters on read, 1158 if requested */ 1159 if (auto_zero_hardware_statistics) 1160 uescr_value |= UESCR_AUTOZ; 1161 out_be16(uescr_register, uescr_value); 1162 1163 return 0; 1164 } 1165 1166 static int init_firmware_statistics_gathering_mode(int 1167 enable_tx_firmware_statistics, 1168 int enable_rx_firmware_statistics, 1169 u32 __iomem *tx_rmon_base_ptr, 1170 u32 tx_firmware_statistics_structure_address, 1171 u32 __iomem *rx_rmon_base_ptr, 1172 u32 rx_firmware_statistics_structure_address, 1173 u16 __iomem *temoder_register, 1174 u32 __iomem *remoder_register) 1175 { 1176 /* Note: this function does not check if */ 1177 /* the parameters it receives are NULL */ 1178 1179 if (enable_tx_firmware_statistics) { 1180 out_be32(tx_rmon_base_ptr, 1181 tx_firmware_statistics_structure_address); 1182 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1183 } 1184 1185 if (enable_rx_firmware_statistics) { 1186 out_be32(rx_rmon_base_ptr, 1187 rx_firmware_statistics_structure_address); 1188 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1189 } 1190 1191 return 0; 1192 } 1193 1194 static int init_mac_station_addr_regs(u8 address_byte_0, 1195 u8 address_byte_1, 1196 u8 address_byte_2, 1197 u8 address_byte_3, 1198 u8 address_byte_4, 1199 u8 address_byte_5, 1200 u32 __iomem *macstnaddr1_register, 1201 u32 __iomem *macstnaddr2_register) 1202 { 1203 u32 value = 0; 1204 1205 /* Example: for a station address of 0x12345678ABCD, */ 1206 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1207 1208 /* MACSTNADDR1 Register: */ 1209 1210 /* 0 7 8 15 */ 1211 /* station address byte 5 station address byte 4 */ 1212 /* 16 23 24 31 */ 1213 /* station address byte 3 station address byte 2 */ 1214 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1215 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1216 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1217 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1218 1219 out_be32(macstnaddr1_register, value); 1220 1221 /* MACSTNADDR2 Register: */ 1222 1223 /* 0 7 8 15 */ 1224 /* station address byte 1 station address byte 0 */ 1225 /* 16 23 24 31 */ 1226 /* reserved reserved */ 1227 value = 0; 1228 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1229 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1230 1231 out_be32(macstnaddr2_register, value); 1232 1233 return 0; 1234 } 1235 1236 static int init_check_frame_length_mode(int length_check, 1237 u32 __iomem *maccfg2_register) 1238 { 1239 u32 value = 0; 1240 1241 value = in_be32(maccfg2_register); 1242 1243 if (length_check) 1244 value |= MACCFG2_LC; 1245 else 1246 value &= ~MACCFG2_LC; 1247 1248 out_be32(maccfg2_register, value); 1249 return 0; 1250 } 1251 1252 static int init_preamble_length(u8 preamble_length, 1253 u32 __iomem *maccfg2_register) 1254 { 1255 if ((preamble_length < 3) || (preamble_length > 7)) 1256 return -EINVAL; 1257 1258 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1259 preamble_length << MACCFG2_PREL_SHIFT); 1260 1261 return 0; 1262 } 1263 1264 static int init_rx_parameters(int reject_broadcast, 1265 int receive_short_frames, 1266 int promiscuous, u32 __iomem *upsmr_register) 1267 { 1268 u32 value = 0; 1269 1270 value = in_be32(upsmr_register); 1271 1272 if (reject_broadcast) 1273 value |= UCC_GETH_UPSMR_BRO; 1274 else 1275 value &= ~UCC_GETH_UPSMR_BRO; 1276 1277 if (receive_short_frames) 1278 value |= UCC_GETH_UPSMR_RSH; 1279 else 1280 value &= ~UCC_GETH_UPSMR_RSH; 1281 1282 if (promiscuous) 1283 value |= UCC_GETH_UPSMR_PRO; 1284 else 1285 value &= ~UCC_GETH_UPSMR_PRO; 1286 1287 out_be32(upsmr_register, value); 1288 1289 return 0; 1290 } 1291 1292 static int init_max_rx_buff_len(u16 max_rx_buf_len, 1293 u16 __iomem *mrblr_register) 1294 { 1295 /* max_rx_buf_len value must be a multiple of 128 */ 1296 if ((max_rx_buf_len == 0) || 1297 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1298 return -EINVAL; 1299 1300 out_be16(mrblr_register, max_rx_buf_len); 1301 return 0; 1302 } 1303 1304 static int init_min_frame_len(u16 min_frame_length, 1305 u16 __iomem *minflr_register, 1306 u16 __iomem *mrblr_register) 1307 { 1308 u16 mrblr_value = 0; 1309 1310 mrblr_value = in_be16(mrblr_register); 1311 if (min_frame_length >= (mrblr_value - 4)) 1312 return -EINVAL; 1313 1314 out_be16(minflr_register, min_frame_length); 1315 return 0; 1316 } 1317 1318 static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1319 { 1320 struct ucc_geth_info *ug_info; 1321 struct ucc_geth __iomem *ug_regs; 1322 struct ucc_fast __iomem *uf_regs; 1323 int ret_val; 1324 u32 upsmr, maccfg2; 1325 u16 value; 1326 1327 ugeth_vdbg("%s: IN", __func__); 1328 1329 ug_info = ugeth->ug_info; 1330 ug_regs = ugeth->ug_regs; 1331 uf_regs = ugeth->uccf->uf_regs; 1332 1333 /* Set MACCFG2 */ 1334 maccfg2 = in_be32(&ug_regs->maccfg2); 1335 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1336 if ((ugeth->max_speed == SPEED_10) || 1337 (ugeth->max_speed == SPEED_100)) 1338 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1339 else if (ugeth->max_speed == SPEED_1000) 1340 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1341 maccfg2 |= ug_info->padAndCrc; 1342 out_be32(&ug_regs->maccfg2, maccfg2); 1343 1344 /* Set UPSMR */ 1345 upsmr = in_be32(&uf_regs->upsmr); 1346 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1347 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1348 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1349 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1350 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1351 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1352 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1353 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1354 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1355 upsmr |= UCC_GETH_UPSMR_RPM; 1356 switch (ugeth->max_speed) { 1357 case SPEED_10: 1358 upsmr |= UCC_GETH_UPSMR_R10M; 1359 /* FALLTHROUGH */ 1360 case SPEED_100: 1361 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1362 upsmr |= UCC_GETH_UPSMR_RMM; 1363 } 1364 } 1365 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1367 upsmr |= UCC_GETH_UPSMR_TBIM; 1368 } 1369 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1370 upsmr |= UCC_GETH_UPSMR_SGMM; 1371 1372 out_be32(&uf_regs->upsmr, upsmr); 1373 1374 /* Disable autonegotiation in tbi mode, because by default it 1375 comes up in autonegotiation mode. */ 1376 /* Note that this depends on proper setting in utbipar register. */ 1377 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1378 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1379 struct ucc_geth_info *ug_info = ugeth->ug_info; 1380 struct phy_device *tbiphy; 1381 1382 if (!ug_info->tbi_node) 1383 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1384 1385 tbiphy = of_phy_find_device(ug_info->tbi_node); 1386 if (!tbiphy) 1387 pr_warn("Could not get TBI device\n"); 1388 1389 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1390 value &= ~0x1000; /* Turn off autonegotiation */ 1391 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1392 } 1393 1394 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1395 1396 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1397 if (ret_val != 0) { 1398 if (netif_msg_probe(ugeth)) 1399 pr_err("Preamble length must be between 3 and 7 inclusive\n"); 1400 return ret_val; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1407 { 1408 struct ucc_fast_private *uccf; 1409 u32 cecr_subblock; 1410 u32 temp; 1411 int i = 10; 1412 1413 uccf = ugeth->uccf; 1414 1415 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1416 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1417 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1418 1419 /* Issue host command */ 1420 cecr_subblock = 1421 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1422 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1423 QE_CR_PROTOCOL_ETHERNET, 0); 1424 1425 /* Wait for command to complete */ 1426 do { 1427 msleep(10); 1428 temp = in_be32(uccf->p_ucce); 1429 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1430 1431 uccf->stopped_tx = 1; 1432 1433 return 0; 1434 } 1435 1436 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1437 { 1438 struct ucc_fast_private *uccf; 1439 u32 cecr_subblock; 1440 u8 temp; 1441 int i = 10; 1442 1443 uccf = ugeth->uccf; 1444 1445 /* Clear acknowledge bit */ 1446 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1447 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1448 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1449 1450 /* Keep issuing command and checking acknowledge bit until 1451 it is asserted, according to spec */ 1452 do { 1453 /* Issue host command */ 1454 cecr_subblock = 1455 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1456 ucc_num); 1457 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1458 QE_CR_PROTOCOL_ETHERNET, 0); 1459 msleep(10); 1460 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1461 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1462 1463 uccf->stopped_rx = 1; 1464 1465 return 0; 1466 } 1467 1468 static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1469 { 1470 struct ucc_fast_private *uccf; 1471 u32 cecr_subblock; 1472 1473 uccf = ugeth->uccf; 1474 1475 cecr_subblock = 1476 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1477 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1478 uccf->stopped_tx = 0; 1479 1480 return 0; 1481 } 1482 1483 static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1484 { 1485 struct ucc_fast_private *uccf; 1486 u32 cecr_subblock; 1487 1488 uccf = ugeth->uccf; 1489 1490 cecr_subblock = 1491 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1492 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1493 0); 1494 uccf->stopped_rx = 0; 1495 1496 return 0; 1497 } 1498 1499 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1500 { 1501 struct ucc_fast_private *uccf; 1502 int enabled_tx, enabled_rx; 1503 1504 uccf = ugeth->uccf; 1505 1506 /* check if the UCC number is in range. */ 1507 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1508 if (netif_msg_probe(ugeth)) 1509 pr_err("ucc_num out of range\n"); 1510 return -EINVAL; 1511 } 1512 1513 enabled_tx = uccf->enabled_tx; 1514 enabled_rx = uccf->enabled_rx; 1515 1516 /* Get Tx and Rx going again, in case this channel was actively 1517 disabled. */ 1518 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1519 ugeth_restart_tx(ugeth); 1520 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1521 ugeth_restart_rx(ugeth); 1522 1523 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1524 1525 return 0; 1526 1527 } 1528 1529 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1530 { 1531 struct ucc_fast_private *uccf; 1532 1533 uccf = ugeth->uccf; 1534 1535 /* check if the UCC number is in range. */ 1536 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1537 if (netif_msg_probe(ugeth)) 1538 pr_err("ucc_num out of range\n"); 1539 return -EINVAL; 1540 } 1541 1542 /* Stop any transmissions */ 1543 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1544 ugeth_graceful_stop_tx(ugeth); 1545 1546 /* Stop any receptions */ 1547 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1548 ugeth_graceful_stop_rx(ugeth); 1549 1550 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1551 1552 return 0; 1553 } 1554 1555 static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1556 { 1557 /* Prevent any further xmits, plus detach the device. */ 1558 netif_device_detach(ugeth->ndev); 1559 1560 /* Wait for any current xmits to finish. */ 1561 netif_tx_disable(ugeth->ndev); 1562 1563 /* Disable the interrupt to avoid NAPI rescheduling. */ 1564 disable_irq(ugeth->ug_info->uf_info.irq); 1565 1566 /* Stop NAPI, and possibly wait for its completion. */ 1567 napi_disable(&ugeth->napi); 1568 } 1569 1570 static void ugeth_activate(struct ucc_geth_private *ugeth) 1571 { 1572 napi_enable(&ugeth->napi); 1573 enable_irq(ugeth->ug_info->uf_info.irq); 1574 netif_device_attach(ugeth->ndev); 1575 } 1576 1577 /* Called every time the controller might need to be made 1578 * aware of new link state. The PHY code conveys this 1579 * information through variables in the ugeth structure, and this 1580 * function converts those variables into the appropriate 1581 * register values, and can bring down the device if needed. 1582 */ 1583 1584 static void adjust_link(struct net_device *dev) 1585 { 1586 struct ucc_geth_private *ugeth = netdev_priv(dev); 1587 struct ucc_geth __iomem *ug_regs; 1588 struct ucc_fast __iomem *uf_regs; 1589 struct phy_device *phydev = ugeth->phydev; 1590 int new_state = 0; 1591 1592 ug_regs = ugeth->ug_regs; 1593 uf_regs = ugeth->uccf->uf_regs; 1594 1595 if (phydev->link) { 1596 u32 tempval = in_be32(&ug_regs->maccfg2); 1597 u32 upsmr = in_be32(&uf_regs->upsmr); 1598 /* Now we make sure that we can be in full duplex mode. 1599 * If not, we operate in half-duplex mode. */ 1600 if (phydev->duplex != ugeth->oldduplex) { 1601 new_state = 1; 1602 if (!(phydev->duplex)) 1603 tempval &= ~(MACCFG2_FDX); 1604 else 1605 tempval |= MACCFG2_FDX; 1606 ugeth->oldduplex = phydev->duplex; 1607 } 1608 1609 if (phydev->speed != ugeth->oldspeed) { 1610 new_state = 1; 1611 switch (phydev->speed) { 1612 case SPEED_1000: 1613 tempval = ((tempval & 1614 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1615 MACCFG2_INTERFACE_MODE_BYTE); 1616 break; 1617 case SPEED_100: 1618 case SPEED_10: 1619 tempval = ((tempval & 1620 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1621 MACCFG2_INTERFACE_MODE_NIBBLE); 1622 /* if reduced mode, re-set UPSMR.R10M */ 1623 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1626 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1627 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1628 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1629 if (phydev->speed == SPEED_10) 1630 upsmr |= UCC_GETH_UPSMR_R10M; 1631 else 1632 upsmr &= ~UCC_GETH_UPSMR_R10M; 1633 } 1634 break; 1635 default: 1636 if (netif_msg_link(ugeth)) 1637 pr_warn( 1638 "%s: Ack! Speed (%d) is not 10/100/1000!", 1639 dev->name, phydev->speed); 1640 break; 1641 } 1642 ugeth->oldspeed = phydev->speed; 1643 } 1644 1645 if (!ugeth->oldlink) { 1646 new_state = 1; 1647 ugeth->oldlink = 1; 1648 } 1649 1650 if (new_state) { 1651 /* 1652 * To change the MAC configuration we need to disable 1653 * the controller. To do so, we have to either grab 1654 * ugeth->lock, which is a bad idea since 'graceful 1655 * stop' commands might take quite a while, or we can 1656 * quiesce driver's activity. 1657 */ 1658 ugeth_quiesce(ugeth); 1659 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1660 1661 out_be32(&ug_regs->maccfg2, tempval); 1662 out_be32(&uf_regs->upsmr, upsmr); 1663 1664 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1665 ugeth_activate(ugeth); 1666 } 1667 } else if (ugeth->oldlink) { 1668 new_state = 1; 1669 ugeth->oldlink = 0; 1670 ugeth->oldspeed = 0; 1671 ugeth->oldduplex = -1; 1672 } 1673 1674 if (new_state && netif_msg_link(ugeth)) 1675 phy_print_status(phydev); 1676 } 1677 1678 /* Initialize TBI PHY interface for communicating with the 1679 * SERDES lynx PHY on the chip. We communicate with this PHY 1680 * through the MDIO bus on each controller, treating it as a 1681 * "normal" PHY at the address found in the UTBIPA register. We assume 1682 * that the UTBIPA register is valid. Either the MDIO bus code will set 1683 * it to a value that doesn't conflict with other PHYs on the bus, or the 1684 * value doesn't matter, as there are no other PHYs on the bus. 1685 */ 1686 static void uec_configure_serdes(struct net_device *dev) 1687 { 1688 struct ucc_geth_private *ugeth = netdev_priv(dev); 1689 struct ucc_geth_info *ug_info = ugeth->ug_info; 1690 struct phy_device *tbiphy; 1691 1692 if (!ug_info->tbi_node) { 1693 dev_warn(&dev->dev, "SGMII mode requires that the device " 1694 "tree specify a tbi-handle\n"); 1695 return; 1696 } 1697 1698 tbiphy = of_phy_find_device(ug_info->tbi_node); 1699 if (!tbiphy) { 1700 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1701 return; 1702 } 1703 1704 /* 1705 * If the link is already up, we must already be ok, and don't need to 1706 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1707 * everything for us? Resetting it takes the link down and requires 1708 * several seconds for it to come back. 1709 */ 1710 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) 1711 return; 1712 1713 /* Single clk mode, mii mode off(for serdes communication) */ 1714 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1715 1716 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1717 1718 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1719 } 1720 1721 /* Configure the PHY for dev. 1722 * returns 0 if success. -1 if failure 1723 */ 1724 static int init_phy(struct net_device *dev) 1725 { 1726 struct ucc_geth_private *priv = netdev_priv(dev); 1727 struct ucc_geth_info *ug_info = priv->ug_info; 1728 struct phy_device *phydev; 1729 1730 priv->oldlink = 0; 1731 priv->oldspeed = 0; 1732 priv->oldduplex = -1; 1733 1734 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1735 priv->phy_interface); 1736 if (!phydev) 1737 phydev = of_phy_connect_fixed_link(dev, &adjust_link, 1738 priv->phy_interface); 1739 if (!phydev) { 1740 dev_err(&dev->dev, "Could not attach to PHY\n"); 1741 return -ENODEV; 1742 } 1743 1744 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1745 uec_configure_serdes(dev); 1746 1747 phydev->supported &= (SUPPORTED_MII | 1748 SUPPORTED_Autoneg | 1749 ADVERTISED_10baseT_Half | 1750 ADVERTISED_10baseT_Full | 1751 ADVERTISED_100baseT_Half | 1752 ADVERTISED_100baseT_Full); 1753 1754 if (priv->max_speed == SPEED_1000) 1755 phydev->supported |= ADVERTISED_1000baseT_Full; 1756 1757 phydev->advertising = phydev->supported; 1758 1759 priv->phydev = phydev; 1760 1761 return 0; 1762 } 1763 1764 static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1765 { 1766 #ifdef DEBUG 1767 ucc_fast_dump_regs(ugeth->uccf); 1768 dump_regs(ugeth); 1769 dump_bds(ugeth); 1770 #endif 1771 } 1772 1773 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1774 ugeth, 1775 enum enet_addr_type 1776 enet_addr_type) 1777 { 1778 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1779 struct ucc_fast_private *uccf; 1780 enum comm_dir comm_dir; 1781 struct list_head *p_lh; 1782 u16 i, num; 1783 u32 __iomem *addr_h; 1784 u32 __iomem *addr_l; 1785 u8 *p_counter; 1786 1787 uccf = ugeth->uccf; 1788 1789 p_82xx_addr_filt = 1790 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1791 ugeth->p_rx_glbl_pram->addressfiltering; 1792 1793 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1794 addr_h = &(p_82xx_addr_filt->gaddr_h); 1795 addr_l = &(p_82xx_addr_filt->gaddr_l); 1796 p_lh = &ugeth->group_hash_q; 1797 p_counter = &(ugeth->numGroupAddrInHash); 1798 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1799 addr_h = &(p_82xx_addr_filt->iaddr_h); 1800 addr_l = &(p_82xx_addr_filt->iaddr_l); 1801 p_lh = &ugeth->ind_hash_q; 1802 p_counter = &(ugeth->numIndAddrInHash); 1803 } else 1804 return -EINVAL; 1805 1806 comm_dir = 0; 1807 if (uccf->enabled_tx) 1808 comm_dir |= COMM_DIR_TX; 1809 if (uccf->enabled_rx) 1810 comm_dir |= COMM_DIR_RX; 1811 if (comm_dir) 1812 ugeth_disable(ugeth, comm_dir); 1813 1814 /* Clear the hash table. */ 1815 out_be32(addr_h, 0x00000000); 1816 out_be32(addr_l, 0x00000000); 1817 1818 if (!p_lh) 1819 return 0; 1820 1821 num = *p_counter; 1822 1823 /* Delete all remaining CQ elements */ 1824 for (i = 0; i < num; i++) 1825 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1826 1827 *p_counter = 0; 1828 1829 if (comm_dir) 1830 ugeth_enable(ugeth, comm_dir); 1831 1832 return 0; 1833 } 1834 1835 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1836 u8 paddr_num) 1837 { 1838 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1839 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1840 } 1841 1842 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1843 { 1844 struct ucc_geth_info *ug_info; 1845 struct ucc_fast_info *uf_info; 1846 u16 i, j; 1847 u8 __iomem *bd; 1848 1849 1850 ug_info = ugeth->ug_info; 1851 uf_info = &ug_info->uf_info; 1852 1853 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1854 if (ugeth->p_rx_bd_ring[i]) { 1855 /* Return existing data buffers in ring */ 1856 bd = ugeth->p_rx_bd_ring[i]; 1857 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1858 if (ugeth->rx_skbuff[i][j]) { 1859 dma_unmap_single(ugeth->dev, 1860 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1861 ugeth->ug_info-> 1862 uf_info.max_rx_buf_length + 1863 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1864 DMA_FROM_DEVICE); 1865 dev_kfree_skb_any( 1866 ugeth->rx_skbuff[i][j]); 1867 ugeth->rx_skbuff[i][j] = NULL; 1868 } 1869 bd += sizeof(struct qe_bd); 1870 } 1871 1872 kfree(ugeth->rx_skbuff[i]); 1873 1874 if (ugeth->ug_info->uf_info.bd_mem_part == 1875 MEM_PART_SYSTEM) 1876 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1877 else if (ugeth->ug_info->uf_info.bd_mem_part == 1878 MEM_PART_MURAM) 1879 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1880 ugeth->p_rx_bd_ring[i] = NULL; 1881 } 1882 } 1883 1884 } 1885 1886 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1887 { 1888 struct ucc_geth_info *ug_info; 1889 struct ucc_fast_info *uf_info; 1890 u16 i, j; 1891 u8 __iomem *bd; 1892 1893 ug_info = ugeth->ug_info; 1894 uf_info = &ug_info->uf_info; 1895 1896 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1897 bd = ugeth->p_tx_bd_ring[i]; 1898 if (!bd) 1899 continue; 1900 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1901 if (ugeth->tx_skbuff[i][j]) { 1902 dma_unmap_single(ugeth->dev, 1903 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1904 (in_be32((u32 __iomem *)bd) & 1905 BD_LENGTH_MASK), 1906 DMA_TO_DEVICE); 1907 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1908 ugeth->tx_skbuff[i][j] = NULL; 1909 } 1910 } 1911 1912 kfree(ugeth->tx_skbuff[i]); 1913 1914 if (ugeth->p_tx_bd_ring[i]) { 1915 if (ugeth->ug_info->uf_info.bd_mem_part == 1916 MEM_PART_SYSTEM) 1917 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1918 else if (ugeth->ug_info->uf_info.bd_mem_part == 1919 MEM_PART_MURAM) 1920 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1921 ugeth->p_tx_bd_ring[i] = NULL; 1922 } 1923 } 1924 1925 } 1926 1927 static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1928 { 1929 if (!ugeth) 1930 return; 1931 1932 if (ugeth->uccf) { 1933 ucc_fast_free(ugeth->uccf); 1934 ugeth->uccf = NULL; 1935 } 1936 1937 if (ugeth->p_thread_data_tx) { 1938 qe_muram_free(ugeth->thread_dat_tx_offset); 1939 ugeth->p_thread_data_tx = NULL; 1940 } 1941 if (ugeth->p_thread_data_rx) { 1942 qe_muram_free(ugeth->thread_dat_rx_offset); 1943 ugeth->p_thread_data_rx = NULL; 1944 } 1945 if (ugeth->p_exf_glbl_param) { 1946 qe_muram_free(ugeth->exf_glbl_param_offset); 1947 ugeth->p_exf_glbl_param = NULL; 1948 } 1949 if (ugeth->p_rx_glbl_pram) { 1950 qe_muram_free(ugeth->rx_glbl_pram_offset); 1951 ugeth->p_rx_glbl_pram = NULL; 1952 } 1953 if (ugeth->p_tx_glbl_pram) { 1954 qe_muram_free(ugeth->tx_glbl_pram_offset); 1955 ugeth->p_tx_glbl_pram = NULL; 1956 } 1957 if (ugeth->p_send_q_mem_reg) { 1958 qe_muram_free(ugeth->send_q_mem_reg_offset); 1959 ugeth->p_send_q_mem_reg = NULL; 1960 } 1961 if (ugeth->p_scheduler) { 1962 qe_muram_free(ugeth->scheduler_offset); 1963 ugeth->p_scheduler = NULL; 1964 } 1965 if (ugeth->p_tx_fw_statistics_pram) { 1966 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1967 ugeth->p_tx_fw_statistics_pram = NULL; 1968 } 1969 if (ugeth->p_rx_fw_statistics_pram) { 1970 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1971 ugeth->p_rx_fw_statistics_pram = NULL; 1972 } 1973 if (ugeth->p_rx_irq_coalescing_tbl) { 1974 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1975 ugeth->p_rx_irq_coalescing_tbl = NULL; 1976 } 1977 if (ugeth->p_rx_bd_qs_tbl) { 1978 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1979 ugeth->p_rx_bd_qs_tbl = NULL; 1980 } 1981 if (ugeth->p_init_enet_param_shadow) { 1982 return_init_enet_entries(ugeth, 1983 &(ugeth->p_init_enet_param_shadow-> 1984 rxthread[0]), 1985 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1986 ugeth->ug_info->riscRx, 1); 1987 return_init_enet_entries(ugeth, 1988 &(ugeth->p_init_enet_param_shadow-> 1989 txthread[0]), 1990 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1991 ugeth->ug_info->riscTx, 0); 1992 kfree(ugeth->p_init_enet_param_shadow); 1993 ugeth->p_init_enet_param_shadow = NULL; 1994 } 1995 ucc_geth_free_tx(ugeth); 1996 ucc_geth_free_rx(ugeth); 1997 while (!list_empty(&ugeth->group_hash_q)) 1998 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1999 (dequeue(&ugeth->group_hash_q))); 2000 while (!list_empty(&ugeth->ind_hash_q)) 2001 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 2002 (dequeue(&ugeth->ind_hash_q))); 2003 if (ugeth->ug_regs) { 2004 iounmap(ugeth->ug_regs); 2005 ugeth->ug_regs = NULL; 2006 } 2007 } 2008 2009 static void ucc_geth_set_multi(struct net_device *dev) 2010 { 2011 struct ucc_geth_private *ugeth; 2012 struct netdev_hw_addr *ha; 2013 struct ucc_fast __iomem *uf_regs; 2014 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2015 2016 ugeth = netdev_priv(dev); 2017 2018 uf_regs = ugeth->uccf->uf_regs; 2019 2020 if (dev->flags & IFF_PROMISC) { 2021 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2022 } else { 2023 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2024 2025 p_82xx_addr_filt = 2026 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2027 p_rx_glbl_pram->addressfiltering; 2028 2029 if (dev->flags & IFF_ALLMULTI) { 2030 /* Catch all multicast addresses, so set the 2031 * filter to all 1's. 2032 */ 2033 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2034 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2035 } else { 2036 /* Clear filter and add the addresses in the list. 2037 */ 2038 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2039 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2040 2041 netdev_for_each_mc_addr(ha, dev) { 2042 /* Ask CPM to run CRC and set bit in 2043 * filter mask. 2044 */ 2045 hw_add_addr_in_hash(ugeth, ha->addr); 2046 } 2047 } 2048 } 2049 } 2050 2051 static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2052 { 2053 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2054 struct phy_device *phydev = ugeth->phydev; 2055 2056 ugeth_vdbg("%s: IN", __func__); 2057 2058 /* 2059 * Tell the kernel the link is down. 2060 * Must be done before disabling the controller 2061 * or deadlock may happen. 2062 */ 2063 phy_stop(phydev); 2064 2065 /* Disable the controller */ 2066 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2067 2068 /* Mask all interrupts */ 2069 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2070 2071 /* Clear all interrupts */ 2072 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2073 2074 /* Disable Rx and Tx */ 2075 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2076 2077 ucc_geth_memclean(ugeth); 2078 } 2079 2080 static int ucc_struct_init(struct ucc_geth_private *ugeth) 2081 { 2082 struct ucc_geth_info *ug_info; 2083 struct ucc_fast_info *uf_info; 2084 int i; 2085 2086 ug_info = ugeth->ug_info; 2087 uf_info = &ug_info->uf_info; 2088 2089 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2090 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2091 if (netif_msg_probe(ugeth)) 2092 pr_err("Bad memory partition value\n"); 2093 return -EINVAL; 2094 } 2095 2096 /* Rx BD lengths */ 2097 for (i = 0; i < ug_info->numQueuesRx; i++) { 2098 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2099 (ug_info->bdRingLenRx[i] % 2100 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2101 if (netif_msg_probe(ugeth)) 2102 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 2103 return -EINVAL; 2104 } 2105 } 2106 2107 /* Tx BD lengths */ 2108 for (i = 0; i < ug_info->numQueuesTx; i++) { 2109 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2110 if (netif_msg_probe(ugeth)) 2111 pr_err("Tx BD ring length must be no smaller than 2\n"); 2112 return -EINVAL; 2113 } 2114 } 2115 2116 /* mrblr */ 2117 if ((uf_info->max_rx_buf_length == 0) || 2118 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2119 if (netif_msg_probe(ugeth)) 2120 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 2121 return -EINVAL; 2122 } 2123 2124 /* num Tx queues */ 2125 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2126 if (netif_msg_probe(ugeth)) 2127 pr_err("number of tx queues too large\n"); 2128 return -EINVAL; 2129 } 2130 2131 /* num Rx queues */ 2132 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2133 if (netif_msg_probe(ugeth)) 2134 pr_err("number of rx queues too large\n"); 2135 return -EINVAL; 2136 } 2137 2138 /* l2qt */ 2139 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2140 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2141 if (netif_msg_probe(ugeth)) 2142 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 2143 return -EINVAL; 2144 } 2145 } 2146 2147 /* l3qt */ 2148 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2149 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2150 if (netif_msg_probe(ugeth)) 2151 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 2152 return -EINVAL; 2153 } 2154 } 2155 2156 if (ug_info->cam && !ug_info->ecamptr) { 2157 if (netif_msg_probe(ugeth)) 2158 pr_err("If cam mode is chosen, must supply cam ptr\n"); 2159 return -EINVAL; 2160 } 2161 2162 if ((ug_info->numStationAddresses != 2163 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2164 ug_info->rxExtendedFiltering) { 2165 if (netif_msg_probe(ugeth)) 2166 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2167 return -EINVAL; 2168 } 2169 2170 /* Generate uccm_mask for receive */ 2171 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2172 for (i = 0; i < ug_info->numQueuesRx; i++) 2173 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2174 2175 for (i = 0; i < ug_info->numQueuesTx; i++) 2176 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2177 /* Initialize the general fast UCC block. */ 2178 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2179 if (netif_msg_probe(ugeth)) 2180 pr_err("Failed to init uccf\n"); 2181 return -ENOMEM; 2182 } 2183 2184 /* read the number of risc engines, update the riscTx and riscRx 2185 * if there are 4 riscs in QE 2186 */ 2187 if (qe_get_num_of_risc() == 4) { 2188 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2189 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2190 } 2191 2192 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2193 if (!ugeth->ug_regs) { 2194 if (netif_msg_probe(ugeth)) 2195 pr_err("Failed to ioremap regs\n"); 2196 return -ENOMEM; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2203 { 2204 struct ucc_geth_info *ug_info; 2205 struct ucc_fast_info *uf_info; 2206 int length; 2207 u16 i, j; 2208 u8 __iomem *bd; 2209 2210 ug_info = ugeth->ug_info; 2211 uf_info = &ug_info->uf_info; 2212 2213 /* Allocate Tx bds */ 2214 for (j = 0; j < ug_info->numQueuesTx; j++) { 2215 /* Allocate in multiple of 2216 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2217 according to spec */ 2218 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2219 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2220 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2221 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2222 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2223 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2224 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2225 u32 align = 4; 2226 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2227 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2228 ugeth->tx_bd_ring_offset[j] = 2229 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2230 2231 if (ugeth->tx_bd_ring_offset[j] != 0) 2232 ugeth->p_tx_bd_ring[j] = 2233 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2234 align) & ~(align - 1)); 2235 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2236 ugeth->tx_bd_ring_offset[j] = 2237 qe_muram_alloc(length, 2238 UCC_GETH_TX_BD_RING_ALIGNMENT); 2239 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2240 ugeth->p_tx_bd_ring[j] = 2241 (u8 __iomem *) qe_muram_addr(ugeth-> 2242 tx_bd_ring_offset[j]); 2243 } 2244 if (!ugeth->p_tx_bd_ring[j]) { 2245 if (netif_msg_ifup(ugeth)) 2246 pr_err("Can not allocate memory for Tx bd rings\n"); 2247 return -ENOMEM; 2248 } 2249 /* Zero unused end of bd ring, according to spec */ 2250 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2251 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2252 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2253 } 2254 2255 /* Init Tx bds */ 2256 for (j = 0; j < ug_info->numQueuesTx; j++) { 2257 /* Setup the skbuff rings */ 2258 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2259 ugeth->ug_info->bdRingLenTx[j], 2260 GFP_KERNEL); 2261 2262 if (ugeth->tx_skbuff[j] == NULL) { 2263 if (netif_msg_ifup(ugeth)) 2264 pr_err("Could not allocate tx_skbuff\n"); 2265 return -ENOMEM; 2266 } 2267 2268 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2269 ugeth->tx_skbuff[j][i] = NULL; 2270 2271 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2272 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2273 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2274 /* clear bd buffer */ 2275 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2276 /* set bd status and length */ 2277 out_be32((u32 __iomem *)bd, 0); 2278 bd += sizeof(struct qe_bd); 2279 } 2280 bd -= sizeof(struct qe_bd); 2281 /* set bd status and length */ 2282 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2283 } 2284 2285 return 0; 2286 } 2287 2288 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2289 { 2290 struct ucc_geth_info *ug_info; 2291 struct ucc_fast_info *uf_info; 2292 int length; 2293 u16 i, j; 2294 u8 __iomem *bd; 2295 2296 ug_info = ugeth->ug_info; 2297 uf_info = &ug_info->uf_info; 2298 2299 /* Allocate Rx bds */ 2300 for (j = 0; j < ug_info->numQueuesRx; j++) { 2301 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2302 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2303 u32 align = 4; 2304 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2305 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2306 ugeth->rx_bd_ring_offset[j] = 2307 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2308 if (ugeth->rx_bd_ring_offset[j] != 0) 2309 ugeth->p_rx_bd_ring[j] = 2310 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2311 align) & ~(align - 1)); 2312 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2313 ugeth->rx_bd_ring_offset[j] = 2314 qe_muram_alloc(length, 2315 UCC_GETH_RX_BD_RING_ALIGNMENT); 2316 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2317 ugeth->p_rx_bd_ring[j] = 2318 (u8 __iomem *) qe_muram_addr(ugeth-> 2319 rx_bd_ring_offset[j]); 2320 } 2321 if (!ugeth->p_rx_bd_ring[j]) { 2322 if (netif_msg_ifup(ugeth)) 2323 pr_err("Can not allocate memory for Rx bd rings\n"); 2324 return -ENOMEM; 2325 } 2326 } 2327 2328 /* Init Rx bds */ 2329 for (j = 0; j < ug_info->numQueuesRx; j++) { 2330 /* Setup the skbuff rings */ 2331 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) * 2332 ugeth->ug_info->bdRingLenRx[j], 2333 GFP_KERNEL); 2334 2335 if (ugeth->rx_skbuff[j] == NULL) { 2336 if (netif_msg_ifup(ugeth)) 2337 pr_err("Could not allocate rx_skbuff\n"); 2338 return -ENOMEM; 2339 } 2340 2341 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2342 ugeth->rx_skbuff[j][i] = NULL; 2343 2344 ugeth->skb_currx[j] = 0; 2345 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2346 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2347 /* set bd status and length */ 2348 out_be32((u32 __iomem *)bd, R_I); 2349 /* clear bd buffer */ 2350 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2351 bd += sizeof(struct qe_bd); 2352 } 2353 bd -= sizeof(struct qe_bd); 2354 /* set bd status and length */ 2355 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2356 } 2357 2358 return 0; 2359 } 2360 2361 static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2362 { 2363 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2364 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2365 struct ucc_fast_private *uccf; 2366 struct ucc_geth_info *ug_info; 2367 struct ucc_fast_info *uf_info; 2368 struct ucc_fast __iomem *uf_regs; 2369 struct ucc_geth __iomem *ug_regs; 2370 int ret_val = -EINVAL; 2371 u32 remoder = UCC_GETH_REMODER_INIT; 2372 u32 init_enet_pram_offset, cecr_subblock, command; 2373 u32 ifstat, i, j, size, l2qt, l3qt; 2374 u16 temoder = UCC_GETH_TEMODER_INIT; 2375 u16 test; 2376 u8 function_code = 0; 2377 u8 __iomem *endOfRing; 2378 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2379 2380 ugeth_vdbg("%s: IN", __func__); 2381 uccf = ugeth->uccf; 2382 ug_info = ugeth->ug_info; 2383 uf_info = &ug_info->uf_info; 2384 uf_regs = uccf->uf_regs; 2385 ug_regs = ugeth->ug_regs; 2386 2387 switch (ug_info->numThreadsRx) { 2388 case UCC_GETH_NUM_OF_THREADS_1: 2389 numThreadsRxNumerical = 1; 2390 break; 2391 case UCC_GETH_NUM_OF_THREADS_2: 2392 numThreadsRxNumerical = 2; 2393 break; 2394 case UCC_GETH_NUM_OF_THREADS_4: 2395 numThreadsRxNumerical = 4; 2396 break; 2397 case UCC_GETH_NUM_OF_THREADS_6: 2398 numThreadsRxNumerical = 6; 2399 break; 2400 case UCC_GETH_NUM_OF_THREADS_8: 2401 numThreadsRxNumerical = 8; 2402 break; 2403 default: 2404 if (netif_msg_ifup(ugeth)) 2405 pr_err("Bad number of Rx threads value\n"); 2406 return -EINVAL; 2407 break; 2408 } 2409 2410 switch (ug_info->numThreadsTx) { 2411 case UCC_GETH_NUM_OF_THREADS_1: 2412 numThreadsTxNumerical = 1; 2413 break; 2414 case UCC_GETH_NUM_OF_THREADS_2: 2415 numThreadsTxNumerical = 2; 2416 break; 2417 case UCC_GETH_NUM_OF_THREADS_4: 2418 numThreadsTxNumerical = 4; 2419 break; 2420 case UCC_GETH_NUM_OF_THREADS_6: 2421 numThreadsTxNumerical = 6; 2422 break; 2423 case UCC_GETH_NUM_OF_THREADS_8: 2424 numThreadsTxNumerical = 8; 2425 break; 2426 default: 2427 if (netif_msg_ifup(ugeth)) 2428 pr_err("Bad number of Tx threads value\n"); 2429 return -EINVAL; 2430 break; 2431 } 2432 2433 /* Calculate rx_extended_features */ 2434 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2435 ug_info->ipAddressAlignment || 2436 (ug_info->numStationAddresses != 2437 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2438 2439 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2440 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2441 (ug_info->vlanOperationNonTagged != 2442 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2443 2444 init_default_reg_vals(&uf_regs->upsmr, 2445 &ug_regs->maccfg1, &ug_regs->maccfg2); 2446 2447 /* Set UPSMR */ 2448 /* For more details see the hardware spec. */ 2449 init_rx_parameters(ug_info->bro, 2450 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2451 2452 /* We're going to ignore other registers for now, */ 2453 /* except as needed to get up and running */ 2454 2455 /* Set MACCFG1 */ 2456 /* For more details see the hardware spec. */ 2457 init_flow_control_params(ug_info->aufc, 2458 ug_info->receiveFlowControl, 2459 ug_info->transmitFlowControl, 2460 ug_info->pausePeriod, 2461 ug_info->extensionField, 2462 &uf_regs->upsmr, 2463 &ug_regs->uempr, &ug_regs->maccfg1); 2464 2465 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2466 2467 /* Set IPGIFG */ 2468 /* For more details see the hardware spec. */ 2469 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2470 ug_info->nonBackToBackIfgPart2, 2471 ug_info-> 2472 miminumInterFrameGapEnforcement, 2473 ug_info->backToBackInterFrameGap, 2474 &ug_regs->ipgifg); 2475 if (ret_val != 0) { 2476 if (netif_msg_ifup(ugeth)) 2477 pr_err("IPGIFG initialization parameter too large\n"); 2478 return ret_val; 2479 } 2480 2481 /* Set HAFDUP */ 2482 /* For more details see the hardware spec. */ 2483 ret_val = init_half_duplex_params(ug_info->altBeb, 2484 ug_info->backPressureNoBackoff, 2485 ug_info->noBackoff, 2486 ug_info->excessDefer, 2487 ug_info->altBebTruncation, 2488 ug_info->maxRetransmission, 2489 ug_info->collisionWindow, 2490 &ug_regs->hafdup); 2491 if (ret_val != 0) { 2492 if (netif_msg_ifup(ugeth)) 2493 pr_err("Half Duplex initialization parameter too large\n"); 2494 return ret_val; 2495 } 2496 2497 /* Set IFSTAT */ 2498 /* For more details see the hardware spec. */ 2499 /* Read only - resets upon read */ 2500 ifstat = in_be32(&ug_regs->ifstat); 2501 2502 /* Clear UEMPR */ 2503 /* For more details see the hardware spec. */ 2504 out_be32(&ug_regs->uempr, 0); 2505 2506 /* Set UESCR */ 2507 /* For more details see the hardware spec. */ 2508 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2509 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2510 0, &uf_regs->upsmr, &ug_regs->uescr); 2511 2512 ret_val = ucc_geth_alloc_tx(ugeth); 2513 if (ret_val != 0) 2514 return ret_val; 2515 2516 ret_val = ucc_geth_alloc_rx(ugeth); 2517 if (ret_val != 0) 2518 return ret_val; 2519 2520 /* 2521 * Global PRAM 2522 */ 2523 /* Tx global PRAM */ 2524 /* Allocate global tx parameter RAM page */ 2525 ugeth->tx_glbl_pram_offset = 2526 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2527 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2528 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2529 if (netif_msg_ifup(ugeth)) 2530 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2531 return -ENOMEM; 2532 } 2533 ugeth->p_tx_glbl_pram = 2534 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2535 tx_glbl_pram_offset); 2536 /* Zero out p_tx_glbl_pram */ 2537 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2538 2539 /* Fill global PRAM */ 2540 2541 /* TQPTR */ 2542 /* Size varies with number of Tx threads */ 2543 ugeth->thread_dat_tx_offset = 2544 qe_muram_alloc(numThreadsTxNumerical * 2545 sizeof(struct ucc_geth_thread_data_tx) + 2546 32 * (numThreadsTxNumerical == 1), 2547 UCC_GETH_THREAD_DATA_ALIGNMENT); 2548 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2549 if (netif_msg_ifup(ugeth)) 2550 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2551 return -ENOMEM; 2552 } 2553 2554 ugeth->p_thread_data_tx = 2555 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2556 thread_dat_tx_offset); 2557 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2558 2559 /* vtagtable */ 2560 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2561 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2562 ug_info->vtagtable[i]); 2563 2564 /* iphoffset */ 2565 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2566 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2567 ug_info->iphoffset[i]); 2568 2569 /* SQPTR */ 2570 /* Size varies with number of Tx queues */ 2571 ugeth->send_q_mem_reg_offset = 2572 qe_muram_alloc(ug_info->numQueuesTx * 2573 sizeof(struct ucc_geth_send_queue_qd), 2574 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2575 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2576 if (netif_msg_ifup(ugeth)) 2577 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2578 return -ENOMEM; 2579 } 2580 2581 ugeth->p_send_q_mem_reg = 2582 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2583 send_q_mem_reg_offset); 2584 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2585 2586 /* Setup the table */ 2587 /* Assume BD rings are already established */ 2588 for (i = 0; i < ug_info->numQueuesTx; i++) { 2589 endOfRing = 2590 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2591 1) * sizeof(struct qe_bd); 2592 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2593 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2594 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2595 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2596 last_bd_completed_address, 2597 (u32) virt_to_phys(endOfRing)); 2598 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2599 MEM_PART_MURAM) { 2600 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2601 (u32) immrbar_virt_to_phys(ugeth-> 2602 p_tx_bd_ring[i])); 2603 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2604 last_bd_completed_address, 2605 (u32) immrbar_virt_to_phys(endOfRing)); 2606 } 2607 } 2608 2609 /* schedulerbasepointer */ 2610 2611 if (ug_info->numQueuesTx > 1) { 2612 /* scheduler exists only if more than 1 tx queue */ 2613 ugeth->scheduler_offset = 2614 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2615 UCC_GETH_SCHEDULER_ALIGNMENT); 2616 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2617 if (netif_msg_ifup(ugeth)) 2618 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2619 return -ENOMEM; 2620 } 2621 2622 ugeth->p_scheduler = 2623 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2624 scheduler_offset); 2625 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2626 ugeth->scheduler_offset); 2627 /* Zero out p_scheduler */ 2628 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2629 2630 /* Set values in scheduler */ 2631 out_be32(&ugeth->p_scheduler->mblinterval, 2632 ug_info->mblinterval); 2633 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2634 ug_info->nortsrbytetime); 2635 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2636 out_8(&ugeth->p_scheduler->strictpriorityq, 2637 ug_info->strictpriorityq); 2638 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2639 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2640 for (i = 0; i < NUM_TX_QUEUES; i++) 2641 out_8(&ugeth->p_scheduler->weightfactor[i], 2642 ug_info->weightfactor[i]); 2643 2644 /* Set pointers to cpucount registers in scheduler */ 2645 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2646 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2647 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2648 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2649 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2650 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2651 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2652 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2653 } 2654 2655 /* schedulerbasepointer */ 2656 /* TxRMON_PTR (statistics) */ 2657 if (ug_info-> 2658 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2659 ugeth->tx_fw_statistics_pram_offset = 2660 qe_muram_alloc(sizeof 2661 (struct ucc_geth_tx_firmware_statistics_pram), 2662 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2663 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2664 if (netif_msg_ifup(ugeth)) 2665 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2666 return -ENOMEM; 2667 } 2668 ugeth->p_tx_fw_statistics_pram = 2669 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2670 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2671 /* Zero out p_tx_fw_statistics_pram */ 2672 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2673 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2674 } 2675 2676 /* temoder */ 2677 /* Already has speed set */ 2678 2679 if (ug_info->numQueuesTx > 1) 2680 temoder |= TEMODER_SCHEDULER_ENABLE; 2681 if (ug_info->ipCheckSumGenerate) 2682 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2683 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2684 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2685 2686 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2687 2688 /* Function code register value to be used later */ 2689 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2690 /* Required for QE */ 2691 2692 /* function code register */ 2693 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2694 2695 /* Rx global PRAM */ 2696 /* Allocate global rx parameter RAM page */ 2697 ugeth->rx_glbl_pram_offset = 2698 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2699 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2700 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2701 if (netif_msg_ifup(ugeth)) 2702 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2703 return -ENOMEM; 2704 } 2705 ugeth->p_rx_glbl_pram = 2706 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2707 rx_glbl_pram_offset); 2708 /* Zero out p_rx_glbl_pram */ 2709 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2710 2711 /* Fill global PRAM */ 2712 2713 /* RQPTR */ 2714 /* Size varies with number of Rx threads */ 2715 ugeth->thread_dat_rx_offset = 2716 qe_muram_alloc(numThreadsRxNumerical * 2717 sizeof(struct ucc_geth_thread_data_rx), 2718 UCC_GETH_THREAD_DATA_ALIGNMENT); 2719 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2720 if (netif_msg_ifup(ugeth)) 2721 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2722 return -ENOMEM; 2723 } 2724 2725 ugeth->p_thread_data_rx = 2726 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2727 thread_dat_rx_offset); 2728 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2729 2730 /* typeorlen */ 2731 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2732 2733 /* rxrmonbaseptr (statistics) */ 2734 if (ug_info-> 2735 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2736 ugeth->rx_fw_statistics_pram_offset = 2737 qe_muram_alloc(sizeof 2738 (struct ucc_geth_rx_firmware_statistics_pram), 2739 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2740 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2741 if (netif_msg_ifup(ugeth)) 2742 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2743 return -ENOMEM; 2744 } 2745 ugeth->p_rx_fw_statistics_pram = 2746 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2747 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2748 /* Zero out p_rx_fw_statistics_pram */ 2749 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2750 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2751 } 2752 2753 /* intCoalescingPtr */ 2754 2755 /* Size varies with number of Rx queues */ 2756 ugeth->rx_irq_coalescing_tbl_offset = 2757 qe_muram_alloc(ug_info->numQueuesRx * 2758 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2759 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2760 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2761 if (netif_msg_ifup(ugeth)) 2762 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2763 return -ENOMEM; 2764 } 2765 2766 ugeth->p_rx_irq_coalescing_tbl = 2767 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2768 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2769 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2770 ugeth->rx_irq_coalescing_tbl_offset); 2771 2772 /* Fill interrupt coalescing table */ 2773 for (i = 0; i < ug_info->numQueuesRx; i++) { 2774 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2775 interruptcoalescingmaxvalue, 2776 ug_info->interruptcoalescingmaxvalue[i]); 2777 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2778 interruptcoalescingcounter, 2779 ug_info->interruptcoalescingmaxvalue[i]); 2780 } 2781 2782 /* MRBLR */ 2783 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2784 &ugeth->p_rx_glbl_pram->mrblr); 2785 /* MFLR */ 2786 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2787 /* MINFLR */ 2788 init_min_frame_len(ug_info->minFrameLength, 2789 &ugeth->p_rx_glbl_pram->minflr, 2790 &ugeth->p_rx_glbl_pram->mrblr); 2791 /* MAXD1 */ 2792 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2793 /* MAXD2 */ 2794 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2795 2796 /* l2qt */ 2797 l2qt = 0; 2798 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2799 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2800 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2801 2802 /* l3qt */ 2803 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2804 l3qt = 0; 2805 for (i = 0; i < 8; i++) 2806 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2807 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2808 } 2809 2810 /* vlantype */ 2811 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2812 2813 /* vlantci */ 2814 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2815 2816 /* ecamptr */ 2817 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2818 2819 /* RBDQPTR */ 2820 /* Size varies with number of Rx queues */ 2821 ugeth->rx_bd_qs_tbl_offset = 2822 qe_muram_alloc(ug_info->numQueuesRx * 2823 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2824 sizeof(struct ucc_geth_rx_prefetched_bds)), 2825 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2826 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2827 if (netif_msg_ifup(ugeth)) 2828 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2829 return -ENOMEM; 2830 } 2831 2832 ugeth->p_rx_bd_qs_tbl = 2833 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2834 rx_bd_qs_tbl_offset); 2835 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2836 /* Zero out p_rx_bd_qs_tbl */ 2837 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2838 0, 2839 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2840 sizeof(struct ucc_geth_rx_prefetched_bds))); 2841 2842 /* Setup the table */ 2843 /* Assume BD rings are already established */ 2844 for (i = 0; i < ug_info->numQueuesRx; i++) { 2845 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2846 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2847 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2848 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2849 MEM_PART_MURAM) { 2850 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2851 (u32) immrbar_virt_to_phys(ugeth-> 2852 p_rx_bd_ring[i])); 2853 } 2854 /* rest of fields handled by QE */ 2855 } 2856 2857 /* remoder */ 2858 /* Already has speed set */ 2859 2860 if (ugeth->rx_extended_features) 2861 remoder |= REMODER_RX_EXTENDED_FEATURES; 2862 if (ug_info->rxExtendedFiltering) 2863 remoder |= REMODER_RX_EXTENDED_FILTERING; 2864 if (ug_info->dynamicMaxFrameLength) 2865 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2866 if (ug_info->dynamicMinFrameLength) 2867 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2868 remoder |= 2869 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2870 remoder |= 2871 ug_info-> 2872 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2873 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2874 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2875 if (ug_info->ipCheckSumCheck) 2876 remoder |= REMODER_IP_CHECKSUM_CHECK; 2877 if (ug_info->ipAddressAlignment) 2878 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2879 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2880 2881 /* Note that this function must be called */ 2882 /* ONLY AFTER p_tx_fw_statistics_pram */ 2883 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2884 init_firmware_statistics_gathering_mode((ug_info-> 2885 statisticsMode & 2886 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2887 (ug_info->statisticsMode & 2888 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2889 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2890 ugeth->tx_fw_statistics_pram_offset, 2891 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2892 ugeth->rx_fw_statistics_pram_offset, 2893 &ugeth->p_tx_glbl_pram->temoder, 2894 &ugeth->p_rx_glbl_pram->remoder); 2895 2896 /* function code register */ 2897 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2898 2899 /* initialize extended filtering */ 2900 if (ug_info->rxExtendedFiltering) { 2901 if (!ug_info->extendedFilteringChainPointer) { 2902 if (netif_msg_ifup(ugeth)) 2903 pr_err("Null Extended Filtering Chain Pointer\n"); 2904 return -EINVAL; 2905 } 2906 2907 /* Allocate memory for extended filtering Mode Global 2908 Parameters */ 2909 ugeth->exf_glbl_param_offset = 2910 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2911 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2912 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2913 if (netif_msg_ifup(ugeth)) 2914 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2915 return -ENOMEM; 2916 } 2917 2918 ugeth->p_exf_glbl_param = 2919 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2920 exf_glbl_param_offset); 2921 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2922 ugeth->exf_glbl_param_offset); 2923 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2924 (u32) ug_info->extendedFilteringChainPointer); 2925 2926 } else { /* initialize 82xx style address filtering */ 2927 2928 /* Init individual address recognition registers to disabled */ 2929 2930 for (j = 0; j < NUM_OF_PADDRS; j++) 2931 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2932 2933 p_82xx_addr_filt = 2934 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2935 p_rx_glbl_pram->addressfiltering; 2936 2937 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2938 ENET_ADDR_TYPE_GROUP); 2939 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2940 ENET_ADDR_TYPE_INDIVIDUAL); 2941 } 2942 2943 /* 2944 * Initialize UCC at QE level 2945 */ 2946 2947 command = QE_INIT_TX_RX; 2948 2949 /* Allocate shadow InitEnet command parameter structure. 2950 * This is needed because after the InitEnet command is executed, 2951 * the structure in DPRAM is released, because DPRAM is a premium 2952 * resource. 2953 * This shadow structure keeps a copy of what was done so that the 2954 * allocated resources can be released when the channel is freed. 2955 */ 2956 if (!(ugeth->p_init_enet_param_shadow = 2957 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2958 if (netif_msg_ifup(ugeth)) 2959 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2960 return -ENOMEM; 2961 } 2962 /* Zero out *p_init_enet_param_shadow */ 2963 memset((char *)ugeth->p_init_enet_param_shadow, 2964 0, sizeof(struct ucc_geth_init_pram)); 2965 2966 /* Fill shadow InitEnet command parameter structure */ 2967 2968 ugeth->p_init_enet_param_shadow->resinit1 = 2969 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2970 ugeth->p_init_enet_param_shadow->resinit2 = 2971 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2972 ugeth->p_init_enet_param_shadow->resinit3 = 2973 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2974 ugeth->p_init_enet_param_shadow->resinit4 = 2975 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2976 ugeth->p_init_enet_param_shadow->resinit5 = 2977 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2978 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2979 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2980 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2981 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2982 2983 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2984 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2985 if ((ug_info->largestexternallookupkeysize != 2986 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2987 (ug_info->largestexternallookupkeysize != 2988 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2989 (ug_info->largestexternallookupkeysize != 2990 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2991 if (netif_msg_ifup(ugeth)) 2992 pr_err("Invalid largest External Lookup Key Size\n"); 2993 return -EINVAL; 2994 } 2995 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2996 ug_info->largestexternallookupkeysize; 2997 size = sizeof(struct ucc_geth_thread_rx_pram); 2998 if (ug_info->rxExtendedFiltering) { 2999 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 3000 if (ug_info->largestexternallookupkeysize == 3001 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 3002 size += 3003 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 3004 if (ug_info->largestexternallookupkeysize == 3005 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 3006 size += 3007 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 3008 } 3009 3010 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 3011 p_init_enet_param_shadow->rxthread[0]), 3012 (u8) (numThreadsRxNumerical + 1) 3013 /* Rx needs one extra for terminator */ 3014 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3015 ug_info->riscRx, 1)) != 0) { 3016 if (netif_msg_ifup(ugeth)) 3017 pr_err("Can not fill p_init_enet_param_shadow\n"); 3018 return ret_val; 3019 } 3020 3021 ugeth->p_init_enet_param_shadow->txglobal = 3022 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3023 if ((ret_val = 3024 fill_init_enet_entries(ugeth, 3025 &(ugeth->p_init_enet_param_shadow-> 3026 txthread[0]), numThreadsTxNumerical, 3027 sizeof(struct ucc_geth_thread_tx_pram), 3028 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3029 ug_info->riscTx, 0)) != 0) { 3030 if (netif_msg_ifup(ugeth)) 3031 pr_err("Can not fill p_init_enet_param_shadow\n"); 3032 return ret_val; 3033 } 3034 3035 /* Load Rx bds with buffers */ 3036 for (i = 0; i < ug_info->numQueuesRx; i++) { 3037 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3038 if (netif_msg_ifup(ugeth)) 3039 pr_err("Can not fill Rx bds with buffers\n"); 3040 return ret_val; 3041 } 3042 } 3043 3044 /* Allocate InitEnet command parameter structure */ 3045 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3046 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3047 if (netif_msg_ifup(ugeth)) 3048 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 3049 return -ENOMEM; 3050 } 3051 p_init_enet_pram = 3052 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3053 3054 /* Copy shadow InitEnet command parameter structure into PRAM */ 3055 out_8(&p_init_enet_pram->resinit1, 3056 ugeth->p_init_enet_param_shadow->resinit1); 3057 out_8(&p_init_enet_pram->resinit2, 3058 ugeth->p_init_enet_param_shadow->resinit2); 3059 out_8(&p_init_enet_pram->resinit3, 3060 ugeth->p_init_enet_param_shadow->resinit3); 3061 out_8(&p_init_enet_pram->resinit4, 3062 ugeth->p_init_enet_param_shadow->resinit4); 3063 out_be16(&p_init_enet_pram->resinit5, 3064 ugeth->p_init_enet_param_shadow->resinit5); 3065 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3066 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3067 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3068 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3069 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3070 out_be32(&p_init_enet_pram->rxthread[i], 3071 ugeth->p_init_enet_param_shadow->rxthread[i]); 3072 out_be32(&p_init_enet_pram->txglobal, 3073 ugeth->p_init_enet_param_shadow->txglobal); 3074 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3075 out_be32(&p_init_enet_pram->txthread[i], 3076 ugeth->p_init_enet_param_shadow->txthread[i]); 3077 3078 /* Issue QE command */ 3079 cecr_subblock = 3080 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3081 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3082 init_enet_pram_offset); 3083 3084 /* Free InitEnet command parameter */ 3085 qe_muram_free(init_enet_pram_offset); 3086 3087 return 0; 3088 } 3089 3090 /* This is called by the kernel when a frame is ready for transmission. */ 3091 /* It is pointed to by the dev->hard_start_xmit function pointer */ 3092 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3093 { 3094 struct ucc_geth_private *ugeth = netdev_priv(dev); 3095 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3096 struct ucc_fast_private *uccf; 3097 #endif 3098 u8 __iomem *bd; /* BD pointer */ 3099 u32 bd_status; 3100 u8 txQ = 0; 3101 unsigned long flags; 3102 3103 ugeth_vdbg("%s: IN", __func__); 3104 3105 spin_lock_irqsave(&ugeth->lock, flags); 3106 3107 dev->stats.tx_bytes += skb->len; 3108 3109 /* Start from the next BD that should be filled */ 3110 bd = ugeth->txBd[txQ]; 3111 bd_status = in_be32((u32 __iomem *)bd); 3112 /* Save the skb pointer so we can free it later */ 3113 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3114 3115 /* Update the current skb pointer (wrapping if this was the last) */ 3116 ugeth->skb_curtx[txQ] = 3117 (ugeth->skb_curtx[txQ] + 3118 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3119 3120 /* set up the buffer descriptor */ 3121 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3122 dma_map_single(ugeth->dev, skb->data, 3123 skb->len, DMA_TO_DEVICE)); 3124 3125 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3126 3127 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3128 3129 /* set bd status and length */ 3130 out_be32((u32 __iomem *)bd, bd_status); 3131 3132 /* Move to next BD in the ring */ 3133 if (!(bd_status & T_W)) 3134 bd += sizeof(struct qe_bd); 3135 else 3136 bd = ugeth->p_tx_bd_ring[txQ]; 3137 3138 /* If the next BD still needs to be cleaned up, then the bds 3139 are full. We need to tell the kernel to stop sending us stuff. */ 3140 if (bd == ugeth->confBd[txQ]) { 3141 if (!netif_queue_stopped(dev)) 3142 netif_stop_queue(dev); 3143 } 3144 3145 ugeth->txBd[txQ] = bd; 3146 3147 skb_tx_timestamp(skb); 3148 3149 if (ugeth->p_scheduler) { 3150 ugeth->cpucount[txQ]++; 3151 /* Indicate to QE that there are more Tx bds ready for 3152 transmission */ 3153 /* This is done by writing a running counter of the bd 3154 count to the scheduler PRAM. */ 3155 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3156 } 3157 3158 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3159 uccf = ugeth->uccf; 3160 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3161 #endif 3162 spin_unlock_irqrestore(&ugeth->lock, flags); 3163 3164 return NETDEV_TX_OK; 3165 } 3166 3167 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3168 { 3169 struct sk_buff *skb; 3170 u8 __iomem *bd; 3171 u16 length, howmany = 0; 3172 u32 bd_status; 3173 u8 *bdBuffer; 3174 struct net_device *dev; 3175 3176 ugeth_vdbg("%s: IN", __func__); 3177 3178 dev = ugeth->ndev; 3179 3180 /* collect received buffers */ 3181 bd = ugeth->rxBd[rxQ]; 3182 3183 bd_status = in_be32((u32 __iomem *)bd); 3184 3185 /* while there are received buffers and BD is full (~R_E) */ 3186 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3187 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3188 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3189 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3190 3191 /* determine whether buffer is first, last, first and last 3192 (single buffer frame) or middle (not first and not last) */ 3193 if (!skb || 3194 (!(bd_status & (R_F | R_L))) || 3195 (bd_status & R_ERRORS_FATAL)) { 3196 if (netif_msg_rx_err(ugeth)) 3197 pr_err("%d: ERROR!!! skb - 0x%08x\n", 3198 __LINE__, (u32)skb); 3199 dev_kfree_skb(skb); 3200 3201 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3202 dev->stats.rx_dropped++; 3203 } else { 3204 dev->stats.rx_packets++; 3205 howmany++; 3206 3207 /* Prep the skb for the packet */ 3208 skb_put(skb, length); 3209 3210 /* Tell the skb what kind of packet this is */ 3211 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3212 3213 dev->stats.rx_bytes += length; 3214 /* Send the packet up the stack */ 3215 netif_receive_skb(skb); 3216 } 3217 3218 skb = get_new_skb(ugeth, bd); 3219 if (!skb) { 3220 if (netif_msg_rx_err(ugeth)) 3221 pr_warn("No Rx Data Buffer\n"); 3222 dev->stats.rx_dropped++; 3223 break; 3224 } 3225 3226 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3227 3228 /* update to point at the next skb */ 3229 ugeth->skb_currx[rxQ] = 3230 (ugeth->skb_currx[rxQ] + 3231 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3232 3233 if (bd_status & R_W) 3234 bd = ugeth->p_rx_bd_ring[rxQ]; 3235 else 3236 bd += sizeof(struct qe_bd); 3237 3238 bd_status = in_be32((u32 __iomem *)bd); 3239 } 3240 3241 ugeth->rxBd[rxQ] = bd; 3242 return howmany; 3243 } 3244 3245 static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3246 { 3247 /* Start from the next BD that should be filled */ 3248 struct ucc_geth_private *ugeth = netdev_priv(dev); 3249 u8 __iomem *bd; /* BD pointer */ 3250 u32 bd_status; 3251 3252 bd = ugeth->confBd[txQ]; 3253 bd_status = in_be32((u32 __iomem *)bd); 3254 3255 /* Normal processing. */ 3256 while ((bd_status & T_R) == 0) { 3257 struct sk_buff *skb; 3258 3259 /* BD contains already transmitted buffer. */ 3260 /* Handle the transmitted buffer and release */ 3261 /* the BD to be used with the current frame */ 3262 3263 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3264 if (!skb) 3265 break; 3266 3267 dev->stats.tx_packets++; 3268 3269 dev_kfree_skb(skb); 3270 3271 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3272 ugeth->skb_dirtytx[txQ] = 3273 (ugeth->skb_dirtytx[txQ] + 3274 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3275 3276 /* We freed a buffer, so now we can restart transmission */ 3277 if (netif_queue_stopped(dev)) 3278 netif_wake_queue(dev); 3279 3280 /* Advance the confirmation BD pointer */ 3281 if (!(bd_status & T_W)) 3282 bd += sizeof(struct qe_bd); 3283 else 3284 bd = ugeth->p_tx_bd_ring[txQ]; 3285 bd_status = in_be32((u32 __iomem *)bd); 3286 } 3287 ugeth->confBd[txQ] = bd; 3288 return 0; 3289 } 3290 3291 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3292 { 3293 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3294 struct ucc_geth_info *ug_info; 3295 int howmany, i; 3296 3297 ug_info = ugeth->ug_info; 3298 3299 /* Tx event processing */ 3300 spin_lock(&ugeth->lock); 3301 for (i = 0; i < ug_info->numQueuesTx; i++) 3302 ucc_geth_tx(ugeth->ndev, i); 3303 spin_unlock(&ugeth->lock); 3304 3305 howmany = 0; 3306 for (i = 0; i < ug_info->numQueuesRx; i++) 3307 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3308 3309 if (howmany < budget) { 3310 napi_complete(napi); 3311 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3312 } 3313 3314 return howmany; 3315 } 3316 3317 static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3318 { 3319 struct net_device *dev = info; 3320 struct ucc_geth_private *ugeth = netdev_priv(dev); 3321 struct ucc_fast_private *uccf; 3322 struct ucc_geth_info *ug_info; 3323 register u32 ucce; 3324 register u32 uccm; 3325 3326 ugeth_vdbg("%s: IN", __func__); 3327 3328 uccf = ugeth->uccf; 3329 ug_info = ugeth->ug_info; 3330 3331 /* read and clear events */ 3332 ucce = (u32) in_be32(uccf->p_ucce); 3333 uccm = (u32) in_be32(uccf->p_uccm); 3334 ucce &= uccm; 3335 out_be32(uccf->p_ucce, ucce); 3336 3337 /* check for receive events that require processing */ 3338 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3339 if (napi_schedule_prep(&ugeth->napi)) { 3340 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3341 out_be32(uccf->p_uccm, uccm); 3342 __napi_schedule(&ugeth->napi); 3343 } 3344 } 3345 3346 /* Errors and other events */ 3347 if (ucce & UCCE_OTHER) { 3348 if (ucce & UCC_GETH_UCCE_BSY) 3349 dev->stats.rx_errors++; 3350 if (ucce & UCC_GETH_UCCE_TXE) 3351 dev->stats.tx_errors++; 3352 } 3353 3354 return IRQ_HANDLED; 3355 } 3356 3357 #ifdef CONFIG_NET_POLL_CONTROLLER 3358 /* 3359 * Polling 'interrupt' - used by things like netconsole to send skbs 3360 * without having to re-enable interrupts. It's not called while 3361 * the interrupt routine is executing. 3362 */ 3363 static void ucc_netpoll(struct net_device *dev) 3364 { 3365 struct ucc_geth_private *ugeth = netdev_priv(dev); 3366 int irq = ugeth->ug_info->uf_info.irq; 3367 3368 disable_irq(irq); 3369 ucc_geth_irq_handler(irq, dev); 3370 enable_irq(irq); 3371 } 3372 #endif /* CONFIG_NET_POLL_CONTROLLER */ 3373 3374 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3375 { 3376 struct ucc_geth_private *ugeth = netdev_priv(dev); 3377 struct sockaddr *addr = p; 3378 3379 if (!is_valid_ether_addr(addr->sa_data)) 3380 return -EADDRNOTAVAIL; 3381 3382 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3383 3384 /* 3385 * If device is not running, we will set mac addr register 3386 * when opening the device. 3387 */ 3388 if (!netif_running(dev)) 3389 return 0; 3390 3391 spin_lock_irq(&ugeth->lock); 3392 init_mac_station_addr_regs(dev->dev_addr[0], 3393 dev->dev_addr[1], 3394 dev->dev_addr[2], 3395 dev->dev_addr[3], 3396 dev->dev_addr[4], 3397 dev->dev_addr[5], 3398 &ugeth->ug_regs->macstnaddr1, 3399 &ugeth->ug_regs->macstnaddr2); 3400 spin_unlock_irq(&ugeth->lock); 3401 3402 return 0; 3403 } 3404 3405 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3406 { 3407 struct net_device *dev = ugeth->ndev; 3408 int err; 3409 3410 err = ucc_struct_init(ugeth); 3411 if (err) { 3412 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3413 goto err; 3414 } 3415 3416 err = ucc_geth_startup(ugeth); 3417 if (err) { 3418 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3419 goto err; 3420 } 3421 3422 err = adjust_enet_interface(ugeth); 3423 if (err) { 3424 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3425 goto err; 3426 } 3427 3428 /* Set MACSTNADDR1, MACSTNADDR2 */ 3429 /* For more details see the hardware spec. */ 3430 init_mac_station_addr_regs(dev->dev_addr[0], 3431 dev->dev_addr[1], 3432 dev->dev_addr[2], 3433 dev->dev_addr[3], 3434 dev->dev_addr[4], 3435 dev->dev_addr[5], 3436 &ugeth->ug_regs->macstnaddr1, 3437 &ugeth->ug_regs->macstnaddr2); 3438 3439 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3440 if (err) { 3441 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n"); 3442 goto err; 3443 } 3444 3445 return 0; 3446 err: 3447 ucc_geth_stop(ugeth); 3448 return err; 3449 } 3450 3451 /* Called when something needs to use the ethernet device */ 3452 /* Returns 0 for success. */ 3453 static int ucc_geth_open(struct net_device *dev) 3454 { 3455 struct ucc_geth_private *ugeth = netdev_priv(dev); 3456 int err; 3457 3458 ugeth_vdbg("%s: IN", __func__); 3459 3460 /* Test station address */ 3461 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3462 netif_err(ugeth, ifup, dev, 3463 "Multicast address used for station address - is this what you wanted?\n"); 3464 return -EINVAL; 3465 } 3466 3467 err = init_phy(dev); 3468 if (err) { 3469 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n"); 3470 return err; 3471 } 3472 3473 err = ucc_geth_init_mac(ugeth); 3474 if (err) { 3475 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3476 goto err; 3477 } 3478 3479 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3480 0, "UCC Geth", dev); 3481 if (err) { 3482 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3483 goto err; 3484 } 3485 3486 phy_start(ugeth->phydev); 3487 napi_enable(&ugeth->napi); 3488 netif_start_queue(dev); 3489 3490 device_set_wakeup_capable(&dev->dev, 3491 qe_alive_during_sleep() || ugeth->phydev->irq); 3492 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3493 3494 return err; 3495 3496 err: 3497 ucc_geth_stop(ugeth); 3498 return err; 3499 } 3500 3501 /* Stops the kernel queue, and halts the controller */ 3502 static int ucc_geth_close(struct net_device *dev) 3503 { 3504 struct ucc_geth_private *ugeth = netdev_priv(dev); 3505 3506 ugeth_vdbg("%s: IN", __func__); 3507 3508 napi_disable(&ugeth->napi); 3509 3510 cancel_work_sync(&ugeth->timeout_work); 3511 ucc_geth_stop(ugeth); 3512 phy_disconnect(ugeth->phydev); 3513 ugeth->phydev = NULL; 3514 3515 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3516 3517 netif_stop_queue(dev); 3518 3519 return 0; 3520 } 3521 3522 /* Reopen device. This will reset the MAC and PHY. */ 3523 static void ucc_geth_timeout_work(struct work_struct *work) 3524 { 3525 struct ucc_geth_private *ugeth; 3526 struct net_device *dev; 3527 3528 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3529 dev = ugeth->ndev; 3530 3531 ugeth_vdbg("%s: IN", __func__); 3532 3533 dev->stats.tx_errors++; 3534 3535 ugeth_dump_regs(ugeth); 3536 3537 if (dev->flags & IFF_UP) { 3538 /* 3539 * Must reset MAC *and* PHY. This is done by reopening 3540 * the device. 3541 */ 3542 netif_tx_stop_all_queues(dev); 3543 ucc_geth_stop(ugeth); 3544 ucc_geth_init_mac(ugeth); 3545 /* Must start PHY here */ 3546 phy_start(ugeth->phydev); 3547 netif_tx_start_all_queues(dev); 3548 } 3549 3550 netif_tx_schedule_all(dev); 3551 } 3552 3553 /* 3554 * ucc_geth_timeout gets called when a packet has not been 3555 * transmitted after a set amount of time. 3556 */ 3557 static void ucc_geth_timeout(struct net_device *dev) 3558 { 3559 struct ucc_geth_private *ugeth = netdev_priv(dev); 3560 3561 schedule_work(&ugeth->timeout_work); 3562 } 3563 3564 3565 #ifdef CONFIG_PM 3566 3567 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3568 { 3569 struct net_device *ndev = platform_get_drvdata(ofdev); 3570 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3571 3572 if (!netif_running(ndev)) 3573 return 0; 3574 3575 netif_device_detach(ndev); 3576 napi_disable(&ugeth->napi); 3577 3578 /* 3579 * Disable the controller, otherwise we'll wakeup on any network 3580 * activity. 3581 */ 3582 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3583 3584 if (ugeth->wol_en & WAKE_MAGIC) { 3585 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3586 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3587 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3588 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3589 phy_stop(ugeth->phydev); 3590 } 3591 3592 return 0; 3593 } 3594 3595 static int ucc_geth_resume(struct platform_device *ofdev) 3596 { 3597 struct net_device *ndev = platform_get_drvdata(ofdev); 3598 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3599 int err; 3600 3601 if (!netif_running(ndev)) 3602 return 0; 3603 3604 if (qe_alive_during_sleep()) { 3605 if (ugeth->wol_en & WAKE_MAGIC) { 3606 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3607 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3608 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3609 } 3610 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3611 } else { 3612 /* 3613 * Full reinitialization is required if QE shuts down 3614 * during sleep. 3615 */ 3616 ucc_geth_memclean(ugeth); 3617 3618 err = ucc_geth_init_mac(ugeth); 3619 if (err) { 3620 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3621 return err; 3622 } 3623 } 3624 3625 ugeth->oldlink = 0; 3626 ugeth->oldspeed = 0; 3627 ugeth->oldduplex = -1; 3628 3629 phy_stop(ugeth->phydev); 3630 phy_start(ugeth->phydev); 3631 3632 napi_enable(&ugeth->napi); 3633 netif_device_attach(ndev); 3634 3635 return 0; 3636 } 3637 3638 #else 3639 #define ucc_geth_suspend NULL 3640 #define ucc_geth_resume NULL 3641 #endif 3642 3643 static phy_interface_t to_phy_interface(const char *phy_connection_type) 3644 { 3645 if (strcasecmp(phy_connection_type, "mii") == 0) 3646 return PHY_INTERFACE_MODE_MII; 3647 if (strcasecmp(phy_connection_type, "gmii") == 0) 3648 return PHY_INTERFACE_MODE_GMII; 3649 if (strcasecmp(phy_connection_type, "tbi") == 0) 3650 return PHY_INTERFACE_MODE_TBI; 3651 if (strcasecmp(phy_connection_type, "rmii") == 0) 3652 return PHY_INTERFACE_MODE_RMII; 3653 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3654 return PHY_INTERFACE_MODE_RGMII; 3655 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3656 return PHY_INTERFACE_MODE_RGMII_ID; 3657 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3658 return PHY_INTERFACE_MODE_RGMII_TXID; 3659 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3660 return PHY_INTERFACE_MODE_RGMII_RXID; 3661 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3662 return PHY_INTERFACE_MODE_RTBI; 3663 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3664 return PHY_INTERFACE_MODE_SGMII; 3665 3666 return PHY_INTERFACE_MODE_MII; 3667 } 3668 3669 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3670 { 3671 struct ucc_geth_private *ugeth = netdev_priv(dev); 3672 3673 if (!netif_running(dev)) 3674 return -EINVAL; 3675 3676 if (!ugeth->phydev) 3677 return -ENODEV; 3678 3679 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3680 } 3681 3682 static const struct net_device_ops ucc_geth_netdev_ops = { 3683 .ndo_open = ucc_geth_open, 3684 .ndo_stop = ucc_geth_close, 3685 .ndo_start_xmit = ucc_geth_start_xmit, 3686 .ndo_validate_addr = eth_validate_addr, 3687 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3688 .ndo_change_mtu = eth_change_mtu, 3689 .ndo_set_rx_mode = ucc_geth_set_multi, 3690 .ndo_tx_timeout = ucc_geth_timeout, 3691 .ndo_do_ioctl = ucc_geth_ioctl, 3692 #ifdef CONFIG_NET_POLL_CONTROLLER 3693 .ndo_poll_controller = ucc_netpoll, 3694 #endif 3695 }; 3696 3697 static int ucc_geth_probe(struct platform_device* ofdev) 3698 { 3699 struct device *device = &ofdev->dev; 3700 struct device_node *np = ofdev->dev.of_node; 3701 struct net_device *dev = NULL; 3702 struct ucc_geth_private *ugeth = NULL; 3703 struct ucc_geth_info *ug_info; 3704 struct resource res; 3705 int err, ucc_num, max_speed = 0; 3706 const unsigned int *prop; 3707 const char *sprop; 3708 const void *mac_addr; 3709 phy_interface_t phy_interface; 3710 static const int enet_to_speed[] = { 3711 SPEED_10, SPEED_10, SPEED_10, 3712 SPEED_100, SPEED_100, SPEED_100, 3713 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3714 }; 3715 static const phy_interface_t enet_to_phy_interface[] = { 3716 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3717 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3718 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3719 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3720 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3721 PHY_INTERFACE_MODE_SGMII, 3722 }; 3723 3724 ugeth_vdbg("%s: IN", __func__); 3725 3726 prop = of_get_property(np, "cell-index", NULL); 3727 if (!prop) { 3728 prop = of_get_property(np, "device-id", NULL); 3729 if (!prop) 3730 return -ENODEV; 3731 } 3732 3733 ucc_num = *prop - 1; 3734 if ((ucc_num < 0) || (ucc_num > 7)) 3735 return -ENODEV; 3736 3737 ug_info = &ugeth_info[ucc_num]; 3738 if (ug_info == NULL) { 3739 if (netif_msg_probe(&debug)) 3740 pr_err("[%d] Missing additional data!\n", ucc_num); 3741 return -ENODEV; 3742 } 3743 3744 ug_info->uf_info.ucc_num = ucc_num; 3745 3746 sprop = of_get_property(np, "rx-clock-name", NULL); 3747 if (sprop) { 3748 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3749 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3750 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3751 pr_err("invalid rx-clock-name property\n"); 3752 return -EINVAL; 3753 } 3754 } else { 3755 prop = of_get_property(np, "rx-clock", NULL); 3756 if (!prop) { 3757 /* If both rx-clock-name and rx-clock are missing, 3758 we want to tell people to use rx-clock-name. */ 3759 pr_err("missing rx-clock-name property\n"); 3760 return -EINVAL; 3761 } 3762 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3763 pr_err("invalid rx-clock propperty\n"); 3764 return -EINVAL; 3765 } 3766 ug_info->uf_info.rx_clock = *prop; 3767 } 3768 3769 sprop = of_get_property(np, "tx-clock-name", NULL); 3770 if (sprop) { 3771 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3772 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3773 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3774 pr_err("invalid tx-clock-name property\n"); 3775 return -EINVAL; 3776 } 3777 } else { 3778 prop = of_get_property(np, "tx-clock", NULL); 3779 if (!prop) { 3780 pr_err("missing tx-clock-name property\n"); 3781 return -EINVAL; 3782 } 3783 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3784 pr_err("invalid tx-clock property\n"); 3785 return -EINVAL; 3786 } 3787 ug_info->uf_info.tx_clock = *prop; 3788 } 3789 3790 err = of_address_to_resource(np, 0, &res); 3791 if (err) 3792 return -EINVAL; 3793 3794 ug_info->uf_info.regs = res.start; 3795 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3796 3797 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3798 3799 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3800 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3801 3802 /* get the phy interface type, or default to MII */ 3803 prop = of_get_property(np, "phy-connection-type", NULL); 3804 if (!prop) { 3805 /* handle interface property present in old trees */ 3806 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3807 if (prop != NULL) { 3808 phy_interface = enet_to_phy_interface[*prop]; 3809 max_speed = enet_to_speed[*prop]; 3810 } else 3811 phy_interface = PHY_INTERFACE_MODE_MII; 3812 } else { 3813 phy_interface = to_phy_interface((const char *)prop); 3814 } 3815 3816 /* get speed, or derive from PHY interface */ 3817 if (max_speed == 0) 3818 switch (phy_interface) { 3819 case PHY_INTERFACE_MODE_GMII: 3820 case PHY_INTERFACE_MODE_RGMII: 3821 case PHY_INTERFACE_MODE_RGMII_ID: 3822 case PHY_INTERFACE_MODE_RGMII_RXID: 3823 case PHY_INTERFACE_MODE_RGMII_TXID: 3824 case PHY_INTERFACE_MODE_TBI: 3825 case PHY_INTERFACE_MODE_RTBI: 3826 case PHY_INTERFACE_MODE_SGMII: 3827 max_speed = SPEED_1000; 3828 break; 3829 default: 3830 max_speed = SPEED_100; 3831 break; 3832 } 3833 3834 if (max_speed == SPEED_1000) { 3835 unsigned int snums = qe_get_num_of_snums(); 3836 3837 /* configure muram FIFOs for gigabit operation */ 3838 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3839 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3840 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3841 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3842 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3843 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3844 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3845 3846 /* If QE's snum number is 46/76 which means we need to support 3847 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3848 * more Threads to Rx. 3849 */ 3850 if ((snums == 76) || (snums == 46)) 3851 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3852 else 3853 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3854 } 3855 3856 if (netif_msg_probe(&debug)) 3857 pr_info("UCC%1d at 0x%8x (irq = %d)\n", 3858 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs, 3859 ug_info->uf_info.irq); 3860 3861 /* Create an ethernet device instance */ 3862 dev = alloc_etherdev(sizeof(*ugeth)); 3863 3864 if (dev == NULL) 3865 return -ENOMEM; 3866 3867 ugeth = netdev_priv(dev); 3868 spin_lock_init(&ugeth->lock); 3869 3870 /* Create CQs for hash tables */ 3871 INIT_LIST_HEAD(&ugeth->group_hash_q); 3872 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3873 3874 dev_set_drvdata(device, dev); 3875 3876 /* Set the dev->base_addr to the gfar reg region */ 3877 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3878 3879 SET_NETDEV_DEV(dev, device); 3880 3881 /* Fill in the dev structure */ 3882 uec_set_ethtool_ops(dev); 3883 dev->netdev_ops = &ucc_geth_netdev_ops; 3884 dev->watchdog_timeo = TX_TIMEOUT; 3885 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3886 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3887 dev->mtu = 1500; 3888 3889 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3890 ugeth->phy_interface = phy_interface; 3891 ugeth->max_speed = max_speed; 3892 3893 err = register_netdev(dev); 3894 if (err) { 3895 if (netif_msg_probe(ugeth)) 3896 pr_err("%s: Cannot register net device, aborting\n", 3897 dev->name); 3898 free_netdev(dev); 3899 return err; 3900 } 3901 3902 mac_addr = of_get_mac_address(np); 3903 if (mac_addr) 3904 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 3905 3906 ugeth->ug_info = ug_info; 3907 ugeth->dev = device; 3908 ugeth->ndev = dev; 3909 ugeth->node = np; 3910 3911 return 0; 3912 } 3913 3914 static int ucc_geth_remove(struct platform_device* ofdev) 3915 { 3916 struct net_device *dev = platform_get_drvdata(ofdev); 3917 struct ucc_geth_private *ugeth = netdev_priv(dev); 3918 3919 unregister_netdev(dev); 3920 free_netdev(dev); 3921 ucc_geth_memclean(ugeth); 3922 3923 return 0; 3924 } 3925 3926 static struct of_device_id ucc_geth_match[] = { 3927 { 3928 .type = "network", 3929 .compatible = "ucc_geth", 3930 }, 3931 {}, 3932 }; 3933 3934 MODULE_DEVICE_TABLE(of, ucc_geth_match); 3935 3936 static struct platform_driver ucc_geth_driver = { 3937 .driver = { 3938 .name = DRV_NAME, 3939 .owner = THIS_MODULE, 3940 .of_match_table = ucc_geth_match, 3941 }, 3942 .probe = ucc_geth_probe, 3943 .remove = ucc_geth_remove, 3944 .suspend = ucc_geth_suspend, 3945 .resume = ucc_geth_resume, 3946 }; 3947 3948 static int __init ucc_geth_init(void) 3949 { 3950 int i, ret; 3951 3952 if (netif_msg_drv(&debug)) 3953 pr_info(DRV_DESC "\n"); 3954 for (i = 0; i < 8; i++) 3955 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 3956 sizeof(ugeth_primary_info)); 3957 3958 ret = platform_driver_register(&ucc_geth_driver); 3959 3960 return ret; 3961 } 3962 3963 static void __exit ucc_geth_exit(void) 3964 { 3965 platform_driver_unregister(&ucc_geth_driver); 3966 } 3967 3968 module_init(ucc_geth_init); 3969 module_exit(ucc_geth_exit); 3970 3971 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3972 MODULE_DESCRIPTION(DRV_DESC); 3973 MODULE_VERSION(DRV_VERSION); 3974 MODULE_LICENSE("GPL"); 3975