1 /* 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved. 3 * 4 * Author: Shlomi Gridish <gridish@freescale.com> 5 * Li Yang <leoli@freescale.com> 6 * 7 * Description: 8 * QE UCC Gigabit Ethernet Driver 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/slab.h> 22 #include <linux/stddef.h> 23 #include <linux/module.h> 24 #include <linux/interrupt.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/skbuff.h> 28 #include <linux/spinlock.h> 29 #include <linux/mm.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/mii.h> 32 #include <linux/phy.h> 33 #include <linux/phy_fixed.h> 34 #include <linux/workqueue.h> 35 #include <linux/of_address.h> 36 #include <linux/of_irq.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 41 #include <linux/uaccess.h> 42 #include <asm/irq.h> 43 #include <asm/io.h> 44 #include <soc/fsl/qe/immap_qe.h> 45 #include <soc/fsl/qe/qe.h> 46 #include <soc/fsl/qe/ucc.h> 47 #include <soc/fsl/qe/ucc_fast.h> 48 #include <asm/machdep.h> 49 50 #include "ucc_geth.h" 51 52 #undef DEBUG 53 54 #define ugeth_printk(level, format, arg...) \ 55 printk(level format "\n", ## arg) 56 57 #define ugeth_dbg(format, arg...) \ 58 ugeth_printk(KERN_DEBUG , format , ## arg) 59 60 #ifdef UGETH_VERBOSE_DEBUG 61 #define ugeth_vdbg ugeth_dbg 62 #else 63 #define ugeth_vdbg(fmt, args...) do { } while (0) 64 #endif /* UGETH_VERBOSE_DEBUG */ 65 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1 66 67 68 static DEFINE_SPINLOCK(ugeth_lock); 69 70 static struct { 71 u32 msg_enable; 72 } debug = { -1 }; 73 74 module_param_named(debug, debug.msg_enable, int, 0); 75 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)"); 76 77 static struct ucc_geth_info ugeth_primary_info = { 78 .uf_info = { 79 .bd_mem_part = MEM_PART_SYSTEM, 80 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES, 81 .max_rx_buf_length = 1536, 82 /* adjusted at startup if max-speed 1000 */ 83 .urfs = UCC_GETH_URFS_INIT, 84 .urfet = UCC_GETH_URFET_INIT, 85 .urfset = UCC_GETH_URFSET_INIT, 86 .utfs = UCC_GETH_UTFS_INIT, 87 .utfet = UCC_GETH_UTFET_INIT, 88 .utftt = UCC_GETH_UTFTT_INIT, 89 .ufpt = 256, 90 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET, 91 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, 92 .tenc = UCC_FAST_TX_ENCODING_NRZ, 93 .renc = UCC_FAST_RX_ENCODING_NRZ, 94 .tcrc = UCC_FAST_16_BIT_CRC, 95 .synl = UCC_FAST_SYNC_LEN_NOT_USED, 96 }, 97 .numQueuesTx = 1, 98 .numQueuesRx = 1, 99 .extendedFilteringChainPointer = ((uint32_t) NULL), 100 .typeorlen = 3072 /*1536 */ , 101 .nonBackToBackIfgPart1 = 0x40, 102 .nonBackToBackIfgPart2 = 0x60, 103 .miminumInterFrameGapEnforcement = 0x50, 104 .backToBackInterFrameGap = 0x60, 105 .mblinterval = 128, 106 .nortsrbytetime = 5, 107 .fracsiz = 1, 108 .strictpriorityq = 0xff, 109 .altBebTruncation = 0xa, 110 .excessDefer = 1, 111 .maxRetransmission = 0xf, 112 .collisionWindow = 0x37, 113 .receiveFlowControl = 1, 114 .transmitFlowControl = 1, 115 .maxGroupAddrInHash = 4, 116 .maxIndAddrInHash = 4, 117 .prel = 7, 118 .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */ 119 .minFrameLength = 64, 120 .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */ 121 .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */ 122 .vlantype = 0x8100, 123 .ecamptr = ((uint32_t) NULL), 124 .eventRegMask = UCCE_OTHER, 125 .pausePeriod = 0xf000, 126 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1}, 127 .bdRingLenTx = { 128 TX_BD_RING_LEN, 129 TX_BD_RING_LEN, 130 TX_BD_RING_LEN, 131 TX_BD_RING_LEN, 132 TX_BD_RING_LEN, 133 TX_BD_RING_LEN, 134 TX_BD_RING_LEN, 135 TX_BD_RING_LEN}, 136 137 .bdRingLenRx = { 138 RX_BD_RING_LEN, 139 RX_BD_RING_LEN, 140 RX_BD_RING_LEN, 141 RX_BD_RING_LEN, 142 RX_BD_RING_LEN, 143 RX_BD_RING_LEN, 144 RX_BD_RING_LEN, 145 RX_BD_RING_LEN}, 146 147 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1, 148 .largestexternallookupkeysize = 149 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE, 150 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE | 151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX | 152 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX, 153 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP, 154 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP, 155 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT, 156 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE, 157 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC, 158 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1, 159 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1, 160 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 161 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, 162 }; 163 164 static struct ucc_geth_info ugeth_info[8]; 165 166 #ifdef DEBUG 167 static void mem_disp(u8 *addr, int size) 168 { 169 u8 *i; 170 int size16Aling = (size >> 4) << 4; 171 int size4Aling = (size >> 2) << 2; 172 int notAlign = 0; 173 if (size % 16) 174 notAlign = 1; 175 176 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16) 177 printk("0x%08x: %08x %08x %08x %08x\r\n", 178 (u32) i, 179 *((u32 *) (i)), 180 *((u32 *) (i + 4)), 181 *((u32 *) (i + 8)), *((u32 *) (i + 12))); 182 if (notAlign == 1) 183 printk("0x%08x: ", (u32) i); 184 for (; (u32) i < (u32) addr + size4Aling; i += 4) 185 printk("%08x ", *((u32 *) (i))); 186 for (; (u32) i < (u32) addr + size; i++) 187 printk("%02x", *((i))); 188 if (notAlign == 1) 189 printk("\r\n"); 190 } 191 #endif /* DEBUG */ 192 193 static struct list_head *dequeue(struct list_head *lh) 194 { 195 unsigned long flags; 196 197 spin_lock_irqsave(&ugeth_lock, flags); 198 if (!list_empty(lh)) { 199 struct list_head *node = lh->next; 200 list_del(node); 201 spin_unlock_irqrestore(&ugeth_lock, flags); 202 return node; 203 } else { 204 spin_unlock_irqrestore(&ugeth_lock, flags); 205 return NULL; 206 } 207 } 208 209 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, 210 u8 __iomem *bd) 211 { 212 struct sk_buff *skb; 213 214 skb = netdev_alloc_skb(ugeth->ndev, 215 ugeth->ug_info->uf_info.max_rx_buf_length + 216 UCC_GETH_RX_DATA_BUF_ALIGNMENT); 217 if (!skb) 218 return NULL; 219 220 /* We need the data buffer to be aligned properly. We will reserve 221 * as many bytes as needed to align the data properly 222 */ 223 skb_reserve(skb, 224 UCC_GETH_RX_DATA_BUF_ALIGNMENT - 225 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT - 226 1))); 227 228 out_be32(&((struct qe_bd __iomem *)bd)->buf, 229 dma_map_single(ugeth->dev, 230 skb->data, 231 ugeth->ug_info->uf_info.max_rx_buf_length + 232 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 233 DMA_FROM_DEVICE)); 234 235 out_be32((u32 __iomem *)bd, 236 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W))); 237 238 return skb; 239 } 240 241 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ) 242 { 243 u8 __iomem *bd; 244 u32 bd_status; 245 struct sk_buff *skb; 246 int i; 247 248 bd = ugeth->p_rx_bd_ring[rxQ]; 249 i = 0; 250 251 do { 252 bd_status = in_be32((u32 __iomem *)bd); 253 skb = get_new_skb(ugeth, bd); 254 255 if (!skb) /* If can not allocate data buffer, 256 abort. Cleanup will be elsewhere */ 257 return -ENOMEM; 258 259 ugeth->rx_skbuff[rxQ][i] = skb; 260 261 /* advance the BD pointer */ 262 bd += sizeof(struct qe_bd); 263 i++; 264 } while (!(bd_status & R_W)); 265 266 return 0; 267 } 268 269 static int fill_init_enet_entries(struct ucc_geth_private *ugeth, 270 u32 *p_start, 271 u8 num_entries, 272 u32 thread_size, 273 u32 thread_alignment, 274 unsigned int risc, 275 int skip_page_for_first_entry) 276 { 277 u32 init_enet_offset; 278 u8 i; 279 int snum; 280 281 for (i = 0; i < num_entries; i++) { 282 if ((snum = qe_get_snum()) < 0) { 283 if (netif_msg_ifup(ugeth)) 284 pr_err("Can not get SNUM\n"); 285 return snum; 286 } 287 if ((i == 0) && skip_page_for_first_entry) 288 /* First entry of Rx does not have page */ 289 init_enet_offset = 0; 290 else { 291 init_enet_offset = 292 qe_muram_alloc(thread_size, thread_alignment); 293 if (IS_ERR_VALUE(init_enet_offset)) { 294 if (netif_msg_ifup(ugeth)) 295 pr_err("Can not allocate DPRAM memory\n"); 296 qe_put_snum((u8) snum); 297 return -ENOMEM; 298 } 299 } 300 *(p_start++) = 301 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset 302 | risc; 303 } 304 305 return 0; 306 } 307 308 static int return_init_enet_entries(struct ucc_geth_private *ugeth, 309 u32 *p_start, 310 u8 num_entries, 311 unsigned int risc, 312 int skip_page_for_first_entry) 313 { 314 u32 init_enet_offset; 315 u8 i; 316 int snum; 317 318 for (i = 0; i < num_entries; i++) { 319 u32 val = *p_start; 320 321 /* Check that this entry was actually valid -- 322 needed in case failed in allocations */ 323 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 324 snum = 325 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 326 ENET_INIT_PARAM_SNUM_SHIFT; 327 qe_put_snum((u8) snum); 328 if (!((i == 0) && skip_page_for_first_entry)) { 329 /* First entry of Rx does not have page */ 330 init_enet_offset = 331 (val & ENET_INIT_PARAM_PTR_MASK); 332 qe_muram_free(init_enet_offset); 333 } 334 *p_start++ = 0; 335 } 336 } 337 338 return 0; 339 } 340 341 #ifdef DEBUG 342 static int dump_init_enet_entries(struct ucc_geth_private *ugeth, 343 u32 __iomem *p_start, 344 u8 num_entries, 345 u32 thread_size, 346 unsigned int risc, 347 int skip_page_for_first_entry) 348 { 349 u32 init_enet_offset; 350 u8 i; 351 int snum; 352 353 for (i = 0; i < num_entries; i++) { 354 u32 val = in_be32(p_start); 355 356 /* Check that this entry was actually valid -- 357 needed in case failed in allocations */ 358 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) { 359 snum = 360 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >> 361 ENET_INIT_PARAM_SNUM_SHIFT; 362 qe_put_snum((u8) snum); 363 if (!((i == 0) && skip_page_for_first_entry)) { 364 /* First entry of Rx does not have page */ 365 init_enet_offset = 366 (in_be32(p_start) & 367 ENET_INIT_PARAM_PTR_MASK); 368 pr_info("Init enet entry %d:\n", i); 369 pr_info("Base address: 0x%08x\n", 370 (u32)qe_muram_addr(init_enet_offset)); 371 mem_disp(qe_muram_addr(init_enet_offset), 372 thread_size); 373 } 374 p_start++; 375 } 376 } 377 378 return 0; 379 } 380 #endif 381 382 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont) 383 { 384 kfree(enet_addr_cont); 385 } 386 387 static void set_mac_addr(__be16 __iomem *reg, u8 *mac) 388 { 389 out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); 390 out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); 391 out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); 392 } 393 394 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num) 395 { 396 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 397 398 if (paddr_num >= NUM_OF_PADDRS) { 399 pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num); 400 return -EINVAL; 401 } 402 403 p_82xx_addr_filt = 404 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 405 addressfiltering; 406 407 /* Writing address ff.ff.ff.ff.ff.ff disables address 408 recognition for this register */ 409 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff); 410 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff); 411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff); 412 413 return 0; 414 } 415 416 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth, 417 u8 *p_enet_addr) 418 { 419 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 420 u32 cecr_subblock; 421 422 p_82xx_addr_filt = 423 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram-> 424 addressfiltering; 425 426 cecr_subblock = 427 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 428 429 /* Ethernet frames are defined in Little Endian mode, 430 therefore to insert */ 431 /* the address to the hash (Big Endian mode), we reverse the bytes.*/ 432 433 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr); 434 435 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock, 436 QE_CR_PROTOCOL_ETHERNET, 0); 437 } 438 439 #ifdef DEBUG 440 static void get_statistics(struct ucc_geth_private *ugeth, 441 struct ucc_geth_tx_firmware_statistics * 442 tx_firmware_statistics, 443 struct ucc_geth_rx_firmware_statistics * 444 rx_firmware_statistics, 445 struct ucc_geth_hardware_statistics *hardware_statistics) 446 { 447 struct ucc_fast __iomem *uf_regs; 448 struct ucc_geth __iomem *ug_regs; 449 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram; 450 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram; 451 452 ug_regs = ugeth->ug_regs; 453 uf_regs = (struct ucc_fast __iomem *) ug_regs; 454 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram; 455 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram; 456 457 /* Tx firmware only if user handed pointer and driver actually 458 gathers Tx firmware statistics */ 459 if (tx_firmware_statistics && p_tx_fw_statistics_pram) { 460 tx_firmware_statistics->sicoltx = 461 in_be32(&p_tx_fw_statistics_pram->sicoltx); 462 tx_firmware_statistics->mulcoltx = 463 in_be32(&p_tx_fw_statistics_pram->mulcoltx); 464 tx_firmware_statistics->latecoltxfr = 465 in_be32(&p_tx_fw_statistics_pram->latecoltxfr); 466 tx_firmware_statistics->frabortduecol = 467 in_be32(&p_tx_fw_statistics_pram->frabortduecol); 468 tx_firmware_statistics->frlostinmactxer = 469 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer); 470 tx_firmware_statistics->carriersenseertx = 471 in_be32(&p_tx_fw_statistics_pram->carriersenseertx); 472 tx_firmware_statistics->frtxok = 473 in_be32(&p_tx_fw_statistics_pram->frtxok); 474 tx_firmware_statistics->txfrexcessivedefer = 475 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer); 476 tx_firmware_statistics->txpkts256 = 477 in_be32(&p_tx_fw_statistics_pram->txpkts256); 478 tx_firmware_statistics->txpkts512 = 479 in_be32(&p_tx_fw_statistics_pram->txpkts512); 480 tx_firmware_statistics->txpkts1024 = 481 in_be32(&p_tx_fw_statistics_pram->txpkts1024); 482 tx_firmware_statistics->txpktsjumbo = 483 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo); 484 } 485 486 /* Rx firmware only if user handed pointer and driver actually 487 * gathers Rx firmware statistics */ 488 if (rx_firmware_statistics && p_rx_fw_statistics_pram) { 489 int i; 490 rx_firmware_statistics->frrxfcser = 491 in_be32(&p_rx_fw_statistics_pram->frrxfcser); 492 rx_firmware_statistics->fraligner = 493 in_be32(&p_rx_fw_statistics_pram->fraligner); 494 rx_firmware_statistics->inrangelenrxer = 495 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer); 496 rx_firmware_statistics->outrangelenrxer = 497 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer); 498 rx_firmware_statistics->frtoolong = 499 in_be32(&p_rx_fw_statistics_pram->frtoolong); 500 rx_firmware_statistics->runt = 501 in_be32(&p_rx_fw_statistics_pram->runt); 502 rx_firmware_statistics->verylongevent = 503 in_be32(&p_rx_fw_statistics_pram->verylongevent); 504 rx_firmware_statistics->symbolerror = 505 in_be32(&p_rx_fw_statistics_pram->symbolerror); 506 rx_firmware_statistics->dropbsy = 507 in_be32(&p_rx_fw_statistics_pram->dropbsy); 508 for (i = 0; i < 0x8; i++) 509 rx_firmware_statistics->res0[i] = 510 p_rx_fw_statistics_pram->res0[i]; 511 rx_firmware_statistics->mismatchdrop = 512 in_be32(&p_rx_fw_statistics_pram->mismatchdrop); 513 rx_firmware_statistics->underpkts = 514 in_be32(&p_rx_fw_statistics_pram->underpkts); 515 rx_firmware_statistics->pkts256 = 516 in_be32(&p_rx_fw_statistics_pram->pkts256); 517 rx_firmware_statistics->pkts512 = 518 in_be32(&p_rx_fw_statistics_pram->pkts512); 519 rx_firmware_statistics->pkts1024 = 520 in_be32(&p_rx_fw_statistics_pram->pkts1024); 521 rx_firmware_statistics->pktsjumbo = 522 in_be32(&p_rx_fw_statistics_pram->pktsjumbo); 523 rx_firmware_statistics->frlossinmacer = 524 in_be32(&p_rx_fw_statistics_pram->frlossinmacer); 525 rx_firmware_statistics->pausefr = 526 in_be32(&p_rx_fw_statistics_pram->pausefr); 527 for (i = 0; i < 0x4; i++) 528 rx_firmware_statistics->res1[i] = 529 p_rx_fw_statistics_pram->res1[i]; 530 rx_firmware_statistics->removevlan = 531 in_be32(&p_rx_fw_statistics_pram->removevlan); 532 rx_firmware_statistics->replacevlan = 533 in_be32(&p_rx_fw_statistics_pram->replacevlan); 534 rx_firmware_statistics->insertvlan = 535 in_be32(&p_rx_fw_statistics_pram->insertvlan); 536 } 537 538 /* Hardware only if user handed pointer and driver actually 539 gathers hardware statistics */ 540 if (hardware_statistics && 541 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) { 542 hardware_statistics->tx64 = in_be32(&ug_regs->tx64); 543 hardware_statistics->tx127 = in_be32(&ug_regs->tx127); 544 hardware_statistics->tx255 = in_be32(&ug_regs->tx255); 545 hardware_statistics->rx64 = in_be32(&ug_regs->rx64); 546 hardware_statistics->rx127 = in_be32(&ug_regs->rx127); 547 hardware_statistics->rx255 = in_be32(&ug_regs->rx255); 548 hardware_statistics->txok = in_be32(&ug_regs->txok); 549 hardware_statistics->txcf = in_be16(&ug_regs->txcf); 550 hardware_statistics->tmca = in_be32(&ug_regs->tmca); 551 hardware_statistics->tbca = in_be32(&ug_regs->tbca); 552 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok); 553 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok); 554 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt); 555 hardware_statistics->rmca = in_be32(&ug_regs->rmca); 556 hardware_statistics->rbca = in_be32(&ug_regs->rbca); 557 } 558 } 559 560 static void dump_bds(struct ucc_geth_private *ugeth) 561 { 562 int i; 563 int length; 564 565 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 566 if (ugeth->p_tx_bd_ring[i]) { 567 length = 568 (ugeth->ug_info->bdRingLenTx[i] * 569 sizeof(struct qe_bd)); 570 pr_info("TX BDs[%d]\n", i); 571 mem_disp(ugeth->p_tx_bd_ring[i], length); 572 } 573 } 574 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 575 if (ugeth->p_rx_bd_ring[i]) { 576 length = 577 (ugeth->ug_info->bdRingLenRx[i] * 578 sizeof(struct qe_bd)); 579 pr_info("RX BDs[%d]\n", i); 580 mem_disp(ugeth->p_rx_bd_ring[i], length); 581 } 582 } 583 } 584 585 static void dump_regs(struct ucc_geth_private *ugeth) 586 { 587 int i; 588 589 pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1); 590 pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs); 591 592 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n", 593 (u32)&ugeth->ug_regs->maccfg1, 594 in_be32(&ugeth->ug_regs->maccfg1)); 595 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n", 596 (u32)&ugeth->ug_regs->maccfg2, 597 in_be32(&ugeth->ug_regs->maccfg2)); 598 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n", 599 (u32)&ugeth->ug_regs->ipgifg, 600 in_be32(&ugeth->ug_regs->ipgifg)); 601 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n", 602 (u32)&ugeth->ug_regs->hafdup, 603 in_be32(&ugeth->ug_regs->hafdup)); 604 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n", 605 (u32)&ugeth->ug_regs->ifctl, 606 in_be32(&ugeth->ug_regs->ifctl)); 607 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n", 608 (u32)&ugeth->ug_regs->ifstat, 609 in_be32(&ugeth->ug_regs->ifstat)); 610 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n", 611 (u32)&ugeth->ug_regs->macstnaddr1, 612 in_be32(&ugeth->ug_regs->macstnaddr1)); 613 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n", 614 (u32)&ugeth->ug_regs->macstnaddr2, 615 in_be32(&ugeth->ug_regs->macstnaddr2)); 616 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n", 617 (u32)&ugeth->ug_regs->uempr, 618 in_be32(&ugeth->ug_regs->uempr)); 619 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n", 620 (u32)&ugeth->ug_regs->utbipar, 621 in_be32(&ugeth->ug_regs->utbipar)); 622 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n", 623 (u32)&ugeth->ug_regs->uescr, 624 in_be16(&ugeth->ug_regs->uescr)); 625 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n", 626 (u32)&ugeth->ug_regs->tx64, 627 in_be32(&ugeth->ug_regs->tx64)); 628 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n", 629 (u32)&ugeth->ug_regs->tx127, 630 in_be32(&ugeth->ug_regs->tx127)); 631 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n", 632 (u32)&ugeth->ug_regs->tx255, 633 in_be32(&ugeth->ug_regs->tx255)); 634 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n", 635 (u32)&ugeth->ug_regs->rx64, 636 in_be32(&ugeth->ug_regs->rx64)); 637 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n", 638 (u32)&ugeth->ug_regs->rx127, 639 in_be32(&ugeth->ug_regs->rx127)); 640 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n", 641 (u32)&ugeth->ug_regs->rx255, 642 in_be32(&ugeth->ug_regs->rx255)); 643 pr_info("txok : addr - 0x%08x, val - 0x%08x\n", 644 (u32)&ugeth->ug_regs->txok, 645 in_be32(&ugeth->ug_regs->txok)); 646 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n", 647 (u32)&ugeth->ug_regs->txcf, 648 in_be16(&ugeth->ug_regs->txcf)); 649 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n", 650 (u32)&ugeth->ug_regs->tmca, 651 in_be32(&ugeth->ug_regs->tmca)); 652 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n", 653 (u32)&ugeth->ug_regs->tbca, 654 in_be32(&ugeth->ug_regs->tbca)); 655 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n", 656 (u32)&ugeth->ug_regs->rxfok, 657 in_be32(&ugeth->ug_regs->rxfok)); 658 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n", 659 (u32)&ugeth->ug_regs->rxbok, 660 in_be32(&ugeth->ug_regs->rxbok)); 661 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n", 662 (u32)&ugeth->ug_regs->rbyt, 663 in_be32(&ugeth->ug_regs->rbyt)); 664 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n", 665 (u32)&ugeth->ug_regs->rmca, 666 in_be32(&ugeth->ug_regs->rmca)); 667 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n", 668 (u32)&ugeth->ug_regs->rbca, 669 in_be32(&ugeth->ug_regs->rbca)); 670 pr_info("scar : addr - 0x%08x, val - 0x%08x\n", 671 (u32)&ugeth->ug_regs->scar, 672 in_be32(&ugeth->ug_regs->scar)); 673 pr_info("scam : addr - 0x%08x, val - 0x%08x\n", 674 (u32)&ugeth->ug_regs->scam, 675 in_be32(&ugeth->ug_regs->scam)); 676 677 if (ugeth->p_thread_data_tx) { 678 int numThreadsTxNumerical; 679 switch (ugeth->ug_info->numThreadsTx) { 680 case UCC_GETH_NUM_OF_THREADS_1: 681 numThreadsTxNumerical = 1; 682 break; 683 case UCC_GETH_NUM_OF_THREADS_2: 684 numThreadsTxNumerical = 2; 685 break; 686 case UCC_GETH_NUM_OF_THREADS_4: 687 numThreadsTxNumerical = 4; 688 break; 689 case UCC_GETH_NUM_OF_THREADS_6: 690 numThreadsTxNumerical = 6; 691 break; 692 case UCC_GETH_NUM_OF_THREADS_8: 693 numThreadsTxNumerical = 8; 694 break; 695 default: 696 numThreadsTxNumerical = 0; 697 break; 698 } 699 700 pr_info("Thread data TXs:\n"); 701 pr_info("Base address: 0x%08x\n", 702 (u32)ugeth->p_thread_data_tx); 703 for (i = 0; i < numThreadsTxNumerical; i++) { 704 pr_info("Thread data TX[%d]:\n", i); 705 pr_info("Base address: 0x%08x\n", 706 (u32)&ugeth->p_thread_data_tx[i]); 707 mem_disp((u8 *) & ugeth->p_thread_data_tx[i], 708 sizeof(struct ucc_geth_thread_data_tx)); 709 } 710 } 711 if (ugeth->p_thread_data_rx) { 712 int numThreadsRxNumerical; 713 switch (ugeth->ug_info->numThreadsRx) { 714 case UCC_GETH_NUM_OF_THREADS_1: 715 numThreadsRxNumerical = 1; 716 break; 717 case UCC_GETH_NUM_OF_THREADS_2: 718 numThreadsRxNumerical = 2; 719 break; 720 case UCC_GETH_NUM_OF_THREADS_4: 721 numThreadsRxNumerical = 4; 722 break; 723 case UCC_GETH_NUM_OF_THREADS_6: 724 numThreadsRxNumerical = 6; 725 break; 726 case UCC_GETH_NUM_OF_THREADS_8: 727 numThreadsRxNumerical = 8; 728 break; 729 default: 730 numThreadsRxNumerical = 0; 731 break; 732 } 733 734 pr_info("Thread data RX:\n"); 735 pr_info("Base address: 0x%08x\n", 736 (u32)ugeth->p_thread_data_rx); 737 for (i = 0; i < numThreadsRxNumerical; i++) { 738 pr_info("Thread data RX[%d]:\n", i); 739 pr_info("Base address: 0x%08x\n", 740 (u32)&ugeth->p_thread_data_rx[i]); 741 mem_disp((u8 *) & ugeth->p_thread_data_rx[i], 742 sizeof(struct ucc_geth_thread_data_rx)); 743 } 744 } 745 if (ugeth->p_exf_glbl_param) { 746 pr_info("EXF global param:\n"); 747 pr_info("Base address: 0x%08x\n", 748 (u32)ugeth->p_exf_glbl_param); 749 mem_disp((u8 *) ugeth->p_exf_glbl_param, 750 sizeof(*ugeth->p_exf_glbl_param)); 751 } 752 if (ugeth->p_tx_glbl_pram) { 753 pr_info("TX global param:\n"); 754 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram); 755 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n", 756 (u32)&ugeth->p_tx_glbl_pram->temoder, 757 in_be16(&ugeth->p_tx_glbl_pram->temoder)); 758 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n", 759 (u32)&ugeth->p_tx_glbl_pram->sqptr, 760 in_be32(&ugeth->p_tx_glbl_pram->sqptr)); 761 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n", 762 (u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer, 763 in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer)); 764 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n", 765 (u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr, 766 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr)); 767 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n", 768 (u32)&ugeth->p_tx_glbl_pram->tstate, 769 in_be32(&ugeth->p_tx_glbl_pram->tstate)); 770 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n", 771 (u32)&ugeth->p_tx_glbl_pram->iphoffset[0], 772 ugeth->p_tx_glbl_pram->iphoffset[0]); 773 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n", 774 (u32)&ugeth->p_tx_glbl_pram->iphoffset[1], 775 ugeth->p_tx_glbl_pram->iphoffset[1]); 776 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n", 777 (u32)&ugeth->p_tx_glbl_pram->iphoffset[2], 778 ugeth->p_tx_glbl_pram->iphoffset[2]); 779 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n", 780 (u32)&ugeth->p_tx_glbl_pram->iphoffset[3], 781 ugeth->p_tx_glbl_pram->iphoffset[3]); 782 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n", 783 (u32)&ugeth->p_tx_glbl_pram->iphoffset[4], 784 ugeth->p_tx_glbl_pram->iphoffset[4]); 785 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n", 786 (u32)&ugeth->p_tx_glbl_pram->iphoffset[5], 787 ugeth->p_tx_glbl_pram->iphoffset[5]); 788 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n", 789 (u32)&ugeth->p_tx_glbl_pram->iphoffset[6], 790 ugeth->p_tx_glbl_pram->iphoffset[6]); 791 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n", 792 (u32)&ugeth->p_tx_glbl_pram->iphoffset[7], 793 ugeth->p_tx_glbl_pram->iphoffset[7]); 794 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n", 795 (u32)&ugeth->p_tx_glbl_pram->vtagtable[0], 796 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0])); 797 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n", 798 (u32)&ugeth->p_tx_glbl_pram->vtagtable[1], 799 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1])); 800 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n", 801 (u32)&ugeth->p_tx_glbl_pram->vtagtable[2], 802 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2])); 803 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n", 804 (u32)&ugeth->p_tx_glbl_pram->vtagtable[3], 805 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3])); 806 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n", 807 (u32)&ugeth->p_tx_glbl_pram->vtagtable[4], 808 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4])); 809 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n", 810 (u32)&ugeth->p_tx_glbl_pram->vtagtable[5], 811 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5])); 812 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n", 813 (u32)&ugeth->p_tx_glbl_pram->vtagtable[6], 814 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6])); 815 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n", 816 (u32)&ugeth->p_tx_glbl_pram->vtagtable[7], 817 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7])); 818 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n", 819 (u32)&ugeth->p_tx_glbl_pram->tqptr, 820 in_be32(&ugeth->p_tx_glbl_pram->tqptr)); 821 } 822 if (ugeth->p_rx_glbl_pram) { 823 pr_info("RX global param:\n"); 824 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram); 825 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n", 826 (u32)&ugeth->p_rx_glbl_pram->remoder, 827 in_be32(&ugeth->p_rx_glbl_pram->remoder)); 828 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n", 829 (u32)&ugeth->p_rx_glbl_pram->rqptr, 830 in_be32(&ugeth->p_rx_glbl_pram->rqptr)); 831 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n", 832 (u32)&ugeth->p_rx_glbl_pram->typeorlen, 833 in_be16(&ugeth->p_rx_glbl_pram->typeorlen)); 834 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n", 835 (u32)&ugeth->p_rx_glbl_pram->rxgstpack, 836 ugeth->p_rx_glbl_pram->rxgstpack); 837 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n", 838 (u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr, 839 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr)); 840 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n", 841 (u32)&ugeth->p_rx_glbl_pram->intcoalescingptr, 842 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr)); 843 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n", 844 (u32)&ugeth->p_rx_glbl_pram->rstate, 845 ugeth->p_rx_glbl_pram->rstate); 846 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n", 847 (u32)&ugeth->p_rx_glbl_pram->mrblr, 848 in_be16(&ugeth->p_rx_glbl_pram->mrblr)); 849 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n", 850 (u32)&ugeth->p_rx_glbl_pram->rbdqptr, 851 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr)); 852 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n", 853 (u32)&ugeth->p_rx_glbl_pram->mflr, 854 in_be16(&ugeth->p_rx_glbl_pram->mflr)); 855 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n", 856 (u32)&ugeth->p_rx_glbl_pram->minflr, 857 in_be16(&ugeth->p_rx_glbl_pram->minflr)); 858 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n", 859 (u32)&ugeth->p_rx_glbl_pram->maxd1, 860 in_be16(&ugeth->p_rx_glbl_pram->maxd1)); 861 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n", 862 (u32)&ugeth->p_rx_glbl_pram->maxd2, 863 in_be16(&ugeth->p_rx_glbl_pram->maxd2)); 864 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n", 865 (u32)&ugeth->p_rx_glbl_pram->ecamptr, 866 in_be32(&ugeth->p_rx_glbl_pram->ecamptr)); 867 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n", 868 (u32)&ugeth->p_rx_glbl_pram->l2qt, 869 in_be32(&ugeth->p_rx_glbl_pram->l2qt)); 870 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n", 871 (u32)&ugeth->p_rx_glbl_pram->l3qt[0], 872 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0])); 873 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n", 874 (u32)&ugeth->p_rx_glbl_pram->l3qt[1], 875 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1])); 876 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n", 877 (u32)&ugeth->p_rx_glbl_pram->l3qt[2], 878 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2])); 879 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n", 880 (u32)&ugeth->p_rx_glbl_pram->l3qt[3], 881 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3])); 882 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n", 883 (u32)&ugeth->p_rx_glbl_pram->l3qt[4], 884 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4])); 885 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n", 886 (u32)&ugeth->p_rx_glbl_pram->l3qt[5], 887 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5])); 888 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n", 889 (u32)&ugeth->p_rx_glbl_pram->l3qt[6], 890 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6])); 891 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n", 892 (u32)&ugeth->p_rx_glbl_pram->l3qt[7], 893 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7])); 894 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n", 895 (u32)&ugeth->p_rx_glbl_pram->vlantype, 896 in_be16(&ugeth->p_rx_glbl_pram->vlantype)); 897 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n", 898 (u32)&ugeth->p_rx_glbl_pram->vlantci, 899 in_be16(&ugeth->p_rx_glbl_pram->vlantci)); 900 for (i = 0; i < 64; i++) 901 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n", 902 i, 903 (u32)&ugeth->p_rx_glbl_pram->addressfiltering[i], 904 ugeth->p_rx_glbl_pram->addressfiltering[i]); 905 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n", 906 (u32)&ugeth->p_rx_glbl_pram->exfGlobalParam, 907 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam)); 908 } 909 if (ugeth->p_send_q_mem_reg) { 910 pr_info("Send Q memory registers:\n"); 911 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg); 912 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 913 pr_info("SQQD[%d]:\n", i); 914 pr_info("Base address: 0x%08x\n", 915 (u32)&ugeth->p_send_q_mem_reg->sqqd[i]); 916 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i], 917 sizeof(struct ucc_geth_send_queue_qd)); 918 } 919 } 920 if (ugeth->p_scheduler) { 921 pr_info("Scheduler:\n"); 922 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler); 923 mem_disp((u8 *) ugeth->p_scheduler, 924 sizeof(*ugeth->p_scheduler)); 925 } 926 if (ugeth->p_tx_fw_statistics_pram) { 927 pr_info("TX FW statistics pram:\n"); 928 pr_info("Base address: 0x%08x\n", 929 (u32)ugeth->p_tx_fw_statistics_pram); 930 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram, 931 sizeof(*ugeth->p_tx_fw_statistics_pram)); 932 } 933 if (ugeth->p_rx_fw_statistics_pram) { 934 pr_info("RX FW statistics pram:\n"); 935 pr_info("Base address: 0x%08x\n", 936 (u32)ugeth->p_rx_fw_statistics_pram); 937 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram, 938 sizeof(*ugeth->p_rx_fw_statistics_pram)); 939 } 940 if (ugeth->p_rx_irq_coalescing_tbl) { 941 pr_info("RX IRQ coalescing tables:\n"); 942 pr_info("Base address: 0x%08x\n", 943 (u32)ugeth->p_rx_irq_coalescing_tbl); 944 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 945 pr_info("RX IRQ coalescing table entry[%d]:\n", i); 946 pr_info("Base address: 0x%08x\n", 947 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 948 coalescingentry[i]); 949 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n", 950 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 951 coalescingentry[i].interruptcoalescingmaxvalue, 952 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 953 coalescingentry[i]. 954 interruptcoalescingmaxvalue)); 955 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n", 956 (u32)&ugeth->p_rx_irq_coalescing_tbl-> 957 coalescingentry[i].interruptcoalescingcounter, 958 in_be32(&ugeth->p_rx_irq_coalescing_tbl-> 959 coalescingentry[i]. 960 interruptcoalescingcounter)); 961 } 962 } 963 if (ugeth->p_rx_bd_qs_tbl) { 964 pr_info("RX BD QS tables:\n"); 965 pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl); 966 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 967 pr_info("RX BD QS table[%d]:\n", i); 968 pr_info("Base address: 0x%08x\n", 969 (u32)&ugeth->p_rx_bd_qs_tbl[i]); 970 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n", 971 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr, 972 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr)); 973 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n", 974 (u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr, 975 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr)); 976 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n", 977 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 978 in_be32(&ugeth->p_rx_bd_qs_tbl[i]. 979 externalbdbaseptr)); 980 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n", 981 (u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr, 982 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr)); 983 pr_info("ucode RX Prefetched BDs:\n"); 984 pr_info("Base address: 0x%08x\n", 985 (u32)qe_muram_addr(in_be32 986 (&ugeth->p_rx_bd_qs_tbl[i]. 987 bdbaseptr))); 988 mem_disp((u8 *) 989 qe_muram_addr(in_be32 990 (&ugeth->p_rx_bd_qs_tbl[i]. 991 bdbaseptr)), 992 sizeof(struct ucc_geth_rx_prefetched_bds)); 993 } 994 } 995 if (ugeth->p_init_enet_param_shadow) { 996 int size; 997 pr_info("Init enet param shadow:\n"); 998 pr_info("Base address: 0x%08x\n", 999 (u32) ugeth->p_init_enet_param_shadow); 1000 mem_disp((u8 *) ugeth->p_init_enet_param_shadow, 1001 sizeof(*ugeth->p_init_enet_param_shadow)); 1002 1003 size = sizeof(struct ucc_geth_thread_rx_pram); 1004 if (ugeth->ug_info->rxExtendedFiltering) { 1005 size += 1006 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 1007 if (ugeth->ug_info->largestexternallookupkeysize == 1008 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 1009 size += 1010 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 1011 if (ugeth->ug_info->largestexternallookupkeysize == 1012 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 1013 size += 1014 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 1015 } 1016 1017 dump_init_enet_entries(ugeth, 1018 &(ugeth->p_init_enet_param_shadow-> 1019 txthread[0]), 1020 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1021 sizeof(struct ucc_geth_thread_tx_pram), 1022 ugeth->ug_info->riscTx, 0); 1023 dump_init_enet_entries(ugeth, 1024 &(ugeth->p_init_enet_param_shadow-> 1025 rxthread[0]), 1026 ENET_INIT_PARAM_MAX_ENTRIES_RX, size, 1027 ugeth->ug_info->riscRx, 1); 1028 } 1029 } 1030 #endif /* DEBUG */ 1031 1032 static void init_default_reg_vals(u32 __iomem *upsmr_register, 1033 u32 __iomem *maccfg1_register, 1034 u32 __iomem *maccfg2_register) 1035 { 1036 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT); 1037 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT); 1038 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT); 1039 } 1040 1041 static int init_half_duplex_params(int alt_beb, 1042 int back_pressure_no_backoff, 1043 int no_backoff, 1044 int excess_defer, 1045 u8 alt_beb_truncation, 1046 u8 max_retransmissions, 1047 u8 collision_window, 1048 u32 __iomem *hafdup_register) 1049 { 1050 u32 value = 0; 1051 1052 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) || 1053 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) || 1054 (collision_window > HALFDUP_COLLISION_WINDOW_MAX)) 1055 return -EINVAL; 1056 1057 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT); 1058 1059 if (alt_beb) 1060 value |= HALFDUP_ALT_BEB; 1061 if (back_pressure_no_backoff) 1062 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF; 1063 if (no_backoff) 1064 value |= HALFDUP_NO_BACKOFF; 1065 if (excess_defer) 1066 value |= HALFDUP_EXCESSIVE_DEFER; 1067 1068 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT); 1069 1070 value |= collision_window; 1071 1072 out_be32(hafdup_register, value); 1073 return 0; 1074 } 1075 1076 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg, 1077 u8 non_btb_ipg, 1078 u8 min_ifg, 1079 u8 btb_ipg, 1080 u32 __iomem *ipgifg_register) 1081 { 1082 u32 value = 0; 1083 1084 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back 1085 IPG part 2 */ 1086 if (non_btb_cs_ipg > non_btb_ipg) 1087 return -EINVAL; 1088 1089 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) || 1090 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) || 1091 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */ 1092 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX)) 1093 return -EINVAL; 1094 1095 value |= 1096 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) & 1097 IPGIFG_NBTB_CS_IPG_MASK); 1098 value |= 1099 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) & 1100 IPGIFG_NBTB_IPG_MASK); 1101 value |= 1102 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) & 1103 IPGIFG_MIN_IFG_MASK); 1104 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK); 1105 1106 out_be32(ipgifg_register, value); 1107 return 0; 1108 } 1109 1110 int init_flow_control_params(u32 automatic_flow_control_mode, 1111 int rx_flow_control_enable, 1112 int tx_flow_control_enable, 1113 u16 pause_period, 1114 u16 extension_field, 1115 u32 __iomem *upsmr_register, 1116 u32 __iomem *uempr_register, 1117 u32 __iomem *maccfg1_register) 1118 { 1119 u32 value = 0; 1120 1121 /* Set UEMPR register */ 1122 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT; 1123 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT; 1124 out_be32(uempr_register, value); 1125 1126 /* Set UPSMR register */ 1127 setbits32(upsmr_register, automatic_flow_control_mode); 1128 1129 value = in_be32(maccfg1_register); 1130 if (rx_flow_control_enable) 1131 value |= MACCFG1_FLOW_RX; 1132 if (tx_flow_control_enable) 1133 value |= MACCFG1_FLOW_TX; 1134 out_be32(maccfg1_register, value); 1135 1136 return 0; 1137 } 1138 1139 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics, 1140 int auto_zero_hardware_statistics, 1141 u32 __iomem *upsmr_register, 1142 u16 __iomem *uescr_register) 1143 { 1144 u16 uescr_value = 0; 1145 1146 /* Enable hardware statistics gathering if requested */ 1147 if (enable_hardware_statistics) 1148 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE); 1149 1150 /* Clear hardware statistics counters */ 1151 uescr_value = in_be16(uescr_register); 1152 uescr_value |= UESCR_CLRCNT; 1153 /* Automatically zero hardware statistics counters on read, 1154 if requested */ 1155 if (auto_zero_hardware_statistics) 1156 uescr_value |= UESCR_AUTOZ; 1157 out_be16(uescr_register, uescr_value); 1158 1159 return 0; 1160 } 1161 1162 static int init_firmware_statistics_gathering_mode(int 1163 enable_tx_firmware_statistics, 1164 int enable_rx_firmware_statistics, 1165 u32 __iomem *tx_rmon_base_ptr, 1166 u32 tx_firmware_statistics_structure_address, 1167 u32 __iomem *rx_rmon_base_ptr, 1168 u32 rx_firmware_statistics_structure_address, 1169 u16 __iomem *temoder_register, 1170 u32 __iomem *remoder_register) 1171 { 1172 /* Note: this function does not check if */ 1173 /* the parameters it receives are NULL */ 1174 1175 if (enable_tx_firmware_statistics) { 1176 out_be32(tx_rmon_base_ptr, 1177 tx_firmware_statistics_structure_address); 1178 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE); 1179 } 1180 1181 if (enable_rx_firmware_statistics) { 1182 out_be32(rx_rmon_base_ptr, 1183 rx_firmware_statistics_structure_address); 1184 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE); 1185 } 1186 1187 return 0; 1188 } 1189 1190 static int init_mac_station_addr_regs(u8 address_byte_0, 1191 u8 address_byte_1, 1192 u8 address_byte_2, 1193 u8 address_byte_3, 1194 u8 address_byte_4, 1195 u8 address_byte_5, 1196 u32 __iomem *macstnaddr1_register, 1197 u32 __iomem *macstnaddr2_register) 1198 { 1199 u32 value = 0; 1200 1201 /* Example: for a station address of 0x12345678ABCD, */ 1202 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */ 1203 1204 /* MACSTNADDR1 Register: */ 1205 1206 /* 0 7 8 15 */ 1207 /* station address byte 5 station address byte 4 */ 1208 /* 16 23 24 31 */ 1209 /* station address byte 3 station address byte 2 */ 1210 value |= (u32) ((address_byte_2 << 0) & 0x000000FF); 1211 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00); 1212 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000); 1213 value |= (u32) ((address_byte_5 << 24) & 0xFF000000); 1214 1215 out_be32(macstnaddr1_register, value); 1216 1217 /* MACSTNADDR2 Register: */ 1218 1219 /* 0 7 8 15 */ 1220 /* station address byte 1 station address byte 0 */ 1221 /* 16 23 24 31 */ 1222 /* reserved reserved */ 1223 value = 0; 1224 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000); 1225 value |= (u32) ((address_byte_1 << 24) & 0xFF000000); 1226 1227 out_be32(macstnaddr2_register, value); 1228 1229 return 0; 1230 } 1231 1232 static int init_check_frame_length_mode(int length_check, 1233 u32 __iomem *maccfg2_register) 1234 { 1235 u32 value = 0; 1236 1237 value = in_be32(maccfg2_register); 1238 1239 if (length_check) 1240 value |= MACCFG2_LC; 1241 else 1242 value &= ~MACCFG2_LC; 1243 1244 out_be32(maccfg2_register, value); 1245 return 0; 1246 } 1247 1248 static int init_preamble_length(u8 preamble_length, 1249 u32 __iomem *maccfg2_register) 1250 { 1251 if ((preamble_length < 3) || (preamble_length > 7)) 1252 return -EINVAL; 1253 1254 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK, 1255 preamble_length << MACCFG2_PREL_SHIFT); 1256 1257 return 0; 1258 } 1259 1260 static int init_rx_parameters(int reject_broadcast, 1261 int receive_short_frames, 1262 int promiscuous, u32 __iomem *upsmr_register) 1263 { 1264 u32 value = 0; 1265 1266 value = in_be32(upsmr_register); 1267 1268 if (reject_broadcast) 1269 value |= UCC_GETH_UPSMR_BRO; 1270 else 1271 value &= ~UCC_GETH_UPSMR_BRO; 1272 1273 if (receive_short_frames) 1274 value |= UCC_GETH_UPSMR_RSH; 1275 else 1276 value &= ~UCC_GETH_UPSMR_RSH; 1277 1278 if (promiscuous) 1279 value |= UCC_GETH_UPSMR_PRO; 1280 else 1281 value &= ~UCC_GETH_UPSMR_PRO; 1282 1283 out_be32(upsmr_register, value); 1284 1285 return 0; 1286 } 1287 1288 static int init_max_rx_buff_len(u16 max_rx_buf_len, 1289 u16 __iomem *mrblr_register) 1290 { 1291 /* max_rx_buf_len value must be a multiple of 128 */ 1292 if ((max_rx_buf_len == 0) || 1293 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT)) 1294 return -EINVAL; 1295 1296 out_be16(mrblr_register, max_rx_buf_len); 1297 return 0; 1298 } 1299 1300 static int init_min_frame_len(u16 min_frame_length, 1301 u16 __iomem *minflr_register, 1302 u16 __iomem *mrblr_register) 1303 { 1304 u16 mrblr_value = 0; 1305 1306 mrblr_value = in_be16(mrblr_register); 1307 if (min_frame_length >= (mrblr_value - 4)) 1308 return -EINVAL; 1309 1310 out_be16(minflr_register, min_frame_length); 1311 return 0; 1312 } 1313 1314 static int adjust_enet_interface(struct ucc_geth_private *ugeth) 1315 { 1316 struct ucc_geth_info *ug_info; 1317 struct ucc_geth __iomem *ug_regs; 1318 struct ucc_fast __iomem *uf_regs; 1319 int ret_val; 1320 u32 upsmr, maccfg2; 1321 u16 value; 1322 1323 ugeth_vdbg("%s: IN", __func__); 1324 1325 ug_info = ugeth->ug_info; 1326 ug_regs = ugeth->ug_regs; 1327 uf_regs = ugeth->uccf->uf_regs; 1328 1329 /* Set MACCFG2 */ 1330 maccfg2 = in_be32(&ug_regs->maccfg2); 1331 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; 1332 if ((ugeth->max_speed == SPEED_10) || 1333 (ugeth->max_speed == SPEED_100)) 1334 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; 1335 else if (ugeth->max_speed == SPEED_1000) 1336 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; 1337 maccfg2 |= ug_info->padAndCrc; 1338 out_be32(&ug_regs->maccfg2, maccfg2); 1339 1340 /* Set UPSMR */ 1341 upsmr = in_be32(&uf_regs->upsmr); 1342 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M | 1343 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM); 1344 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1345 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1346 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1347 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1348 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1349 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1350 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII) 1351 upsmr |= UCC_GETH_UPSMR_RPM; 1352 switch (ugeth->max_speed) { 1353 case SPEED_10: 1354 upsmr |= UCC_GETH_UPSMR_R10M; 1355 /* FALLTHROUGH */ 1356 case SPEED_100: 1357 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI) 1358 upsmr |= UCC_GETH_UPSMR_RMM; 1359 } 1360 } 1361 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1362 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1363 upsmr |= UCC_GETH_UPSMR_TBIM; 1364 } 1365 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)) 1366 upsmr |= UCC_GETH_UPSMR_SGMM; 1367 1368 out_be32(&uf_regs->upsmr, upsmr); 1369 1370 /* Disable autonegotiation in tbi mode, because by default it 1371 comes up in autonegotiation mode. */ 1372 /* Note that this depends on proper setting in utbipar register. */ 1373 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) || 1374 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1375 struct ucc_geth_info *ug_info = ugeth->ug_info; 1376 struct phy_device *tbiphy; 1377 1378 if (!ug_info->tbi_node) 1379 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n"); 1380 1381 tbiphy = of_phy_find_device(ug_info->tbi_node); 1382 if (!tbiphy) 1383 pr_warn("Could not get TBI device\n"); 1384 1385 value = phy_read(tbiphy, ENET_TBI_MII_CR); 1386 value &= ~0x1000; /* Turn off autonegotiation */ 1387 phy_write(tbiphy, ENET_TBI_MII_CR, value); 1388 1389 put_device(&tbiphy->mdio.dev); 1390 } 1391 1392 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2); 1393 1394 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2); 1395 if (ret_val != 0) { 1396 if (netif_msg_probe(ugeth)) 1397 pr_err("Preamble length must be between 3 and 7 inclusive\n"); 1398 return ret_val; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth) 1405 { 1406 struct ucc_fast_private *uccf; 1407 u32 cecr_subblock; 1408 u32 temp; 1409 int i = 10; 1410 1411 uccf = ugeth->uccf; 1412 1413 /* Mask GRACEFUL STOP TX interrupt bit and clear it */ 1414 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA); 1415 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */ 1416 1417 /* Issue host command */ 1418 cecr_subblock = 1419 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1420 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, 1421 QE_CR_PROTOCOL_ETHERNET, 0); 1422 1423 /* Wait for command to complete */ 1424 do { 1425 msleep(10); 1426 temp = in_be32(uccf->p_ucce); 1427 } while (!(temp & UCC_GETH_UCCE_GRA) && --i); 1428 1429 uccf->stopped_tx = 1; 1430 1431 return 0; 1432 } 1433 1434 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth) 1435 { 1436 struct ucc_fast_private *uccf; 1437 u32 cecr_subblock; 1438 u8 temp; 1439 int i = 10; 1440 1441 uccf = ugeth->uccf; 1442 1443 /* Clear acknowledge bit */ 1444 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1445 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; 1446 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp); 1447 1448 /* Keep issuing command and checking acknowledge bit until 1449 it is asserted, according to spec */ 1450 do { 1451 /* Issue host command */ 1452 cecr_subblock = 1453 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info. 1454 ucc_num); 1455 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, 1456 QE_CR_PROTOCOL_ETHERNET, 0); 1457 msleep(10); 1458 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack); 1459 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i); 1460 1461 uccf->stopped_rx = 1; 1462 1463 return 0; 1464 } 1465 1466 static int ugeth_restart_tx(struct ucc_geth_private *ugeth) 1467 { 1468 struct ucc_fast_private *uccf; 1469 u32 cecr_subblock; 1470 1471 uccf = ugeth->uccf; 1472 1473 cecr_subblock = 1474 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1475 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0); 1476 uccf->stopped_tx = 0; 1477 1478 return 0; 1479 } 1480 1481 static int ugeth_restart_rx(struct ucc_geth_private *ugeth) 1482 { 1483 struct ucc_fast_private *uccf; 1484 u32 cecr_subblock; 1485 1486 uccf = ugeth->uccf; 1487 1488 cecr_subblock = 1489 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 1490 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 1491 0); 1492 uccf->stopped_rx = 0; 1493 1494 return 0; 1495 } 1496 1497 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1498 { 1499 struct ucc_fast_private *uccf; 1500 int enabled_tx, enabled_rx; 1501 1502 uccf = ugeth->uccf; 1503 1504 /* check if the UCC number is in range. */ 1505 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1506 if (netif_msg_probe(ugeth)) 1507 pr_err("ucc_num out of range\n"); 1508 return -EINVAL; 1509 } 1510 1511 enabled_tx = uccf->enabled_tx; 1512 enabled_rx = uccf->enabled_rx; 1513 1514 /* Get Tx and Rx going again, in case this channel was actively 1515 disabled. */ 1516 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx) 1517 ugeth_restart_tx(ugeth); 1518 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx) 1519 ugeth_restart_rx(ugeth); 1520 1521 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */ 1522 1523 return 0; 1524 1525 } 1526 1527 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode) 1528 { 1529 struct ucc_fast_private *uccf; 1530 1531 uccf = ugeth->uccf; 1532 1533 /* check if the UCC number is in range. */ 1534 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) { 1535 if (netif_msg_probe(ugeth)) 1536 pr_err("ucc_num out of range\n"); 1537 return -EINVAL; 1538 } 1539 1540 /* Stop any transmissions */ 1541 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx) 1542 ugeth_graceful_stop_tx(ugeth); 1543 1544 /* Stop any receptions */ 1545 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx) 1546 ugeth_graceful_stop_rx(ugeth); 1547 1548 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */ 1549 1550 return 0; 1551 } 1552 1553 static void ugeth_quiesce(struct ucc_geth_private *ugeth) 1554 { 1555 /* Prevent any further xmits, plus detach the device. */ 1556 netif_device_detach(ugeth->ndev); 1557 1558 /* Wait for any current xmits to finish. */ 1559 netif_tx_disable(ugeth->ndev); 1560 1561 /* Disable the interrupt to avoid NAPI rescheduling. */ 1562 disable_irq(ugeth->ug_info->uf_info.irq); 1563 1564 /* Stop NAPI, and possibly wait for its completion. */ 1565 napi_disable(&ugeth->napi); 1566 } 1567 1568 static void ugeth_activate(struct ucc_geth_private *ugeth) 1569 { 1570 napi_enable(&ugeth->napi); 1571 enable_irq(ugeth->ug_info->uf_info.irq); 1572 netif_device_attach(ugeth->ndev); 1573 } 1574 1575 /* Called every time the controller might need to be made 1576 * aware of new link state. The PHY code conveys this 1577 * information through variables in the ugeth structure, and this 1578 * function converts those variables into the appropriate 1579 * register values, and can bring down the device if needed. 1580 */ 1581 1582 static void adjust_link(struct net_device *dev) 1583 { 1584 struct ucc_geth_private *ugeth = netdev_priv(dev); 1585 struct ucc_geth __iomem *ug_regs; 1586 struct ucc_fast __iomem *uf_regs; 1587 struct phy_device *phydev = ugeth->phydev; 1588 int new_state = 0; 1589 1590 ug_regs = ugeth->ug_regs; 1591 uf_regs = ugeth->uccf->uf_regs; 1592 1593 if (phydev->link) { 1594 u32 tempval = in_be32(&ug_regs->maccfg2); 1595 u32 upsmr = in_be32(&uf_regs->upsmr); 1596 /* Now we make sure that we can be in full duplex mode. 1597 * If not, we operate in half-duplex mode. */ 1598 if (phydev->duplex != ugeth->oldduplex) { 1599 new_state = 1; 1600 if (!(phydev->duplex)) 1601 tempval &= ~(MACCFG2_FDX); 1602 else 1603 tempval |= MACCFG2_FDX; 1604 ugeth->oldduplex = phydev->duplex; 1605 } 1606 1607 if (phydev->speed != ugeth->oldspeed) { 1608 new_state = 1; 1609 switch (phydev->speed) { 1610 case SPEED_1000: 1611 tempval = ((tempval & 1612 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1613 MACCFG2_INTERFACE_MODE_BYTE); 1614 break; 1615 case SPEED_100: 1616 case SPEED_10: 1617 tempval = ((tempval & 1618 ~(MACCFG2_INTERFACE_MODE_MASK)) | 1619 MACCFG2_INTERFACE_MODE_NIBBLE); 1620 /* if reduced mode, re-set UPSMR.R10M */ 1621 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) || 1622 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) || 1623 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || 1624 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1625 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) || 1626 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) { 1627 if (phydev->speed == SPEED_10) 1628 upsmr |= UCC_GETH_UPSMR_R10M; 1629 else 1630 upsmr &= ~UCC_GETH_UPSMR_R10M; 1631 } 1632 break; 1633 default: 1634 if (netif_msg_link(ugeth)) 1635 pr_warn( 1636 "%s: Ack! Speed (%d) is not 10/100/1000!", 1637 dev->name, phydev->speed); 1638 break; 1639 } 1640 ugeth->oldspeed = phydev->speed; 1641 } 1642 1643 if (!ugeth->oldlink) { 1644 new_state = 1; 1645 ugeth->oldlink = 1; 1646 } 1647 1648 if (new_state) { 1649 /* 1650 * To change the MAC configuration we need to disable 1651 * the controller. To do so, we have to either grab 1652 * ugeth->lock, which is a bad idea since 'graceful 1653 * stop' commands might take quite a while, or we can 1654 * quiesce driver's activity. 1655 */ 1656 ugeth_quiesce(ugeth); 1657 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 1658 1659 out_be32(&ug_regs->maccfg2, tempval); 1660 out_be32(&uf_regs->upsmr, upsmr); 1661 1662 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 1663 ugeth_activate(ugeth); 1664 } 1665 } else if (ugeth->oldlink) { 1666 new_state = 1; 1667 ugeth->oldlink = 0; 1668 ugeth->oldspeed = 0; 1669 ugeth->oldduplex = -1; 1670 } 1671 1672 if (new_state && netif_msg_link(ugeth)) 1673 phy_print_status(phydev); 1674 } 1675 1676 /* Initialize TBI PHY interface for communicating with the 1677 * SERDES lynx PHY on the chip. We communicate with this PHY 1678 * through the MDIO bus on each controller, treating it as a 1679 * "normal" PHY at the address found in the UTBIPA register. We assume 1680 * that the UTBIPA register is valid. Either the MDIO bus code will set 1681 * it to a value that doesn't conflict with other PHYs on the bus, or the 1682 * value doesn't matter, as there are no other PHYs on the bus. 1683 */ 1684 static void uec_configure_serdes(struct net_device *dev) 1685 { 1686 struct ucc_geth_private *ugeth = netdev_priv(dev); 1687 struct ucc_geth_info *ug_info = ugeth->ug_info; 1688 struct phy_device *tbiphy; 1689 1690 if (!ug_info->tbi_node) { 1691 dev_warn(&dev->dev, "SGMII mode requires that the device " 1692 "tree specify a tbi-handle\n"); 1693 return; 1694 } 1695 1696 tbiphy = of_phy_find_device(ug_info->tbi_node); 1697 if (!tbiphy) { 1698 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1699 return; 1700 } 1701 1702 /* 1703 * If the link is already up, we must already be ok, and don't need to 1704 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1705 * everything for us? Resetting it takes the link down and requires 1706 * several seconds for it to come back. 1707 */ 1708 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) { 1709 put_device(&tbiphy->mdio.dev); 1710 return; 1711 } 1712 1713 /* Single clk mode, mii mode off(for serdes communication) */ 1714 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); 1715 1716 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); 1717 1718 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); 1719 1720 put_device(&tbiphy->mdio.dev); 1721 } 1722 1723 /* Configure the PHY for dev. 1724 * returns 0 if success. -1 if failure 1725 */ 1726 static int init_phy(struct net_device *dev) 1727 { 1728 struct ucc_geth_private *priv = netdev_priv(dev); 1729 struct ucc_geth_info *ug_info = priv->ug_info; 1730 struct phy_device *phydev; 1731 1732 priv->oldlink = 0; 1733 priv->oldspeed = 0; 1734 priv->oldduplex = -1; 1735 1736 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0, 1737 priv->phy_interface); 1738 if (!phydev) { 1739 dev_err(&dev->dev, "Could not attach to PHY\n"); 1740 return -ENODEV; 1741 } 1742 1743 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) 1744 uec_configure_serdes(dev); 1745 1746 phy_set_max_speed(phydev, priv->max_speed); 1747 1748 priv->phydev = phydev; 1749 1750 return 0; 1751 } 1752 1753 static void ugeth_dump_regs(struct ucc_geth_private *ugeth) 1754 { 1755 #ifdef DEBUG 1756 ucc_fast_dump_regs(ugeth->uccf); 1757 dump_regs(ugeth); 1758 dump_bds(ugeth); 1759 #endif 1760 } 1761 1762 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private * 1763 ugeth, 1764 enum enet_addr_type 1765 enet_addr_type) 1766 { 1767 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 1768 struct ucc_fast_private *uccf; 1769 enum comm_dir comm_dir; 1770 struct list_head *p_lh; 1771 u16 i, num; 1772 u32 __iomem *addr_h; 1773 u32 __iomem *addr_l; 1774 u8 *p_counter; 1775 1776 uccf = ugeth->uccf; 1777 1778 p_82xx_addr_filt = 1779 (struct ucc_geth_82xx_address_filtering_pram __iomem *) 1780 ugeth->p_rx_glbl_pram->addressfiltering; 1781 1782 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) { 1783 addr_h = &(p_82xx_addr_filt->gaddr_h); 1784 addr_l = &(p_82xx_addr_filt->gaddr_l); 1785 p_lh = &ugeth->group_hash_q; 1786 p_counter = &(ugeth->numGroupAddrInHash); 1787 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) { 1788 addr_h = &(p_82xx_addr_filt->iaddr_h); 1789 addr_l = &(p_82xx_addr_filt->iaddr_l); 1790 p_lh = &ugeth->ind_hash_q; 1791 p_counter = &(ugeth->numIndAddrInHash); 1792 } else 1793 return -EINVAL; 1794 1795 comm_dir = 0; 1796 if (uccf->enabled_tx) 1797 comm_dir |= COMM_DIR_TX; 1798 if (uccf->enabled_rx) 1799 comm_dir |= COMM_DIR_RX; 1800 if (comm_dir) 1801 ugeth_disable(ugeth, comm_dir); 1802 1803 /* Clear the hash table. */ 1804 out_be32(addr_h, 0x00000000); 1805 out_be32(addr_l, 0x00000000); 1806 1807 if (!p_lh) 1808 return 0; 1809 1810 num = *p_counter; 1811 1812 /* Delete all remaining CQ elements */ 1813 for (i = 0; i < num; i++) 1814 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh))); 1815 1816 *p_counter = 0; 1817 1818 if (comm_dir) 1819 ugeth_enable(ugeth, comm_dir); 1820 1821 return 0; 1822 } 1823 1824 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth, 1825 u8 paddr_num) 1826 { 1827 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */ 1828 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */ 1829 } 1830 1831 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth) 1832 { 1833 struct ucc_geth_info *ug_info; 1834 struct ucc_fast_info *uf_info; 1835 u16 i, j; 1836 u8 __iomem *bd; 1837 1838 1839 ug_info = ugeth->ug_info; 1840 uf_info = &ug_info->uf_info; 1841 1842 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) { 1843 if (ugeth->p_rx_bd_ring[i]) { 1844 /* Return existing data buffers in ring */ 1845 bd = ugeth->p_rx_bd_ring[i]; 1846 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) { 1847 if (ugeth->rx_skbuff[i][j]) { 1848 dma_unmap_single(ugeth->dev, 1849 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1850 ugeth->ug_info-> 1851 uf_info.max_rx_buf_length + 1852 UCC_GETH_RX_DATA_BUF_ALIGNMENT, 1853 DMA_FROM_DEVICE); 1854 dev_kfree_skb_any( 1855 ugeth->rx_skbuff[i][j]); 1856 ugeth->rx_skbuff[i][j] = NULL; 1857 } 1858 bd += sizeof(struct qe_bd); 1859 } 1860 1861 kfree(ugeth->rx_skbuff[i]); 1862 1863 if (ugeth->ug_info->uf_info.bd_mem_part == 1864 MEM_PART_SYSTEM) 1865 kfree((void *)ugeth->rx_bd_ring_offset[i]); 1866 else if (ugeth->ug_info->uf_info.bd_mem_part == 1867 MEM_PART_MURAM) 1868 qe_muram_free(ugeth->rx_bd_ring_offset[i]); 1869 ugeth->p_rx_bd_ring[i] = NULL; 1870 } 1871 } 1872 1873 } 1874 1875 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth) 1876 { 1877 struct ucc_geth_info *ug_info; 1878 struct ucc_fast_info *uf_info; 1879 u16 i, j; 1880 u8 __iomem *bd; 1881 1882 ug_info = ugeth->ug_info; 1883 uf_info = &ug_info->uf_info; 1884 1885 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) { 1886 bd = ugeth->p_tx_bd_ring[i]; 1887 if (!bd) 1888 continue; 1889 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) { 1890 if (ugeth->tx_skbuff[i][j]) { 1891 dma_unmap_single(ugeth->dev, 1892 in_be32(&((struct qe_bd __iomem *)bd)->buf), 1893 (in_be32((u32 __iomem *)bd) & 1894 BD_LENGTH_MASK), 1895 DMA_TO_DEVICE); 1896 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]); 1897 ugeth->tx_skbuff[i][j] = NULL; 1898 } 1899 } 1900 1901 kfree(ugeth->tx_skbuff[i]); 1902 1903 if (ugeth->p_tx_bd_ring[i]) { 1904 if (ugeth->ug_info->uf_info.bd_mem_part == 1905 MEM_PART_SYSTEM) 1906 kfree((void *)ugeth->tx_bd_ring_offset[i]); 1907 else if (ugeth->ug_info->uf_info.bd_mem_part == 1908 MEM_PART_MURAM) 1909 qe_muram_free(ugeth->tx_bd_ring_offset[i]); 1910 ugeth->p_tx_bd_ring[i] = NULL; 1911 } 1912 } 1913 1914 } 1915 1916 static void ucc_geth_memclean(struct ucc_geth_private *ugeth) 1917 { 1918 if (!ugeth) 1919 return; 1920 1921 if (ugeth->uccf) { 1922 ucc_fast_free(ugeth->uccf); 1923 ugeth->uccf = NULL; 1924 } 1925 1926 if (ugeth->p_thread_data_tx) { 1927 qe_muram_free(ugeth->thread_dat_tx_offset); 1928 ugeth->p_thread_data_tx = NULL; 1929 } 1930 if (ugeth->p_thread_data_rx) { 1931 qe_muram_free(ugeth->thread_dat_rx_offset); 1932 ugeth->p_thread_data_rx = NULL; 1933 } 1934 if (ugeth->p_exf_glbl_param) { 1935 qe_muram_free(ugeth->exf_glbl_param_offset); 1936 ugeth->p_exf_glbl_param = NULL; 1937 } 1938 if (ugeth->p_rx_glbl_pram) { 1939 qe_muram_free(ugeth->rx_glbl_pram_offset); 1940 ugeth->p_rx_glbl_pram = NULL; 1941 } 1942 if (ugeth->p_tx_glbl_pram) { 1943 qe_muram_free(ugeth->tx_glbl_pram_offset); 1944 ugeth->p_tx_glbl_pram = NULL; 1945 } 1946 if (ugeth->p_send_q_mem_reg) { 1947 qe_muram_free(ugeth->send_q_mem_reg_offset); 1948 ugeth->p_send_q_mem_reg = NULL; 1949 } 1950 if (ugeth->p_scheduler) { 1951 qe_muram_free(ugeth->scheduler_offset); 1952 ugeth->p_scheduler = NULL; 1953 } 1954 if (ugeth->p_tx_fw_statistics_pram) { 1955 qe_muram_free(ugeth->tx_fw_statistics_pram_offset); 1956 ugeth->p_tx_fw_statistics_pram = NULL; 1957 } 1958 if (ugeth->p_rx_fw_statistics_pram) { 1959 qe_muram_free(ugeth->rx_fw_statistics_pram_offset); 1960 ugeth->p_rx_fw_statistics_pram = NULL; 1961 } 1962 if (ugeth->p_rx_irq_coalescing_tbl) { 1963 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset); 1964 ugeth->p_rx_irq_coalescing_tbl = NULL; 1965 } 1966 if (ugeth->p_rx_bd_qs_tbl) { 1967 qe_muram_free(ugeth->rx_bd_qs_tbl_offset); 1968 ugeth->p_rx_bd_qs_tbl = NULL; 1969 } 1970 if (ugeth->p_init_enet_param_shadow) { 1971 return_init_enet_entries(ugeth, 1972 &(ugeth->p_init_enet_param_shadow-> 1973 rxthread[0]), 1974 ENET_INIT_PARAM_MAX_ENTRIES_RX, 1975 ugeth->ug_info->riscRx, 1); 1976 return_init_enet_entries(ugeth, 1977 &(ugeth->p_init_enet_param_shadow-> 1978 txthread[0]), 1979 ENET_INIT_PARAM_MAX_ENTRIES_TX, 1980 ugeth->ug_info->riscTx, 0); 1981 kfree(ugeth->p_init_enet_param_shadow); 1982 ugeth->p_init_enet_param_shadow = NULL; 1983 } 1984 ucc_geth_free_tx(ugeth); 1985 ucc_geth_free_rx(ugeth); 1986 while (!list_empty(&ugeth->group_hash_q)) 1987 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1988 (dequeue(&ugeth->group_hash_q))); 1989 while (!list_empty(&ugeth->ind_hash_q)) 1990 put_enet_addr_container(ENET_ADDR_CONT_ENTRY 1991 (dequeue(&ugeth->ind_hash_q))); 1992 if (ugeth->ug_regs) { 1993 iounmap(ugeth->ug_regs); 1994 ugeth->ug_regs = NULL; 1995 } 1996 } 1997 1998 static void ucc_geth_set_multi(struct net_device *dev) 1999 { 2000 struct ucc_geth_private *ugeth; 2001 struct netdev_hw_addr *ha; 2002 struct ucc_fast __iomem *uf_regs; 2003 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2004 2005 ugeth = netdev_priv(dev); 2006 2007 uf_regs = ugeth->uccf->uf_regs; 2008 2009 if (dev->flags & IFF_PROMISC) { 2010 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2011 } else { 2012 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO); 2013 2014 p_82xx_addr_filt = 2015 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2016 p_rx_glbl_pram->addressfiltering; 2017 2018 if (dev->flags & IFF_ALLMULTI) { 2019 /* Catch all multicast addresses, so set the 2020 * filter to all 1's. 2021 */ 2022 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff); 2023 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff); 2024 } else { 2025 /* Clear filter and add the addresses in the list. 2026 */ 2027 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0); 2028 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0); 2029 2030 netdev_for_each_mc_addr(ha, dev) { 2031 /* Ask CPM to run CRC and set bit in 2032 * filter mask. 2033 */ 2034 hw_add_addr_in_hash(ugeth, ha->addr); 2035 } 2036 } 2037 } 2038 } 2039 2040 static void ucc_geth_stop(struct ucc_geth_private *ugeth) 2041 { 2042 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs; 2043 struct phy_device *phydev = ugeth->phydev; 2044 2045 ugeth_vdbg("%s: IN", __func__); 2046 2047 /* 2048 * Tell the kernel the link is down. 2049 * Must be done before disabling the controller 2050 * or deadlock may happen. 2051 */ 2052 phy_stop(phydev); 2053 2054 /* Disable the controller */ 2055 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 2056 2057 /* Mask all interrupts */ 2058 out_be32(ugeth->uccf->p_uccm, 0x00000000); 2059 2060 /* Clear all interrupts */ 2061 out_be32(ugeth->uccf->p_ucce, 0xffffffff); 2062 2063 /* Disable Rx and Tx */ 2064 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2065 2066 ucc_geth_memclean(ugeth); 2067 } 2068 2069 static int ucc_struct_init(struct ucc_geth_private *ugeth) 2070 { 2071 struct ucc_geth_info *ug_info; 2072 struct ucc_fast_info *uf_info; 2073 int i; 2074 2075 ug_info = ugeth->ug_info; 2076 uf_info = &ug_info->uf_info; 2077 2078 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) || 2079 (uf_info->bd_mem_part == MEM_PART_MURAM))) { 2080 if (netif_msg_probe(ugeth)) 2081 pr_err("Bad memory partition value\n"); 2082 return -EINVAL; 2083 } 2084 2085 /* Rx BD lengths */ 2086 for (i = 0; i < ug_info->numQueuesRx; i++) { 2087 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) || 2088 (ug_info->bdRingLenRx[i] % 2089 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) { 2090 if (netif_msg_probe(ugeth)) 2091 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n"); 2092 return -EINVAL; 2093 } 2094 } 2095 2096 /* Tx BD lengths */ 2097 for (i = 0; i < ug_info->numQueuesTx; i++) { 2098 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) { 2099 if (netif_msg_probe(ugeth)) 2100 pr_err("Tx BD ring length must be no smaller than 2\n"); 2101 return -EINVAL; 2102 } 2103 } 2104 2105 /* mrblr */ 2106 if ((uf_info->max_rx_buf_length == 0) || 2107 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) { 2108 if (netif_msg_probe(ugeth)) 2109 pr_err("max_rx_buf_length must be non-zero multiple of 128\n"); 2110 return -EINVAL; 2111 } 2112 2113 /* num Tx queues */ 2114 if (ug_info->numQueuesTx > NUM_TX_QUEUES) { 2115 if (netif_msg_probe(ugeth)) 2116 pr_err("number of tx queues too large\n"); 2117 return -EINVAL; 2118 } 2119 2120 /* num Rx queues */ 2121 if (ug_info->numQueuesRx > NUM_RX_QUEUES) { 2122 if (netif_msg_probe(ugeth)) 2123 pr_err("number of rx queues too large\n"); 2124 return -EINVAL; 2125 } 2126 2127 /* l2qt */ 2128 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) { 2129 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) { 2130 if (netif_msg_probe(ugeth)) 2131 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n"); 2132 return -EINVAL; 2133 } 2134 } 2135 2136 /* l3qt */ 2137 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) { 2138 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) { 2139 if (netif_msg_probe(ugeth)) 2140 pr_err("IP priority table entry must not be larger than number of Rx queues\n"); 2141 return -EINVAL; 2142 } 2143 } 2144 2145 if (ug_info->cam && !ug_info->ecamptr) { 2146 if (netif_msg_probe(ugeth)) 2147 pr_err("If cam mode is chosen, must supply cam ptr\n"); 2148 return -EINVAL; 2149 } 2150 2151 if ((ug_info->numStationAddresses != 2152 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) && 2153 ug_info->rxExtendedFiltering) { 2154 if (netif_msg_probe(ugeth)) 2155 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n"); 2156 return -EINVAL; 2157 } 2158 2159 /* Generate uccm_mask for receive */ 2160 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */ 2161 for (i = 0; i < ug_info->numQueuesRx; i++) 2162 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i); 2163 2164 for (i = 0; i < ug_info->numQueuesTx; i++) 2165 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i); 2166 /* Initialize the general fast UCC block. */ 2167 if (ucc_fast_init(uf_info, &ugeth->uccf)) { 2168 if (netif_msg_probe(ugeth)) 2169 pr_err("Failed to init uccf\n"); 2170 return -ENOMEM; 2171 } 2172 2173 /* read the number of risc engines, update the riscTx and riscRx 2174 * if there are 4 riscs in QE 2175 */ 2176 if (qe_get_num_of_risc() == 4) { 2177 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; 2178 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; 2179 } 2180 2181 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); 2182 if (!ugeth->ug_regs) { 2183 if (netif_msg_probe(ugeth)) 2184 pr_err("Failed to ioremap regs\n"); 2185 return -ENOMEM; 2186 } 2187 2188 return 0; 2189 } 2190 2191 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth) 2192 { 2193 struct ucc_geth_info *ug_info; 2194 struct ucc_fast_info *uf_info; 2195 int length; 2196 u16 i, j; 2197 u8 __iomem *bd; 2198 2199 ug_info = ugeth->ug_info; 2200 uf_info = &ug_info->uf_info; 2201 2202 /* Allocate Tx bds */ 2203 for (j = 0; j < ug_info->numQueuesTx; j++) { 2204 /* Allocate in multiple of 2205 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT, 2206 according to spec */ 2207 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) 2208 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2209 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2210 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) % 2211 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) 2212 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; 2213 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2214 u32 align = 4; 2215 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4) 2216 align = UCC_GETH_TX_BD_RING_ALIGNMENT; 2217 ugeth->tx_bd_ring_offset[j] = 2218 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2219 2220 if (ugeth->tx_bd_ring_offset[j] != 0) 2221 ugeth->p_tx_bd_ring[j] = 2222 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] + 2223 align) & ~(align - 1)); 2224 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2225 ugeth->tx_bd_ring_offset[j] = 2226 qe_muram_alloc(length, 2227 UCC_GETH_TX_BD_RING_ALIGNMENT); 2228 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j])) 2229 ugeth->p_tx_bd_ring[j] = 2230 (u8 __iomem *) qe_muram_addr(ugeth-> 2231 tx_bd_ring_offset[j]); 2232 } 2233 if (!ugeth->p_tx_bd_ring[j]) { 2234 if (netif_msg_ifup(ugeth)) 2235 pr_err("Can not allocate memory for Tx bd rings\n"); 2236 return -ENOMEM; 2237 } 2238 /* Zero unused end of bd ring, according to spec */ 2239 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] + 2240 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0, 2241 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)); 2242 } 2243 2244 /* Init Tx bds */ 2245 for (j = 0; j < ug_info->numQueuesTx; j++) { 2246 /* Setup the skbuff rings */ 2247 ugeth->tx_skbuff[j] = 2248 kmalloc_array(ugeth->ug_info->bdRingLenTx[j], 2249 sizeof(struct sk_buff *), GFP_KERNEL); 2250 2251 if (ugeth->tx_skbuff[j] == NULL) { 2252 if (netif_msg_ifup(ugeth)) 2253 pr_err("Could not allocate tx_skbuff\n"); 2254 return -ENOMEM; 2255 } 2256 2257 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++) 2258 ugeth->tx_skbuff[j][i] = NULL; 2259 2260 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0; 2261 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j]; 2262 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) { 2263 /* clear bd buffer */ 2264 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2265 /* set bd status and length */ 2266 out_be32((u32 __iomem *)bd, 0); 2267 bd += sizeof(struct qe_bd); 2268 } 2269 bd -= sizeof(struct qe_bd); 2270 /* set bd status and length */ 2271 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */ 2272 } 2273 2274 return 0; 2275 } 2276 2277 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth) 2278 { 2279 struct ucc_geth_info *ug_info; 2280 struct ucc_fast_info *uf_info; 2281 int length; 2282 u16 i, j; 2283 u8 __iomem *bd; 2284 2285 ug_info = ugeth->ug_info; 2286 uf_info = &ug_info->uf_info; 2287 2288 /* Allocate Rx bds */ 2289 for (j = 0; j < ug_info->numQueuesRx; j++) { 2290 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd); 2291 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) { 2292 u32 align = 4; 2293 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4) 2294 align = UCC_GETH_RX_BD_RING_ALIGNMENT; 2295 ugeth->rx_bd_ring_offset[j] = 2296 (u32) kmalloc((u32) (length + align), GFP_KERNEL); 2297 if (ugeth->rx_bd_ring_offset[j] != 0) 2298 ugeth->p_rx_bd_ring[j] = 2299 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] + 2300 align) & ~(align - 1)); 2301 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) { 2302 ugeth->rx_bd_ring_offset[j] = 2303 qe_muram_alloc(length, 2304 UCC_GETH_RX_BD_RING_ALIGNMENT); 2305 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j])) 2306 ugeth->p_rx_bd_ring[j] = 2307 (u8 __iomem *) qe_muram_addr(ugeth-> 2308 rx_bd_ring_offset[j]); 2309 } 2310 if (!ugeth->p_rx_bd_ring[j]) { 2311 if (netif_msg_ifup(ugeth)) 2312 pr_err("Can not allocate memory for Rx bd rings\n"); 2313 return -ENOMEM; 2314 } 2315 } 2316 2317 /* Init Rx bds */ 2318 for (j = 0; j < ug_info->numQueuesRx; j++) { 2319 /* Setup the skbuff rings */ 2320 ugeth->rx_skbuff[j] = 2321 kmalloc_array(ugeth->ug_info->bdRingLenRx[j], 2322 sizeof(struct sk_buff *), GFP_KERNEL); 2323 2324 if (ugeth->rx_skbuff[j] == NULL) { 2325 if (netif_msg_ifup(ugeth)) 2326 pr_err("Could not allocate rx_skbuff\n"); 2327 return -ENOMEM; 2328 } 2329 2330 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++) 2331 ugeth->rx_skbuff[j][i] = NULL; 2332 2333 ugeth->skb_currx[j] = 0; 2334 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j]; 2335 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) { 2336 /* set bd status and length */ 2337 out_be32((u32 __iomem *)bd, R_I); 2338 /* clear bd buffer */ 2339 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0); 2340 bd += sizeof(struct qe_bd); 2341 } 2342 bd -= sizeof(struct qe_bd); 2343 /* set bd status and length */ 2344 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */ 2345 } 2346 2347 return 0; 2348 } 2349 2350 static int ucc_geth_startup(struct ucc_geth_private *ugeth) 2351 { 2352 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt; 2353 struct ucc_geth_init_pram __iomem *p_init_enet_pram; 2354 struct ucc_fast_private *uccf; 2355 struct ucc_geth_info *ug_info; 2356 struct ucc_fast_info *uf_info; 2357 struct ucc_fast __iomem *uf_regs; 2358 struct ucc_geth __iomem *ug_regs; 2359 int ret_val = -EINVAL; 2360 u32 remoder = UCC_GETH_REMODER_INIT; 2361 u32 init_enet_pram_offset, cecr_subblock, command; 2362 u32 ifstat, i, j, size, l2qt, l3qt; 2363 u16 temoder = UCC_GETH_TEMODER_INIT; 2364 u16 test; 2365 u8 function_code = 0; 2366 u8 __iomem *endOfRing; 2367 u8 numThreadsRxNumerical, numThreadsTxNumerical; 2368 2369 ugeth_vdbg("%s: IN", __func__); 2370 uccf = ugeth->uccf; 2371 ug_info = ugeth->ug_info; 2372 uf_info = &ug_info->uf_info; 2373 uf_regs = uccf->uf_regs; 2374 ug_regs = ugeth->ug_regs; 2375 2376 switch (ug_info->numThreadsRx) { 2377 case UCC_GETH_NUM_OF_THREADS_1: 2378 numThreadsRxNumerical = 1; 2379 break; 2380 case UCC_GETH_NUM_OF_THREADS_2: 2381 numThreadsRxNumerical = 2; 2382 break; 2383 case UCC_GETH_NUM_OF_THREADS_4: 2384 numThreadsRxNumerical = 4; 2385 break; 2386 case UCC_GETH_NUM_OF_THREADS_6: 2387 numThreadsRxNumerical = 6; 2388 break; 2389 case UCC_GETH_NUM_OF_THREADS_8: 2390 numThreadsRxNumerical = 8; 2391 break; 2392 default: 2393 if (netif_msg_ifup(ugeth)) 2394 pr_err("Bad number of Rx threads value\n"); 2395 return -EINVAL; 2396 } 2397 2398 switch (ug_info->numThreadsTx) { 2399 case UCC_GETH_NUM_OF_THREADS_1: 2400 numThreadsTxNumerical = 1; 2401 break; 2402 case UCC_GETH_NUM_OF_THREADS_2: 2403 numThreadsTxNumerical = 2; 2404 break; 2405 case UCC_GETH_NUM_OF_THREADS_4: 2406 numThreadsTxNumerical = 4; 2407 break; 2408 case UCC_GETH_NUM_OF_THREADS_6: 2409 numThreadsTxNumerical = 6; 2410 break; 2411 case UCC_GETH_NUM_OF_THREADS_8: 2412 numThreadsTxNumerical = 8; 2413 break; 2414 default: 2415 if (netif_msg_ifup(ugeth)) 2416 pr_err("Bad number of Tx threads value\n"); 2417 return -EINVAL; 2418 } 2419 2420 /* Calculate rx_extended_features */ 2421 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck || 2422 ug_info->ipAddressAlignment || 2423 (ug_info->numStationAddresses != 2424 UCC_GETH_NUM_OF_STATION_ADDRESSES_1); 2425 2426 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features || 2427 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) || 2428 (ug_info->vlanOperationNonTagged != 2429 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP); 2430 2431 init_default_reg_vals(&uf_regs->upsmr, 2432 &ug_regs->maccfg1, &ug_regs->maccfg2); 2433 2434 /* Set UPSMR */ 2435 /* For more details see the hardware spec. */ 2436 init_rx_parameters(ug_info->bro, 2437 ug_info->rsh, ug_info->pro, &uf_regs->upsmr); 2438 2439 /* We're going to ignore other registers for now, */ 2440 /* except as needed to get up and running */ 2441 2442 /* Set MACCFG1 */ 2443 /* For more details see the hardware spec. */ 2444 init_flow_control_params(ug_info->aufc, 2445 ug_info->receiveFlowControl, 2446 ug_info->transmitFlowControl, 2447 ug_info->pausePeriod, 2448 ug_info->extensionField, 2449 &uf_regs->upsmr, 2450 &ug_regs->uempr, &ug_regs->maccfg1); 2451 2452 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX); 2453 2454 /* Set IPGIFG */ 2455 /* For more details see the hardware spec. */ 2456 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1, 2457 ug_info->nonBackToBackIfgPart2, 2458 ug_info-> 2459 miminumInterFrameGapEnforcement, 2460 ug_info->backToBackInterFrameGap, 2461 &ug_regs->ipgifg); 2462 if (ret_val != 0) { 2463 if (netif_msg_ifup(ugeth)) 2464 pr_err("IPGIFG initialization parameter too large\n"); 2465 return ret_val; 2466 } 2467 2468 /* Set HAFDUP */ 2469 /* For more details see the hardware spec. */ 2470 ret_val = init_half_duplex_params(ug_info->altBeb, 2471 ug_info->backPressureNoBackoff, 2472 ug_info->noBackoff, 2473 ug_info->excessDefer, 2474 ug_info->altBebTruncation, 2475 ug_info->maxRetransmission, 2476 ug_info->collisionWindow, 2477 &ug_regs->hafdup); 2478 if (ret_val != 0) { 2479 if (netif_msg_ifup(ugeth)) 2480 pr_err("Half Duplex initialization parameter too large\n"); 2481 return ret_val; 2482 } 2483 2484 /* Set IFSTAT */ 2485 /* For more details see the hardware spec. */ 2486 /* Read only - resets upon read */ 2487 ifstat = in_be32(&ug_regs->ifstat); 2488 2489 /* Clear UEMPR */ 2490 /* For more details see the hardware spec. */ 2491 out_be32(&ug_regs->uempr, 0); 2492 2493 /* Set UESCR */ 2494 /* For more details see the hardware spec. */ 2495 init_hw_statistics_gathering_mode((ug_info->statisticsMode & 2496 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE), 2497 0, &uf_regs->upsmr, &ug_regs->uescr); 2498 2499 ret_val = ucc_geth_alloc_tx(ugeth); 2500 if (ret_val != 0) 2501 return ret_val; 2502 2503 ret_val = ucc_geth_alloc_rx(ugeth); 2504 if (ret_val != 0) 2505 return ret_val; 2506 2507 /* 2508 * Global PRAM 2509 */ 2510 /* Tx global PRAM */ 2511 /* Allocate global tx parameter RAM page */ 2512 ugeth->tx_glbl_pram_offset = 2513 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram), 2514 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT); 2515 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) { 2516 if (netif_msg_ifup(ugeth)) 2517 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n"); 2518 return -ENOMEM; 2519 } 2520 ugeth->p_tx_glbl_pram = 2521 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth-> 2522 tx_glbl_pram_offset); 2523 /* Zero out p_tx_glbl_pram */ 2524 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram)); 2525 2526 /* Fill global PRAM */ 2527 2528 /* TQPTR */ 2529 /* Size varies with number of Tx threads */ 2530 ugeth->thread_dat_tx_offset = 2531 qe_muram_alloc(numThreadsTxNumerical * 2532 sizeof(struct ucc_geth_thread_data_tx) + 2533 32 * (numThreadsTxNumerical == 1), 2534 UCC_GETH_THREAD_DATA_ALIGNMENT); 2535 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) { 2536 if (netif_msg_ifup(ugeth)) 2537 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n"); 2538 return -ENOMEM; 2539 } 2540 2541 ugeth->p_thread_data_tx = 2542 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth-> 2543 thread_dat_tx_offset); 2544 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset); 2545 2546 /* vtagtable */ 2547 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++) 2548 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i], 2549 ug_info->vtagtable[i]); 2550 2551 /* iphoffset */ 2552 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++) 2553 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i], 2554 ug_info->iphoffset[i]); 2555 2556 /* SQPTR */ 2557 /* Size varies with number of Tx queues */ 2558 ugeth->send_q_mem_reg_offset = 2559 qe_muram_alloc(ug_info->numQueuesTx * 2560 sizeof(struct ucc_geth_send_queue_qd), 2561 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); 2562 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) { 2563 if (netif_msg_ifup(ugeth)) 2564 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n"); 2565 return -ENOMEM; 2566 } 2567 2568 ugeth->p_send_q_mem_reg = 2569 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth-> 2570 send_q_mem_reg_offset); 2571 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset); 2572 2573 /* Setup the table */ 2574 /* Assume BD rings are already established */ 2575 for (i = 0; i < ug_info->numQueuesTx; i++) { 2576 endOfRing = 2577 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] - 2578 1) * sizeof(struct qe_bd); 2579 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2580 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2581 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i])); 2582 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2583 last_bd_completed_address, 2584 (u32) virt_to_phys(endOfRing)); 2585 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2586 MEM_PART_MURAM) { 2587 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base, 2588 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i])); 2589 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i]. 2590 last_bd_completed_address, 2591 (u32)qe_muram_dma(endOfRing)); 2592 } 2593 } 2594 2595 /* schedulerbasepointer */ 2596 2597 if (ug_info->numQueuesTx > 1) { 2598 /* scheduler exists only if more than 1 tx queue */ 2599 ugeth->scheduler_offset = 2600 qe_muram_alloc(sizeof(struct ucc_geth_scheduler), 2601 UCC_GETH_SCHEDULER_ALIGNMENT); 2602 if (IS_ERR_VALUE(ugeth->scheduler_offset)) { 2603 if (netif_msg_ifup(ugeth)) 2604 pr_err("Can not allocate DPRAM memory for p_scheduler\n"); 2605 return -ENOMEM; 2606 } 2607 2608 ugeth->p_scheduler = 2609 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth-> 2610 scheduler_offset); 2611 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer, 2612 ugeth->scheduler_offset); 2613 /* Zero out p_scheduler */ 2614 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler)); 2615 2616 /* Set values in scheduler */ 2617 out_be32(&ugeth->p_scheduler->mblinterval, 2618 ug_info->mblinterval); 2619 out_be16(&ugeth->p_scheduler->nortsrbytetime, 2620 ug_info->nortsrbytetime); 2621 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz); 2622 out_8(&ugeth->p_scheduler->strictpriorityq, 2623 ug_info->strictpriorityq); 2624 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap); 2625 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw); 2626 for (i = 0; i < NUM_TX_QUEUES; i++) 2627 out_8(&ugeth->p_scheduler->weightfactor[i], 2628 ug_info->weightfactor[i]); 2629 2630 /* Set pointers to cpucount registers in scheduler */ 2631 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0); 2632 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1); 2633 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2); 2634 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3); 2635 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4); 2636 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5); 2637 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6); 2638 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7); 2639 } 2640 2641 /* schedulerbasepointer */ 2642 /* TxRMON_PTR (statistics) */ 2643 if (ug_info-> 2644 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) { 2645 ugeth->tx_fw_statistics_pram_offset = 2646 qe_muram_alloc(sizeof 2647 (struct ucc_geth_tx_firmware_statistics_pram), 2648 UCC_GETH_TX_STATISTICS_ALIGNMENT); 2649 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) { 2650 if (netif_msg_ifup(ugeth)) 2651 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n"); 2652 return -ENOMEM; 2653 } 2654 ugeth->p_tx_fw_statistics_pram = 2655 (struct ucc_geth_tx_firmware_statistics_pram __iomem *) 2656 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset); 2657 /* Zero out p_tx_fw_statistics_pram */ 2658 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram, 2659 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram)); 2660 } 2661 2662 /* temoder */ 2663 /* Already has speed set */ 2664 2665 if (ug_info->numQueuesTx > 1) 2666 temoder |= TEMODER_SCHEDULER_ENABLE; 2667 if (ug_info->ipCheckSumGenerate) 2668 temoder |= TEMODER_IP_CHECKSUM_GENERATE; 2669 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT); 2670 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder); 2671 2672 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2673 2674 /* Function code register value to be used later */ 2675 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL; 2676 /* Required for QE */ 2677 2678 /* function code register */ 2679 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24); 2680 2681 /* Rx global PRAM */ 2682 /* Allocate global rx parameter RAM page */ 2683 ugeth->rx_glbl_pram_offset = 2684 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram), 2685 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT); 2686 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) { 2687 if (netif_msg_ifup(ugeth)) 2688 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n"); 2689 return -ENOMEM; 2690 } 2691 ugeth->p_rx_glbl_pram = 2692 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth-> 2693 rx_glbl_pram_offset); 2694 /* Zero out p_rx_glbl_pram */ 2695 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram)); 2696 2697 /* Fill global PRAM */ 2698 2699 /* RQPTR */ 2700 /* Size varies with number of Rx threads */ 2701 ugeth->thread_dat_rx_offset = 2702 qe_muram_alloc(numThreadsRxNumerical * 2703 sizeof(struct ucc_geth_thread_data_rx), 2704 UCC_GETH_THREAD_DATA_ALIGNMENT); 2705 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) { 2706 if (netif_msg_ifup(ugeth)) 2707 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n"); 2708 return -ENOMEM; 2709 } 2710 2711 ugeth->p_thread_data_rx = 2712 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth-> 2713 thread_dat_rx_offset); 2714 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset); 2715 2716 /* typeorlen */ 2717 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen); 2718 2719 /* rxrmonbaseptr (statistics) */ 2720 if (ug_info-> 2721 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) { 2722 ugeth->rx_fw_statistics_pram_offset = 2723 qe_muram_alloc(sizeof 2724 (struct ucc_geth_rx_firmware_statistics_pram), 2725 UCC_GETH_RX_STATISTICS_ALIGNMENT); 2726 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) { 2727 if (netif_msg_ifup(ugeth)) 2728 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n"); 2729 return -ENOMEM; 2730 } 2731 ugeth->p_rx_fw_statistics_pram = 2732 (struct ucc_geth_rx_firmware_statistics_pram __iomem *) 2733 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset); 2734 /* Zero out p_rx_fw_statistics_pram */ 2735 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0, 2736 sizeof(struct ucc_geth_rx_firmware_statistics_pram)); 2737 } 2738 2739 /* intCoalescingPtr */ 2740 2741 /* Size varies with number of Rx queues */ 2742 ugeth->rx_irq_coalescing_tbl_offset = 2743 qe_muram_alloc(ug_info->numQueuesRx * 2744 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry) 2745 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT); 2746 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) { 2747 if (netif_msg_ifup(ugeth)) 2748 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n"); 2749 return -ENOMEM; 2750 } 2751 2752 ugeth->p_rx_irq_coalescing_tbl = 2753 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *) 2754 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset); 2755 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr, 2756 ugeth->rx_irq_coalescing_tbl_offset); 2757 2758 /* Fill interrupt coalescing table */ 2759 for (i = 0; i < ug_info->numQueuesRx; i++) { 2760 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2761 interruptcoalescingmaxvalue, 2762 ug_info->interruptcoalescingmaxvalue[i]); 2763 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i]. 2764 interruptcoalescingcounter, 2765 ug_info->interruptcoalescingmaxvalue[i]); 2766 } 2767 2768 /* MRBLR */ 2769 init_max_rx_buff_len(uf_info->max_rx_buf_length, 2770 &ugeth->p_rx_glbl_pram->mrblr); 2771 /* MFLR */ 2772 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength); 2773 /* MINFLR */ 2774 init_min_frame_len(ug_info->minFrameLength, 2775 &ugeth->p_rx_glbl_pram->minflr, 2776 &ugeth->p_rx_glbl_pram->mrblr); 2777 /* MAXD1 */ 2778 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length); 2779 /* MAXD2 */ 2780 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length); 2781 2782 /* l2qt */ 2783 l2qt = 0; 2784 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) 2785 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i)); 2786 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt); 2787 2788 /* l3qt */ 2789 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) { 2790 l3qt = 0; 2791 for (i = 0; i < 8; i++) 2792 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i)); 2793 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt); 2794 } 2795 2796 /* vlantype */ 2797 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype); 2798 2799 /* vlantci */ 2800 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci); 2801 2802 /* ecamptr */ 2803 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr); 2804 2805 /* RBDQPTR */ 2806 /* Size varies with number of Rx queues */ 2807 ugeth->rx_bd_qs_tbl_offset = 2808 qe_muram_alloc(ug_info->numQueuesRx * 2809 (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2810 sizeof(struct ucc_geth_rx_prefetched_bds)), 2811 UCC_GETH_RX_BD_QUEUES_ALIGNMENT); 2812 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) { 2813 if (netif_msg_ifup(ugeth)) 2814 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n"); 2815 return -ENOMEM; 2816 } 2817 2818 ugeth->p_rx_bd_qs_tbl = 2819 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth-> 2820 rx_bd_qs_tbl_offset); 2821 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset); 2822 /* Zero out p_rx_bd_qs_tbl */ 2823 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl, 2824 0, 2825 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) + 2826 sizeof(struct ucc_geth_rx_prefetched_bds))); 2827 2828 /* Setup the table */ 2829 /* Assume BD rings are already established */ 2830 for (i = 0; i < ug_info->numQueuesRx; i++) { 2831 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) { 2832 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2833 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i])); 2834 } else if (ugeth->ug_info->uf_info.bd_mem_part == 2835 MEM_PART_MURAM) { 2836 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr, 2837 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i])); 2838 } 2839 /* rest of fields handled by QE */ 2840 } 2841 2842 /* remoder */ 2843 /* Already has speed set */ 2844 2845 if (ugeth->rx_extended_features) 2846 remoder |= REMODER_RX_EXTENDED_FEATURES; 2847 if (ug_info->rxExtendedFiltering) 2848 remoder |= REMODER_RX_EXTENDED_FILTERING; 2849 if (ug_info->dynamicMaxFrameLength) 2850 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH; 2851 if (ug_info->dynamicMinFrameLength) 2852 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH; 2853 remoder |= 2854 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT; 2855 remoder |= 2856 ug_info-> 2857 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT; 2858 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT; 2859 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT); 2860 if (ug_info->ipCheckSumCheck) 2861 remoder |= REMODER_IP_CHECKSUM_CHECK; 2862 if (ug_info->ipAddressAlignment) 2863 remoder |= REMODER_IP_ADDRESS_ALIGNMENT; 2864 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder); 2865 2866 /* Note that this function must be called */ 2867 /* ONLY AFTER p_tx_fw_statistics_pram */ 2868 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */ 2869 init_firmware_statistics_gathering_mode((ug_info-> 2870 statisticsMode & 2871 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX), 2872 (ug_info->statisticsMode & 2873 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX), 2874 &ugeth->p_tx_glbl_pram->txrmonbaseptr, 2875 ugeth->tx_fw_statistics_pram_offset, 2876 &ugeth->p_rx_glbl_pram->rxrmonbaseptr, 2877 ugeth->rx_fw_statistics_pram_offset, 2878 &ugeth->p_tx_glbl_pram->temoder, 2879 &ugeth->p_rx_glbl_pram->remoder); 2880 2881 /* function code register */ 2882 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code); 2883 2884 /* initialize extended filtering */ 2885 if (ug_info->rxExtendedFiltering) { 2886 if (!ug_info->extendedFilteringChainPointer) { 2887 if (netif_msg_ifup(ugeth)) 2888 pr_err("Null Extended Filtering Chain Pointer\n"); 2889 return -EINVAL; 2890 } 2891 2892 /* Allocate memory for extended filtering Mode Global 2893 Parameters */ 2894 ugeth->exf_glbl_param_offset = 2895 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram), 2896 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT); 2897 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) { 2898 if (netif_msg_ifup(ugeth)) 2899 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n"); 2900 return -ENOMEM; 2901 } 2902 2903 ugeth->p_exf_glbl_param = 2904 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth-> 2905 exf_glbl_param_offset); 2906 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam, 2907 ugeth->exf_glbl_param_offset); 2908 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr, 2909 (u32) ug_info->extendedFilteringChainPointer); 2910 2911 } else { /* initialize 82xx style address filtering */ 2912 2913 /* Init individual address recognition registers to disabled */ 2914 2915 for (j = 0; j < NUM_OF_PADDRS; j++) 2916 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j); 2917 2918 p_82xx_addr_filt = 2919 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth-> 2920 p_rx_glbl_pram->addressfiltering; 2921 2922 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2923 ENET_ADDR_TYPE_GROUP); 2924 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth, 2925 ENET_ADDR_TYPE_INDIVIDUAL); 2926 } 2927 2928 /* 2929 * Initialize UCC at QE level 2930 */ 2931 2932 command = QE_INIT_TX_RX; 2933 2934 /* Allocate shadow InitEnet command parameter structure. 2935 * This is needed because after the InitEnet command is executed, 2936 * the structure in DPRAM is released, because DPRAM is a premium 2937 * resource. 2938 * This shadow structure keeps a copy of what was done so that the 2939 * allocated resources can be released when the channel is freed. 2940 */ 2941 if (!(ugeth->p_init_enet_param_shadow = 2942 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) { 2943 if (netif_msg_ifup(ugeth)) 2944 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n"); 2945 return -ENOMEM; 2946 } 2947 /* Zero out *p_init_enet_param_shadow */ 2948 memset((char *)ugeth->p_init_enet_param_shadow, 2949 0, sizeof(struct ucc_geth_init_pram)); 2950 2951 /* Fill shadow InitEnet command parameter structure */ 2952 2953 ugeth->p_init_enet_param_shadow->resinit1 = 2954 ENET_INIT_PARAM_MAGIC_RES_INIT1; 2955 ugeth->p_init_enet_param_shadow->resinit2 = 2956 ENET_INIT_PARAM_MAGIC_RES_INIT2; 2957 ugeth->p_init_enet_param_shadow->resinit3 = 2958 ENET_INIT_PARAM_MAGIC_RES_INIT3; 2959 ugeth->p_init_enet_param_shadow->resinit4 = 2960 ENET_INIT_PARAM_MAGIC_RES_INIT4; 2961 ugeth->p_init_enet_param_shadow->resinit5 = 2962 ENET_INIT_PARAM_MAGIC_RES_INIT5; 2963 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2964 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT; 2965 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2966 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT; 2967 2968 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |= 2969 ugeth->rx_glbl_pram_offset | ug_info->riscRx; 2970 if ((ug_info->largestexternallookupkeysize != 2971 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) && 2972 (ug_info->largestexternallookupkeysize != 2973 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) && 2974 (ug_info->largestexternallookupkeysize != 2975 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) { 2976 if (netif_msg_ifup(ugeth)) 2977 pr_err("Invalid largest External Lookup Key Size\n"); 2978 return -EINVAL; 2979 } 2980 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize = 2981 ug_info->largestexternallookupkeysize; 2982 size = sizeof(struct ucc_geth_thread_rx_pram); 2983 if (ug_info->rxExtendedFiltering) { 2984 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING; 2985 if (ug_info->largestexternallookupkeysize == 2986 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) 2987 size += 2988 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8; 2989 if (ug_info->largestexternallookupkeysize == 2990 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES) 2991 size += 2992 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16; 2993 } 2994 2995 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth-> 2996 p_init_enet_param_shadow->rxthread[0]), 2997 (u8) (numThreadsRxNumerical + 1) 2998 /* Rx needs one extra for terminator */ 2999 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT, 3000 ug_info->riscRx, 1)) != 0) { 3001 if (netif_msg_ifup(ugeth)) 3002 pr_err("Can not fill p_init_enet_param_shadow\n"); 3003 return ret_val; 3004 } 3005 3006 ugeth->p_init_enet_param_shadow->txglobal = 3007 ugeth->tx_glbl_pram_offset | ug_info->riscTx; 3008 if ((ret_val = 3009 fill_init_enet_entries(ugeth, 3010 &(ugeth->p_init_enet_param_shadow-> 3011 txthread[0]), numThreadsTxNumerical, 3012 sizeof(struct ucc_geth_thread_tx_pram), 3013 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT, 3014 ug_info->riscTx, 0)) != 0) { 3015 if (netif_msg_ifup(ugeth)) 3016 pr_err("Can not fill p_init_enet_param_shadow\n"); 3017 return ret_val; 3018 } 3019 3020 /* Load Rx bds with buffers */ 3021 for (i = 0; i < ug_info->numQueuesRx; i++) { 3022 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) { 3023 if (netif_msg_ifup(ugeth)) 3024 pr_err("Can not fill Rx bds with buffers\n"); 3025 return ret_val; 3026 } 3027 } 3028 3029 /* Allocate InitEnet command parameter structure */ 3030 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4); 3031 if (IS_ERR_VALUE(init_enet_pram_offset)) { 3032 if (netif_msg_ifup(ugeth)) 3033 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n"); 3034 return -ENOMEM; 3035 } 3036 p_init_enet_pram = 3037 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset); 3038 3039 /* Copy shadow InitEnet command parameter structure into PRAM */ 3040 out_8(&p_init_enet_pram->resinit1, 3041 ugeth->p_init_enet_param_shadow->resinit1); 3042 out_8(&p_init_enet_pram->resinit2, 3043 ugeth->p_init_enet_param_shadow->resinit2); 3044 out_8(&p_init_enet_pram->resinit3, 3045 ugeth->p_init_enet_param_shadow->resinit3); 3046 out_8(&p_init_enet_pram->resinit4, 3047 ugeth->p_init_enet_param_shadow->resinit4); 3048 out_be16(&p_init_enet_pram->resinit5, 3049 ugeth->p_init_enet_param_shadow->resinit5); 3050 out_8(&p_init_enet_pram->largestexternallookupkeysize, 3051 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize); 3052 out_be32(&p_init_enet_pram->rgftgfrxglobal, 3053 ugeth->p_init_enet_param_shadow->rgftgfrxglobal); 3054 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++) 3055 out_be32(&p_init_enet_pram->rxthread[i], 3056 ugeth->p_init_enet_param_shadow->rxthread[i]); 3057 out_be32(&p_init_enet_pram->txglobal, 3058 ugeth->p_init_enet_param_shadow->txglobal); 3059 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++) 3060 out_be32(&p_init_enet_pram->txthread[i], 3061 ugeth->p_init_enet_param_shadow->txthread[i]); 3062 3063 /* Issue QE command */ 3064 cecr_subblock = 3065 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num); 3066 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 3067 init_enet_pram_offset); 3068 3069 /* Free InitEnet command parameter */ 3070 qe_muram_free(init_enet_pram_offset); 3071 3072 return 0; 3073 } 3074 3075 /* This is called by the kernel when a frame is ready for transmission. */ 3076 /* It is pointed to by the dev->hard_start_xmit function pointer */ 3077 static netdev_tx_t 3078 ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev) 3079 { 3080 struct ucc_geth_private *ugeth = netdev_priv(dev); 3081 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3082 struct ucc_fast_private *uccf; 3083 #endif 3084 u8 __iomem *bd; /* BD pointer */ 3085 u32 bd_status; 3086 u8 txQ = 0; 3087 unsigned long flags; 3088 3089 ugeth_vdbg("%s: IN", __func__); 3090 3091 netdev_sent_queue(dev, skb->len); 3092 spin_lock_irqsave(&ugeth->lock, flags); 3093 3094 dev->stats.tx_bytes += skb->len; 3095 3096 /* Start from the next BD that should be filled */ 3097 bd = ugeth->txBd[txQ]; 3098 bd_status = in_be32((u32 __iomem *)bd); 3099 /* Save the skb pointer so we can free it later */ 3100 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb; 3101 3102 /* Update the current skb pointer (wrapping if this was the last) */ 3103 ugeth->skb_curtx[txQ] = 3104 (ugeth->skb_curtx[txQ] + 3105 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3106 3107 /* set up the buffer descriptor */ 3108 out_be32(&((struct qe_bd __iomem *)bd)->buf, 3109 dma_map_single(ugeth->dev, skb->data, 3110 skb->len, DMA_TO_DEVICE)); 3111 3112 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */ 3113 3114 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len; 3115 3116 /* set bd status and length */ 3117 out_be32((u32 __iomem *)bd, bd_status); 3118 3119 /* Move to next BD in the ring */ 3120 if (!(bd_status & T_W)) 3121 bd += sizeof(struct qe_bd); 3122 else 3123 bd = ugeth->p_tx_bd_ring[txQ]; 3124 3125 /* If the next BD still needs to be cleaned up, then the bds 3126 are full. We need to tell the kernel to stop sending us stuff. */ 3127 if (bd == ugeth->confBd[txQ]) { 3128 if (!netif_queue_stopped(dev)) 3129 netif_stop_queue(dev); 3130 } 3131 3132 ugeth->txBd[txQ] = bd; 3133 3134 skb_tx_timestamp(skb); 3135 3136 if (ugeth->p_scheduler) { 3137 ugeth->cpucount[txQ]++; 3138 /* Indicate to QE that there are more Tx bds ready for 3139 transmission */ 3140 /* This is done by writing a running counter of the bd 3141 count to the scheduler PRAM. */ 3142 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]); 3143 } 3144 3145 #ifdef CONFIG_UGETH_TX_ON_DEMAND 3146 uccf = ugeth->uccf; 3147 out_be16(uccf->p_utodr, UCC_FAST_TOD); 3148 #endif 3149 spin_unlock_irqrestore(&ugeth->lock, flags); 3150 3151 return NETDEV_TX_OK; 3152 } 3153 3154 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit) 3155 { 3156 struct sk_buff *skb; 3157 u8 __iomem *bd; 3158 u16 length, howmany = 0; 3159 u32 bd_status; 3160 u8 *bdBuffer; 3161 struct net_device *dev; 3162 3163 ugeth_vdbg("%s: IN", __func__); 3164 3165 dev = ugeth->ndev; 3166 3167 /* collect received buffers */ 3168 bd = ugeth->rxBd[rxQ]; 3169 3170 bd_status = in_be32((u32 __iomem *)bd); 3171 3172 /* while there are received buffers and BD is full (~R_E) */ 3173 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) { 3174 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf); 3175 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4); 3176 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]]; 3177 3178 /* determine whether buffer is first, last, first and last 3179 (single buffer frame) or middle (not first and not last) */ 3180 if (!skb || 3181 (!(bd_status & (R_F | R_L))) || 3182 (bd_status & R_ERRORS_FATAL)) { 3183 if (netif_msg_rx_err(ugeth)) 3184 pr_err("%d: ERROR!!! skb - 0x%08x\n", 3185 __LINE__, (u32)skb); 3186 dev_kfree_skb(skb); 3187 3188 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL; 3189 dev->stats.rx_dropped++; 3190 } else { 3191 dev->stats.rx_packets++; 3192 howmany++; 3193 3194 /* Prep the skb for the packet */ 3195 skb_put(skb, length); 3196 3197 /* Tell the skb what kind of packet this is */ 3198 skb->protocol = eth_type_trans(skb, ugeth->ndev); 3199 3200 dev->stats.rx_bytes += length; 3201 /* Send the packet up the stack */ 3202 netif_receive_skb(skb); 3203 } 3204 3205 skb = get_new_skb(ugeth, bd); 3206 if (!skb) { 3207 if (netif_msg_rx_err(ugeth)) 3208 pr_warn("No Rx Data Buffer\n"); 3209 dev->stats.rx_dropped++; 3210 break; 3211 } 3212 3213 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb; 3214 3215 /* update to point at the next skb */ 3216 ugeth->skb_currx[rxQ] = 3217 (ugeth->skb_currx[rxQ] + 3218 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]); 3219 3220 if (bd_status & R_W) 3221 bd = ugeth->p_rx_bd_ring[rxQ]; 3222 else 3223 bd += sizeof(struct qe_bd); 3224 3225 bd_status = in_be32((u32 __iomem *)bd); 3226 } 3227 3228 ugeth->rxBd[rxQ] = bd; 3229 return howmany; 3230 } 3231 3232 static int ucc_geth_tx(struct net_device *dev, u8 txQ) 3233 { 3234 /* Start from the next BD that should be filled */ 3235 struct ucc_geth_private *ugeth = netdev_priv(dev); 3236 unsigned int bytes_sent = 0; 3237 int howmany = 0; 3238 u8 __iomem *bd; /* BD pointer */ 3239 u32 bd_status; 3240 3241 bd = ugeth->confBd[txQ]; 3242 bd_status = in_be32((u32 __iomem *)bd); 3243 3244 /* Normal processing. */ 3245 while ((bd_status & T_R) == 0) { 3246 struct sk_buff *skb; 3247 3248 /* BD contains already transmitted buffer. */ 3249 /* Handle the transmitted buffer and release */ 3250 /* the BD to be used with the current frame */ 3251 3252 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]; 3253 if (!skb) 3254 break; 3255 howmany++; 3256 bytes_sent += skb->len; 3257 dev->stats.tx_packets++; 3258 3259 dev_consume_skb_any(skb); 3260 3261 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL; 3262 ugeth->skb_dirtytx[txQ] = 3263 (ugeth->skb_dirtytx[txQ] + 3264 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]); 3265 3266 /* We freed a buffer, so now we can restart transmission */ 3267 if (netif_queue_stopped(dev)) 3268 netif_wake_queue(dev); 3269 3270 /* Advance the confirmation BD pointer */ 3271 if (!(bd_status & T_W)) 3272 bd += sizeof(struct qe_bd); 3273 else 3274 bd = ugeth->p_tx_bd_ring[txQ]; 3275 bd_status = in_be32((u32 __iomem *)bd); 3276 } 3277 ugeth->confBd[txQ] = bd; 3278 netdev_completed_queue(dev, howmany, bytes_sent); 3279 return 0; 3280 } 3281 3282 static int ucc_geth_poll(struct napi_struct *napi, int budget) 3283 { 3284 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi); 3285 struct ucc_geth_info *ug_info; 3286 int howmany, i; 3287 3288 ug_info = ugeth->ug_info; 3289 3290 /* Tx event processing */ 3291 spin_lock(&ugeth->lock); 3292 for (i = 0; i < ug_info->numQueuesTx; i++) 3293 ucc_geth_tx(ugeth->ndev, i); 3294 spin_unlock(&ugeth->lock); 3295 3296 howmany = 0; 3297 for (i = 0; i < ug_info->numQueuesRx; i++) 3298 howmany += ucc_geth_rx(ugeth, i, budget - howmany); 3299 3300 if (howmany < budget) { 3301 napi_complete_done(napi, howmany); 3302 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3303 } 3304 3305 return howmany; 3306 } 3307 3308 static irqreturn_t ucc_geth_irq_handler(int irq, void *info) 3309 { 3310 struct net_device *dev = info; 3311 struct ucc_geth_private *ugeth = netdev_priv(dev); 3312 struct ucc_fast_private *uccf; 3313 struct ucc_geth_info *ug_info; 3314 register u32 ucce; 3315 register u32 uccm; 3316 3317 ugeth_vdbg("%s: IN", __func__); 3318 3319 uccf = ugeth->uccf; 3320 ug_info = ugeth->ug_info; 3321 3322 /* read and clear events */ 3323 ucce = (u32) in_be32(uccf->p_ucce); 3324 uccm = (u32) in_be32(uccf->p_uccm); 3325 ucce &= uccm; 3326 out_be32(uccf->p_ucce, ucce); 3327 3328 /* check for receive events that require processing */ 3329 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) { 3330 if (napi_schedule_prep(&ugeth->napi)) { 3331 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS); 3332 out_be32(uccf->p_uccm, uccm); 3333 __napi_schedule(&ugeth->napi); 3334 } 3335 } 3336 3337 /* Errors and other events */ 3338 if (ucce & UCCE_OTHER) { 3339 if (ucce & UCC_GETH_UCCE_BSY) 3340 dev->stats.rx_errors++; 3341 if (ucce & UCC_GETH_UCCE_TXE) 3342 dev->stats.tx_errors++; 3343 } 3344 3345 return IRQ_HANDLED; 3346 } 3347 3348 #ifdef CONFIG_NET_POLL_CONTROLLER 3349 /* 3350 * Polling 'interrupt' - used by things like netconsole to send skbs 3351 * without having to re-enable interrupts. It's not called while 3352 * the interrupt routine is executing. 3353 */ 3354 static void ucc_netpoll(struct net_device *dev) 3355 { 3356 struct ucc_geth_private *ugeth = netdev_priv(dev); 3357 int irq = ugeth->ug_info->uf_info.irq; 3358 3359 disable_irq(irq); 3360 ucc_geth_irq_handler(irq, dev); 3361 enable_irq(irq); 3362 } 3363 #endif /* CONFIG_NET_POLL_CONTROLLER */ 3364 3365 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p) 3366 { 3367 struct ucc_geth_private *ugeth = netdev_priv(dev); 3368 struct sockaddr *addr = p; 3369 3370 if (!is_valid_ether_addr(addr->sa_data)) 3371 return -EADDRNOTAVAIL; 3372 3373 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3374 3375 /* 3376 * If device is not running, we will set mac addr register 3377 * when opening the device. 3378 */ 3379 if (!netif_running(dev)) 3380 return 0; 3381 3382 spin_lock_irq(&ugeth->lock); 3383 init_mac_station_addr_regs(dev->dev_addr[0], 3384 dev->dev_addr[1], 3385 dev->dev_addr[2], 3386 dev->dev_addr[3], 3387 dev->dev_addr[4], 3388 dev->dev_addr[5], 3389 &ugeth->ug_regs->macstnaddr1, 3390 &ugeth->ug_regs->macstnaddr2); 3391 spin_unlock_irq(&ugeth->lock); 3392 3393 return 0; 3394 } 3395 3396 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth) 3397 { 3398 struct net_device *dev = ugeth->ndev; 3399 int err; 3400 3401 err = ucc_struct_init(ugeth); 3402 if (err) { 3403 netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n"); 3404 goto err; 3405 } 3406 3407 err = ucc_geth_startup(ugeth); 3408 if (err) { 3409 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3410 goto err; 3411 } 3412 3413 err = adjust_enet_interface(ugeth); 3414 if (err) { 3415 netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n"); 3416 goto err; 3417 } 3418 3419 /* Set MACSTNADDR1, MACSTNADDR2 */ 3420 /* For more details see the hardware spec. */ 3421 init_mac_station_addr_regs(dev->dev_addr[0], 3422 dev->dev_addr[1], 3423 dev->dev_addr[2], 3424 dev->dev_addr[3], 3425 dev->dev_addr[4], 3426 dev->dev_addr[5], 3427 &ugeth->ug_regs->macstnaddr1, 3428 &ugeth->ug_regs->macstnaddr2); 3429 3430 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3431 if (err) { 3432 netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n"); 3433 goto err; 3434 } 3435 3436 return 0; 3437 err: 3438 ucc_geth_stop(ugeth); 3439 return err; 3440 } 3441 3442 /* Called when something needs to use the ethernet device */ 3443 /* Returns 0 for success. */ 3444 static int ucc_geth_open(struct net_device *dev) 3445 { 3446 struct ucc_geth_private *ugeth = netdev_priv(dev); 3447 int err; 3448 3449 ugeth_vdbg("%s: IN", __func__); 3450 3451 /* Test station address */ 3452 if (dev->dev_addr[0] & ENET_GROUP_ADDR) { 3453 netif_err(ugeth, ifup, dev, 3454 "Multicast address used for station address - is this what you wanted?\n"); 3455 return -EINVAL; 3456 } 3457 3458 err = init_phy(dev); 3459 if (err) { 3460 netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n"); 3461 return err; 3462 } 3463 3464 err = ucc_geth_init_mac(ugeth); 3465 if (err) { 3466 netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n"); 3467 goto err; 3468 } 3469 3470 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 3471 0, "UCC Geth", dev); 3472 if (err) { 3473 netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n"); 3474 goto err; 3475 } 3476 3477 phy_start(ugeth->phydev); 3478 napi_enable(&ugeth->napi); 3479 netdev_reset_queue(dev); 3480 netif_start_queue(dev); 3481 3482 device_set_wakeup_capable(&dev->dev, 3483 qe_alive_during_sleep() || ugeth->phydev->irq); 3484 device_set_wakeup_enable(&dev->dev, ugeth->wol_en); 3485 3486 return err; 3487 3488 err: 3489 ucc_geth_stop(ugeth); 3490 return err; 3491 } 3492 3493 /* Stops the kernel queue, and halts the controller */ 3494 static int ucc_geth_close(struct net_device *dev) 3495 { 3496 struct ucc_geth_private *ugeth = netdev_priv(dev); 3497 3498 ugeth_vdbg("%s: IN", __func__); 3499 3500 napi_disable(&ugeth->napi); 3501 3502 cancel_work_sync(&ugeth->timeout_work); 3503 ucc_geth_stop(ugeth); 3504 phy_disconnect(ugeth->phydev); 3505 ugeth->phydev = NULL; 3506 3507 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev); 3508 3509 netif_stop_queue(dev); 3510 netdev_reset_queue(dev); 3511 3512 return 0; 3513 } 3514 3515 /* Reopen device. This will reset the MAC and PHY. */ 3516 static void ucc_geth_timeout_work(struct work_struct *work) 3517 { 3518 struct ucc_geth_private *ugeth; 3519 struct net_device *dev; 3520 3521 ugeth = container_of(work, struct ucc_geth_private, timeout_work); 3522 dev = ugeth->ndev; 3523 3524 ugeth_vdbg("%s: IN", __func__); 3525 3526 dev->stats.tx_errors++; 3527 3528 ugeth_dump_regs(ugeth); 3529 3530 if (dev->flags & IFF_UP) { 3531 /* 3532 * Must reset MAC *and* PHY. This is done by reopening 3533 * the device. 3534 */ 3535 netif_tx_stop_all_queues(dev); 3536 ucc_geth_stop(ugeth); 3537 ucc_geth_init_mac(ugeth); 3538 /* Must start PHY here */ 3539 phy_start(ugeth->phydev); 3540 netif_tx_start_all_queues(dev); 3541 } 3542 3543 netif_tx_schedule_all(dev); 3544 } 3545 3546 /* 3547 * ucc_geth_timeout gets called when a packet has not been 3548 * transmitted after a set amount of time. 3549 */ 3550 static void ucc_geth_timeout(struct net_device *dev) 3551 { 3552 struct ucc_geth_private *ugeth = netdev_priv(dev); 3553 3554 schedule_work(&ugeth->timeout_work); 3555 } 3556 3557 3558 #ifdef CONFIG_PM 3559 3560 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state) 3561 { 3562 struct net_device *ndev = platform_get_drvdata(ofdev); 3563 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3564 3565 if (!netif_running(ndev)) 3566 return 0; 3567 3568 netif_device_detach(ndev); 3569 napi_disable(&ugeth->napi); 3570 3571 /* 3572 * Disable the controller, otherwise we'll wakeup on any network 3573 * activity. 3574 */ 3575 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX); 3576 3577 if (ugeth->wol_en & WAKE_MAGIC) { 3578 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3579 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3580 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3581 } else if (!(ugeth->wol_en & WAKE_PHY)) { 3582 phy_stop(ugeth->phydev); 3583 } 3584 3585 return 0; 3586 } 3587 3588 static int ucc_geth_resume(struct platform_device *ofdev) 3589 { 3590 struct net_device *ndev = platform_get_drvdata(ofdev); 3591 struct ucc_geth_private *ugeth = netdev_priv(ndev); 3592 int err; 3593 3594 if (!netif_running(ndev)) 3595 return 0; 3596 3597 if (qe_alive_during_sleep()) { 3598 if (ugeth->wol_en & WAKE_MAGIC) { 3599 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX); 3600 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE); 3601 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD); 3602 } 3603 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX); 3604 } else { 3605 /* 3606 * Full reinitialization is required if QE shuts down 3607 * during sleep. 3608 */ 3609 ucc_geth_memclean(ugeth); 3610 3611 err = ucc_geth_init_mac(ugeth); 3612 if (err) { 3613 netdev_err(ndev, "Cannot initialize MAC, aborting\n"); 3614 return err; 3615 } 3616 } 3617 3618 ugeth->oldlink = 0; 3619 ugeth->oldspeed = 0; 3620 ugeth->oldduplex = -1; 3621 3622 phy_stop(ugeth->phydev); 3623 phy_start(ugeth->phydev); 3624 3625 napi_enable(&ugeth->napi); 3626 netif_device_attach(ndev); 3627 3628 return 0; 3629 } 3630 3631 #else 3632 #define ucc_geth_suspend NULL 3633 #define ucc_geth_resume NULL 3634 #endif 3635 3636 static phy_interface_t to_phy_interface(const char *phy_connection_type) 3637 { 3638 if (strcasecmp(phy_connection_type, "mii") == 0) 3639 return PHY_INTERFACE_MODE_MII; 3640 if (strcasecmp(phy_connection_type, "gmii") == 0) 3641 return PHY_INTERFACE_MODE_GMII; 3642 if (strcasecmp(phy_connection_type, "tbi") == 0) 3643 return PHY_INTERFACE_MODE_TBI; 3644 if (strcasecmp(phy_connection_type, "rmii") == 0) 3645 return PHY_INTERFACE_MODE_RMII; 3646 if (strcasecmp(phy_connection_type, "rgmii") == 0) 3647 return PHY_INTERFACE_MODE_RGMII; 3648 if (strcasecmp(phy_connection_type, "rgmii-id") == 0) 3649 return PHY_INTERFACE_MODE_RGMII_ID; 3650 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0) 3651 return PHY_INTERFACE_MODE_RGMII_TXID; 3652 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0) 3653 return PHY_INTERFACE_MODE_RGMII_RXID; 3654 if (strcasecmp(phy_connection_type, "rtbi") == 0) 3655 return PHY_INTERFACE_MODE_RTBI; 3656 if (strcasecmp(phy_connection_type, "sgmii") == 0) 3657 return PHY_INTERFACE_MODE_SGMII; 3658 3659 return PHY_INTERFACE_MODE_MII; 3660 } 3661 3662 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3663 { 3664 struct ucc_geth_private *ugeth = netdev_priv(dev); 3665 3666 if (!netif_running(dev)) 3667 return -EINVAL; 3668 3669 if (!ugeth->phydev) 3670 return -ENODEV; 3671 3672 return phy_mii_ioctl(ugeth->phydev, rq, cmd); 3673 } 3674 3675 static const struct net_device_ops ucc_geth_netdev_ops = { 3676 .ndo_open = ucc_geth_open, 3677 .ndo_stop = ucc_geth_close, 3678 .ndo_start_xmit = ucc_geth_start_xmit, 3679 .ndo_validate_addr = eth_validate_addr, 3680 .ndo_change_carrier = fixed_phy_change_carrier, 3681 .ndo_set_mac_address = ucc_geth_set_mac_addr, 3682 .ndo_set_rx_mode = ucc_geth_set_multi, 3683 .ndo_tx_timeout = ucc_geth_timeout, 3684 .ndo_do_ioctl = ucc_geth_ioctl, 3685 #ifdef CONFIG_NET_POLL_CONTROLLER 3686 .ndo_poll_controller = ucc_netpoll, 3687 #endif 3688 }; 3689 3690 static int ucc_geth_probe(struct platform_device* ofdev) 3691 { 3692 struct device *device = &ofdev->dev; 3693 struct device_node *np = ofdev->dev.of_node; 3694 struct net_device *dev = NULL; 3695 struct ucc_geth_private *ugeth = NULL; 3696 struct ucc_geth_info *ug_info; 3697 struct resource res; 3698 int err, ucc_num, max_speed = 0; 3699 const unsigned int *prop; 3700 const char *sprop; 3701 const void *mac_addr; 3702 phy_interface_t phy_interface; 3703 static const int enet_to_speed[] = { 3704 SPEED_10, SPEED_10, SPEED_10, 3705 SPEED_100, SPEED_100, SPEED_100, 3706 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000, 3707 }; 3708 static const phy_interface_t enet_to_phy_interface[] = { 3709 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII, 3710 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII, 3711 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII, 3712 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII, 3713 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI, 3714 PHY_INTERFACE_MODE_SGMII, 3715 }; 3716 3717 ugeth_vdbg("%s: IN", __func__); 3718 3719 prop = of_get_property(np, "cell-index", NULL); 3720 if (!prop) { 3721 prop = of_get_property(np, "device-id", NULL); 3722 if (!prop) 3723 return -ENODEV; 3724 } 3725 3726 ucc_num = *prop - 1; 3727 if ((ucc_num < 0) || (ucc_num > 7)) 3728 return -ENODEV; 3729 3730 ug_info = &ugeth_info[ucc_num]; 3731 if (ug_info == NULL) { 3732 if (netif_msg_probe(&debug)) 3733 pr_err("[%d] Missing additional data!\n", ucc_num); 3734 return -ENODEV; 3735 } 3736 3737 ug_info->uf_info.ucc_num = ucc_num; 3738 3739 sprop = of_get_property(np, "rx-clock-name", NULL); 3740 if (sprop) { 3741 ug_info->uf_info.rx_clock = qe_clock_source(sprop); 3742 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) || 3743 (ug_info->uf_info.rx_clock > QE_CLK24)) { 3744 pr_err("invalid rx-clock-name property\n"); 3745 return -EINVAL; 3746 } 3747 } else { 3748 prop = of_get_property(np, "rx-clock", NULL); 3749 if (!prop) { 3750 /* If both rx-clock-name and rx-clock are missing, 3751 we want to tell people to use rx-clock-name. */ 3752 pr_err("missing rx-clock-name property\n"); 3753 return -EINVAL; 3754 } 3755 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3756 pr_err("invalid rx-clock property\n"); 3757 return -EINVAL; 3758 } 3759 ug_info->uf_info.rx_clock = *prop; 3760 } 3761 3762 sprop = of_get_property(np, "tx-clock-name", NULL); 3763 if (sprop) { 3764 ug_info->uf_info.tx_clock = qe_clock_source(sprop); 3765 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) || 3766 (ug_info->uf_info.tx_clock > QE_CLK24)) { 3767 pr_err("invalid tx-clock-name property\n"); 3768 return -EINVAL; 3769 } 3770 } else { 3771 prop = of_get_property(np, "tx-clock", NULL); 3772 if (!prop) { 3773 pr_err("missing tx-clock-name property\n"); 3774 return -EINVAL; 3775 } 3776 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) { 3777 pr_err("invalid tx-clock property\n"); 3778 return -EINVAL; 3779 } 3780 ug_info->uf_info.tx_clock = *prop; 3781 } 3782 3783 err = of_address_to_resource(np, 0, &res); 3784 if (err) 3785 return -EINVAL; 3786 3787 ug_info->uf_info.regs = res.start; 3788 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); 3789 3790 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0); 3791 if (!ug_info->phy_node && of_phy_is_fixed_link(np)) { 3792 /* 3793 * In the case of a fixed PHY, the DT node associated 3794 * to the PHY is the Ethernet MAC DT node. 3795 */ 3796 err = of_phy_register_fixed_link(np); 3797 if (err) 3798 return err; 3799 ug_info->phy_node = of_node_get(np); 3800 } 3801 3802 /* Find the TBI PHY node. If it's not there, we don't support SGMII */ 3803 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 3804 3805 /* get the phy interface type, or default to MII */ 3806 prop = of_get_property(np, "phy-connection-type", NULL); 3807 if (!prop) { 3808 /* handle interface property present in old trees */ 3809 prop = of_get_property(ug_info->phy_node, "interface", NULL); 3810 if (prop != NULL) { 3811 phy_interface = enet_to_phy_interface[*prop]; 3812 max_speed = enet_to_speed[*prop]; 3813 } else 3814 phy_interface = PHY_INTERFACE_MODE_MII; 3815 } else { 3816 phy_interface = to_phy_interface((const char *)prop); 3817 } 3818 3819 /* get speed, or derive from PHY interface */ 3820 if (max_speed == 0) 3821 switch (phy_interface) { 3822 case PHY_INTERFACE_MODE_GMII: 3823 case PHY_INTERFACE_MODE_RGMII: 3824 case PHY_INTERFACE_MODE_RGMII_ID: 3825 case PHY_INTERFACE_MODE_RGMII_RXID: 3826 case PHY_INTERFACE_MODE_RGMII_TXID: 3827 case PHY_INTERFACE_MODE_TBI: 3828 case PHY_INTERFACE_MODE_RTBI: 3829 case PHY_INTERFACE_MODE_SGMII: 3830 max_speed = SPEED_1000; 3831 break; 3832 default: 3833 max_speed = SPEED_100; 3834 break; 3835 } 3836 3837 if (max_speed == SPEED_1000) { 3838 unsigned int snums = qe_get_num_of_snums(); 3839 3840 /* configure muram FIFOs for gigabit operation */ 3841 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT; 3842 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT; 3843 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT; 3844 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT; 3845 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; 3846 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; 3847 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; 3848 3849 /* If QE's snum number is 46/76 which means we need to support 3850 * 4 UECs at 1000Base-T simultaneously, we need to allocate 3851 * more Threads to Rx. 3852 */ 3853 if ((snums == 76) || (snums == 46)) 3854 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; 3855 else 3856 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; 3857 } 3858 3859 if (netif_msg_probe(&debug)) 3860 pr_info("UCC%1d at 0x%8llx (irq = %d)\n", 3861 ug_info->uf_info.ucc_num + 1, 3862 (u64)ug_info->uf_info.regs, 3863 ug_info->uf_info.irq); 3864 3865 /* Create an ethernet device instance */ 3866 dev = alloc_etherdev(sizeof(*ugeth)); 3867 3868 if (dev == NULL) { 3869 err = -ENOMEM; 3870 goto err_deregister_fixed_link; 3871 } 3872 3873 ugeth = netdev_priv(dev); 3874 spin_lock_init(&ugeth->lock); 3875 3876 /* Create CQs for hash tables */ 3877 INIT_LIST_HEAD(&ugeth->group_hash_q); 3878 INIT_LIST_HEAD(&ugeth->ind_hash_q); 3879 3880 dev_set_drvdata(device, dev); 3881 3882 /* Set the dev->base_addr to the gfar reg region */ 3883 dev->base_addr = (unsigned long)(ug_info->uf_info.regs); 3884 3885 SET_NETDEV_DEV(dev, device); 3886 3887 /* Fill in the dev structure */ 3888 uec_set_ethtool_ops(dev); 3889 dev->netdev_ops = &ucc_geth_netdev_ops; 3890 dev->watchdog_timeo = TX_TIMEOUT; 3891 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work); 3892 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64); 3893 dev->mtu = 1500; 3894 3895 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT); 3896 ugeth->phy_interface = phy_interface; 3897 ugeth->max_speed = max_speed; 3898 3899 /* Carrier starts down, phylib will bring it up */ 3900 netif_carrier_off(dev); 3901 3902 err = register_netdev(dev); 3903 if (err) { 3904 if (netif_msg_probe(ugeth)) 3905 pr_err("%s: Cannot register net device, aborting\n", 3906 dev->name); 3907 goto err_free_netdev; 3908 } 3909 3910 mac_addr = of_get_mac_address(np); 3911 if (mac_addr) 3912 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 3913 3914 ugeth->ug_info = ug_info; 3915 ugeth->dev = device; 3916 ugeth->ndev = dev; 3917 ugeth->node = np; 3918 3919 return 0; 3920 3921 err_free_netdev: 3922 free_netdev(dev); 3923 err_deregister_fixed_link: 3924 if (of_phy_is_fixed_link(np)) 3925 of_phy_deregister_fixed_link(np); 3926 of_node_put(ug_info->tbi_node); 3927 of_node_put(ug_info->phy_node); 3928 3929 return err; 3930 } 3931 3932 static int ucc_geth_remove(struct platform_device* ofdev) 3933 { 3934 struct net_device *dev = platform_get_drvdata(ofdev); 3935 struct ucc_geth_private *ugeth = netdev_priv(dev); 3936 struct device_node *np = ofdev->dev.of_node; 3937 3938 unregister_netdev(dev); 3939 free_netdev(dev); 3940 ucc_geth_memclean(ugeth); 3941 if (of_phy_is_fixed_link(np)) 3942 of_phy_deregister_fixed_link(np); 3943 of_node_put(ugeth->ug_info->tbi_node); 3944 of_node_put(ugeth->ug_info->phy_node); 3945 3946 return 0; 3947 } 3948 3949 static const struct of_device_id ucc_geth_match[] = { 3950 { 3951 .type = "network", 3952 .compatible = "ucc_geth", 3953 }, 3954 {}, 3955 }; 3956 3957 MODULE_DEVICE_TABLE(of, ucc_geth_match); 3958 3959 static struct platform_driver ucc_geth_driver = { 3960 .driver = { 3961 .name = DRV_NAME, 3962 .of_match_table = ucc_geth_match, 3963 }, 3964 .probe = ucc_geth_probe, 3965 .remove = ucc_geth_remove, 3966 .suspend = ucc_geth_suspend, 3967 .resume = ucc_geth_resume, 3968 }; 3969 3970 static int __init ucc_geth_init(void) 3971 { 3972 int i, ret; 3973 3974 if (netif_msg_drv(&debug)) 3975 pr_info(DRV_DESC "\n"); 3976 for (i = 0; i < 8; i++) 3977 memcpy(&(ugeth_info[i]), &ugeth_primary_info, 3978 sizeof(ugeth_primary_info)); 3979 3980 ret = platform_driver_register(&ucc_geth_driver); 3981 3982 return ret; 3983 } 3984 3985 static void __exit ucc_geth_exit(void) 3986 { 3987 platform_driver_unregister(&ucc_geth_driver); 3988 } 3989 3990 module_init(ucc_geth_init); 3991 module_exit(ucc_geth_exit); 3992 3993 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 3994 MODULE_DESCRIPTION(DRV_DESC); 3995 MODULE_VERSION(DRV_VERSION); 3996 MODULE_LICENSE("GPL"); 3997