1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
4  *
5  * Author: Shlomi Gridish <gridish@freescale.com>
6  *	   Li Yang <leoli@freescale.com>
7  *
8  * Description:
9  * QE UCC Gigabit Ethernet Driver
10  */
11 
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
25 #include <linux/mm.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/phy_fixed.h>
30 #include <linux/workqueue.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35 #include <linux/of_platform.h>
36 
37 #include <linux/uaccess.h>
38 #include <asm/irq.h>
39 #include <asm/io.h>
40 #include <soc/fsl/qe/immap_qe.h>
41 #include <soc/fsl/qe/qe.h>
42 #include <soc/fsl/qe/ucc.h>
43 #include <soc/fsl/qe/ucc_fast.h>
44 #include <asm/machdep.h>
45 
46 #include "ucc_geth.h"
47 
48 #undef DEBUG
49 
50 #define ugeth_printk(level, format, arg...)  \
51         printk(level format "\n", ## arg)
52 
53 #define ugeth_dbg(format, arg...)            \
54         ugeth_printk(KERN_DEBUG , format , ## arg)
55 
56 #ifdef UGETH_VERBOSE_DEBUG
57 #define ugeth_vdbg ugeth_dbg
58 #else
59 #define ugeth_vdbg(fmt, args...) do { } while (0)
60 #endif				/* UGETH_VERBOSE_DEBUG */
61 #define UGETH_MSG_DEFAULT	(NETIF_MSG_IFUP << 1 ) - 1
62 
63 
64 static DEFINE_SPINLOCK(ugeth_lock);
65 
66 static struct {
67 	u32 msg_enable;
68 } debug = { -1 };
69 
70 module_param_named(debug, debug.msg_enable, int, 0);
71 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
72 
73 static struct ucc_geth_info ugeth_primary_info = {
74 	.uf_info = {
75 		    .bd_mem_part = MEM_PART_SYSTEM,
76 		    .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
77 		    .max_rx_buf_length = 1536,
78 		    /* adjusted at startup if max-speed 1000 */
79 		    .urfs = UCC_GETH_URFS_INIT,
80 		    .urfet = UCC_GETH_URFET_INIT,
81 		    .urfset = UCC_GETH_URFSET_INIT,
82 		    .utfs = UCC_GETH_UTFS_INIT,
83 		    .utfet = UCC_GETH_UTFET_INIT,
84 		    .utftt = UCC_GETH_UTFTT_INIT,
85 		    .ufpt = 256,
86 		    .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
87 		    .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
88 		    .tenc = UCC_FAST_TX_ENCODING_NRZ,
89 		    .renc = UCC_FAST_RX_ENCODING_NRZ,
90 		    .tcrc = UCC_FAST_16_BIT_CRC,
91 		    .synl = UCC_FAST_SYNC_LEN_NOT_USED,
92 		    },
93 	.numQueuesTx = 1,
94 	.numQueuesRx = 1,
95 	.extendedFilteringChainPointer = ((uint32_t) NULL),
96 	.typeorlen = 3072 /*1536 */ ,
97 	.nonBackToBackIfgPart1 = 0x40,
98 	.nonBackToBackIfgPart2 = 0x60,
99 	.miminumInterFrameGapEnforcement = 0x50,
100 	.backToBackInterFrameGap = 0x60,
101 	.mblinterval = 128,
102 	.nortsrbytetime = 5,
103 	.fracsiz = 1,
104 	.strictpriorityq = 0xff,
105 	.altBebTruncation = 0xa,
106 	.excessDefer = 1,
107 	.maxRetransmission = 0xf,
108 	.collisionWindow = 0x37,
109 	.receiveFlowControl = 1,
110 	.transmitFlowControl = 1,
111 	.maxGroupAddrInHash = 4,
112 	.maxIndAddrInHash = 4,
113 	.prel = 7,
114 	.maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
115 	.minFrameLength = 64,
116 	.maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
117 	.maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
118 	.vlantype = 0x8100,
119 	.ecamptr = ((uint32_t) NULL),
120 	.eventRegMask = UCCE_OTHER,
121 	.pausePeriod = 0xf000,
122 	.interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
123 	.bdRingLenTx = {
124 			TX_BD_RING_LEN,
125 			TX_BD_RING_LEN,
126 			TX_BD_RING_LEN,
127 			TX_BD_RING_LEN,
128 			TX_BD_RING_LEN,
129 			TX_BD_RING_LEN,
130 			TX_BD_RING_LEN,
131 			TX_BD_RING_LEN},
132 
133 	.bdRingLenRx = {
134 			RX_BD_RING_LEN,
135 			RX_BD_RING_LEN,
136 			RX_BD_RING_LEN,
137 			RX_BD_RING_LEN,
138 			RX_BD_RING_LEN,
139 			RX_BD_RING_LEN,
140 			RX_BD_RING_LEN,
141 			RX_BD_RING_LEN},
142 
143 	.numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
144 	.largestexternallookupkeysize =
145 	    QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
146 	.statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
147 		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
148 		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
149 	.vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
150 	.vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
151 	.rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
152 	.aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
153 	.padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
154 	.numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
155 	.numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
156 	.riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
157 	.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
158 };
159 
160 static struct ucc_geth_info ugeth_info[8];
161 
162 #ifdef DEBUG
163 static void mem_disp(u8 *addr, int size)
164 {
165 	u8 *i;
166 	int size16Aling = (size >> 4) << 4;
167 	int size4Aling = (size >> 2) << 2;
168 	int notAlign = 0;
169 	if (size % 16)
170 		notAlign = 1;
171 
172 	for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
173 		printk("0x%08x: %08x %08x %08x %08x\r\n",
174 		       (u32) i,
175 		       *((u32 *) (i)),
176 		       *((u32 *) (i + 4)),
177 		       *((u32 *) (i + 8)), *((u32 *) (i + 12)));
178 	if (notAlign == 1)
179 		printk("0x%08x: ", (u32) i);
180 	for (; (u32) i < (u32) addr + size4Aling; i += 4)
181 		printk("%08x ", *((u32 *) (i)));
182 	for (; (u32) i < (u32) addr + size; i++)
183 		printk("%02x", *((i)));
184 	if (notAlign == 1)
185 		printk("\r\n");
186 }
187 #endif /* DEBUG */
188 
189 static struct list_head *dequeue(struct list_head *lh)
190 {
191 	unsigned long flags;
192 
193 	spin_lock_irqsave(&ugeth_lock, flags);
194 	if (!list_empty(lh)) {
195 		struct list_head *node = lh->next;
196 		list_del(node);
197 		spin_unlock_irqrestore(&ugeth_lock, flags);
198 		return node;
199 	} else {
200 		spin_unlock_irqrestore(&ugeth_lock, flags);
201 		return NULL;
202 	}
203 }
204 
205 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
206 		u8 __iomem *bd)
207 {
208 	struct sk_buff *skb;
209 
210 	skb = netdev_alloc_skb(ugeth->ndev,
211 			       ugeth->ug_info->uf_info.max_rx_buf_length +
212 			       UCC_GETH_RX_DATA_BUF_ALIGNMENT);
213 	if (!skb)
214 		return NULL;
215 
216 	/* We need the data buffer to be aligned properly.  We will reserve
217 	 * as many bytes as needed to align the data properly
218 	 */
219 	skb_reserve(skb,
220 		    UCC_GETH_RX_DATA_BUF_ALIGNMENT -
221 		    (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
222 					      1)));
223 
224 	out_be32(&((struct qe_bd __iomem *)bd)->buf,
225 		      dma_map_single(ugeth->dev,
226 				     skb->data,
227 				     ugeth->ug_info->uf_info.max_rx_buf_length +
228 				     UCC_GETH_RX_DATA_BUF_ALIGNMENT,
229 				     DMA_FROM_DEVICE));
230 
231 	out_be32((u32 __iomem *)bd,
232 			(R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
233 
234 	return skb;
235 }
236 
237 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
238 {
239 	u8 __iomem *bd;
240 	u32 bd_status;
241 	struct sk_buff *skb;
242 	int i;
243 
244 	bd = ugeth->p_rx_bd_ring[rxQ];
245 	i = 0;
246 
247 	do {
248 		bd_status = in_be32((u32 __iomem *)bd);
249 		skb = get_new_skb(ugeth, bd);
250 
251 		if (!skb)	/* If can not allocate data buffer,
252 				abort. Cleanup will be elsewhere */
253 			return -ENOMEM;
254 
255 		ugeth->rx_skbuff[rxQ][i] = skb;
256 
257 		/* advance the BD pointer */
258 		bd += sizeof(struct qe_bd);
259 		i++;
260 	} while (!(bd_status & R_W));
261 
262 	return 0;
263 }
264 
265 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
266 				  u32 *p_start,
267 				  u8 num_entries,
268 				  u32 thread_size,
269 				  u32 thread_alignment,
270 				  unsigned int risc,
271 				  int skip_page_for_first_entry)
272 {
273 	u32 init_enet_offset;
274 	u8 i;
275 	int snum;
276 
277 	for (i = 0; i < num_entries; i++) {
278 		if ((snum = qe_get_snum()) < 0) {
279 			if (netif_msg_ifup(ugeth))
280 				pr_err("Can not get SNUM\n");
281 			return snum;
282 		}
283 		if ((i == 0) && skip_page_for_first_entry)
284 		/* First entry of Rx does not have page */
285 			init_enet_offset = 0;
286 		else {
287 			init_enet_offset =
288 			    qe_muram_alloc(thread_size, thread_alignment);
289 			if (IS_ERR_VALUE(init_enet_offset)) {
290 				if (netif_msg_ifup(ugeth))
291 					pr_err("Can not allocate DPRAM memory\n");
292 				qe_put_snum((u8) snum);
293 				return -ENOMEM;
294 			}
295 		}
296 		*(p_start++) =
297 		    ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
298 		    | risc;
299 	}
300 
301 	return 0;
302 }
303 
304 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
305 				    u32 *p_start,
306 				    u8 num_entries,
307 				    unsigned int risc,
308 				    int skip_page_for_first_entry)
309 {
310 	u32 init_enet_offset;
311 	u8 i;
312 	int snum;
313 
314 	for (i = 0; i < num_entries; i++) {
315 		u32 val = *p_start;
316 
317 		/* Check that this entry was actually valid --
318 		needed in case failed in allocations */
319 		if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
320 			snum =
321 			    (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
322 			    ENET_INIT_PARAM_SNUM_SHIFT;
323 			qe_put_snum((u8) snum);
324 			if (!((i == 0) && skip_page_for_first_entry)) {
325 			/* First entry of Rx does not have page */
326 				init_enet_offset =
327 				    (val & ENET_INIT_PARAM_PTR_MASK);
328 				qe_muram_free(init_enet_offset);
329 			}
330 			*p_start++ = 0;
331 		}
332 	}
333 
334 	return 0;
335 }
336 
337 #ifdef DEBUG
338 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
339 				  u32 __iomem *p_start,
340 				  u8 num_entries,
341 				  u32 thread_size,
342 				  unsigned int risc,
343 				  int skip_page_for_first_entry)
344 {
345 	u32 init_enet_offset;
346 	u8 i;
347 	int snum;
348 
349 	for (i = 0; i < num_entries; i++) {
350 		u32 val = in_be32(p_start);
351 
352 		/* Check that this entry was actually valid --
353 		needed in case failed in allocations */
354 		if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
355 			snum =
356 			    (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
357 			    ENET_INIT_PARAM_SNUM_SHIFT;
358 			qe_put_snum((u8) snum);
359 			if (!((i == 0) && skip_page_for_first_entry)) {
360 			/* First entry of Rx does not have page */
361 				init_enet_offset =
362 				    (in_be32(p_start) &
363 				     ENET_INIT_PARAM_PTR_MASK);
364 				pr_info("Init enet entry %d:\n", i);
365 				pr_info("Base address: 0x%08x\n",
366 					(u32)qe_muram_addr(init_enet_offset));
367 				mem_disp(qe_muram_addr(init_enet_offset),
368 					 thread_size);
369 			}
370 			p_start++;
371 		}
372 	}
373 
374 	return 0;
375 }
376 #endif
377 
378 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
379 {
380 	kfree(enet_addr_cont);
381 }
382 
383 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
384 {
385 	out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
386 	out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
387 	out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
388 }
389 
390 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
391 {
392 	struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
393 
394 	if (paddr_num >= NUM_OF_PADDRS) {
395 		pr_warn("%s: Invalid paddr_num: %u\n", __func__, paddr_num);
396 		return -EINVAL;
397 	}
398 
399 	p_82xx_addr_filt =
400 	    (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
401 	    addressfiltering;
402 
403 	/* Writing address ff.ff.ff.ff.ff.ff disables address
404 	recognition for this register */
405 	out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
406 	out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
407 	out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
408 
409 	return 0;
410 }
411 
412 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
413                                 u8 *p_enet_addr)
414 {
415 	struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
416 	u32 cecr_subblock;
417 
418 	p_82xx_addr_filt =
419 	    (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
420 	    addressfiltering;
421 
422 	cecr_subblock =
423 	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
424 
425 	/* Ethernet frames are defined in Little Endian mode,
426 	therefore to insert */
427 	/* the address to the hash (Big Endian mode), we reverse the bytes.*/
428 
429 	set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
430 
431 	qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
432 		     QE_CR_PROTOCOL_ETHERNET, 0);
433 }
434 
435 #ifdef DEBUG
436 static void get_statistics(struct ucc_geth_private *ugeth,
437 			   struct ucc_geth_tx_firmware_statistics *
438 			   tx_firmware_statistics,
439 			   struct ucc_geth_rx_firmware_statistics *
440 			   rx_firmware_statistics,
441 			   struct ucc_geth_hardware_statistics *hardware_statistics)
442 {
443 	struct ucc_fast __iomem *uf_regs;
444 	struct ucc_geth __iomem *ug_regs;
445 	struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
446 	struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
447 
448 	ug_regs = ugeth->ug_regs;
449 	uf_regs = (struct ucc_fast __iomem *) ug_regs;
450 	p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
451 	p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
452 
453 	/* Tx firmware only if user handed pointer and driver actually
454 	gathers Tx firmware statistics */
455 	if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
456 		tx_firmware_statistics->sicoltx =
457 		    in_be32(&p_tx_fw_statistics_pram->sicoltx);
458 		tx_firmware_statistics->mulcoltx =
459 		    in_be32(&p_tx_fw_statistics_pram->mulcoltx);
460 		tx_firmware_statistics->latecoltxfr =
461 		    in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
462 		tx_firmware_statistics->frabortduecol =
463 		    in_be32(&p_tx_fw_statistics_pram->frabortduecol);
464 		tx_firmware_statistics->frlostinmactxer =
465 		    in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
466 		tx_firmware_statistics->carriersenseertx =
467 		    in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
468 		tx_firmware_statistics->frtxok =
469 		    in_be32(&p_tx_fw_statistics_pram->frtxok);
470 		tx_firmware_statistics->txfrexcessivedefer =
471 		    in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
472 		tx_firmware_statistics->txpkts256 =
473 		    in_be32(&p_tx_fw_statistics_pram->txpkts256);
474 		tx_firmware_statistics->txpkts512 =
475 		    in_be32(&p_tx_fw_statistics_pram->txpkts512);
476 		tx_firmware_statistics->txpkts1024 =
477 		    in_be32(&p_tx_fw_statistics_pram->txpkts1024);
478 		tx_firmware_statistics->txpktsjumbo =
479 		    in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
480 	}
481 
482 	/* Rx firmware only if user handed pointer and driver actually
483 	 * gathers Rx firmware statistics */
484 	if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
485 		int i;
486 		rx_firmware_statistics->frrxfcser =
487 		    in_be32(&p_rx_fw_statistics_pram->frrxfcser);
488 		rx_firmware_statistics->fraligner =
489 		    in_be32(&p_rx_fw_statistics_pram->fraligner);
490 		rx_firmware_statistics->inrangelenrxer =
491 		    in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
492 		rx_firmware_statistics->outrangelenrxer =
493 		    in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
494 		rx_firmware_statistics->frtoolong =
495 		    in_be32(&p_rx_fw_statistics_pram->frtoolong);
496 		rx_firmware_statistics->runt =
497 		    in_be32(&p_rx_fw_statistics_pram->runt);
498 		rx_firmware_statistics->verylongevent =
499 		    in_be32(&p_rx_fw_statistics_pram->verylongevent);
500 		rx_firmware_statistics->symbolerror =
501 		    in_be32(&p_rx_fw_statistics_pram->symbolerror);
502 		rx_firmware_statistics->dropbsy =
503 		    in_be32(&p_rx_fw_statistics_pram->dropbsy);
504 		for (i = 0; i < 0x8; i++)
505 			rx_firmware_statistics->res0[i] =
506 			    p_rx_fw_statistics_pram->res0[i];
507 		rx_firmware_statistics->mismatchdrop =
508 		    in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
509 		rx_firmware_statistics->underpkts =
510 		    in_be32(&p_rx_fw_statistics_pram->underpkts);
511 		rx_firmware_statistics->pkts256 =
512 		    in_be32(&p_rx_fw_statistics_pram->pkts256);
513 		rx_firmware_statistics->pkts512 =
514 		    in_be32(&p_rx_fw_statistics_pram->pkts512);
515 		rx_firmware_statistics->pkts1024 =
516 		    in_be32(&p_rx_fw_statistics_pram->pkts1024);
517 		rx_firmware_statistics->pktsjumbo =
518 		    in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
519 		rx_firmware_statistics->frlossinmacer =
520 		    in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
521 		rx_firmware_statistics->pausefr =
522 		    in_be32(&p_rx_fw_statistics_pram->pausefr);
523 		for (i = 0; i < 0x4; i++)
524 			rx_firmware_statistics->res1[i] =
525 			    p_rx_fw_statistics_pram->res1[i];
526 		rx_firmware_statistics->removevlan =
527 		    in_be32(&p_rx_fw_statistics_pram->removevlan);
528 		rx_firmware_statistics->replacevlan =
529 		    in_be32(&p_rx_fw_statistics_pram->replacevlan);
530 		rx_firmware_statistics->insertvlan =
531 		    in_be32(&p_rx_fw_statistics_pram->insertvlan);
532 	}
533 
534 	/* Hardware only if user handed pointer and driver actually
535 	gathers hardware statistics */
536 	if (hardware_statistics &&
537 	    (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
538 		hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
539 		hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
540 		hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
541 		hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
542 		hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
543 		hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
544 		hardware_statistics->txok = in_be32(&ug_regs->txok);
545 		hardware_statistics->txcf = in_be16(&ug_regs->txcf);
546 		hardware_statistics->tmca = in_be32(&ug_regs->tmca);
547 		hardware_statistics->tbca = in_be32(&ug_regs->tbca);
548 		hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
549 		hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
550 		hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
551 		hardware_statistics->rmca = in_be32(&ug_regs->rmca);
552 		hardware_statistics->rbca = in_be32(&ug_regs->rbca);
553 	}
554 }
555 
556 static void dump_bds(struct ucc_geth_private *ugeth)
557 {
558 	int i;
559 	int length;
560 
561 	for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
562 		if (ugeth->p_tx_bd_ring[i]) {
563 			length =
564 			    (ugeth->ug_info->bdRingLenTx[i] *
565 			     sizeof(struct qe_bd));
566 			pr_info("TX BDs[%d]\n", i);
567 			mem_disp(ugeth->p_tx_bd_ring[i], length);
568 		}
569 	}
570 	for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
571 		if (ugeth->p_rx_bd_ring[i]) {
572 			length =
573 			    (ugeth->ug_info->bdRingLenRx[i] *
574 			     sizeof(struct qe_bd));
575 			pr_info("RX BDs[%d]\n", i);
576 			mem_disp(ugeth->p_rx_bd_ring[i], length);
577 		}
578 	}
579 }
580 
581 static void dump_regs(struct ucc_geth_private *ugeth)
582 {
583 	int i;
584 
585 	pr_info("UCC%d Geth registers:\n", ugeth->ug_info->uf_info.ucc_num + 1);
586 	pr_info("Base address: 0x%08x\n", (u32)ugeth->ug_regs);
587 
588 	pr_info("maccfg1    : addr - 0x%08x, val - 0x%08x\n",
589 		(u32)&ugeth->ug_regs->maccfg1,
590 		in_be32(&ugeth->ug_regs->maccfg1));
591 	pr_info("maccfg2    : addr - 0x%08x, val - 0x%08x\n",
592 		(u32)&ugeth->ug_regs->maccfg2,
593 		in_be32(&ugeth->ug_regs->maccfg2));
594 	pr_info("ipgifg     : addr - 0x%08x, val - 0x%08x\n",
595 		(u32)&ugeth->ug_regs->ipgifg,
596 		in_be32(&ugeth->ug_regs->ipgifg));
597 	pr_info("hafdup     : addr - 0x%08x, val - 0x%08x\n",
598 		(u32)&ugeth->ug_regs->hafdup,
599 		in_be32(&ugeth->ug_regs->hafdup));
600 	pr_info("ifctl      : addr - 0x%08x, val - 0x%08x\n",
601 		(u32)&ugeth->ug_regs->ifctl,
602 		in_be32(&ugeth->ug_regs->ifctl));
603 	pr_info("ifstat     : addr - 0x%08x, val - 0x%08x\n",
604 		(u32)&ugeth->ug_regs->ifstat,
605 		in_be32(&ugeth->ug_regs->ifstat));
606 	pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
607 		(u32)&ugeth->ug_regs->macstnaddr1,
608 		in_be32(&ugeth->ug_regs->macstnaddr1));
609 	pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
610 		(u32)&ugeth->ug_regs->macstnaddr2,
611 		in_be32(&ugeth->ug_regs->macstnaddr2));
612 	pr_info("uempr      : addr - 0x%08x, val - 0x%08x\n",
613 		(u32)&ugeth->ug_regs->uempr,
614 		in_be32(&ugeth->ug_regs->uempr));
615 	pr_info("utbipar    : addr - 0x%08x, val - 0x%08x\n",
616 		(u32)&ugeth->ug_regs->utbipar,
617 		in_be32(&ugeth->ug_regs->utbipar));
618 	pr_info("uescr      : addr - 0x%08x, val - 0x%04x\n",
619 		(u32)&ugeth->ug_regs->uescr,
620 		in_be16(&ugeth->ug_regs->uescr));
621 	pr_info("tx64       : addr - 0x%08x, val - 0x%08x\n",
622 		(u32)&ugeth->ug_regs->tx64,
623 		in_be32(&ugeth->ug_regs->tx64));
624 	pr_info("tx127      : addr - 0x%08x, val - 0x%08x\n",
625 		(u32)&ugeth->ug_regs->tx127,
626 		in_be32(&ugeth->ug_regs->tx127));
627 	pr_info("tx255      : addr - 0x%08x, val - 0x%08x\n",
628 		(u32)&ugeth->ug_regs->tx255,
629 		in_be32(&ugeth->ug_regs->tx255));
630 	pr_info("rx64       : addr - 0x%08x, val - 0x%08x\n",
631 		(u32)&ugeth->ug_regs->rx64,
632 		in_be32(&ugeth->ug_regs->rx64));
633 	pr_info("rx127      : addr - 0x%08x, val - 0x%08x\n",
634 		(u32)&ugeth->ug_regs->rx127,
635 		in_be32(&ugeth->ug_regs->rx127));
636 	pr_info("rx255      : addr - 0x%08x, val - 0x%08x\n",
637 		(u32)&ugeth->ug_regs->rx255,
638 		in_be32(&ugeth->ug_regs->rx255));
639 	pr_info("txok       : addr - 0x%08x, val - 0x%08x\n",
640 		(u32)&ugeth->ug_regs->txok,
641 		in_be32(&ugeth->ug_regs->txok));
642 	pr_info("txcf       : addr - 0x%08x, val - 0x%04x\n",
643 		(u32)&ugeth->ug_regs->txcf,
644 		in_be16(&ugeth->ug_regs->txcf));
645 	pr_info("tmca       : addr - 0x%08x, val - 0x%08x\n",
646 		(u32)&ugeth->ug_regs->tmca,
647 		in_be32(&ugeth->ug_regs->tmca));
648 	pr_info("tbca       : addr - 0x%08x, val - 0x%08x\n",
649 		(u32)&ugeth->ug_regs->tbca,
650 		in_be32(&ugeth->ug_regs->tbca));
651 	pr_info("rxfok      : addr - 0x%08x, val - 0x%08x\n",
652 		(u32)&ugeth->ug_regs->rxfok,
653 		in_be32(&ugeth->ug_regs->rxfok));
654 	pr_info("rxbok      : addr - 0x%08x, val - 0x%08x\n",
655 		(u32)&ugeth->ug_regs->rxbok,
656 		in_be32(&ugeth->ug_regs->rxbok));
657 	pr_info("rbyt       : addr - 0x%08x, val - 0x%08x\n",
658 		(u32)&ugeth->ug_regs->rbyt,
659 		in_be32(&ugeth->ug_regs->rbyt));
660 	pr_info("rmca       : addr - 0x%08x, val - 0x%08x\n",
661 		(u32)&ugeth->ug_regs->rmca,
662 		in_be32(&ugeth->ug_regs->rmca));
663 	pr_info("rbca       : addr - 0x%08x, val - 0x%08x\n",
664 		(u32)&ugeth->ug_regs->rbca,
665 		in_be32(&ugeth->ug_regs->rbca));
666 	pr_info("scar       : addr - 0x%08x, val - 0x%08x\n",
667 		(u32)&ugeth->ug_regs->scar,
668 		in_be32(&ugeth->ug_regs->scar));
669 	pr_info("scam       : addr - 0x%08x, val - 0x%08x\n",
670 		(u32)&ugeth->ug_regs->scam,
671 		in_be32(&ugeth->ug_regs->scam));
672 
673 	if (ugeth->p_thread_data_tx) {
674 		int numThreadsTxNumerical;
675 		switch (ugeth->ug_info->numThreadsTx) {
676 		case UCC_GETH_NUM_OF_THREADS_1:
677 			numThreadsTxNumerical = 1;
678 			break;
679 		case UCC_GETH_NUM_OF_THREADS_2:
680 			numThreadsTxNumerical = 2;
681 			break;
682 		case UCC_GETH_NUM_OF_THREADS_4:
683 			numThreadsTxNumerical = 4;
684 			break;
685 		case UCC_GETH_NUM_OF_THREADS_6:
686 			numThreadsTxNumerical = 6;
687 			break;
688 		case UCC_GETH_NUM_OF_THREADS_8:
689 			numThreadsTxNumerical = 8;
690 			break;
691 		default:
692 			numThreadsTxNumerical = 0;
693 			break;
694 		}
695 
696 		pr_info("Thread data TXs:\n");
697 		pr_info("Base address: 0x%08x\n",
698 			(u32)ugeth->p_thread_data_tx);
699 		for (i = 0; i < numThreadsTxNumerical; i++) {
700 			pr_info("Thread data TX[%d]:\n", i);
701 			pr_info("Base address: 0x%08x\n",
702 				(u32)&ugeth->p_thread_data_tx[i]);
703 			mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
704 				 sizeof(struct ucc_geth_thread_data_tx));
705 		}
706 	}
707 	if (ugeth->p_thread_data_rx) {
708 		int numThreadsRxNumerical;
709 		switch (ugeth->ug_info->numThreadsRx) {
710 		case UCC_GETH_NUM_OF_THREADS_1:
711 			numThreadsRxNumerical = 1;
712 			break;
713 		case UCC_GETH_NUM_OF_THREADS_2:
714 			numThreadsRxNumerical = 2;
715 			break;
716 		case UCC_GETH_NUM_OF_THREADS_4:
717 			numThreadsRxNumerical = 4;
718 			break;
719 		case UCC_GETH_NUM_OF_THREADS_6:
720 			numThreadsRxNumerical = 6;
721 			break;
722 		case UCC_GETH_NUM_OF_THREADS_8:
723 			numThreadsRxNumerical = 8;
724 			break;
725 		default:
726 			numThreadsRxNumerical = 0;
727 			break;
728 		}
729 
730 		pr_info("Thread data RX:\n");
731 		pr_info("Base address: 0x%08x\n",
732 			(u32)ugeth->p_thread_data_rx);
733 		for (i = 0; i < numThreadsRxNumerical; i++) {
734 			pr_info("Thread data RX[%d]:\n", i);
735 			pr_info("Base address: 0x%08x\n",
736 				(u32)&ugeth->p_thread_data_rx[i]);
737 			mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
738 				 sizeof(struct ucc_geth_thread_data_rx));
739 		}
740 	}
741 	if (ugeth->p_exf_glbl_param) {
742 		pr_info("EXF global param:\n");
743 		pr_info("Base address: 0x%08x\n",
744 			(u32)ugeth->p_exf_glbl_param);
745 		mem_disp((u8 *) ugeth->p_exf_glbl_param,
746 			 sizeof(*ugeth->p_exf_glbl_param));
747 	}
748 	if (ugeth->p_tx_glbl_pram) {
749 		pr_info("TX global param:\n");
750 		pr_info("Base address: 0x%08x\n", (u32)ugeth->p_tx_glbl_pram);
751 		pr_info("temoder      : addr - 0x%08x, val - 0x%04x\n",
752 			(u32)&ugeth->p_tx_glbl_pram->temoder,
753 			in_be16(&ugeth->p_tx_glbl_pram->temoder));
754 	       pr_info("sqptr        : addr - 0x%08x, val - 0x%08x\n",
755 			(u32)&ugeth->p_tx_glbl_pram->sqptr,
756 			in_be32(&ugeth->p_tx_glbl_pram->sqptr));
757 		pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
758 			(u32)&ugeth->p_tx_glbl_pram->schedulerbasepointer,
759 			in_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer));
760 		pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
761 			(u32)&ugeth->p_tx_glbl_pram->txrmonbaseptr,
762 			in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
763 		pr_info("tstate       : addr - 0x%08x, val - 0x%08x\n",
764 			(u32)&ugeth->p_tx_glbl_pram->tstate,
765 			in_be32(&ugeth->p_tx_glbl_pram->tstate));
766 		pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
767 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[0],
768 			ugeth->p_tx_glbl_pram->iphoffset[0]);
769 		pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
770 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[1],
771 			ugeth->p_tx_glbl_pram->iphoffset[1]);
772 		pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
773 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[2],
774 			ugeth->p_tx_glbl_pram->iphoffset[2]);
775 		pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
776 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[3],
777 			ugeth->p_tx_glbl_pram->iphoffset[3]);
778 		pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
779 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[4],
780 			ugeth->p_tx_glbl_pram->iphoffset[4]);
781 		pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
782 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[5],
783 			ugeth->p_tx_glbl_pram->iphoffset[5]);
784 		pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
785 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[6],
786 			ugeth->p_tx_glbl_pram->iphoffset[6]);
787 		pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
788 			(u32)&ugeth->p_tx_glbl_pram->iphoffset[7],
789 			ugeth->p_tx_glbl_pram->iphoffset[7]);
790 		pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
791 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[0],
792 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
793 		pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
794 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[1],
795 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
796 		pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
797 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[2],
798 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
799 		pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
800 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[3],
801 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
802 		pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
803 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[4],
804 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
805 		pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
806 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[5],
807 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
808 		pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
809 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[6],
810 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
811 		pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
812 			(u32)&ugeth->p_tx_glbl_pram->vtagtable[7],
813 			in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
814 		pr_info("tqptr        : addr - 0x%08x, val - 0x%08x\n",
815 			(u32)&ugeth->p_tx_glbl_pram->tqptr,
816 			in_be32(&ugeth->p_tx_glbl_pram->tqptr));
817 	}
818 	if (ugeth->p_rx_glbl_pram) {
819 		pr_info("RX global param:\n");
820 		pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_glbl_pram);
821 		pr_info("remoder         : addr - 0x%08x, val - 0x%08x\n",
822 			(u32)&ugeth->p_rx_glbl_pram->remoder,
823 			in_be32(&ugeth->p_rx_glbl_pram->remoder));
824 		pr_info("rqptr           : addr - 0x%08x, val - 0x%08x\n",
825 			(u32)&ugeth->p_rx_glbl_pram->rqptr,
826 			in_be32(&ugeth->p_rx_glbl_pram->rqptr));
827 		pr_info("typeorlen       : addr - 0x%08x, val - 0x%04x\n",
828 			(u32)&ugeth->p_rx_glbl_pram->typeorlen,
829 			in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
830 		pr_info("rxgstpack       : addr - 0x%08x, val - 0x%02x\n",
831 			(u32)&ugeth->p_rx_glbl_pram->rxgstpack,
832 			ugeth->p_rx_glbl_pram->rxgstpack);
833 		pr_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x\n",
834 			(u32)&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
835 			in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
836 		pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
837 			(u32)&ugeth->p_rx_glbl_pram->intcoalescingptr,
838 			in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
839 		pr_info("rstate          : addr - 0x%08x, val - 0x%02x\n",
840 			(u32)&ugeth->p_rx_glbl_pram->rstate,
841 			ugeth->p_rx_glbl_pram->rstate);
842 		pr_info("mrblr           : addr - 0x%08x, val - 0x%04x\n",
843 			(u32)&ugeth->p_rx_glbl_pram->mrblr,
844 			in_be16(&ugeth->p_rx_glbl_pram->mrblr));
845 		pr_info("rbdqptr         : addr - 0x%08x, val - 0x%08x\n",
846 			(u32)&ugeth->p_rx_glbl_pram->rbdqptr,
847 			in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
848 		pr_info("mflr            : addr - 0x%08x, val - 0x%04x\n",
849 			(u32)&ugeth->p_rx_glbl_pram->mflr,
850 			in_be16(&ugeth->p_rx_glbl_pram->mflr));
851 		pr_info("minflr          : addr - 0x%08x, val - 0x%04x\n",
852 			(u32)&ugeth->p_rx_glbl_pram->minflr,
853 			in_be16(&ugeth->p_rx_glbl_pram->minflr));
854 		pr_info("maxd1           : addr - 0x%08x, val - 0x%04x\n",
855 			(u32)&ugeth->p_rx_glbl_pram->maxd1,
856 			in_be16(&ugeth->p_rx_glbl_pram->maxd1));
857 		pr_info("maxd2           : addr - 0x%08x, val - 0x%04x\n",
858 			(u32)&ugeth->p_rx_glbl_pram->maxd2,
859 			in_be16(&ugeth->p_rx_glbl_pram->maxd2));
860 		pr_info("ecamptr         : addr - 0x%08x, val - 0x%08x\n",
861 			(u32)&ugeth->p_rx_glbl_pram->ecamptr,
862 			in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
863 		pr_info("l2qt            : addr - 0x%08x, val - 0x%08x\n",
864 			(u32)&ugeth->p_rx_glbl_pram->l2qt,
865 			in_be32(&ugeth->p_rx_glbl_pram->l2qt));
866 		pr_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x\n",
867 			(u32)&ugeth->p_rx_glbl_pram->l3qt[0],
868 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
869 		pr_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x\n",
870 			(u32)&ugeth->p_rx_glbl_pram->l3qt[1],
871 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
872 		pr_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x\n",
873 			(u32)&ugeth->p_rx_glbl_pram->l3qt[2],
874 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
875 		pr_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x\n",
876 			(u32)&ugeth->p_rx_glbl_pram->l3qt[3],
877 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
878 		pr_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x\n",
879 			(u32)&ugeth->p_rx_glbl_pram->l3qt[4],
880 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
881 		pr_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x\n",
882 			(u32)&ugeth->p_rx_glbl_pram->l3qt[5],
883 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
884 		pr_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x\n",
885 			(u32)&ugeth->p_rx_glbl_pram->l3qt[6],
886 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
887 		pr_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x\n",
888 			(u32)&ugeth->p_rx_glbl_pram->l3qt[7],
889 			in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
890 		pr_info("vlantype        : addr - 0x%08x, val - 0x%04x\n",
891 			(u32)&ugeth->p_rx_glbl_pram->vlantype,
892 			in_be16(&ugeth->p_rx_glbl_pram->vlantype));
893 		pr_info("vlantci         : addr - 0x%08x, val - 0x%04x\n",
894 			(u32)&ugeth->p_rx_glbl_pram->vlantci,
895 			in_be16(&ugeth->p_rx_glbl_pram->vlantci));
896 		for (i = 0; i < 64; i++)
897 			pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
898 				i,
899 				(u32)&ugeth->p_rx_glbl_pram->addressfiltering[i],
900 				ugeth->p_rx_glbl_pram->addressfiltering[i]);
901 		pr_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x\n",
902 			(u32)&ugeth->p_rx_glbl_pram->exfGlobalParam,
903 			in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
904 	}
905 	if (ugeth->p_send_q_mem_reg) {
906 		pr_info("Send Q memory registers:\n");
907 		pr_info("Base address: 0x%08x\n", (u32)ugeth->p_send_q_mem_reg);
908 		for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
909 			pr_info("SQQD[%d]:\n", i);
910 			pr_info("Base address: 0x%08x\n",
911 				(u32)&ugeth->p_send_q_mem_reg->sqqd[i]);
912 			mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
913 				 sizeof(struct ucc_geth_send_queue_qd));
914 		}
915 	}
916 	if (ugeth->p_scheduler) {
917 		pr_info("Scheduler:\n");
918 		pr_info("Base address: 0x%08x\n", (u32)ugeth->p_scheduler);
919 		mem_disp((u8 *) ugeth->p_scheduler,
920 			 sizeof(*ugeth->p_scheduler));
921 	}
922 	if (ugeth->p_tx_fw_statistics_pram) {
923 		pr_info("TX FW statistics pram:\n");
924 		pr_info("Base address: 0x%08x\n",
925 			(u32)ugeth->p_tx_fw_statistics_pram);
926 		mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
927 			 sizeof(*ugeth->p_tx_fw_statistics_pram));
928 	}
929 	if (ugeth->p_rx_fw_statistics_pram) {
930 		pr_info("RX FW statistics pram:\n");
931 		pr_info("Base address: 0x%08x\n",
932 			(u32)ugeth->p_rx_fw_statistics_pram);
933 		mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
934 			 sizeof(*ugeth->p_rx_fw_statistics_pram));
935 	}
936 	if (ugeth->p_rx_irq_coalescing_tbl) {
937 		pr_info("RX IRQ coalescing tables:\n");
938 		pr_info("Base address: 0x%08x\n",
939 			(u32)ugeth->p_rx_irq_coalescing_tbl);
940 		for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
941 			pr_info("RX IRQ coalescing table entry[%d]:\n", i);
942 			pr_info("Base address: 0x%08x\n",
943 				(u32)&ugeth->p_rx_irq_coalescing_tbl->
944 				coalescingentry[i]);
945 			pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
946 				(u32)&ugeth->p_rx_irq_coalescing_tbl->
947 				coalescingentry[i].interruptcoalescingmaxvalue,
948 				in_be32(&ugeth->p_rx_irq_coalescing_tbl->
949 					coalescingentry[i].
950 					interruptcoalescingmaxvalue));
951 			pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
952 				(u32)&ugeth->p_rx_irq_coalescing_tbl->
953 				coalescingentry[i].interruptcoalescingcounter,
954 				in_be32(&ugeth->p_rx_irq_coalescing_tbl->
955 					coalescingentry[i].
956 					interruptcoalescingcounter));
957 		}
958 	}
959 	if (ugeth->p_rx_bd_qs_tbl) {
960 		pr_info("RX BD QS tables:\n");
961 		pr_info("Base address: 0x%08x\n", (u32)ugeth->p_rx_bd_qs_tbl);
962 		for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
963 			pr_info("RX BD QS table[%d]:\n", i);
964 			pr_info("Base address: 0x%08x\n",
965 				(u32)&ugeth->p_rx_bd_qs_tbl[i]);
966 			pr_info("bdbaseptr        : addr - 0x%08x, val - 0x%08x\n",
967 				(u32)&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
968 				in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
969 			pr_info("bdptr            : addr - 0x%08x, val - 0x%08x\n",
970 				(u32)&ugeth->p_rx_bd_qs_tbl[i].bdptr,
971 				in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
972 			pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
973 				(u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
974 				in_be32(&ugeth->p_rx_bd_qs_tbl[i].
975 					externalbdbaseptr));
976 			pr_info("externalbdptr    : addr - 0x%08x, val - 0x%08x\n",
977 				(u32)&ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
978 				in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
979 			pr_info("ucode RX Prefetched BDs:\n");
980 			pr_info("Base address: 0x%08x\n",
981 				(u32)qe_muram_addr(in_be32
982 						   (&ugeth->p_rx_bd_qs_tbl[i].
983 						    bdbaseptr)));
984 			mem_disp((u8 *)
985 				 qe_muram_addr(in_be32
986 					       (&ugeth->p_rx_bd_qs_tbl[i].
987 						bdbaseptr)),
988 				 sizeof(struct ucc_geth_rx_prefetched_bds));
989 		}
990 	}
991 	if (ugeth->p_init_enet_param_shadow) {
992 		int size;
993 		pr_info("Init enet param shadow:\n");
994 		pr_info("Base address: 0x%08x\n",
995 			(u32) ugeth->p_init_enet_param_shadow);
996 		mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
997 			 sizeof(*ugeth->p_init_enet_param_shadow));
998 
999 		size = sizeof(struct ucc_geth_thread_rx_pram);
1000 		if (ugeth->ug_info->rxExtendedFiltering) {
1001 			size +=
1002 			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1003 			if (ugeth->ug_info->largestexternallookupkeysize ==
1004 			    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1005 				size +=
1006 			THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1007 			if (ugeth->ug_info->largestexternallookupkeysize ==
1008 			    QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1009 				size +=
1010 			THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1011 		}
1012 
1013 		dump_init_enet_entries(ugeth,
1014 				       &(ugeth->p_init_enet_param_shadow->
1015 					 txthread[0]),
1016 				       ENET_INIT_PARAM_MAX_ENTRIES_TX,
1017 				       sizeof(struct ucc_geth_thread_tx_pram),
1018 				       ugeth->ug_info->riscTx, 0);
1019 		dump_init_enet_entries(ugeth,
1020 				       &(ugeth->p_init_enet_param_shadow->
1021 					 rxthread[0]),
1022 				       ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1023 				       ugeth->ug_info->riscRx, 1);
1024 	}
1025 }
1026 #endif /* DEBUG */
1027 
1028 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1029 				  u32 __iomem *maccfg1_register,
1030 				  u32 __iomem *maccfg2_register)
1031 {
1032 	out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1033 	out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1034 	out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1035 }
1036 
1037 static int init_half_duplex_params(int alt_beb,
1038 				   int back_pressure_no_backoff,
1039 				   int no_backoff,
1040 				   int excess_defer,
1041 				   u8 alt_beb_truncation,
1042 				   u8 max_retransmissions,
1043 				   u8 collision_window,
1044 				   u32 __iomem *hafdup_register)
1045 {
1046 	u32 value = 0;
1047 
1048 	if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1049 	    (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1050 	    (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1051 		return -EINVAL;
1052 
1053 	value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1054 
1055 	if (alt_beb)
1056 		value |= HALFDUP_ALT_BEB;
1057 	if (back_pressure_no_backoff)
1058 		value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1059 	if (no_backoff)
1060 		value |= HALFDUP_NO_BACKOFF;
1061 	if (excess_defer)
1062 		value |= HALFDUP_EXCESSIVE_DEFER;
1063 
1064 	value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1065 
1066 	value |= collision_window;
1067 
1068 	out_be32(hafdup_register, value);
1069 	return 0;
1070 }
1071 
1072 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1073 				       u8 non_btb_ipg,
1074 				       u8 min_ifg,
1075 				       u8 btb_ipg,
1076 				       u32 __iomem *ipgifg_register)
1077 {
1078 	u32 value = 0;
1079 
1080 	/* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1081 	IPG part 2 */
1082 	if (non_btb_cs_ipg > non_btb_ipg)
1083 		return -EINVAL;
1084 
1085 	if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1086 	    (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1087 	    /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1088 	    (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1089 		return -EINVAL;
1090 
1091 	value |=
1092 	    ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1093 	     IPGIFG_NBTB_CS_IPG_MASK);
1094 	value |=
1095 	    ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1096 	     IPGIFG_NBTB_IPG_MASK);
1097 	value |=
1098 	    ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1099 	     IPGIFG_MIN_IFG_MASK);
1100 	value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1101 
1102 	out_be32(ipgifg_register, value);
1103 	return 0;
1104 }
1105 
1106 int init_flow_control_params(u32 automatic_flow_control_mode,
1107 				    int rx_flow_control_enable,
1108 				    int tx_flow_control_enable,
1109 				    u16 pause_period,
1110 				    u16 extension_field,
1111 				    u32 __iomem *upsmr_register,
1112 				    u32 __iomem *uempr_register,
1113 				    u32 __iomem *maccfg1_register)
1114 {
1115 	u32 value = 0;
1116 
1117 	/* Set UEMPR register */
1118 	value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1119 	value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1120 	out_be32(uempr_register, value);
1121 
1122 	/* Set UPSMR register */
1123 	setbits32(upsmr_register, automatic_flow_control_mode);
1124 
1125 	value = in_be32(maccfg1_register);
1126 	if (rx_flow_control_enable)
1127 		value |= MACCFG1_FLOW_RX;
1128 	if (tx_flow_control_enable)
1129 		value |= MACCFG1_FLOW_TX;
1130 	out_be32(maccfg1_register, value);
1131 
1132 	return 0;
1133 }
1134 
1135 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1136 					     int auto_zero_hardware_statistics,
1137 					     u32 __iomem *upsmr_register,
1138 					     u16 __iomem *uescr_register)
1139 {
1140 	u16 uescr_value = 0;
1141 
1142 	/* Enable hardware statistics gathering if requested */
1143 	if (enable_hardware_statistics)
1144 		setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1145 
1146 	/* Clear hardware statistics counters */
1147 	uescr_value = in_be16(uescr_register);
1148 	uescr_value |= UESCR_CLRCNT;
1149 	/* Automatically zero hardware statistics counters on read,
1150 	if requested */
1151 	if (auto_zero_hardware_statistics)
1152 		uescr_value |= UESCR_AUTOZ;
1153 	out_be16(uescr_register, uescr_value);
1154 
1155 	return 0;
1156 }
1157 
1158 static int init_firmware_statistics_gathering_mode(int
1159 		enable_tx_firmware_statistics,
1160 		int enable_rx_firmware_statistics,
1161 		u32 __iomem *tx_rmon_base_ptr,
1162 		u32 tx_firmware_statistics_structure_address,
1163 		u32 __iomem *rx_rmon_base_ptr,
1164 		u32 rx_firmware_statistics_structure_address,
1165 		u16 __iomem *temoder_register,
1166 		u32 __iomem *remoder_register)
1167 {
1168 	/* Note: this function does not check if */
1169 	/* the parameters it receives are NULL   */
1170 
1171 	if (enable_tx_firmware_statistics) {
1172 		out_be32(tx_rmon_base_ptr,
1173 			 tx_firmware_statistics_structure_address);
1174 		setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1175 	}
1176 
1177 	if (enable_rx_firmware_statistics) {
1178 		out_be32(rx_rmon_base_ptr,
1179 			 rx_firmware_statistics_structure_address);
1180 		setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1181 	}
1182 
1183 	return 0;
1184 }
1185 
1186 static int init_mac_station_addr_regs(u8 address_byte_0,
1187 				      u8 address_byte_1,
1188 				      u8 address_byte_2,
1189 				      u8 address_byte_3,
1190 				      u8 address_byte_4,
1191 				      u8 address_byte_5,
1192 				      u32 __iomem *macstnaddr1_register,
1193 				      u32 __iomem *macstnaddr2_register)
1194 {
1195 	u32 value = 0;
1196 
1197 	/* Example: for a station address of 0x12345678ABCD, */
1198 	/* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1199 
1200 	/* MACSTNADDR1 Register: */
1201 
1202 	/* 0                      7   8                      15  */
1203 	/* station address byte 5     station address byte 4     */
1204 	/* 16                     23  24                     31  */
1205 	/* station address byte 3     station address byte 2     */
1206 	value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1207 	value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1208 	value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1209 	value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1210 
1211 	out_be32(macstnaddr1_register, value);
1212 
1213 	/* MACSTNADDR2 Register: */
1214 
1215 	/* 0                      7   8                      15  */
1216 	/* station address byte 1     station address byte 0     */
1217 	/* 16                     23  24                     31  */
1218 	/*         reserved                   reserved           */
1219 	value = 0;
1220 	value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1221 	value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1222 
1223 	out_be32(macstnaddr2_register, value);
1224 
1225 	return 0;
1226 }
1227 
1228 static int init_check_frame_length_mode(int length_check,
1229 					u32 __iomem *maccfg2_register)
1230 {
1231 	u32 value = 0;
1232 
1233 	value = in_be32(maccfg2_register);
1234 
1235 	if (length_check)
1236 		value |= MACCFG2_LC;
1237 	else
1238 		value &= ~MACCFG2_LC;
1239 
1240 	out_be32(maccfg2_register, value);
1241 	return 0;
1242 }
1243 
1244 static int init_preamble_length(u8 preamble_length,
1245 				u32 __iomem *maccfg2_register)
1246 {
1247 	if ((preamble_length < 3) || (preamble_length > 7))
1248 		return -EINVAL;
1249 
1250 	clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1251 			preamble_length << MACCFG2_PREL_SHIFT);
1252 
1253 	return 0;
1254 }
1255 
1256 static int init_rx_parameters(int reject_broadcast,
1257 			      int receive_short_frames,
1258 			      int promiscuous, u32 __iomem *upsmr_register)
1259 {
1260 	u32 value = 0;
1261 
1262 	value = in_be32(upsmr_register);
1263 
1264 	if (reject_broadcast)
1265 		value |= UCC_GETH_UPSMR_BRO;
1266 	else
1267 		value &= ~UCC_GETH_UPSMR_BRO;
1268 
1269 	if (receive_short_frames)
1270 		value |= UCC_GETH_UPSMR_RSH;
1271 	else
1272 		value &= ~UCC_GETH_UPSMR_RSH;
1273 
1274 	if (promiscuous)
1275 		value |= UCC_GETH_UPSMR_PRO;
1276 	else
1277 		value &= ~UCC_GETH_UPSMR_PRO;
1278 
1279 	out_be32(upsmr_register, value);
1280 
1281 	return 0;
1282 }
1283 
1284 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1285 				u16 __iomem *mrblr_register)
1286 {
1287 	/* max_rx_buf_len value must be a multiple of 128 */
1288 	if ((max_rx_buf_len == 0) ||
1289 	    (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1290 		return -EINVAL;
1291 
1292 	out_be16(mrblr_register, max_rx_buf_len);
1293 	return 0;
1294 }
1295 
1296 static int init_min_frame_len(u16 min_frame_length,
1297 			      u16 __iomem *minflr_register,
1298 			      u16 __iomem *mrblr_register)
1299 {
1300 	u16 mrblr_value = 0;
1301 
1302 	mrblr_value = in_be16(mrblr_register);
1303 	if (min_frame_length >= (mrblr_value - 4))
1304 		return -EINVAL;
1305 
1306 	out_be16(minflr_register, min_frame_length);
1307 	return 0;
1308 }
1309 
1310 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1311 {
1312 	struct ucc_geth_info *ug_info;
1313 	struct ucc_geth __iomem *ug_regs;
1314 	struct ucc_fast __iomem *uf_regs;
1315 	int ret_val;
1316 	u32 upsmr, maccfg2;
1317 	u16 value;
1318 
1319 	ugeth_vdbg("%s: IN", __func__);
1320 
1321 	ug_info = ugeth->ug_info;
1322 	ug_regs = ugeth->ug_regs;
1323 	uf_regs = ugeth->uccf->uf_regs;
1324 
1325 	/*                    Set MACCFG2                    */
1326 	maccfg2 = in_be32(&ug_regs->maccfg2);
1327 	maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1328 	if ((ugeth->max_speed == SPEED_10) ||
1329 	    (ugeth->max_speed == SPEED_100))
1330 		maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1331 	else if (ugeth->max_speed == SPEED_1000)
1332 		maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1333 	maccfg2 |= ug_info->padAndCrc;
1334 	out_be32(&ug_regs->maccfg2, maccfg2);
1335 
1336 	/*                    Set UPSMR                      */
1337 	upsmr = in_be32(&uf_regs->upsmr);
1338 	upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1339 		   UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1340 	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1341 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1342 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1343 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1344 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1345 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1346 		if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1347 			upsmr |= UCC_GETH_UPSMR_RPM;
1348 		switch (ugeth->max_speed) {
1349 		case SPEED_10:
1350 			upsmr |= UCC_GETH_UPSMR_R10M;
1351 			fallthrough;
1352 		case SPEED_100:
1353 			if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1354 				upsmr |= UCC_GETH_UPSMR_RMM;
1355 		}
1356 	}
1357 	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1358 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1359 		upsmr |= UCC_GETH_UPSMR_TBIM;
1360 	}
1361 	if (ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII)
1362 		upsmr |= UCC_GETH_UPSMR_SGMM;
1363 
1364 	out_be32(&uf_regs->upsmr, upsmr);
1365 
1366 	/* Disable autonegotiation in tbi mode, because by default it
1367 	comes up in autonegotiation mode. */
1368 	/* Note that this depends on proper setting in utbipar register. */
1369 	if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1370 	    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1371 		struct ucc_geth_info *ug_info = ugeth->ug_info;
1372 		struct phy_device *tbiphy;
1373 
1374 		if (!ug_info->tbi_node)
1375 			pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1376 
1377 		tbiphy = of_phy_find_device(ug_info->tbi_node);
1378 		if (!tbiphy)
1379 			pr_warn("Could not get TBI device\n");
1380 
1381 		value = phy_read(tbiphy, ENET_TBI_MII_CR);
1382 		value &= ~0x1000;	/* Turn off autonegotiation */
1383 		phy_write(tbiphy, ENET_TBI_MII_CR, value);
1384 
1385 		put_device(&tbiphy->mdio.dev);
1386 	}
1387 
1388 	init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1389 
1390 	ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1391 	if (ret_val != 0) {
1392 		if (netif_msg_probe(ugeth))
1393 			pr_err("Preamble length must be between 3 and 7 inclusive\n");
1394 		return ret_val;
1395 	}
1396 
1397 	return 0;
1398 }
1399 
1400 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1401 {
1402 	struct ucc_fast_private *uccf;
1403 	u32 cecr_subblock;
1404 	u32 temp;
1405 	int i = 10;
1406 
1407 	uccf = ugeth->uccf;
1408 
1409 	/* Mask GRACEFUL STOP TX interrupt bit and clear it */
1410 	clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1411 	out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1412 
1413 	/* Issue host command */
1414 	cecr_subblock =
1415 	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1416 	qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1417 		     QE_CR_PROTOCOL_ETHERNET, 0);
1418 
1419 	/* Wait for command to complete */
1420 	do {
1421 		msleep(10);
1422 		temp = in_be32(uccf->p_ucce);
1423 	} while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1424 
1425 	uccf->stopped_tx = 1;
1426 
1427 	return 0;
1428 }
1429 
1430 static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1431 {
1432 	struct ucc_fast_private *uccf;
1433 	u32 cecr_subblock;
1434 	u8 temp;
1435 	int i = 10;
1436 
1437 	uccf = ugeth->uccf;
1438 
1439 	/* Clear acknowledge bit */
1440 	temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1441 	temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1442 	out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1443 
1444 	/* Keep issuing command and checking acknowledge bit until
1445 	it is asserted, according to spec */
1446 	do {
1447 		/* Issue host command */
1448 		cecr_subblock =
1449 		    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1450 						ucc_num);
1451 		qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1452 			     QE_CR_PROTOCOL_ETHERNET, 0);
1453 		msleep(10);
1454 		temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1455 	} while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1456 
1457 	uccf->stopped_rx = 1;
1458 
1459 	return 0;
1460 }
1461 
1462 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1463 {
1464 	struct ucc_fast_private *uccf;
1465 	u32 cecr_subblock;
1466 
1467 	uccf = ugeth->uccf;
1468 
1469 	cecr_subblock =
1470 	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1471 	qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1472 	uccf->stopped_tx = 0;
1473 
1474 	return 0;
1475 }
1476 
1477 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1478 {
1479 	struct ucc_fast_private *uccf;
1480 	u32 cecr_subblock;
1481 
1482 	uccf = ugeth->uccf;
1483 
1484 	cecr_subblock =
1485 	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1486 	qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1487 		     0);
1488 	uccf->stopped_rx = 0;
1489 
1490 	return 0;
1491 }
1492 
1493 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1494 {
1495 	struct ucc_fast_private *uccf;
1496 	int enabled_tx, enabled_rx;
1497 
1498 	uccf = ugeth->uccf;
1499 
1500 	/* check if the UCC number is in range. */
1501 	if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1502 		if (netif_msg_probe(ugeth))
1503 			pr_err("ucc_num out of range\n");
1504 		return -EINVAL;
1505 	}
1506 
1507 	enabled_tx = uccf->enabled_tx;
1508 	enabled_rx = uccf->enabled_rx;
1509 
1510 	/* Get Tx and Rx going again, in case this channel was actively
1511 	disabled. */
1512 	if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1513 		ugeth_restart_tx(ugeth);
1514 	if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1515 		ugeth_restart_rx(ugeth);
1516 
1517 	ucc_fast_enable(uccf, mode);	/* OK to do even if not disabled */
1518 
1519 	return 0;
1520 
1521 }
1522 
1523 static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1524 {
1525 	struct ucc_fast_private *uccf;
1526 
1527 	uccf = ugeth->uccf;
1528 
1529 	/* check if the UCC number is in range. */
1530 	if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1531 		if (netif_msg_probe(ugeth))
1532 			pr_err("ucc_num out of range\n");
1533 		return -EINVAL;
1534 	}
1535 
1536 	/* Stop any transmissions */
1537 	if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1538 		ugeth_graceful_stop_tx(ugeth);
1539 
1540 	/* Stop any receptions */
1541 	if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1542 		ugeth_graceful_stop_rx(ugeth);
1543 
1544 	ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1545 
1546 	return 0;
1547 }
1548 
1549 static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1550 {
1551 	/* Prevent any further xmits */
1552 	netif_tx_stop_all_queues(ugeth->ndev);
1553 
1554 	/* Disable the interrupt to avoid NAPI rescheduling. */
1555 	disable_irq(ugeth->ug_info->uf_info.irq);
1556 
1557 	/* Stop NAPI, and possibly wait for its completion. */
1558 	napi_disable(&ugeth->napi);
1559 }
1560 
1561 static void ugeth_activate(struct ucc_geth_private *ugeth)
1562 {
1563 	napi_enable(&ugeth->napi);
1564 	enable_irq(ugeth->ug_info->uf_info.irq);
1565 
1566 	/* allow to xmit again  */
1567 	netif_tx_wake_all_queues(ugeth->ndev);
1568 	__netdev_watchdog_up(ugeth->ndev);
1569 }
1570 
1571 /* Called every time the controller might need to be made
1572  * aware of new link state.  The PHY code conveys this
1573  * information through variables in the ugeth structure, and this
1574  * function converts those variables into the appropriate
1575  * register values, and can bring down the device if needed.
1576  */
1577 
1578 static void adjust_link(struct net_device *dev)
1579 {
1580 	struct ucc_geth_private *ugeth = netdev_priv(dev);
1581 	struct ucc_geth __iomem *ug_regs;
1582 	struct ucc_fast __iomem *uf_regs;
1583 	struct phy_device *phydev = ugeth->phydev;
1584 	int new_state = 0;
1585 
1586 	ug_regs = ugeth->ug_regs;
1587 	uf_regs = ugeth->uccf->uf_regs;
1588 
1589 	if (phydev->link) {
1590 		u32 tempval = in_be32(&ug_regs->maccfg2);
1591 		u32 upsmr = in_be32(&uf_regs->upsmr);
1592 		/* Now we make sure that we can be in full duplex mode.
1593 		 * If not, we operate in half-duplex mode. */
1594 		if (phydev->duplex != ugeth->oldduplex) {
1595 			new_state = 1;
1596 			if (!(phydev->duplex))
1597 				tempval &= ~(MACCFG2_FDX);
1598 			else
1599 				tempval |= MACCFG2_FDX;
1600 			ugeth->oldduplex = phydev->duplex;
1601 		}
1602 
1603 		if (phydev->speed != ugeth->oldspeed) {
1604 			new_state = 1;
1605 			switch (phydev->speed) {
1606 			case SPEED_1000:
1607 				tempval = ((tempval &
1608 					    ~(MACCFG2_INTERFACE_MODE_MASK)) |
1609 					    MACCFG2_INTERFACE_MODE_BYTE);
1610 				break;
1611 			case SPEED_100:
1612 			case SPEED_10:
1613 				tempval = ((tempval &
1614 					    ~(MACCFG2_INTERFACE_MODE_MASK)) |
1615 					    MACCFG2_INTERFACE_MODE_NIBBLE);
1616 				/* if reduced mode, re-set UPSMR.R10M */
1617 				if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1618 				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1619 				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1620 				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1621 				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1622 				    (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1623 					if (phydev->speed == SPEED_10)
1624 						upsmr |= UCC_GETH_UPSMR_R10M;
1625 					else
1626 						upsmr &= ~UCC_GETH_UPSMR_R10M;
1627 				}
1628 				break;
1629 			default:
1630 				if (netif_msg_link(ugeth))
1631 					pr_warn(
1632 						"%s: Ack!  Speed (%d) is not 10/100/1000!",
1633 						dev->name, phydev->speed);
1634 				break;
1635 			}
1636 			ugeth->oldspeed = phydev->speed;
1637 		}
1638 
1639 		if (!ugeth->oldlink) {
1640 			new_state = 1;
1641 			ugeth->oldlink = 1;
1642 		}
1643 
1644 		if (new_state) {
1645 			/*
1646 			 * To change the MAC configuration we need to disable
1647 			 * the controller. To do so, we have to either grab
1648 			 * ugeth->lock, which is a bad idea since 'graceful
1649 			 * stop' commands might take quite a while, or we can
1650 			 * quiesce driver's activity.
1651 			 */
1652 			ugeth_quiesce(ugeth);
1653 			ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1654 
1655 			out_be32(&ug_regs->maccfg2, tempval);
1656 			out_be32(&uf_regs->upsmr, upsmr);
1657 
1658 			ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1659 			ugeth_activate(ugeth);
1660 		}
1661 	} else if (ugeth->oldlink) {
1662 			new_state = 1;
1663 			ugeth->oldlink = 0;
1664 			ugeth->oldspeed = 0;
1665 			ugeth->oldduplex = -1;
1666 	}
1667 
1668 	if (new_state && netif_msg_link(ugeth))
1669 		phy_print_status(phydev);
1670 }
1671 
1672 /* Initialize TBI PHY interface for communicating with the
1673  * SERDES lynx PHY on the chip.  We communicate with this PHY
1674  * through the MDIO bus on each controller, treating it as a
1675  * "normal" PHY at the address found in the UTBIPA register.  We assume
1676  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1677  * it to a value that doesn't conflict with other PHYs on the bus, or the
1678  * value doesn't matter, as there are no other PHYs on the bus.
1679  */
1680 static void uec_configure_serdes(struct net_device *dev)
1681 {
1682 	struct ucc_geth_private *ugeth = netdev_priv(dev);
1683 	struct ucc_geth_info *ug_info = ugeth->ug_info;
1684 	struct phy_device *tbiphy;
1685 
1686 	if (!ug_info->tbi_node) {
1687 		dev_warn(&dev->dev, "SGMII mode requires that the device "
1688 			"tree specify a tbi-handle\n");
1689 		return;
1690 	}
1691 
1692 	tbiphy = of_phy_find_device(ug_info->tbi_node);
1693 	if (!tbiphy) {
1694 		dev_err(&dev->dev, "error: Could not get TBI device\n");
1695 		return;
1696 	}
1697 
1698 	/*
1699 	 * If the link is already up, we must already be ok, and don't need to
1700 	 * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1701 	 * everything for us?  Resetting it takes the link down and requires
1702 	 * several seconds for it to come back.
1703 	 */
1704 	if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS) {
1705 		put_device(&tbiphy->mdio.dev);
1706 		return;
1707 	}
1708 
1709 	/* Single clk mode, mii mode off(for serdes communication) */
1710 	phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1711 
1712 	phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1713 
1714 	phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1715 
1716 	put_device(&tbiphy->mdio.dev);
1717 }
1718 
1719 /* Configure the PHY for dev.
1720  * returns 0 if success.  -1 if failure
1721  */
1722 static int init_phy(struct net_device *dev)
1723 {
1724 	struct ucc_geth_private *priv = netdev_priv(dev);
1725 	struct ucc_geth_info *ug_info = priv->ug_info;
1726 	struct phy_device *phydev;
1727 
1728 	priv->oldlink = 0;
1729 	priv->oldspeed = 0;
1730 	priv->oldduplex = -1;
1731 
1732 	phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1733 				priv->phy_interface);
1734 	if (!phydev) {
1735 		dev_err(&dev->dev, "Could not attach to PHY\n");
1736 		return -ENODEV;
1737 	}
1738 
1739 	if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1740 		uec_configure_serdes(dev);
1741 
1742 	phy_set_max_speed(phydev, priv->max_speed);
1743 
1744 	priv->phydev = phydev;
1745 
1746 	return 0;
1747 }
1748 
1749 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1750 {
1751 #ifdef DEBUG
1752 	ucc_fast_dump_regs(ugeth->uccf);
1753 	dump_regs(ugeth);
1754 	dump_bds(ugeth);
1755 #endif
1756 }
1757 
1758 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1759 						       ugeth,
1760 						       enum enet_addr_type
1761 						       enet_addr_type)
1762 {
1763 	struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1764 	struct ucc_fast_private *uccf;
1765 	enum comm_dir comm_dir;
1766 	struct list_head *p_lh;
1767 	u16 i, num;
1768 	u32 __iomem *addr_h;
1769 	u32 __iomem *addr_l;
1770 	u8 *p_counter;
1771 
1772 	uccf = ugeth->uccf;
1773 
1774 	p_82xx_addr_filt =
1775 	    (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1776 	    ugeth->p_rx_glbl_pram->addressfiltering;
1777 
1778 	if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1779 		addr_h = &(p_82xx_addr_filt->gaddr_h);
1780 		addr_l = &(p_82xx_addr_filt->gaddr_l);
1781 		p_lh = &ugeth->group_hash_q;
1782 		p_counter = &(ugeth->numGroupAddrInHash);
1783 	} else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1784 		addr_h = &(p_82xx_addr_filt->iaddr_h);
1785 		addr_l = &(p_82xx_addr_filt->iaddr_l);
1786 		p_lh = &ugeth->ind_hash_q;
1787 		p_counter = &(ugeth->numIndAddrInHash);
1788 	} else
1789 		return -EINVAL;
1790 
1791 	comm_dir = 0;
1792 	if (uccf->enabled_tx)
1793 		comm_dir |= COMM_DIR_TX;
1794 	if (uccf->enabled_rx)
1795 		comm_dir |= COMM_DIR_RX;
1796 	if (comm_dir)
1797 		ugeth_disable(ugeth, comm_dir);
1798 
1799 	/* Clear the hash table. */
1800 	out_be32(addr_h, 0x00000000);
1801 	out_be32(addr_l, 0x00000000);
1802 
1803 	if (!p_lh)
1804 		return 0;
1805 
1806 	num = *p_counter;
1807 
1808 	/* Delete all remaining CQ elements */
1809 	for (i = 0; i < num; i++)
1810 		put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1811 
1812 	*p_counter = 0;
1813 
1814 	if (comm_dir)
1815 		ugeth_enable(ugeth, comm_dir);
1816 
1817 	return 0;
1818 }
1819 
1820 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1821 						    u8 paddr_num)
1822 {
1823 	ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1824 	return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1825 }
1826 
1827 static void ucc_geth_free_rx(struct ucc_geth_private *ugeth)
1828 {
1829 	struct ucc_geth_info *ug_info;
1830 	struct ucc_fast_info *uf_info;
1831 	u16 i, j;
1832 	u8 __iomem *bd;
1833 
1834 
1835 	ug_info = ugeth->ug_info;
1836 	uf_info = &ug_info->uf_info;
1837 
1838 	for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1839 		if (ugeth->p_rx_bd_ring[i]) {
1840 			/* Return existing data buffers in ring */
1841 			bd = ugeth->p_rx_bd_ring[i];
1842 			for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1843 				if (ugeth->rx_skbuff[i][j]) {
1844 					dma_unmap_single(ugeth->dev,
1845 						in_be32(&((struct qe_bd __iomem *)bd)->buf),
1846 						ugeth->ug_info->
1847 						uf_info.max_rx_buf_length +
1848 						UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1849 						DMA_FROM_DEVICE);
1850 					dev_kfree_skb_any(
1851 						ugeth->rx_skbuff[i][j]);
1852 					ugeth->rx_skbuff[i][j] = NULL;
1853 				}
1854 				bd += sizeof(struct qe_bd);
1855 			}
1856 
1857 			kfree(ugeth->rx_skbuff[i]);
1858 
1859 			if (ugeth->ug_info->uf_info.bd_mem_part ==
1860 			    MEM_PART_SYSTEM)
1861 				kfree((void *)ugeth->rx_bd_ring_offset[i]);
1862 			else if (ugeth->ug_info->uf_info.bd_mem_part ==
1863 				 MEM_PART_MURAM)
1864 				qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1865 			ugeth->p_rx_bd_ring[i] = NULL;
1866 		}
1867 	}
1868 
1869 }
1870 
1871 static void ucc_geth_free_tx(struct ucc_geth_private *ugeth)
1872 {
1873 	struct ucc_geth_info *ug_info;
1874 	struct ucc_fast_info *uf_info;
1875 	u16 i, j;
1876 	u8 __iomem *bd;
1877 
1878 	netdev_reset_queue(ugeth->ndev);
1879 
1880 	ug_info = ugeth->ug_info;
1881 	uf_info = &ug_info->uf_info;
1882 
1883 	for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1884 		bd = ugeth->p_tx_bd_ring[i];
1885 		if (!bd)
1886 			continue;
1887 		for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1888 			if (ugeth->tx_skbuff[i][j]) {
1889 				dma_unmap_single(ugeth->dev,
1890 						 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1891 						 (in_be32((u32 __iomem *)bd) &
1892 						  BD_LENGTH_MASK),
1893 						 DMA_TO_DEVICE);
1894 				dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1895 				ugeth->tx_skbuff[i][j] = NULL;
1896 			}
1897 		}
1898 
1899 		kfree(ugeth->tx_skbuff[i]);
1900 
1901 		if (ugeth->p_tx_bd_ring[i]) {
1902 			if (ugeth->ug_info->uf_info.bd_mem_part ==
1903 			    MEM_PART_SYSTEM)
1904 				kfree((void *)ugeth->tx_bd_ring_offset[i]);
1905 			else if (ugeth->ug_info->uf_info.bd_mem_part ==
1906 				 MEM_PART_MURAM)
1907 				qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1908 			ugeth->p_tx_bd_ring[i] = NULL;
1909 		}
1910 	}
1911 
1912 }
1913 
1914 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1915 {
1916 	if (!ugeth)
1917 		return;
1918 
1919 	if (ugeth->uccf) {
1920 		ucc_fast_free(ugeth->uccf);
1921 		ugeth->uccf = NULL;
1922 	}
1923 
1924 	if (ugeth->p_thread_data_tx) {
1925 		qe_muram_free(ugeth->thread_dat_tx_offset);
1926 		ugeth->p_thread_data_tx = NULL;
1927 	}
1928 	if (ugeth->p_thread_data_rx) {
1929 		qe_muram_free(ugeth->thread_dat_rx_offset);
1930 		ugeth->p_thread_data_rx = NULL;
1931 	}
1932 	if (ugeth->p_exf_glbl_param) {
1933 		qe_muram_free(ugeth->exf_glbl_param_offset);
1934 		ugeth->p_exf_glbl_param = NULL;
1935 	}
1936 	if (ugeth->p_rx_glbl_pram) {
1937 		qe_muram_free(ugeth->rx_glbl_pram_offset);
1938 		ugeth->p_rx_glbl_pram = NULL;
1939 	}
1940 	if (ugeth->p_tx_glbl_pram) {
1941 		qe_muram_free(ugeth->tx_glbl_pram_offset);
1942 		ugeth->p_tx_glbl_pram = NULL;
1943 	}
1944 	if (ugeth->p_send_q_mem_reg) {
1945 		qe_muram_free(ugeth->send_q_mem_reg_offset);
1946 		ugeth->p_send_q_mem_reg = NULL;
1947 	}
1948 	if (ugeth->p_scheduler) {
1949 		qe_muram_free(ugeth->scheduler_offset);
1950 		ugeth->p_scheduler = NULL;
1951 	}
1952 	if (ugeth->p_tx_fw_statistics_pram) {
1953 		qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1954 		ugeth->p_tx_fw_statistics_pram = NULL;
1955 	}
1956 	if (ugeth->p_rx_fw_statistics_pram) {
1957 		qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1958 		ugeth->p_rx_fw_statistics_pram = NULL;
1959 	}
1960 	if (ugeth->p_rx_irq_coalescing_tbl) {
1961 		qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1962 		ugeth->p_rx_irq_coalescing_tbl = NULL;
1963 	}
1964 	if (ugeth->p_rx_bd_qs_tbl) {
1965 		qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1966 		ugeth->p_rx_bd_qs_tbl = NULL;
1967 	}
1968 	if (ugeth->p_init_enet_param_shadow) {
1969 		return_init_enet_entries(ugeth,
1970 					 &(ugeth->p_init_enet_param_shadow->
1971 					   rxthread[0]),
1972 					 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1973 					 ugeth->ug_info->riscRx, 1);
1974 		return_init_enet_entries(ugeth,
1975 					 &(ugeth->p_init_enet_param_shadow->
1976 					   txthread[0]),
1977 					 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1978 					 ugeth->ug_info->riscTx, 0);
1979 		kfree(ugeth->p_init_enet_param_shadow);
1980 		ugeth->p_init_enet_param_shadow = NULL;
1981 	}
1982 	ucc_geth_free_tx(ugeth);
1983 	ucc_geth_free_rx(ugeth);
1984 	while (!list_empty(&ugeth->group_hash_q))
1985 		put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1986 					(dequeue(&ugeth->group_hash_q)));
1987 	while (!list_empty(&ugeth->ind_hash_q))
1988 		put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1989 					(dequeue(&ugeth->ind_hash_q)));
1990 	if (ugeth->ug_regs) {
1991 		iounmap(ugeth->ug_regs);
1992 		ugeth->ug_regs = NULL;
1993 	}
1994 }
1995 
1996 static void ucc_geth_set_multi(struct net_device *dev)
1997 {
1998 	struct ucc_geth_private *ugeth;
1999 	struct netdev_hw_addr *ha;
2000 	struct ucc_fast __iomem *uf_regs;
2001 	struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2002 
2003 	ugeth = netdev_priv(dev);
2004 
2005 	uf_regs = ugeth->uccf->uf_regs;
2006 
2007 	if (dev->flags & IFF_PROMISC) {
2008 		setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2009 	} else {
2010 		clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
2011 
2012 		p_82xx_addr_filt =
2013 		    (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2014 		    p_rx_glbl_pram->addressfiltering;
2015 
2016 		if (dev->flags & IFF_ALLMULTI) {
2017 			/* Catch all multicast addresses, so set the
2018 			 * filter to all 1's.
2019 			 */
2020 			out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2021 			out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2022 		} else {
2023 			/* Clear filter and add the addresses in the list.
2024 			 */
2025 			out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2026 			out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2027 
2028 			netdev_for_each_mc_addr(ha, dev) {
2029 				/* Ask CPM to run CRC and set bit in
2030 				 * filter mask.
2031 				 */
2032 				hw_add_addr_in_hash(ugeth, ha->addr);
2033 			}
2034 		}
2035 	}
2036 }
2037 
2038 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2039 {
2040 	struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2041 	struct phy_device *phydev = ugeth->phydev;
2042 
2043 	ugeth_vdbg("%s: IN", __func__);
2044 
2045 	/*
2046 	 * Tell the kernel the link is down.
2047 	 * Must be done before disabling the controller
2048 	 * or deadlock may happen.
2049 	 */
2050 	phy_stop(phydev);
2051 
2052 	/* Disable the controller */
2053 	ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2054 
2055 	/* Mask all interrupts */
2056 	out_be32(ugeth->uccf->p_uccm, 0x00000000);
2057 
2058 	/* Clear all interrupts */
2059 	out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2060 
2061 	/* Disable Rx and Tx */
2062 	clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2063 
2064 	ucc_geth_memclean(ugeth);
2065 }
2066 
2067 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2068 {
2069 	struct ucc_geth_info *ug_info;
2070 	struct ucc_fast_info *uf_info;
2071 	int i;
2072 
2073 	ug_info = ugeth->ug_info;
2074 	uf_info = &ug_info->uf_info;
2075 
2076 	if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2077 	      (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2078 		if (netif_msg_probe(ugeth))
2079 			pr_err("Bad memory partition value\n");
2080 		return -EINVAL;
2081 	}
2082 
2083 	/* Rx BD lengths */
2084 	for (i = 0; i < ug_info->numQueuesRx; i++) {
2085 		if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2086 		    (ug_info->bdRingLenRx[i] %
2087 		     UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2088 			if (netif_msg_probe(ugeth))
2089 				pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2090 			return -EINVAL;
2091 		}
2092 	}
2093 
2094 	/* Tx BD lengths */
2095 	for (i = 0; i < ug_info->numQueuesTx; i++) {
2096 		if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2097 			if (netif_msg_probe(ugeth))
2098 				pr_err("Tx BD ring length must be no smaller than 2\n");
2099 			return -EINVAL;
2100 		}
2101 	}
2102 
2103 	/* mrblr */
2104 	if ((uf_info->max_rx_buf_length == 0) ||
2105 	    (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2106 		if (netif_msg_probe(ugeth))
2107 			pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2108 		return -EINVAL;
2109 	}
2110 
2111 	/* num Tx queues */
2112 	if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2113 		if (netif_msg_probe(ugeth))
2114 			pr_err("number of tx queues too large\n");
2115 		return -EINVAL;
2116 	}
2117 
2118 	/* num Rx queues */
2119 	if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2120 		if (netif_msg_probe(ugeth))
2121 			pr_err("number of rx queues too large\n");
2122 		return -EINVAL;
2123 	}
2124 
2125 	/* l2qt */
2126 	for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2127 		if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2128 			if (netif_msg_probe(ugeth))
2129 				pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2130 			return -EINVAL;
2131 		}
2132 	}
2133 
2134 	/* l3qt */
2135 	for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2136 		if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2137 			if (netif_msg_probe(ugeth))
2138 				pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2139 			return -EINVAL;
2140 		}
2141 	}
2142 
2143 	if (ug_info->cam && !ug_info->ecamptr) {
2144 		if (netif_msg_probe(ugeth))
2145 			pr_err("If cam mode is chosen, must supply cam ptr\n");
2146 		return -EINVAL;
2147 	}
2148 
2149 	if ((ug_info->numStationAddresses !=
2150 	     UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2151 	    ug_info->rxExtendedFiltering) {
2152 		if (netif_msg_probe(ugeth))
2153 			pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2154 		return -EINVAL;
2155 	}
2156 
2157 	/* Generate uccm_mask for receive */
2158 	uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2159 	for (i = 0; i < ug_info->numQueuesRx; i++)
2160 		uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2161 
2162 	for (i = 0; i < ug_info->numQueuesTx; i++)
2163 		uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2164 	/* Initialize the general fast UCC block. */
2165 	if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2166 		if (netif_msg_probe(ugeth))
2167 			pr_err("Failed to init uccf\n");
2168 		return -ENOMEM;
2169 	}
2170 
2171 	/* read the number of risc engines, update the riscTx and riscRx
2172 	 * if there are 4 riscs in QE
2173 	 */
2174 	if (qe_get_num_of_risc() == 4) {
2175 		ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2176 		ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2177 	}
2178 
2179 	ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2180 	if (!ugeth->ug_regs) {
2181 		if (netif_msg_probe(ugeth))
2182 			pr_err("Failed to ioremap regs\n");
2183 		return -ENOMEM;
2184 	}
2185 
2186 	return 0;
2187 }
2188 
2189 static int ucc_geth_alloc_tx(struct ucc_geth_private *ugeth)
2190 {
2191 	struct ucc_geth_info *ug_info;
2192 	struct ucc_fast_info *uf_info;
2193 	int length;
2194 	u16 i, j;
2195 	u8 __iomem *bd;
2196 
2197 	ug_info = ugeth->ug_info;
2198 	uf_info = &ug_info->uf_info;
2199 
2200 	/* Allocate Tx bds */
2201 	for (j = 0; j < ug_info->numQueuesTx; j++) {
2202 		/* Allocate in multiple of
2203 		   UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2204 		   according to spec */
2205 		length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2206 			  / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2207 		    * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2208 		if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2209 		    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2210 			length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2211 		if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2212 			u32 align = 4;
2213 			if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2214 				align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2215 			ugeth->tx_bd_ring_offset[j] =
2216 				(u32) kmalloc((u32) (length + align), GFP_KERNEL);
2217 
2218 			if (ugeth->tx_bd_ring_offset[j] != 0)
2219 				ugeth->p_tx_bd_ring[j] =
2220 					(u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2221 					align) & ~(align - 1));
2222 		} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2223 			ugeth->tx_bd_ring_offset[j] =
2224 			    qe_muram_alloc(length,
2225 					   UCC_GETH_TX_BD_RING_ALIGNMENT);
2226 			if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2227 				ugeth->p_tx_bd_ring[j] =
2228 				    (u8 __iomem *) qe_muram_addr(ugeth->
2229 							 tx_bd_ring_offset[j]);
2230 		}
2231 		if (!ugeth->p_tx_bd_ring[j]) {
2232 			if (netif_msg_ifup(ugeth))
2233 				pr_err("Can not allocate memory for Tx bd rings\n");
2234 			return -ENOMEM;
2235 		}
2236 		/* Zero unused end of bd ring, according to spec */
2237 		memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2238 		       ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2239 		       length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2240 	}
2241 
2242 	/* Init Tx bds */
2243 	for (j = 0; j < ug_info->numQueuesTx; j++) {
2244 		/* Setup the skbuff rings */
2245 		ugeth->tx_skbuff[j] =
2246 			kmalloc_array(ugeth->ug_info->bdRingLenTx[j],
2247 				      sizeof(struct sk_buff *), GFP_KERNEL);
2248 
2249 		if (ugeth->tx_skbuff[j] == NULL) {
2250 			if (netif_msg_ifup(ugeth))
2251 				pr_err("Could not allocate tx_skbuff\n");
2252 			return -ENOMEM;
2253 		}
2254 
2255 		for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2256 			ugeth->tx_skbuff[j][i] = NULL;
2257 
2258 		ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2259 		bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2260 		for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2261 			/* clear bd buffer */
2262 			out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2263 			/* set bd status and length */
2264 			out_be32((u32 __iomem *)bd, 0);
2265 			bd += sizeof(struct qe_bd);
2266 		}
2267 		bd -= sizeof(struct qe_bd);
2268 		/* set bd status and length */
2269 		out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2270 	}
2271 
2272 	return 0;
2273 }
2274 
2275 static int ucc_geth_alloc_rx(struct ucc_geth_private *ugeth)
2276 {
2277 	struct ucc_geth_info *ug_info;
2278 	struct ucc_fast_info *uf_info;
2279 	int length;
2280 	u16 i, j;
2281 	u8 __iomem *bd;
2282 
2283 	ug_info = ugeth->ug_info;
2284 	uf_info = &ug_info->uf_info;
2285 
2286 	/* Allocate Rx bds */
2287 	for (j = 0; j < ug_info->numQueuesRx; j++) {
2288 		length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2289 		if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2290 			u32 align = 4;
2291 			if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2292 				align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2293 			ugeth->rx_bd_ring_offset[j] =
2294 				(u32) kmalloc((u32) (length + align), GFP_KERNEL);
2295 			if (ugeth->rx_bd_ring_offset[j] != 0)
2296 				ugeth->p_rx_bd_ring[j] =
2297 					(u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2298 					align) & ~(align - 1));
2299 		} else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2300 			ugeth->rx_bd_ring_offset[j] =
2301 			    qe_muram_alloc(length,
2302 					   UCC_GETH_RX_BD_RING_ALIGNMENT);
2303 			if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2304 				ugeth->p_rx_bd_ring[j] =
2305 				    (u8 __iomem *) qe_muram_addr(ugeth->
2306 							 rx_bd_ring_offset[j]);
2307 		}
2308 		if (!ugeth->p_rx_bd_ring[j]) {
2309 			if (netif_msg_ifup(ugeth))
2310 				pr_err("Can not allocate memory for Rx bd rings\n");
2311 			return -ENOMEM;
2312 		}
2313 	}
2314 
2315 	/* Init Rx bds */
2316 	for (j = 0; j < ug_info->numQueuesRx; j++) {
2317 		/* Setup the skbuff rings */
2318 		ugeth->rx_skbuff[j] =
2319 			kmalloc_array(ugeth->ug_info->bdRingLenRx[j],
2320 				      sizeof(struct sk_buff *), GFP_KERNEL);
2321 
2322 		if (ugeth->rx_skbuff[j] == NULL) {
2323 			if (netif_msg_ifup(ugeth))
2324 				pr_err("Could not allocate rx_skbuff\n");
2325 			return -ENOMEM;
2326 		}
2327 
2328 		for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2329 			ugeth->rx_skbuff[j][i] = NULL;
2330 
2331 		ugeth->skb_currx[j] = 0;
2332 		bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2333 		for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2334 			/* set bd status and length */
2335 			out_be32((u32 __iomem *)bd, R_I);
2336 			/* clear bd buffer */
2337 			out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2338 			bd += sizeof(struct qe_bd);
2339 		}
2340 		bd -= sizeof(struct qe_bd);
2341 		/* set bd status and length */
2342 		out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2343 	}
2344 
2345 	return 0;
2346 }
2347 
2348 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2349 {
2350 	struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2351 	struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2352 	struct ucc_fast_private *uccf;
2353 	struct ucc_geth_info *ug_info;
2354 	struct ucc_fast_info *uf_info;
2355 	struct ucc_fast __iomem *uf_regs;
2356 	struct ucc_geth __iomem *ug_regs;
2357 	int ret_val = -EINVAL;
2358 	u32 remoder = UCC_GETH_REMODER_INIT;
2359 	u32 init_enet_pram_offset, cecr_subblock, command;
2360 	u32 ifstat, i, j, size, l2qt, l3qt;
2361 	u16 temoder = UCC_GETH_TEMODER_INIT;
2362 	u16 test;
2363 	u8 function_code = 0;
2364 	u8 __iomem *endOfRing;
2365 	u8 numThreadsRxNumerical, numThreadsTxNumerical;
2366 
2367 	ugeth_vdbg("%s: IN", __func__);
2368 	uccf = ugeth->uccf;
2369 	ug_info = ugeth->ug_info;
2370 	uf_info = &ug_info->uf_info;
2371 	uf_regs = uccf->uf_regs;
2372 	ug_regs = ugeth->ug_regs;
2373 
2374 	switch (ug_info->numThreadsRx) {
2375 	case UCC_GETH_NUM_OF_THREADS_1:
2376 		numThreadsRxNumerical = 1;
2377 		break;
2378 	case UCC_GETH_NUM_OF_THREADS_2:
2379 		numThreadsRxNumerical = 2;
2380 		break;
2381 	case UCC_GETH_NUM_OF_THREADS_4:
2382 		numThreadsRxNumerical = 4;
2383 		break;
2384 	case UCC_GETH_NUM_OF_THREADS_6:
2385 		numThreadsRxNumerical = 6;
2386 		break;
2387 	case UCC_GETH_NUM_OF_THREADS_8:
2388 		numThreadsRxNumerical = 8;
2389 		break;
2390 	default:
2391 		if (netif_msg_ifup(ugeth))
2392 			pr_err("Bad number of Rx threads value\n");
2393 		return -EINVAL;
2394 	}
2395 
2396 	switch (ug_info->numThreadsTx) {
2397 	case UCC_GETH_NUM_OF_THREADS_1:
2398 		numThreadsTxNumerical = 1;
2399 		break;
2400 	case UCC_GETH_NUM_OF_THREADS_2:
2401 		numThreadsTxNumerical = 2;
2402 		break;
2403 	case UCC_GETH_NUM_OF_THREADS_4:
2404 		numThreadsTxNumerical = 4;
2405 		break;
2406 	case UCC_GETH_NUM_OF_THREADS_6:
2407 		numThreadsTxNumerical = 6;
2408 		break;
2409 	case UCC_GETH_NUM_OF_THREADS_8:
2410 		numThreadsTxNumerical = 8;
2411 		break;
2412 	default:
2413 		if (netif_msg_ifup(ugeth))
2414 			pr_err("Bad number of Tx threads value\n");
2415 		return -EINVAL;
2416 	}
2417 
2418 	/* Calculate rx_extended_features */
2419 	ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2420 	    ug_info->ipAddressAlignment ||
2421 	    (ug_info->numStationAddresses !=
2422 	     UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2423 
2424 	ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2425 		(ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2426 		(ug_info->vlanOperationNonTagged !=
2427 		 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2428 
2429 	init_default_reg_vals(&uf_regs->upsmr,
2430 			      &ug_regs->maccfg1, &ug_regs->maccfg2);
2431 
2432 	/*                    Set UPSMR                      */
2433 	/* For more details see the hardware spec.           */
2434 	init_rx_parameters(ug_info->bro,
2435 			   ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2436 
2437 	/* We're going to ignore other registers for now, */
2438 	/* except as needed to get up and running         */
2439 
2440 	/*                    Set MACCFG1                    */
2441 	/* For more details see the hardware spec.           */
2442 	init_flow_control_params(ug_info->aufc,
2443 				 ug_info->receiveFlowControl,
2444 				 ug_info->transmitFlowControl,
2445 				 ug_info->pausePeriod,
2446 				 ug_info->extensionField,
2447 				 &uf_regs->upsmr,
2448 				 &ug_regs->uempr, &ug_regs->maccfg1);
2449 
2450 	setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2451 
2452 	/*                    Set IPGIFG                     */
2453 	/* For more details see the hardware spec.           */
2454 	ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2455 					      ug_info->nonBackToBackIfgPart2,
2456 					      ug_info->
2457 					      miminumInterFrameGapEnforcement,
2458 					      ug_info->backToBackInterFrameGap,
2459 					      &ug_regs->ipgifg);
2460 	if (ret_val != 0) {
2461 		if (netif_msg_ifup(ugeth))
2462 			pr_err("IPGIFG initialization parameter too large\n");
2463 		return ret_val;
2464 	}
2465 
2466 	/*                    Set HAFDUP                     */
2467 	/* For more details see the hardware spec.           */
2468 	ret_val = init_half_duplex_params(ug_info->altBeb,
2469 					  ug_info->backPressureNoBackoff,
2470 					  ug_info->noBackoff,
2471 					  ug_info->excessDefer,
2472 					  ug_info->altBebTruncation,
2473 					  ug_info->maxRetransmission,
2474 					  ug_info->collisionWindow,
2475 					  &ug_regs->hafdup);
2476 	if (ret_val != 0) {
2477 		if (netif_msg_ifup(ugeth))
2478 			pr_err("Half Duplex initialization parameter too large\n");
2479 		return ret_val;
2480 	}
2481 
2482 	/*                    Set IFSTAT                     */
2483 	/* For more details see the hardware spec.           */
2484 	/* Read only - resets upon read                      */
2485 	ifstat = in_be32(&ug_regs->ifstat);
2486 
2487 	/*                    Clear UEMPR                    */
2488 	/* For more details see the hardware spec.           */
2489 	out_be32(&ug_regs->uempr, 0);
2490 
2491 	/*                    Set UESCR                      */
2492 	/* For more details see the hardware spec.           */
2493 	init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2494 				UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2495 				0, &uf_regs->upsmr, &ug_regs->uescr);
2496 
2497 	ret_val = ucc_geth_alloc_tx(ugeth);
2498 	if (ret_val != 0)
2499 		return ret_val;
2500 
2501 	ret_val = ucc_geth_alloc_rx(ugeth);
2502 	if (ret_val != 0)
2503 		return ret_val;
2504 
2505 	/*
2506 	 * Global PRAM
2507 	 */
2508 	/* Tx global PRAM */
2509 	/* Allocate global tx parameter RAM page */
2510 	ugeth->tx_glbl_pram_offset =
2511 	    qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2512 			   UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2513 	if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2514 		if (netif_msg_ifup(ugeth))
2515 			pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2516 		return -ENOMEM;
2517 	}
2518 	ugeth->p_tx_glbl_pram =
2519 	    (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2520 							tx_glbl_pram_offset);
2521 	/* Zero out p_tx_glbl_pram */
2522 	memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2523 
2524 	/* Fill global PRAM */
2525 
2526 	/* TQPTR */
2527 	/* Size varies with number of Tx threads */
2528 	ugeth->thread_dat_tx_offset =
2529 	    qe_muram_alloc(numThreadsTxNumerical *
2530 			   sizeof(struct ucc_geth_thread_data_tx) +
2531 			   32 * (numThreadsTxNumerical == 1),
2532 			   UCC_GETH_THREAD_DATA_ALIGNMENT);
2533 	if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2534 		if (netif_msg_ifup(ugeth))
2535 			pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2536 		return -ENOMEM;
2537 	}
2538 
2539 	ugeth->p_thread_data_tx =
2540 	    (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2541 							thread_dat_tx_offset);
2542 	out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2543 
2544 	/* vtagtable */
2545 	for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2546 		out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2547 			 ug_info->vtagtable[i]);
2548 
2549 	/* iphoffset */
2550 	for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2551 		out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2552 				ug_info->iphoffset[i]);
2553 
2554 	/* SQPTR */
2555 	/* Size varies with number of Tx queues */
2556 	ugeth->send_q_mem_reg_offset =
2557 	    qe_muram_alloc(ug_info->numQueuesTx *
2558 			   sizeof(struct ucc_geth_send_queue_qd),
2559 			   UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2560 	if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2561 		if (netif_msg_ifup(ugeth))
2562 			pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2563 		return -ENOMEM;
2564 	}
2565 
2566 	ugeth->p_send_q_mem_reg =
2567 	    (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2568 			send_q_mem_reg_offset);
2569 	out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2570 
2571 	/* Setup the table */
2572 	/* Assume BD rings are already established */
2573 	for (i = 0; i < ug_info->numQueuesTx; i++) {
2574 		endOfRing =
2575 		    ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2576 					      1) * sizeof(struct qe_bd);
2577 		if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2578 			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2579 				 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2580 			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2581 				 last_bd_completed_address,
2582 				 (u32) virt_to_phys(endOfRing));
2583 		} else if (ugeth->ug_info->uf_info.bd_mem_part ==
2584 			   MEM_PART_MURAM) {
2585 			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2586 				 (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
2587 			out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2588 				 last_bd_completed_address,
2589 				 (u32)qe_muram_dma(endOfRing));
2590 		}
2591 	}
2592 
2593 	/* schedulerbasepointer */
2594 
2595 	if (ug_info->numQueuesTx > 1) {
2596 	/* scheduler exists only if more than 1 tx queue */
2597 		ugeth->scheduler_offset =
2598 		    qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2599 				   UCC_GETH_SCHEDULER_ALIGNMENT);
2600 		if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2601 			if (netif_msg_ifup(ugeth))
2602 				pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2603 			return -ENOMEM;
2604 		}
2605 
2606 		ugeth->p_scheduler =
2607 		    (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2608 							   scheduler_offset);
2609 		out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2610 			 ugeth->scheduler_offset);
2611 		/* Zero out p_scheduler */
2612 		memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2613 
2614 		/* Set values in scheduler */
2615 		out_be32(&ugeth->p_scheduler->mblinterval,
2616 			 ug_info->mblinterval);
2617 		out_be16(&ugeth->p_scheduler->nortsrbytetime,
2618 			 ug_info->nortsrbytetime);
2619 		out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2620 		out_8(&ugeth->p_scheduler->strictpriorityq,
2621 				ug_info->strictpriorityq);
2622 		out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2623 		out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2624 		for (i = 0; i < NUM_TX_QUEUES; i++)
2625 			out_8(&ugeth->p_scheduler->weightfactor[i],
2626 			    ug_info->weightfactor[i]);
2627 
2628 		/* Set pointers to cpucount registers in scheduler */
2629 		ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2630 		ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2631 		ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2632 		ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2633 		ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2634 		ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2635 		ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2636 		ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2637 	}
2638 
2639 	/* schedulerbasepointer */
2640 	/* TxRMON_PTR (statistics) */
2641 	if (ug_info->
2642 	    statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2643 		ugeth->tx_fw_statistics_pram_offset =
2644 		    qe_muram_alloc(sizeof
2645 				   (struct ucc_geth_tx_firmware_statistics_pram),
2646 				   UCC_GETH_TX_STATISTICS_ALIGNMENT);
2647 		if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2648 			if (netif_msg_ifup(ugeth))
2649 				pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2650 			return -ENOMEM;
2651 		}
2652 		ugeth->p_tx_fw_statistics_pram =
2653 		    (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2654 		    qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2655 		/* Zero out p_tx_fw_statistics_pram */
2656 		memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2657 		       0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2658 	}
2659 
2660 	/* temoder */
2661 	/* Already has speed set */
2662 
2663 	if (ug_info->numQueuesTx > 1)
2664 		temoder |= TEMODER_SCHEDULER_ENABLE;
2665 	if (ug_info->ipCheckSumGenerate)
2666 		temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2667 	temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2668 	out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2669 
2670 	test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2671 
2672 	/* Function code register value to be used later */
2673 	function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2674 	/* Required for QE */
2675 
2676 	/* function code register */
2677 	out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2678 
2679 	/* Rx global PRAM */
2680 	/* Allocate global rx parameter RAM page */
2681 	ugeth->rx_glbl_pram_offset =
2682 	    qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2683 			   UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2684 	if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2685 		if (netif_msg_ifup(ugeth))
2686 			pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2687 		return -ENOMEM;
2688 	}
2689 	ugeth->p_rx_glbl_pram =
2690 	    (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2691 							rx_glbl_pram_offset);
2692 	/* Zero out p_rx_glbl_pram */
2693 	memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2694 
2695 	/* Fill global PRAM */
2696 
2697 	/* RQPTR */
2698 	/* Size varies with number of Rx threads */
2699 	ugeth->thread_dat_rx_offset =
2700 	    qe_muram_alloc(numThreadsRxNumerical *
2701 			   sizeof(struct ucc_geth_thread_data_rx),
2702 			   UCC_GETH_THREAD_DATA_ALIGNMENT);
2703 	if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2704 		if (netif_msg_ifup(ugeth))
2705 			pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2706 		return -ENOMEM;
2707 	}
2708 
2709 	ugeth->p_thread_data_rx =
2710 	    (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2711 							thread_dat_rx_offset);
2712 	out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2713 
2714 	/* typeorlen */
2715 	out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2716 
2717 	/* rxrmonbaseptr (statistics) */
2718 	if (ug_info->
2719 	    statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2720 		ugeth->rx_fw_statistics_pram_offset =
2721 		    qe_muram_alloc(sizeof
2722 				   (struct ucc_geth_rx_firmware_statistics_pram),
2723 				   UCC_GETH_RX_STATISTICS_ALIGNMENT);
2724 		if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2725 			if (netif_msg_ifup(ugeth))
2726 				pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2727 			return -ENOMEM;
2728 		}
2729 		ugeth->p_rx_fw_statistics_pram =
2730 		    (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2731 		    qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2732 		/* Zero out p_rx_fw_statistics_pram */
2733 		memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2734 		       sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2735 	}
2736 
2737 	/* intCoalescingPtr */
2738 
2739 	/* Size varies with number of Rx queues */
2740 	ugeth->rx_irq_coalescing_tbl_offset =
2741 	    qe_muram_alloc(ug_info->numQueuesRx *
2742 			   sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2743 			   + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2744 	if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2745 		if (netif_msg_ifup(ugeth))
2746 			pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2747 		return -ENOMEM;
2748 	}
2749 
2750 	ugeth->p_rx_irq_coalescing_tbl =
2751 	    (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2752 	    qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2753 	out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2754 		 ugeth->rx_irq_coalescing_tbl_offset);
2755 
2756 	/* Fill interrupt coalescing table */
2757 	for (i = 0; i < ug_info->numQueuesRx; i++) {
2758 		out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2759 			 interruptcoalescingmaxvalue,
2760 			 ug_info->interruptcoalescingmaxvalue[i]);
2761 		out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2762 			 interruptcoalescingcounter,
2763 			 ug_info->interruptcoalescingmaxvalue[i]);
2764 	}
2765 
2766 	/* MRBLR */
2767 	init_max_rx_buff_len(uf_info->max_rx_buf_length,
2768 			     &ugeth->p_rx_glbl_pram->mrblr);
2769 	/* MFLR */
2770 	out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2771 	/* MINFLR */
2772 	init_min_frame_len(ug_info->minFrameLength,
2773 			   &ugeth->p_rx_glbl_pram->minflr,
2774 			   &ugeth->p_rx_glbl_pram->mrblr);
2775 	/* MAXD1 */
2776 	out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2777 	/* MAXD2 */
2778 	out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2779 
2780 	/* l2qt */
2781 	l2qt = 0;
2782 	for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2783 		l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2784 	out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2785 
2786 	/* l3qt */
2787 	for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2788 		l3qt = 0;
2789 		for (i = 0; i < 8; i++)
2790 			l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2791 		out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2792 	}
2793 
2794 	/* vlantype */
2795 	out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2796 
2797 	/* vlantci */
2798 	out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2799 
2800 	/* ecamptr */
2801 	out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2802 
2803 	/* RBDQPTR */
2804 	/* Size varies with number of Rx queues */
2805 	ugeth->rx_bd_qs_tbl_offset =
2806 	    qe_muram_alloc(ug_info->numQueuesRx *
2807 			   (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2808 			    sizeof(struct ucc_geth_rx_prefetched_bds)),
2809 			   UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2810 	if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2811 		if (netif_msg_ifup(ugeth))
2812 			pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2813 		return -ENOMEM;
2814 	}
2815 
2816 	ugeth->p_rx_bd_qs_tbl =
2817 	    (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2818 				    rx_bd_qs_tbl_offset);
2819 	out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2820 	/* Zero out p_rx_bd_qs_tbl */
2821 	memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2822 	       0,
2823 	       ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2824 				       sizeof(struct ucc_geth_rx_prefetched_bds)));
2825 
2826 	/* Setup the table */
2827 	/* Assume BD rings are already established */
2828 	for (i = 0; i < ug_info->numQueuesRx; i++) {
2829 		if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2830 			out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2831 				 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2832 		} else if (ugeth->ug_info->uf_info.bd_mem_part ==
2833 			   MEM_PART_MURAM) {
2834 			out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2835 				 (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
2836 		}
2837 		/* rest of fields handled by QE */
2838 	}
2839 
2840 	/* remoder */
2841 	/* Already has speed set */
2842 
2843 	if (ugeth->rx_extended_features)
2844 		remoder |= REMODER_RX_EXTENDED_FEATURES;
2845 	if (ug_info->rxExtendedFiltering)
2846 		remoder |= REMODER_RX_EXTENDED_FILTERING;
2847 	if (ug_info->dynamicMaxFrameLength)
2848 		remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2849 	if (ug_info->dynamicMinFrameLength)
2850 		remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2851 	remoder |=
2852 	    ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2853 	remoder |=
2854 	    ug_info->
2855 	    vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2856 	remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2857 	remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2858 	if (ug_info->ipCheckSumCheck)
2859 		remoder |= REMODER_IP_CHECKSUM_CHECK;
2860 	if (ug_info->ipAddressAlignment)
2861 		remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2862 	out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2863 
2864 	/* Note that this function must be called */
2865 	/* ONLY AFTER p_tx_fw_statistics_pram */
2866 	/* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2867 	init_firmware_statistics_gathering_mode((ug_info->
2868 		statisticsMode &
2869 		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2870 		(ug_info->statisticsMode &
2871 		UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2872 		&ugeth->p_tx_glbl_pram->txrmonbaseptr,
2873 		ugeth->tx_fw_statistics_pram_offset,
2874 		&ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2875 		ugeth->rx_fw_statistics_pram_offset,
2876 		&ugeth->p_tx_glbl_pram->temoder,
2877 		&ugeth->p_rx_glbl_pram->remoder);
2878 
2879 	/* function code register */
2880 	out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2881 
2882 	/* initialize extended filtering */
2883 	if (ug_info->rxExtendedFiltering) {
2884 		if (!ug_info->extendedFilteringChainPointer) {
2885 			if (netif_msg_ifup(ugeth))
2886 				pr_err("Null Extended Filtering Chain Pointer\n");
2887 			return -EINVAL;
2888 		}
2889 
2890 		/* Allocate memory for extended filtering Mode Global
2891 		Parameters */
2892 		ugeth->exf_glbl_param_offset =
2893 		    qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2894 		UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2895 		if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2896 			if (netif_msg_ifup(ugeth))
2897 				pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2898 			return -ENOMEM;
2899 		}
2900 
2901 		ugeth->p_exf_glbl_param =
2902 		    (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2903 				 exf_glbl_param_offset);
2904 		out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2905 			 ugeth->exf_glbl_param_offset);
2906 		out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2907 			 (u32) ug_info->extendedFilteringChainPointer);
2908 
2909 	} else {		/* initialize 82xx style address filtering */
2910 
2911 		/* Init individual address recognition registers to disabled */
2912 
2913 		for (j = 0; j < NUM_OF_PADDRS; j++)
2914 			ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2915 
2916 		p_82xx_addr_filt =
2917 		    (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2918 		    p_rx_glbl_pram->addressfiltering;
2919 
2920 		ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2921 			ENET_ADDR_TYPE_GROUP);
2922 		ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2923 			ENET_ADDR_TYPE_INDIVIDUAL);
2924 	}
2925 
2926 	/*
2927 	 * Initialize UCC at QE level
2928 	 */
2929 
2930 	command = QE_INIT_TX_RX;
2931 
2932 	/* Allocate shadow InitEnet command parameter structure.
2933 	 * This is needed because after the InitEnet command is executed,
2934 	 * the structure in DPRAM is released, because DPRAM is a premium
2935 	 * resource.
2936 	 * This shadow structure keeps a copy of what was done so that the
2937 	 * allocated resources can be released when the channel is freed.
2938 	 */
2939 	if (!(ugeth->p_init_enet_param_shadow =
2940 	      kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2941 		if (netif_msg_ifup(ugeth))
2942 			pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2943 		return -ENOMEM;
2944 	}
2945 	/* Zero out *p_init_enet_param_shadow */
2946 	memset((char *)ugeth->p_init_enet_param_shadow,
2947 	       0, sizeof(struct ucc_geth_init_pram));
2948 
2949 	/* Fill shadow InitEnet command parameter structure */
2950 
2951 	ugeth->p_init_enet_param_shadow->resinit1 =
2952 	    ENET_INIT_PARAM_MAGIC_RES_INIT1;
2953 	ugeth->p_init_enet_param_shadow->resinit2 =
2954 	    ENET_INIT_PARAM_MAGIC_RES_INIT2;
2955 	ugeth->p_init_enet_param_shadow->resinit3 =
2956 	    ENET_INIT_PARAM_MAGIC_RES_INIT3;
2957 	ugeth->p_init_enet_param_shadow->resinit4 =
2958 	    ENET_INIT_PARAM_MAGIC_RES_INIT4;
2959 	ugeth->p_init_enet_param_shadow->resinit5 =
2960 	    ENET_INIT_PARAM_MAGIC_RES_INIT5;
2961 	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2962 	    ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2963 	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2964 	    ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2965 
2966 	ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2967 	    ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2968 	if ((ug_info->largestexternallookupkeysize !=
2969 	     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2970 	    (ug_info->largestexternallookupkeysize !=
2971 	     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2972 	    (ug_info->largestexternallookupkeysize !=
2973 	     QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2974 		if (netif_msg_ifup(ugeth))
2975 			pr_err("Invalid largest External Lookup Key Size\n");
2976 		return -EINVAL;
2977 	}
2978 	ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2979 	    ug_info->largestexternallookupkeysize;
2980 	size = sizeof(struct ucc_geth_thread_rx_pram);
2981 	if (ug_info->rxExtendedFiltering) {
2982 		size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2983 		if (ug_info->largestexternallookupkeysize ==
2984 		    QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2985 			size +=
2986 			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2987 		if (ug_info->largestexternallookupkeysize ==
2988 		    QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2989 			size +=
2990 			    THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2991 	}
2992 
2993 	if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2994 		p_init_enet_param_shadow->rxthread[0]),
2995 		(u8) (numThreadsRxNumerical + 1)
2996 		/* Rx needs one extra for terminator */
2997 		, size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2998 		ug_info->riscRx, 1)) != 0) {
2999 		if (netif_msg_ifup(ugeth))
3000 			pr_err("Can not fill p_init_enet_param_shadow\n");
3001 		return ret_val;
3002 	}
3003 
3004 	ugeth->p_init_enet_param_shadow->txglobal =
3005 	    ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3006 	if ((ret_val =
3007 	     fill_init_enet_entries(ugeth,
3008 				    &(ugeth->p_init_enet_param_shadow->
3009 				      txthread[0]), numThreadsTxNumerical,
3010 				    sizeof(struct ucc_geth_thread_tx_pram),
3011 				    UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3012 				    ug_info->riscTx, 0)) != 0) {
3013 		if (netif_msg_ifup(ugeth))
3014 			pr_err("Can not fill p_init_enet_param_shadow\n");
3015 		return ret_val;
3016 	}
3017 
3018 	/* Load Rx bds with buffers */
3019 	for (i = 0; i < ug_info->numQueuesRx; i++) {
3020 		if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3021 			if (netif_msg_ifup(ugeth))
3022 				pr_err("Can not fill Rx bds with buffers\n");
3023 			return ret_val;
3024 		}
3025 	}
3026 
3027 	/* Allocate InitEnet command parameter structure */
3028 	init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3029 	if (IS_ERR_VALUE(init_enet_pram_offset)) {
3030 		if (netif_msg_ifup(ugeth))
3031 			pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
3032 		return -ENOMEM;
3033 	}
3034 	p_init_enet_pram =
3035 	    (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3036 
3037 	/* Copy shadow InitEnet command parameter structure into PRAM */
3038 	out_8(&p_init_enet_pram->resinit1,
3039 			ugeth->p_init_enet_param_shadow->resinit1);
3040 	out_8(&p_init_enet_pram->resinit2,
3041 			ugeth->p_init_enet_param_shadow->resinit2);
3042 	out_8(&p_init_enet_pram->resinit3,
3043 			ugeth->p_init_enet_param_shadow->resinit3);
3044 	out_8(&p_init_enet_pram->resinit4,
3045 			ugeth->p_init_enet_param_shadow->resinit4);
3046 	out_be16(&p_init_enet_pram->resinit5,
3047 		 ugeth->p_init_enet_param_shadow->resinit5);
3048 	out_8(&p_init_enet_pram->largestexternallookupkeysize,
3049 	    ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3050 	out_be32(&p_init_enet_pram->rgftgfrxglobal,
3051 		 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3052 	for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3053 		out_be32(&p_init_enet_pram->rxthread[i],
3054 			 ugeth->p_init_enet_param_shadow->rxthread[i]);
3055 	out_be32(&p_init_enet_pram->txglobal,
3056 		 ugeth->p_init_enet_param_shadow->txglobal);
3057 	for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3058 		out_be32(&p_init_enet_pram->txthread[i],
3059 			 ugeth->p_init_enet_param_shadow->txthread[i]);
3060 
3061 	/* Issue QE command */
3062 	cecr_subblock =
3063 	    ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3064 	qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3065 		     init_enet_pram_offset);
3066 
3067 	/* Free InitEnet command parameter */
3068 	qe_muram_free(init_enet_pram_offset);
3069 
3070 	return 0;
3071 }
3072 
3073 /* This is called by the kernel when a frame is ready for transmission. */
3074 /* It is pointed to by the dev->hard_start_xmit function pointer */
3075 static netdev_tx_t
3076 ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3077 {
3078 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3079 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3080 	struct ucc_fast_private *uccf;
3081 #endif
3082 	u8 __iomem *bd;			/* BD pointer */
3083 	u32 bd_status;
3084 	u8 txQ = 0;
3085 	unsigned long flags;
3086 
3087 	ugeth_vdbg("%s: IN", __func__);
3088 
3089 	netdev_sent_queue(dev, skb->len);
3090 	spin_lock_irqsave(&ugeth->lock, flags);
3091 
3092 	dev->stats.tx_bytes += skb->len;
3093 
3094 	/* Start from the next BD that should be filled */
3095 	bd = ugeth->txBd[txQ];
3096 	bd_status = in_be32((u32 __iomem *)bd);
3097 	/* Save the skb pointer so we can free it later */
3098 	ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3099 
3100 	/* Update the current skb pointer (wrapping if this was the last) */
3101 	ugeth->skb_curtx[txQ] =
3102 	    (ugeth->skb_curtx[txQ] +
3103 	     1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3104 
3105 	/* set up the buffer descriptor */
3106 	out_be32(&((struct qe_bd __iomem *)bd)->buf,
3107 		      dma_map_single(ugeth->dev, skb->data,
3108 			      skb->len, DMA_TO_DEVICE));
3109 
3110 	/* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3111 
3112 	bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3113 
3114 	/* set bd status and length */
3115 	out_be32((u32 __iomem *)bd, bd_status);
3116 
3117 	/* Move to next BD in the ring */
3118 	if (!(bd_status & T_W))
3119 		bd += sizeof(struct qe_bd);
3120 	else
3121 		bd = ugeth->p_tx_bd_ring[txQ];
3122 
3123 	/* If the next BD still needs to be cleaned up, then the bds
3124 	   are full.  We need to tell the kernel to stop sending us stuff. */
3125 	if (bd == ugeth->confBd[txQ]) {
3126 		if (!netif_queue_stopped(dev))
3127 			netif_stop_queue(dev);
3128 	}
3129 
3130 	ugeth->txBd[txQ] = bd;
3131 
3132 	skb_tx_timestamp(skb);
3133 
3134 	if (ugeth->p_scheduler) {
3135 		ugeth->cpucount[txQ]++;
3136 		/* Indicate to QE that there are more Tx bds ready for
3137 		transmission */
3138 		/* This is done by writing a running counter of the bd
3139 		count to the scheduler PRAM. */
3140 		out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3141 	}
3142 
3143 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3144 	uccf = ugeth->uccf;
3145 	out_be16(uccf->p_utodr, UCC_FAST_TOD);
3146 #endif
3147 	spin_unlock_irqrestore(&ugeth->lock, flags);
3148 
3149 	return NETDEV_TX_OK;
3150 }
3151 
3152 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3153 {
3154 	struct sk_buff *skb;
3155 	u8 __iomem *bd;
3156 	u16 length, howmany = 0;
3157 	u32 bd_status;
3158 	u8 *bdBuffer;
3159 	struct net_device *dev;
3160 
3161 	ugeth_vdbg("%s: IN", __func__);
3162 
3163 	dev = ugeth->ndev;
3164 
3165 	/* collect received buffers */
3166 	bd = ugeth->rxBd[rxQ];
3167 
3168 	bd_status = in_be32((u32 __iomem *)bd);
3169 
3170 	/* while there are received buffers and BD is full (~R_E) */
3171 	while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3172 		bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3173 		length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3174 		skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3175 
3176 		/* determine whether buffer is first, last, first and last
3177 		(single buffer frame) or middle (not first and not last) */
3178 		if (!skb ||
3179 		    (!(bd_status & (R_F | R_L))) ||
3180 		    (bd_status & R_ERRORS_FATAL)) {
3181 			if (netif_msg_rx_err(ugeth))
3182 				pr_err("%d: ERROR!!! skb - 0x%08x\n",
3183 				       __LINE__, (u32)skb);
3184 			dev_kfree_skb(skb);
3185 
3186 			ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3187 			dev->stats.rx_dropped++;
3188 		} else {
3189 			dev->stats.rx_packets++;
3190 			howmany++;
3191 
3192 			/* Prep the skb for the packet */
3193 			skb_put(skb, length);
3194 
3195 			/* Tell the skb what kind of packet this is */
3196 			skb->protocol = eth_type_trans(skb, ugeth->ndev);
3197 
3198 			dev->stats.rx_bytes += length;
3199 			/* Send the packet up the stack */
3200 			netif_receive_skb(skb);
3201 		}
3202 
3203 		skb = get_new_skb(ugeth, bd);
3204 		if (!skb) {
3205 			if (netif_msg_rx_err(ugeth))
3206 				pr_warn("No Rx Data Buffer\n");
3207 			dev->stats.rx_dropped++;
3208 			break;
3209 		}
3210 
3211 		ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3212 
3213 		/* update to point at the next skb */
3214 		ugeth->skb_currx[rxQ] =
3215 		    (ugeth->skb_currx[rxQ] +
3216 		     1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3217 
3218 		if (bd_status & R_W)
3219 			bd = ugeth->p_rx_bd_ring[rxQ];
3220 		else
3221 			bd += sizeof(struct qe_bd);
3222 
3223 		bd_status = in_be32((u32 __iomem *)bd);
3224 	}
3225 
3226 	ugeth->rxBd[rxQ] = bd;
3227 	return howmany;
3228 }
3229 
3230 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3231 {
3232 	/* Start from the next BD that should be filled */
3233 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3234 	unsigned int bytes_sent = 0;
3235 	int howmany = 0;
3236 	u8 __iomem *bd;		/* BD pointer */
3237 	u32 bd_status;
3238 
3239 	bd = ugeth->confBd[txQ];
3240 	bd_status = in_be32((u32 __iomem *)bd);
3241 
3242 	/* Normal processing. */
3243 	while ((bd_status & T_R) == 0) {
3244 		struct sk_buff *skb;
3245 
3246 		/* BD contains already transmitted buffer.   */
3247 		/* Handle the transmitted buffer and release */
3248 		/* the BD to be used with the current frame  */
3249 
3250 		skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3251 		if (!skb)
3252 			break;
3253 		howmany++;
3254 		bytes_sent += skb->len;
3255 		dev->stats.tx_packets++;
3256 
3257 		dev_consume_skb_any(skb);
3258 
3259 		ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3260 		ugeth->skb_dirtytx[txQ] =
3261 		    (ugeth->skb_dirtytx[txQ] +
3262 		     1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3263 
3264 		/* We freed a buffer, so now we can restart transmission */
3265 		if (netif_queue_stopped(dev))
3266 			netif_wake_queue(dev);
3267 
3268 		/* Advance the confirmation BD pointer */
3269 		if (!(bd_status & T_W))
3270 			bd += sizeof(struct qe_bd);
3271 		else
3272 			bd = ugeth->p_tx_bd_ring[txQ];
3273 		bd_status = in_be32((u32 __iomem *)bd);
3274 	}
3275 	ugeth->confBd[txQ] = bd;
3276 	netdev_completed_queue(dev, howmany, bytes_sent);
3277 	return 0;
3278 }
3279 
3280 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3281 {
3282 	struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3283 	struct ucc_geth_info *ug_info;
3284 	int howmany, i;
3285 
3286 	ug_info = ugeth->ug_info;
3287 
3288 	/* Tx event processing */
3289 	spin_lock(&ugeth->lock);
3290 	for (i = 0; i < ug_info->numQueuesTx; i++)
3291 		ucc_geth_tx(ugeth->ndev, i);
3292 	spin_unlock(&ugeth->lock);
3293 
3294 	howmany = 0;
3295 	for (i = 0; i < ug_info->numQueuesRx; i++)
3296 		howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3297 
3298 	if (howmany < budget) {
3299 		napi_complete_done(napi, howmany);
3300 		setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3301 	}
3302 
3303 	return howmany;
3304 }
3305 
3306 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3307 {
3308 	struct net_device *dev = info;
3309 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3310 	struct ucc_fast_private *uccf;
3311 	struct ucc_geth_info *ug_info;
3312 	register u32 ucce;
3313 	register u32 uccm;
3314 
3315 	ugeth_vdbg("%s: IN", __func__);
3316 
3317 	uccf = ugeth->uccf;
3318 	ug_info = ugeth->ug_info;
3319 
3320 	/* read and clear events */
3321 	ucce = (u32) in_be32(uccf->p_ucce);
3322 	uccm = (u32) in_be32(uccf->p_uccm);
3323 	ucce &= uccm;
3324 	out_be32(uccf->p_ucce, ucce);
3325 
3326 	/* check for receive events that require processing */
3327 	if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3328 		if (napi_schedule_prep(&ugeth->napi)) {
3329 			uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3330 			out_be32(uccf->p_uccm, uccm);
3331 			__napi_schedule(&ugeth->napi);
3332 		}
3333 	}
3334 
3335 	/* Errors and other events */
3336 	if (ucce & UCCE_OTHER) {
3337 		if (ucce & UCC_GETH_UCCE_BSY)
3338 			dev->stats.rx_errors++;
3339 		if (ucce & UCC_GETH_UCCE_TXE)
3340 			dev->stats.tx_errors++;
3341 	}
3342 
3343 	return IRQ_HANDLED;
3344 }
3345 
3346 #ifdef CONFIG_NET_POLL_CONTROLLER
3347 /*
3348  * Polling 'interrupt' - used by things like netconsole to send skbs
3349  * without having to re-enable interrupts. It's not called while
3350  * the interrupt routine is executing.
3351  */
3352 static void ucc_netpoll(struct net_device *dev)
3353 {
3354 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3355 	int irq = ugeth->ug_info->uf_info.irq;
3356 
3357 	disable_irq(irq);
3358 	ucc_geth_irq_handler(irq, dev);
3359 	enable_irq(irq);
3360 }
3361 #endif /* CONFIG_NET_POLL_CONTROLLER */
3362 
3363 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3364 {
3365 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3366 	struct sockaddr *addr = p;
3367 
3368 	if (!is_valid_ether_addr(addr->sa_data))
3369 		return -EADDRNOTAVAIL;
3370 
3371 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3372 
3373 	/*
3374 	 * If device is not running, we will set mac addr register
3375 	 * when opening the device.
3376 	 */
3377 	if (!netif_running(dev))
3378 		return 0;
3379 
3380 	spin_lock_irq(&ugeth->lock);
3381 	init_mac_station_addr_regs(dev->dev_addr[0],
3382 				   dev->dev_addr[1],
3383 				   dev->dev_addr[2],
3384 				   dev->dev_addr[3],
3385 				   dev->dev_addr[4],
3386 				   dev->dev_addr[5],
3387 				   &ugeth->ug_regs->macstnaddr1,
3388 				   &ugeth->ug_regs->macstnaddr2);
3389 	spin_unlock_irq(&ugeth->lock);
3390 
3391 	return 0;
3392 }
3393 
3394 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3395 {
3396 	struct net_device *dev = ugeth->ndev;
3397 	int err;
3398 
3399 	err = ucc_struct_init(ugeth);
3400 	if (err) {
3401 		netif_err(ugeth, ifup, dev, "Cannot configure internal struct, aborting\n");
3402 		goto err;
3403 	}
3404 
3405 	err = ucc_geth_startup(ugeth);
3406 	if (err) {
3407 		netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3408 		goto err;
3409 	}
3410 
3411 	err = adjust_enet_interface(ugeth);
3412 	if (err) {
3413 		netif_err(ugeth, ifup, dev, "Cannot configure net device, aborting\n");
3414 		goto err;
3415 	}
3416 
3417 	/*       Set MACSTNADDR1, MACSTNADDR2                */
3418 	/* For more details see the hardware spec.           */
3419 	init_mac_station_addr_regs(dev->dev_addr[0],
3420 				   dev->dev_addr[1],
3421 				   dev->dev_addr[2],
3422 				   dev->dev_addr[3],
3423 				   dev->dev_addr[4],
3424 				   dev->dev_addr[5],
3425 				   &ugeth->ug_regs->macstnaddr1,
3426 				   &ugeth->ug_regs->macstnaddr2);
3427 
3428 	err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3429 	if (err) {
3430 		netif_err(ugeth, ifup, dev, "Cannot enable net device, aborting\n");
3431 		goto err;
3432 	}
3433 
3434 	return 0;
3435 err:
3436 	ucc_geth_stop(ugeth);
3437 	return err;
3438 }
3439 
3440 /* Called when something needs to use the ethernet device */
3441 /* Returns 0 for success. */
3442 static int ucc_geth_open(struct net_device *dev)
3443 {
3444 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3445 	int err;
3446 
3447 	ugeth_vdbg("%s: IN", __func__);
3448 
3449 	/* Test station address */
3450 	if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3451 		netif_err(ugeth, ifup, dev,
3452 			  "Multicast address used for station address - is this what you wanted?\n");
3453 		return -EINVAL;
3454 	}
3455 
3456 	err = init_phy(dev);
3457 	if (err) {
3458 		netif_err(ugeth, ifup, dev, "Cannot initialize PHY, aborting\n");
3459 		return err;
3460 	}
3461 
3462 	err = ucc_geth_init_mac(ugeth);
3463 	if (err) {
3464 		netif_err(ugeth, ifup, dev, "Cannot initialize MAC, aborting\n");
3465 		goto err;
3466 	}
3467 
3468 	err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3469 			  0, "UCC Geth", dev);
3470 	if (err) {
3471 		netif_err(ugeth, ifup, dev, "Cannot get IRQ for net device, aborting\n");
3472 		goto err;
3473 	}
3474 
3475 	phy_start(ugeth->phydev);
3476 	napi_enable(&ugeth->napi);
3477 	netdev_reset_queue(dev);
3478 	netif_start_queue(dev);
3479 
3480 	device_set_wakeup_capable(&dev->dev,
3481 			qe_alive_during_sleep() || ugeth->phydev->irq);
3482 	device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3483 
3484 	return err;
3485 
3486 err:
3487 	ucc_geth_stop(ugeth);
3488 	return err;
3489 }
3490 
3491 /* Stops the kernel queue, and halts the controller */
3492 static int ucc_geth_close(struct net_device *dev)
3493 {
3494 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3495 
3496 	ugeth_vdbg("%s: IN", __func__);
3497 
3498 	napi_disable(&ugeth->napi);
3499 
3500 	cancel_work_sync(&ugeth->timeout_work);
3501 	ucc_geth_stop(ugeth);
3502 	phy_disconnect(ugeth->phydev);
3503 	ugeth->phydev = NULL;
3504 
3505 	free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3506 
3507 	netif_stop_queue(dev);
3508 	netdev_reset_queue(dev);
3509 
3510 	return 0;
3511 }
3512 
3513 /* Reopen device. This will reset the MAC and PHY. */
3514 static void ucc_geth_timeout_work(struct work_struct *work)
3515 {
3516 	struct ucc_geth_private *ugeth;
3517 	struct net_device *dev;
3518 
3519 	ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3520 	dev = ugeth->ndev;
3521 
3522 	ugeth_vdbg("%s: IN", __func__);
3523 
3524 	dev->stats.tx_errors++;
3525 
3526 	ugeth_dump_regs(ugeth);
3527 
3528 	if (dev->flags & IFF_UP) {
3529 		/*
3530 		 * Must reset MAC *and* PHY. This is done by reopening
3531 		 * the device.
3532 		 */
3533 		netif_tx_stop_all_queues(dev);
3534 		ucc_geth_stop(ugeth);
3535 		ucc_geth_init_mac(ugeth);
3536 		/* Must start PHY here */
3537 		phy_start(ugeth->phydev);
3538 		netif_tx_start_all_queues(dev);
3539 	}
3540 
3541 	netif_tx_schedule_all(dev);
3542 }
3543 
3544 /*
3545  * ucc_geth_timeout gets called when a packet has not been
3546  * transmitted after a set amount of time.
3547  */
3548 static void ucc_geth_timeout(struct net_device *dev, unsigned int txqueue)
3549 {
3550 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3551 
3552 	schedule_work(&ugeth->timeout_work);
3553 }
3554 
3555 
3556 #ifdef CONFIG_PM
3557 
3558 static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
3559 {
3560 	struct net_device *ndev = platform_get_drvdata(ofdev);
3561 	struct ucc_geth_private *ugeth = netdev_priv(ndev);
3562 
3563 	if (!netif_running(ndev))
3564 		return 0;
3565 
3566 	netif_device_detach(ndev);
3567 	napi_disable(&ugeth->napi);
3568 
3569 	/*
3570 	 * Disable the controller, otherwise we'll wakeup on any network
3571 	 * activity.
3572 	 */
3573 	ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3574 
3575 	if (ugeth->wol_en & WAKE_MAGIC) {
3576 		setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3577 		setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3578 		ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3579 	} else if (!(ugeth->wol_en & WAKE_PHY)) {
3580 		phy_stop(ugeth->phydev);
3581 	}
3582 
3583 	return 0;
3584 }
3585 
3586 static int ucc_geth_resume(struct platform_device *ofdev)
3587 {
3588 	struct net_device *ndev = platform_get_drvdata(ofdev);
3589 	struct ucc_geth_private *ugeth = netdev_priv(ndev);
3590 	int err;
3591 
3592 	if (!netif_running(ndev))
3593 		return 0;
3594 
3595 	if (qe_alive_during_sleep()) {
3596 		if (ugeth->wol_en & WAKE_MAGIC) {
3597 			ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3598 			clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3599 			clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3600 		}
3601 		ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3602 	} else {
3603 		/*
3604 		 * Full reinitialization is required if QE shuts down
3605 		 * during sleep.
3606 		 */
3607 		ucc_geth_memclean(ugeth);
3608 
3609 		err = ucc_geth_init_mac(ugeth);
3610 		if (err) {
3611 			netdev_err(ndev, "Cannot initialize MAC, aborting\n");
3612 			return err;
3613 		}
3614 	}
3615 
3616 	ugeth->oldlink = 0;
3617 	ugeth->oldspeed = 0;
3618 	ugeth->oldduplex = -1;
3619 
3620 	phy_stop(ugeth->phydev);
3621 	phy_start(ugeth->phydev);
3622 
3623 	napi_enable(&ugeth->napi);
3624 	netif_device_attach(ndev);
3625 
3626 	return 0;
3627 }
3628 
3629 #else
3630 #define ucc_geth_suspend NULL
3631 #define ucc_geth_resume NULL
3632 #endif
3633 
3634 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3635 {
3636 	if (strcasecmp(phy_connection_type, "mii") == 0)
3637 		return PHY_INTERFACE_MODE_MII;
3638 	if (strcasecmp(phy_connection_type, "gmii") == 0)
3639 		return PHY_INTERFACE_MODE_GMII;
3640 	if (strcasecmp(phy_connection_type, "tbi") == 0)
3641 		return PHY_INTERFACE_MODE_TBI;
3642 	if (strcasecmp(phy_connection_type, "rmii") == 0)
3643 		return PHY_INTERFACE_MODE_RMII;
3644 	if (strcasecmp(phy_connection_type, "rgmii") == 0)
3645 		return PHY_INTERFACE_MODE_RGMII;
3646 	if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3647 		return PHY_INTERFACE_MODE_RGMII_ID;
3648 	if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3649 		return PHY_INTERFACE_MODE_RGMII_TXID;
3650 	if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3651 		return PHY_INTERFACE_MODE_RGMII_RXID;
3652 	if (strcasecmp(phy_connection_type, "rtbi") == 0)
3653 		return PHY_INTERFACE_MODE_RTBI;
3654 	if (strcasecmp(phy_connection_type, "sgmii") == 0)
3655 		return PHY_INTERFACE_MODE_SGMII;
3656 
3657 	return PHY_INTERFACE_MODE_MII;
3658 }
3659 
3660 static int ucc_geth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3661 {
3662 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3663 
3664 	if (!netif_running(dev))
3665 		return -EINVAL;
3666 
3667 	if (!ugeth->phydev)
3668 		return -ENODEV;
3669 
3670 	return phy_mii_ioctl(ugeth->phydev, rq, cmd);
3671 }
3672 
3673 static const struct net_device_ops ucc_geth_netdev_ops = {
3674 	.ndo_open		= ucc_geth_open,
3675 	.ndo_stop		= ucc_geth_close,
3676 	.ndo_start_xmit		= ucc_geth_start_xmit,
3677 	.ndo_validate_addr	= eth_validate_addr,
3678 	.ndo_change_carrier     = fixed_phy_change_carrier,
3679 	.ndo_set_mac_address	= ucc_geth_set_mac_addr,
3680 	.ndo_set_rx_mode	= ucc_geth_set_multi,
3681 	.ndo_tx_timeout		= ucc_geth_timeout,
3682 	.ndo_do_ioctl		= ucc_geth_ioctl,
3683 #ifdef CONFIG_NET_POLL_CONTROLLER
3684 	.ndo_poll_controller	= ucc_netpoll,
3685 #endif
3686 };
3687 
3688 static int ucc_geth_probe(struct platform_device* ofdev)
3689 {
3690 	struct device *device = &ofdev->dev;
3691 	struct device_node *np = ofdev->dev.of_node;
3692 	struct net_device *dev = NULL;
3693 	struct ucc_geth_private *ugeth = NULL;
3694 	struct ucc_geth_info *ug_info;
3695 	struct resource res;
3696 	int err, ucc_num, max_speed = 0;
3697 	const unsigned int *prop;
3698 	const char *sprop;
3699 	const void *mac_addr;
3700 	phy_interface_t phy_interface;
3701 	static const int enet_to_speed[] = {
3702 		SPEED_10, SPEED_10, SPEED_10,
3703 		SPEED_100, SPEED_100, SPEED_100,
3704 		SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3705 	};
3706 	static const phy_interface_t enet_to_phy_interface[] = {
3707 		PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3708 		PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3709 		PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3710 		PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3711 		PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3712 		PHY_INTERFACE_MODE_SGMII,
3713 	};
3714 
3715 	ugeth_vdbg("%s: IN", __func__);
3716 
3717 	prop = of_get_property(np, "cell-index", NULL);
3718 	if (!prop) {
3719 		prop = of_get_property(np, "device-id", NULL);
3720 		if (!prop)
3721 			return -ENODEV;
3722 	}
3723 
3724 	ucc_num = *prop - 1;
3725 	if ((ucc_num < 0) || (ucc_num > 7))
3726 		return -ENODEV;
3727 
3728 	ug_info = &ugeth_info[ucc_num];
3729 	if (ug_info == NULL) {
3730 		if (netif_msg_probe(&debug))
3731 			pr_err("[%d] Missing additional data!\n", ucc_num);
3732 		return -ENODEV;
3733 	}
3734 
3735 	ug_info->uf_info.ucc_num = ucc_num;
3736 
3737 	sprop = of_get_property(np, "rx-clock-name", NULL);
3738 	if (sprop) {
3739 		ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3740 		if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3741 		    (ug_info->uf_info.rx_clock > QE_CLK24)) {
3742 			pr_err("invalid rx-clock-name property\n");
3743 			return -EINVAL;
3744 		}
3745 	} else {
3746 		prop = of_get_property(np, "rx-clock", NULL);
3747 		if (!prop) {
3748 			/* If both rx-clock-name and rx-clock are missing,
3749 			   we want to tell people to use rx-clock-name. */
3750 			pr_err("missing rx-clock-name property\n");
3751 			return -EINVAL;
3752 		}
3753 		if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3754 			pr_err("invalid rx-clock property\n");
3755 			return -EINVAL;
3756 		}
3757 		ug_info->uf_info.rx_clock = *prop;
3758 	}
3759 
3760 	sprop = of_get_property(np, "tx-clock-name", NULL);
3761 	if (sprop) {
3762 		ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3763 		if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3764 		    (ug_info->uf_info.tx_clock > QE_CLK24)) {
3765 			pr_err("invalid tx-clock-name property\n");
3766 			return -EINVAL;
3767 		}
3768 	} else {
3769 		prop = of_get_property(np, "tx-clock", NULL);
3770 		if (!prop) {
3771 			pr_err("missing tx-clock-name property\n");
3772 			return -EINVAL;
3773 		}
3774 		if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3775 			pr_err("invalid tx-clock property\n");
3776 			return -EINVAL;
3777 		}
3778 		ug_info->uf_info.tx_clock = *prop;
3779 	}
3780 
3781 	err = of_address_to_resource(np, 0, &res);
3782 	if (err)
3783 		return -EINVAL;
3784 
3785 	ug_info->uf_info.regs = res.start;
3786 	ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3787 
3788 	ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3789 	if (!ug_info->phy_node && of_phy_is_fixed_link(np)) {
3790 		/*
3791 		 * In the case of a fixed PHY, the DT node associated
3792 		 * to the PHY is the Ethernet MAC DT node.
3793 		 */
3794 		err = of_phy_register_fixed_link(np);
3795 		if (err)
3796 			return err;
3797 		ug_info->phy_node = of_node_get(np);
3798 	}
3799 
3800 	/* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3801 	ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3802 
3803 	/* get the phy interface type, or default to MII */
3804 	prop = of_get_property(np, "phy-connection-type", NULL);
3805 	if (!prop) {
3806 		/* handle interface property present in old trees */
3807 		prop = of_get_property(ug_info->phy_node, "interface", NULL);
3808 		if (prop != NULL) {
3809 			phy_interface = enet_to_phy_interface[*prop];
3810 			max_speed = enet_to_speed[*prop];
3811 		} else
3812 			phy_interface = PHY_INTERFACE_MODE_MII;
3813 	} else {
3814 		phy_interface = to_phy_interface((const char *)prop);
3815 	}
3816 
3817 	/* get speed, or derive from PHY interface */
3818 	if (max_speed == 0)
3819 		switch (phy_interface) {
3820 		case PHY_INTERFACE_MODE_GMII:
3821 		case PHY_INTERFACE_MODE_RGMII:
3822 		case PHY_INTERFACE_MODE_RGMII_ID:
3823 		case PHY_INTERFACE_MODE_RGMII_RXID:
3824 		case PHY_INTERFACE_MODE_RGMII_TXID:
3825 		case PHY_INTERFACE_MODE_TBI:
3826 		case PHY_INTERFACE_MODE_RTBI:
3827 		case PHY_INTERFACE_MODE_SGMII:
3828 			max_speed = SPEED_1000;
3829 			break;
3830 		default:
3831 			max_speed = SPEED_100;
3832 			break;
3833 		}
3834 
3835 	if (max_speed == SPEED_1000) {
3836 		unsigned int snums = qe_get_num_of_snums();
3837 
3838 		/* configure muram FIFOs for gigabit operation */
3839 		ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3840 		ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3841 		ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3842 		ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3843 		ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3844 		ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3845 		ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3846 
3847 		/* If QE's snum number is 46/76 which means we need to support
3848 		 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3849 		 * more Threads to Rx.
3850 		 */
3851 		if ((snums == 76) || (snums == 46))
3852 			ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3853 		else
3854 			ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3855 	}
3856 
3857 	if (netif_msg_probe(&debug))
3858 		pr_info("UCC%1d at 0x%8llx (irq = %d)\n",
3859 			ug_info->uf_info.ucc_num + 1,
3860 			(u64)ug_info->uf_info.regs,
3861 			ug_info->uf_info.irq);
3862 
3863 	/* Create an ethernet device instance */
3864 	dev = alloc_etherdev(sizeof(*ugeth));
3865 
3866 	if (dev == NULL) {
3867 		err = -ENOMEM;
3868 		goto err_deregister_fixed_link;
3869 	}
3870 
3871 	ugeth = netdev_priv(dev);
3872 	spin_lock_init(&ugeth->lock);
3873 
3874 	/* Create CQs for hash tables */
3875 	INIT_LIST_HEAD(&ugeth->group_hash_q);
3876 	INIT_LIST_HEAD(&ugeth->ind_hash_q);
3877 
3878 	dev_set_drvdata(device, dev);
3879 
3880 	/* Set the dev->base_addr to the gfar reg region */
3881 	dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3882 
3883 	SET_NETDEV_DEV(dev, device);
3884 
3885 	/* Fill in the dev structure */
3886 	uec_set_ethtool_ops(dev);
3887 	dev->netdev_ops = &ucc_geth_netdev_ops;
3888 	dev->watchdog_timeo = TX_TIMEOUT;
3889 	INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3890 	netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3891 	dev->mtu = 1500;
3892 	dev->max_mtu = 1518;
3893 
3894 	ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3895 	ugeth->phy_interface = phy_interface;
3896 	ugeth->max_speed = max_speed;
3897 
3898 	/* Carrier starts down, phylib will bring it up */
3899 	netif_carrier_off(dev);
3900 
3901 	err = register_netdev(dev);
3902 	if (err) {
3903 		if (netif_msg_probe(ugeth))
3904 			pr_err("%s: Cannot register net device, aborting\n",
3905 			       dev->name);
3906 		goto err_free_netdev;
3907 	}
3908 
3909 	mac_addr = of_get_mac_address(np);
3910 	if (!IS_ERR(mac_addr))
3911 		ether_addr_copy(dev->dev_addr, mac_addr);
3912 
3913 	ugeth->ug_info = ug_info;
3914 	ugeth->dev = device;
3915 	ugeth->ndev = dev;
3916 	ugeth->node = np;
3917 
3918 	return 0;
3919 
3920 err_free_netdev:
3921 	free_netdev(dev);
3922 err_deregister_fixed_link:
3923 	if (of_phy_is_fixed_link(np))
3924 		of_phy_deregister_fixed_link(np);
3925 	of_node_put(ug_info->tbi_node);
3926 	of_node_put(ug_info->phy_node);
3927 
3928 	return err;
3929 }
3930 
3931 static int ucc_geth_remove(struct platform_device* ofdev)
3932 {
3933 	struct net_device *dev = platform_get_drvdata(ofdev);
3934 	struct ucc_geth_private *ugeth = netdev_priv(dev);
3935 	struct device_node *np = ofdev->dev.of_node;
3936 
3937 	unregister_netdev(dev);
3938 	ucc_geth_memclean(ugeth);
3939 	if (of_phy_is_fixed_link(np))
3940 		of_phy_deregister_fixed_link(np);
3941 	of_node_put(ugeth->ug_info->tbi_node);
3942 	of_node_put(ugeth->ug_info->phy_node);
3943 	free_netdev(dev);
3944 
3945 	return 0;
3946 }
3947 
3948 static const struct of_device_id ucc_geth_match[] = {
3949 	{
3950 		.type = "network",
3951 		.compatible = "ucc_geth",
3952 	},
3953 	{},
3954 };
3955 
3956 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3957 
3958 static struct platform_driver ucc_geth_driver = {
3959 	.driver = {
3960 		.name = DRV_NAME,
3961 		.of_match_table = ucc_geth_match,
3962 	},
3963 	.probe		= ucc_geth_probe,
3964 	.remove		= ucc_geth_remove,
3965 	.suspend	= ucc_geth_suspend,
3966 	.resume		= ucc_geth_resume,
3967 };
3968 
3969 static int __init ucc_geth_init(void)
3970 {
3971 	int i, ret;
3972 
3973 	if (netif_msg_drv(&debug))
3974 		pr_info(DRV_DESC "\n");
3975 	for (i = 0; i < 8; i++)
3976 		memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3977 		       sizeof(ugeth_primary_info));
3978 
3979 	ret = platform_driver_register(&ucc_geth_driver);
3980 
3981 	return ret;
3982 }
3983 
3984 static void __exit ucc_geth_exit(void)
3985 {
3986 	platform_driver_unregister(&ucc_geth_driver);
3987 }
3988 
3989 module_init(ucc_geth_init);
3990 module_exit(ucc_geth_exit);
3991 
3992 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3993 MODULE_DESCRIPTION(DRV_DESC);
3994 MODULE_LICENSE("GPL");
3995