1 /* 2 * drivers/net/ethernet/freescale/gianfar.h 3 * 4 * Gianfar Ethernet Driver 5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 * Still left to do: 20 * -Add support for module parameters 21 * -Add patch for ethtool phys id 22 */ 23 #ifndef __GIANFAR_H 24 #define __GIANFAR_H 25 26 #include <linux/kernel.h> 27 #include <linux/sched.h> 28 #include <linux/string.h> 29 #include <linux/errno.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/spinlock.h> 38 #include <linux/mm.h> 39 #include <linux/mii.h> 40 #include <linux/phy.h> 41 42 #include <asm/io.h> 43 #include <asm/irq.h> 44 #include <asm/uaccess.h> 45 #include <linux/module.h> 46 #include <linux/crc32.h> 47 #include <linux/workqueue.h> 48 #include <linux/ethtool.h> 49 50 struct ethtool_flow_spec_container { 51 struct ethtool_rx_flow_spec fs; 52 struct list_head list; 53 }; 54 55 struct ethtool_rx_list { 56 struct list_head list; 57 unsigned int count; 58 }; 59 60 /* The maximum number of packets to be handled in one call of gfar_poll */ 61 #define GFAR_DEV_WEIGHT 64 62 63 /* Length for FCB */ 64 #define GMAC_FCB_LEN 8 65 66 /* Length for TxPAL */ 67 #define GMAC_TXPAL_LEN 16 68 69 /* Default padding amount */ 70 #define DEFAULT_PADDING 2 71 72 /* Number of bytes to align the rx bufs to */ 73 #define RXBUF_ALIGNMENT 64 74 75 /* The number of bytes which composes a unit for the purpose of 76 * allocating data buffers. ie-for any given MTU, the data buffer 77 * will be the next highest multiple of 512 bytes. */ 78 #define INCREMENTAL_BUFFER_SIZE 512 79 80 #define PHY_INIT_TIMEOUT 100000 81 82 #define DRV_NAME "gfar-enet" 83 extern const char gfar_driver_version[]; 84 85 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 86 #define MAX_TX_QS 0x8 87 #define MAX_RX_QS 0x8 88 89 /* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 90 #define MAXGROUPS 0x2 91 92 /* These need to be powers of 2 for this driver */ 93 #define DEFAULT_TX_RING_SIZE 256 94 #define DEFAULT_RX_RING_SIZE 256 95 96 #define GFAR_RX_MAX_RING_SIZE 256 97 #define GFAR_TX_MAX_RING_SIZE 256 98 99 #define GFAR_MAX_FIFO_THRESHOLD 511 100 #define GFAR_MAX_FIFO_STARVE 511 101 #define GFAR_MAX_FIFO_STARVE_OFF 511 102 103 #define DEFAULT_RX_BUFFER_SIZE 1536 104 #define TX_RING_MOD_MASK(size) (size-1) 105 #define RX_RING_MOD_MASK(size) (size-1) 106 #define JUMBO_BUFFER_SIZE 9728 107 #define JUMBO_FRAME_SIZE 9600 108 109 #define DEFAULT_FIFO_TX_THR 0x100 110 #define DEFAULT_FIFO_TX_STARVE 0x40 111 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 112 #define DEFAULT_BD_STASH 1 113 #define DEFAULT_STASH_LENGTH 96 114 #define DEFAULT_STASH_INDEX 0 115 116 /* The number of Exact Match registers */ 117 #define GFAR_EM_NUM 15 118 119 /* Latency of interface clock in nanoseconds */ 120 /* Interface clock latency , in this case, means the 121 * time described by a value of 1 in the interrupt 122 * coalescing registers' time fields. Since those fields 123 * refer to the time it takes for 64 clocks to pass, the 124 * latencies are as such: 125 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 126 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 127 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 128 */ 129 #define GFAR_GBIT_TIME 512 130 #define GFAR_100_TIME 2560 131 #define GFAR_10_TIME 25600 132 133 #define DEFAULT_TX_COALESCE 1 134 #define DEFAULT_TXCOUNT 16 135 #define DEFAULT_TXTIME 21 136 137 #define DEFAULT_RXTIME 21 138 139 #define DEFAULT_RX_COALESCE 0 140 #define DEFAULT_RXCOUNT 0 141 142 #define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \ 143 | SUPPORTED_10baseT_Full \ 144 | SUPPORTED_100baseT_Half \ 145 | SUPPORTED_100baseT_Full \ 146 | SUPPORTED_Autoneg \ 147 | SUPPORTED_MII) 148 149 /* TBI register addresses */ 150 #define MII_TBICON 0x11 151 152 /* TBICON register bit fields */ 153 #define TBICON_CLK_SELECT 0x0020 154 155 /* MAC register bits */ 156 #define MACCFG1_SOFT_RESET 0x80000000 157 #define MACCFG1_RESET_RX_MC 0x00080000 158 #define MACCFG1_RESET_TX_MC 0x00040000 159 #define MACCFG1_RESET_RX_FUN 0x00020000 160 #define MACCFG1_RESET_TX_FUN 0x00010000 161 #define MACCFG1_LOOPBACK 0x00000100 162 #define MACCFG1_RX_FLOW 0x00000020 163 #define MACCFG1_TX_FLOW 0x00000010 164 #define MACCFG1_SYNCD_RX_EN 0x00000008 165 #define MACCFG1_RX_EN 0x00000004 166 #define MACCFG1_SYNCD_TX_EN 0x00000002 167 #define MACCFG1_TX_EN 0x00000001 168 169 #define MACCFG2_INIT_SETTINGS 0x00007205 170 #define MACCFG2_FULL_DUPLEX 0x00000001 171 #define MACCFG2_IF 0x00000300 172 #define MACCFG2_MII 0x00000100 173 #define MACCFG2_GMII 0x00000200 174 #define MACCFG2_HUGEFRAME 0x00000020 175 #define MACCFG2_LENGTHCHECK 0x00000010 176 #define MACCFG2_MPEN 0x00000008 177 178 #define ECNTRL_FIFM 0x00008000 179 #define ECNTRL_INIT_SETTINGS 0x00001000 180 #define ECNTRL_TBI_MODE 0x00000020 181 #define ECNTRL_REDUCED_MODE 0x00000010 182 #define ECNTRL_R100 0x00000008 183 #define ECNTRL_REDUCED_MII_MODE 0x00000004 184 #define ECNTRL_SGMII_MODE 0x00000002 185 186 #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 187 188 #define MINFLR_INIT_SETTINGS 0x00000040 189 190 /* Tqueue control */ 191 #define TQUEUE_EN0 0x00008000 192 #define TQUEUE_EN1 0x00004000 193 #define TQUEUE_EN2 0x00002000 194 #define TQUEUE_EN3 0x00001000 195 #define TQUEUE_EN4 0x00000800 196 #define TQUEUE_EN5 0x00000400 197 #define TQUEUE_EN6 0x00000200 198 #define TQUEUE_EN7 0x00000100 199 #define TQUEUE_EN_ALL 0x0000FF00 200 201 #define TR03WT_WT0_MASK 0xFF000000 202 #define TR03WT_WT1_MASK 0x00FF0000 203 #define TR03WT_WT2_MASK 0x0000FF00 204 #define TR03WT_WT3_MASK 0x000000FF 205 206 #define TR47WT_WT4_MASK 0xFF000000 207 #define TR47WT_WT5_MASK 0x00FF0000 208 #define TR47WT_WT6_MASK 0x0000FF00 209 #define TR47WT_WT7_MASK 0x000000FF 210 211 /* Rqueue control */ 212 #define RQUEUE_EX0 0x00800000 213 #define RQUEUE_EX1 0x00400000 214 #define RQUEUE_EX2 0x00200000 215 #define RQUEUE_EX3 0x00100000 216 #define RQUEUE_EX4 0x00080000 217 #define RQUEUE_EX5 0x00040000 218 #define RQUEUE_EX6 0x00020000 219 #define RQUEUE_EX7 0x00010000 220 #define RQUEUE_EX_ALL 0x00FF0000 221 222 #define RQUEUE_EN0 0x00000080 223 #define RQUEUE_EN1 0x00000040 224 #define RQUEUE_EN2 0x00000020 225 #define RQUEUE_EN3 0x00000010 226 #define RQUEUE_EN4 0x00000008 227 #define RQUEUE_EN5 0x00000004 228 #define RQUEUE_EN6 0x00000002 229 #define RQUEUE_EN7 0x00000001 230 #define RQUEUE_EN_ALL 0x000000FF 231 232 /* Init to do tx snooping for buffers and descriptors */ 233 #define DMACTRL_INIT_SETTINGS 0x000000c3 234 #define DMACTRL_GRS 0x00000010 235 #define DMACTRL_GTS 0x00000008 236 237 #define TSTAT_CLEAR_THALT_ALL 0xFF000000 238 #define TSTAT_CLEAR_THALT 0x80000000 239 #define TSTAT_CLEAR_THALT0 0x80000000 240 #define TSTAT_CLEAR_THALT1 0x40000000 241 #define TSTAT_CLEAR_THALT2 0x20000000 242 #define TSTAT_CLEAR_THALT3 0x10000000 243 #define TSTAT_CLEAR_THALT4 0x08000000 244 #define TSTAT_CLEAR_THALT5 0x04000000 245 #define TSTAT_CLEAR_THALT6 0x02000000 246 #define TSTAT_CLEAR_THALT7 0x01000000 247 248 /* Interrupt coalescing macros */ 249 #define IC_ICEN 0x80000000 250 #define IC_ICFT_MASK 0x1fe00000 251 #define IC_ICFT_SHIFT 21 252 #define mk_ic_icft(x) \ 253 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 254 #define IC_ICTT_MASK 0x0000ffff 255 #define mk_ic_ictt(x) (x&IC_ICTT_MASK) 256 257 #define mk_ic_value(count, time) (IC_ICEN | \ 258 mk_ic_icft(count) | \ 259 mk_ic_ictt(time)) 260 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 261 IC_ICFT_SHIFT) 262 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 263 264 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 265 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 266 267 #define skip_bd(bdp, stride, base, ring_size) ({ \ 268 typeof(bdp) new_bd = (bdp) + (stride); \ 269 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; }) 270 271 #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size) 272 273 #define RCTRL_TS_ENABLE 0x01000000 274 #define RCTRL_PAL_MASK 0x001f0000 275 #define RCTRL_VLEX 0x00002000 276 #define RCTRL_FILREN 0x00001000 277 #define RCTRL_GHTX 0x00000400 278 #define RCTRL_IPCSEN 0x00000200 279 #define RCTRL_TUCSEN 0x00000100 280 #define RCTRL_PRSDEP_MASK 0x000000c0 281 #define RCTRL_PRSDEP_INIT 0x000000c0 282 #define RCTRL_PRSFM 0x00000020 283 #define RCTRL_PROM 0x00000008 284 #define RCTRL_EMEN 0x00000002 285 #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 286 RCTRL_TUCSEN | RCTRL_FILREN) 287 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 288 RCTRL_PRSDEP_INIT) 289 #define RCTRL_EXTHASH (RCTRL_GHTX) 290 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 291 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 292 293 294 #define RSTAT_CLEAR_RHALT 0x00800000 295 #define RSTAT_CLEAR_RXF0 0x00000080 296 #define RSTAT_RXF_MASK 0x000000ff 297 298 #define TCTRL_IPCSEN 0x00004000 299 #define TCTRL_TUCSEN 0x00002000 300 #define TCTRL_VLINS 0x00001000 301 #define TCTRL_THDF 0x00000800 302 #define TCTRL_RFCPAUSE 0x00000010 303 #define TCTRL_TFCPAUSE 0x00000008 304 #define TCTRL_TXSCHED_MASK 0x00000006 305 #define TCTRL_TXSCHED_INIT 0x00000000 306 /* priority scheduling */ 307 #define TCTRL_TXSCHED_PRIO 0x00000002 308 /* weighted round-robin scheduling (WRRS) */ 309 #define TCTRL_TXSCHED_WRRS 0x00000004 310 /* default WRRS weight and policy setting, 311 * tailored to the tr03wt and tr47wt registers: 312 * equal weight for all Tx Qs, measured in 64byte units 313 */ 314 #define DEFAULT_WRRS_WEIGHT 0x18181818 315 316 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 317 318 #define IEVENT_INIT_CLEAR 0xffffffff 319 #define IEVENT_BABR 0x80000000 320 #define IEVENT_RXC 0x40000000 321 #define IEVENT_BSY 0x20000000 322 #define IEVENT_EBERR 0x10000000 323 #define IEVENT_MSRO 0x04000000 324 #define IEVENT_GTSC 0x02000000 325 #define IEVENT_BABT 0x01000000 326 #define IEVENT_TXC 0x00800000 327 #define IEVENT_TXE 0x00400000 328 #define IEVENT_TXB 0x00200000 329 #define IEVENT_TXF 0x00100000 330 #define IEVENT_LC 0x00040000 331 #define IEVENT_CRL 0x00020000 332 #define IEVENT_XFUN 0x00010000 333 #define IEVENT_RXB0 0x00008000 334 #define IEVENT_MAG 0x00000800 335 #define IEVENT_GRSC 0x00000100 336 #define IEVENT_RXF0 0x00000080 337 #define IEVENT_FIR 0x00000008 338 #define IEVENT_FIQ 0x00000004 339 #define IEVENT_DPE 0x00000002 340 #define IEVENT_PERR 0x00000001 341 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 342 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 343 #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 344 #define IEVENT_ERR_MASK \ 345 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 346 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 347 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 348 | IEVENT_MAG | IEVENT_BABR) 349 350 #define IMASK_INIT_CLEAR 0x00000000 351 #define IMASK_BABR 0x80000000 352 #define IMASK_RXC 0x40000000 353 #define IMASK_BSY 0x20000000 354 #define IMASK_EBERR 0x10000000 355 #define IMASK_MSRO 0x04000000 356 #define IMASK_GTSC 0x02000000 357 #define IMASK_BABT 0x01000000 358 #define IMASK_TXC 0x00800000 359 #define IMASK_TXEEN 0x00400000 360 #define IMASK_TXBEN 0x00200000 361 #define IMASK_TXFEN 0x00100000 362 #define IMASK_LC 0x00040000 363 #define IMASK_CRL 0x00020000 364 #define IMASK_XFUN 0x00010000 365 #define IMASK_RXB0 0x00008000 366 #define IMASK_MAG 0x00000800 367 #define IMASK_GRSC 0x00000100 368 #define IMASK_RXFEN0 0x00000080 369 #define IMASK_FIR 0x00000008 370 #define IMASK_FIQ 0x00000004 371 #define IMASK_DPE 0x00000002 372 #define IMASK_PERR 0x00000001 373 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 374 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 375 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 376 | IMASK_PERR) 377 #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \ 378 & IMASK_DEFAULT) 379 380 /* Fifo management */ 381 #define FIFO_TX_THR_MASK 0x01ff 382 #define FIFO_TX_STARVE_MASK 0x01ff 383 #define FIFO_TX_STARVE_OFF_MASK 0x01ff 384 385 /* Attribute fields */ 386 387 /* This enables rx snooping for buffers and descriptors */ 388 #define ATTR_BDSTASH 0x00000800 389 390 #define ATTR_BUFSTASH 0x00004000 391 392 #define ATTR_SNOOPING 0x000000c0 393 #define ATTR_INIT_SETTINGS ATTR_SNOOPING 394 395 #define ATTRELI_INIT_SETTINGS 0x0 396 #define ATTRELI_EL_MASK 0x3fff0000 397 #define ATTRELI_EL(x) (x << 16) 398 #define ATTRELI_EI_MASK 0x00003fff 399 #define ATTRELI_EI(x) (x) 400 401 #define BD_LFLAG(flags) ((flags) << 16) 402 #define BD_LENGTH_MASK 0x0000ffff 403 404 #define FPR_FILER_MASK 0xFFFFFFFF 405 #define MAX_FILER_IDX 0xFF 406 407 /* This default RIR value directly corresponds 408 * to the 3-bit hash value generated */ 409 #define DEFAULT_RIR0 0x05397700 410 411 /* RQFCR register bits */ 412 #define RQFCR_GPI 0x80000000 413 #define RQFCR_HASHTBL_Q 0x00000000 414 #define RQFCR_HASHTBL_0 0x00020000 415 #define RQFCR_HASHTBL_1 0x00040000 416 #define RQFCR_HASHTBL_2 0x00060000 417 #define RQFCR_HASHTBL_3 0x00080000 418 #define RQFCR_HASH 0x00010000 419 #define RQFCR_QUEUE 0x0000FC00 420 #define RQFCR_CLE 0x00000200 421 #define RQFCR_RJE 0x00000100 422 #define RQFCR_AND 0x00000080 423 #define RQFCR_CMP_EXACT 0x00000000 424 #define RQFCR_CMP_MATCH 0x00000020 425 #define RQFCR_CMP_NOEXACT 0x00000040 426 #define RQFCR_CMP_NOMATCH 0x00000060 427 428 /* RQFCR PID values */ 429 #define RQFCR_PID_MASK 0x00000000 430 #define RQFCR_PID_PARSE 0x00000001 431 #define RQFCR_PID_ARB 0x00000002 432 #define RQFCR_PID_DAH 0x00000003 433 #define RQFCR_PID_DAL 0x00000004 434 #define RQFCR_PID_SAH 0x00000005 435 #define RQFCR_PID_SAL 0x00000006 436 #define RQFCR_PID_ETY 0x00000007 437 #define RQFCR_PID_VID 0x00000008 438 #define RQFCR_PID_PRI 0x00000009 439 #define RQFCR_PID_TOS 0x0000000A 440 #define RQFCR_PID_L4P 0x0000000B 441 #define RQFCR_PID_DIA 0x0000000C 442 #define RQFCR_PID_SIA 0x0000000D 443 #define RQFCR_PID_DPT 0x0000000E 444 #define RQFCR_PID_SPT 0x0000000F 445 446 /* RQFPR when PID is 0x0001 */ 447 #define RQFPR_HDR_GE_512 0x00200000 448 #define RQFPR_LERR 0x00100000 449 #define RQFPR_RAR 0x00080000 450 #define RQFPR_RARQ 0x00040000 451 #define RQFPR_AR 0x00020000 452 #define RQFPR_ARQ 0x00010000 453 #define RQFPR_EBC 0x00008000 454 #define RQFPR_VLN 0x00004000 455 #define RQFPR_CFI 0x00002000 456 #define RQFPR_JUM 0x00001000 457 #define RQFPR_IPF 0x00000800 458 #define RQFPR_FIF 0x00000400 459 #define RQFPR_IPV4 0x00000200 460 #define RQFPR_IPV6 0x00000100 461 #define RQFPR_ICC 0x00000080 462 #define RQFPR_ICV 0x00000040 463 #define RQFPR_TCP 0x00000020 464 #define RQFPR_UDP 0x00000010 465 #define RQFPR_TUC 0x00000008 466 #define RQFPR_TUV 0x00000004 467 #define RQFPR_PER 0x00000002 468 #define RQFPR_EER 0x00000001 469 470 /* TxBD status field bits */ 471 #define TXBD_READY 0x8000 472 #define TXBD_PADCRC 0x4000 473 #define TXBD_WRAP 0x2000 474 #define TXBD_INTERRUPT 0x1000 475 #define TXBD_LAST 0x0800 476 #define TXBD_CRC 0x0400 477 #define TXBD_DEF 0x0200 478 #define TXBD_HUGEFRAME 0x0080 479 #define TXBD_LATECOLLISION 0x0080 480 #define TXBD_RETRYLIMIT 0x0040 481 #define TXBD_RETRYCOUNTMASK 0x003c 482 #define TXBD_UNDERRUN 0x0002 483 #define TXBD_TOE 0x0002 484 485 /* Tx FCB param bits */ 486 #define TXFCB_VLN 0x80 487 #define TXFCB_IP 0x40 488 #define TXFCB_IP6 0x20 489 #define TXFCB_TUP 0x10 490 #define TXFCB_UDP 0x08 491 #define TXFCB_CIP 0x04 492 #define TXFCB_CTU 0x02 493 #define TXFCB_NPH 0x01 494 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 495 496 /* RxBD status field bits */ 497 #define RXBD_EMPTY 0x8000 498 #define RXBD_RO1 0x4000 499 #define RXBD_WRAP 0x2000 500 #define RXBD_INTERRUPT 0x1000 501 #define RXBD_LAST 0x0800 502 #define RXBD_FIRST 0x0400 503 #define RXBD_MISS 0x0100 504 #define RXBD_BROADCAST 0x0080 505 #define RXBD_MULTICAST 0x0040 506 #define RXBD_LARGE 0x0020 507 #define RXBD_NONOCTET 0x0010 508 #define RXBD_SHORT 0x0008 509 #define RXBD_CRCERR 0x0004 510 #define RXBD_OVERRUN 0x0002 511 #define RXBD_TRUNCATED 0x0001 512 #define RXBD_STATS 0x01ff 513 #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 514 | RXBD_CRCERR | RXBD_OVERRUN \ 515 | RXBD_TRUNCATED) 516 517 /* Rx FCB status field bits */ 518 #define RXFCB_VLN 0x8000 519 #define RXFCB_IP 0x4000 520 #define RXFCB_IP6 0x2000 521 #define RXFCB_TUP 0x1000 522 #define RXFCB_CIP 0x0800 523 #define RXFCB_CTU 0x0400 524 #define RXFCB_EIP 0x0200 525 #define RXFCB_ETU 0x0100 526 #define RXFCB_CSUM_MASK 0x0f00 527 #define RXFCB_PERR_MASK 0x000c 528 #define RXFCB_PERR_BADL3 0x0008 529 530 #define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 531 532 struct txbd8 533 { 534 union { 535 struct { 536 u16 status; /* Status Fields */ 537 u16 length; /* Buffer length */ 538 }; 539 u32 lstatus; 540 }; 541 u32 bufPtr; /* Buffer Pointer */ 542 }; 543 544 struct txfcb { 545 u8 flags; 546 u8 ptp; /* Flag to enable tx timestamping */ 547 u8 l4os; /* Level 4 Header Offset */ 548 u8 l3os; /* Level 3 Header Offset */ 549 u16 phcs; /* Pseudo-header Checksum */ 550 u16 vlctl; /* VLAN control word */ 551 }; 552 553 struct rxbd8 554 { 555 union { 556 struct { 557 u16 status; /* Status Fields */ 558 u16 length; /* Buffer Length */ 559 }; 560 u32 lstatus; 561 }; 562 u32 bufPtr; /* Buffer Pointer */ 563 }; 564 565 struct rxfcb { 566 u16 flags; 567 u8 rq; /* Receive Queue index */ 568 u8 pro; /* Layer 4 Protocol */ 569 u16 reserved; 570 u16 vlctl; /* VLAN control word */ 571 }; 572 573 struct gianfar_skb_cb { 574 int alignamount; 575 }; 576 577 #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 578 579 struct rmon_mib 580 { 581 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 582 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 583 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 584 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 585 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 586 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 587 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 588 u32 rbyt; /* 0x.69c - Receive Byte Counter */ 589 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 590 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 591 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 592 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 593 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 594 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 595 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 596 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 597 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 598 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 599 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 600 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 601 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 602 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 603 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 604 u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 605 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 606 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 607 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 608 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 609 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 610 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 611 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 612 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 613 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 614 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 615 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 616 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 617 u8 res1[4]; 618 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 619 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 620 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 621 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 622 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 623 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 624 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 625 u32 car1; /* 0x.730 - Carry Register One */ 626 u32 car2; /* 0x.734 - Carry Register Two */ 627 u32 cam1; /* 0x.738 - Carry Mask Register One */ 628 u32 cam2; /* 0x.73c - Carry Mask Register Two */ 629 }; 630 631 struct gfar_extra_stats { 632 atomic64_t rx_large; 633 atomic64_t rx_short; 634 atomic64_t rx_nonoctet; 635 atomic64_t rx_crcerr; 636 atomic64_t rx_overrun; 637 atomic64_t rx_bsy; 638 atomic64_t rx_babr; 639 atomic64_t rx_trunc; 640 atomic64_t eberr; 641 atomic64_t tx_babt; 642 atomic64_t tx_underrun; 643 atomic64_t rx_skbmissing; 644 atomic64_t tx_timeout; 645 }; 646 647 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 648 #define GFAR_EXTRA_STATS_LEN \ 649 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 650 651 /* Number of stats exported via ethtool */ 652 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 653 654 struct gfar { 655 u32 tsec_id; /* 0x.000 - Controller ID register */ 656 u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 657 u8 res1[8]; 658 u32 ievent; /* 0x.010 - Interrupt Event Register */ 659 u32 imask; /* 0x.014 - Interrupt Mask Register */ 660 u32 edis; /* 0x.018 - Error Disabled Register */ 661 u32 emapg; /* 0x.01c - Group Error mapping register */ 662 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 663 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 664 u32 ptv; /* 0x.028 - Pause Time Value Register */ 665 u32 dmactrl; /* 0x.02c - DMA Control Register */ 666 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 667 u8 res2[28]; 668 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 669 register */ 670 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 671 register */ 672 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 673 register */ 674 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 675 shutoff register */ 676 u8 res3[44]; 677 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 678 u8 res4[8]; 679 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 680 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 681 u8 res5[96]; 682 u32 tctrl; /* 0x.100 - Transmit Control Register */ 683 u32 tstat; /* 0x.104 - Transmit Status Register */ 684 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 685 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 686 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 687 u32 tqueue; /* 0x.114 - Transmit queue control register */ 688 u8 res7[40]; 689 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 690 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 691 u8 res8[52]; 692 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 693 u8 res9a[4]; 694 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 695 u8 res9b[4]; 696 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 697 u8 res9c[4]; 698 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 699 u8 res9d[4]; 700 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 701 u8 res9e[4]; 702 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 703 u8 res9f[4]; 704 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 705 u8 res9g[4]; 706 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 707 u8 res9h[4]; 708 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 709 u8 res9[64]; 710 u32 tbaseh; /* 0x.200 - TxBD base address high */ 711 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 712 u8 res10a[4]; 713 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 714 u8 res10b[4]; 715 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 716 u8 res10c[4]; 717 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 718 u8 res10d[4]; 719 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 720 u8 res10e[4]; 721 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 722 u8 res10f[4]; 723 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 724 u8 res10g[4]; 725 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 726 u8 res10[192]; 727 u32 rctrl; /* 0x.300 - Receive Control Register */ 728 u32 rstat; /* 0x.304 - Receive Status Register */ 729 u8 res12[8]; 730 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 731 u32 rqueue; /* 0x.314 - Receive queue control register */ 732 u32 rir0; /* 0x.318 - Ring mapping register 0 */ 733 u32 rir1; /* 0x.31c - Ring mapping register 1 */ 734 u32 rir2; /* 0x.320 - Ring mapping register 2 */ 735 u32 rir3; /* 0x.324 - Ring mapping register 3 */ 736 u8 res13[8]; 737 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 738 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 739 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 740 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 741 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 742 u8 res14[56]; 743 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 744 u8 res15a[4]; 745 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 746 u8 res15b[4]; 747 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 748 u8 res15c[4]; 749 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 750 u8 res15d[4]; 751 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 752 u8 res15e[4]; 753 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 754 u8 res15f[4]; 755 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 756 u8 res15g[4]; 757 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 758 u8 res15h[4]; 759 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 760 u8 res16[64]; 761 u32 rbaseh; /* 0x.400 - RxBD base address high */ 762 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 763 u8 res17a[4]; 764 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 765 u8 res17b[4]; 766 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 767 u8 res17c[4]; 768 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 769 u8 res17d[4]; 770 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 771 u8 res17e[4]; 772 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 773 u8 res17f[4]; 774 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 775 u8 res17g[4]; 776 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 777 u8 res17[192]; 778 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 779 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 780 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 781 u32 hafdup; /* 0x.50c - Half Duplex Register */ 782 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 783 u8 res18[12]; 784 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 785 u32 ifctrl; /* 0x.538 - Interface control register */ 786 u32 ifstat; /* 0x.53c - Interface Status Register */ 787 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 788 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 789 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 790 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 791 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 792 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 793 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 794 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 795 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 796 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 797 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 798 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 799 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 800 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 801 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 802 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 803 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 804 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 805 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 806 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 807 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 808 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 809 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 810 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 811 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 812 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 813 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 814 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 815 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 816 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 817 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 818 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 819 u8 res20[192]; 820 struct rmon_mib rmon; /* 0x.680-0x.73c */ 821 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 822 u8 res21[188]; 823 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 824 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 825 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 826 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 827 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 828 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 829 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 830 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 831 u8 res22[96]; 832 u32 gaddr0; /* 0x.880 - Group address register 0 */ 833 u32 gaddr1; /* 0x.884 - Group address register 1 */ 834 u32 gaddr2; /* 0x.888 - Group address register 2 */ 835 u32 gaddr3; /* 0x.88c - Group address register 3 */ 836 u32 gaddr4; /* 0x.890 - Group address register 4 */ 837 u32 gaddr5; /* 0x.894 - Group address register 5 */ 838 u32 gaddr6; /* 0x.898 - Group address register 6 */ 839 u32 gaddr7; /* 0x.89c - Group address register 7 */ 840 u8 res23a[352]; 841 u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 842 u8 res23b[252]; 843 u8 res23c[248]; 844 u32 attr; /* 0x.bf8 - Attributes Register */ 845 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 846 u8 res24[688]; 847 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 848 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 849 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 850 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 851 u8 res25[16]; 852 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 853 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 854 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 855 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 856 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 857 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 858 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 859 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 860 u8 res26[32]; 861 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 862 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 863 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 864 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 865 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 866 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 867 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 868 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 869 u8 res27[208]; 870 }; 871 872 /* Flags related to gianfar device features */ 873 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 874 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 875 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 876 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 877 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 878 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 879 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 880 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080 881 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 882 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 883 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 884 #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 885 886 #if (MAXGROUPS == 2) 887 #define DEFAULT_MAPPING 0xAA 888 #else 889 #define DEFAULT_MAPPING 0xFF 890 #endif 891 892 #define ISRG_SHIFT_TX 0x10 893 #define ISRG_SHIFT_RX 0x18 894 895 /* The same driver can operate in two modes */ 896 /* SQ_SG_MODE: Single Queue Single Group Mode 897 * (Backward compatible mode) 898 * MQ_MG_MODE: Multi Queue Multi Group mode 899 */ 900 enum { 901 SQ_SG_MODE = 0, 902 MQ_MG_MODE 903 }; 904 905 /* 906 * Per TX queue stats 907 */ 908 struct tx_q_stats { 909 unsigned long tx_packets; 910 unsigned long tx_bytes; 911 }; 912 913 /** 914 * struct gfar_priv_tx_q - per tx queue structure 915 * @txlock: per queue tx spin lock 916 * @tx_skbuff:skb pointers 917 * @skb_curtx: to be used skb pointer 918 * @skb_dirtytx:the last used skb pointer 919 * @stats: bytes/packets stats 920 * @qindex: index of this queue 921 * @dev: back pointer to the dev structure 922 * @grp: back pointer to the group to which this queue belongs 923 * @tx_bd_base: First tx buffer descriptor 924 * @cur_tx: Next free ring entry 925 * @dirty_tx: First buffer in line to be transmitted 926 * @tx_ring_size: Tx ring size 927 * @num_txbdfree: number of free TxBds 928 * @txcoalescing: enable/disable tx coalescing 929 * @txic: transmit interrupt coalescing value 930 * @txcount: coalescing value if based on tx frame count 931 * @txtime: coalescing value if based on time 932 */ 933 struct gfar_priv_tx_q { 934 /* cacheline 1 */ 935 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 936 struct txbd8 *tx_bd_base; 937 struct txbd8 *cur_tx; 938 unsigned int num_txbdfree; 939 unsigned short skb_curtx; 940 unsigned short tx_ring_size; 941 struct tx_q_stats stats; 942 struct gfar_priv_grp *grp; 943 /* cacheline 2 */ 944 struct net_device *dev; 945 struct sk_buff **tx_skbuff; 946 struct txbd8 *dirty_tx; 947 unsigned short skb_dirtytx; 948 unsigned short qindex; 949 /* Configuration info for the coalescing features */ 950 unsigned int txcoalescing; 951 unsigned long txic; 952 dma_addr_t tx_bd_dma_base; 953 }; 954 955 /* 956 * Per RX queue stats 957 */ 958 struct rx_q_stats { 959 unsigned long rx_packets; 960 unsigned long rx_bytes; 961 unsigned long rx_dropped; 962 }; 963 964 /** 965 * struct gfar_priv_rx_q - per rx queue structure 966 * @rxlock: per queue rx spin lock 967 * @rx_skbuff: skb pointers 968 * @skb_currx: currently use skb pointer 969 * @rx_bd_base: First rx buffer descriptor 970 * @cur_rx: Next free rx ring entry 971 * @qindex: index of this queue 972 * @dev: back pointer to the dev structure 973 * @rx_ring_size: Rx ring size 974 * @rxcoalescing: enable/disable rx-coalescing 975 * @rxic: receive interrupt coalescing vlaue 976 */ 977 978 struct gfar_priv_rx_q { 979 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 980 struct sk_buff ** rx_skbuff; 981 dma_addr_t rx_bd_dma_base; 982 struct rxbd8 *rx_bd_base; 983 struct rxbd8 *cur_rx; 984 struct net_device *dev; 985 struct gfar_priv_grp *grp; 986 struct rx_q_stats stats; 987 u16 skb_currx; 988 u16 qindex; 989 unsigned int rx_ring_size; 990 /* RX Coalescing values */ 991 unsigned char rxcoalescing; 992 unsigned long rxic; 993 }; 994 995 enum gfar_irqinfo_id { 996 GFAR_TX = 0, 997 GFAR_RX = 1, 998 GFAR_ER = 2, 999 GFAR_NUM_IRQS = 3 1000 }; 1001 1002 struct gfar_irqinfo { 1003 unsigned int irq; 1004 char name[GFAR_INT_NAME_MAX]; 1005 }; 1006 1007 /** 1008 * struct gfar_priv_grp - per group structure 1009 * @napi: the napi poll function 1010 * @priv: back pointer to the priv structure 1011 * @regs: the ioremapped register space for this group 1012 * @grp_id: group id for this group 1013 * @irqinfo: TX/RX/ER irq data for this group 1014 */ 1015 1016 struct gfar_priv_grp { 1017 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES))); 1018 struct napi_struct napi; 1019 struct gfar_private *priv; 1020 struct gfar __iomem *regs; 1021 unsigned int grp_id; 1022 unsigned long num_rx_queues; 1023 unsigned long rx_bit_map; 1024 /* cacheline 3 */ 1025 unsigned int rstat; 1026 unsigned int tstat; 1027 unsigned long num_tx_queues; 1028 unsigned long tx_bit_map; 1029 1030 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1031 }; 1032 1033 #define gfar_irq(grp, ID) \ 1034 ((grp)->irqinfo[GFAR_##ID]) 1035 1036 enum gfar_errata { 1037 GFAR_ERRATA_74 = 0x01, 1038 GFAR_ERRATA_76 = 0x02, 1039 GFAR_ERRATA_A002 = 0x04, 1040 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1041 }; 1042 1043 /* Struct stolen almost completely (and shamelessly) from the FCC enet source 1044 * (Ok, that's not so true anymore, but there is a family resemblance) 1045 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1046 * and tx_bd_base always point to the currently available buffer. 1047 * The dirty_tx tracks the current buffer that is being sent by the 1048 * controller. The cur_tx and dirty_tx are equal under both completely 1049 * empty and completely full conditions. The empty/ready indicator in 1050 * the buffer descriptor determines the actual condition. 1051 */ 1052 struct gfar_private { 1053 unsigned int num_rx_queues; 1054 1055 struct device *dev; 1056 struct net_device *ndev; 1057 enum gfar_errata errata; 1058 unsigned int rx_buffer_size; 1059 1060 u16 uses_rxfcb; 1061 u16 padding; 1062 1063 /* HW time stamping enabled flag */ 1064 int hwts_rx_en; 1065 int hwts_tx_en; 1066 1067 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1068 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1069 struct gfar_priv_grp gfargrp[MAXGROUPS]; 1070 1071 u32 device_flags; 1072 1073 unsigned int mode; 1074 unsigned int num_tx_queues; 1075 unsigned int num_grps; 1076 1077 /* Network Statistics */ 1078 struct gfar_extra_stats extra_stats; 1079 1080 /* PHY stuff */ 1081 phy_interface_t interface; 1082 struct device_node *phy_node; 1083 struct device_node *tbi_node; 1084 struct phy_device *phydev; 1085 struct mii_bus *mii_bus; 1086 int oldspeed; 1087 int oldduplex; 1088 int oldlink; 1089 1090 /* Bitfield update lock */ 1091 spinlock_t bflock; 1092 1093 uint32_t msg_enable; 1094 1095 struct work_struct reset_task; 1096 1097 struct platform_device *ofdev; 1098 unsigned char 1099 extended_hash:1, 1100 bd_stash_en:1, 1101 rx_filer_enable:1, 1102 /* Wake-on-LAN enabled */ 1103 wol_en:1, 1104 /* Enable priorty based Tx scheduling in Hw */ 1105 prio_sched_en:1; 1106 1107 /* The total tx and rx ring size for the enabled queues */ 1108 unsigned int total_tx_ring_size; 1109 unsigned int total_rx_ring_size; 1110 1111 /* RX per device parameters */ 1112 unsigned int rx_stash_size; 1113 unsigned int rx_stash_index; 1114 1115 u32 cur_filer_idx; 1116 1117 /* RX queue filer rule set*/ 1118 struct ethtool_rx_list rx_list; 1119 struct mutex rx_queue_access; 1120 1121 /* Hash registers and their width */ 1122 u32 __iomem *hash_regs[16]; 1123 int hash_width; 1124 1125 /* global parameters */ 1126 unsigned int fifo_threshold; 1127 unsigned int fifo_starve; 1128 unsigned int fifo_starve_off; 1129 1130 /*Filer table*/ 1131 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1132 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1133 }; 1134 1135 1136 static inline int gfar_has_errata(struct gfar_private *priv, 1137 enum gfar_errata err) 1138 { 1139 return priv->errata & err; 1140 } 1141 1142 static inline u32 gfar_read(unsigned __iomem *addr) 1143 { 1144 u32 val; 1145 val = ioread32be(addr); 1146 return val; 1147 } 1148 1149 static inline void gfar_write(unsigned __iomem *addr, u32 val) 1150 { 1151 iowrite32be(val, addr); 1152 } 1153 1154 static inline void gfar_write_filer(struct gfar_private *priv, 1155 unsigned int far, unsigned int fcr, unsigned int fpr) 1156 { 1157 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1158 1159 gfar_write(®s->rqfar, far); 1160 gfar_write(®s->rqfcr, fcr); 1161 gfar_write(®s->rqfpr, fpr); 1162 } 1163 1164 static inline void gfar_read_filer(struct gfar_private *priv, 1165 unsigned int far, unsigned int *fcr, unsigned int *fpr) 1166 { 1167 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1168 1169 gfar_write(®s->rqfar, far); 1170 *fcr = gfar_read(®s->rqfcr); 1171 *fpr = gfar_read(®s->rqfpr); 1172 } 1173 1174 extern void lock_rx_qs(struct gfar_private *priv); 1175 extern void lock_tx_qs(struct gfar_private *priv); 1176 extern void unlock_rx_qs(struct gfar_private *priv); 1177 extern void unlock_tx_qs(struct gfar_private *priv); 1178 extern irqreturn_t gfar_receive(int irq, void *dev_id); 1179 extern int startup_gfar(struct net_device *dev); 1180 extern void stop_gfar(struct net_device *dev); 1181 extern void gfar_halt(struct net_device *dev); 1182 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, 1183 int enable, u32 regnum, u32 read); 1184 extern void gfar_configure_coalescing_all(struct gfar_private *priv); 1185 void gfar_init_sysfs(struct net_device *dev); 1186 int gfar_set_features(struct net_device *dev, netdev_features_t features); 1187 extern void gfar_check_rx_parser_mode(struct gfar_private *priv); 1188 extern void gfar_vlan_mode(struct net_device *dev, netdev_features_t features); 1189 1190 extern const struct ethtool_ops gfar_ethtool_ops; 1191 1192 #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1193 1194 #define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1195 #define RQFCR_PID_L4P_MASK 0xFFFFFF00 1196 #define RQFCR_PID_VID_MASK 0xFFFFF000 1197 #define RQFCR_PID_PORT_MASK 0xFFFF0000 1198 #define RQFCR_PID_MAC_MASK 0xFF000000 1199 1200 struct gfar_mask_entry { 1201 unsigned int mask; /* The mask value which is valid form start to end */ 1202 unsigned int start; 1203 unsigned int end; 1204 unsigned int block; /* Same block values indicate depended entries */ 1205 }; 1206 1207 /* Represents a receive filer table entry */ 1208 struct gfar_filer_entry { 1209 u32 ctrl; 1210 u32 prop; 1211 }; 1212 1213 1214 /* The 20 additional entries are a shadow for one extra element */ 1215 struct filer_table { 1216 u32 index; 1217 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1218 }; 1219 1220 /* The gianfar_ptp module will set this variable */ 1221 extern int gfar_phc_index; 1222 1223 #endif /* __GIANFAR_H */ 1224