12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ec21e2ecSJeff Kirsher /* 33396c782SPaul Gortmaker * drivers/net/ethernet/freescale/gianfar.h 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Gianfar Ethernet Driver 6ec21e2ecSJeff Kirsher * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 7ec21e2ecSJeff Kirsher * Based on 8260_io/fcc_enet.c 8ec21e2ecSJeff Kirsher * 9ec21e2ecSJeff Kirsher * Author: Andy Fleming 10ec21e2ecSJeff Kirsher * Maintainer: Kumar Gala 11ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 12ec21e2ecSJeff Kirsher * 1320862788SClaudiu Manoil * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 14ec21e2ecSJeff Kirsher * 15ec21e2ecSJeff Kirsher * Still left to do: 16ec21e2ecSJeff Kirsher * -Add support for module parameters 17ec21e2ecSJeff Kirsher * -Add patch for ethtool phys id 18ec21e2ecSJeff Kirsher */ 19ec21e2ecSJeff Kirsher #ifndef __GIANFAR_H 20ec21e2ecSJeff Kirsher #define __GIANFAR_H 21ec21e2ecSJeff Kirsher 22ec21e2ecSJeff Kirsher #include <linux/kernel.h> 23ec21e2ecSJeff Kirsher #include <linux/sched.h> 24ec21e2ecSJeff Kirsher #include <linux/string.h> 25ec21e2ecSJeff Kirsher #include <linux/errno.h> 26ec21e2ecSJeff Kirsher #include <linux/slab.h> 27ec21e2ecSJeff Kirsher #include <linux/interrupt.h> 28ec21e2ecSJeff Kirsher #include <linux/delay.h> 29ec21e2ecSJeff Kirsher #include <linux/netdevice.h> 30ec21e2ecSJeff Kirsher #include <linux/etherdevice.h> 31ec21e2ecSJeff Kirsher #include <linux/skbuff.h> 32ec21e2ecSJeff Kirsher #include <linux/spinlock.h> 33ec21e2ecSJeff Kirsher #include <linux/mm.h> 34ec21e2ecSJeff Kirsher #include <linux/mii.h> 35ec21e2ecSJeff Kirsher #include <linux/phy.h> 36ec21e2ecSJeff Kirsher 37ec21e2ecSJeff Kirsher #include <asm/io.h> 38ec21e2ecSJeff Kirsher #include <asm/irq.h> 397c0f6ba6SLinus Torvalds #include <linux/uaccess.h> 40ec21e2ecSJeff Kirsher #include <linux/module.h> 41ec21e2ecSJeff Kirsher #include <linux/crc32.h> 42ec21e2ecSJeff Kirsher #include <linux/workqueue.h> 43ec21e2ecSJeff Kirsher #include <linux/ethtool.h> 44ec21e2ecSJeff Kirsher 45ec21e2ecSJeff Kirsher struct ethtool_flow_spec_container { 46ec21e2ecSJeff Kirsher struct ethtool_rx_flow_spec fs; 47ec21e2ecSJeff Kirsher struct list_head list; 48ec21e2ecSJeff Kirsher }; 49ec21e2ecSJeff Kirsher 50ec21e2ecSJeff Kirsher struct ethtool_rx_list { 51ec21e2ecSJeff Kirsher struct list_head list; 52ec21e2ecSJeff Kirsher unsigned int count; 53ec21e2ecSJeff Kirsher }; 54ec21e2ecSJeff Kirsher 55ec21e2ecSJeff Kirsher /* The maximum number of packets to be handled in one call of gfar_poll */ 56ec21e2ecSJeff Kirsher #define GFAR_DEV_WEIGHT 64 57ec21e2ecSJeff Kirsher 58ec21e2ecSJeff Kirsher /* Length for FCB */ 59ec21e2ecSJeff Kirsher #define GMAC_FCB_LEN 8 60ec21e2ecSJeff Kirsher 619c4886e5SManfred Rudigier /* Length for TxPAL */ 629c4886e5SManfred Rudigier #define GMAC_TXPAL_LEN 16 639c4886e5SManfred Rudigier 64ec21e2ecSJeff Kirsher /* Default padding amount */ 65ec21e2ecSJeff Kirsher #define DEFAULT_PADDING 2 66ec21e2ecSJeff Kirsher 67ec21e2ecSJeff Kirsher /* Number of bytes to align the rx bufs to */ 68ec21e2ecSJeff Kirsher #define RXBUF_ALIGNMENT 64 69ec21e2ecSJeff Kirsher 70ec21e2ecSJeff Kirsher #define PHY_INIT_TIMEOUT 100000 71ec21e2ecSJeff Kirsher 72ec21e2ecSJeff Kirsher #define DRV_NAME "gfar-enet" 73ec21e2ecSJeff Kirsher extern const char gfar_driver_version[]; 74ec21e2ecSJeff Kirsher 75ec21e2ecSJeff Kirsher /* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 76ec21e2ecSJeff Kirsher #define MAX_TX_QS 0x8 77ec21e2ecSJeff Kirsher #define MAX_RX_QS 0x8 78ec21e2ecSJeff Kirsher 79ec21e2ecSJeff Kirsher /* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 80ec21e2ecSJeff Kirsher #define MAXGROUPS 0x2 81ec21e2ecSJeff Kirsher 82ec21e2ecSJeff Kirsher /* These need to be powers of 2 for this driver */ 83ec21e2ecSJeff Kirsher #define DEFAULT_TX_RING_SIZE 256 84ec21e2ecSJeff Kirsher #define DEFAULT_RX_RING_SIZE 256 85ec21e2ecSJeff Kirsher 8676f31e8bSClaudiu Manoil #define GFAR_RX_BUFF_ALLOC 16 8776f31e8bSClaudiu Manoil 88ec21e2ecSJeff Kirsher #define GFAR_RX_MAX_RING_SIZE 256 89ec21e2ecSJeff Kirsher #define GFAR_TX_MAX_RING_SIZE 256 90ec21e2ecSJeff Kirsher 91ec21e2ecSJeff Kirsher #define GFAR_MAX_FIFO_THRESHOLD 511 92ec21e2ecSJeff Kirsher #define GFAR_MAX_FIFO_STARVE 511 93ec21e2ecSJeff Kirsher #define GFAR_MAX_FIFO_STARVE_OFF 511 94ec21e2ecSJeff Kirsher 9545b679c9SMatei Pavaluca #define FBTHR_SHIFT 24 9645b679c9SMatei Pavaluca #define DEFAULT_RX_LFC_THR 16 9745b679c9SMatei Pavaluca #define DEFAULT_LFC_PTVVAL 4 9845b679c9SMatei Pavaluca 99b323431bSZefir Kurtisi /* prevent fragmenation by HW in DSA environments */ 100b323431bSZefir Kurtisi #define GFAR_RXB_SIZE roundup(1536 + 8, 64) 10175354148SClaudiu Manoil #define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \ 10275354148SClaudiu Manoil + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 10375354148SClaudiu Manoil #define GFAR_RXB_TRUESIZE 2048 10475354148SClaudiu Manoil 105ec21e2ecSJeff Kirsher #define TX_RING_MOD_MASK(size) (size-1) 106ec21e2ecSJeff Kirsher #define RX_RING_MOD_MASK(size) (size-1) 10775354148SClaudiu Manoil #define GFAR_JUMBO_FRAME_SIZE 9600 108ec21e2ecSJeff Kirsher 109ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_THR 0x100 110ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_STARVE 0x40 111ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 112ec21e2ecSJeff Kirsher #define DEFAULT_BD_STASH 1 113ec21e2ecSJeff Kirsher #define DEFAULT_STASH_LENGTH 96 114ec21e2ecSJeff Kirsher #define DEFAULT_STASH_INDEX 0 115ec21e2ecSJeff Kirsher 116ec21e2ecSJeff Kirsher /* The number of Exact Match registers */ 117ec21e2ecSJeff Kirsher #define GFAR_EM_NUM 15 118ec21e2ecSJeff Kirsher 119ec21e2ecSJeff Kirsher /* Latency of interface clock in nanoseconds */ 120ec21e2ecSJeff Kirsher /* Interface clock latency , in this case, means the 121ec21e2ecSJeff Kirsher * time described by a value of 1 in the interrupt 122ec21e2ecSJeff Kirsher * coalescing registers' time fields. Since those fields 123ec21e2ecSJeff Kirsher * refer to the time it takes for 64 clocks to pass, the 124ec21e2ecSJeff Kirsher * latencies are as such: 125ec21e2ecSJeff Kirsher * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 126ec21e2ecSJeff Kirsher * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 127ec21e2ecSJeff Kirsher * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 128ec21e2ecSJeff Kirsher */ 129ec21e2ecSJeff Kirsher #define GFAR_GBIT_TIME 512 130ec21e2ecSJeff Kirsher #define GFAR_100_TIME 2560 131ec21e2ecSJeff Kirsher #define GFAR_10_TIME 25600 132ec21e2ecSJeff Kirsher 133ec21e2ecSJeff Kirsher #define DEFAULT_TX_COALESCE 1 134ec21e2ecSJeff Kirsher #define DEFAULT_TXCOUNT 16 135ec21e2ecSJeff Kirsher #define DEFAULT_TXTIME 21 136ec21e2ecSJeff Kirsher 137ec21e2ecSJeff Kirsher #define DEFAULT_RXTIME 21 138ec21e2ecSJeff Kirsher 139ec21e2ecSJeff Kirsher #define DEFAULT_RX_COALESCE 0 140ec21e2ecSJeff Kirsher #define DEFAULT_RXCOUNT 0 141ec21e2ecSJeff Kirsher 142ec21e2ecSJeff Kirsher #define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \ 143ec21e2ecSJeff Kirsher | SUPPORTED_10baseT_Full \ 144ec21e2ecSJeff Kirsher | SUPPORTED_100baseT_Half \ 145ec21e2ecSJeff Kirsher | SUPPORTED_100baseT_Full \ 146ec21e2ecSJeff Kirsher | SUPPORTED_Autoneg \ 147ec21e2ecSJeff Kirsher | SUPPORTED_MII) 148ec21e2ecSJeff Kirsher 149cf987afcSPavaluca Matei-B46610 #define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full 15023402bddSClaudiu Manoil 151ec21e2ecSJeff Kirsher /* TBI register addresses */ 152ec21e2ecSJeff Kirsher #define MII_TBICON 0x11 153ec21e2ecSJeff Kirsher 154ec21e2ecSJeff Kirsher /* TBICON register bit fields */ 155ec21e2ecSJeff Kirsher #define TBICON_CLK_SELECT 0x0020 156ec21e2ecSJeff Kirsher 157ec21e2ecSJeff Kirsher /* MAC register bits */ 158ec21e2ecSJeff Kirsher #define MACCFG1_SOFT_RESET 0x80000000 159ec21e2ecSJeff Kirsher #define MACCFG1_RESET_RX_MC 0x00080000 160ec21e2ecSJeff Kirsher #define MACCFG1_RESET_TX_MC 0x00040000 161ec21e2ecSJeff Kirsher #define MACCFG1_RESET_RX_FUN 0x00020000 162ec21e2ecSJeff Kirsher #define MACCFG1_RESET_TX_FUN 0x00010000 163ec21e2ecSJeff Kirsher #define MACCFG1_LOOPBACK 0x00000100 164ec21e2ecSJeff Kirsher #define MACCFG1_RX_FLOW 0x00000020 165ec21e2ecSJeff Kirsher #define MACCFG1_TX_FLOW 0x00000010 166ec21e2ecSJeff Kirsher #define MACCFG1_SYNCD_RX_EN 0x00000008 167ec21e2ecSJeff Kirsher #define MACCFG1_RX_EN 0x00000004 168ec21e2ecSJeff Kirsher #define MACCFG1_SYNCD_TX_EN 0x00000002 169ec21e2ecSJeff Kirsher #define MACCFG1_TX_EN 0x00000001 170ec21e2ecSJeff Kirsher 171ec21e2ecSJeff Kirsher #define MACCFG2_INIT_SETTINGS 0x00007205 172ec21e2ecSJeff Kirsher #define MACCFG2_FULL_DUPLEX 0x00000001 173ec21e2ecSJeff Kirsher #define MACCFG2_IF 0x00000300 174ec21e2ecSJeff Kirsher #define MACCFG2_MII 0x00000100 175ec21e2ecSJeff Kirsher #define MACCFG2_GMII 0x00000200 176ec21e2ecSJeff Kirsher #define MACCFG2_HUGEFRAME 0x00000020 177ec21e2ecSJeff Kirsher #define MACCFG2_LENGTHCHECK 0x00000010 178ec21e2ecSJeff Kirsher #define MACCFG2_MPEN 0x00000008 179ec21e2ecSJeff Kirsher 180ec21e2ecSJeff Kirsher #define ECNTRL_FIFM 0x00008000 181ec21e2ecSJeff Kirsher #define ECNTRL_INIT_SETTINGS 0x00001000 182ec21e2ecSJeff Kirsher #define ECNTRL_TBI_MODE 0x00000020 183ec21e2ecSJeff Kirsher #define ECNTRL_REDUCED_MODE 0x00000010 184ec21e2ecSJeff Kirsher #define ECNTRL_R100 0x00000008 185ec21e2ecSJeff Kirsher #define ECNTRL_REDUCED_MII_MODE 0x00000004 186ec21e2ecSJeff Kirsher #define ECNTRL_SGMII_MODE 0x00000002 187ec21e2ecSJeff Kirsher 188ec21e2ecSJeff Kirsher #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 189ec21e2ecSJeff Kirsher 190ec21e2ecSJeff Kirsher #define MINFLR_INIT_SETTINGS 0x00000040 191ec21e2ecSJeff Kirsher 192ec21e2ecSJeff Kirsher /* Tqueue control */ 193ec21e2ecSJeff Kirsher #define TQUEUE_EN0 0x00008000 194ec21e2ecSJeff Kirsher #define TQUEUE_EN1 0x00004000 195ec21e2ecSJeff Kirsher #define TQUEUE_EN2 0x00002000 196ec21e2ecSJeff Kirsher #define TQUEUE_EN3 0x00001000 197ec21e2ecSJeff Kirsher #define TQUEUE_EN4 0x00000800 198ec21e2ecSJeff Kirsher #define TQUEUE_EN5 0x00000400 199ec21e2ecSJeff Kirsher #define TQUEUE_EN6 0x00000200 200ec21e2ecSJeff Kirsher #define TQUEUE_EN7 0x00000100 201ec21e2ecSJeff Kirsher #define TQUEUE_EN_ALL 0x0000FF00 202ec21e2ecSJeff Kirsher 203ec21e2ecSJeff Kirsher #define TR03WT_WT0_MASK 0xFF000000 204ec21e2ecSJeff Kirsher #define TR03WT_WT1_MASK 0x00FF0000 205ec21e2ecSJeff Kirsher #define TR03WT_WT2_MASK 0x0000FF00 206ec21e2ecSJeff Kirsher #define TR03WT_WT3_MASK 0x000000FF 207ec21e2ecSJeff Kirsher 208ec21e2ecSJeff Kirsher #define TR47WT_WT4_MASK 0xFF000000 209ec21e2ecSJeff Kirsher #define TR47WT_WT5_MASK 0x00FF0000 210ec21e2ecSJeff Kirsher #define TR47WT_WT6_MASK 0x0000FF00 211ec21e2ecSJeff Kirsher #define TR47WT_WT7_MASK 0x000000FF 212ec21e2ecSJeff Kirsher 213ec21e2ecSJeff Kirsher /* Rqueue control */ 214ec21e2ecSJeff Kirsher #define RQUEUE_EX0 0x00800000 215ec21e2ecSJeff Kirsher #define RQUEUE_EX1 0x00400000 216ec21e2ecSJeff Kirsher #define RQUEUE_EX2 0x00200000 217ec21e2ecSJeff Kirsher #define RQUEUE_EX3 0x00100000 218ec21e2ecSJeff Kirsher #define RQUEUE_EX4 0x00080000 219ec21e2ecSJeff Kirsher #define RQUEUE_EX5 0x00040000 220ec21e2ecSJeff Kirsher #define RQUEUE_EX6 0x00020000 221ec21e2ecSJeff Kirsher #define RQUEUE_EX7 0x00010000 222ec21e2ecSJeff Kirsher #define RQUEUE_EX_ALL 0x00FF0000 223ec21e2ecSJeff Kirsher 224ec21e2ecSJeff Kirsher #define RQUEUE_EN0 0x00000080 225ec21e2ecSJeff Kirsher #define RQUEUE_EN1 0x00000040 226ec21e2ecSJeff Kirsher #define RQUEUE_EN2 0x00000020 227ec21e2ecSJeff Kirsher #define RQUEUE_EN3 0x00000010 228ec21e2ecSJeff Kirsher #define RQUEUE_EN4 0x00000008 229ec21e2ecSJeff Kirsher #define RQUEUE_EN5 0x00000004 230ec21e2ecSJeff Kirsher #define RQUEUE_EN6 0x00000002 231ec21e2ecSJeff Kirsher #define RQUEUE_EN7 0x00000001 232ec21e2ecSJeff Kirsher #define RQUEUE_EN_ALL 0x000000FF 233ec21e2ecSJeff Kirsher 234ec21e2ecSJeff Kirsher /* Init to do tx snooping for buffers and descriptors */ 235ec21e2ecSJeff Kirsher #define DMACTRL_INIT_SETTINGS 0x000000c3 236ec21e2ecSJeff Kirsher #define DMACTRL_GRS 0x00000010 237ec21e2ecSJeff Kirsher #define DMACTRL_GTS 0x00000008 238ec21e2ecSJeff Kirsher 239ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT_ALL 0xFF000000 240ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT 0x80000000 241ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT0 0x80000000 242ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT1 0x40000000 243ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT2 0x20000000 244ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT3 0x10000000 245ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT4 0x08000000 246ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT5 0x04000000 247ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT6 0x02000000 248ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT7 0x01000000 249ec21e2ecSJeff Kirsher 250ec21e2ecSJeff Kirsher /* Interrupt coalescing macros */ 251ec21e2ecSJeff Kirsher #define IC_ICEN 0x80000000 252ec21e2ecSJeff Kirsher #define IC_ICFT_MASK 0x1fe00000 253ec21e2ecSJeff Kirsher #define IC_ICFT_SHIFT 21 254ec21e2ecSJeff Kirsher #define mk_ic_icft(x) \ 255ec21e2ecSJeff Kirsher (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 256ec21e2ecSJeff Kirsher #define IC_ICTT_MASK 0x0000ffff 257ec21e2ecSJeff Kirsher #define mk_ic_ictt(x) (x&IC_ICTT_MASK) 258ec21e2ecSJeff Kirsher 259ec21e2ecSJeff Kirsher #define mk_ic_value(count, time) (IC_ICEN | \ 260ec21e2ecSJeff Kirsher mk_ic_icft(count) | \ 261ec21e2ecSJeff Kirsher mk_ic_ictt(time)) 262ec21e2ecSJeff Kirsher #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 263ec21e2ecSJeff Kirsher IC_ICFT_SHIFT) 264ec21e2ecSJeff Kirsher #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 265ec21e2ecSJeff Kirsher 266ec21e2ecSJeff Kirsher #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 267ec21e2ecSJeff Kirsher #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 268ec21e2ecSJeff Kirsher 269ec21e2ecSJeff Kirsher #define skip_bd(bdp, stride, base, ring_size) ({ \ 270ec21e2ecSJeff Kirsher typeof(bdp) new_bd = (bdp) + (stride); \ 271ec21e2ecSJeff Kirsher (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; }) 272ec21e2ecSJeff Kirsher 273ec21e2ecSJeff Kirsher #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size) 274ec21e2ecSJeff Kirsher 275ec21e2ecSJeff Kirsher #define RCTRL_TS_ENABLE 0x01000000 276ec21e2ecSJeff Kirsher #define RCTRL_PAL_MASK 0x001f0000 27745b679c9SMatei Pavaluca #define RCTRL_LFC 0x00004000 278ec21e2ecSJeff Kirsher #define RCTRL_VLEX 0x00002000 279ec21e2ecSJeff Kirsher #define RCTRL_FILREN 0x00001000 280ec21e2ecSJeff Kirsher #define RCTRL_GHTX 0x00000400 281ec21e2ecSJeff Kirsher #define RCTRL_IPCSEN 0x00000200 282ec21e2ecSJeff Kirsher #define RCTRL_TUCSEN 0x00000100 283ec21e2ecSJeff Kirsher #define RCTRL_PRSDEP_MASK 0x000000c0 284ec21e2ecSJeff Kirsher #define RCTRL_PRSDEP_INIT 0x000000c0 285ec21e2ecSJeff Kirsher #define RCTRL_PRSFM 0x00000020 286ec21e2ecSJeff Kirsher #define RCTRL_PROM 0x00000008 287ec21e2ecSJeff Kirsher #define RCTRL_EMEN 0x00000002 288ec21e2ecSJeff Kirsher #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 289ec21e2ecSJeff Kirsher RCTRL_TUCSEN | RCTRL_FILREN) 290ec21e2ecSJeff Kirsher #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 291ec21e2ecSJeff Kirsher RCTRL_PRSDEP_INIT) 292ec21e2ecSJeff Kirsher #define RCTRL_EXTHASH (RCTRL_GHTX) 293ec21e2ecSJeff Kirsher #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 294ec21e2ecSJeff Kirsher #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 295ec21e2ecSJeff Kirsher 296ec21e2ecSJeff Kirsher 297ec21e2ecSJeff Kirsher #define RSTAT_CLEAR_RHALT 0x00800000 2986be5ed3fSClaudiu Manoil #define RSTAT_CLEAR_RXF0 0x00000080 2996be5ed3fSClaudiu Manoil #define RSTAT_RXF_MASK 0x000000ff 300ec21e2ecSJeff Kirsher 301ec21e2ecSJeff Kirsher #define TCTRL_IPCSEN 0x00004000 302ec21e2ecSJeff Kirsher #define TCTRL_TUCSEN 0x00002000 303ec21e2ecSJeff Kirsher #define TCTRL_VLINS 0x00001000 304ec21e2ecSJeff Kirsher #define TCTRL_THDF 0x00000800 305ec21e2ecSJeff Kirsher #define TCTRL_RFCPAUSE 0x00000010 306ec21e2ecSJeff Kirsher #define TCTRL_TFCPAUSE 0x00000008 307ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_MASK 0x00000006 308ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_INIT 0x00000000 309b98b8babSClaudiu Manoil /* priority scheduling */ 310ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_PRIO 0x00000002 311b98b8babSClaudiu Manoil /* weighted round-robin scheduling (WRRS) */ 312ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_WRRS 0x00000004 313b98b8babSClaudiu Manoil /* default WRRS weight and policy setting, 314b98b8babSClaudiu Manoil * tailored to the tr03wt and tr47wt registers: 315b98b8babSClaudiu Manoil * equal weight for all Tx Qs, measured in 64byte units 316b98b8babSClaudiu Manoil */ 317b98b8babSClaudiu Manoil #define DEFAULT_WRRS_WEIGHT 0x18181818 318b98b8babSClaudiu Manoil 319ec21e2ecSJeff Kirsher #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 320ec21e2ecSJeff Kirsher 321ec21e2ecSJeff Kirsher #define IEVENT_INIT_CLEAR 0xffffffff 322ec21e2ecSJeff Kirsher #define IEVENT_BABR 0x80000000 323ec21e2ecSJeff Kirsher #define IEVENT_RXC 0x40000000 324ec21e2ecSJeff Kirsher #define IEVENT_BSY 0x20000000 325ec21e2ecSJeff Kirsher #define IEVENT_EBERR 0x10000000 326ec21e2ecSJeff Kirsher #define IEVENT_MSRO 0x04000000 327ec21e2ecSJeff Kirsher #define IEVENT_GTSC 0x02000000 328ec21e2ecSJeff Kirsher #define IEVENT_BABT 0x01000000 329ec21e2ecSJeff Kirsher #define IEVENT_TXC 0x00800000 330ec21e2ecSJeff Kirsher #define IEVENT_TXE 0x00400000 331ec21e2ecSJeff Kirsher #define IEVENT_TXB 0x00200000 332ec21e2ecSJeff Kirsher #define IEVENT_TXF 0x00100000 333ec21e2ecSJeff Kirsher #define IEVENT_LC 0x00040000 334ec21e2ecSJeff Kirsher #define IEVENT_CRL 0x00020000 335ec21e2ecSJeff Kirsher #define IEVENT_XFUN 0x00010000 336ec21e2ecSJeff Kirsher #define IEVENT_RXB0 0x00008000 337ec21e2ecSJeff Kirsher #define IEVENT_MAG 0x00000800 338ec21e2ecSJeff Kirsher #define IEVENT_GRSC 0x00000100 339ec21e2ecSJeff Kirsher #define IEVENT_RXF0 0x00000080 3403e905b80SClaudiu Manoil #define IEVENT_FGPI 0x00000010 341ec21e2ecSJeff Kirsher #define IEVENT_FIR 0x00000008 342ec21e2ecSJeff Kirsher #define IEVENT_FIQ 0x00000004 343ec21e2ecSJeff Kirsher #define IEVENT_DPE 0x00000002 344ec21e2ecSJeff Kirsher #define IEVENT_PERR 0x00000001 345ec21e2ecSJeff Kirsher #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 346ec21e2ecSJeff Kirsher #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 347ec21e2ecSJeff Kirsher #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 348ec21e2ecSJeff Kirsher #define IEVENT_ERR_MASK \ 349ec21e2ecSJeff Kirsher (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 350ec21e2ecSJeff Kirsher IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 351ec21e2ecSJeff Kirsher | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 352ec21e2ecSJeff Kirsher | IEVENT_MAG | IEVENT_BABR) 353ec21e2ecSJeff Kirsher 354ec21e2ecSJeff Kirsher #define IMASK_INIT_CLEAR 0x00000000 355ec21e2ecSJeff Kirsher #define IMASK_BABR 0x80000000 356ec21e2ecSJeff Kirsher #define IMASK_RXC 0x40000000 357ec21e2ecSJeff Kirsher #define IMASK_BSY 0x20000000 358ec21e2ecSJeff Kirsher #define IMASK_EBERR 0x10000000 359ec21e2ecSJeff Kirsher #define IMASK_MSRO 0x04000000 360ec21e2ecSJeff Kirsher #define IMASK_GTSC 0x02000000 361ec21e2ecSJeff Kirsher #define IMASK_BABT 0x01000000 362ec21e2ecSJeff Kirsher #define IMASK_TXC 0x00800000 363ec21e2ecSJeff Kirsher #define IMASK_TXEEN 0x00400000 364ec21e2ecSJeff Kirsher #define IMASK_TXBEN 0x00200000 365ec21e2ecSJeff Kirsher #define IMASK_TXFEN 0x00100000 366ec21e2ecSJeff Kirsher #define IMASK_LC 0x00040000 367ec21e2ecSJeff Kirsher #define IMASK_CRL 0x00020000 368ec21e2ecSJeff Kirsher #define IMASK_XFUN 0x00010000 369ec21e2ecSJeff Kirsher #define IMASK_RXB0 0x00008000 370ec21e2ecSJeff Kirsher #define IMASK_MAG 0x00000800 371ec21e2ecSJeff Kirsher #define IMASK_GRSC 0x00000100 372ec21e2ecSJeff Kirsher #define IMASK_RXFEN0 0x00000080 3733e905b80SClaudiu Manoil #define IMASK_FGPI 0x00000010 374ec21e2ecSJeff Kirsher #define IMASK_FIR 0x00000008 375ec21e2ecSJeff Kirsher #define IMASK_FIQ 0x00000004 376ec21e2ecSJeff Kirsher #define IMASK_DPE 0x00000002 377ec21e2ecSJeff Kirsher #define IMASK_PERR 0x00000001 378ec21e2ecSJeff Kirsher #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 379ec21e2ecSJeff Kirsher IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 380ec21e2ecSJeff Kirsher IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 381ec21e2ecSJeff Kirsher | IMASK_PERR) 382aeb12c5eSClaudiu Manoil #define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY) 383aeb12c5eSClaudiu Manoil #define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN) 384aeb12c5eSClaudiu Manoil 385aeb12c5eSClaudiu Manoil #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT) 386aeb12c5eSClaudiu Manoil #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT) 387ec21e2ecSJeff Kirsher 388ec21e2ecSJeff Kirsher /* Fifo management */ 389ec21e2ecSJeff Kirsher #define FIFO_TX_THR_MASK 0x01ff 390ec21e2ecSJeff Kirsher #define FIFO_TX_STARVE_MASK 0x01ff 391ec21e2ecSJeff Kirsher #define FIFO_TX_STARVE_OFF_MASK 0x01ff 392ec21e2ecSJeff Kirsher 393ec21e2ecSJeff Kirsher /* Attribute fields */ 394ec21e2ecSJeff Kirsher 395ec21e2ecSJeff Kirsher /* This enables rx snooping for buffers and descriptors */ 396ec21e2ecSJeff Kirsher #define ATTR_BDSTASH 0x00000800 397ec21e2ecSJeff Kirsher 398ec21e2ecSJeff Kirsher #define ATTR_BUFSTASH 0x00004000 399ec21e2ecSJeff Kirsher 400ec21e2ecSJeff Kirsher #define ATTR_SNOOPING 0x000000c0 401ec21e2ecSJeff Kirsher #define ATTR_INIT_SETTINGS ATTR_SNOOPING 402ec21e2ecSJeff Kirsher 403ec21e2ecSJeff Kirsher #define ATTRELI_INIT_SETTINGS 0x0 404ec21e2ecSJeff Kirsher #define ATTRELI_EL_MASK 0x3fff0000 405ec21e2ecSJeff Kirsher #define ATTRELI_EL(x) (x << 16) 406ec21e2ecSJeff Kirsher #define ATTRELI_EI_MASK 0x00003fff 407ec21e2ecSJeff Kirsher #define ATTRELI_EI(x) (x) 408ec21e2ecSJeff Kirsher 409ec21e2ecSJeff Kirsher #define BD_LFLAG(flags) ((flags) << 16) 410ec21e2ecSJeff Kirsher #define BD_LENGTH_MASK 0x0000ffff 411ec21e2ecSJeff Kirsher 412ec21e2ecSJeff Kirsher #define FPR_FILER_MASK 0xFFFFFFFF 413ec21e2ecSJeff Kirsher #define MAX_FILER_IDX 0xFF 414ec21e2ecSJeff Kirsher 415ec21e2ecSJeff Kirsher /* This default RIR value directly corresponds 416ec21e2ecSJeff Kirsher * to the 3-bit hash value generated */ 41771ff9e3dSClaudiu Manoil #define DEFAULT_8RXQ_RIR0 0x05397700 41871ff9e3dSClaudiu Manoil /* Map even hash values to Q0, and odd ones to Q1 */ 41971ff9e3dSClaudiu Manoil #define DEFAULT_2RXQ_RIR0 0x04104100 420ec21e2ecSJeff Kirsher 421ec21e2ecSJeff Kirsher /* RQFCR register bits */ 422ec21e2ecSJeff Kirsher #define RQFCR_GPI 0x80000000 423ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_Q 0x00000000 424ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_0 0x00020000 425ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_1 0x00040000 426ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_2 0x00060000 427ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_3 0x00080000 428ec21e2ecSJeff Kirsher #define RQFCR_HASH 0x00010000 429ec21e2ecSJeff Kirsher #define RQFCR_QUEUE 0x0000FC00 430ec21e2ecSJeff Kirsher #define RQFCR_CLE 0x00000200 431ec21e2ecSJeff Kirsher #define RQFCR_RJE 0x00000100 432ec21e2ecSJeff Kirsher #define RQFCR_AND 0x00000080 433ec21e2ecSJeff Kirsher #define RQFCR_CMP_EXACT 0x00000000 434ec21e2ecSJeff Kirsher #define RQFCR_CMP_MATCH 0x00000020 435ec21e2ecSJeff Kirsher #define RQFCR_CMP_NOEXACT 0x00000040 436ec21e2ecSJeff Kirsher #define RQFCR_CMP_NOMATCH 0x00000060 437ec21e2ecSJeff Kirsher 438ec21e2ecSJeff Kirsher /* RQFCR PID values */ 439ec21e2ecSJeff Kirsher #define RQFCR_PID_MASK 0x00000000 440ec21e2ecSJeff Kirsher #define RQFCR_PID_PARSE 0x00000001 441ec21e2ecSJeff Kirsher #define RQFCR_PID_ARB 0x00000002 442ec21e2ecSJeff Kirsher #define RQFCR_PID_DAH 0x00000003 443ec21e2ecSJeff Kirsher #define RQFCR_PID_DAL 0x00000004 444ec21e2ecSJeff Kirsher #define RQFCR_PID_SAH 0x00000005 445ec21e2ecSJeff Kirsher #define RQFCR_PID_SAL 0x00000006 446ec21e2ecSJeff Kirsher #define RQFCR_PID_ETY 0x00000007 447ec21e2ecSJeff Kirsher #define RQFCR_PID_VID 0x00000008 448ec21e2ecSJeff Kirsher #define RQFCR_PID_PRI 0x00000009 449ec21e2ecSJeff Kirsher #define RQFCR_PID_TOS 0x0000000A 450ec21e2ecSJeff Kirsher #define RQFCR_PID_L4P 0x0000000B 451ec21e2ecSJeff Kirsher #define RQFCR_PID_DIA 0x0000000C 452ec21e2ecSJeff Kirsher #define RQFCR_PID_SIA 0x0000000D 453ec21e2ecSJeff Kirsher #define RQFCR_PID_DPT 0x0000000E 454ec21e2ecSJeff Kirsher #define RQFCR_PID_SPT 0x0000000F 455ec21e2ecSJeff Kirsher 456ec21e2ecSJeff Kirsher /* RQFPR when PID is 0x0001 */ 457ec21e2ecSJeff Kirsher #define RQFPR_HDR_GE_512 0x00200000 458ec21e2ecSJeff Kirsher #define RQFPR_LERR 0x00100000 459ec21e2ecSJeff Kirsher #define RQFPR_RAR 0x00080000 460ec21e2ecSJeff Kirsher #define RQFPR_RARQ 0x00040000 461ec21e2ecSJeff Kirsher #define RQFPR_AR 0x00020000 462ec21e2ecSJeff Kirsher #define RQFPR_ARQ 0x00010000 463ec21e2ecSJeff Kirsher #define RQFPR_EBC 0x00008000 464ec21e2ecSJeff Kirsher #define RQFPR_VLN 0x00004000 465ec21e2ecSJeff Kirsher #define RQFPR_CFI 0x00002000 466ec21e2ecSJeff Kirsher #define RQFPR_JUM 0x00001000 467ec21e2ecSJeff Kirsher #define RQFPR_IPF 0x00000800 468ec21e2ecSJeff Kirsher #define RQFPR_FIF 0x00000400 469ec21e2ecSJeff Kirsher #define RQFPR_IPV4 0x00000200 470ec21e2ecSJeff Kirsher #define RQFPR_IPV6 0x00000100 471ec21e2ecSJeff Kirsher #define RQFPR_ICC 0x00000080 472ec21e2ecSJeff Kirsher #define RQFPR_ICV 0x00000040 473ec21e2ecSJeff Kirsher #define RQFPR_TCP 0x00000020 474ec21e2ecSJeff Kirsher #define RQFPR_UDP 0x00000010 475ec21e2ecSJeff Kirsher #define RQFPR_TUC 0x00000008 476ec21e2ecSJeff Kirsher #define RQFPR_TUV 0x00000004 477ec21e2ecSJeff Kirsher #define RQFPR_PER 0x00000002 478ec21e2ecSJeff Kirsher #define RQFPR_EER 0x00000001 479ec21e2ecSJeff Kirsher 480ec21e2ecSJeff Kirsher /* TxBD status field bits */ 481ec21e2ecSJeff Kirsher #define TXBD_READY 0x8000 482ec21e2ecSJeff Kirsher #define TXBD_PADCRC 0x4000 483ec21e2ecSJeff Kirsher #define TXBD_WRAP 0x2000 484ec21e2ecSJeff Kirsher #define TXBD_INTERRUPT 0x1000 485ec21e2ecSJeff Kirsher #define TXBD_LAST 0x0800 486ec21e2ecSJeff Kirsher #define TXBD_CRC 0x0400 487ec21e2ecSJeff Kirsher #define TXBD_DEF 0x0200 488ec21e2ecSJeff Kirsher #define TXBD_HUGEFRAME 0x0080 489ec21e2ecSJeff Kirsher #define TXBD_LATECOLLISION 0x0080 490ec21e2ecSJeff Kirsher #define TXBD_RETRYLIMIT 0x0040 491ec21e2ecSJeff Kirsher #define TXBD_RETRYCOUNTMASK 0x003c 492ec21e2ecSJeff Kirsher #define TXBD_UNDERRUN 0x0002 493ec21e2ecSJeff Kirsher #define TXBD_TOE 0x0002 494ec21e2ecSJeff Kirsher 495ec21e2ecSJeff Kirsher /* Tx FCB param bits */ 496ec21e2ecSJeff Kirsher #define TXFCB_VLN 0x80 497ec21e2ecSJeff Kirsher #define TXFCB_IP 0x40 498ec21e2ecSJeff Kirsher #define TXFCB_IP6 0x20 499ec21e2ecSJeff Kirsher #define TXFCB_TUP 0x10 500ec21e2ecSJeff Kirsher #define TXFCB_UDP 0x08 501ec21e2ecSJeff Kirsher #define TXFCB_CIP 0x04 502ec21e2ecSJeff Kirsher #define TXFCB_CTU 0x02 503ec21e2ecSJeff Kirsher #define TXFCB_NPH 0x01 504ec21e2ecSJeff Kirsher #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 505ec21e2ecSJeff Kirsher 506ec21e2ecSJeff Kirsher /* RxBD status field bits */ 507ec21e2ecSJeff Kirsher #define RXBD_EMPTY 0x8000 508ec21e2ecSJeff Kirsher #define RXBD_RO1 0x4000 509ec21e2ecSJeff Kirsher #define RXBD_WRAP 0x2000 510ec21e2ecSJeff Kirsher #define RXBD_INTERRUPT 0x1000 511ec21e2ecSJeff Kirsher #define RXBD_LAST 0x0800 512ec21e2ecSJeff Kirsher #define RXBD_FIRST 0x0400 513ec21e2ecSJeff Kirsher #define RXBD_MISS 0x0100 514ec21e2ecSJeff Kirsher #define RXBD_BROADCAST 0x0080 515ec21e2ecSJeff Kirsher #define RXBD_MULTICAST 0x0040 516ec21e2ecSJeff Kirsher #define RXBD_LARGE 0x0020 517ec21e2ecSJeff Kirsher #define RXBD_NONOCTET 0x0010 518ec21e2ecSJeff Kirsher #define RXBD_SHORT 0x0008 519ec21e2ecSJeff Kirsher #define RXBD_CRCERR 0x0004 520ec21e2ecSJeff Kirsher #define RXBD_OVERRUN 0x0002 521ec21e2ecSJeff Kirsher #define RXBD_TRUNCATED 0x0001 522ec21e2ecSJeff Kirsher #define RXBD_STATS 0x01ff 523ec21e2ecSJeff Kirsher #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 524ec21e2ecSJeff Kirsher | RXBD_CRCERR | RXBD_OVERRUN \ 525ec21e2ecSJeff Kirsher | RXBD_TRUNCATED) 526ec21e2ecSJeff Kirsher 527ec21e2ecSJeff Kirsher /* Rx FCB status field bits */ 528ec21e2ecSJeff Kirsher #define RXFCB_VLN 0x8000 529ec21e2ecSJeff Kirsher #define RXFCB_IP 0x4000 530ec21e2ecSJeff Kirsher #define RXFCB_IP6 0x2000 531ec21e2ecSJeff Kirsher #define RXFCB_TUP 0x1000 532ec21e2ecSJeff Kirsher #define RXFCB_CIP 0x0800 533ec21e2ecSJeff Kirsher #define RXFCB_CTU 0x0400 534ec21e2ecSJeff Kirsher #define RXFCB_EIP 0x0200 535ec21e2ecSJeff Kirsher #define RXFCB_ETU 0x0100 536ec21e2ecSJeff Kirsher #define RXFCB_CSUM_MASK 0x0f00 537ec21e2ecSJeff Kirsher #define RXFCB_PERR_MASK 0x000c 538ec21e2ecSJeff Kirsher #define RXFCB_PERR_BADL3 0x0008 539ec21e2ecSJeff Kirsher 5400015e551SJoe Perches #define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 541ec21e2ecSJeff Kirsher 5423e905b80SClaudiu Manoil #define GFAR_WOL_MAGIC 0x00000001 5433e905b80SClaudiu Manoil #define GFAR_WOL_FILER_UCAST 0x00000002 5443e905b80SClaudiu Manoil 545ec21e2ecSJeff Kirsher struct txbd8 546ec21e2ecSJeff Kirsher { 547ec21e2ecSJeff Kirsher union { 548ec21e2ecSJeff Kirsher struct { 549a7312d58SClaudiu Manoil __be16 status; /* Status Fields */ 550a7312d58SClaudiu Manoil __be16 length; /* Buffer length */ 551ec21e2ecSJeff Kirsher }; 552a7312d58SClaudiu Manoil __be32 lstatus; 553ec21e2ecSJeff Kirsher }; 554a7312d58SClaudiu Manoil __be32 bufPtr; /* Buffer Pointer */ 555ec21e2ecSJeff Kirsher }; 556ec21e2ecSJeff Kirsher 557ec21e2ecSJeff Kirsher struct txfcb { 558ec21e2ecSJeff Kirsher u8 flags; 559ec21e2ecSJeff Kirsher u8 ptp; /* Flag to enable tx timestamping */ 560ec21e2ecSJeff Kirsher u8 l4os; /* Level 4 Header Offset */ 561ec21e2ecSJeff Kirsher u8 l3os; /* Level 3 Header Offset */ 56226eb9374SClaudiu Manoil __be16 phcs; /* Pseudo-header Checksum */ 56326eb9374SClaudiu Manoil __be16 vlctl; /* VLAN control word */ 564ec21e2ecSJeff Kirsher }; 565ec21e2ecSJeff Kirsher 566ec21e2ecSJeff Kirsher struct rxbd8 567ec21e2ecSJeff Kirsher { 568ec21e2ecSJeff Kirsher union { 569ec21e2ecSJeff Kirsher struct { 570a7312d58SClaudiu Manoil __be16 status; /* Status Fields */ 571a7312d58SClaudiu Manoil __be16 length; /* Buffer Length */ 572ec21e2ecSJeff Kirsher }; 573a7312d58SClaudiu Manoil __be32 lstatus; 574ec21e2ecSJeff Kirsher }; 575a7312d58SClaudiu Manoil __be32 bufPtr; /* Buffer Pointer */ 576ec21e2ecSJeff Kirsher }; 577ec21e2ecSJeff Kirsher 578ec21e2ecSJeff Kirsher struct rxfcb { 57926eb9374SClaudiu Manoil __be16 flags; 580ec21e2ecSJeff Kirsher u8 rq; /* Receive Queue index */ 581ec21e2ecSJeff Kirsher u8 pro; /* Layer 4 Protocol */ 582ec21e2ecSJeff Kirsher u16 reserved; 58326eb9374SClaudiu Manoil __be16 vlctl; /* VLAN control word */ 584ec21e2ecSJeff Kirsher }; 585ec21e2ecSJeff Kirsher 586ec21e2ecSJeff Kirsher struct gianfar_skb_cb { 58750ad076bSClaudiu Manoil unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ 588ec21e2ecSJeff Kirsher }; 589ec21e2ecSJeff Kirsher 590ec21e2ecSJeff Kirsher #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 591ec21e2ecSJeff Kirsher 592ec21e2ecSJeff Kirsher struct rmon_mib 593ec21e2ecSJeff Kirsher { 594ec21e2ecSJeff Kirsher u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 595ec21e2ecSJeff Kirsher u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 596ec21e2ecSJeff Kirsher u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 597ec21e2ecSJeff Kirsher u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 598ec21e2ecSJeff Kirsher u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 599ec21e2ecSJeff Kirsher u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 600ec21e2ecSJeff Kirsher u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 601ec21e2ecSJeff Kirsher u32 rbyt; /* 0x.69c - Receive Byte Counter */ 602ec21e2ecSJeff Kirsher u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 603ec21e2ecSJeff Kirsher u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 604ec21e2ecSJeff Kirsher u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 605ec21e2ecSJeff Kirsher u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 606ec21e2ecSJeff Kirsher u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 607ec21e2ecSJeff Kirsher u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 608ec21e2ecSJeff Kirsher u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 609ec21e2ecSJeff Kirsher u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 610ec21e2ecSJeff Kirsher u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 611ec21e2ecSJeff Kirsher u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 612ec21e2ecSJeff Kirsher u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 613ec21e2ecSJeff Kirsher u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 614ec21e2ecSJeff Kirsher u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 615ec21e2ecSJeff Kirsher u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 616ec21e2ecSJeff Kirsher u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 617ec21e2ecSJeff Kirsher u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 618ec21e2ecSJeff Kirsher u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 619ec21e2ecSJeff Kirsher u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 620ec21e2ecSJeff Kirsher u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 621ec21e2ecSJeff Kirsher u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 622ec21e2ecSJeff Kirsher u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 623ec21e2ecSJeff Kirsher u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 624ec21e2ecSJeff Kirsher u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 625ec21e2ecSJeff Kirsher u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 626ec21e2ecSJeff Kirsher u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 627ec21e2ecSJeff Kirsher u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 628ec21e2ecSJeff Kirsher u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 629ec21e2ecSJeff Kirsher u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 630ec21e2ecSJeff Kirsher u8 res1[4]; 631ec21e2ecSJeff Kirsher u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 632ec21e2ecSJeff Kirsher u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 633ec21e2ecSJeff Kirsher u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 634ec21e2ecSJeff Kirsher u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 635ec21e2ecSJeff Kirsher u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 636ec21e2ecSJeff Kirsher u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 637ec21e2ecSJeff Kirsher u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 638ec21e2ecSJeff Kirsher u32 car1; /* 0x.730 - Carry Register One */ 639ec21e2ecSJeff Kirsher u32 car2; /* 0x.734 - Carry Register Two */ 640ec21e2ecSJeff Kirsher u32 cam1; /* 0x.738 - Carry Mask Register One */ 641ec21e2ecSJeff Kirsher u32 cam2; /* 0x.73c - Carry Mask Register Two */ 642ec21e2ecSJeff Kirsher }; 643ec21e2ecSJeff Kirsher 644ec21e2ecSJeff Kirsher struct gfar_extra_stats { 64576f31e8bSClaudiu Manoil atomic64_t rx_alloc_err; 646212079dfSPaul Gortmaker atomic64_t rx_large; 647212079dfSPaul Gortmaker atomic64_t rx_short; 648212079dfSPaul Gortmaker atomic64_t rx_nonoctet; 649212079dfSPaul Gortmaker atomic64_t rx_crcerr; 650212079dfSPaul Gortmaker atomic64_t rx_overrun; 651212079dfSPaul Gortmaker atomic64_t rx_bsy; 652212079dfSPaul Gortmaker atomic64_t rx_babr; 653212079dfSPaul Gortmaker atomic64_t rx_trunc; 654212079dfSPaul Gortmaker atomic64_t eberr; 655212079dfSPaul Gortmaker atomic64_t tx_babt; 656212079dfSPaul Gortmaker atomic64_t tx_underrun; 657212079dfSPaul Gortmaker atomic64_t tx_timeout; 658ec21e2ecSJeff Kirsher }; 659ec21e2ecSJeff Kirsher 660ec21e2ecSJeff Kirsher #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 661212079dfSPaul Gortmaker #define GFAR_EXTRA_STATS_LEN \ 662212079dfSPaul Gortmaker (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 663ec21e2ecSJeff Kirsher 66468719786SPaul Gortmaker /* Number of stats exported via ethtool */ 665ec21e2ecSJeff Kirsher #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 666ec21e2ecSJeff Kirsher 667ec21e2ecSJeff Kirsher struct gfar { 668ec21e2ecSJeff Kirsher u32 tsec_id; /* 0x.000 - Controller ID register */ 669ec21e2ecSJeff Kirsher u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 670ec21e2ecSJeff Kirsher u8 res1[8]; 671ec21e2ecSJeff Kirsher u32 ievent; /* 0x.010 - Interrupt Event Register */ 672ec21e2ecSJeff Kirsher u32 imask; /* 0x.014 - Interrupt Mask Register */ 673ec21e2ecSJeff Kirsher u32 edis; /* 0x.018 - Error Disabled Register */ 674ec21e2ecSJeff Kirsher u32 emapg; /* 0x.01c - Group Error mapping register */ 675ec21e2ecSJeff Kirsher u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 676ec21e2ecSJeff Kirsher u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 677ec21e2ecSJeff Kirsher u32 ptv; /* 0x.028 - Pause Time Value Register */ 678ec21e2ecSJeff Kirsher u32 dmactrl; /* 0x.02c - DMA Control Register */ 679ec21e2ecSJeff Kirsher u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 680ec21e2ecSJeff Kirsher u8 res2[28]; 681ec21e2ecSJeff Kirsher u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 682ec21e2ecSJeff Kirsher register */ 683ec21e2ecSJeff Kirsher u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 684ec21e2ecSJeff Kirsher register */ 685ec21e2ecSJeff Kirsher u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 686ec21e2ecSJeff Kirsher register */ 687ec21e2ecSJeff Kirsher u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 688ec21e2ecSJeff Kirsher shutoff register */ 689ec21e2ecSJeff Kirsher u8 res3[44]; 690ec21e2ecSJeff Kirsher u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 691ec21e2ecSJeff Kirsher u8 res4[8]; 692ec21e2ecSJeff Kirsher u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 693ec21e2ecSJeff Kirsher u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 694ec21e2ecSJeff Kirsher u8 res5[96]; 695ec21e2ecSJeff Kirsher u32 tctrl; /* 0x.100 - Transmit Control Register */ 696ec21e2ecSJeff Kirsher u32 tstat; /* 0x.104 - Transmit Status Register */ 697ec21e2ecSJeff Kirsher u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 698ec21e2ecSJeff Kirsher u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 699ec21e2ecSJeff Kirsher u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 700ec21e2ecSJeff Kirsher u32 tqueue; /* 0x.114 - Transmit queue control register */ 701ec21e2ecSJeff Kirsher u8 res7[40]; 702ec21e2ecSJeff Kirsher u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 703ec21e2ecSJeff Kirsher u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 704ec21e2ecSJeff Kirsher u8 res8[52]; 705ec21e2ecSJeff Kirsher u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 706ec21e2ecSJeff Kirsher u8 res9a[4]; 707ec21e2ecSJeff Kirsher u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 708ec21e2ecSJeff Kirsher u8 res9b[4]; 709ec21e2ecSJeff Kirsher u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 710ec21e2ecSJeff Kirsher u8 res9c[4]; 711ec21e2ecSJeff Kirsher u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 712ec21e2ecSJeff Kirsher u8 res9d[4]; 713ec21e2ecSJeff Kirsher u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 714ec21e2ecSJeff Kirsher u8 res9e[4]; 715ec21e2ecSJeff Kirsher u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 716ec21e2ecSJeff Kirsher u8 res9f[4]; 717ec21e2ecSJeff Kirsher u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 718ec21e2ecSJeff Kirsher u8 res9g[4]; 719ec21e2ecSJeff Kirsher u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 720ec21e2ecSJeff Kirsher u8 res9h[4]; 721ec21e2ecSJeff Kirsher u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 722ec21e2ecSJeff Kirsher u8 res9[64]; 723ec21e2ecSJeff Kirsher u32 tbaseh; /* 0x.200 - TxBD base address high */ 724ec21e2ecSJeff Kirsher u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 725ec21e2ecSJeff Kirsher u8 res10a[4]; 726ec21e2ecSJeff Kirsher u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 727ec21e2ecSJeff Kirsher u8 res10b[4]; 728ec21e2ecSJeff Kirsher u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 729ec21e2ecSJeff Kirsher u8 res10c[4]; 730ec21e2ecSJeff Kirsher u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 731ec21e2ecSJeff Kirsher u8 res10d[4]; 732ec21e2ecSJeff Kirsher u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 733ec21e2ecSJeff Kirsher u8 res10e[4]; 734ec21e2ecSJeff Kirsher u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 735ec21e2ecSJeff Kirsher u8 res10f[4]; 736ec21e2ecSJeff Kirsher u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 737ec21e2ecSJeff Kirsher u8 res10g[4]; 738ec21e2ecSJeff Kirsher u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 739ec21e2ecSJeff Kirsher u8 res10[192]; 740ec21e2ecSJeff Kirsher u32 rctrl; /* 0x.300 - Receive Control Register */ 741ec21e2ecSJeff Kirsher u32 rstat; /* 0x.304 - Receive Status Register */ 742ec21e2ecSJeff Kirsher u8 res12[8]; 743ec21e2ecSJeff Kirsher u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 744ec21e2ecSJeff Kirsher u32 rqueue; /* 0x.314 - Receive queue control register */ 745ec21e2ecSJeff Kirsher u32 rir0; /* 0x.318 - Ring mapping register 0 */ 746ec21e2ecSJeff Kirsher u32 rir1; /* 0x.31c - Ring mapping register 1 */ 747ec21e2ecSJeff Kirsher u32 rir2; /* 0x.320 - Ring mapping register 2 */ 748ec21e2ecSJeff Kirsher u32 rir3; /* 0x.324 - Ring mapping register 3 */ 749ec21e2ecSJeff Kirsher u8 res13[8]; 750ec21e2ecSJeff Kirsher u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 751ec21e2ecSJeff Kirsher u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 752ec21e2ecSJeff Kirsher u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 753ec21e2ecSJeff Kirsher u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 754ec21e2ecSJeff Kirsher u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 755ec21e2ecSJeff Kirsher u8 res14[56]; 756ec21e2ecSJeff Kirsher u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 757ec21e2ecSJeff Kirsher u8 res15a[4]; 758ec21e2ecSJeff Kirsher u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 759ec21e2ecSJeff Kirsher u8 res15b[4]; 760ec21e2ecSJeff Kirsher u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 761ec21e2ecSJeff Kirsher u8 res15c[4]; 762ec21e2ecSJeff Kirsher u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 763ec21e2ecSJeff Kirsher u8 res15d[4]; 764ec21e2ecSJeff Kirsher u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 765ec21e2ecSJeff Kirsher u8 res15e[4]; 766ec21e2ecSJeff Kirsher u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 767ec21e2ecSJeff Kirsher u8 res15f[4]; 768ec21e2ecSJeff Kirsher u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 769ec21e2ecSJeff Kirsher u8 res15g[4]; 770ec21e2ecSJeff Kirsher u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 771ec21e2ecSJeff Kirsher u8 res15h[4]; 772ec21e2ecSJeff Kirsher u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 773ec21e2ecSJeff Kirsher u8 res16[64]; 774ec21e2ecSJeff Kirsher u32 rbaseh; /* 0x.400 - RxBD base address high */ 775ec21e2ecSJeff Kirsher u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 776ec21e2ecSJeff Kirsher u8 res17a[4]; 777ec21e2ecSJeff Kirsher u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 778ec21e2ecSJeff Kirsher u8 res17b[4]; 779ec21e2ecSJeff Kirsher u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 780ec21e2ecSJeff Kirsher u8 res17c[4]; 781ec21e2ecSJeff Kirsher u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 782ec21e2ecSJeff Kirsher u8 res17d[4]; 783ec21e2ecSJeff Kirsher u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 784ec21e2ecSJeff Kirsher u8 res17e[4]; 785ec21e2ecSJeff Kirsher u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 786ec21e2ecSJeff Kirsher u8 res17f[4]; 787ec21e2ecSJeff Kirsher u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 788ec21e2ecSJeff Kirsher u8 res17g[4]; 789ec21e2ecSJeff Kirsher u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 790ec21e2ecSJeff Kirsher u8 res17[192]; 791ec21e2ecSJeff Kirsher u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 792ec21e2ecSJeff Kirsher u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 793ec21e2ecSJeff Kirsher u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 794ec21e2ecSJeff Kirsher u32 hafdup; /* 0x.50c - Half Duplex Register */ 795ec21e2ecSJeff Kirsher u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 796ec21e2ecSJeff Kirsher u8 res18[12]; 797ec21e2ecSJeff Kirsher u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 798ec21e2ecSJeff Kirsher u32 ifctrl; /* 0x.538 - Interface control register */ 799ec21e2ecSJeff Kirsher u32 ifstat; /* 0x.53c - Interface Status Register */ 800ec21e2ecSJeff Kirsher u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 801ec21e2ecSJeff Kirsher u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 802ec21e2ecSJeff Kirsher u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 803ec21e2ecSJeff Kirsher u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 804ec21e2ecSJeff Kirsher u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 805ec21e2ecSJeff Kirsher u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 806ec21e2ecSJeff Kirsher u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 807ec21e2ecSJeff Kirsher u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 808ec21e2ecSJeff Kirsher u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 809ec21e2ecSJeff Kirsher u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 810ec21e2ecSJeff Kirsher u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 811ec21e2ecSJeff Kirsher u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 812ec21e2ecSJeff Kirsher u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 813ec21e2ecSJeff Kirsher u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 814ec21e2ecSJeff Kirsher u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 815ec21e2ecSJeff Kirsher u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 816ec21e2ecSJeff Kirsher u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 817ec21e2ecSJeff Kirsher u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 818ec21e2ecSJeff Kirsher u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 819ec21e2ecSJeff Kirsher u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 820ec21e2ecSJeff Kirsher u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 821ec21e2ecSJeff Kirsher u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 822ec21e2ecSJeff Kirsher u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 823ec21e2ecSJeff Kirsher u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 824ec21e2ecSJeff Kirsher u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 825ec21e2ecSJeff Kirsher u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 826ec21e2ecSJeff Kirsher u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 827ec21e2ecSJeff Kirsher u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 828ec21e2ecSJeff Kirsher u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 829ec21e2ecSJeff Kirsher u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 830ec21e2ecSJeff Kirsher u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 831ec21e2ecSJeff Kirsher u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 832ec21e2ecSJeff Kirsher u8 res20[192]; 833ec21e2ecSJeff Kirsher struct rmon_mib rmon; /* 0x.680-0x.73c */ 834ec21e2ecSJeff Kirsher u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 835ec21e2ecSJeff Kirsher u8 res21[188]; 836ec21e2ecSJeff Kirsher u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 837ec21e2ecSJeff Kirsher u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 838ec21e2ecSJeff Kirsher u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 839ec21e2ecSJeff Kirsher u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 840ec21e2ecSJeff Kirsher u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 841ec21e2ecSJeff Kirsher u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 842ec21e2ecSJeff Kirsher u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 843ec21e2ecSJeff Kirsher u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 844ec21e2ecSJeff Kirsher u8 res22[96]; 845ec21e2ecSJeff Kirsher u32 gaddr0; /* 0x.880 - Group address register 0 */ 846ec21e2ecSJeff Kirsher u32 gaddr1; /* 0x.884 - Group address register 1 */ 847ec21e2ecSJeff Kirsher u32 gaddr2; /* 0x.888 - Group address register 2 */ 848ec21e2ecSJeff Kirsher u32 gaddr3; /* 0x.88c - Group address register 3 */ 849ec21e2ecSJeff Kirsher u32 gaddr4; /* 0x.890 - Group address register 4 */ 850ec21e2ecSJeff Kirsher u32 gaddr5; /* 0x.894 - Group address register 5 */ 851ec21e2ecSJeff Kirsher u32 gaddr6; /* 0x.898 - Group address register 6 */ 852ec21e2ecSJeff Kirsher u32 gaddr7; /* 0x.89c - Group address register 7 */ 853ec21e2ecSJeff Kirsher u8 res23a[352]; 854ec21e2ecSJeff Kirsher u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 855ec21e2ecSJeff Kirsher u8 res23b[252]; 856ec21e2ecSJeff Kirsher u8 res23c[248]; 857ec21e2ecSJeff Kirsher u32 attr; /* 0x.bf8 - Attributes Register */ 858ec21e2ecSJeff Kirsher u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 85945b679c9SMatei Pavaluca u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */ 86045b679c9SMatei Pavaluca u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */ 86145b679c9SMatei Pavaluca u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */ 86245b679c9SMatei Pavaluca u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */ 86345b679c9SMatei Pavaluca u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */ 86445b679c9SMatei Pavaluca u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */ 86545b679c9SMatei Pavaluca u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */ 86645b679c9SMatei Pavaluca u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */ 86745b679c9SMatei Pavaluca u8 res24[36]; 86845b679c9SMatei Pavaluca u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */ 86945b679c9SMatei Pavaluca u8 res24a[4]; 87045b679c9SMatei Pavaluca u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */ 87145b679c9SMatei Pavaluca u8 res24b[4]; 87245b679c9SMatei Pavaluca u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */ 87345b679c9SMatei Pavaluca u8 res24c[4]; 87445b679c9SMatei Pavaluca u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */ 87545b679c9SMatei Pavaluca u8 res24d[4]; 87645b679c9SMatei Pavaluca u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */ 87745b679c9SMatei Pavaluca u8 res24e[4]; 87845b679c9SMatei Pavaluca u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */ 87945b679c9SMatei Pavaluca u8 res24f[4]; 88045b679c9SMatei Pavaluca u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */ 88145b679c9SMatei Pavaluca u8 res24g[4]; 88245b679c9SMatei Pavaluca u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */ 88345b679c9SMatei Pavaluca u8 res24h[4]; 88445b679c9SMatei Pavaluca u8 res24x[556]; 885ec21e2ecSJeff Kirsher u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 886ec21e2ecSJeff Kirsher u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 887ec21e2ecSJeff Kirsher u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 888ec21e2ecSJeff Kirsher u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 889ec21e2ecSJeff Kirsher u8 res25[16]; 890ec21e2ecSJeff Kirsher u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 891ec21e2ecSJeff Kirsher u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 892ec21e2ecSJeff Kirsher u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 893ec21e2ecSJeff Kirsher u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 894ec21e2ecSJeff Kirsher u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 895ec21e2ecSJeff Kirsher u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 896ec21e2ecSJeff Kirsher u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 897ec21e2ecSJeff Kirsher u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 898ec21e2ecSJeff Kirsher u8 res26[32]; 899ec21e2ecSJeff Kirsher u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 900ec21e2ecSJeff Kirsher u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 901ec21e2ecSJeff Kirsher u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 902ec21e2ecSJeff Kirsher u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 903ec21e2ecSJeff Kirsher u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 904ec21e2ecSJeff Kirsher u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 905ec21e2ecSJeff Kirsher u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 906ec21e2ecSJeff Kirsher u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 907ec21e2ecSJeff Kirsher u8 res27[208]; 908ec21e2ecSJeff Kirsher }; 909ec21e2ecSJeff Kirsher 910ec21e2ecSJeff Kirsher /* Flags related to gianfar device features */ 911ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 912ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 913ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 914ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 915ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 916ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 917ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 918ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 919ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 920ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 921ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 9223e905b80SClaudiu Manoil #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000 9237bff47daSHamish Martin #define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000 924ec21e2ecSJeff Kirsher 925ec21e2ecSJeff Kirsher #if (MAXGROUPS == 2) 926ec21e2ecSJeff Kirsher #define DEFAULT_MAPPING 0xAA 927ec21e2ecSJeff Kirsher #else 928ec21e2ecSJeff Kirsher #define DEFAULT_MAPPING 0xFF 929ec21e2ecSJeff Kirsher #endif 930ec21e2ecSJeff Kirsher 93120862788SClaudiu Manoil #define ISRG_RR0 0x80000000 93220862788SClaudiu Manoil #define ISRG_TR0 0x00800000 933ec21e2ecSJeff Kirsher 934ec21e2ecSJeff Kirsher /* The same driver can operate in two modes */ 935ec21e2ecSJeff Kirsher /* SQ_SG_MODE: Single Queue Single Group Mode 936ec21e2ecSJeff Kirsher * (Backward compatible mode) 937ec21e2ecSJeff Kirsher * MQ_MG_MODE: Multi Queue Multi Group mode 938ec21e2ecSJeff Kirsher */ 939ec21e2ecSJeff Kirsher enum { 940ec21e2ecSJeff Kirsher SQ_SG_MODE = 0, 941ec21e2ecSJeff Kirsher MQ_MG_MODE 942ec21e2ecSJeff Kirsher }; 943ec21e2ecSJeff Kirsher 94471ff9e3dSClaudiu Manoil /* GFAR_SQ_POLLING: Single Queue NAPI polling mode 94571ff9e3dSClaudiu Manoil * The driver supports a single pair of RX/Tx queues 94671ff9e3dSClaudiu Manoil * per interrupt group (Rx/Tx int line). MQ_MG mode 94771ff9e3dSClaudiu Manoil * devices have 2 interrupt groups, so the device will 94871ff9e3dSClaudiu Manoil * have a total of 2 Tx and 2 Rx queues in this case. 94971ff9e3dSClaudiu Manoil * GFAR_MQ_POLLING: Multi Queue NAPI polling mode 95071ff9e3dSClaudiu Manoil * The driver supports all the 8 Rx and Tx HW queues 95171ff9e3dSClaudiu Manoil * each queue mapped by the Device Tree to one of 95271ff9e3dSClaudiu Manoil * the 2 interrupt groups. This mode implies significant 95371ff9e3dSClaudiu Manoil * processing overhead (CPU and controller level). 95471ff9e3dSClaudiu Manoil */ 95571ff9e3dSClaudiu Manoil enum gfar_poll_mode { 95671ff9e3dSClaudiu Manoil GFAR_SQ_POLLING = 0, 95771ff9e3dSClaudiu Manoil GFAR_MQ_POLLING 95871ff9e3dSClaudiu Manoil }; 95971ff9e3dSClaudiu Manoil 960ec21e2ecSJeff Kirsher /* 961ec21e2ecSJeff Kirsher * Per TX queue stats 962ec21e2ecSJeff Kirsher */ 963ec21e2ecSJeff Kirsher struct tx_q_stats { 964ec21e2ecSJeff Kirsher unsigned long tx_packets; 965ec21e2ecSJeff Kirsher unsigned long tx_bytes; 966ec21e2ecSJeff Kirsher }; 967ec21e2ecSJeff Kirsher 968ec21e2ecSJeff Kirsher /** 969ec21e2ecSJeff Kirsher * struct gfar_priv_tx_q - per tx queue structure 970ec21e2ecSJeff Kirsher * @txlock: per queue tx spin lock 971ec21e2ecSJeff Kirsher * @tx_skbuff:skb pointers 972ec21e2ecSJeff Kirsher * @skb_curtx: to be used skb pointer 973ec21e2ecSJeff Kirsher * @skb_dirtytx:the last used skb pointer 974ec21e2ecSJeff Kirsher * @stats: bytes/packets stats 975ec21e2ecSJeff Kirsher * @qindex: index of this queue 976ec21e2ecSJeff Kirsher * @dev: back pointer to the dev structure 977ec21e2ecSJeff Kirsher * @grp: back pointer to the group to which this queue belongs 978ec21e2ecSJeff Kirsher * @tx_bd_base: First tx buffer descriptor 979ec21e2ecSJeff Kirsher * @cur_tx: Next free ring entry 980ec21e2ecSJeff Kirsher * @dirty_tx: First buffer in line to be transmitted 981ec21e2ecSJeff Kirsher * @tx_ring_size: Tx ring size 982ec21e2ecSJeff Kirsher * @num_txbdfree: number of free TxBds 983ec21e2ecSJeff Kirsher * @txcoalescing: enable/disable tx coalescing 984ec21e2ecSJeff Kirsher * @txic: transmit interrupt coalescing value 985ec21e2ecSJeff Kirsher * @txcount: coalescing value if based on tx frame count 986ec21e2ecSJeff Kirsher * @txtime: coalescing value if based on time 987ec21e2ecSJeff Kirsher */ 988ec21e2ecSJeff Kirsher struct gfar_priv_tx_q { 9890cd3fdeaSClaudiu Manoil /* cacheline 1 */ 990ec21e2ecSJeff Kirsher spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 991ec21e2ecSJeff Kirsher struct txbd8 *tx_bd_base; 992ec21e2ecSJeff Kirsher struct txbd8 *cur_tx; 993ec21e2ecSJeff Kirsher unsigned int num_txbdfree; 9940cd3fdeaSClaudiu Manoil unsigned short skb_curtx; 9950cd3fdeaSClaudiu Manoil unsigned short tx_ring_size; 9960cd3fdeaSClaudiu Manoil struct tx_q_stats stats; 9970cd3fdeaSClaudiu Manoil struct gfar_priv_grp *grp; 9980cd3fdeaSClaudiu Manoil /* cacheline 2 */ 9990cd3fdeaSClaudiu Manoil struct net_device *dev; 10000cd3fdeaSClaudiu Manoil struct sk_buff **tx_skbuff; 10010cd3fdeaSClaudiu Manoil struct txbd8 *dirty_tx; 10020cd3fdeaSClaudiu Manoil unsigned short skb_dirtytx; 10030cd3fdeaSClaudiu Manoil unsigned short qindex; 1004ec21e2ecSJeff Kirsher /* Configuration info for the coalescing features */ 10050cd3fdeaSClaudiu Manoil unsigned int txcoalescing; 1006ec21e2ecSJeff Kirsher unsigned long txic; 10070cd3fdeaSClaudiu Manoil dma_addr_t tx_bd_dma_base; 1008ec21e2ecSJeff Kirsher }; 1009ec21e2ecSJeff Kirsher 1010ec21e2ecSJeff Kirsher /* 1011ec21e2ecSJeff Kirsher * Per RX queue stats 1012ec21e2ecSJeff Kirsher */ 1013ec21e2ecSJeff Kirsher struct rx_q_stats { 1014ec21e2ecSJeff Kirsher unsigned long rx_packets; 1015ec21e2ecSJeff Kirsher unsigned long rx_bytes; 1016ec21e2ecSJeff Kirsher unsigned long rx_dropped; 1017ec21e2ecSJeff Kirsher }; 1018ec21e2ecSJeff Kirsher 101975354148SClaudiu Manoil struct gfar_rx_buff { 102075354148SClaudiu Manoil dma_addr_t dma; 102175354148SClaudiu Manoil struct page *page; 102275354148SClaudiu Manoil unsigned int page_offset; 102375354148SClaudiu Manoil }; 102475354148SClaudiu Manoil 1025ec21e2ecSJeff Kirsher /** 1026ec21e2ecSJeff Kirsher * struct gfar_priv_rx_q - per rx queue structure 102775354148SClaudiu Manoil * @rx_buff: Array of buffer info metadata structs 1028ec21e2ecSJeff Kirsher * @rx_bd_base: First rx buffer descriptor 102976f31e8bSClaudiu Manoil * @next_to_use: index of the next buffer to be alloc'd 103076f31e8bSClaudiu Manoil * @next_to_clean: index of the next buffer to be cleaned 1031ec21e2ecSJeff Kirsher * @qindex: index of this queue 1032f23223f1SClaudiu Manoil * @ndev: back pointer to net_device 1033ec21e2ecSJeff Kirsher * @rx_ring_size: Rx ring size 1034ec21e2ecSJeff Kirsher * @rxcoalescing: enable/disable rx-coalescing 1035ec21e2ecSJeff Kirsher * @rxic: receive interrupt coalescing vlaue 1036ec21e2ecSJeff Kirsher */ 1037ec21e2ecSJeff Kirsher 1038ec21e2ecSJeff Kirsher struct gfar_priv_rx_q { 103975354148SClaudiu Manoil struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES); 1040ec21e2ecSJeff Kirsher struct rxbd8 *rx_bd_base; 1041f23223f1SClaudiu Manoil struct net_device *ndev; 104275354148SClaudiu Manoil struct device *dev; 104376f31e8bSClaudiu Manoil u16 rx_ring_size; 1044ec21e2ecSJeff Kirsher u16 qindex; 104575354148SClaudiu Manoil struct gfar_priv_grp *grp; 104676f31e8bSClaudiu Manoil u16 next_to_clean; 104776f31e8bSClaudiu Manoil u16 next_to_use; 104875354148SClaudiu Manoil u16 next_to_alloc; 104975354148SClaudiu Manoil struct sk_buff *skb; 105076f31e8bSClaudiu Manoil struct rx_q_stats stats; 105176f31e8bSClaudiu Manoil u32 __iomem *rfbptr; 1052ec21e2ecSJeff Kirsher unsigned char rxcoalescing; 1053ec21e2ecSJeff Kirsher unsigned long rxic; 105476f31e8bSClaudiu Manoil dma_addr_t rx_bd_dma_base; 1055ec21e2ecSJeff Kirsher }; 1056ec21e2ecSJeff Kirsher 1057ee873fdaSClaudiu Manoil enum gfar_irqinfo_id { 1058ee873fdaSClaudiu Manoil GFAR_TX = 0, 1059ee873fdaSClaudiu Manoil GFAR_RX = 1, 1060ee873fdaSClaudiu Manoil GFAR_ER = 2, 1061ee873fdaSClaudiu Manoil GFAR_NUM_IRQS = 3 1062ee873fdaSClaudiu Manoil }; 1063ee873fdaSClaudiu Manoil 1064ee873fdaSClaudiu Manoil struct gfar_irqinfo { 1065ee873fdaSClaudiu Manoil unsigned int irq; 1066ee873fdaSClaudiu Manoil char name[GFAR_INT_NAME_MAX]; 1067ee873fdaSClaudiu Manoil }; 1068ee873fdaSClaudiu Manoil 1069ec21e2ecSJeff Kirsher /** 1070ec21e2ecSJeff Kirsher * struct gfar_priv_grp - per group structure 1071ec21e2ecSJeff Kirsher * @napi: the napi poll function 1072ec21e2ecSJeff Kirsher * @priv: back pointer to the priv structure 1073ec21e2ecSJeff Kirsher * @regs: the ioremapped register space for this group 1074ee873fdaSClaudiu Manoil * @irqinfo: TX/RX/ER irq data for this group 1075ec21e2ecSJeff Kirsher */ 1076ec21e2ecSJeff Kirsher 1077ec21e2ecSJeff Kirsher struct gfar_priv_grp { 107871ff9e3dSClaudiu Manoil spinlock_t grplock __aligned(SMP_CACHE_BYTES); 1079aeb12c5eSClaudiu Manoil struct napi_struct napi_rx; 1080aeb12c5eSClaudiu Manoil struct napi_struct napi_tx; 1081ec21e2ecSJeff Kirsher struct gfar __iomem *regs; 108271ff9e3dSClaudiu Manoil struct gfar_priv_tx_q *tx_queue; 108371ff9e3dSClaudiu Manoil struct gfar_priv_rx_q *rx_queue; 1084ec21e2ecSJeff Kirsher unsigned int tstat; 108571ff9e3dSClaudiu Manoil unsigned int rstat; 108671ff9e3dSClaudiu Manoil 108771ff9e3dSClaudiu Manoil struct gfar_private *priv; 1088ee873fdaSClaudiu Manoil unsigned long num_tx_queues; 1089ee873fdaSClaudiu Manoil unsigned long tx_bit_map; 109071ff9e3dSClaudiu Manoil unsigned long num_rx_queues; 109171ff9e3dSClaudiu Manoil unsigned long rx_bit_map; 1092ec21e2ecSJeff Kirsher 1093ee873fdaSClaudiu Manoil struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1094ec21e2ecSJeff Kirsher }; 1095ec21e2ecSJeff Kirsher 1096ee873fdaSClaudiu Manoil #define gfar_irq(grp, ID) \ 1097ee873fdaSClaudiu Manoil ((grp)->irqinfo[GFAR_##ID]) 1098ee873fdaSClaudiu Manoil 1099ec21e2ecSJeff Kirsher enum gfar_errata { 1100ec21e2ecSJeff Kirsher GFAR_ERRATA_74 = 0x01, 1101ec21e2ecSJeff Kirsher GFAR_ERRATA_76 = 0x02, 1102ec21e2ecSJeff Kirsher GFAR_ERRATA_A002 = 0x04, 1103ec21e2ecSJeff Kirsher GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1104ec21e2ecSJeff Kirsher }; 1105ec21e2ecSJeff Kirsher 11060851133bSClaudiu Manoil enum gfar_dev_state { 11070851133bSClaudiu Manoil GFAR_DOWN = 1, 11080851133bSClaudiu Manoil GFAR_RESETTING 11090851133bSClaudiu Manoil }; 11100851133bSClaudiu Manoil 1111ec21e2ecSJeff Kirsher /* Struct stolen almost completely (and shamelessly) from the FCC enet source 1112ec21e2ecSJeff Kirsher * (Ok, that's not so true anymore, but there is a family resemblance) 1113ec21e2ecSJeff Kirsher * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1114ec21e2ecSJeff Kirsher * and tx_bd_base always point to the currently available buffer. 1115ec21e2ecSJeff Kirsher * The dirty_tx tracks the current buffer that is being sent by the 1116ec21e2ecSJeff Kirsher * controller. The cur_tx and dirty_tx are equal under both completely 1117ec21e2ecSJeff Kirsher * empty and completely full conditions. The empty/ready indicator in 1118ec21e2ecSJeff Kirsher * the buffer descriptor determines the actual condition. 1119ec21e2ecSJeff Kirsher */ 1120ec21e2ecSJeff Kirsher struct gfar_private { 1121b597d20dSClaudiu Manoil struct device *dev; 1122b597d20dSClaudiu Manoil struct net_device *ndev; 1123b597d20dSClaudiu Manoil enum gfar_errata errata; 1124b597d20dSClaudiu Manoil 1125ba779711SClaudiu Manoil u16 uses_rxfcb; 1126b597d20dSClaudiu Manoil u16 padding; 112771ff9e3dSClaudiu Manoil u32 device_flags; 1128b597d20dSClaudiu Manoil 1129b597d20dSClaudiu Manoil /* HW time stamping enabled flag */ 1130b597d20dSClaudiu Manoil int hwts_rx_en; 1131b597d20dSClaudiu Manoil int hwts_tx_en; 1132b597d20dSClaudiu Manoil 1133b597d20dSClaudiu Manoil struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1134b597d20dSClaudiu Manoil struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1135b597d20dSClaudiu Manoil struct gfar_priv_grp gfargrp[MAXGROUPS]; 1136b597d20dSClaudiu Manoil 11370851133bSClaudiu Manoil unsigned long state; 1138b597d20dSClaudiu Manoil 113971ff9e3dSClaudiu Manoil unsigned short mode; 114071ff9e3dSClaudiu Manoil unsigned short poll_mode; 1141b597d20dSClaudiu Manoil unsigned int num_tx_queues; 114271ff9e3dSClaudiu Manoil unsigned int num_rx_queues; 1143b597d20dSClaudiu Manoil unsigned int num_grps; 114445b679c9SMatei Pavaluca int tx_actual_en; 1145b597d20dSClaudiu Manoil 1146b597d20dSClaudiu Manoil /* Network Statistics */ 1147b597d20dSClaudiu Manoil struct gfar_extra_stats extra_stats; 1148b597d20dSClaudiu Manoil 1149b597d20dSClaudiu Manoil /* PHY stuff */ 1150b597d20dSClaudiu Manoil phy_interface_t interface; 1151b597d20dSClaudiu Manoil struct device_node *phy_node; 1152b597d20dSClaudiu Manoil struct device_node *tbi_node; 1153b597d20dSClaudiu Manoil struct mii_bus *mii_bus; 1154b597d20dSClaudiu Manoil int oldspeed; 1155b597d20dSClaudiu Manoil int oldduplex; 1156b597d20dSClaudiu Manoil int oldlink; 1157b597d20dSClaudiu Manoil 1158b597d20dSClaudiu Manoil uint32_t msg_enable; 1159b597d20dSClaudiu Manoil 1160b597d20dSClaudiu Manoil struct work_struct reset_task; 1161b597d20dSClaudiu Manoil 1162b597d20dSClaudiu Manoil struct platform_device *ofdev; 1163b597d20dSClaudiu Manoil unsigned char 1164b597d20dSClaudiu Manoil extended_hash:1, 1165b597d20dSClaudiu Manoil bd_stash_en:1, 1166b597d20dSClaudiu Manoil rx_filer_enable:1, 1167b597d20dSClaudiu Manoil /* Enable priorty based Tx scheduling in Hw */ 116823402bddSClaudiu Manoil prio_sched_en:1, 116923402bddSClaudiu Manoil /* Flow control flags */ 117023402bddSClaudiu Manoil pause_aneg_en:1, 117123402bddSClaudiu Manoil tx_pause_en:1, 117223402bddSClaudiu Manoil rx_pause_en:1; 1173ec21e2ecSJeff Kirsher 1174ec21e2ecSJeff Kirsher /* The total tx and rx ring size for the enabled queues */ 1175ec21e2ecSJeff Kirsher unsigned int total_tx_ring_size; 1176ec21e2ecSJeff Kirsher unsigned int total_rx_ring_size; 1177ec21e2ecSJeff Kirsher 117820862788SClaudiu Manoil u32 rqueue; 117920862788SClaudiu Manoil u32 tqueue; 118020862788SClaudiu Manoil 1181ec21e2ecSJeff Kirsher /* RX per device parameters */ 1182ec21e2ecSJeff Kirsher unsigned int rx_stash_size; 1183ec21e2ecSJeff Kirsher unsigned int rx_stash_index; 1184ec21e2ecSJeff Kirsher 1185ec21e2ecSJeff Kirsher u32 cur_filer_idx; 1186ec21e2ecSJeff Kirsher 1187ec21e2ecSJeff Kirsher /* RX queue filer rule set*/ 1188ec21e2ecSJeff Kirsher struct ethtool_rx_list rx_list; 1189ec21e2ecSJeff Kirsher struct mutex rx_queue_access; 1190ec21e2ecSJeff Kirsher 1191ec21e2ecSJeff Kirsher /* Hash registers and their width */ 1192ec21e2ecSJeff Kirsher u32 __iomem *hash_regs[16]; 1193ec21e2ecSJeff Kirsher int hash_width; 1194ec21e2ecSJeff Kirsher 11953e905b80SClaudiu Manoil /* wake-on-lan settings */ 11963e905b80SClaudiu Manoil u16 wol_opts; 11973e905b80SClaudiu Manoil u16 wol_supported; 11983e905b80SClaudiu Manoil 1199ec21e2ecSJeff Kirsher /*Filer table*/ 1200ec21e2ecSJeff Kirsher unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1201ec21e2ecSJeff Kirsher unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1202ec21e2ecSJeff Kirsher }; 1203ec21e2ecSJeff Kirsher 1204ec21e2ecSJeff Kirsher 1205ec21e2ecSJeff Kirsher static inline int gfar_has_errata(struct gfar_private *priv, 1206ec21e2ecSJeff Kirsher enum gfar_errata err) 1207ec21e2ecSJeff Kirsher { 1208ec21e2ecSJeff Kirsher return priv->errata & err; 1209ec21e2ecSJeff Kirsher } 1210ec21e2ecSJeff Kirsher 1211fb017472SKim Phillips static inline u32 gfar_read(unsigned __iomem *addr) 1212ec21e2ecSJeff Kirsher { 1213ec21e2ecSJeff Kirsher u32 val; 1214fb017472SKim Phillips val = ioread32be(addr); 1215ec21e2ecSJeff Kirsher return val; 1216ec21e2ecSJeff Kirsher } 1217ec21e2ecSJeff Kirsher 1218fb017472SKim Phillips static inline void gfar_write(unsigned __iomem *addr, u32 val) 1219ec21e2ecSJeff Kirsher { 1220fb017472SKim Phillips iowrite32be(val, addr); 1221ec21e2ecSJeff Kirsher } 1222ec21e2ecSJeff Kirsher 1223ec21e2ecSJeff Kirsher static inline void gfar_write_filer(struct gfar_private *priv, 1224ec21e2ecSJeff Kirsher unsigned int far, unsigned int fcr, unsigned int fpr) 1225ec21e2ecSJeff Kirsher { 1226ec21e2ecSJeff Kirsher struct gfar __iomem *regs = priv->gfargrp[0].regs; 1227ec21e2ecSJeff Kirsher 1228ec21e2ecSJeff Kirsher gfar_write(®s->rqfar, far); 1229ec21e2ecSJeff Kirsher gfar_write(®s->rqfcr, fcr); 1230ec21e2ecSJeff Kirsher gfar_write(®s->rqfpr, fpr); 1231ec21e2ecSJeff Kirsher } 1232ec21e2ecSJeff Kirsher 1233ec21e2ecSJeff Kirsher static inline void gfar_read_filer(struct gfar_private *priv, 1234ec21e2ecSJeff Kirsher unsigned int far, unsigned int *fcr, unsigned int *fpr) 1235ec21e2ecSJeff Kirsher { 1236ec21e2ecSJeff Kirsher struct gfar __iomem *regs = priv->gfargrp[0].regs; 1237ec21e2ecSJeff Kirsher 1238ec21e2ecSJeff Kirsher gfar_write(®s->rqfar, far); 1239ec21e2ecSJeff Kirsher *fcr = gfar_read(®s->rqfcr); 1240ec21e2ecSJeff Kirsher *fpr = gfar_read(®s->rqfpr); 1241ec21e2ecSJeff Kirsher } 1242ec21e2ecSJeff Kirsher 124320862788SClaudiu Manoil static inline void gfar_write_isrg(struct gfar_private *priv) 124420862788SClaudiu Manoil { 124520862788SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 124620862788SClaudiu Manoil u32 __iomem *baddr = ®s->isrg0; 124720862788SClaudiu Manoil u32 isrg = 0; 124820862788SClaudiu Manoil int grp_idx, i; 124920862788SClaudiu Manoil 125020862788SClaudiu Manoil for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 125120862788SClaudiu Manoil struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; 125220862788SClaudiu Manoil 125320862788SClaudiu Manoil for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 125420862788SClaudiu Manoil isrg |= (ISRG_RR0 >> i); 125520862788SClaudiu Manoil } 125620862788SClaudiu Manoil 125720862788SClaudiu Manoil for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 125820862788SClaudiu Manoil isrg |= (ISRG_TR0 >> i); 125920862788SClaudiu Manoil } 126020862788SClaudiu Manoil 126120862788SClaudiu Manoil gfar_write(baddr, isrg); 126220862788SClaudiu Manoil 126320862788SClaudiu Manoil baddr++; 126420862788SClaudiu Manoil isrg = 0; 126520862788SClaudiu Manoil } 126620862788SClaudiu Manoil } 126720862788SClaudiu Manoil 1268a4feee89SClaudiu Manoil static inline int gfar_is_dma_stopped(struct gfar_private *priv) 1269a4feee89SClaudiu Manoil { 1270a4feee89SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 1271a4feee89SClaudiu Manoil 1272a4feee89SClaudiu Manoil return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == 1273a4feee89SClaudiu Manoil (IEVENT_GRSC | IEVENT_GTSC)); 1274a4feee89SClaudiu Manoil } 1275a4feee89SClaudiu Manoil 1276a4feee89SClaudiu Manoil static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) 1277a4feee89SClaudiu Manoil { 1278a4feee89SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 1279a4feee89SClaudiu Manoil 1280a4feee89SClaudiu Manoil return gfar_read(®s->ievent) & IEVENT_GRSC; 1281a4feee89SClaudiu Manoil } 1282a4feee89SClaudiu Manoil 1283d55398baSClaudiu Manoil static inline void gfar_wmb(void) 1284d55398baSClaudiu Manoil { 1285d55398baSClaudiu Manoil #if defined(CONFIG_PPC) 1286d55398baSClaudiu Manoil /* The powerpc-specific eieio() is used, as wmb() has too strong 1287d55398baSClaudiu Manoil * semantics (it requires synchronization between cacheable and 1288d55398baSClaudiu Manoil * uncacheable mappings, which eieio() doesn't provide and which we 1289d55398baSClaudiu Manoil * don't need), thus requiring a more expensive sync instruction. At 1290d55398baSClaudiu Manoil * some point, the set of architecture-independent barrier functions 1291d55398baSClaudiu Manoil * should be expanded to include weaker barriers. 1292d55398baSClaudiu Manoil */ 1293d55398baSClaudiu Manoil eieio(); 1294d55398baSClaudiu Manoil #else 1295d55398baSClaudiu Manoil wmb(); /* order write acesses for BD (or FCB) fields */ 1296d55398baSClaudiu Manoil #endif 1297d55398baSClaudiu Manoil } 1298d55398baSClaudiu Manoil 1299a7312d58SClaudiu Manoil static inline void gfar_clear_txbd_status(struct txbd8 *bdp) 1300a7312d58SClaudiu Manoil { 1301a7312d58SClaudiu Manoil u32 lstatus = be32_to_cpu(bdp->lstatus); 1302a7312d58SClaudiu Manoil 1303a7312d58SClaudiu Manoil lstatus &= BD_LFLAG(TXBD_WRAP); 1304a7312d58SClaudiu Manoil bdp->lstatus = cpu_to_be32(lstatus); 1305a7312d58SClaudiu Manoil } 1306a7312d58SClaudiu Manoil 130776f31e8bSClaudiu Manoil static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq) 130876f31e8bSClaudiu Manoil { 130976f31e8bSClaudiu Manoil if (rxq->next_to_clean > rxq->next_to_use) 131076f31e8bSClaudiu Manoil return rxq->next_to_clean - rxq->next_to_use - 1; 131176f31e8bSClaudiu Manoil 131276f31e8bSClaudiu Manoil return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1; 131376f31e8bSClaudiu Manoil } 131476f31e8bSClaudiu Manoil 1315b4b67f26SScott Wood static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq) 131676f31e8bSClaudiu Manoil { 1317b4b67f26SScott Wood struct rxbd8 *bdp; 1318b4b67f26SScott Wood u32 bdp_dma; 131976f31e8bSClaudiu Manoil int i; 132076f31e8bSClaudiu Manoil 132176f31e8bSClaudiu Manoil i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1; 1322b4b67f26SScott Wood bdp = &rxq->rx_bd_base[i]; 1323b4b67f26SScott Wood bdp_dma = lower_32_bits(rxq->rx_bd_dma_base); 1324b4b67f26SScott Wood bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base; 132576f31e8bSClaudiu Manoil 1326b4b67f26SScott Wood return bdp_dma; 132776f31e8bSClaudiu Manoil } 132876f31e8bSClaudiu Manoil 1329bddb2d9aSJoe Perches irqreturn_t gfar_receive(int irq, void *dev_id); 1330bddb2d9aSJoe Perches int startup_gfar(struct net_device *dev); 1331bddb2d9aSJoe Perches void stop_gfar(struct net_device *dev); 13320851133bSClaudiu Manoil void reset_gfar(struct net_device *dev); 13330851133bSClaudiu Manoil void gfar_mac_reset(struct gfar_private *priv); 1334c10650b6SClaudiu Manoil void gfar_halt(struct gfar_private *priv); 1335c10650b6SClaudiu Manoil void gfar_start(struct gfar_private *priv); 1336bddb2d9aSJoe Perches void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, 1337bddb2d9aSJoe Perches u32 regnum, u32 read); 1338bddb2d9aSJoe Perches void gfar_configure_coalescing_all(struct gfar_private *priv); 1339c8f44affSMichał Mirosław int gfar_set_features(struct net_device *dev, netdev_features_t features); 1340ec21e2ecSJeff Kirsher 1341ec21e2ecSJeff Kirsher extern const struct ethtool_ops gfar_ethtool_ops; 1342ec21e2ecSJeff Kirsher 1343ec21e2ecSJeff Kirsher #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1344ec21e2ecSJeff Kirsher 1345ec21e2ecSJeff Kirsher #define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1346ec21e2ecSJeff Kirsher #define RQFCR_PID_L4P_MASK 0xFFFFFF00 1347ec21e2ecSJeff Kirsher #define RQFCR_PID_VID_MASK 0xFFFFF000 1348ec21e2ecSJeff Kirsher #define RQFCR_PID_PORT_MASK 0xFFFF0000 1349ec21e2ecSJeff Kirsher #define RQFCR_PID_MAC_MASK 0xFF000000 1350ec21e2ecSJeff Kirsher 1351ec21e2ecSJeff Kirsher struct gfar_mask_entry { 1352ec21e2ecSJeff Kirsher unsigned int mask; /* The mask value which is valid form start to end */ 1353ec21e2ecSJeff Kirsher unsigned int start; 1354ec21e2ecSJeff Kirsher unsigned int end; 1355ec21e2ecSJeff Kirsher unsigned int block; /* Same block values indicate depended entries */ 1356ec21e2ecSJeff Kirsher }; 1357ec21e2ecSJeff Kirsher 1358ec21e2ecSJeff Kirsher /* Represents a receive filer table entry */ 1359ec21e2ecSJeff Kirsher struct gfar_filer_entry { 1360ec21e2ecSJeff Kirsher u32 ctrl; 1361ec21e2ecSJeff Kirsher u32 prop; 1362ec21e2ecSJeff Kirsher }; 1363ec21e2ecSJeff Kirsher 1364ec21e2ecSJeff Kirsher 1365ec21e2ecSJeff Kirsher /* The 20 additional entries are a shadow for one extra element */ 1366ec21e2ecSJeff Kirsher struct filer_table { 1367ec21e2ecSJeff Kirsher u32 index; 1368ec21e2ecSJeff Kirsher struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1369ec21e2ecSJeff Kirsher }; 1370ec21e2ecSJeff Kirsher 1371ec21e2ecSJeff Kirsher #endif /* __GIANFAR_H */ 1372