12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ec21e2ecSJeff Kirsher /* 33396c782SPaul Gortmaker * drivers/net/ethernet/freescale/gianfar.h 4ec21e2ecSJeff Kirsher * 5ec21e2ecSJeff Kirsher * Gianfar Ethernet Driver 6ec21e2ecSJeff Kirsher * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 7ec21e2ecSJeff Kirsher * Based on 8260_io/fcc_enet.c 8ec21e2ecSJeff Kirsher * 9ec21e2ecSJeff Kirsher * Author: Andy Fleming 10ec21e2ecSJeff Kirsher * Maintainer: Kumar Gala 11ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 12ec21e2ecSJeff Kirsher * 1320862788SClaudiu Manoil * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 14ec21e2ecSJeff Kirsher * 15ec21e2ecSJeff Kirsher * Still left to do: 16ec21e2ecSJeff Kirsher * -Add support for module parameters 17ec21e2ecSJeff Kirsher * -Add patch for ethtool phys id 18ec21e2ecSJeff Kirsher */ 19ec21e2ecSJeff Kirsher #ifndef __GIANFAR_H 20ec21e2ecSJeff Kirsher #define __GIANFAR_H 21ec21e2ecSJeff Kirsher 22ec21e2ecSJeff Kirsher #include <linux/kernel.h> 23ec21e2ecSJeff Kirsher #include <linux/sched.h> 24ec21e2ecSJeff Kirsher #include <linux/string.h> 25ec21e2ecSJeff Kirsher #include <linux/errno.h> 26ec21e2ecSJeff Kirsher #include <linux/slab.h> 27ec21e2ecSJeff Kirsher #include <linux/interrupt.h> 28ec21e2ecSJeff Kirsher #include <linux/delay.h> 29ec21e2ecSJeff Kirsher #include <linux/netdevice.h> 30ec21e2ecSJeff Kirsher #include <linux/etherdevice.h> 31ec21e2ecSJeff Kirsher #include <linux/skbuff.h> 32ec21e2ecSJeff Kirsher #include <linux/spinlock.h> 33ec21e2ecSJeff Kirsher #include <linux/mm.h> 34ec21e2ecSJeff Kirsher #include <linux/mii.h> 35ec21e2ecSJeff Kirsher #include <linux/phy.h> 36ec21e2ecSJeff Kirsher 37ec21e2ecSJeff Kirsher #include <asm/io.h> 38ec21e2ecSJeff Kirsher #include <asm/irq.h> 397c0f6ba6SLinus Torvalds #include <linux/uaccess.h> 40ec21e2ecSJeff Kirsher #include <linux/module.h> 41ec21e2ecSJeff Kirsher #include <linux/crc32.h> 42ec21e2ecSJeff Kirsher #include <linux/workqueue.h> 43ec21e2ecSJeff Kirsher #include <linux/ethtool.h> 44ec21e2ecSJeff Kirsher 45ec21e2ecSJeff Kirsher struct ethtool_flow_spec_container { 46ec21e2ecSJeff Kirsher struct ethtool_rx_flow_spec fs; 47ec21e2ecSJeff Kirsher struct list_head list; 48ec21e2ecSJeff Kirsher }; 49ec21e2ecSJeff Kirsher 50ec21e2ecSJeff Kirsher struct ethtool_rx_list { 51ec21e2ecSJeff Kirsher struct list_head list; 52ec21e2ecSJeff Kirsher unsigned int count; 53ec21e2ecSJeff Kirsher }; 54ec21e2ecSJeff Kirsher 55ec21e2ecSJeff Kirsher /* The maximum number of packets to be handled in one call of gfar_poll */ 56ec21e2ecSJeff Kirsher #define GFAR_DEV_WEIGHT 64 57ec21e2ecSJeff Kirsher 58ec21e2ecSJeff Kirsher /* Length for FCB */ 59ec21e2ecSJeff Kirsher #define GMAC_FCB_LEN 8 60ec21e2ecSJeff Kirsher 619c4886e5SManfred Rudigier /* Length for TxPAL */ 629c4886e5SManfred Rudigier #define GMAC_TXPAL_LEN 16 639c4886e5SManfred Rudigier 64ec21e2ecSJeff Kirsher /* Default padding amount */ 65ec21e2ecSJeff Kirsher #define DEFAULT_PADDING 2 66ec21e2ecSJeff Kirsher 67ec21e2ecSJeff Kirsher /* Number of bytes to align the rx bufs to */ 68ec21e2ecSJeff Kirsher #define RXBUF_ALIGNMENT 64 69ec21e2ecSJeff Kirsher 70ec21e2ecSJeff Kirsher #define DRV_NAME "gfar-enet" 71ec21e2ecSJeff Kirsher 72ec21e2ecSJeff Kirsher /* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 73ec21e2ecSJeff Kirsher #define MAX_TX_QS 0x8 74ec21e2ecSJeff Kirsher #define MAX_RX_QS 0x8 75ec21e2ecSJeff Kirsher 76ec21e2ecSJeff Kirsher /* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 77ec21e2ecSJeff Kirsher #define MAXGROUPS 0x2 78ec21e2ecSJeff Kirsher 79ec21e2ecSJeff Kirsher /* These need to be powers of 2 for this driver */ 80ec21e2ecSJeff Kirsher #define DEFAULT_TX_RING_SIZE 256 81ec21e2ecSJeff Kirsher #define DEFAULT_RX_RING_SIZE 256 82ec21e2ecSJeff Kirsher 8376f31e8bSClaudiu Manoil #define GFAR_RX_BUFF_ALLOC 16 8476f31e8bSClaudiu Manoil 85ec21e2ecSJeff Kirsher #define GFAR_RX_MAX_RING_SIZE 256 86ec21e2ecSJeff Kirsher #define GFAR_TX_MAX_RING_SIZE 256 87ec21e2ecSJeff Kirsher 8845b679c9SMatei Pavaluca #define FBTHR_SHIFT 24 8945b679c9SMatei Pavaluca #define DEFAULT_RX_LFC_THR 16 9045b679c9SMatei Pavaluca #define DEFAULT_LFC_PTVVAL 4 9145b679c9SMatei Pavaluca 9275354148SClaudiu Manoil #define GFAR_RXB_TRUESIZE 2048 93a9b97286SClaudiu Manoil #define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \ 94a9b97286SClaudiu Manoil + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 95a9b97286SClaudiu Manoil #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64) 96a9b97286SClaudiu Manoil #define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR) 9775354148SClaudiu Manoil 98ec21e2ecSJeff Kirsher #define TX_RING_MOD_MASK(size) (size-1) 99ec21e2ecSJeff Kirsher #define RX_RING_MOD_MASK(size) (size-1) 10075354148SClaudiu Manoil #define GFAR_JUMBO_FRAME_SIZE 9600 101ec21e2ecSJeff Kirsher 102ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_THR 0x100 103ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_STARVE 0x40 104ec21e2ecSJeff Kirsher #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 105ec21e2ecSJeff Kirsher 106ec21e2ecSJeff Kirsher /* The number of Exact Match registers */ 107ec21e2ecSJeff Kirsher #define GFAR_EM_NUM 15 108ec21e2ecSJeff Kirsher 109ec21e2ecSJeff Kirsher /* Latency of interface clock in nanoseconds */ 110ec21e2ecSJeff Kirsher /* Interface clock latency , in this case, means the 111ec21e2ecSJeff Kirsher * time described by a value of 1 in the interrupt 112ec21e2ecSJeff Kirsher * coalescing registers' time fields. Since those fields 113ec21e2ecSJeff Kirsher * refer to the time it takes for 64 clocks to pass, the 114ec21e2ecSJeff Kirsher * latencies are as such: 115ec21e2ecSJeff Kirsher * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 116ec21e2ecSJeff Kirsher * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 117ec21e2ecSJeff Kirsher * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 118ec21e2ecSJeff Kirsher */ 119ec21e2ecSJeff Kirsher #define GFAR_GBIT_TIME 512 120ec21e2ecSJeff Kirsher #define GFAR_100_TIME 2560 121ec21e2ecSJeff Kirsher #define GFAR_10_TIME 25600 122ec21e2ecSJeff Kirsher 123ec21e2ecSJeff Kirsher #define DEFAULT_TX_COALESCE 1 124ec21e2ecSJeff Kirsher #define DEFAULT_TXCOUNT 16 125ec21e2ecSJeff Kirsher #define DEFAULT_TXTIME 21 126ec21e2ecSJeff Kirsher 127ec21e2ecSJeff Kirsher #define DEFAULT_RXTIME 21 128ec21e2ecSJeff Kirsher 129ec21e2ecSJeff Kirsher #define DEFAULT_RX_COALESCE 0 130ec21e2ecSJeff Kirsher #define DEFAULT_RXCOUNT 0 131ec21e2ecSJeff Kirsher 132ec21e2ecSJeff Kirsher /* TBI register addresses */ 133ec21e2ecSJeff Kirsher #define MII_TBICON 0x11 134ec21e2ecSJeff Kirsher 135ec21e2ecSJeff Kirsher /* TBICON register bit fields */ 136ec21e2ecSJeff Kirsher #define TBICON_CLK_SELECT 0x0020 137ec21e2ecSJeff Kirsher 138ec21e2ecSJeff Kirsher /* MAC register bits */ 139ec21e2ecSJeff Kirsher #define MACCFG1_SOFT_RESET 0x80000000 140ec21e2ecSJeff Kirsher #define MACCFG1_RESET_RX_MC 0x00080000 141ec21e2ecSJeff Kirsher #define MACCFG1_RESET_TX_MC 0x00040000 142ec21e2ecSJeff Kirsher #define MACCFG1_RESET_RX_FUN 0x00020000 143ec21e2ecSJeff Kirsher #define MACCFG1_RESET_TX_FUN 0x00010000 144ec21e2ecSJeff Kirsher #define MACCFG1_LOOPBACK 0x00000100 145ec21e2ecSJeff Kirsher #define MACCFG1_RX_FLOW 0x00000020 146ec21e2ecSJeff Kirsher #define MACCFG1_TX_FLOW 0x00000010 147ec21e2ecSJeff Kirsher #define MACCFG1_SYNCD_RX_EN 0x00000008 148ec21e2ecSJeff Kirsher #define MACCFG1_RX_EN 0x00000004 149ec21e2ecSJeff Kirsher #define MACCFG1_SYNCD_TX_EN 0x00000002 150ec21e2ecSJeff Kirsher #define MACCFG1_TX_EN 0x00000001 151ec21e2ecSJeff Kirsher 152ec21e2ecSJeff Kirsher #define MACCFG2_INIT_SETTINGS 0x00007205 153ec21e2ecSJeff Kirsher #define MACCFG2_FULL_DUPLEX 0x00000001 154ec21e2ecSJeff Kirsher #define MACCFG2_IF 0x00000300 155ec21e2ecSJeff Kirsher #define MACCFG2_MII 0x00000100 156ec21e2ecSJeff Kirsher #define MACCFG2_GMII 0x00000200 157ec21e2ecSJeff Kirsher #define MACCFG2_HUGEFRAME 0x00000020 158ec21e2ecSJeff Kirsher #define MACCFG2_LENGTHCHECK 0x00000010 159ec21e2ecSJeff Kirsher #define MACCFG2_MPEN 0x00000008 160ec21e2ecSJeff Kirsher 161ec21e2ecSJeff Kirsher #define ECNTRL_FIFM 0x00008000 162ec21e2ecSJeff Kirsher #define ECNTRL_INIT_SETTINGS 0x00001000 163ec21e2ecSJeff Kirsher #define ECNTRL_TBI_MODE 0x00000020 164ec21e2ecSJeff Kirsher #define ECNTRL_REDUCED_MODE 0x00000010 165ec21e2ecSJeff Kirsher #define ECNTRL_R100 0x00000008 166ec21e2ecSJeff Kirsher #define ECNTRL_REDUCED_MII_MODE 0x00000004 167ec21e2ecSJeff Kirsher #define ECNTRL_SGMII_MODE 0x00000002 168ec21e2ecSJeff Kirsher 169ec21e2ecSJeff Kirsher #define MINFLR_INIT_SETTINGS 0x00000040 170ec21e2ecSJeff Kirsher 171ec21e2ecSJeff Kirsher /* Tqueue control */ 172ec21e2ecSJeff Kirsher #define TQUEUE_EN0 0x00008000 173ec21e2ecSJeff Kirsher #define TQUEUE_EN1 0x00004000 174ec21e2ecSJeff Kirsher #define TQUEUE_EN2 0x00002000 175ec21e2ecSJeff Kirsher #define TQUEUE_EN3 0x00001000 176ec21e2ecSJeff Kirsher #define TQUEUE_EN4 0x00000800 177ec21e2ecSJeff Kirsher #define TQUEUE_EN5 0x00000400 178ec21e2ecSJeff Kirsher #define TQUEUE_EN6 0x00000200 179ec21e2ecSJeff Kirsher #define TQUEUE_EN7 0x00000100 180ec21e2ecSJeff Kirsher #define TQUEUE_EN_ALL 0x0000FF00 181ec21e2ecSJeff Kirsher 182ec21e2ecSJeff Kirsher #define TR03WT_WT0_MASK 0xFF000000 183ec21e2ecSJeff Kirsher #define TR03WT_WT1_MASK 0x00FF0000 184ec21e2ecSJeff Kirsher #define TR03WT_WT2_MASK 0x0000FF00 185ec21e2ecSJeff Kirsher #define TR03WT_WT3_MASK 0x000000FF 186ec21e2ecSJeff Kirsher 187ec21e2ecSJeff Kirsher #define TR47WT_WT4_MASK 0xFF000000 188ec21e2ecSJeff Kirsher #define TR47WT_WT5_MASK 0x00FF0000 189ec21e2ecSJeff Kirsher #define TR47WT_WT6_MASK 0x0000FF00 190ec21e2ecSJeff Kirsher #define TR47WT_WT7_MASK 0x000000FF 191ec21e2ecSJeff Kirsher 192ec21e2ecSJeff Kirsher /* Rqueue control */ 193ec21e2ecSJeff Kirsher #define RQUEUE_EX0 0x00800000 194ec21e2ecSJeff Kirsher #define RQUEUE_EX1 0x00400000 195ec21e2ecSJeff Kirsher #define RQUEUE_EX2 0x00200000 196ec21e2ecSJeff Kirsher #define RQUEUE_EX3 0x00100000 197ec21e2ecSJeff Kirsher #define RQUEUE_EX4 0x00080000 198ec21e2ecSJeff Kirsher #define RQUEUE_EX5 0x00040000 199ec21e2ecSJeff Kirsher #define RQUEUE_EX6 0x00020000 200ec21e2ecSJeff Kirsher #define RQUEUE_EX7 0x00010000 201ec21e2ecSJeff Kirsher #define RQUEUE_EX_ALL 0x00FF0000 202ec21e2ecSJeff Kirsher 203ec21e2ecSJeff Kirsher #define RQUEUE_EN0 0x00000080 204ec21e2ecSJeff Kirsher #define RQUEUE_EN1 0x00000040 205ec21e2ecSJeff Kirsher #define RQUEUE_EN2 0x00000020 206ec21e2ecSJeff Kirsher #define RQUEUE_EN3 0x00000010 207ec21e2ecSJeff Kirsher #define RQUEUE_EN4 0x00000008 208ec21e2ecSJeff Kirsher #define RQUEUE_EN5 0x00000004 209ec21e2ecSJeff Kirsher #define RQUEUE_EN6 0x00000002 210ec21e2ecSJeff Kirsher #define RQUEUE_EN7 0x00000001 211ec21e2ecSJeff Kirsher #define RQUEUE_EN_ALL 0x000000FF 212ec21e2ecSJeff Kirsher 213ec21e2ecSJeff Kirsher /* Init to do tx snooping for buffers and descriptors */ 214ec21e2ecSJeff Kirsher #define DMACTRL_INIT_SETTINGS 0x000000c3 215ec21e2ecSJeff Kirsher #define DMACTRL_GRS 0x00000010 216ec21e2ecSJeff Kirsher #define DMACTRL_GTS 0x00000008 217ec21e2ecSJeff Kirsher 218ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT_ALL 0xFF000000 219ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT 0x80000000 220ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT0 0x80000000 221ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT1 0x40000000 222ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT2 0x20000000 223ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT3 0x10000000 224ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT4 0x08000000 225ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT5 0x04000000 226ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT6 0x02000000 227ec21e2ecSJeff Kirsher #define TSTAT_CLEAR_THALT7 0x01000000 228ec21e2ecSJeff Kirsher 229ec21e2ecSJeff Kirsher /* Interrupt coalescing macros */ 230ec21e2ecSJeff Kirsher #define IC_ICEN 0x80000000 231ec21e2ecSJeff Kirsher #define IC_ICFT_MASK 0x1fe00000 232ec21e2ecSJeff Kirsher #define IC_ICFT_SHIFT 21 233ec21e2ecSJeff Kirsher #define mk_ic_icft(x) \ 234ec21e2ecSJeff Kirsher (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 235ec21e2ecSJeff Kirsher #define IC_ICTT_MASK 0x0000ffff 236ec21e2ecSJeff Kirsher #define mk_ic_ictt(x) (x&IC_ICTT_MASK) 237ec21e2ecSJeff Kirsher 238ec21e2ecSJeff Kirsher #define mk_ic_value(count, time) (IC_ICEN | \ 239ec21e2ecSJeff Kirsher mk_ic_icft(count) | \ 240ec21e2ecSJeff Kirsher mk_ic_ictt(time)) 241ec21e2ecSJeff Kirsher #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 242ec21e2ecSJeff Kirsher IC_ICFT_SHIFT) 243ec21e2ecSJeff Kirsher #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 244ec21e2ecSJeff Kirsher 245ec21e2ecSJeff Kirsher #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 246ec21e2ecSJeff Kirsher #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 247ec21e2ecSJeff Kirsher 248ec21e2ecSJeff Kirsher #define RCTRL_TS_ENABLE 0x01000000 249ec21e2ecSJeff Kirsher #define RCTRL_PAL_MASK 0x001f0000 25045b679c9SMatei Pavaluca #define RCTRL_LFC 0x00004000 251ec21e2ecSJeff Kirsher #define RCTRL_VLEX 0x00002000 252ec21e2ecSJeff Kirsher #define RCTRL_FILREN 0x00001000 253ec21e2ecSJeff Kirsher #define RCTRL_GHTX 0x00000400 254ec21e2ecSJeff Kirsher #define RCTRL_IPCSEN 0x00000200 255ec21e2ecSJeff Kirsher #define RCTRL_TUCSEN 0x00000100 256ec21e2ecSJeff Kirsher #define RCTRL_PRSDEP_MASK 0x000000c0 257ec21e2ecSJeff Kirsher #define RCTRL_PRSDEP_INIT 0x000000c0 258ec21e2ecSJeff Kirsher #define RCTRL_PRSFM 0x00000020 259ec21e2ecSJeff Kirsher #define RCTRL_PROM 0x00000008 260ec21e2ecSJeff Kirsher #define RCTRL_EMEN 0x00000002 261ec21e2ecSJeff Kirsher #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 262ec21e2ecSJeff Kirsher RCTRL_TUCSEN | RCTRL_FILREN) 263ec21e2ecSJeff Kirsher #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 264ec21e2ecSJeff Kirsher RCTRL_PRSDEP_INIT) 265ec21e2ecSJeff Kirsher #define RCTRL_EXTHASH (RCTRL_GHTX) 266ec21e2ecSJeff Kirsher #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 267ec21e2ecSJeff Kirsher #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 268ec21e2ecSJeff Kirsher 269ec21e2ecSJeff Kirsher 270ec21e2ecSJeff Kirsher #define RSTAT_CLEAR_RHALT 0x00800000 2716be5ed3fSClaudiu Manoil #define RSTAT_CLEAR_RXF0 0x00000080 2726be5ed3fSClaudiu Manoil #define RSTAT_RXF_MASK 0x000000ff 273ec21e2ecSJeff Kirsher 274ec21e2ecSJeff Kirsher #define TCTRL_IPCSEN 0x00004000 275ec21e2ecSJeff Kirsher #define TCTRL_TUCSEN 0x00002000 276ec21e2ecSJeff Kirsher #define TCTRL_VLINS 0x00001000 277ec21e2ecSJeff Kirsher #define TCTRL_THDF 0x00000800 278ec21e2ecSJeff Kirsher #define TCTRL_RFCPAUSE 0x00000010 279ec21e2ecSJeff Kirsher #define TCTRL_TFCPAUSE 0x00000008 280ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_MASK 0x00000006 281ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_INIT 0x00000000 282b98b8babSClaudiu Manoil /* priority scheduling */ 283ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_PRIO 0x00000002 284b98b8babSClaudiu Manoil /* weighted round-robin scheduling (WRRS) */ 285ec21e2ecSJeff Kirsher #define TCTRL_TXSCHED_WRRS 0x00000004 286b98b8babSClaudiu Manoil /* default WRRS weight and policy setting, 287b98b8babSClaudiu Manoil * tailored to the tr03wt and tr47wt registers: 288b98b8babSClaudiu Manoil * equal weight for all Tx Qs, measured in 64byte units 289b98b8babSClaudiu Manoil */ 290b98b8babSClaudiu Manoil #define DEFAULT_WRRS_WEIGHT 0x18181818 291b98b8babSClaudiu Manoil 292ec21e2ecSJeff Kirsher #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 293ec21e2ecSJeff Kirsher 294ec21e2ecSJeff Kirsher #define IEVENT_INIT_CLEAR 0xffffffff 295ec21e2ecSJeff Kirsher #define IEVENT_BABR 0x80000000 296ec21e2ecSJeff Kirsher #define IEVENT_RXC 0x40000000 297ec21e2ecSJeff Kirsher #define IEVENT_BSY 0x20000000 298ec21e2ecSJeff Kirsher #define IEVENT_EBERR 0x10000000 299ec21e2ecSJeff Kirsher #define IEVENT_MSRO 0x04000000 300ec21e2ecSJeff Kirsher #define IEVENT_GTSC 0x02000000 301ec21e2ecSJeff Kirsher #define IEVENT_BABT 0x01000000 302ec21e2ecSJeff Kirsher #define IEVENT_TXC 0x00800000 303ec21e2ecSJeff Kirsher #define IEVENT_TXE 0x00400000 304ec21e2ecSJeff Kirsher #define IEVENT_TXB 0x00200000 305ec21e2ecSJeff Kirsher #define IEVENT_TXF 0x00100000 306ec21e2ecSJeff Kirsher #define IEVENT_LC 0x00040000 307ec21e2ecSJeff Kirsher #define IEVENT_CRL 0x00020000 308ec21e2ecSJeff Kirsher #define IEVENT_XFUN 0x00010000 309ec21e2ecSJeff Kirsher #define IEVENT_RXB0 0x00008000 310ec21e2ecSJeff Kirsher #define IEVENT_MAG 0x00000800 311ec21e2ecSJeff Kirsher #define IEVENT_GRSC 0x00000100 312ec21e2ecSJeff Kirsher #define IEVENT_RXF0 0x00000080 3133e905b80SClaudiu Manoil #define IEVENT_FGPI 0x00000010 314ec21e2ecSJeff Kirsher #define IEVENT_FIR 0x00000008 315ec21e2ecSJeff Kirsher #define IEVENT_FIQ 0x00000004 316ec21e2ecSJeff Kirsher #define IEVENT_DPE 0x00000002 317ec21e2ecSJeff Kirsher #define IEVENT_PERR 0x00000001 318ec21e2ecSJeff Kirsher #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 319ec21e2ecSJeff Kirsher #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 320ec21e2ecSJeff Kirsher #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 321ec21e2ecSJeff Kirsher #define IEVENT_ERR_MASK \ 322ec21e2ecSJeff Kirsher (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 323ec21e2ecSJeff Kirsher IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 324ec21e2ecSJeff Kirsher | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 325ec21e2ecSJeff Kirsher | IEVENT_MAG | IEVENT_BABR) 326ec21e2ecSJeff Kirsher 327ec21e2ecSJeff Kirsher #define IMASK_INIT_CLEAR 0x00000000 328ec21e2ecSJeff Kirsher #define IMASK_BABR 0x80000000 329ec21e2ecSJeff Kirsher #define IMASK_RXC 0x40000000 330ec21e2ecSJeff Kirsher #define IMASK_BSY 0x20000000 331ec21e2ecSJeff Kirsher #define IMASK_EBERR 0x10000000 332ec21e2ecSJeff Kirsher #define IMASK_MSRO 0x04000000 333ec21e2ecSJeff Kirsher #define IMASK_GTSC 0x02000000 334ec21e2ecSJeff Kirsher #define IMASK_BABT 0x01000000 335ec21e2ecSJeff Kirsher #define IMASK_TXC 0x00800000 336ec21e2ecSJeff Kirsher #define IMASK_TXEEN 0x00400000 337ec21e2ecSJeff Kirsher #define IMASK_TXBEN 0x00200000 338ec21e2ecSJeff Kirsher #define IMASK_TXFEN 0x00100000 339ec21e2ecSJeff Kirsher #define IMASK_LC 0x00040000 340ec21e2ecSJeff Kirsher #define IMASK_CRL 0x00020000 341ec21e2ecSJeff Kirsher #define IMASK_XFUN 0x00010000 342ec21e2ecSJeff Kirsher #define IMASK_RXB0 0x00008000 343ec21e2ecSJeff Kirsher #define IMASK_MAG 0x00000800 344ec21e2ecSJeff Kirsher #define IMASK_GRSC 0x00000100 345ec21e2ecSJeff Kirsher #define IMASK_RXFEN0 0x00000080 3463e905b80SClaudiu Manoil #define IMASK_FGPI 0x00000010 347ec21e2ecSJeff Kirsher #define IMASK_FIR 0x00000008 348ec21e2ecSJeff Kirsher #define IMASK_FIQ 0x00000004 349ec21e2ecSJeff Kirsher #define IMASK_DPE 0x00000002 350ec21e2ecSJeff Kirsher #define IMASK_PERR 0x00000001 351ec21e2ecSJeff Kirsher #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 352ec21e2ecSJeff Kirsher IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 353ec21e2ecSJeff Kirsher IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 354ec21e2ecSJeff Kirsher | IMASK_PERR) 355aeb12c5eSClaudiu Manoil #define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY) 356aeb12c5eSClaudiu Manoil #define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN) 357aeb12c5eSClaudiu Manoil 358aeb12c5eSClaudiu Manoil #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT) 359aeb12c5eSClaudiu Manoil #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT) 360ec21e2ecSJeff Kirsher 361ec21e2ecSJeff Kirsher /* Attribute fields */ 362ec21e2ecSJeff Kirsher 363ec21e2ecSJeff Kirsher /* This enables rx snooping for buffers and descriptors */ 364ec21e2ecSJeff Kirsher #define ATTR_BDSTASH 0x00000800 365ec21e2ecSJeff Kirsher 366ec21e2ecSJeff Kirsher #define ATTR_BUFSTASH 0x00004000 367ec21e2ecSJeff Kirsher 368ec21e2ecSJeff Kirsher #define ATTR_SNOOPING 0x000000c0 369ec21e2ecSJeff Kirsher #define ATTR_INIT_SETTINGS ATTR_SNOOPING 370ec21e2ecSJeff Kirsher 371ec21e2ecSJeff Kirsher #define ATTRELI_INIT_SETTINGS 0x0 372ec21e2ecSJeff Kirsher #define ATTRELI_EL_MASK 0x3fff0000 373ec21e2ecSJeff Kirsher #define ATTRELI_EL(x) (x << 16) 374ec21e2ecSJeff Kirsher #define ATTRELI_EI_MASK 0x00003fff 375ec21e2ecSJeff Kirsher #define ATTRELI_EI(x) (x) 376ec21e2ecSJeff Kirsher 377ec21e2ecSJeff Kirsher #define BD_LFLAG(flags) ((flags) << 16) 378ec21e2ecSJeff Kirsher #define BD_LENGTH_MASK 0x0000ffff 379ec21e2ecSJeff Kirsher 380ec21e2ecSJeff Kirsher #define FPR_FILER_MASK 0xFFFFFFFF 381ec21e2ecSJeff Kirsher #define MAX_FILER_IDX 0xFF 382ec21e2ecSJeff Kirsher 383ec21e2ecSJeff Kirsher /* This default RIR value directly corresponds 384ec21e2ecSJeff Kirsher * to the 3-bit hash value generated */ 38571ff9e3dSClaudiu Manoil #define DEFAULT_8RXQ_RIR0 0x05397700 38671ff9e3dSClaudiu Manoil /* Map even hash values to Q0, and odd ones to Q1 */ 38771ff9e3dSClaudiu Manoil #define DEFAULT_2RXQ_RIR0 0x04104100 388ec21e2ecSJeff Kirsher 389ec21e2ecSJeff Kirsher /* RQFCR register bits */ 390ec21e2ecSJeff Kirsher #define RQFCR_GPI 0x80000000 391ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_Q 0x00000000 392ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_0 0x00020000 393ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_1 0x00040000 394ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_2 0x00060000 395ec21e2ecSJeff Kirsher #define RQFCR_HASHTBL_3 0x00080000 396ec21e2ecSJeff Kirsher #define RQFCR_HASH 0x00010000 397ec21e2ecSJeff Kirsher #define RQFCR_QUEUE 0x0000FC00 398ec21e2ecSJeff Kirsher #define RQFCR_CLE 0x00000200 399ec21e2ecSJeff Kirsher #define RQFCR_RJE 0x00000100 400ec21e2ecSJeff Kirsher #define RQFCR_AND 0x00000080 401ec21e2ecSJeff Kirsher #define RQFCR_CMP_EXACT 0x00000000 402ec21e2ecSJeff Kirsher #define RQFCR_CMP_MATCH 0x00000020 403ec21e2ecSJeff Kirsher #define RQFCR_CMP_NOEXACT 0x00000040 404ec21e2ecSJeff Kirsher #define RQFCR_CMP_NOMATCH 0x00000060 405ec21e2ecSJeff Kirsher 406ec21e2ecSJeff Kirsher /* RQFCR PID values */ 407ec21e2ecSJeff Kirsher #define RQFCR_PID_MASK 0x00000000 408ec21e2ecSJeff Kirsher #define RQFCR_PID_PARSE 0x00000001 409ec21e2ecSJeff Kirsher #define RQFCR_PID_ARB 0x00000002 410ec21e2ecSJeff Kirsher #define RQFCR_PID_DAH 0x00000003 411ec21e2ecSJeff Kirsher #define RQFCR_PID_DAL 0x00000004 412ec21e2ecSJeff Kirsher #define RQFCR_PID_SAH 0x00000005 413ec21e2ecSJeff Kirsher #define RQFCR_PID_SAL 0x00000006 414ec21e2ecSJeff Kirsher #define RQFCR_PID_ETY 0x00000007 415ec21e2ecSJeff Kirsher #define RQFCR_PID_VID 0x00000008 416ec21e2ecSJeff Kirsher #define RQFCR_PID_PRI 0x00000009 417ec21e2ecSJeff Kirsher #define RQFCR_PID_TOS 0x0000000A 418ec21e2ecSJeff Kirsher #define RQFCR_PID_L4P 0x0000000B 419ec21e2ecSJeff Kirsher #define RQFCR_PID_DIA 0x0000000C 420ec21e2ecSJeff Kirsher #define RQFCR_PID_SIA 0x0000000D 421ec21e2ecSJeff Kirsher #define RQFCR_PID_DPT 0x0000000E 422ec21e2ecSJeff Kirsher #define RQFCR_PID_SPT 0x0000000F 423ec21e2ecSJeff Kirsher 424ec21e2ecSJeff Kirsher /* RQFPR when PID is 0x0001 */ 425ec21e2ecSJeff Kirsher #define RQFPR_HDR_GE_512 0x00200000 426ec21e2ecSJeff Kirsher #define RQFPR_LERR 0x00100000 427ec21e2ecSJeff Kirsher #define RQFPR_RAR 0x00080000 428ec21e2ecSJeff Kirsher #define RQFPR_RARQ 0x00040000 429ec21e2ecSJeff Kirsher #define RQFPR_AR 0x00020000 430ec21e2ecSJeff Kirsher #define RQFPR_ARQ 0x00010000 431ec21e2ecSJeff Kirsher #define RQFPR_EBC 0x00008000 432ec21e2ecSJeff Kirsher #define RQFPR_VLN 0x00004000 433ec21e2ecSJeff Kirsher #define RQFPR_CFI 0x00002000 434ec21e2ecSJeff Kirsher #define RQFPR_JUM 0x00001000 435ec21e2ecSJeff Kirsher #define RQFPR_IPF 0x00000800 436ec21e2ecSJeff Kirsher #define RQFPR_FIF 0x00000400 437ec21e2ecSJeff Kirsher #define RQFPR_IPV4 0x00000200 438ec21e2ecSJeff Kirsher #define RQFPR_IPV6 0x00000100 439ec21e2ecSJeff Kirsher #define RQFPR_ICC 0x00000080 440ec21e2ecSJeff Kirsher #define RQFPR_ICV 0x00000040 441ec21e2ecSJeff Kirsher #define RQFPR_TCP 0x00000020 442ec21e2ecSJeff Kirsher #define RQFPR_UDP 0x00000010 443ec21e2ecSJeff Kirsher #define RQFPR_TUC 0x00000008 444ec21e2ecSJeff Kirsher #define RQFPR_TUV 0x00000004 445ec21e2ecSJeff Kirsher #define RQFPR_PER 0x00000002 446ec21e2ecSJeff Kirsher #define RQFPR_EER 0x00000001 447ec21e2ecSJeff Kirsher 448ec21e2ecSJeff Kirsher /* TxBD status field bits */ 449ec21e2ecSJeff Kirsher #define TXBD_READY 0x8000 450ec21e2ecSJeff Kirsher #define TXBD_PADCRC 0x4000 451ec21e2ecSJeff Kirsher #define TXBD_WRAP 0x2000 452ec21e2ecSJeff Kirsher #define TXBD_INTERRUPT 0x1000 453ec21e2ecSJeff Kirsher #define TXBD_LAST 0x0800 454ec21e2ecSJeff Kirsher #define TXBD_CRC 0x0400 455ec21e2ecSJeff Kirsher #define TXBD_DEF 0x0200 456ec21e2ecSJeff Kirsher #define TXBD_HUGEFRAME 0x0080 457ec21e2ecSJeff Kirsher #define TXBD_LATECOLLISION 0x0080 458ec21e2ecSJeff Kirsher #define TXBD_RETRYLIMIT 0x0040 459ec21e2ecSJeff Kirsher #define TXBD_RETRYCOUNTMASK 0x003c 460ec21e2ecSJeff Kirsher #define TXBD_UNDERRUN 0x0002 461ec21e2ecSJeff Kirsher #define TXBD_TOE 0x0002 462ec21e2ecSJeff Kirsher 463ec21e2ecSJeff Kirsher /* Tx FCB param bits */ 464ec21e2ecSJeff Kirsher #define TXFCB_VLN 0x80 465ec21e2ecSJeff Kirsher #define TXFCB_IP 0x40 466ec21e2ecSJeff Kirsher #define TXFCB_IP6 0x20 467ec21e2ecSJeff Kirsher #define TXFCB_TUP 0x10 468ec21e2ecSJeff Kirsher #define TXFCB_UDP 0x08 469ec21e2ecSJeff Kirsher #define TXFCB_CIP 0x04 470ec21e2ecSJeff Kirsher #define TXFCB_CTU 0x02 471ec21e2ecSJeff Kirsher #define TXFCB_NPH 0x01 472ec21e2ecSJeff Kirsher #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 473ec21e2ecSJeff Kirsher 474ec21e2ecSJeff Kirsher /* RxBD status field bits */ 475ec21e2ecSJeff Kirsher #define RXBD_EMPTY 0x8000 476ec21e2ecSJeff Kirsher #define RXBD_RO1 0x4000 477ec21e2ecSJeff Kirsher #define RXBD_WRAP 0x2000 478ec21e2ecSJeff Kirsher #define RXBD_INTERRUPT 0x1000 479ec21e2ecSJeff Kirsher #define RXBD_LAST 0x0800 480ec21e2ecSJeff Kirsher #define RXBD_FIRST 0x0400 481ec21e2ecSJeff Kirsher #define RXBD_MISS 0x0100 482ec21e2ecSJeff Kirsher #define RXBD_BROADCAST 0x0080 483ec21e2ecSJeff Kirsher #define RXBD_MULTICAST 0x0040 484ec21e2ecSJeff Kirsher #define RXBD_LARGE 0x0020 485ec21e2ecSJeff Kirsher #define RXBD_NONOCTET 0x0010 486ec21e2ecSJeff Kirsher #define RXBD_SHORT 0x0008 487ec21e2ecSJeff Kirsher #define RXBD_CRCERR 0x0004 488ec21e2ecSJeff Kirsher #define RXBD_OVERRUN 0x0002 489ec21e2ecSJeff Kirsher #define RXBD_TRUNCATED 0x0001 490ec21e2ecSJeff Kirsher #define RXBD_STATS 0x01ff 491ec21e2ecSJeff Kirsher #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 492ec21e2ecSJeff Kirsher | RXBD_CRCERR | RXBD_OVERRUN \ 493ec21e2ecSJeff Kirsher | RXBD_TRUNCATED) 494ec21e2ecSJeff Kirsher 495ec21e2ecSJeff Kirsher /* Rx FCB status field bits */ 496ec21e2ecSJeff Kirsher #define RXFCB_VLN 0x8000 497ec21e2ecSJeff Kirsher #define RXFCB_IP 0x4000 498ec21e2ecSJeff Kirsher #define RXFCB_IP6 0x2000 499ec21e2ecSJeff Kirsher #define RXFCB_TUP 0x1000 500ec21e2ecSJeff Kirsher #define RXFCB_CIP 0x0800 501ec21e2ecSJeff Kirsher #define RXFCB_CTU 0x0400 502ec21e2ecSJeff Kirsher #define RXFCB_EIP 0x0200 503ec21e2ecSJeff Kirsher #define RXFCB_ETU 0x0100 504ec21e2ecSJeff Kirsher #define RXFCB_CSUM_MASK 0x0f00 505ec21e2ecSJeff Kirsher #define RXFCB_PERR_MASK 0x000c 506ec21e2ecSJeff Kirsher #define RXFCB_PERR_BADL3 0x0008 507ec21e2ecSJeff Kirsher 5080015e551SJoe Perches #define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 509ec21e2ecSJeff Kirsher 5103e905b80SClaudiu Manoil #define GFAR_WOL_MAGIC 0x00000001 5113e905b80SClaudiu Manoil #define GFAR_WOL_FILER_UCAST 0x00000002 5123e905b80SClaudiu Manoil 513ec21e2ecSJeff Kirsher struct txbd8 514ec21e2ecSJeff Kirsher { 515ec21e2ecSJeff Kirsher union { 516ec21e2ecSJeff Kirsher struct { 517a7312d58SClaudiu Manoil __be16 status; /* Status Fields */ 518a7312d58SClaudiu Manoil __be16 length; /* Buffer length */ 519ec21e2ecSJeff Kirsher }; 520a7312d58SClaudiu Manoil __be32 lstatus; 521ec21e2ecSJeff Kirsher }; 522a7312d58SClaudiu Manoil __be32 bufPtr; /* Buffer Pointer */ 523ec21e2ecSJeff Kirsher }; 524ec21e2ecSJeff Kirsher 525ec21e2ecSJeff Kirsher struct txfcb { 526ec21e2ecSJeff Kirsher u8 flags; 527ec21e2ecSJeff Kirsher u8 ptp; /* Flag to enable tx timestamping */ 528ec21e2ecSJeff Kirsher u8 l4os; /* Level 4 Header Offset */ 529ec21e2ecSJeff Kirsher u8 l3os; /* Level 3 Header Offset */ 53026eb9374SClaudiu Manoil __be16 phcs; /* Pseudo-header Checksum */ 53126eb9374SClaudiu Manoil __be16 vlctl; /* VLAN control word */ 532ec21e2ecSJeff Kirsher }; 533ec21e2ecSJeff Kirsher 534ec21e2ecSJeff Kirsher struct rxbd8 535ec21e2ecSJeff Kirsher { 536ec21e2ecSJeff Kirsher union { 537ec21e2ecSJeff Kirsher struct { 538a7312d58SClaudiu Manoil __be16 status; /* Status Fields */ 539a7312d58SClaudiu Manoil __be16 length; /* Buffer Length */ 540ec21e2ecSJeff Kirsher }; 541a7312d58SClaudiu Manoil __be32 lstatus; 542ec21e2ecSJeff Kirsher }; 543a7312d58SClaudiu Manoil __be32 bufPtr; /* Buffer Pointer */ 544ec21e2ecSJeff Kirsher }; 545ec21e2ecSJeff Kirsher 546ec21e2ecSJeff Kirsher struct rxfcb { 54726eb9374SClaudiu Manoil __be16 flags; 548ec21e2ecSJeff Kirsher u8 rq; /* Receive Queue index */ 549ec21e2ecSJeff Kirsher u8 pro; /* Layer 4 Protocol */ 550ec21e2ecSJeff Kirsher u16 reserved; 55126eb9374SClaudiu Manoil __be16 vlctl; /* VLAN control word */ 552ec21e2ecSJeff Kirsher }; 553ec21e2ecSJeff Kirsher 554ec21e2ecSJeff Kirsher struct gianfar_skb_cb { 55550ad076bSClaudiu Manoil unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ 556ec21e2ecSJeff Kirsher }; 557ec21e2ecSJeff Kirsher 558ec21e2ecSJeff Kirsher #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 559ec21e2ecSJeff Kirsher 560ec21e2ecSJeff Kirsher struct rmon_mib 561ec21e2ecSJeff Kirsher { 562ec21e2ecSJeff Kirsher u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 563ec21e2ecSJeff Kirsher u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 564ec21e2ecSJeff Kirsher u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 565ec21e2ecSJeff Kirsher u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 566ec21e2ecSJeff Kirsher u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 567ec21e2ecSJeff Kirsher u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 568ec21e2ecSJeff Kirsher u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 569ec21e2ecSJeff Kirsher u32 rbyt; /* 0x.69c - Receive Byte Counter */ 570ec21e2ecSJeff Kirsher u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 571ec21e2ecSJeff Kirsher u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 572ec21e2ecSJeff Kirsher u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 573ec21e2ecSJeff Kirsher u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 574ec21e2ecSJeff Kirsher u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 575ec21e2ecSJeff Kirsher u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 576ec21e2ecSJeff Kirsher u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 577ec21e2ecSJeff Kirsher u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 578ec21e2ecSJeff Kirsher u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 579ec21e2ecSJeff Kirsher u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 580ec21e2ecSJeff Kirsher u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 581ec21e2ecSJeff Kirsher u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 582ec21e2ecSJeff Kirsher u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 583ec21e2ecSJeff Kirsher u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 584ec21e2ecSJeff Kirsher u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 585ec21e2ecSJeff Kirsher u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 586ec21e2ecSJeff Kirsher u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 587ec21e2ecSJeff Kirsher u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 588ec21e2ecSJeff Kirsher u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 589ec21e2ecSJeff Kirsher u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 590ec21e2ecSJeff Kirsher u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 591ec21e2ecSJeff Kirsher u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 592ec21e2ecSJeff Kirsher u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 593ec21e2ecSJeff Kirsher u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 594ec21e2ecSJeff Kirsher u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 595ec21e2ecSJeff Kirsher u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 596ec21e2ecSJeff Kirsher u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 597ec21e2ecSJeff Kirsher u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 598ec21e2ecSJeff Kirsher u8 res1[4]; 599ec21e2ecSJeff Kirsher u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 600ec21e2ecSJeff Kirsher u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 601ec21e2ecSJeff Kirsher u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 602ec21e2ecSJeff Kirsher u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 603ec21e2ecSJeff Kirsher u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 604ec21e2ecSJeff Kirsher u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 605ec21e2ecSJeff Kirsher u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 606ec21e2ecSJeff Kirsher u32 car1; /* 0x.730 - Carry Register One */ 607ec21e2ecSJeff Kirsher u32 car2; /* 0x.734 - Carry Register Two */ 608ec21e2ecSJeff Kirsher u32 cam1; /* 0x.738 - Carry Mask Register One */ 609ec21e2ecSJeff Kirsher u32 cam2; /* 0x.73c - Carry Mask Register Two */ 610ec21e2ecSJeff Kirsher }; 611ec21e2ecSJeff Kirsher 612ec21e2ecSJeff Kirsher struct gfar_extra_stats { 61376f31e8bSClaudiu Manoil atomic64_t rx_alloc_err; 614212079dfSPaul Gortmaker atomic64_t rx_large; 615212079dfSPaul Gortmaker atomic64_t rx_short; 616212079dfSPaul Gortmaker atomic64_t rx_nonoctet; 617212079dfSPaul Gortmaker atomic64_t rx_crcerr; 618212079dfSPaul Gortmaker atomic64_t rx_overrun; 619212079dfSPaul Gortmaker atomic64_t rx_bsy; 620212079dfSPaul Gortmaker atomic64_t rx_babr; 621212079dfSPaul Gortmaker atomic64_t rx_trunc; 622212079dfSPaul Gortmaker atomic64_t eberr; 623212079dfSPaul Gortmaker atomic64_t tx_babt; 624212079dfSPaul Gortmaker atomic64_t tx_underrun; 625212079dfSPaul Gortmaker atomic64_t tx_timeout; 626ec21e2ecSJeff Kirsher }; 627ec21e2ecSJeff Kirsher 628ec21e2ecSJeff Kirsher #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 629212079dfSPaul Gortmaker #define GFAR_EXTRA_STATS_LEN \ 630212079dfSPaul Gortmaker (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 631ec21e2ecSJeff Kirsher 63268719786SPaul Gortmaker /* Number of stats exported via ethtool */ 633ec21e2ecSJeff Kirsher #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 634ec21e2ecSJeff Kirsher 635ec21e2ecSJeff Kirsher struct gfar { 636ec21e2ecSJeff Kirsher u32 tsec_id; /* 0x.000 - Controller ID register */ 637ec21e2ecSJeff Kirsher u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 638ec21e2ecSJeff Kirsher u8 res1[8]; 639ec21e2ecSJeff Kirsher u32 ievent; /* 0x.010 - Interrupt Event Register */ 640ec21e2ecSJeff Kirsher u32 imask; /* 0x.014 - Interrupt Mask Register */ 641ec21e2ecSJeff Kirsher u32 edis; /* 0x.018 - Error Disabled Register */ 642ec21e2ecSJeff Kirsher u32 emapg; /* 0x.01c - Group Error mapping register */ 643ec21e2ecSJeff Kirsher u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 644ec21e2ecSJeff Kirsher u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 645ec21e2ecSJeff Kirsher u32 ptv; /* 0x.028 - Pause Time Value Register */ 646ec21e2ecSJeff Kirsher u32 dmactrl; /* 0x.02c - DMA Control Register */ 647ec21e2ecSJeff Kirsher u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 648ec21e2ecSJeff Kirsher u8 res2[28]; 649ec21e2ecSJeff Kirsher u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 650ec21e2ecSJeff Kirsher register */ 651ec21e2ecSJeff Kirsher u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 652ec21e2ecSJeff Kirsher register */ 653ec21e2ecSJeff Kirsher u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 654ec21e2ecSJeff Kirsher register */ 655ec21e2ecSJeff Kirsher u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 656ec21e2ecSJeff Kirsher shutoff register */ 657ec21e2ecSJeff Kirsher u8 res3[44]; 658ec21e2ecSJeff Kirsher u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 659ec21e2ecSJeff Kirsher u8 res4[8]; 660ec21e2ecSJeff Kirsher u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 661ec21e2ecSJeff Kirsher u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 662ec21e2ecSJeff Kirsher u8 res5[96]; 663ec21e2ecSJeff Kirsher u32 tctrl; /* 0x.100 - Transmit Control Register */ 664ec21e2ecSJeff Kirsher u32 tstat; /* 0x.104 - Transmit Status Register */ 665ec21e2ecSJeff Kirsher u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 666ec21e2ecSJeff Kirsher u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 667ec21e2ecSJeff Kirsher u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 668ec21e2ecSJeff Kirsher u32 tqueue; /* 0x.114 - Transmit queue control register */ 669ec21e2ecSJeff Kirsher u8 res7[40]; 670ec21e2ecSJeff Kirsher u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 671ec21e2ecSJeff Kirsher u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 672ec21e2ecSJeff Kirsher u8 res8[52]; 673ec21e2ecSJeff Kirsher u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 674ec21e2ecSJeff Kirsher u8 res9a[4]; 675ec21e2ecSJeff Kirsher u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 676ec21e2ecSJeff Kirsher u8 res9b[4]; 677ec21e2ecSJeff Kirsher u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 678ec21e2ecSJeff Kirsher u8 res9c[4]; 679ec21e2ecSJeff Kirsher u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 680ec21e2ecSJeff Kirsher u8 res9d[4]; 681ec21e2ecSJeff Kirsher u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 682ec21e2ecSJeff Kirsher u8 res9e[4]; 683ec21e2ecSJeff Kirsher u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 684ec21e2ecSJeff Kirsher u8 res9f[4]; 685ec21e2ecSJeff Kirsher u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 686ec21e2ecSJeff Kirsher u8 res9g[4]; 687ec21e2ecSJeff Kirsher u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 688ec21e2ecSJeff Kirsher u8 res9h[4]; 689ec21e2ecSJeff Kirsher u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 690ec21e2ecSJeff Kirsher u8 res9[64]; 691ec21e2ecSJeff Kirsher u32 tbaseh; /* 0x.200 - TxBD base address high */ 692ec21e2ecSJeff Kirsher u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 693ec21e2ecSJeff Kirsher u8 res10a[4]; 694ec21e2ecSJeff Kirsher u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 695ec21e2ecSJeff Kirsher u8 res10b[4]; 696ec21e2ecSJeff Kirsher u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 697ec21e2ecSJeff Kirsher u8 res10c[4]; 698ec21e2ecSJeff Kirsher u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 699ec21e2ecSJeff Kirsher u8 res10d[4]; 700ec21e2ecSJeff Kirsher u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 701ec21e2ecSJeff Kirsher u8 res10e[4]; 702ec21e2ecSJeff Kirsher u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 703ec21e2ecSJeff Kirsher u8 res10f[4]; 704ec21e2ecSJeff Kirsher u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 705ec21e2ecSJeff Kirsher u8 res10g[4]; 706ec21e2ecSJeff Kirsher u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 707ec21e2ecSJeff Kirsher u8 res10[192]; 708ec21e2ecSJeff Kirsher u32 rctrl; /* 0x.300 - Receive Control Register */ 709ec21e2ecSJeff Kirsher u32 rstat; /* 0x.304 - Receive Status Register */ 710ec21e2ecSJeff Kirsher u8 res12[8]; 711ec21e2ecSJeff Kirsher u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 712ec21e2ecSJeff Kirsher u32 rqueue; /* 0x.314 - Receive queue control register */ 713ec21e2ecSJeff Kirsher u32 rir0; /* 0x.318 - Ring mapping register 0 */ 714ec21e2ecSJeff Kirsher u32 rir1; /* 0x.31c - Ring mapping register 1 */ 715ec21e2ecSJeff Kirsher u32 rir2; /* 0x.320 - Ring mapping register 2 */ 716ec21e2ecSJeff Kirsher u32 rir3; /* 0x.324 - Ring mapping register 3 */ 717ec21e2ecSJeff Kirsher u8 res13[8]; 718ec21e2ecSJeff Kirsher u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 719ec21e2ecSJeff Kirsher u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 720ec21e2ecSJeff Kirsher u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 721ec21e2ecSJeff Kirsher u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 722ec21e2ecSJeff Kirsher u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 723ec21e2ecSJeff Kirsher u8 res14[56]; 724ec21e2ecSJeff Kirsher u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 725ec21e2ecSJeff Kirsher u8 res15a[4]; 726ec21e2ecSJeff Kirsher u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 727ec21e2ecSJeff Kirsher u8 res15b[4]; 728ec21e2ecSJeff Kirsher u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 729ec21e2ecSJeff Kirsher u8 res15c[4]; 730ec21e2ecSJeff Kirsher u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 731ec21e2ecSJeff Kirsher u8 res15d[4]; 732ec21e2ecSJeff Kirsher u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 733ec21e2ecSJeff Kirsher u8 res15e[4]; 734ec21e2ecSJeff Kirsher u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 735ec21e2ecSJeff Kirsher u8 res15f[4]; 736ec21e2ecSJeff Kirsher u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 737ec21e2ecSJeff Kirsher u8 res15g[4]; 738ec21e2ecSJeff Kirsher u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 739ec21e2ecSJeff Kirsher u8 res15h[4]; 740ec21e2ecSJeff Kirsher u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 741ec21e2ecSJeff Kirsher u8 res16[64]; 742ec21e2ecSJeff Kirsher u32 rbaseh; /* 0x.400 - RxBD base address high */ 743ec21e2ecSJeff Kirsher u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 744ec21e2ecSJeff Kirsher u8 res17a[4]; 745ec21e2ecSJeff Kirsher u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 746ec21e2ecSJeff Kirsher u8 res17b[4]; 747ec21e2ecSJeff Kirsher u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 748ec21e2ecSJeff Kirsher u8 res17c[4]; 749ec21e2ecSJeff Kirsher u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 750ec21e2ecSJeff Kirsher u8 res17d[4]; 751ec21e2ecSJeff Kirsher u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 752ec21e2ecSJeff Kirsher u8 res17e[4]; 753ec21e2ecSJeff Kirsher u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 754ec21e2ecSJeff Kirsher u8 res17f[4]; 755ec21e2ecSJeff Kirsher u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 756ec21e2ecSJeff Kirsher u8 res17g[4]; 757ec21e2ecSJeff Kirsher u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 758ec21e2ecSJeff Kirsher u8 res17[192]; 759ec21e2ecSJeff Kirsher u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 760ec21e2ecSJeff Kirsher u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 761ec21e2ecSJeff Kirsher u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 762ec21e2ecSJeff Kirsher u32 hafdup; /* 0x.50c - Half Duplex Register */ 763ec21e2ecSJeff Kirsher u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 764ec21e2ecSJeff Kirsher u8 res18[12]; 765ec21e2ecSJeff Kirsher u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 766ec21e2ecSJeff Kirsher u32 ifctrl; /* 0x.538 - Interface control register */ 767ec21e2ecSJeff Kirsher u32 ifstat; /* 0x.53c - Interface Status Register */ 768ec21e2ecSJeff Kirsher u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 769ec21e2ecSJeff Kirsher u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 770ec21e2ecSJeff Kirsher u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 771ec21e2ecSJeff Kirsher u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 772ec21e2ecSJeff Kirsher u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 773ec21e2ecSJeff Kirsher u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 774ec21e2ecSJeff Kirsher u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 775ec21e2ecSJeff Kirsher u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 776ec21e2ecSJeff Kirsher u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 777ec21e2ecSJeff Kirsher u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 778ec21e2ecSJeff Kirsher u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 779ec21e2ecSJeff Kirsher u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 780ec21e2ecSJeff Kirsher u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 781ec21e2ecSJeff Kirsher u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 782ec21e2ecSJeff Kirsher u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 783ec21e2ecSJeff Kirsher u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 784ec21e2ecSJeff Kirsher u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 785ec21e2ecSJeff Kirsher u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 786ec21e2ecSJeff Kirsher u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 787ec21e2ecSJeff Kirsher u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 788ec21e2ecSJeff Kirsher u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 789ec21e2ecSJeff Kirsher u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 790ec21e2ecSJeff Kirsher u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 791ec21e2ecSJeff Kirsher u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 792ec21e2ecSJeff Kirsher u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 793ec21e2ecSJeff Kirsher u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 794ec21e2ecSJeff Kirsher u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 795ec21e2ecSJeff Kirsher u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 796ec21e2ecSJeff Kirsher u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 797ec21e2ecSJeff Kirsher u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 798ec21e2ecSJeff Kirsher u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 799ec21e2ecSJeff Kirsher u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 800ec21e2ecSJeff Kirsher u8 res20[192]; 801ec21e2ecSJeff Kirsher struct rmon_mib rmon; /* 0x.680-0x.73c */ 802ec21e2ecSJeff Kirsher u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 803ec21e2ecSJeff Kirsher u8 res21[188]; 804ec21e2ecSJeff Kirsher u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 805ec21e2ecSJeff Kirsher u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 806ec21e2ecSJeff Kirsher u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 807ec21e2ecSJeff Kirsher u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 808ec21e2ecSJeff Kirsher u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 809ec21e2ecSJeff Kirsher u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 810ec21e2ecSJeff Kirsher u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 811ec21e2ecSJeff Kirsher u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 812ec21e2ecSJeff Kirsher u8 res22[96]; 813ec21e2ecSJeff Kirsher u32 gaddr0; /* 0x.880 - Group address register 0 */ 814ec21e2ecSJeff Kirsher u32 gaddr1; /* 0x.884 - Group address register 1 */ 815ec21e2ecSJeff Kirsher u32 gaddr2; /* 0x.888 - Group address register 2 */ 816ec21e2ecSJeff Kirsher u32 gaddr3; /* 0x.88c - Group address register 3 */ 817ec21e2ecSJeff Kirsher u32 gaddr4; /* 0x.890 - Group address register 4 */ 818ec21e2ecSJeff Kirsher u32 gaddr5; /* 0x.894 - Group address register 5 */ 819ec21e2ecSJeff Kirsher u32 gaddr6; /* 0x.898 - Group address register 6 */ 820ec21e2ecSJeff Kirsher u32 gaddr7; /* 0x.89c - Group address register 7 */ 821ec21e2ecSJeff Kirsher u8 res23a[352]; 822ec21e2ecSJeff Kirsher u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 823ec21e2ecSJeff Kirsher u8 res23b[252]; 824ec21e2ecSJeff Kirsher u8 res23c[248]; 825ec21e2ecSJeff Kirsher u32 attr; /* 0x.bf8 - Attributes Register */ 826ec21e2ecSJeff Kirsher u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 82745b679c9SMatei Pavaluca u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */ 82845b679c9SMatei Pavaluca u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */ 82945b679c9SMatei Pavaluca u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */ 83045b679c9SMatei Pavaluca u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */ 83145b679c9SMatei Pavaluca u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */ 83245b679c9SMatei Pavaluca u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */ 83345b679c9SMatei Pavaluca u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */ 83445b679c9SMatei Pavaluca u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */ 83545b679c9SMatei Pavaluca u8 res24[36]; 83645b679c9SMatei Pavaluca u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */ 83745b679c9SMatei Pavaluca u8 res24a[4]; 83845b679c9SMatei Pavaluca u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */ 83945b679c9SMatei Pavaluca u8 res24b[4]; 84045b679c9SMatei Pavaluca u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */ 84145b679c9SMatei Pavaluca u8 res24c[4]; 84245b679c9SMatei Pavaluca u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */ 84345b679c9SMatei Pavaluca u8 res24d[4]; 84445b679c9SMatei Pavaluca u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */ 84545b679c9SMatei Pavaluca u8 res24e[4]; 84645b679c9SMatei Pavaluca u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */ 84745b679c9SMatei Pavaluca u8 res24f[4]; 84845b679c9SMatei Pavaluca u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */ 84945b679c9SMatei Pavaluca u8 res24g[4]; 85045b679c9SMatei Pavaluca u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */ 85145b679c9SMatei Pavaluca u8 res24h[4]; 85245b679c9SMatei Pavaluca u8 res24x[556]; 853ec21e2ecSJeff Kirsher u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 854ec21e2ecSJeff Kirsher u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 855ec21e2ecSJeff Kirsher u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 856ec21e2ecSJeff Kirsher u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 857ec21e2ecSJeff Kirsher u8 res25[16]; 858ec21e2ecSJeff Kirsher u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 859ec21e2ecSJeff Kirsher u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 860ec21e2ecSJeff Kirsher u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 861ec21e2ecSJeff Kirsher u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 862ec21e2ecSJeff Kirsher u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 863ec21e2ecSJeff Kirsher u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 864ec21e2ecSJeff Kirsher u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 865ec21e2ecSJeff Kirsher u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 866ec21e2ecSJeff Kirsher u8 res26[32]; 867ec21e2ecSJeff Kirsher u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 868ec21e2ecSJeff Kirsher u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 869ec21e2ecSJeff Kirsher u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 870ec21e2ecSJeff Kirsher u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 871ec21e2ecSJeff Kirsher u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 872ec21e2ecSJeff Kirsher u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 873ec21e2ecSJeff Kirsher u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 874ec21e2ecSJeff Kirsher u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 875ec21e2ecSJeff Kirsher u8 res27[208]; 876ec21e2ecSJeff Kirsher }; 877ec21e2ecSJeff Kirsher 878ec21e2ecSJeff Kirsher /* Flags related to gianfar device features */ 879ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 880ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 881ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 882ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 883ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 884ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 885ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 886ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 887ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 888ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 889ec21e2ecSJeff Kirsher #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 8903e905b80SClaudiu Manoil #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000 8917bff47daSHamish Martin #define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000 892ec21e2ecSJeff Kirsher 893ec21e2ecSJeff Kirsher #if (MAXGROUPS == 2) 894ec21e2ecSJeff Kirsher #define DEFAULT_MAPPING 0xAA 895ec21e2ecSJeff Kirsher #else 896ec21e2ecSJeff Kirsher #define DEFAULT_MAPPING 0xFF 897ec21e2ecSJeff Kirsher #endif 898ec21e2ecSJeff Kirsher 89920862788SClaudiu Manoil #define ISRG_RR0 0x80000000 90020862788SClaudiu Manoil #define ISRG_TR0 0x00800000 901ec21e2ecSJeff Kirsher 902ec21e2ecSJeff Kirsher /* The same driver can operate in two modes */ 903ec21e2ecSJeff Kirsher /* SQ_SG_MODE: Single Queue Single Group Mode 904ec21e2ecSJeff Kirsher * (Backward compatible mode) 905ec21e2ecSJeff Kirsher * MQ_MG_MODE: Multi Queue Multi Group mode 906ec21e2ecSJeff Kirsher */ 907ec21e2ecSJeff Kirsher enum { 908ec21e2ecSJeff Kirsher SQ_SG_MODE = 0, 909ec21e2ecSJeff Kirsher MQ_MG_MODE 910ec21e2ecSJeff Kirsher }; 911ec21e2ecSJeff Kirsher 912ec21e2ecSJeff Kirsher /* 913ec21e2ecSJeff Kirsher * Per TX queue stats 914ec21e2ecSJeff Kirsher */ 915ec21e2ecSJeff Kirsher struct tx_q_stats { 916*2658530dSEsben Haabendal u64 tx_packets; 917*2658530dSEsben Haabendal u64 tx_bytes; 918ec21e2ecSJeff Kirsher }; 919ec21e2ecSJeff Kirsher 920ec21e2ecSJeff Kirsher /** 921ec21e2ecSJeff Kirsher * struct gfar_priv_tx_q - per tx queue structure 922ec21e2ecSJeff Kirsher * @txlock: per queue tx spin lock 923ec21e2ecSJeff Kirsher * @tx_skbuff:skb pointers 924ec21e2ecSJeff Kirsher * @skb_curtx: to be used skb pointer 925ec21e2ecSJeff Kirsher * @skb_dirtytx:the last used skb pointer 926ec21e2ecSJeff Kirsher * @stats: bytes/packets stats 927ec21e2ecSJeff Kirsher * @qindex: index of this queue 928ec21e2ecSJeff Kirsher * @dev: back pointer to the dev structure 929ec21e2ecSJeff Kirsher * @grp: back pointer to the group to which this queue belongs 930ec21e2ecSJeff Kirsher * @tx_bd_base: First tx buffer descriptor 931ec21e2ecSJeff Kirsher * @cur_tx: Next free ring entry 932ec21e2ecSJeff Kirsher * @dirty_tx: First buffer in line to be transmitted 933ec21e2ecSJeff Kirsher * @tx_ring_size: Tx ring size 934ec21e2ecSJeff Kirsher * @num_txbdfree: number of free TxBds 935ec21e2ecSJeff Kirsher * @txcoalescing: enable/disable tx coalescing 936ec21e2ecSJeff Kirsher * @txic: transmit interrupt coalescing value 937ec21e2ecSJeff Kirsher * @txcount: coalescing value if based on tx frame count 938ec21e2ecSJeff Kirsher * @txtime: coalescing value if based on time 939ec21e2ecSJeff Kirsher */ 940ec21e2ecSJeff Kirsher struct gfar_priv_tx_q { 9410cd3fdeaSClaudiu Manoil /* cacheline 1 */ 942ec21e2ecSJeff Kirsher spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 943ec21e2ecSJeff Kirsher struct txbd8 *tx_bd_base; 944ec21e2ecSJeff Kirsher struct txbd8 *cur_tx; 945ec21e2ecSJeff Kirsher unsigned int num_txbdfree; 9460cd3fdeaSClaudiu Manoil unsigned short skb_curtx; 9470cd3fdeaSClaudiu Manoil unsigned short tx_ring_size; 9480cd3fdeaSClaudiu Manoil struct tx_q_stats stats; 9490cd3fdeaSClaudiu Manoil struct gfar_priv_grp *grp; 9500cd3fdeaSClaudiu Manoil /* cacheline 2 */ 9510cd3fdeaSClaudiu Manoil struct net_device *dev; 9520cd3fdeaSClaudiu Manoil struct sk_buff **tx_skbuff; 9530cd3fdeaSClaudiu Manoil struct txbd8 *dirty_tx; 9540cd3fdeaSClaudiu Manoil unsigned short skb_dirtytx; 9550cd3fdeaSClaudiu Manoil unsigned short qindex; 956ec21e2ecSJeff Kirsher /* Configuration info for the coalescing features */ 9570cd3fdeaSClaudiu Manoil unsigned int txcoalescing; 958ec21e2ecSJeff Kirsher unsigned long txic; 9590cd3fdeaSClaudiu Manoil dma_addr_t tx_bd_dma_base; 960ec21e2ecSJeff Kirsher }; 961ec21e2ecSJeff Kirsher 962ec21e2ecSJeff Kirsher /* 963ec21e2ecSJeff Kirsher * Per RX queue stats 964ec21e2ecSJeff Kirsher */ 965ec21e2ecSJeff Kirsher struct rx_q_stats { 966*2658530dSEsben Haabendal u64 rx_packets; 967*2658530dSEsben Haabendal u64 rx_bytes; 968*2658530dSEsben Haabendal u64 rx_dropped; 969ec21e2ecSJeff Kirsher }; 970ec21e2ecSJeff Kirsher 97175354148SClaudiu Manoil struct gfar_rx_buff { 97275354148SClaudiu Manoil dma_addr_t dma; 97375354148SClaudiu Manoil struct page *page; 97475354148SClaudiu Manoil unsigned int page_offset; 97575354148SClaudiu Manoil }; 97675354148SClaudiu Manoil 977ec21e2ecSJeff Kirsher /** 978ec21e2ecSJeff Kirsher * struct gfar_priv_rx_q - per rx queue structure 97975354148SClaudiu Manoil * @rx_buff: Array of buffer info metadata structs 980ec21e2ecSJeff Kirsher * @rx_bd_base: First rx buffer descriptor 98176f31e8bSClaudiu Manoil * @next_to_use: index of the next buffer to be alloc'd 98276f31e8bSClaudiu Manoil * @next_to_clean: index of the next buffer to be cleaned 983ec21e2ecSJeff Kirsher * @qindex: index of this queue 984f23223f1SClaudiu Manoil * @ndev: back pointer to net_device 985ec21e2ecSJeff Kirsher * @rx_ring_size: Rx ring size 986ec21e2ecSJeff Kirsher * @rxcoalescing: enable/disable rx-coalescing 987ec21e2ecSJeff Kirsher * @rxic: receive interrupt coalescing vlaue 988ec21e2ecSJeff Kirsher */ 989ec21e2ecSJeff Kirsher 990ec21e2ecSJeff Kirsher struct gfar_priv_rx_q { 99175354148SClaudiu Manoil struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES); 992ec21e2ecSJeff Kirsher struct rxbd8 *rx_bd_base; 993f23223f1SClaudiu Manoil struct net_device *ndev; 99475354148SClaudiu Manoil struct device *dev; 99576f31e8bSClaudiu Manoil u16 rx_ring_size; 996ec21e2ecSJeff Kirsher u16 qindex; 99775354148SClaudiu Manoil struct gfar_priv_grp *grp; 99876f31e8bSClaudiu Manoil u16 next_to_clean; 99976f31e8bSClaudiu Manoil u16 next_to_use; 100075354148SClaudiu Manoil u16 next_to_alloc; 100175354148SClaudiu Manoil struct sk_buff *skb; 100276f31e8bSClaudiu Manoil struct rx_q_stats stats; 100376f31e8bSClaudiu Manoil u32 __iomem *rfbptr; 1004ec21e2ecSJeff Kirsher unsigned char rxcoalescing; 1005ec21e2ecSJeff Kirsher unsigned long rxic; 100676f31e8bSClaudiu Manoil dma_addr_t rx_bd_dma_base; 1007ec21e2ecSJeff Kirsher }; 1008ec21e2ecSJeff Kirsher 1009ee873fdaSClaudiu Manoil enum gfar_irqinfo_id { 1010ee873fdaSClaudiu Manoil GFAR_TX = 0, 1011ee873fdaSClaudiu Manoil GFAR_RX = 1, 1012ee873fdaSClaudiu Manoil GFAR_ER = 2, 1013ee873fdaSClaudiu Manoil GFAR_NUM_IRQS = 3 1014ee873fdaSClaudiu Manoil }; 1015ee873fdaSClaudiu Manoil 1016ee873fdaSClaudiu Manoil struct gfar_irqinfo { 1017ee873fdaSClaudiu Manoil unsigned int irq; 1018ee873fdaSClaudiu Manoil char name[GFAR_INT_NAME_MAX]; 1019ee873fdaSClaudiu Manoil }; 1020ee873fdaSClaudiu Manoil 1021ec21e2ecSJeff Kirsher /** 1022ec21e2ecSJeff Kirsher * struct gfar_priv_grp - per group structure 1023ec21e2ecSJeff Kirsher * @napi: the napi poll function 1024ec21e2ecSJeff Kirsher * @priv: back pointer to the priv structure 1025ec21e2ecSJeff Kirsher * @regs: the ioremapped register space for this group 1026ee873fdaSClaudiu Manoil * @irqinfo: TX/RX/ER irq data for this group 1027ec21e2ecSJeff Kirsher */ 1028ec21e2ecSJeff Kirsher 1029ec21e2ecSJeff Kirsher struct gfar_priv_grp { 103071ff9e3dSClaudiu Manoil spinlock_t grplock __aligned(SMP_CACHE_BYTES); 1031aeb12c5eSClaudiu Manoil struct napi_struct napi_rx; 1032aeb12c5eSClaudiu Manoil struct napi_struct napi_tx; 1033ec21e2ecSJeff Kirsher struct gfar __iomem *regs; 103471ff9e3dSClaudiu Manoil struct gfar_priv_tx_q *tx_queue; 103571ff9e3dSClaudiu Manoil struct gfar_priv_rx_q *rx_queue; 1036ec21e2ecSJeff Kirsher unsigned int tstat; 103771ff9e3dSClaudiu Manoil unsigned int rstat; 103871ff9e3dSClaudiu Manoil 103971ff9e3dSClaudiu Manoil struct gfar_private *priv; 1040ee873fdaSClaudiu Manoil unsigned long num_tx_queues; 1041ee873fdaSClaudiu Manoil unsigned long tx_bit_map; 104271ff9e3dSClaudiu Manoil unsigned long num_rx_queues; 104371ff9e3dSClaudiu Manoil unsigned long rx_bit_map; 1044ec21e2ecSJeff Kirsher 1045ee873fdaSClaudiu Manoil struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1046ec21e2ecSJeff Kirsher }; 1047ec21e2ecSJeff Kirsher 1048ee873fdaSClaudiu Manoil #define gfar_irq(grp, ID) \ 1049ee873fdaSClaudiu Manoil ((grp)->irqinfo[GFAR_##ID]) 1050ee873fdaSClaudiu Manoil 1051ec21e2ecSJeff Kirsher enum gfar_errata { 1052ec21e2ecSJeff Kirsher GFAR_ERRATA_74 = 0x01, 1053ec21e2ecSJeff Kirsher GFAR_ERRATA_76 = 0x02, 1054ec21e2ecSJeff Kirsher GFAR_ERRATA_A002 = 0x04, 1055ec21e2ecSJeff Kirsher GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1056ec21e2ecSJeff Kirsher }; 1057ec21e2ecSJeff Kirsher 10580851133bSClaudiu Manoil enum gfar_dev_state { 10590851133bSClaudiu Manoil GFAR_DOWN = 1, 10600851133bSClaudiu Manoil GFAR_RESETTING 10610851133bSClaudiu Manoil }; 10620851133bSClaudiu Manoil 1063ec21e2ecSJeff Kirsher /* Struct stolen almost completely (and shamelessly) from the FCC enet source 1064ec21e2ecSJeff Kirsher * (Ok, that's not so true anymore, but there is a family resemblance) 1065ec21e2ecSJeff Kirsher * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1066ec21e2ecSJeff Kirsher * and tx_bd_base always point to the currently available buffer. 1067ec21e2ecSJeff Kirsher * The dirty_tx tracks the current buffer that is being sent by the 1068ec21e2ecSJeff Kirsher * controller. The cur_tx and dirty_tx are equal under both completely 1069ec21e2ecSJeff Kirsher * empty and completely full conditions. The empty/ready indicator in 1070ec21e2ecSJeff Kirsher * the buffer descriptor determines the actual condition. 1071ec21e2ecSJeff Kirsher */ 1072ec21e2ecSJeff Kirsher struct gfar_private { 1073b597d20dSClaudiu Manoil struct device *dev; 1074b597d20dSClaudiu Manoil struct net_device *ndev; 1075b597d20dSClaudiu Manoil enum gfar_errata errata; 1076b597d20dSClaudiu Manoil 1077ba779711SClaudiu Manoil u16 uses_rxfcb; 1078b597d20dSClaudiu Manoil u16 padding; 107971ff9e3dSClaudiu Manoil u32 device_flags; 1080b597d20dSClaudiu Manoil 1081b597d20dSClaudiu Manoil /* HW time stamping enabled flag */ 1082b597d20dSClaudiu Manoil int hwts_rx_en; 1083b597d20dSClaudiu Manoil int hwts_tx_en; 1084b597d20dSClaudiu Manoil 1085b597d20dSClaudiu Manoil struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1086b597d20dSClaudiu Manoil struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1087b597d20dSClaudiu Manoil struct gfar_priv_grp gfargrp[MAXGROUPS]; 1088b597d20dSClaudiu Manoil 10890851133bSClaudiu Manoil unsigned long state; 1090b597d20dSClaudiu Manoil 109171ff9e3dSClaudiu Manoil unsigned short mode; 1092b597d20dSClaudiu Manoil unsigned int num_tx_queues; 109371ff9e3dSClaudiu Manoil unsigned int num_rx_queues; 1094b597d20dSClaudiu Manoil unsigned int num_grps; 109545b679c9SMatei Pavaluca int tx_actual_en; 1096b597d20dSClaudiu Manoil 1097b597d20dSClaudiu Manoil /* Network Statistics */ 1098b597d20dSClaudiu Manoil struct gfar_extra_stats extra_stats; 1099b597d20dSClaudiu Manoil 1100b597d20dSClaudiu Manoil /* PHY stuff */ 1101b597d20dSClaudiu Manoil phy_interface_t interface; 1102b597d20dSClaudiu Manoil struct device_node *phy_node; 1103b597d20dSClaudiu Manoil struct device_node *tbi_node; 1104b597d20dSClaudiu Manoil struct mii_bus *mii_bus; 1105b597d20dSClaudiu Manoil int oldspeed; 1106b597d20dSClaudiu Manoil int oldduplex; 1107b597d20dSClaudiu Manoil int oldlink; 1108b597d20dSClaudiu Manoil 1109b597d20dSClaudiu Manoil uint32_t msg_enable; 1110b597d20dSClaudiu Manoil 1111b597d20dSClaudiu Manoil struct work_struct reset_task; 1112b597d20dSClaudiu Manoil 1113b597d20dSClaudiu Manoil struct platform_device *ofdev; 1114b597d20dSClaudiu Manoil unsigned char 1115b597d20dSClaudiu Manoil extended_hash:1, 1116b597d20dSClaudiu Manoil bd_stash_en:1, 1117b597d20dSClaudiu Manoil rx_filer_enable:1, 1118b597d20dSClaudiu Manoil /* Enable priorty based Tx scheduling in Hw */ 111923402bddSClaudiu Manoil prio_sched_en:1, 112023402bddSClaudiu Manoil /* Flow control flags */ 112123402bddSClaudiu Manoil pause_aneg_en:1, 112223402bddSClaudiu Manoil tx_pause_en:1, 112323402bddSClaudiu Manoil rx_pause_en:1; 1124ec21e2ecSJeff Kirsher 1125ec21e2ecSJeff Kirsher /* The total tx and rx ring size for the enabled queues */ 1126ec21e2ecSJeff Kirsher unsigned int total_tx_ring_size; 1127ec21e2ecSJeff Kirsher unsigned int total_rx_ring_size; 1128ec21e2ecSJeff Kirsher 112920862788SClaudiu Manoil u32 rqueue; 113020862788SClaudiu Manoil u32 tqueue; 113120862788SClaudiu Manoil 1132ec21e2ecSJeff Kirsher /* RX per device parameters */ 1133ec21e2ecSJeff Kirsher unsigned int rx_stash_size; 1134ec21e2ecSJeff Kirsher unsigned int rx_stash_index; 1135ec21e2ecSJeff Kirsher 1136ec21e2ecSJeff Kirsher u32 cur_filer_idx; 1137ec21e2ecSJeff Kirsher 1138ec21e2ecSJeff Kirsher /* RX queue filer rule set*/ 1139ec21e2ecSJeff Kirsher struct ethtool_rx_list rx_list; 1140ec21e2ecSJeff Kirsher struct mutex rx_queue_access; 1141ec21e2ecSJeff Kirsher 1142ec21e2ecSJeff Kirsher /* Hash registers and their width */ 1143ec21e2ecSJeff Kirsher u32 __iomem *hash_regs[16]; 1144ec21e2ecSJeff Kirsher int hash_width; 1145ec21e2ecSJeff Kirsher 11463e905b80SClaudiu Manoil /* wake-on-lan settings */ 11473e905b80SClaudiu Manoil u16 wol_opts; 11483e905b80SClaudiu Manoil u16 wol_supported; 11493e905b80SClaudiu Manoil 1150ec21e2ecSJeff Kirsher /*Filer table*/ 1151ec21e2ecSJeff Kirsher unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1152ec21e2ecSJeff Kirsher unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1153ec21e2ecSJeff Kirsher }; 1154ec21e2ecSJeff Kirsher 1155ec21e2ecSJeff Kirsher 1156ec21e2ecSJeff Kirsher static inline int gfar_has_errata(struct gfar_private *priv, 1157ec21e2ecSJeff Kirsher enum gfar_errata err) 1158ec21e2ecSJeff Kirsher { 1159ec21e2ecSJeff Kirsher return priv->errata & err; 1160ec21e2ecSJeff Kirsher } 1161ec21e2ecSJeff Kirsher 1162fb017472SKim Phillips static inline u32 gfar_read(unsigned __iomem *addr) 1163ec21e2ecSJeff Kirsher { 1164ec21e2ecSJeff Kirsher u32 val; 1165fb017472SKim Phillips val = ioread32be(addr); 1166ec21e2ecSJeff Kirsher return val; 1167ec21e2ecSJeff Kirsher } 1168ec21e2ecSJeff Kirsher 1169fb017472SKim Phillips static inline void gfar_write(unsigned __iomem *addr, u32 val) 1170ec21e2ecSJeff Kirsher { 1171fb017472SKim Phillips iowrite32be(val, addr); 1172ec21e2ecSJeff Kirsher } 1173ec21e2ecSJeff Kirsher 1174ec21e2ecSJeff Kirsher static inline void gfar_write_filer(struct gfar_private *priv, 1175ec21e2ecSJeff Kirsher unsigned int far, unsigned int fcr, unsigned int fpr) 1176ec21e2ecSJeff Kirsher { 1177ec21e2ecSJeff Kirsher struct gfar __iomem *regs = priv->gfargrp[0].regs; 1178ec21e2ecSJeff Kirsher 1179ec21e2ecSJeff Kirsher gfar_write(®s->rqfar, far); 1180ec21e2ecSJeff Kirsher gfar_write(®s->rqfcr, fcr); 1181ec21e2ecSJeff Kirsher gfar_write(®s->rqfpr, fpr); 1182ec21e2ecSJeff Kirsher } 1183ec21e2ecSJeff Kirsher 1184ec21e2ecSJeff Kirsher static inline void gfar_read_filer(struct gfar_private *priv, 1185ec21e2ecSJeff Kirsher unsigned int far, unsigned int *fcr, unsigned int *fpr) 1186ec21e2ecSJeff Kirsher { 1187ec21e2ecSJeff Kirsher struct gfar __iomem *regs = priv->gfargrp[0].regs; 1188ec21e2ecSJeff Kirsher 1189ec21e2ecSJeff Kirsher gfar_write(®s->rqfar, far); 1190ec21e2ecSJeff Kirsher *fcr = gfar_read(®s->rqfcr); 1191ec21e2ecSJeff Kirsher *fpr = gfar_read(®s->rqfpr); 1192ec21e2ecSJeff Kirsher } 1193ec21e2ecSJeff Kirsher 119420862788SClaudiu Manoil static inline void gfar_write_isrg(struct gfar_private *priv) 119520862788SClaudiu Manoil { 119620862788SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 119720862788SClaudiu Manoil u32 __iomem *baddr = ®s->isrg0; 119820862788SClaudiu Manoil u32 isrg = 0; 119920862788SClaudiu Manoil int grp_idx, i; 120020862788SClaudiu Manoil 120120862788SClaudiu Manoil for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 120220862788SClaudiu Manoil struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; 120320862788SClaudiu Manoil 120420862788SClaudiu Manoil for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 120520862788SClaudiu Manoil isrg |= (ISRG_RR0 >> i); 120620862788SClaudiu Manoil } 120720862788SClaudiu Manoil 120820862788SClaudiu Manoil for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 120920862788SClaudiu Manoil isrg |= (ISRG_TR0 >> i); 121020862788SClaudiu Manoil } 121120862788SClaudiu Manoil 121220862788SClaudiu Manoil gfar_write(baddr, isrg); 121320862788SClaudiu Manoil 121420862788SClaudiu Manoil baddr++; 121520862788SClaudiu Manoil isrg = 0; 121620862788SClaudiu Manoil } 121720862788SClaudiu Manoil } 121820862788SClaudiu Manoil 1219a4feee89SClaudiu Manoil static inline int gfar_is_dma_stopped(struct gfar_private *priv) 1220a4feee89SClaudiu Manoil { 1221a4feee89SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 1222a4feee89SClaudiu Manoil 1223a4feee89SClaudiu Manoil return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == 1224a4feee89SClaudiu Manoil (IEVENT_GRSC | IEVENT_GTSC)); 1225a4feee89SClaudiu Manoil } 1226a4feee89SClaudiu Manoil 1227a4feee89SClaudiu Manoil static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) 1228a4feee89SClaudiu Manoil { 1229a4feee89SClaudiu Manoil struct gfar __iomem *regs = priv->gfargrp[0].regs; 1230a4feee89SClaudiu Manoil 1231a4feee89SClaudiu Manoil return gfar_read(®s->ievent) & IEVENT_GRSC; 1232a4feee89SClaudiu Manoil } 1233a4feee89SClaudiu Manoil 1234d55398baSClaudiu Manoil static inline void gfar_wmb(void) 1235d55398baSClaudiu Manoil { 1236d55398baSClaudiu Manoil #if defined(CONFIG_PPC) 1237d55398baSClaudiu Manoil /* The powerpc-specific eieio() is used, as wmb() has too strong 1238d55398baSClaudiu Manoil * semantics (it requires synchronization between cacheable and 1239d55398baSClaudiu Manoil * uncacheable mappings, which eieio() doesn't provide and which we 1240d55398baSClaudiu Manoil * don't need), thus requiring a more expensive sync instruction. At 1241d55398baSClaudiu Manoil * some point, the set of architecture-independent barrier functions 1242d55398baSClaudiu Manoil * should be expanded to include weaker barriers. 1243d55398baSClaudiu Manoil */ 1244d55398baSClaudiu Manoil eieio(); 1245d55398baSClaudiu Manoil #else 1246d55398baSClaudiu Manoil wmb(); /* order write acesses for BD (or FCB) fields */ 1247d55398baSClaudiu Manoil #endif 1248d55398baSClaudiu Manoil } 1249d55398baSClaudiu Manoil 1250a7312d58SClaudiu Manoil static inline void gfar_clear_txbd_status(struct txbd8 *bdp) 1251a7312d58SClaudiu Manoil { 1252a7312d58SClaudiu Manoil u32 lstatus = be32_to_cpu(bdp->lstatus); 1253a7312d58SClaudiu Manoil 1254a7312d58SClaudiu Manoil lstatus &= BD_LFLAG(TXBD_WRAP); 1255a7312d58SClaudiu Manoil bdp->lstatus = cpu_to_be32(lstatus); 1256a7312d58SClaudiu Manoil } 1257a7312d58SClaudiu Manoil 125876f31e8bSClaudiu Manoil static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq) 125976f31e8bSClaudiu Manoil { 126076f31e8bSClaudiu Manoil if (rxq->next_to_clean > rxq->next_to_use) 126176f31e8bSClaudiu Manoil return rxq->next_to_clean - rxq->next_to_use - 1; 126276f31e8bSClaudiu Manoil 126376f31e8bSClaudiu Manoil return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1; 126476f31e8bSClaudiu Manoil } 126576f31e8bSClaudiu Manoil 1266b4b67f26SScott Wood static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq) 126776f31e8bSClaudiu Manoil { 1268b4b67f26SScott Wood struct rxbd8 *bdp; 1269b4b67f26SScott Wood u32 bdp_dma; 127076f31e8bSClaudiu Manoil int i; 127176f31e8bSClaudiu Manoil 127276f31e8bSClaudiu Manoil i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1; 1273b4b67f26SScott Wood bdp = &rxq->rx_bd_base[i]; 1274b4b67f26SScott Wood bdp_dma = lower_32_bits(rxq->rx_bd_dma_base); 1275b4b67f26SScott Wood bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base; 127676f31e8bSClaudiu Manoil 1277b4b67f26SScott Wood return bdp_dma; 127876f31e8bSClaudiu Manoil } 127976f31e8bSClaudiu Manoil 1280bddb2d9aSJoe Perches int startup_gfar(struct net_device *dev); 1281bddb2d9aSJoe Perches void stop_gfar(struct net_device *dev); 12820851133bSClaudiu Manoil void gfar_mac_reset(struct gfar_private *priv); 1283c8f44affSMichał Mirosław int gfar_set_features(struct net_device *dev, netdev_features_t features); 1284ec21e2ecSJeff Kirsher 1285ec21e2ecSJeff Kirsher extern const struct ethtool_ops gfar_ethtool_ops; 1286ec21e2ecSJeff Kirsher 1287ec21e2ecSJeff Kirsher #define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1288ec21e2ecSJeff Kirsher 1289ec21e2ecSJeff Kirsher #define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1290ec21e2ecSJeff Kirsher #define RQFCR_PID_L4P_MASK 0xFFFFFF00 1291ec21e2ecSJeff Kirsher #define RQFCR_PID_VID_MASK 0xFFFFF000 1292ec21e2ecSJeff Kirsher #define RQFCR_PID_PORT_MASK 0xFFFF0000 1293ec21e2ecSJeff Kirsher #define RQFCR_PID_MAC_MASK 0xFF000000 1294ec21e2ecSJeff Kirsher 1295ec21e2ecSJeff Kirsher /* Represents a receive filer table entry */ 1296ec21e2ecSJeff Kirsher struct gfar_filer_entry { 1297ec21e2ecSJeff Kirsher u32 ctrl; 1298ec21e2ecSJeff Kirsher u32 prop; 1299ec21e2ecSJeff Kirsher }; 1300ec21e2ecSJeff Kirsher 1301ec21e2ecSJeff Kirsher 1302ec21e2ecSJeff Kirsher /* The 20 additional entries are a shadow for one extra element */ 1303ec21e2ecSJeff Kirsher struct filer_table { 1304ec21e2ecSJeff Kirsher u32 index; 1305ec21e2ecSJeff Kirsher struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1306ec21e2ecSJeff Kirsher }; 1307ec21e2ecSJeff Kirsher 1308ec21e2ecSJeff Kirsher #endif /* __GIANFAR_H */ 1309