1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/delay.h> 74 #include <linux/netdevice.h> 75 #include <linux/etherdevice.h> 76 #include <linux/skbuff.h> 77 #include <linux/if_vlan.h> 78 #include <linux/spinlock.h> 79 #include <linux/mm.h> 80 #include <linux/of_address.h> 81 #include <linux/of_irq.h> 82 #include <linux/of_mdio.h> 83 #include <linux/of_platform.h> 84 #include <linux/ip.h> 85 #include <linux/tcp.h> 86 #include <linux/udp.h> 87 #include <linux/in.h> 88 #include <linux/net_tstamp.h> 89 90 #include <asm/io.h> 91 #ifdef CONFIG_PPC 92 #include <asm/reg.h> 93 #include <asm/mpc85xx.h> 94 #endif 95 #include <asm/irq.h> 96 #include <asm/uaccess.h> 97 #include <linux/module.h> 98 #include <linux/dma-mapping.h> 99 #include <linux/crc32.h> 100 #include <linux/mii.h> 101 #include <linux/phy.h> 102 #include <linux/phy_fixed.h> 103 #include <linux/of.h> 104 #include <linux/of_net.h> 105 #include <linux/of_address.h> 106 #include <linux/of_irq.h> 107 108 #include "gianfar.h" 109 110 #define TX_TIMEOUT (1*HZ) 111 112 const char gfar_driver_version[] = "1.3"; 113 114 static int gfar_enet_open(struct net_device *dev); 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 116 static void gfar_reset_task(struct work_struct *work); 117 static void gfar_timeout(struct net_device *dev); 118 static int gfar_close(struct net_device *dev); 119 struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr); 120 static int gfar_set_mac_address(struct net_device *dev); 121 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 122 static irqreturn_t gfar_error(int irq, void *dev_id); 123 static irqreturn_t gfar_transmit(int irq, void *dev_id); 124 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 125 static void adjust_link(struct net_device *dev); 126 static noinline void gfar_update_link_state(struct gfar_private *priv); 127 static int init_phy(struct net_device *dev); 128 static int gfar_probe(struct platform_device *ofdev); 129 static int gfar_remove(struct platform_device *ofdev); 130 static void free_skb_resources(struct gfar_private *priv); 131 static void gfar_set_multi(struct net_device *dev); 132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 133 static void gfar_configure_serdes(struct net_device *dev); 134 static int gfar_poll_rx(struct napi_struct *napi, int budget); 135 static int gfar_poll_tx(struct napi_struct *napi, int budget); 136 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget); 137 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget); 138 #ifdef CONFIG_NET_POLL_CONTROLLER 139 static void gfar_netpoll(struct net_device *dev); 140 #endif 141 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 142 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 143 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 144 int amount_pull, struct napi_struct *napi); 145 static void gfar_halt_nodisable(struct gfar_private *priv); 146 static void gfar_clear_exact_match(struct net_device *dev); 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 148 const u8 *addr); 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 150 151 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 153 MODULE_LICENSE("GPL"); 154 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 156 dma_addr_t buf) 157 { 158 u32 lstatus; 159 160 bdp->bufPtr = buf; 161 162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 164 lstatus |= BD_LFLAG(RXBD_WRAP); 165 166 gfar_wmb(); 167 168 bdp->lstatus = lstatus; 169 } 170 171 static int gfar_init_bds(struct net_device *ndev) 172 { 173 struct gfar_private *priv = netdev_priv(ndev); 174 struct gfar __iomem *regs = priv->gfargrp[0].regs; 175 struct gfar_priv_tx_q *tx_queue = NULL; 176 struct gfar_priv_rx_q *rx_queue = NULL; 177 struct txbd8 *txbdp; 178 struct rxbd8 *rxbdp; 179 u32 *rfbptr; 180 int i, j; 181 dma_addr_t bufaddr; 182 183 for (i = 0; i < priv->num_tx_queues; i++) { 184 tx_queue = priv->tx_queue[i]; 185 /* Initialize some variables in our dev structure */ 186 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 187 tx_queue->dirty_tx = tx_queue->tx_bd_base; 188 tx_queue->cur_tx = tx_queue->tx_bd_base; 189 tx_queue->skb_curtx = 0; 190 tx_queue->skb_dirtytx = 0; 191 192 /* Initialize Transmit Descriptor Ring */ 193 txbdp = tx_queue->tx_bd_base; 194 for (j = 0; j < tx_queue->tx_ring_size; j++) { 195 txbdp->lstatus = 0; 196 txbdp->bufPtr = 0; 197 txbdp++; 198 } 199 200 /* Set the last descriptor in the ring to indicate wrap */ 201 txbdp--; 202 txbdp->status |= TXBD_WRAP; 203 } 204 205 rfbptr = ®s->rfbptr0; 206 for (i = 0; i < priv->num_rx_queues; i++) { 207 rx_queue = priv->rx_queue[i]; 208 rx_queue->cur_rx = rx_queue->rx_bd_base; 209 rx_queue->skb_currx = 0; 210 rxbdp = rx_queue->rx_bd_base; 211 212 for (j = 0; j < rx_queue->rx_ring_size; j++) { 213 struct sk_buff *skb = rx_queue->rx_skbuff[j]; 214 215 if (skb) { 216 bufaddr = rxbdp->bufPtr; 217 } else { 218 skb = gfar_new_skb(ndev, &bufaddr); 219 if (!skb) { 220 netdev_err(ndev, "Can't allocate RX buffers\n"); 221 return -ENOMEM; 222 } 223 rx_queue->rx_skbuff[j] = skb; 224 } 225 226 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr); 227 rxbdp++; 228 } 229 230 rx_queue->rfbptr = rfbptr; 231 rfbptr += 2; 232 } 233 234 return 0; 235 } 236 237 static int gfar_alloc_skb_resources(struct net_device *ndev) 238 { 239 void *vaddr; 240 dma_addr_t addr; 241 int i, j, k; 242 struct gfar_private *priv = netdev_priv(ndev); 243 struct device *dev = priv->dev; 244 struct gfar_priv_tx_q *tx_queue = NULL; 245 struct gfar_priv_rx_q *rx_queue = NULL; 246 247 priv->total_tx_ring_size = 0; 248 for (i = 0; i < priv->num_tx_queues; i++) 249 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 250 251 priv->total_rx_ring_size = 0; 252 for (i = 0; i < priv->num_rx_queues; i++) 253 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 254 255 /* Allocate memory for the buffer descriptors */ 256 vaddr = dma_alloc_coherent(dev, 257 (priv->total_tx_ring_size * 258 sizeof(struct txbd8)) + 259 (priv->total_rx_ring_size * 260 sizeof(struct rxbd8)), 261 &addr, GFP_KERNEL); 262 if (!vaddr) 263 return -ENOMEM; 264 265 for (i = 0; i < priv->num_tx_queues; i++) { 266 tx_queue = priv->tx_queue[i]; 267 tx_queue->tx_bd_base = vaddr; 268 tx_queue->tx_bd_dma_base = addr; 269 tx_queue->dev = ndev; 270 /* enet DMA only understands physical addresses */ 271 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 272 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 273 } 274 275 /* Start the rx descriptor ring where the tx ring leaves off */ 276 for (i = 0; i < priv->num_rx_queues; i++) { 277 rx_queue = priv->rx_queue[i]; 278 rx_queue->rx_bd_base = vaddr; 279 rx_queue->rx_bd_dma_base = addr; 280 rx_queue->dev = ndev; 281 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 282 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 283 } 284 285 /* Setup the skbuff rings */ 286 for (i = 0; i < priv->num_tx_queues; i++) { 287 tx_queue = priv->tx_queue[i]; 288 tx_queue->tx_skbuff = 289 kmalloc_array(tx_queue->tx_ring_size, 290 sizeof(*tx_queue->tx_skbuff), 291 GFP_KERNEL); 292 if (!tx_queue->tx_skbuff) 293 goto cleanup; 294 295 for (k = 0; k < tx_queue->tx_ring_size; k++) 296 tx_queue->tx_skbuff[k] = NULL; 297 } 298 299 for (i = 0; i < priv->num_rx_queues; i++) { 300 rx_queue = priv->rx_queue[i]; 301 rx_queue->rx_skbuff = 302 kmalloc_array(rx_queue->rx_ring_size, 303 sizeof(*rx_queue->rx_skbuff), 304 GFP_KERNEL); 305 if (!rx_queue->rx_skbuff) 306 goto cleanup; 307 308 for (j = 0; j < rx_queue->rx_ring_size; j++) 309 rx_queue->rx_skbuff[j] = NULL; 310 } 311 312 if (gfar_init_bds(ndev)) 313 goto cleanup; 314 315 return 0; 316 317 cleanup: 318 free_skb_resources(priv); 319 return -ENOMEM; 320 } 321 322 static void gfar_init_tx_rx_base(struct gfar_private *priv) 323 { 324 struct gfar __iomem *regs = priv->gfargrp[0].regs; 325 u32 __iomem *baddr; 326 int i; 327 328 baddr = ®s->tbase0; 329 for (i = 0; i < priv->num_tx_queues; i++) { 330 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 331 baddr += 2; 332 } 333 334 baddr = ®s->rbase0; 335 for (i = 0; i < priv->num_rx_queues; i++) { 336 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 337 baddr += 2; 338 } 339 } 340 341 static void gfar_init_rqprm(struct gfar_private *priv) 342 { 343 struct gfar __iomem *regs = priv->gfargrp[0].regs; 344 u32 __iomem *baddr; 345 int i; 346 347 baddr = ®s->rqprm0; 348 for (i = 0; i < priv->num_rx_queues; i++) { 349 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size | 350 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT)); 351 baddr++; 352 } 353 } 354 355 static void gfar_rx_buff_size_config(struct gfar_private *priv) 356 { 357 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN; 358 359 /* set this when rx hw offload (TOE) functions are being used */ 360 priv->uses_rxfcb = 0; 361 362 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) 363 priv->uses_rxfcb = 1; 364 365 if (priv->hwts_rx_en) 366 priv->uses_rxfcb = 1; 367 368 if (priv->uses_rxfcb) 369 frame_size += GMAC_FCB_LEN; 370 371 frame_size += priv->padding; 372 373 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + 374 INCREMENTAL_BUFFER_SIZE; 375 376 priv->rx_buffer_size = frame_size; 377 } 378 379 static void gfar_mac_rx_config(struct gfar_private *priv) 380 { 381 struct gfar __iomem *regs = priv->gfargrp[0].regs; 382 u32 rctrl = 0; 383 384 if (priv->rx_filer_enable) { 385 rctrl |= RCTRL_FILREN; 386 /* Program the RIR0 reg with the required distribution */ 387 if (priv->poll_mode == GFAR_SQ_POLLING) 388 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0); 389 else /* GFAR_MQ_POLLING */ 390 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0); 391 } 392 393 /* Restore PROMISC mode */ 394 if (priv->ndev->flags & IFF_PROMISC) 395 rctrl |= RCTRL_PROM; 396 397 if (priv->ndev->features & NETIF_F_RXCSUM) 398 rctrl |= RCTRL_CHECKSUMMING; 399 400 if (priv->extended_hash) 401 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN; 402 403 if (priv->padding) { 404 rctrl &= ~RCTRL_PAL_MASK; 405 rctrl |= RCTRL_PADDING(priv->padding); 406 } 407 408 /* Enable HW time stamping if requested from user space */ 409 if (priv->hwts_rx_en) 410 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 411 412 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) 413 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 414 415 /* Clear the LFC bit */ 416 gfar_write(®s->rctrl, rctrl); 417 /* Init flow control threshold values */ 418 gfar_init_rqprm(priv); 419 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL); 420 rctrl |= RCTRL_LFC; 421 422 /* Init rctrl based on our settings */ 423 gfar_write(®s->rctrl, rctrl); 424 } 425 426 static void gfar_mac_tx_config(struct gfar_private *priv) 427 { 428 struct gfar __iomem *regs = priv->gfargrp[0].regs; 429 u32 tctrl = 0; 430 431 if (priv->ndev->features & NETIF_F_IP_CSUM) 432 tctrl |= TCTRL_INIT_CSUM; 433 434 if (priv->prio_sched_en) 435 tctrl |= TCTRL_TXSCHED_PRIO; 436 else { 437 tctrl |= TCTRL_TXSCHED_WRRS; 438 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 439 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 440 } 441 442 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX) 443 tctrl |= TCTRL_VLINS; 444 445 gfar_write(®s->tctrl, tctrl); 446 } 447 448 static void gfar_configure_coalescing(struct gfar_private *priv, 449 unsigned long tx_mask, unsigned long rx_mask) 450 { 451 struct gfar __iomem *regs = priv->gfargrp[0].regs; 452 u32 __iomem *baddr; 453 454 if (priv->mode == MQ_MG_MODE) { 455 int i = 0; 456 457 baddr = ®s->txic0; 458 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 459 gfar_write(baddr + i, 0); 460 if (likely(priv->tx_queue[i]->txcoalescing)) 461 gfar_write(baddr + i, priv->tx_queue[i]->txic); 462 } 463 464 baddr = ®s->rxic0; 465 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 466 gfar_write(baddr + i, 0); 467 if (likely(priv->rx_queue[i]->rxcoalescing)) 468 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 469 } 470 } else { 471 /* Backward compatible case -- even if we enable 472 * multiple queues, there's only single reg to program 473 */ 474 gfar_write(®s->txic, 0); 475 if (likely(priv->tx_queue[0]->txcoalescing)) 476 gfar_write(®s->txic, priv->tx_queue[0]->txic); 477 478 gfar_write(®s->rxic, 0); 479 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 480 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 481 } 482 } 483 484 void gfar_configure_coalescing_all(struct gfar_private *priv) 485 { 486 gfar_configure_coalescing(priv, 0xFF, 0xFF); 487 } 488 489 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 490 { 491 struct gfar_private *priv = netdev_priv(dev); 492 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 493 unsigned long tx_packets = 0, tx_bytes = 0; 494 int i; 495 496 for (i = 0; i < priv->num_rx_queues; i++) { 497 rx_packets += priv->rx_queue[i]->stats.rx_packets; 498 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 499 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 500 } 501 502 dev->stats.rx_packets = rx_packets; 503 dev->stats.rx_bytes = rx_bytes; 504 dev->stats.rx_dropped = rx_dropped; 505 506 for (i = 0; i < priv->num_tx_queues; i++) { 507 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 508 tx_packets += priv->tx_queue[i]->stats.tx_packets; 509 } 510 511 dev->stats.tx_bytes = tx_bytes; 512 dev->stats.tx_packets = tx_packets; 513 514 return &dev->stats; 515 } 516 517 static const struct net_device_ops gfar_netdev_ops = { 518 .ndo_open = gfar_enet_open, 519 .ndo_start_xmit = gfar_start_xmit, 520 .ndo_stop = gfar_close, 521 .ndo_change_mtu = gfar_change_mtu, 522 .ndo_set_features = gfar_set_features, 523 .ndo_set_rx_mode = gfar_set_multi, 524 .ndo_tx_timeout = gfar_timeout, 525 .ndo_do_ioctl = gfar_ioctl, 526 .ndo_get_stats = gfar_get_stats, 527 .ndo_set_mac_address = eth_mac_addr, 528 .ndo_validate_addr = eth_validate_addr, 529 #ifdef CONFIG_NET_POLL_CONTROLLER 530 .ndo_poll_controller = gfar_netpoll, 531 #endif 532 }; 533 534 static void gfar_ints_disable(struct gfar_private *priv) 535 { 536 int i; 537 for (i = 0; i < priv->num_grps; i++) { 538 struct gfar __iomem *regs = priv->gfargrp[i].regs; 539 /* Clear IEVENT */ 540 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 541 542 /* Initialize IMASK */ 543 gfar_write(®s->imask, IMASK_INIT_CLEAR); 544 } 545 } 546 547 static void gfar_ints_enable(struct gfar_private *priv) 548 { 549 int i; 550 for (i = 0; i < priv->num_grps; i++) { 551 struct gfar __iomem *regs = priv->gfargrp[i].regs; 552 /* Unmask the interrupts we look for */ 553 gfar_write(®s->imask, IMASK_DEFAULT); 554 } 555 } 556 557 void lock_tx_qs(struct gfar_private *priv) 558 { 559 int i; 560 561 for (i = 0; i < priv->num_tx_queues; i++) 562 spin_lock(&priv->tx_queue[i]->txlock); 563 } 564 565 void unlock_tx_qs(struct gfar_private *priv) 566 { 567 int i; 568 569 for (i = 0; i < priv->num_tx_queues; i++) 570 spin_unlock(&priv->tx_queue[i]->txlock); 571 } 572 573 static int gfar_alloc_tx_queues(struct gfar_private *priv) 574 { 575 int i; 576 577 for (i = 0; i < priv->num_tx_queues; i++) { 578 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 579 GFP_KERNEL); 580 if (!priv->tx_queue[i]) 581 return -ENOMEM; 582 583 priv->tx_queue[i]->tx_skbuff = NULL; 584 priv->tx_queue[i]->qindex = i; 585 priv->tx_queue[i]->dev = priv->ndev; 586 spin_lock_init(&(priv->tx_queue[i]->txlock)); 587 } 588 return 0; 589 } 590 591 static int gfar_alloc_rx_queues(struct gfar_private *priv) 592 { 593 int i; 594 595 for (i = 0; i < priv->num_rx_queues; i++) { 596 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 597 GFP_KERNEL); 598 if (!priv->rx_queue[i]) 599 return -ENOMEM; 600 601 priv->rx_queue[i]->rx_skbuff = NULL; 602 priv->rx_queue[i]->qindex = i; 603 priv->rx_queue[i]->dev = priv->ndev; 604 } 605 return 0; 606 } 607 608 static void gfar_free_tx_queues(struct gfar_private *priv) 609 { 610 int i; 611 612 for (i = 0; i < priv->num_tx_queues; i++) 613 kfree(priv->tx_queue[i]); 614 } 615 616 static void gfar_free_rx_queues(struct gfar_private *priv) 617 { 618 int i; 619 620 for (i = 0; i < priv->num_rx_queues; i++) 621 kfree(priv->rx_queue[i]); 622 } 623 624 static void unmap_group_regs(struct gfar_private *priv) 625 { 626 int i; 627 628 for (i = 0; i < MAXGROUPS; i++) 629 if (priv->gfargrp[i].regs) 630 iounmap(priv->gfargrp[i].regs); 631 } 632 633 static void free_gfar_dev(struct gfar_private *priv) 634 { 635 int i, j; 636 637 for (i = 0; i < priv->num_grps; i++) 638 for (j = 0; j < GFAR_NUM_IRQS; j++) { 639 kfree(priv->gfargrp[i].irqinfo[j]); 640 priv->gfargrp[i].irqinfo[j] = NULL; 641 } 642 643 free_netdev(priv->ndev); 644 } 645 646 static void disable_napi(struct gfar_private *priv) 647 { 648 int i; 649 650 for (i = 0; i < priv->num_grps; i++) { 651 napi_disable(&priv->gfargrp[i].napi_rx); 652 napi_disable(&priv->gfargrp[i].napi_tx); 653 } 654 } 655 656 static void enable_napi(struct gfar_private *priv) 657 { 658 int i; 659 660 for (i = 0; i < priv->num_grps; i++) { 661 napi_enable(&priv->gfargrp[i].napi_rx); 662 napi_enable(&priv->gfargrp[i].napi_tx); 663 } 664 } 665 666 static int gfar_parse_group(struct device_node *np, 667 struct gfar_private *priv, const char *model) 668 { 669 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 670 int i; 671 672 for (i = 0; i < GFAR_NUM_IRQS; i++) { 673 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 674 GFP_KERNEL); 675 if (!grp->irqinfo[i]) 676 return -ENOMEM; 677 } 678 679 grp->regs = of_iomap(np, 0); 680 if (!grp->regs) 681 return -ENOMEM; 682 683 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 684 685 /* If we aren't the FEC we have multiple interrupts */ 686 if (model && strcasecmp(model, "FEC")) { 687 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 688 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 689 if (gfar_irq(grp, TX)->irq == NO_IRQ || 690 gfar_irq(grp, RX)->irq == NO_IRQ || 691 gfar_irq(grp, ER)->irq == NO_IRQ) 692 return -EINVAL; 693 } 694 695 grp->priv = priv; 696 spin_lock_init(&grp->grplock); 697 if (priv->mode == MQ_MG_MODE) { 698 u32 *rxq_mask, *txq_mask; 699 rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); 700 txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); 701 702 if (priv->poll_mode == GFAR_SQ_POLLING) { 703 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */ 704 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 705 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps); 706 } else { /* GFAR_MQ_POLLING */ 707 grp->rx_bit_map = rxq_mask ? 708 *rxq_mask : (DEFAULT_MAPPING >> priv->num_grps); 709 grp->tx_bit_map = txq_mask ? 710 *txq_mask : (DEFAULT_MAPPING >> priv->num_grps); 711 } 712 } else { 713 grp->rx_bit_map = 0xFF; 714 grp->tx_bit_map = 0xFF; 715 } 716 717 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses 718 * right to left, so we need to revert the 8 bits to get the q index 719 */ 720 grp->rx_bit_map = bitrev8(grp->rx_bit_map); 721 grp->tx_bit_map = bitrev8(grp->tx_bit_map); 722 723 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 724 * also assign queues to groups 725 */ 726 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 727 if (!grp->rx_queue) 728 grp->rx_queue = priv->rx_queue[i]; 729 grp->num_rx_queues++; 730 grp->rstat |= (RSTAT_CLEAR_RHALT >> i); 731 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 732 priv->rx_queue[i]->grp = grp; 733 } 734 735 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 736 if (!grp->tx_queue) 737 grp->tx_queue = priv->tx_queue[i]; 738 grp->num_tx_queues++; 739 grp->tstat |= (TSTAT_CLEAR_THALT >> i); 740 priv->tqueue |= (TQUEUE_EN0 >> i); 741 priv->tx_queue[i]->grp = grp; 742 } 743 744 priv->num_grps++; 745 746 return 0; 747 } 748 749 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 750 { 751 const char *model; 752 const char *ctype; 753 const void *mac_addr; 754 int err = 0, i; 755 struct net_device *dev = NULL; 756 struct gfar_private *priv = NULL; 757 struct device_node *np = ofdev->dev.of_node; 758 struct device_node *child = NULL; 759 const u32 *stash; 760 const u32 *stash_len; 761 const u32 *stash_idx; 762 unsigned int num_tx_qs, num_rx_qs; 763 u32 *tx_queues, *rx_queues; 764 unsigned short mode, poll_mode; 765 766 if (!np || !of_device_is_available(np)) 767 return -ENODEV; 768 769 if (of_device_is_compatible(np, "fsl,etsec2")) { 770 mode = MQ_MG_MODE; 771 poll_mode = GFAR_SQ_POLLING; 772 } else { 773 mode = SQ_SG_MODE; 774 poll_mode = GFAR_SQ_POLLING; 775 } 776 777 /* parse the num of HW tx and rx queues */ 778 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); 779 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); 780 781 if (mode == SQ_SG_MODE) { 782 num_tx_qs = 1; 783 num_rx_qs = 1; 784 } else { /* MQ_MG_MODE */ 785 /* get the actual number of supported groups */ 786 unsigned int num_grps = of_get_available_child_count(np); 787 788 if (num_grps == 0 || num_grps > MAXGROUPS) { 789 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n", 790 num_grps); 791 pr_err("Cannot do alloc_etherdev, aborting\n"); 792 return -EINVAL; 793 } 794 795 if (poll_mode == GFAR_SQ_POLLING) { 796 num_tx_qs = num_grps; /* one txq per int group */ 797 num_rx_qs = num_grps; /* one rxq per int group */ 798 } else { /* GFAR_MQ_POLLING */ 799 num_tx_qs = tx_queues ? *tx_queues : 1; 800 num_rx_qs = rx_queues ? *rx_queues : 1; 801 } 802 } 803 804 if (num_tx_qs > MAX_TX_QS) { 805 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 806 num_tx_qs, MAX_TX_QS); 807 pr_err("Cannot do alloc_etherdev, aborting\n"); 808 return -EINVAL; 809 } 810 811 if (num_rx_qs > MAX_RX_QS) { 812 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 813 num_rx_qs, MAX_RX_QS); 814 pr_err("Cannot do alloc_etherdev, aborting\n"); 815 return -EINVAL; 816 } 817 818 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 819 dev = *pdev; 820 if (NULL == dev) 821 return -ENOMEM; 822 823 priv = netdev_priv(dev); 824 priv->ndev = dev; 825 826 priv->mode = mode; 827 priv->poll_mode = poll_mode; 828 829 priv->num_tx_queues = num_tx_qs; 830 netif_set_real_num_rx_queues(dev, num_rx_qs); 831 priv->num_rx_queues = num_rx_qs; 832 833 err = gfar_alloc_tx_queues(priv); 834 if (err) 835 goto tx_alloc_failed; 836 837 err = gfar_alloc_rx_queues(priv); 838 if (err) 839 goto rx_alloc_failed; 840 841 /* Init Rx queue filer rule set linked list */ 842 INIT_LIST_HEAD(&priv->rx_list.list); 843 priv->rx_list.count = 0; 844 mutex_init(&priv->rx_queue_access); 845 846 model = of_get_property(np, "model", NULL); 847 848 for (i = 0; i < MAXGROUPS; i++) 849 priv->gfargrp[i].regs = NULL; 850 851 /* Parse and initialize group specific information */ 852 if (priv->mode == MQ_MG_MODE) { 853 for_each_child_of_node(np, child) { 854 err = gfar_parse_group(child, priv, model); 855 if (err) 856 goto err_grp_init; 857 } 858 } else { /* SQ_SG_MODE */ 859 err = gfar_parse_group(np, priv, model); 860 if (err) 861 goto err_grp_init; 862 } 863 864 stash = of_get_property(np, "bd-stash", NULL); 865 866 if (stash) { 867 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 868 priv->bd_stash_en = 1; 869 } 870 871 stash_len = of_get_property(np, "rx-stash-len", NULL); 872 873 if (stash_len) 874 priv->rx_stash_size = *stash_len; 875 876 stash_idx = of_get_property(np, "rx-stash-idx", NULL); 877 878 if (stash_idx) 879 priv->rx_stash_index = *stash_idx; 880 881 if (stash_len || stash_idx) 882 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 883 884 mac_addr = of_get_mac_address(np); 885 886 if (mac_addr) 887 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 888 889 if (model && !strcasecmp(model, "TSEC")) 890 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 891 FSL_GIANFAR_DEV_HAS_COALESCE | 892 FSL_GIANFAR_DEV_HAS_RMON | 893 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 894 895 if (model && !strcasecmp(model, "eTSEC")) 896 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | 897 FSL_GIANFAR_DEV_HAS_COALESCE | 898 FSL_GIANFAR_DEV_HAS_RMON | 899 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 900 FSL_GIANFAR_DEV_HAS_CSUM | 901 FSL_GIANFAR_DEV_HAS_VLAN | 902 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 903 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 904 FSL_GIANFAR_DEV_HAS_TIMER; 905 906 ctype = of_get_property(np, "phy-connection-type", NULL); 907 908 /* We only care about rgmii-id. The rest are autodetected */ 909 if (ctype && !strcmp(ctype, "rgmii-id")) 910 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 911 else 912 priv->interface = PHY_INTERFACE_MODE_MII; 913 914 if (of_get_property(np, "fsl,magic-packet", NULL)) 915 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 916 917 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 918 919 /* In the case of a fixed PHY, the DT node associated 920 * to the PHY is the Ethernet MAC DT node. 921 */ 922 if (!priv->phy_node && of_phy_is_fixed_link(np)) { 923 err = of_phy_register_fixed_link(np); 924 if (err) 925 goto err_grp_init; 926 927 priv->phy_node = of_node_get(np); 928 } 929 930 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 931 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 932 933 return 0; 934 935 err_grp_init: 936 unmap_group_regs(priv); 937 rx_alloc_failed: 938 gfar_free_rx_queues(priv); 939 tx_alloc_failed: 940 gfar_free_tx_queues(priv); 941 free_gfar_dev(priv); 942 return err; 943 } 944 945 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 946 { 947 struct hwtstamp_config config; 948 struct gfar_private *priv = netdev_priv(netdev); 949 950 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 951 return -EFAULT; 952 953 /* reserved for future extensions */ 954 if (config.flags) 955 return -EINVAL; 956 957 switch (config.tx_type) { 958 case HWTSTAMP_TX_OFF: 959 priv->hwts_tx_en = 0; 960 break; 961 case HWTSTAMP_TX_ON: 962 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 963 return -ERANGE; 964 priv->hwts_tx_en = 1; 965 break; 966 default: 967 return -ERANGE; 968 } 969 970 switch (config.rx_filter) { 971 case HWTSTAMP_FILTER_NONE: 972 if (priv->hwts_rx_en) { 973 priv->hwts_rx_en = 0; 974 reset_gfar(netdev); 975 } 976 break; 977 default: 978 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 979 return -ERANGE; 980 if (!priv->hwts_rx_en) { 981 priv->hwts_rx_en = 1; 982 reset_gfar(netdev); 983 } 984 config.rx_filter = HWTSTAMP_FILTER_ALL; 985 break; 986 } 987 988 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 989 -EFAULT : 0; 990 } 991 992 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 993 { 994 struct hwtstamp_config config; 995 struct gfar_private *priv = netdev_priv(netdev); 996 997 config.flags = 0; 998 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 999 config.rx_filter = (priv->hwts_rx_en ? 1000 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 1001 1002 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1003 -EFAULT : 0; 1004 } 1005 1006 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1007 { 1008 struct gfar_private *priv = netdev_priv(dev); 1009 1010 if (!netif_running(dev)) 1011 return -EINVAL; 1012 1013 if (cmd == SIOCSHWTSTAMP) 1014 return gfar_hwtstamp_set(dev, rq); 1015 if (cmd == SIOCGHWTSTAMP) 1016 return gfar_hwtstamp_get(dev, rq); 1017 1018 if (!priv->phydev) 1019 return -ENODEV; 1020 1021 return phy_mii_ioctl(priv->phydev, rq, cmd); 1022 } 1023 1024 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 1025 u32 class) 1026 { 1027 u32 rqfpr = FPR_FILER_MASK; 1028 u32 rqfcr = 0x0; 1029 1030 rqfar--; 1031 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 1032 priv->ftp_rqfpr[rqfar] = rqfpr; 1033 priv->ftp_rqfcr[rqfar] = rqfcr; 1034 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1035 1036 rqfar--; 1037 rqfcr = RQFCR_CMP_NOMATCH; 1038 priv->ftp_rqfpr[rqfar] = rqfpr; 1039 priv->ftp_rqfcr[rqfar] = rqfcr; 1040 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1041 1042 rqfar--; 1043 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 1044 rqfpr = class; 1045 priv->ftp_rqfcr[rqfar] = rqfcr; 1046 priv->ftp_rqfpr[rqfar] = rqfpr; 1047 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1048 1049 rqfar--; 1050 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 1051 rqfpr = class; 1052 priv->ftp_rqfcr[rqfar] = rqfcr; 1053 priv->ftp_rqfpr[rqfar] = rqfpr; 1054 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1055 1056 return rqfar; 1057 } 1058 1059 static void gfar_init_filer_table(struct gfar_private *priv) 1060 { 1061 int i = 0x0; 1062 u32 rqfar = MAX_FILER_IDX; 1063 u32 rqfcr = 0x0; 1064 u32 rqfpr = FPR_FILER_MASK; 1065 1066 /* Default rule */ 1067 rqfcr = RQFCR_CMP_MATCH; 1068 priv->ftp_rqfcr[rqfar] = rqfcr; 1069 priv->ftp_rqfpr[rqfar] = rqfpr; 1070 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 1071 1072 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 1073 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 1074 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 1075 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 1076 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 1077 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 1078 1079 /* cur_filer_idx indicated the first non-masked rule */ 1080 priv->cur_filer_idx = rqfar; 1081 1082 /* Rest are masked rules */ 1083 rqfcr = RQFCR_CMP_NOMATCH; 1084 for (i = 0; i < rqfar; i++) { 1085 priv->ftp_rqfcr[i] = rqfcr; 1086 priv->ftp_rqfpr[i] = rqfpr; 1087 gfar_write_filer(priv, i, rqfcr, rqfpr); 1088 } 1089 } 1090 1091 #ifdef CONFIG_PPC 1092 static void __gfar_detect_errata_83xx(struct gfar_private *priv) 1093 { 1094 unsigned int pvr = mfspr(SPRN_PVR); 1095 unsigned int svr = mfspr(SPRN_SVR); 1096 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 1097 unsigned int rev = svr & 0xffff; 1098 1099 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 1100 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 1101 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1102 priv->errata |= GFAR_ERRATA_74; 1103 1104 /* MPC8313 and MPC837x all rev */ 1105 if ((pvr == 0x80850010 && mod == 0x80b0) || 1106 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 1107 priv->errata |= GFAR_ERRATA_76; 1108 1109 /* MPC8313 Rev < 2.0 */ 1110 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) 1111 priv->errata |= GFAR_ERRATA_12; 1112 } 1113 1114 static void __gfar_detect_errata_85xx(struct gfar_private *priv) 1115 { 1116 unsigned int svr = mfspr(SPRN_SVR); 1117 1118 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)) 1119 priv->errata |= GFAR_ERRATA_12; 1120 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) || 1121 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20))) 1122 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */ 1123 } 1124 #endif 1125 1126 static void gfar_detect_errata(struct gfar_private *priv) 1127 { 1128 struct device *dev = &priv->ofdev->dev; 1129 1130 /* no plans to fix */ 1131 priv->errata |= GFAR_ERRATA_A002; 1132 1133 #ifdef CONFIG_PPC 1134 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)) 1135 __gfar_detect_errata_85xx(priv); 1136 else /* non-mpc85xx parts, i.e. e300 core based */ 1137 __gfar_detect_errata_83xx(priv); 1138 #endif 1139 1140 if (priv->errata) 1141 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 1142 priv->errata); 1143 } 1144 1145 void gfar_mac_reset(struct gfar_private *priv) 1146 { 1147 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1148 u32 tempval; 1149 1150 /* Reset MAC layer */ 1151 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1152 1153 /* We need to delay at least 3 TX clocks */ 1154 udelay(3); 1155 1156 /* the soft reset bit is not self-resetting, so we need to 1157 * clear it before resuming normal operation 1158 */ 1159 gfar_write(®s->maccfg1, 0); 1160 1161 udelay(3); 1162 1163 /* Compute rx_buff_size based on config flags */ 1164 gfar_rx_buff_size_config(priv); 1165 1166 /* Initialize the max receive frame/buffer lengths */ 1167 gfar_write(®s->maxfrm, priv->rx_buffer_size); 1168 gfar_write(®s->mrblr, priv->rx_buffer_size); 1169 1170 /* Initialize the Minimum Frame Length Register */ 1171 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1172 1173 /* Initialize MACCFG2. */ 1174 tempval = MACCFG2_INIT_SETTINGS; 1175 1176 /* If the mtu is larger than the max size for standard 1177 * ethernet frames (ie, a jumbo frame), then set maccfg2 1178 * to allow huge frames, and to check the length 1179 */ 1180 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || 1181 gfar_has_errata(priv, GFAR_ERRATA_74)) 1182 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1183 1184 gfar_write(®s->maccfg2, tempval); 1185 1186 /* Clear mac addr hash registers */ 1187 gfar_write(®s->igaddr0, 0); 1188 gfar_write(®s->igaddr1, 0); 1189 gfar_write(®s->igaddr2, 0); 1190 gfar_write(®s->igaddr3, 0); 1191 gfar_write(®s->igaddr4, 0); 1192 gfar_write(®s->igaddr5, 0); 1193 gfar_write(®s->igaddr6, 0); 1194 gfar_write(®s->igaddr7, 0); 1195 1196 gfar_write(®s->gaddr0, 0); 1197 gfar_write(®s->gaddr1, 0); 1198 gfar_write(®s->gaddr2, 0); 1199 gfar_write(®s->gaddr3, 0); 1200 gfar_write(®s->gaddr4, 0); 1201 gfar_write(®s->gaddr5, 0); 1202 gfar_write(®s->gaddr6, 0); 1203 gfar_write(®s->gaddr7, 0); 1204 1205 if (priv->extended_hash) 1206 gfar_clear_exact_match(priv->ndev); 1207 1208 gfar_mac_rx_config(priv); 1209 1210 gfar_mac_tx_config(priv); 1211 1212 gfar_set_mac_address(priv->ndev); 1213 1214 gfar_set_multi(priv->ndev); 1215 1216 /* clear ievent and imask before configuring coalescing */ 1217 gfar_ints_disable(priv); 1218 1219 /* Configure the coalescing support */ 1220 gfar_configure_coalescing_all(priv); 1221 } 1222 1223 static void gfar_hw_init(struct gfar_private *priv) 1224 { 1225 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1226 u32 attrs; 1227 1228 /* Stop the DMA engine now, in case it was running before 1229 * (The firmware could have used it, and left it running). 1230 */ 1231 gfar_halt(priv); 1232 1233 gfar_mac_reset(priv); 1234 1235 /* Zero out the rmon mib registers if it has them */ 1236 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1237 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib)); 1238 1239 /* Mask off the CAM interrupts */ 1240 gfar_write(®s->rmon.cam1, 0xffffffff); 1241 gfar_write(®s->rmon.cam2, 0xffffffff); 1242 } 1243 1244 /* Initialize ECNTRL */ 1245 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1246 1247 /* Set the extraction length and index */ 1248 attrs = ATTRELI_EL(priv->rx_stash_size) | 1249 ATTRELI_EI(priv->rx_stash_index); 1250 1251 gfar_write(®s->attreli, attrs); 1252 1253 /* Start with defaults, and add stashing 1254 * depending on driver parameters 1255 */ 1256 attrs = ATTR_INIT_SETTINGS; 1257 1258 if (priv->bd_stash_en) 1259 attrs |= ATTR_BDSTASH; 1260 1261 if (priv->rx_stash_size != 0) 1262 attrs |= ATTR_BUFSTASH; 1263 1264 gfar_write(®s->attr, attrs); 1265 1266 /* FIFO configs */ 1267 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR); 1268 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE); 1269 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF); 1270 1271 /* Program the interrupt steering regs, only for MG devices */ 1272 if (priv->num_grps > 1) 1273 gfar_write_isrg(priv); 1274 } 1275 1276 static void gfar_init_addr_hash_table(struct gfar_private *priv) 1277 { 1278 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1279 1280 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1281 priv->extended_hash = 1; 1282 priv->hash_width = 9; 1283 1284 priv->hash_regs[0] = ®s->igaddr0; 1285 priv->hash_regs[1] = ®s->igaddr1; 1286 priv->hash_regs[2] = ®s->igaddr2; 1287 priv->hash_regs[3] = ®s->igaddr3; 1288 priv->hash_regs[4] = ®s->igaddr4; 1289 priv->hash_regs[5] = ®s->igaddr5; 1290 priv->hash_regs[6] = ®s->igaddr6; 1291 priv->hash_regs[7] = ®s->igaddr7; 1292 priv->hash_regs[8] = ®s->gaddr0; 1293 priv->hash_regs[9] = ®s->gaddr1; 1294 priv->hash_regs[10] = ®s->gaddr2; 1295 priv->hash_regs[11] = ®s->gaddr3; 1296 priv->hash_regs[12] = ®s->gaddr4; 1297 priv->hash_regs[13] = ®s->gaddr5; 1298 priv->hash_regs[14] = ®s->gaddr6; 1299 priv->hash_regs[15] = ®s->gaddr7; 1300 1301 } else { 1302 priv->extended_hash = 0; 1303 priv->hash_width = 8; 1304 1305 priv->hash_regs[0] = ®s->gaddr0; 1306 priv->hash_regs[1] = ®s->gaddr1; 1307 priv->hash_regs[2] = ®s->gaddr2; 1308 priv->hash_regs[3] = ®s->gaddr3; 1309 priv->hash_regs[4] = ®s->gaddr4; 1310 priv->hash_regs[5] = ®s->gaddr5; 1311 priv->hash_regs[6] = ®s->gaddr6; 1312 priv->hash_regs[7] = ®s->gaddr7; 1313 } 1314 } 1315 1316 /* Set up the ethernet device structure, private data, 1317 * and anything else we need before we start 1318 */ 1319 static int gfar_probe(struct platform_device *ofdev) 1320 { 1321 struct net_device *dev = NULL; 1322 struct gfar_private *priv = NULL; 1323 int err = 0, i; 1324 1325 err = gfar_of_init(ofdev, &dev); 1326 1327 if (err) 1328 return err; 1329 1330 priv = netdev_priv(dev); 1331 priv->ndev = dev; 1332 priv->ofdev = ofdev; 1333 priv->dev = &ofdev->dev; 1334 SET_NETDEV_DEV(dev, &ofdev->dev); 1335 1336 spin_lock_init(&priv->bflock); 1337 INIT_WORK(&priv->reset_task, gfar_reset_task); 1338 1339 platform_set_drvdata(ofdev, priv); 1340 1341 gfar_detect_errata(priv); 1342 1343 /* Set the dev->base_addr to the gfar reg region */ 1344 dev->base_addr = (unsigned long) priv->gfargrp[0].regs; 1345 1346 /* Fill in the dev structure */ 1347 dev->watchdog_timeo = TX_TIMEOUT; 1348 dev->mtu = 1500; 1349 dev->netdev_ops = &gfar_netdev_ops; 1350 dev->ethtool_ops = &gfar_ethtool_ops; 1351 1352 /* Register for napi ...We are registering NAPI for each grp */ 1353 for (i = 0; i < priv->num_grps; i++) { 1354 if (priv->poll_mode == GFAR_SQ_POLLING) { 1355 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1356 gfar_poll_rx_sq, GFAR_DEV_WEIGHT); 1357 netif_napi_add(dev, &priv->gfargrp[i].napi_tx, 1358 gfar_poll_tx_sq, 2); 1359 } else { 1360 netif_napi_add(dev, &priv->gfargrp[i].napi_rx, 1361 gfar_poll_rx, GFAR_DEV_WEIGHT); 1362 netif_napi_add(dev, &priv->gfargrp[i].napi_tx, 1363 gfar_poll_tx, 2); 1364 } 1365 } 1366 1367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1368 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1369 NETIF_F_RXCSUM; 1370 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1371 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1372 } 1373 1374 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1375 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1376 NETIF_F_HW_VLAN_CTAG_RX; 1377 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1378 } 1379 1380 gfar_init_addr_hash_table(priv); 1381 1382 /* Insert receive time stamps into padding alignment bytes */ 1383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1384 priv->padding = 8; 1385 1386 if (dev->features & NETIF_F_IP_CSUM || 1387 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1388 dev->needed_headroom = GMAC_FCB_LEN; 1389 1390 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 1391 1392 /* Initializing some of the rx/tx queue level parameters */ 1393 for (i = 0; i < priv->num_tx_queues; i++) { 1394 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1395 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1396 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1397 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1398 } 1399 1400 for (i = 0; i < priv->num_rx_queues; i++) { 1401 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1402 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1403 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1404 } 1405 1406 /* always enable rx filer */ 1407 priv->rx_filer_enable = 1; 1408 /* Enable most messages by default */ 1409 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1410 /* use pritority h/w tx queue scheduling for single queue devices */ 1411 if (priv->num_tx_queues == 1) 1412 priv->prio_sched_en = 1; 1413 1414 set_bit(GFAR_DOWN, &priv->state); 1415 1416 gfar_hw_init(priv); 1417 1418 /* Carrier starts down, phylib will bring it up */ 1419 netif_carrier_off(dev); 1420 1421 err = register_netdev(dev); 1422 1423 if (err) { 1424 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1425 goto register_fail; 1426 } 1427 1428 device_init_wakeup(&dev->dev, 1429 priv->device_flags & 1430 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1431 1432 /* fill out IRQ number and name fields */ 1433 for (i = 0; i < priv->num_grps; i++) { 1434 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1435 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1436 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1437 dev->name, "_g", '0' + i, "_tx"); 1438 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1439 dev->name, "_g", '0' + i, "_rx"); 1440 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1441 dev->name, "_g", '0' + i, "_er"); 1442 } else 1443 strcpy(gfar_irq(grp, TX)->name, dev->name); 1444 } 1445 1446 /* Initialize the filer table */ 1447 gfar_init_filer_table(priv); 1448 1449 /* Print out the device info */ 1450 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1451 1452 /* Even more device info helps when determining which kernel 1453 * provided which set of benchmarks. 1454 */ 1455 netdev_info(dev, "Running with NAPI enabled\n"); 1456 for (i = 0; i < priv->num_rx_queues; i++) 1457 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1458 i, priv->rx_queue[i]->rx_ring_size); 1459 for (i = 0; i < priv->num_tx_queues; i++) 1460 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1461 i, priv->tx_queue[i]->tx_ring_size); 1462 1463 return 0; 1464 1465 register_fail: 1466 unmap_group_regs(priv); 1467 gfar_free_rx_queues(priv); 1468 gfar_free_tx_queues(priv); 1469 of_node_put(priv->phy_node); 1470 of_node_put(priv->tbi_node); 1471 free_gfar_dev(priv); 1472 return err; 1473 } 1474 1475 static int gfar_remove(struct platform_device *ofdev) 1476 { 1477 struct gfar_private *priv = platform_get_drvdata(ofdev); 1478 1479 of_node_put(priv->phy_node); 1480 of_node_put(priv->tbi_node); 1481 1482 unregister_netdev(priv->ndev); 1483 unmap_group_regs(priv); 1484 gfar_free_rx_queues(priv); 1485 gfar_free_tx_queues(priv); 1486 free_gfar_dev(priv); 1487 1488 return 0; 1489 } 1490 1491 #ifdef CONFIG_PM 1492 1493 static int gfar_suspend(struct device *dev) 1494 { 1495 struct gfar_private *priv = dev_get_drvdata(dev); 1496 struct net_device *ndev = priv->ndev; 1497 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1498 unsigned long flags; 1499 u32 tempval; 1500 1501 int magic_packet = priv->wol_en && 1502 (priv->device_flags & 1503 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1504 1505 netif_device_detach(ndev); 1506 1507 if (netif_running(ndev)) { 1508 1509 local_irq_save(flags); 1510 lock_tx_qs(priv); 1511 1512 gfar_halt_nodisable(priv); 1513 1514 /* Disable Tx, and Rx if wake-on-LAN is disabled. */ 1515 tempval = gfar_read(®s->maccfg1); 1516 1517 tempval &= ~MACCFG1_TX_EN; 1518 1519 if (!magic_packet) 1520 tempval &= ~MACCFG1_RX_EN; 1521 1522 gfar_write(®s->maccfg1, tempval); 1523 1524 unlock_tx_qs(priv); 1525 local_irq_restore(flags); 1526 1527 disable_napi(priv); 1528 1529 if (magic_packet) { 1530 /* Enable interrupt on Magic Packet */ 1531 gfar_write(®s->imask, IMASK_MAG); 1532 1533 /* Enable Magic Packet mode */ 1534 tempval = gfar_read(®s->maccfg2); 1535 tempval |= MACCFG2_MPEN; 1536 gfar_write(®s->maccfg2, tempval); 1537 } else { 1538 phy_stop(priv->phydev); 1539 } 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int gfar_resume(struct device *dev) 1546 { 1547 struct gfar_private *priv = dev_get_drvdata(dev); 1548 struct net_device *ndev = priv->ndev; 1549 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1550 unsigned long flags; 1551 u32 tempval; 1552 int magic_packet = priv->wol_en && 1553 (priv->device_flags & 1554 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1555 1556 if (!netif_running(ndev)) { 1557 netif_device_attach(ndev); 1558 return 0; 1559 } 1560 1561 if (!magic_packet && priv->phydev) 1562 phy_start(priv->phydev); 1563 1564 /* Disable Magic Packet mode, in case something 1565 * else woke us up. 1566 */ 1567 local_irq_save(flags); 1568 lock_tx_qs(priv); 1569 1570 tempval = gfar_read(®s->maccfg2); 1571 tempval &= ~MACCFG2_MPEN; 1572 gfar_write(®s->maccfg2, tempval); 1573 1574 gfar_start(priv); 1575 1576 unlock_tx_qs(priv); 1577 local_irq_restore(flags); 1578 1579 netif_device_attach(ndev); 1580 1581 enable_napi(priv); 1582 1583 return 0; 1584 } 1585 1586 static int gfar_restore(struct device *dev) 1587 { 1588 struct gfar_private *priv = dev_get_drvdata(dev); 1589 struct net_device *ndev = priv->ndev; 1590 1591 if (!netif_running(ndev)) { 1592 netif_device_attach(ndev); 1593 1594 return 0; 1595 } 1596 1597 if (gfar_init_bds(ndev)) { 1598 free_skb_resources(priv); 1599 return -ENOMEM; 1600 } 1601 1602 gfar_mac_reset(priv); 1603 1604 gfar_init_tx_rx_base(priv); 1605 1606 gfar_start(priv); 1607 1608 priv->oldlink = 0; 1609 priv->oldspeed = 0; 1610 priv->oldduplex = -1; 1611 1612 if (priv->phydev) 1613 phy_start(priv->phydev); 1614 1615 netif_device_attach(ndev); 1616 enable_napi(priv); 1617 1618 return 0; 1619 } 1620 1621 static struct dev_pm_ops gfar_pm_ops = { 1622 .suspend = gfar_suspend, 1623 .resume = gfar_resume, 1624 .freeze = gfar_suspend, 1625 .thaw = gfar_resume, 1626 .restore = gfar_restore, 1627 }; 1628 1629 #define GFAR_PM_OPS (&gfar_pm_ops) 1630 1631 #else 1632 1633 #define GFAR_PM_OPS NULL 1634 1635 #endif 1636 1637 /* Reads the controller's registers to determine what interface 1638 * connects it to the PHY. 1639 */ 1640 static phy_interface_t gfar_get_interface(struct net_device *dev) 1641 { 1642 struct gfar_private *priv = netdev_priv(dev); 1643 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1644 u32 ecntrl; 1645 1646 ecntrl = gfar_read(®s->ecntrl); 1647 1648 if (ecntrl & ECNTRL_SGMII_MODE) 1649 return PHY_INTERFACE_MODE_SGMII; 1650 1651 if (ecntrl & ECNTRL_TBI_MODE) { 1652 if (ecntrl & ECNTRL_REDUCED_MODE) 1653 return PHY_INTERFACE_MODE_RTBI; 1654 else 1655 return PHY_INTERFACE_MODE_TBI; 1656 } 1657 1658 if (ecntrl & ECNTRL_REDUCED_MODE) { 1659 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1660 return PHY_INTERFACE_MODE_RMII; 1661 } 1662 else { 1663 phy_interface_t interface = priv->interface; 1664 1665 /* This isn't autodetected right now, so it must 1666 * be set by the device tree or platform code. 1667 */ 1668 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1669 return PHY_INTERFACE_MODE_RGMII_ID; 1670 1671 return PHY_INTERFACE_MODE_RGMII; 1672 } 1673 } 1674 1675 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1676 return PHY_INTERFACE_MODE_GMII; 1677 1678 return PHY_INTERFACE_MODE_MII; 1679 } 1680 1681 1682 /* Initializes driver's PHY state, and attaches to the PHY. 1683 * Returns 0 on success. 1684 */ 1685 static int init_phy(struct net_device *dev) 1686 { 1687 struct gfar_private *priv = netdev_priv(dev); 1688 uint gigabit_support = 1689 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? 1690 GFAR_SUPPORTED_GBIT : 0; 1691 phy_interface_t interface; 1692 1693 priv->oldlink = 0; 1694 priv->oldspeed = 0; 1695 priv->oldduplex = -1; 1696 1697 interface = gfar_get_interface(dev); 1698 1699 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1700 interface); 1701 if (!priv->phydev) { 1702 dev_err(&dev->dev, "could not attach to PHY\n"); 1703 return -ENODEV; 1704 } 1705 1706 if (interface == PHY_INTERFACE_MODE_SGMII) 1707 gfar_configure_serdes(dev); 1708 1709 /* Remove any features not supported by the controller */ 1710 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); 1711 priv->phydev->advertising = priv->phydev->supported; 1712 1713 /* Add support for flow control, but don't advertise it by default */ 1714 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause); 1715 1716 return 0; 1717 } 1718 1719 /* Initialize TBI PHY interface for communicating with the 1720 * SERDES lynx PHY on the chip. We communicate with this PHY 1721 * through the MDIO bus on each controller, treating it as a 1722 * "normal" PHY at the address found in the TBIPA register. We assume 1723 * that the TBIPA register is valid. Either the MDIO bus code will set 1724 * it to a value that doesn't conflict with other PHYs on the bus, or the 1725 * value doesn't matter, as there are no other PHYs on the bus. 1726 */ 1727 static void gfar_configure_serdes(struct net_device *dev) 1728 { 1729 struct gfar_private *priv = netdev_priv(dev); 1730 struct phy_device *tbiphy; 1731 1732 if (!priv->tbi_node) { 1733 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1734 "device tree specify a tbi-handle\n"); 1735 return; 1736 } 1737 1738 tbiphy = of_phy_find_device(priv->tbi_node); 1739 if (!tbiphy) { 1740 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1741 return; 1742 } 1743 1744 /* If the link is already up, we must already be ok, and don't need to 1745 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1746 * everything for us? Resetting it takes the link down and requires 1747 * several seconds for it to come back. 1748 */ 1749 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) 1750 return; 1751 1752 /* Single clk mode, mii mode off(for serdes communication) */ 1753 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1754 1755 phy_write(tbiphy, MII_ADVERTISE, 1756 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1757 ADVERTISE_1000XPSE_ASYM); 1758 1759 phy_write(tbiphy, MII_BMCR, 1760 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1761 BMCR_SPEED1000); 1762 } 1763 1764 static int __gfar_is_rx_idle(struct gfar_private *priv) 1765 { 1766 u32 res; 1767 1768 /* Normaly TSEC should not hang on GRS commands, so we should 1769 * actually wait for IEVENT_GRSC flag. 1770 */ 1771 if (!gfar_has_errata(priv, GFAR_ERRATA_A002)) 1772 return 0; 1773 1774 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1775 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1776 * and the Rx can be safely reset. 1777 */ 1778 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1779 res &= 0x7f807f80; 1780 if ((res & 0xffff) == (res >> 16)) 1781 return 1; 1782 1783 return 0; 1784 } 1785 1786 /* Halt the receive and transmit queues */ 1787 static void gfar_halt_nodisable(struct gfar_private *priv) 1788 { 1789 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1790 u32 tempval; 1791 unsigned int timeout; 1792 int stopped; 1793 1794 gfar_ints_disable(priv); 1795 1796 if (gfar_is_dma_stopped(priv)) 1797 return; 1798 1799 /* Stop the DMA, and wait for it to stop */ 1800 tempval = gfar_read(®s->dmactrl); 1801 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1802 gfar_write(®s->dmactrl, tempval); 1803 1804 retry: 1805 timeout = 1000; 1806 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) { 1807 cpu_relax(); 1808 timeout--; 1809 } 1810 1811 if (!timeout) 1812 stopped = gfar_is_dma_stopped(priv); 1813 1814 if (!stopped && !gfar_is_rx_dma_stopped(priv) && 1815 !__gfar_is_rx_idle(priv)) 1816 goto retry; 1817 } 1818 1819 /* Halt the receive and transmit queues */ 1820 void gfar_halt(struct gfar_private *priv) 1821 { 1822 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1823 u32 tempval; 1824 1825 /* Dissable the Rx/Tx hw queues */ 1826 gfar_write(®s->rqueue, 0); 1827 gfar_write(®s->tqueue, 0); 1828 1829 mdelay(10); 1830 1831 gfar_halt_nodisable(priv); 1832 1833 /* Disable Rx/Tx DMA */ 1834 tempval = gfar_read(®s->maccfg1); 1835 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1836 gfar_write(®s->maccfg1, tempval); 1837 } 1838 1839 void stop_gfar(struct net_device *dev) 1840 { 1841 struct gfar_private *priv = netdev_priv(dev); 1842 1843 netif_tx_stop_all_queues(dev); 1844 1845 smp_mb__before_atomic(); 1846 set_bit(GFAR_DOWN, &priv->state); 1847 smp_mb__after_atomic(); 1848 1849 disable_napi(priv); 1850 1851 /* disable ints and gracefully shut down Rx/Tx DMA */ 1852 gfar_halt(priv); 1853 1854 phy_stop(priv->phydev); 1855 1856 free_skb_resources(priv); 1857 } 1858 1859 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1860 { 1861 struct txbd8 *txbdp; 1862 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1863 int i, j; 1864 1865 txbdp = tx_queue->tx_bd_base; 1866 1867 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1868 if (!tx_queue->tx_skbuff[i]) 1869 continue; 1870 1871 dma_unmap_single(priv->dev, txbdp->bufPtr, 1872 txbdp->length, DMA_TO_DEVICE); 1873 txbdp->lstatus = 0; 1874 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1875 j++) { 1876 txbdp++; 1877 dma_unmap_page(priv->dev, txbdp->bufPtr, 1878 txbdp->length, DMA_TO_DEVICE); 1879 } 1880 txbdp++; 1881 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1882 tx_queue->tx_skbuff[i] = NULL; 1883 } 1884 kfree(tx_queue->tx_skbuff); 1885 tx_queue->tx_skbuff = NULL; 1886 } 1887 1888 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1889 { 1890 struct rxbd8 *rxbdp; 1891 struct gfar_private *priv = netdev_priv(rx_queue->dev); 1892 int i; 1893 1894 rxbdp = rx_queue->rx_bd_base; 1895 1896 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1897 if (rx_queue->rx_skbuff[i]) { 1898 dma_unmap_single(priv->dev, rxbdp->bufPtr, 1899 priv->rx_buffer_size, 1900 DMA_FROM_DEVICE); 1901 dev_kfree_skb_any(rx_queue->rx_skbuff[i]); 1902 rx_queue->rx_skbuff[i] = NULL; 1903 } 1904 rxbdp->lstatus = 0; 1905 rxbdp->bufPtr = 0; 1906 rxbdp++; 1907 } 1908 kfree(rx_queue->rx_skbuff); 1909 rx_queue->rx_skbuff = NULL; 1910 } 1911 1912 /* If there are any tx skbs or rx skbs still around, free them. 1913 * Then free tx_skbuff and rx_skbuff 1914 */ 1915 static void free_skb_resources(struct gfar_private *priv) 1916 { 1917 struct gfar_priv_tx_q *tx_queue = NULL; 1918 struct gfar_priv_rx_q *rx_queue = NULL; 1919 int i; 1920 1921 /* Go through all the buffer descriptors and free their data buffers */ 1922 for (i = 0; i < priv->num_tx_queues; i++) { 1923 struct netdev_queue *txq; 1924 1925 tx_queue = priv->tx_queue[i]; 1926 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1927 if (tx_queue->tx_skbuff) 1928 free_skb_tx_queue(tx_queue); 1929 netdev_tx_reset_queue(txq); 1930 } 1931 1932 for (i = 0; i < priv->num_rx_queues; i++) { 1933 rx_queue = priv->rx_queue[i]; 1934 if (rx_queue->rx_skbuff) 1935 free_skb_rx_queue(rx_queue); 1936 } 1937 1938 dma_free_coherent(priv->dev, 1939 sizeof(struct txbd8) * priv->total_tx_ring_size + 1940 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1941 priv->tx_queue[0]->tx_bd_base, 1942 priv->tx_queue[0]->tx_bd_dma_base); 1943 } 1944 1945 void gfar_start(struct gfar_private *priv) 1946 { 1947 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1948 u32 tempval; 1949 int i = 0; 1950 1951 /* Enable Rx/Tx hw queues */ 1952 gfar_write(®s->rqueue, priv->rqueue); 1953 gfar_write(®s->tqueue, priv->tqueue); 1954 1955 /* Initialize DMACTRL to have WWR and WOP */ 1956 tempval = gfar_read(®s->dmactrl); 1957 tempval |= DMACTRL_INIT_SETTINGS; 1958 gfar_write(®s->dmactrl, tempval); 1959 1960 /* Make sure we aren't stopped */ 1961 tempval = gfar_read(®s->dmactrl); 1962 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1963 gfar_write(®s->dmactrl, tempval); 1964 1965 for (i = 0; i < priv->num_grps; i++) { 1966 regs = priv->gfargrp[i].regs; 1967 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1968 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1969 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1970 } 1971 1972 /* Enable Rx/Tx DMA */ 1973 tempval = gfar_read(®s->maccfg1); 1974 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1975 gfar_write(®s->maccfg1, tempval); 1976 1977 gfar_ints_enable(priv); 1978 1979 priv->ndev->trans_start = jiffies; /* prevent tx timeout */ 1980 } 1981 1982 static void free_grp_irqs(struct gfar_priv_grp *grp) 1983 { 1984 free_irq(gfar_irq(grp, TX)->irq, grp); 1985 free_irq(gfar_irq(grp, RX)->irq, grp); 1986 free_irq(gfar_irq(grp, ER)->irq, grp); 1987 } 1988 1989 static int register_grp_irqs(struct gfar_priv_grp *grp) 1990 { 1991 struct gfar_private *priv = grp->priv; 1992 struct net_device *dev = priv->ndev; 1993 int err; 1994 1995 /* If the device has multiple interrupts, register for 1996 * them. Otherwise, only register for the one 1997 */ 1998 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1999 /* Install our interrupt handlers for Error, 2000 * Transmit, and Receive 2001 */ 2002 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 2003 gfar_irq(grp, ER)->name, grp); 2004 if (err < 0) { 2005 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2006 gfar_irq(grp, ER)->irq); 2007 2008 goto err_irq_fail; 2009 } 2010 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 2011 gfar_irq(grp, TX)->name, grp); 2012 if (err < 0) { 2013 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2014 gfar_irq(grp, TX)->irq); 2015 goto tx_irq_fail; 2016 } 2017 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 2018 gfar_irq(grp, RX)->name, grp); 2019 if (err < 0) { 2020 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2021 gfar_irq(grp, RX)->irq); 2022 goto rx_irq_fail; 2023 } 2024 } else { 2025 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 2026 gfar_irq(grp, TX)->name, grp); 2027 if (err < 0) { 2028 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 2029 gfar_irq(grp, TX)->irq); 2030 goto err_irq_fail; 2031 } 2032 } 2033 2034 return 0; 2035 2036 rx_irq_fail: 2037 free_irq(gfar_irq(grp, TX)->irq, grp); 2038 tx_irq_fail: 2039 free_irq(gfar_irq(grp, ER)->irq, grp); 2040 err_irq_fail: 2041 return err; 2042 2043 } 2044 2045 static void gfar_free_irq(struct gfar_private *priv) 2046 { 2047 int i; 2048 2049 /* Free the IRQs */ 2050 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2051 for (i = 0; i < priv->num_grps; i++) 2052 free_grp_irqs(&priv->gfargrp[i]); 2053 } else { 2054 for (i = 0; i < priv->num_grps; i++) 2055 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 2056 &priv->gfargrp[i]); 2057 } 2058 } 2059 2060 static int gfar_request_irq(struct gfar_private *priv) 2061 { 2062 int err, i, j; 2063 2064 for (i = 0; i < priv->num_grps; i++) { 2065 err = register_grp_irqs(&priv->gfargrp[i]); 2066 if (err) { 2067 for (j = 0; j < i; j++) 2068 free_grp_irqs(&priv->gfargrp[j]); 2069 return err; 2070 } 2071 } 2072 2073 return 0; 2074 } 2075 2076 /* Bring the controller up and running */ 2077 int startup_gfar(struct net_device *ndev) 2078 { 2079 struct gfar_private *priv = netdev_priv(ndev); 2080 int err; 2081 2082 gfar_mac_reset(priv); 2083 2084 err = gfar_alloc_skb_resources(ndev); 2085 if (err) 2086 return err; 2087 2088 gfar_init_tx_rx_base(priv); 2089 2090 smp_mb__before_atomic(); 2091 clear_bit(GFAR_DOWN, &priv->state); 2092 smp_mb__after_atomic(); 2093 2094 /* Start Rx/Tx DMA and enable the interrupts */ 2095 gfar_start(priv); 2096 2097 phy_start(priv->phydev); 2098 2099 enable_napi(priv); 2100 2101 netif_tx_wake_all_queues(ndev); 2102 2103 return 0; 2104 } 2105 2106 /* Called when something needs to use the ethernet device 2107 * Returns 0 for success. 2108 */ 2109 static int gfar_enet_open(struct net_device *dev) 2110 { 2111 struct gfar_private *priv = netdev_priv(dev); 2112 int err; 2113 2114 err = init_phy(dev); 2115 if (err) 2116 return err; 2117 2118 err = gfar_request_irq(priv); 2119 if (err) 2120 return err; 2121 2122 err = startup_gfar(dev); 2123 if (err) 2124 return err; 2125 2126 device_set_wakeup_enable(&dev->dev, priv->wol_en); 2127 2128 return err; 2129 } 2130 2131 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 2132 { 2133 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); 2134 2135 memset(fcb, 0, GMAC_FCB_LEN); 2136 2137 return fcb; 2138 } 2139 2140 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2141 int fcb_length) 2142 { 2143 /* If we're here, it's a IP packet with a TCP or UDP 2144 * payload. We set it to checksum, using a pseudo-header 2145 * we provide 2146 */ 2147 u8 flags = TXFCB_DEFAULT; 2148 2149 /* Tell the controller what the protocol is 2150 * And provide the already calculated phcs 2151 */ 2152 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2153 flags |= TXFCB_UDP; 2154 fcb->phcs = udp_hdr(skb)->check; 2155 } else 2156 fcb->phcs = tcp_hdr(skb)->check; 2157 2158 /* l3os is the distance between the start of the 2159 * frame (skb->data) and the start of the IP hdr. 2160 * l4os is the distance between the start of the 2161 * l3 hdr and the l4 hdr 2162 */ 2163 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); 2164 fcb->l4os = skb_network_header_len(skb); 2165 2166 fcb->flags = flags; 2167 } 2168 2169 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2170 { 2171 fcb->flags |= TXFCB_VLN; 2172 fcb->vlctl = vlan_tx_tag_get(skb); 2173 } 2174 2175 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2176 struct txbd8 *base, int ring_size) 2177 { 2178 struct txbd8 *new_bd = bdp + stride; 2179 2180 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2181 } 2182 2183 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2184 int ring_size) 2185 { 2186 return skip_txbd(bdp, 1, base, ring_size); 2187 } 2188 2189 /* eTSEC12: csum generation not supported for some fcb offsets */ 2190 static inline bool gfar_csum_errata_12(struct gfar_private *priv, 2191 unsigned long fcb_addr) 2192 { 2193 return (gfar_has_errata(priv, GFAR_ERRATA_12) && 2194 (fcb_addr % 0x20) > 0x18); 2195 } 2196 2197 /* eTSEC76: csum generation for frames larger than 2500 may 2198 * cause excess delays before start of transmission 2199 */ 2200 static inline bool gfar_csum_errata_76(struct gfar_private *priv, 2201 unsigned int len) 2202 { 2203 return (gfar_has_errata(priv, GFAR_ERRATA_76) && 2204 (len > 2500)); 2205 } 2206 2207 /* This is called by the kernel when a frame is ready for transmission. 2208 * It is pointed to by the dev->hard_start_xmit function pointer 2209 */ 2210 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2211 { 2212 struct gfar_private *priv = netdev_priv(dev); 2213 struct gfar_priv_tx_q *tx_queue = NULL; 2214 struct netdev_queue *txq; 2215 struct gfar __iomem *regs = NULL; 2216 struct txfcb *fcb = NULL; 2217 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2218 u32 lstatus; 2219 int i, rq = 0; 2220 int do_tstamp, do_csum, do_vlan; 2221 u32 bufaddr; 2222 unsigned long flags; 2223 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; 2224 2225 rq = skb->queue_mapping; 2226 tx_queue = priv->tx_queue[rq]; 2227 txq = netdev_get_tx_queue(dev, rq); 2228 base = tx_queue->tx_bd_base; 2229 regs = tx_queue->grp->regs; 2230 2231 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); 2232 do_vlan = vlan_tx_tag_present(skb); 2233 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2234 priv->hwts_tx_en; 2235 2236 if (do_csum || do_vlan) 2237 fcb_len = GMAC_FCB_LEN; 2238 2239 /* check if time stamp should be generated */ 2240 if (unlikely(do_tstamp)) 2241 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2242 2243 /* make space for additional header when fcb is needed */ 2244 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { 2245 struct sk_buff *skb_new; 2246 2247 skb_new = skb_realloc_headroom(skb, fcb_len); 2248 if (!skb_new) { 2249 dev->stats.tx_errors++; 2250 dev_kfree_skb_any(skb); 2251 return NETDEV_TX_OK; 2252 } 2253 2254 if (skb->sk) 2255 skb_set_owner_w(skb_new, skb->sk); 2256 dev_consume_skb_any(skb); 2257 skb = skb_new; 2258 } 2259 2260 /* total number of fragments in the SKB */ 2261 nr_frags = skb_shinfo(skb)->nr_frags; 2262 2263 /* calculate the required number of TxBDs for this skb */ 2264 if (unlikely(do_tstamp)) 2265 nr_txbds = nr_frags + 2; 2266 else 2267 nr_txbds = nr_frags + 1; 2268 2269 /* check if there is space to queue this packet */ 2270 if (nr_txbds > tx_queue->num_txbdfree) { 2271 /* no space, stop the queue */ 2272 netif_tx_stop_queue(txq); 2273 dev->stats.tx_fifo_errors++; 2274 return NETDEV_TX_BUSY; 2275 } 2276 2277 /* Update transmit stats */ 2278 bytes_sent = skb->len; 2279 tx_queue->stats.tx_bytes += bytes_sent; 2280 /* keep Tx bytes on wire for BQL accounting */ 2281 GFAR_CB(skb)->bytes_sent = bytes_sent; 2282 tx_queue->stats.tx_packets++; 2283 2284 txbdp = txbdp_start = tx_queue->cur_tx; 2285 lstatus = txbdp->lstatus; 2286 2287 /* Time stamp insertion requires one additional TxBD */ 2288 if (unlikely(do_tstamp)) 2289 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2290 tx_queue->tx_ring_size); 2291 2292 if (nr_frags == 0) { 2293 if (unlikely(do_tstamp)) 2294 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | 2295 TXBD_INTERRUPT); 2296 else 2297 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2298 } else { 2299 /* Place the fragment addresses and lengths into the TxBDs */ 2300 for (i = 0; i < nr_frags; i++) { 2301 unsigned int frag_len; 2302 /* Point at the next BD, wrapping as needed */ 2303 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2304 2305 frag_len = skb_shinfo(skb)->frags[i].size; 2306 2307 lstatus = txbdp->lstatus | frag_len | 2308 BD_LFLAG(TXBD_READY); 2309 2310 /* Handle the last BD specially */ 2311 if (i == nr_frags - 1) 2312 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2313 2314 bufaddr = skb_frag_dma_map(priv->dev, 2315 &skb_shinfo(skb)->frags[i], 2316 0, 2317 frag_len, 2318 DMA_TO_DEVICE); 2319 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2320 goto dma_map_err; 2321 2322 /* set the TxBD length and buffer pointer */ 2323 txbdp->bufPtr = bufaddr; 2324 txbdp->lstatus = lstatus; 2325 } 2326 2327 lstatus = txbdp_start->lstatus; 2328 } 2329 2330 /* Add TxPAL between FCB and frame if required */ 2331 if (unlikely(do_tstamp)) { 2332 skb_push(skb, GMAC_TXPAL_LEN); 2333 memset(skb->data, 0, GMAC_TXPAL_LEN); 2334 } 2335 2336 /* Add TxFCB if required */ 2337 if (fcb_len) { 2338 fcb = gfar_add_fcb(skb); 2339 lstatus |= BD_LFLAG(TXBD_TOE); 2340 } 2341 2342 /* Set up checksumming */ 2343 if (do_csum) { 2344 gfar_tx_checksum(skb, fcb, fcb_len); 2345 2346 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || 2347 unlikely(gfar_csum_errata_76(priv, skb->len))) { 2348 __skb_pull(skb, GMAC_FCB_LEN); 2349 skb_checksum_help(skb); 2350 if (do_vlan || do_tstamp) { 2351 /* put back a new fcb for vlan/tstamp TOE */ 2352 fcb = gfar_add_fcb(skb); 2353 } else { 2354 /* Tx TOE not used */ 2355 lstatus &= ~(BD_LFLAG(TXBD_TOE)); 2356 fcb = NULL; 2357 } 2358 } 2359 } 2360 2361 if (do_vlan) 2362 gfar_tx_vlan(skb, fcb); 2363 2364 /* Setup tx hardware time stamping if requested */ 2365 if (unlikely(do_tstamp)) { 2366 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2367 fcb->ptp = 1; 2368 } 2369 2370 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb), 2371 DMA_TO_DEVICE); 2372 if (unlikely(dma_mapping_error(priv->dev, bufaddr))) 2373 goto dma_map_err; 2374 2375 txbdp_start->bufPtr = bufaddr; 2376 2377 /* If time stamping is requested one additional TxBD must be set up. The 2378 * first TxBD points to the FCB and must have a data length of 2379 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2380 * the full frame length. 2381 */ 2382 if (unlikely(do_tstamp)) { 2383 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; 2384 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | 2385 (skb_headlen(skb) - fcb_len); 2386 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2387 } else { 2388 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2389 } 2390 2391 netdev_tx_sent_queue(txq, bytes_sent); 2392 2393 /* We can work in parallel with gfar_clean_tx_ring(), except 2394 * when modifying num_txbdfree. Note that we didn't grab the lock 2395 * when we were reading the num_txbdfree and checking for available 2396 * space, that's because outside of this function it can only grow, 2397 * and once we've got needed space, it cannot suddenly disappear. 2398 * 2399 * The lock also protects us from gfar_error(), which can modify 2400 * regs->tstat and thus retrigger the transfers, which is why we 2401 * also must grab the lock before setting ready bit for the first 2402 * to be transmitted BD. 2403 */ 2404 spin_lock_irqsave(&tx_queue->txlock, flags); 2405 2406 gfar_wmb(); 2407 2408 txbdp_start->lstatus = lstatus; 2409 2410 gfar_wmb(); /* force lstatus write before tx_skbuff */ 2411 2412 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2413 2414 /* Update the current skb pointer to the next entry we will use 2415 * (wrapping if necessary) 2416 */ 2417 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2418 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2419 2420 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2421 2422 /* reduce TxBD free count */ 2423 tx_queue->num_txbdfree -= (nr_txbds); 2424 2425 /* If the next BD still needs to be cleaned up, then the bds 2426 * are full. We need to tell the kernel to stop sending us stuff. 2427 */ 2428 if (!tx_queue->num_txbdfree) { 2429 netif_tx_stop_queue(txq); 2430 2431 dev->stats.tx_fifo_errors++; 2432 } 2433 2434 /* Tell the DMA to go go go */ 2435 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2436 2437 /* Unlock priv */ 2438 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2439 2440 return NETDEV_TX_OK; 2441 2442 dma_map_err: 2443 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size); 2444 if (do_tstamp) 2445 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2446 for (i = 0; i < nr_frags; i++) { 2447 lstatus = txbdp->lstatus; 2448 if (!(lstatus & BD_LFLAG(TXBD_READY))) 2449 break; 2450 2451 txbdp->lstatus = lstatus & ~BD_LFLAG(TXBD_READY); 2452 bufaddr = txbdp->bufPtr; 2453 dma_unmap_page(priv->dev, bufaddr, txbdp->length, 2454 DMA_TO_DEVICE); 2455 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2456 } 2457 gfar_wmb(); 2458 dev_kfree_skb_any(skb); 2459 return NETDEV_TX_OK; 2460 } 2461 2462 /* Stops the kernel queue, and halts the controller */ 2463 static int gfar_close(struct net_device *dev) 2464 { 2465 struct gfar_private *priv = netdev_priv(dev); 2466 2467 cancel_work_sync(&priv->reset_task); 2468 stop_gfar(dev); 2469 2470 /* Disconnect from the PHY */ 2471 phy_disconnect(priv->phydev); 2472 priv->phydev = NULL; 2473 2474 gfar_free_irq(priv); 2475 2476 return 0; 2477 } 2478 2479 /* Changes the mac address if the controller is not running. */ 2480 static int gfar_set_mac_address(struct net_device *dev) 2481 { 2482 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2483 2484 return 0; 2485 } 2486 2487 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2488 { 2489 struct gfar_private *priv = netdev_priv(dev); 2490 int frame_size = new_mtu + ETH_HLEN; 2491 2492 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { 2493 netif_err(priv, drv, dev, "Invalid MTU setting\n"); 2494 return -EINVAL; 2495 } 2496 2497 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2498 cpu_relax(); 2499 2500 if (dev->flags & IFF_UP) 2501 stop_gfar(dev); 2502 2503 dev->mtu = new_mtu; 2504 2505 if (dev->flags & IFF_UP) 2506 startup_gfar(dev); 2507 2508 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2509 2510 return 0; 2511 } 2512 2513 void reset_gfar(struct net_device *ndev) 2514 { 2515 struct gfar_private *priv = netdev_priv(ndev); 2516 2517 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state)) 2518 cpu_relax(); 2519 2520 stop_gfar(ndev); 2521 startup_gfar(ndev); 2522 2523 clear_bit_unlock(GFAR_RESETTING, &priv->state); 2524 } 2525 2526 /* gfar_reset_task gets scheduled when a packet has not been 2527 * transmitted after a set amount of time. 2528 * For now, assume that clearing out all the structures, and 2529 * starting over will fix the problem. 2530 */ 2531 static void gfar_reset_task(struct work_struct *work) 2532 { 2533 struct gfar_private *priv = container_of(work, struct gfar_private, 2534 reset_task); 2535 reset_gfar(priv->ndev); 2536 } 2537 2538 static void gfar_timeout(struct net_device *dev) 2539 { 2540 struct gfar_private *priv = netdev_priv(dev); 2541 2542 dev->stats.tx_errors++; 2543 schedule_work(&priv->reset_task); 2544 } 2545 2546 static void gfar_align_skb(struct sk_buff *skb) 2547 { 2548 /* We need the data buffer to be aligned properly. We will reserve 2549 * as many bytes as needed to align the data properly 2550 */ 2551 skb_reserve(skb, RXBUF_ALIGNMENT - 2552 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); 2553 } 2554 2555 /* Interrupt Handler for Transmit complete */ 2556 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2557 { 2558 struct net_device *dev = tx_queue->dev; 2559 struct netdev_queue *txq; 2560 struct gfar_private *priv = netdev_priv(dev); 2561 struct txbd8 *bdp, *next = NULL; 2562 struct txbd8 *lbdp = NULL; 2563 struct txbd8 *base = tx_queue->tx_bd_base; 2564 struct sk_buff *skb; 2565 int skb_dirtytx; 2566 int tx_ring_size = tx_queue->tx_ring_size; 2567 int frags = 0, nr_txbds = 0; 2568 int i; 2569 int howmany = 0; 2570 int tqi = tx_queue->qindex; 2571 unsigned int bytes_sent = 0; 2572 u32 lstatus; 2573 size_t buflen; 2574 2575 txq = netdev_get_tx_queue(dev, tqi); 2576 bdp = tx_queue->dirty_tx; 2577 skb_dirtytx = tx_queue->skb_dirtytx; 2578 2579 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2580 unsigned long flags; 2581 2582 frags = skb_shinfo(skb)->nr_frags; 2583 2584 /* When time stamping, one additional TxBD must be freed. 2585 * Also, we need to dma_unmap_single() the TxPAL. 2586 */ 2587 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2588 nr_txbds = frags + 2; 2589 else 2590 nr_txbds = frags + 1; 2591 2592 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2593 2594 lstatus = lbdp->lstatus; 2595 2596 /* Only clean completed frames */ 2597 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2598 (lstatus & BD_LENGTH_MASK)) 2599 break; 2600 2601 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2602 next = next_txbd(bdp, base, tx_ring_size); 2603 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2604 } else 2605 buflen = bdp->length; 2606 2607 dma_unmap_single(priv->dev, bdp->bufPtr, 2608 buflen, DMA_TO_DEVICE); 2609 2610 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2611 struct skb_shared_hwtstamps shhwtstamps; 2612 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); 2613 2614 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2615 shhwtstamps.hwtstamp = ns_to_ktime(*ns); 2616 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2617 skb_tstamp_tx(skb, &shhwtstamps); 2618 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2619 bdp = next; 2620 } 2621 2622 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2623 bdp = next_txbd(bdp, base, tx_ring_size); 2624 2625 for (i = 0; i < frags; i++) { 2626 dma_unmap_page(priv->dev, bdp->bufPtr, 2627 bdp->length, DMA_TO_DEVICE); 2628 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2629 bdp = next_txbd(bdp, base, tx_ring_size); 2630 } 2631 2632 bytes_sent += GFAR_CB(skb)->bytes_sent; 2633 2634 dev_kfree_skb_any(skb); 2635 2636 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2637 2638 skb_dirtytx = (skb_dirtytx + 1) & 2639 TX_RING_MOD_MASK(tx_ring_size); 2640 2641 howmany++; 2642 spin_lock_irqsave(&tx_queue->txlock, flags); 2643 tx_queue->num_txbdfree += nr_txbds; 2644 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2645 } 2646 2647 /* If we freed a buffer, we can restart transmission, if necessary */ 2648 if (tx_queue->num_txbdfree && 2649 netif_tx_queue_stopped(txq) && 2650 !(test_bit(GFAR_DOWN, &priv->state))) 2651 netif_wake_subqueue(priv->ndev, tqi); 2652 2653 /* Update dirty indicators */ 2654 tx_queue->skb_dirtytx = skb_dirtytx; 2655 tx_queue->dirty_tx = bdp; 2656 2657 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2658 } 2659 2660 static struct sk_buff *gfar_alloc_skb(struct net_device *dev) 2661 { 2662 struct gfar_private *priv = netdev_priv(dev); 2663 struct sk_buff *skb; 2664 2665 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); 2666 if (!skb) 2667 return NULL; 2668 2669 gfar_align_skb(skb); 2670 2671 return skb; 2672 } 2673 2674 struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr) 2675 { 2676 struct gfar_private *priv = netdev_priv(dev); 2677 struct sk_buff *skb; 2678 dma_addr_t addr; 2679 2680 skb = gfar_alloc_skb(dev); 2681 if (!skb) 2682 return NULL; 2683 2684 addr = dma_map_single(priv->dev, skb->data, 2685 priv->rx_buffer_size, DMA_FROM_DEVICE); 2686 if (unlikely(dma_mapping_error(priv->dev, addr))) { 2687 dev_kfree_skb_any(skb); 2688 return NULL; 2689 } 2690 2691 *bufaddr = addr; 2692 return skb; 2693 } 2694 2695 static inline void count_errors(unsigned short status, struct net_device *dev) 2696 { 2697 struct gfar_private *priv = netdev_priv(dev); 2698 struct net_device_stats *stats = &dev->stats; 2699 struct gfar_extra_stats *estats = &priv->extra_stats; 2700 2701 /* If the packet was truncated, none of the other errors matter */ 2702 if (status & RXBD_TRUNCATED) { 2703 stats->rx_length_errors++; 2704 2705 atomic64_inc(&estats->rx_trunc); 2706 2707 return; 2708 } 2709 /* Count the errors, if there were any */ 2710 if (status & (RXBD_LARGE | RXBD_SHORT)) { 2711 stats->rx_length_errors++; 2712 2713 if (status & RXBD_LARGE) 2714 atomic64_inc(&estats->rx_large); 2715 else 2716 atomic64_inc(&estats->rx_short); 2717 } 2718 if (status & RXBD_NONOCTET) { 2719 stats->rx_frame_errors++; 2720 atomic64_inc(&estats->rx_nonoctet); 2721 } 2722 if (status & RXBD_CRCERR) { 2723 atomic64_inc(&estats->rx_crcerr); 2724 stats->rx_crc_errors++; 2725 } 2726 if (status & RXBD_OVERRUN) { 2727 atomic64_inc(&estats->rx_overrun); 2728 stats->rx_crc_errors++; 2729 } 2730 } 2731 2732 irqreturn_t gfar_receive(int irq, void *grp_id) 2733 { 2734 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2735 unsigned long flags; 2736 u32 imask; 2737 2738 if (likely(napi_schedule_prep(&grp->napi_rx))) { 2739 spin_lock_irqsave(&grp->grplock, flags); 2740 imask = gfar_read(&grp->regs->imask); 2741 imask &= IMASK_RX_DISABLED; 2742 gfar_write(&grp->regs->imask, imask); 2743 spin_unlock_irqrestore(&grp->grplock, flags); 2744 __napi_schedule(&grp->napi_rx); 2745 } else { 2746 /* Clear IEVENT, so interrupts aren't called again 2747 * because of the packets that have already arrived. 2748 */ 2749 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK); 2750 } 2751 2752 return IRQ_HANDLED; 2753 } 2754 2755 /* Interrupt Handler for Transmit complete */ 2756 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2757 { 2758 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id; 2759 unsigned long flags; 2760 u32 imask; 2761 2762 if (likely(napi_schedule_prep(&grp->napi_tx))) { 2763 spin_lock_irqsave(&grp->grplock, flags); 2764 imask = gfar_read(&grp->regs->imask); 2765 imask &= IMASK_TX_DISABLED; 2766 gfar_write(&grp->regs->imask, imask); 2767 spin_unlock_irqrestore(&grp->grplock, flags); 2768 __napi_schedule(&grp->napi_tx); 2769 } else { 2770 /* Clear IEVENT, so interrupts aren't called again 2771 * because of the packets that have already arrived. 2772 */ 2773 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK); 2774 } 2775 2776 return IRQ_HANDLED; 2777 } 2778 2779 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2780 { 2781 /* If valid headers were found, and valid sums 2782 * were verified, then we tell the kernel that no 2783 * checksumming is necessary. Otherwise, it is [FIXME] 2784 */ 2785 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) 2786 skb->ip_summed = CHECKSUM_UNNECESSARY; 2787 else 2788 skb_checksum_none_assert(skb); 2789 } 2790 2791 2792 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2793 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 2794 int amount_pull, struct napi_struct *napi) 2795 { 2796 struct gfar_private *priv = netdev_priv(dev); 2797 struct rxfcb *fcb = NULL; 2798 2799 /* fcb is at the beginning if exists */ 2800 fcb = (struct rxfcb *)skb->data; 2801 2802 /* Remove the FCB from the skb 2803 * Remove the padded bytes, if there are any 2804 */ 2805 if (amount_pull) { 2806 skb_record_rx_queue(skb, fcb->rq); 2807 skb_pull(skb, amount_pull); 2808 } 2809 2810 /* Get receive timestamp from the skb */ 2811 if (priv->hwts_rx_en) { 2812 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2813 u64 *ns = (u64 *) skb->data; 2814 2815 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2816 shhwtstamps->hwtstamp = ns_to_ktime(*ns); 2817 } 2818 2819 if (priv->padding) 2820 skb_pull(skb, priv->padding); 2821 2822 if (dev->features & NETIF_F_RXCSUM) 2823 gfar_rx_checksum(skb, fcb); 2824 2825 /* Tell the skb what kind of packet this is */ 2826 skb->protocol = eth_type_trans(skb, dev); 2827 2828 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2829 * Even if vlan rx accel is disabled, on some chips 2830 * RXFCB_VLN is pseudo randomly set. 2831 */ 2832 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && 2833 fcb->flags & RXFCB_VLN) 2834 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); 2835 2836 /* Send the packet up the stack */ 2837 napi_gro_receive(napi, skb); 2838 2839 } 2840 2841 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2842 * until the budget/quota has been reached. Returns the number 2843 * of frames handled 2844 */ 2845 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 2846 { 2847 struct net_device *dev = rx_queue->dev; 2848 struct rxbd8 *bdp, *base; 2849 struct sk_buff *skb; 2850 int pkt_len; 2851 int amount_pull; 2852 int howmany = 0; 2853 struct gfar_private *priv = netdev_priv(dev); 2854 2855 /* Get the first full descriptor */ 2856 bdp = rx_queue->cur_rx; 2857 base = rx_queue->rx_bd_base; 2858 2859 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; 2860 2861 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { 2862 struct sk_buff *newskb; 2863 dma_addr_t bufaddr; 2864 2865 rmb(); 2866 2867 /* Add another skb for the future */ 2868 newskb = gfar_new_skb(dev, &bufaddr); 2869 2870 skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; 2871 2872 dma_unmap_single(priv->dev, bdp->bufPtr, 2873 priv->rx_buffer_size, DMA_FROM_DEVICE); 2874 2875 if (unlikely(!(bdp->status & RXBD_ERR) && 2876 bdp->length > priv->rx_buffer_size)) 2877 bdp->status = RXBD_LARGE; 2878 2879 /* We drop the frame if we failed to allocate a new buffer */ 2880 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || 2881 bdp->status & RXBD_ERR)) { 2882 count_errors(bdp->status, dev); 2883 2884 if (unlikely(!newskb)) { 2885 newskb = skb; 2886 bufaddr = bdp->bufPtr; 2887 } else if (skb) 2888 dev_kfree_skb(skb); 2889 } else { 2890 /* Increment the number of packets */ 2891 rx_queue->stats.rx_packets++; 2892 howmany++; 2893 2894 if (likely(skb)) { 2895 pkt_len = bdp->length - ETH_FCS_LEN; 2896 /* Remove the FCS from the packet length */ 2897 skb_put(skb, pkt_len); 2898 rx_queue->stats.rx_bytes += pkt_len; 2899 skb_record_rx_queue(skb, rx_queue->qindex); 2900 gfar_process_frame(dev, skb, amount_pull, 2901 &rx_queue->grp->napi_rx); 2902 2903 } else { 2904 netif_warn(priv, rx_err, dev, "Missing skb!\n"); 2905 rx_queue->stats.rx_dropped++; 2906 atomic64_inc(&priv->extra_stats.rx_skbmissing); 2907 } 2908 2909 } 2910 2911 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; 2912 2913 /* Setup the new bdp */ 2914 gfar_init_rxbdp(rx_queue, bdp, bufaddr); 2915 2916 /* Update Last Free RxBD pointer for LFC */ 2917 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en)) 2918 gfar_write(rx_queue->rfbptr, (u32)bdp); 2919 2920 /* Update to the next pointer */ 2921 bdp = next_bd(bdp, base, rx_queue->rx_ring_size); 2922 2923 /* update to point at the next skb */ 2924 rx_queue->skb_currx = (rx_queue->skb_currx + 1) & 2925 RX_RING_MOD_MASK(rx_queue->rx_ring_size); 2926 } 2927 2928 /* Update the current rxbd pointer to be the next one */ 2929 rx_queue->cur_rx = bdp; 2930 2931 return howmany; 2932 } 2933 2934 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget) 2935 { 2936 struct gfar_priv_grp *gfargrp = 2937 container_of(napi, struct gfar_priv_grp, napi_rx); 2938 struct gfar __iomem *regs = gfargrp->regs; 2939 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue; 2940 int work_done = 0; 2941 2942 /* Clear IEVENT, so interrupts aren't called again 2943 * because of the packets that have already arrived 2944 */ 2945 gfar_write(®s->ievent, IEVENT_RX_MASK); 2946 2947 work_done = gfar_clean_rx_ring(rx_queue, budget); 2948 2949 if (work_done < budget) { 2950 u32 imask; 2951 napi_complete(napi); 2952 /* Clear the halt bit in RSTAT */ 2953 gfar_write(®s->rstat, gfargrp->rstat); 2954 2955 spin_lock_irq(&gfargrp->grplock); 2956 imask = gfar_read(®s->imask); 2957 imask |= IMASK_RX_DEFAULT; 2958 gfar_write(®s->imask, imask); 2959 spin_unlock_irq(&gfargrp->grplock); 2960 } 2961 2962 return work_done; 2963 } 2964 2965 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget) 2966 { 2967 struct gfar_priv_grp *gfargrp = 2968 container_of(napi, struct gfar_priv_grp, napi_tx); 2969 struct gfar __iomem *regs = gfargrp->regs; 2970 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue; 2971 u32 imask; 2972 2973 /* Clear IEVENT, so interrupts aren't called again 2974 * because of the packets that have already arrived 2975 */ 2976 gfar_write(®s->ievent, IEVENT_TX_MASK); 2977 2978 /* run Tx cleanup to completion */ 2979 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) 2980 gfar_clean_tx_ring(tx_queue); 2981 2982 napi_complete(napi); 2983 2984 spin_lock_irq(&gfargrp->grplock); 2985 imask = gfar_read(®s->imask); 2986 imask |= IMASK_TX_DEFAULT; 2987 gfar_write(®s->imask, imask); 2988 spin_unlock_irq(&gfargrp->grplock); 2989 2990 return 0; 2991 } 2992 2993 static int gfar_poll_rx(struct napi_struct *napi, int budget) 2994 { 2995 struct gfar_priv_grp *gfargrp = 2996 container_of(napi, struct gfar_priv_grp, napi_rx); 2997 struct gfar_private *priv = gfargrp->priv; 2998 struct gfar __iomem *regs = gfargrp->regs; 2999 struct gfar_priv_rx_q *rx_queue = NULL; 3000 int work_done = 0, work_done_per_q = 0; 3001 int i, budget_per_q = 0; 3002 unsigned long rstat_rxf; 3003 int num_act_queues; 3004 3005 /* Clear IEVENT, so interrupts aren't called again 3006 * because of the packets that have already arrived 3007 */ 3008 gfar_write(®s->ievent, IEVENT_RX_MASK); 3009 3010 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 3011 3012 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 3013 if (num_act_queues) 3014 budget_per_q = budget/num_act_queues; 3015 3016 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 3017 /* skip queue if not active */ 3018 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 3019 continue; 3020 3021 rx_queue = priv->rx_queue[i]; 3022 work_done_per_q = 3023 gfar_clean_rx_ring(rx_queue, budget_per_q); 3024 work_done += work_done_per_q; 3025 3026 /* finished processing this queue */ 3027 if (work_done_per_q < budget_per_q) { 3028 /* clear active queue hw indication */ 3029 gfar_write(®s->rstat, 3030 RSTAT_CLEAR_RXF0 >> i); 3031 num_act_queues--; 3032 3033 if (!num_act_queues) 3034 break; 3035 } 3036 } 3037 3038 if (!num_act_queues) { 3039 u32 imask; 3040 napi_complete(napi); 3041 3042 /* Clear the halt bit in RSTAT */ 3043 gfar_write(®s->rstat, gfargrp->rstat); 3044 3045 spin_lock_irq(&gfargrp->grplock); 3046 imask = gfar_read(®s->imask); 3047 imask |= IMASK_RX_DEFAULT; 3048 gfar_write(®s->imask, imask); 3049 spin_unlock_irq(&gfargrp->grplock); 3050 } 3051 3052 return work_done; 3053 } 3054 3055 static int gfar_poll_tx(struct napi_struct *napi, int budget) 3056 { 3057 struct gfar_priv_grp *gfargrp = 3058 container_of(napi, struct gfar_priv_grp, napi_tx); 3059 struct gfar_private *priv = gfargrp->priv; 3060 struct gfar __iomem *regs = gfargrp->regs; 3061 struct gfar_priv_tx_q *tx_queue = NULL; 3062 int has_tx_work = 0; 3063 int i; 3064 3065 /* Clear IEVENT, so interrupts aren't called again 3066 * because of the packets that have already arrived 3067 */ 3068 gfar_write(®s->ievent, IEVENT_TX_MASK); 3069 3070 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 3071 tx_queue = priv->tx_queue[i]; 3072 /* run Tx cleanup to completion */ 3073 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 3074 gfar_clean_tx_ring(tx_queue); 3075 has_tx_work = 1; 3076 } 3077 } 3078 3079 if (!has_tx_work) { 3080 u32 imask; 3081 napi_complete(napi); 3082 3083 spin_lock_irq(&gfargrp->grplock); 3084 imask = gfar_read(®s->imask); 3085 imask |= IMASK_TX_DEFAULT; 3086 gfar_write(®s->imask, imask); 3087 spin_unlock_irq(&gfargrp->grplock); 3088 } 3089 3090 return 0; 3091 } 3092 3093 3094 #ifdef CONFIG_NET_POLL_CONTROLLER 3095 /* Polling 'interrupt' - used by things like netconsole to send skbs 3096 * without having to re-enable interrupts. It's not called while 3097 * the interrupt routine is executing. 3098 */ 3099 static void gfar_netpoll(struct net_device *dev) 3100 { 3101 struct gfar_private *priv = netdev_priv(dev); 3102 int i; 3103 3104 /* If the device has multiple interrupts, run tx/rx */ 3105 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 3106 for (i = 0; i < priv->num_grps; i++) { 3107 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3108 3109 disable_irq(gfar_irq(grp, TX)->irq); 3110 disable_irq(gfar_irq(grp, RX)->irq); 3111 disable_irq(gfar_irq(grp, ER)->irq); 3112 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3113 enable_irq(gfar_irq(grp, ER)->irq); 3114 enable_irq(gfar_irq(grp, RX)->irq); 3115 enable_irq(gfar_irq(grp, TX)->irq); 3116 } 3117 } else { 3118 for (i = 0; i < priv->num_grps; i++) { 3119 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 3120 3121 disable_irq(gfar_irq(grp, TX)->irq); 3122 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 3123 enable_irq(gfar_irq(grp, TX)->irq); 3124 } 3125 } 3126 } 3127 #endif 3128 3129 /* The interrupt handler for devices with one interrupt */ 3130 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 3131 { 3132 struct gfar_priv_grp *gfargrp = grp_id; 3133 3134 /* Save ievent for future reference */ 3135 u32 events = gfar_read(&gfargrp->regs->ievent); 3136 3137 /* Check for reception */ 3138 if (events & IEVENT_RX_MASK) 3139 gfar_receive(irq, grp_id); 3140 3141 /* Check for transmit completion */ 3142 if (events & IEVENT_TX_MASK) 3143 gfar_transmit(irq, grp_id); 3144 3145 /* Check for errors */ 3146 if (events & IEVENT_ERR_MASK) 3147 gfar_error(irq, grp_id); 3148 3149 return IRQ_HANDLED; 3150 } 3151 3152 /* Called every time the controller might need to be made 3153 * aware of new link state. The PHY code conveys this 3154 * information through variables in the phydev structure, and this 3155 * function converts those variables into the appropriate 3156 * register values, and can bring down the device if needed. 3157 */ 3158 static void adjust_link(struct net_device *dev) 3159 { 3160 struct gfar_private *priv = netdev_priv(dev); 3161 struct phy_device *phydev = priv->phydev; 3162 3163 if (unlikely(phydev->link != priv->oldlink || 3164 phydev->duplex != priv->oldduplex || 3165 phydev->speed != priv->oldspeed)) 3166 gfar_update_link_state(priv); 3167 } 3168 3169 /* Update the hash table based on the current list of multicast 3170 * addresses we subscribe to. Also, change the promiscuity of 3171 * the device based on the flags (this function is called 3172 * whenever dev->flags is changed 3173 */ 3174 static void gfar_set_multi(struct net_device *dev) 3175 { 3176 struct netdev_hw_addr *ha; 3177 struct gfar_private *priv = netdev_priv(dev); 3178 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3179 u32 tempval; 3180 3181 if (dev->flags & IFF_PROMISC) { 3182 /* Set RCTRL to PROM */ 3183 tempval = gfar_read(®s->rctrl); 3184 tempval |= RCTRL_PROM; 3185 gfar_write(®s->rctrl, tempval); 3186 } else { 3187 /* Set RCTRL to not PROM */ 3188 tempval = gfar_read(®s->rctrl); 3189 tempval &= ~(RCTRL_PROM); 3190 gfar_write(®s->rctrl, tempval); 3191 } 3192 3193 if (dev->flags & IFF_ALLMULTI) { 3194 /* Set the hash to rx all multicast frames */ 3195 gfar_write(®s->igaddr0, 0xffffffff); 3196 gfar_write(®s->igaddr1, 0xffffffff); 3197 gfar_write(®s->igaddr2, 0xffffffff); 3198 gfar_write(®s->igaddr3, 0xffffffff); 3199 gfar_write(®s->igaddr4, 0xffffffff); 3200 gfar_write(®s->igaddr5, 0xffffffff); 3201 gfar_write(®s->igaddr6, 0xffffffff); 3202 gfar_write(®s->igaddr7, 0xffffffff); 3203 gfar_write(®s->gaddr0, 0xffffffff); 3204 gfar_write(®s->gaddr1, 0xffffffff); 3205 gfar_write(®s->gaddr2, 0xffffffff); 3206 gfar_write(®s->gaddr3, 0xffffffff); 3207 gfar_write(®s->gaddr4, 0xffffffff); 3208 gfar_write(®s->gaddr5, 0xffffffff); 3209 gfar_write(®s->gaddr6, 0xffffffff); 3210 gfar_write(®s->gaddr7, 0xffffffff); 3211 } else { 3212 int em_num; 3213 int idx; 3214 3215 /* zero out the hash */ 3216 gfar_write(®s->igaddr0, 0x0); 3217 gfar_write(®s->igaddr1, 0x0); 3218 gfar_write(®s->igaddr2, 0x0); 3219 gfar_write(®s->igaddr3, 0x0); 3220 gfar_write(®s->igaddr4, 0x0); 3221 gfar_write(®s->igaddr5, 0x0); 3222 gfar_write(®s->igaddr6, 0x0); 3223 gfar_write(®s->igaddr7, 0x0); 3224 gfar_write(®s->gaddr0, 0x0); 3225 gfar_write(®s->gaddr1, 0x0); 3226 gfar_write(®s->gaddr2, 0x0); 3227 gfar_write(®s->gaddr3, 0x0); 3228 gfar_write(®s->gaddr4, 0x0); 3229 gfar_write(®s->gaddr5, 0x0); 3230 gfar_write(®s->gaddr6, 0x0); 3231 gfar_write(®s->gaddr7, 0x0); 3232 3233 /* If we have extended hash tables, we need to 3234 * clear the exact match registers to prepare for 3235 * setting them 3236 */ 3237 if (priv->extended_hash) { 3238 em_num = GFAR_EM_NUM + 1; 3239 gfar_clear_exact_match(dev); 3240 idx = 1; 3241 } else { 3242 idx = 0; 3243 em_num = 0; 3244 } 3245 3246 if (netdev_mc_empty(dev)) 3247 return; 3248 3249 /* Parse the list, and set the appropriate bits */ 3250 netdev_for_each_mc_addr(ha, dev) { 3251 if (idx < em_num) { 3252 gfar_set_mac_for_addr(dev, idx, ha->addr); 3253 idx++; 3254 } else 3255 gfar_set_hash_for_addr(dev, ha->addr); 3256 } 3257 } 3258 } 3259 3260 3261 /* Clears each of the exact match registers to zero, so they 3262 * don't interfere with normal reception 3263 */ 3264 static void gfar_clear_exact_match(struct net_device *dev) 3265 { 3266 int idx; 3267 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3268 3269 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3270 gfar_set_mac_for_addr(dev, idx, zero_arr); 3271 } 3272 3273 /* Set the appropriate hash bit for the given addr */ 3274 /* The algorithm works like so: 3275 * 1) Take the Destination Address (ie the multicast address), and 3276 * do a CRC on it (little endian), and reverse the bits of the 3277 * result. 3278 * 2) Use the 8 most significant bits as a hash into a 256-entry 3279 * table. The table is controlled through 8 32-bit registers: 3280 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3281 * gaddr7. This means that the 3 most significant bits in the 3282 * hash index which gaddr register to use, and the 5 other bits 3283 * indicate which bit (assuming an IBM numbering scheme, which 3284 * for PowerPC (tm) is usually the case) in the register holds 3285 * the entry. 3286 */ 3287 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3288 { 3289 u32 tempval; 3290 struct gfar_private *priv = netdev_priv(dev); 3291 u32 result = ether_crc(ETH_ALEN, addr); 3292 int width = priv->hash_width; 3293 u8 whichbit = (result >> (32 - width)) & 0x1f; 3294 u8 whichreg = result >> (32 - width + 5); 3295 u32 value = (1 << (31-whichbit)); 3296 3297 tempval = gfar_read(priv->hash_regs[whichreg]); 3298 tempval |= value; 3299 gfar_write(priv->hash_regs[whichreg], tempval); 3300 } 3301 3302 3303 /* There are multiple MAC Address register pairs on some controllers 3304 * This function sets the numth pair to a given address 3305 */ 3306 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3307 const u8 *addr) 3308 { 3309 struct gfar_private *priv = netdev_priv(dev); 3310 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3311 u32 tempval; 3312 u32 __iomem *macptr = ®s->macstnaddr1; 3313 3314 macptr += num*2; 3315 3316 /* For a station address of 0x12345678ABCD in transmission 3317 * order (BE), MACnADDR1 is set to 0xCDAB7856 and 3318 * MACnADDR2 is set to 0x34120000. 3319 */ 3320 tempval = (addr[5] << 24) | (addr[4] << 16) | 3321 (addr[3] << 8) | addr[2]; 3322 3323 gfar_write(macptr, tempval); 3324 3325 tempval = (addr[1] << 24) | (addr[0] << 16); 3326 3327 gfar_write(macptr+1, tempval); 3328 } 3329 3330 /* GFAR error interrupt handler */ 3331 static irqreturn_t gfar_error(int irq, void *grp_id) 3332 { 3333 struct gfar_priv_grp *gfargrp = grp_id; 3334 struct gfar __iomem *regs = gfargrp->regs; 3335 struct gfar_private *priv= gfargrp->priv; 3336 struct net_device *dev = priv->ndev; 3337 3338 /* Save ievent for future reference */ 3339 u32 events = gfar_read(®s->ievent); 3340 3341 /* Clear IEVENT */ 3342 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3343 3344 /* Magic Packet is not an error. */ 3345 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3346 (events & IEVENT_MAG)) 3347 events &= ~IEVENT_MAG; 3348 3349 /* Hmm... */ 3350 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3351 netdev_dbg(dev, 3352 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3353 events, gfar_read(®s->imask)); 3354 3355 /* Update the error counters */ 3356 if (events & IEVENT_TXE) { 3357 dev->stats.tx_errors++; 3358 3359 if (events & IEVENT_LC) 3360 dev->stats.tx_window_errors++; 3361 if (events & IEVENT_CRL) 3362 dev->stats.tx_aborted_errors++; 3363 if (events & IEVENT_XFUN) { 3364 unsigned long flags; 3365 3366 netif_dbg(priv, tx_err, dev, 3367 "TX FIFO underrun, packet dropped\n"); 3368 dev->stats.tx_dropped++; 3369 atomic64_inc(&priv->extra_stats.tx_underrun); 3370 3371 local_irq_save(flags); 3372 lock_tx_qs(priv); 3373 3374 /* Reactivate the Tx Queues */ 3375 gfar_write(®s->tstat, gfargrp->tstat); 3376 3377 unlock_tx_qs(priv); 3378 local_irq_restore(flags); 3379 } 3380 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3381 } 3382 if (events & IEVENT_BSY) { 3383 dev->stats.rx_errors++; 3384 atomic64_inc(&priv->extra_stats.rx_bsy); 3385 3386 gfar_receive(irq, grp_id); 3387 3388 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3389 gfar_read(®s->rstat)); 3390 } 3391 if (events & IEVENT_BABR) { 3392 dev->stats.rx_errors++; 3393 atomic64_inc(&priv->extra_stats.rx_babr); 3394 3395 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3396 } 3397 if (events & IEVENT_EBERR) { 3398 atomic64_inc(&priv->extra_stats.eberr); 3399 netif_dbg(priv, rx_err, dev, "bus error\n"); 3400 } 3401 if (events & IEVENT_RXC) 3402 netif_dbg(priv, rx_status, dev, "control frame\n"); 3403 3404 if (events & IEVENT_BABT) { 3405 atomic64_inc(&priv->extra_stats.tx_babt); 3406 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3407 } 3408 return IRQ_HANDLED; 3409 } 3410 3411 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) 3412 { 3413 struct phy_device *phydev = priv->phydev; 3414 u32 val = 0; 3415 3416 if (!phydev->duplex) 3417 return val; 3418 3419 if (!priv->pause_aneg_en) { 3420 if (priv->tx_pause_en) 3421 val |= MACCFG1_TX_FLOW; 3422 if (priv->rx_pause_en) 3423 val |= MACCFG1_RX_FLOW; 3424 } else { 3425 u16 lcl_adv, rmt_adv; 3426 u8 flowctrl; 3427 /* get link partner capabilities */ 3428 rmt_adv = 0; 3429 if (phydev->pause) 3430 rmt_adv = LPA_PAUSE_CAP; 3431 if (phydev->asym_pause) 3432 rmt_adv |= LPA_PAUSE_ASYM; 3433 3434 lcl_adv = 0; 3435 if (phydev->advertising & ADVERTISED_Pause) 3436 lcl_adv |= ADVERTISE_PAUSE_CAP; 3437 if (phydev->advertising & ADVERTISED_Asym_Pause) 3438 lcl_adv |= ADVERTISE_PAUSE_ASYM; 3439 3440 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 3441 if (flowctrl & FLOW_CTRL_TX) 3442 val |= MACCFG1_TX_FLOW; 3443 if (flowctrl & FLOW_CTRL_RX) 3444 val |= MACCFG1_RX_FLOW; 3445 } 3446 3447 return val; 3448 } 3449 3450 static noinline void gfar_update_link_state(struct gfar_private *priv) 3451 { 3452 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3453 struct phy_device *phydev = priv->phydev; 3454 struct gfar_priv_rx_q *rx_queue = NULL; 3455 int i; 3456 struct rxbd8 *bdp; 3457 3458 if (unlikely(test_bit(GFAR_RESETTING, &priv->state))) 3459 return; 3460 3461 if (phydev->link) { 3462 u32 tempval1 = gfar_read(®s->maccfg1); 3463 u32 tempval = gfar_read(®s->maccfg2); 3464 u32 ecntrl = gfar_read(®s->ecntrl); 3465 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW); 3466 3467 if (phydev->duplex != priv->oldduplex) { 3468 if (!(phydev->duplex)) 3469 tempval &= ~(MACCFG2_FULL_DUPLEX); 3470 else 3471 tempval |= MACCFG2_FULL_DUPLEX; 3472 3473 priv->oldduplex = phydev->duplex; 3474 } 3475 3476 if (phydev->speed != priv->oldspeed) { 3477 switch (phydev->speed) { 3478 case 1000: 3479 tempval = 3480 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3481 3482 ecntrl &= ~(ECNTRL_R100); 3483 break; 3484 case 100: 3485 case 10: 3486 tempval = 3487 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3488 3489 /* Reduced mode distinguishes 3490 * between 10 and 100 3491 */ 3492 if (phydev->speed == SPEED_100) 3493 ecntrl |= ECNTRL_R100; 3494 else 3495 ecntrl &= ~(ECNTRL_R100); 3496 break; 3497 default: 3498 netif_warn(priv, link, priv->ndev, 3499 "Ack! Speed (%d) is not 10/100/1000!\n", 3500 phydev->speed); 3501 break; 3502 } 3503 3504 priv->oldspeed = phydev->speed; 3505 } 3506 3507 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 3508 tempval1 |= gfar_get_flowctrl_cfg(priv); 3509 3510 /* Turn last free buffer recording on */ 3511 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) { 3512 for (i = 0; i < priv->num_rx_queues; i++) { 3513 rx_queue = priv->rx_queue[i]; 3514 bdp = rx_queue->cur_rx; 3515 /* skip to previous bd */ 3516 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1, 3517 rx_queue->rx_bd_base, 3518 rx_queue->rx_ring_size); 3519 3520 if (rx_queue->rfbptr) 3521 gfar_write(rx_queue->rfbptr, (u32)bdp); 3522 } 3523 3524 priv->tx_actual_en = 1; 3525 } 3526 3527 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval)) 3528 priv->tx_actual_en = 0; 3529 3530 gfar_write(®s->maccfg1, tempval1); 3531 gfar_write(®s->maccfg2, tempval); 3532 gfar_write(®s->ecntrl, ecntrl); 3533 3534 if (!priv->oldlink) 3535 priv->oldlink = 1; 3536 3537 } else if (priv->oldlink) { 3538 priv->oldlink = 0; 3539 priv->oldspeed = 0; 3540 priv->oldduplex = -1; 3541 } 3542 3543 if (netif_msg_link(priv)) 3544 phy_print_status(phydev); 3545 } 3546 3547 static struct of_device_id gfar_match[] = 3548 { 3549 { 3550 .type = "network", 3551 .compatible = "gianfar", 3552 }, 3553 { 3554 .compatible = "fsl,etsec2", 3555 }, 3556 {}, 3557 }; 3558 MODULE_DEVICE_TABLE(of, gfar_match); 3559 3560 /* Structure for a device driver */ 3561 static struct platform_driver gfar_driver = { 3562 .driver = { 3563 .name = "fsl-gianfar", 3564 .pm = GFAR_PM_OPS, 3565 .of_match_table = gfar_match, 3566 }, 3567 .probe = gfar_probe, 3568 .remove = gfar_remove, 3569 }; 3570 3571 module_platform_driver(gfar_driver); 3572