1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* drivers/net/ethernet/freescale/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12  *
13  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
14  * Copyright 2007 MontaVista Software, Inc.
15  *
16  *  Gianfar:  AKA Lambda Draconis, "Dragon"
17  *  RA 11 31 24.2
18  *  Dec +69 19 52
19  *  V 3.84
20  *  B-V +1.62
21  *
22  *  Theory of operation
23  *
24  *  The driver is initialized through of_device. Configuration information
25  *  is therefore conveyed through an OF-style device tree.
26  *
27  *  The Gianfar Ethernet Controller uses a ring of buffer
28  *  descriptors.  The beginning is indicated by a register
29  *  pointing to the physical address of the start of the ring.
30  *  The end is determined by a "wrap" bit being set in the
31  *  last descriptor of the ring.
32  *
33  *  When a packet is received, the RXF bit in the
34  *  IEVENT register is set, triggering an interrupt when the
35  *  corresponding bit in the IMASK register is also set (if
36  *  interrupt coalescing is active, then the interrupt may not
37  *  happen immediately, but will wait until either a set number
38  *  of frames or amount of time have passed).  In NAPI, the
39  *  interrupt handler will signal there is work to be done, and
40  *  exit. This method will start at the last known empty
41  *  descriptor, and process every subsequent descriptor until there
42  *  are none left with data (NAPI will stop after a set number of
43  *  packets to give time to other tasks, but will eventually
44  *  process all the packets).  The data arrives inside a
45  *  pre-allocated skb, and so after the skb is passed up to the
46  *  stack, a new skb must be allocated, and the address field in
47  *  the buffer descriptor must be updated to indicate this new
48  *  skb.
49  *
50  *  When the kernel requests that a packet be transmitted, the
51  *  driver starts where it left off last time, and points the
52  *  descriptor at the buffer which was passed in.  The driver
53  *  then informs the DMA engine that there are packets ready to
54  *  be transmitted.  Once the controller is finished transmitting
55  *  the packet, an interrupt may be triggered (under the same
56  *  conditions as for reception, but depending on the TXF bit).
57  *  The driver then cleans up the buffer.
58  */
59 
60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61 #define DEBUG
62 
63 #include <linux/kernel.h>
64 #include <linux/string.h>
65 #include <linux/errno.h>
66 #include <linux/unistd.h>
67 #include <linux/slab.h>
68 #include <linux/interrupt.h>
69 #include <linux/delay.h>
70 #include <linux/netdevice.h>
71 #include <linux/etherdevice.h>
72 #include <linux/skbuff.h>
73 #include <linux/if_vlan.h>
74 #include <linux/spinlock.h>
75 #include <linux/mm.h>
76 #include <linux/of_address.h>
77 #include <linux/of_irq.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84 #include <linux/net_tstamp.h>
85 
86 #include <asm/io.h>
87 #ifdef CONFIG_PPC
88 #include <asm/reg.h>
89 #include <asm/mpc85xx.h>
90 #endif
91 #include <asm/irq.h>
92 #include <linux/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
99 #include <linux/of.h>
100 #include <linux/of_net.h>
101 
102 #include "gianfar.h"
103 
104 #define TX_TIMEOUT      (5*HZ)
105 
106 const char gfar_driver_version[] = "2.0";
107 
108 MODULE_AUTHOR("Freescale Semiconductor, Inc");
109 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
110 MODULE_LICENSE("GPL");
111 
112 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
113 			    dma_addr_t buf)
114 {
115 	u32 lstatus;
116 
117 	bdp->bufPtr = cpu_to_be32(buf);
118 
119 	lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
120 	if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
121 		lstatus |= BD_LFLAG(RXBD_WRAP);
122 
123 	gfar_wmb();
124 
125 	bdp->lstatus = cpu_to_be32(lstatus);
126 }
127 
128 static void gfar_init_tx_rx_base(struct gfar_private *priv)
129 {
130 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
131 	u32 __iomem *baddr;
132 	int i;
133 
134 	baddr = &regs->tbase0;
135 	for (i = 0; i < priv->num_tx_queues; i++) {
136 		gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
137 		baddr += 2;
138 	}
139 
140 	baddr = &regs->rbase0;
141 	for (i = 0; i < priv->num_rx_queues; i++) {
142 		gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
143 		baddr += 2;
144 	}
145 }
146 
147 static void gfar_init_rqprm(struct gfar_private *priv)
148 {
149 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
150 	u32 __iomem *baddr;
151 	int i;
152 
153 	baddr = &regs->rqprm0;
154 	for (i = 0; i < priv->num_rx_queues; i++) {
155 		gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
156 			   (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
157 		baddr++;
158 	}
159 }
160 
161 static void gfar_rx_offload_en(struct gfar_private *priv)
162 {
163 	/* set this when rx hw offload (TOE) functions are being used */
164 	priv->uses_rxfcb = 0;
165 
166 	if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
167 		priv->uses_rxfcb = 1;
168 
169 	if (priv->hwts_rx_en || priv->rx_filer_enable)
170 		priv->uses_rxfcb = 1;
171 }
172 
173 static void gfar_mac_rx_config(struct gfar_private *priv)
174 {
175 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 	u32 rctrl = 0;
177 
178 	if (priv->rx_filer_enable) {
179 		rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
180 		/* Program the RIR0 reg with the required distribution */
181 		if (priv->poll_mode == GFAR_SQ_POLLING)
182 			gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
183 		else /* GFAR_MQ_POLLING */
184 			gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
185 	}
186 
187 	/* Restore PROMISC mode */
188 	if (priv->ndev->flags & IFF_PROMISC)
189 		rctrl |= RCTRL_PROM;
190 
191 	if (priv->ndev->features & NETIF_F_RXCSUM)
192 		rctrl |= RCTRL_CHECKSUMMING;
193 
194 	if (priv->extended_hash)
195 		rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
196 
197 	if (priv->padding) {
198 		rctrl &= ~RCTRL_PAL_MASK;
199 		rctrl |= RCTRL_PADDING(priv->padding);
200 	}
201 
202 	/* Enable HW time stamping if requested from user space */
203 	if (priv->hwts_rx_en)
204 		rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
205 
206 	if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
207 		rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
208 
209 	/* Clear the LFC bit */
210 	gfar_write(&regs->rctrl, rctrl);
211 	/* Init flow control threshold values */
212 	gfar_init_rqprm(priv);
213 	gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
214 	rctrl |= RCTRL_LFC;
215 
216 	/* Init rctrl based on our settings */
217 	gfar_write(&regs->rctrl, rctrl);
218 }
219 
220 static void gfar_mac_tx_config(struct gfar_private *priv)
221 {
222 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
223 	u32 tctrl = 0;
224 
225 	if (priv->ndev->features & NETIF_F_IP_CSUM)
226 		tctrl |= TCTRL_INIT_CSUM;
227 
228 	if (priv->prio_sched_en)
229 		tctrl |= TCTRL_TXSCHED_PRIO;
230 	else {
231 		tctrl |= TCTRL_TXSCHED_WRRS;
232 		gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
233 		gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
234 	}
235 
236 	if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
237 		tctrl |= TCTRL_VLINS;
238 
239 	gfar_write(&regs->tctrl, tctrl);
240 }
241 
242 static void gfar_configure_coalescing(struct gfar_private *priv,
243 			       unsigned long tx_mask, unsigned long rx_mask)
244 {
245 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
246 	u32 __iomem *baddr;
247 
248 	if (priv->mode == MQ_MG_MODE) {
249 		int i = 0;
250 
251 		baddr = &regs->txic0;
252 		for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
253 			gfar_write(baddr + i, 0);
254 			if (likely(priv->tx_queue[i]->txcoalescing))
255 				gfar_write(baddr + i, priv->tx_queue[i]->txic);
256 		}
257 
258 		baddr = &regs->rxic0;
259 		for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
260 			gfar_write(baddr + i, 0);
261 			if (likely(priv->rx_queue[i]->rxcoalescing))
262 				gfar_write(baddr + i, priv->rx_queue[i]->rxic);
263 		}
264 	} else {
265 		/* Backward compatible case -- even if we enable
266 		 * multiple queues, there's only single reg to program
267 		 */
268 		gfar_write(&regs->txic, 0);
269 		if (likely(priv->tx_queue[0]->txcoalescing))
270 			gfar_write(&regs->txic, priv->tx_queue[0]->txic);
271 
272 		gfar_write(&regs->rxic, 0);
273 		if (unlikely(priv->rx_queue[0]->rxcoalescing))
274 			gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
275 	}
276 }
277 
278 static void gfar_configure_coalescing_all(struct gfar_private *priv)
279 {
280 	gfar_configure_coalescing(priv, 0xFF, 0xFF);
281 }
282 
283 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
284 {
285 	struct gfar_private *priv = netdev_priv(dev);
286 	unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
287 	unsigned long tx_packets = 0, tx_bytes = 0;
288 	int i;
289 
290 	for (i = 0; i < priv->num_rx_queues; i++) {
291 		rx_packets += priv->rx_queue[i]->stats.rx_packets;
292 		rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
293 		rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
294 	}
295 
296 	dev->stats.rx_packets = rx_packets;
297 	dev->stats.rx_bytes   = rx_bytes;
298 	dev->stats.rx_dropped = rx_dropped;
299 
300 	for (i = 0; i < priv->num_tx_queues; i++) {
301 		tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
302 		tx_packets += priv->tx_queue[i]->stats.tx_packets;
303 	}
304 
305 	dev->stats.tx_bytes   = tx_bytes;
306 	dev->stats.tx_packets = tx_packets;
307 
308 	return &dev->stats;
309 }
310 
311 /* Set the appropriate hash bit for the given addr */
312 /* The algorithm works like so:
313  * 1) Take the Destination Address (ie the multicast address), and
314  * do a CRC on it (little endian), and reverse the bits of the
315  * result.
316  * 2) Use the 8 most significant bits as a hash into a 256-entry
317  * table.  The table is controlled through 8 32-bit registers:
318  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
319  * gaddr7.  This means that the 3 most significant bits in the
320  * hash index which gaddr register to use, and the 5 other bits
321  * indicate which bit (assuming an IBM numbering scheme, which
322  * for PowerPC (tm) is usually the case) in the register holds
323  * the entry.
324  */
325 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
326 {
327 	u32 tempval;
328 	struct gfar_private *priv = netdev_priv(dev);
329 	u32 result = ether_crc(ETH_ALEN, addr);
330 	int width = priv->hash_width;
331 	u8 whichbit = (result >> (32 - width)) & 0x1f;
332 	u8 whichreg = result >> (32 - width + 5);
333 	u32 value = (1 << (31-whichbit));
334 
335 	tempval = gfar_read(priv->hash_regs[whichreg]);
336 	tempval |= value;
337 	gfar_write(priv->hash_regs[whichreg], tempval);
338 }
339 
340 /* There are multiple MAC Address register pairs on some controllers
341  * This function sets the numth pair to a given address
342  */
343 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
344 				  const u8 *addr)
345 {
346 	struct gfar_private *priv = netdev_priv(dev);
347 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
348 	u32 tempval;
349 	u32 __iomem *macptr = &regs->macstnaddr1;
350 
351 	macptr += num*2;
352 
353 	/* For a station address of 0x12345678ABCD in transmission
354 	 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
355 	 * MACnADDR2 is set to 0x34120000.
356 	 */
357 	tempval = (addr[5] << 24) | (addr[4] << 16) |
358 		  (addr[3] << 8)  |  addr[2];
359 
360 	gfar_write(macptr, tempval);
361 
362 	tempval = (addr[1] << 24) | (addr[0] << 16);
363 
364 	gfar_write(macptr+1, tempval);
365 }
366 
367 static int gfar_set_mac_addr(struct net_device *dev, void *p)
368 {
369 	eth_mac_addr(dev, p);
370 
371 	gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
372 
373 	return 0;
374 }
375 
376 static void gfar_ints_disable(struct gfar_private *priv)
377 {
378 	int i;
379 	for (i = 0; i < priv->num_grps; i++) {
380 		struct gfar __iomem *regs = priv->gfargrp[i].regs;
381 		/* Clear IEVENT */
382 		gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
383 
384 		/* Initialize IMASK */
385 		gfar_write(&regs->imask, IMASK_INIT_CLEAR);
386 	}
387 }
388 
389 static void gfar_ints_enable(struct gfar_private *priv)
390 {
391 	int i;
392 	for (i = 0; i < priv->num_grps; i++) {
393 		struct gfar __iomem *regs = priv->gfargrp[i].regs;
394 		/* Unmask the interrupts we look for */
395 		gfar_write(&regs->imask, IMASK_DEFAULT);
396 	}
397 }
398 
399 static int gfar_alloc_tx_queues(struct gfar_private *priv)
400 {
401 	int i;
402 
403 	for (i = 0; i < priv->num_tx_queues; i++) {
404 		priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
405 					    GFP_KERNEL);
406 		if (!priv->tx_queue[i])
407 			return -ENOMEM;
408 
409 		priv->tx_queue[i]->tx_skbuff = NULL;
410 		priv->tx_queue[i]->qindex = i;
411 		priv->tx_queue[i]->dev = priv->ndev;
412 		spin_lock_init(&(priv->tx_queue[i]->txlock));
413 	}
414 	return 0;
415 }
416 
417 static int gfar_alloc_rx_queues(struct gfar_private *priv)
418 {
419 	int i;
420 
421 	for (i = 0; i < priv->num_rx_queues; i++) {
422 		priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
423 					    GFP_KERNEL);
424 		if (!priv->rx_queue[i])
425 			return -ENOMEM;
426 
427 		priv->rx_queue[i]->qindex = i;
428 		priv->rx_queue[i]->ndev = priv->ndev;
429 	}
430 	return 0;
431 }
432 
433 static void gfar_free_tx_queues(struct gfar_private *priv)
434 {
435 	int i;
436 
437 	for (i = 0; i < priv->num_tx_queues; i++)
438 		kfree(priv->tx_queue[i]);
439 }
440 
441 static void gfar_free_rx_queues(struct gfar_private *priv)
442 {
443 	int i;
444 
445 	for (i = 0; i < priv->num_rx_queues; i++)
446 		kfree(priv->rx_queue[i]);
447 }
448 
449 static void unmap_group_regs(struct gfar_private *priv)
450 {
451 	int i;
452 
453 	for (i = 0; i < MAXGROUPS; i++)
454 		if (priv->gfargrp[i].regs)
455 			iounmap(priv->gfargrp[i].regs);
456 }
457 
458 static void free_gfar_dev(struct gfar_private *priv)
459 {
460 	int i, j;
461 
462 	for (i = 0; i < priv->num_grps; i++)
463 		for (j = 0; j < GFAR_NUM_IRQS; j++) {
464 			kfree(priv->gfargrp[i].irqinfo[j]);
465 			priv->gfargrp[i].irqinfo[j] = NULL;
466 		}
467 
468 	free_netdev(priv->ndev);
469 }
470 
471 static void disable_napi(struct gfar_private *priv)
472 {
473 	int i;
474 
475 	for (i = 0; i < priv->num_grps; i++) {
476 		napi_disable(&priv->gfargrp[i].napi_rx);
477 		napi_disable(&priv->gfargrp[i].napi_tx);
478 	}
479 }
480 
481 static void enable_napi(struct gfar_private *priv)
482 {
483 	int i;
484 
485 	for (i = 0; i < priv->num_grps; i++) {
486 		napi_enable(&priv->gfargrp[i].napi_rx);
487 		napi_enable(&priv->gfargrp[i].napi_tx);
488 	}
489 }
490 
491 static int gfar_parse_group(struct device_node *np,
492 			    struct gfar_private *priv, const char *model)
493 {
494 	struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
495 	int i;
496 
497 	for (i = 0; i < GFAR_NUM_IRQS; i++) {
498 		grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
499 					  GFP_KERNEL);
500 		if (!grp->irqinfo[i])
501 			return -ENOMEM;
502 	}
503 
504 	grp->regs = of_iomap(np, 0);
505 	if (!grp->regs)
506 		return -ENOMEM;
507 
508 	gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
509 
510 	/* If we aren't the FEC we have multiple interrupts */
511 	if (model && strcasecmp(model, "FEC")) {
512 		gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
513 		gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
514 		if (!gfar_irq(grp, TX)->irq ||
515 		    !gfar_irq(grp, RX)->irq ||
516 		    !gfar_irq(grp, ER)->irq)
517 			return -EINVAL;
518 	}
519 
520 	grp->priv = priv;
521 	spin_lock_init(&grp->grplock);
522 	if (priv->mode == MQ_MG_MODE) {
523 		u32 rxq_mask, txq_mask;
524 		int ret;
525 
526 		grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
527 		grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
528 
529 		ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
530 		if (!ret) {
531 			grp->rx_bit_map = rxq_mask ?
532 			rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
533 		}
534 
535 		ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
536 		if (!ret) {
537 			grp->tx_bit_map = txq_mask ?
538 			txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
539 		}
540 
541 		if (priv->poll_mode == GFAR_SQ_POLLING) {
542 			/* One Q per interrupt group: Q0 to G0, Q1 to G1 */
543 			grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
544 			grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
545 		}
546 	} else {
547 		grp->rx_bit_map = 0xFF;
548 		grp->tx_bit_map = 0xFF;
549 	}
550 
551 	/* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
552 	 * right to left, so we need to revert the 8 bits to get the q index
553 	 */
554 	grp->rx_bit_map = bitrev8(grp->rx_bit_map);
555 	grp->tx_bit_map = bitrev8(grp->tx_bit_map);
556 
557 	/* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
558 	 * also assign queues to groups
559 	 */
560 	for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
561 		if (!grp->rx_queue)
562 			grp->rx_queue = priv->rx_queue[i];
563 		grp->num_rx_queues++;
564 		grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
565 		priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
566 		priv->rx_queue[i]->grp = grp;
567 	}
568 
569 	for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
570 		if (!grp->tx_queue)
571 			grp->tx_queue = priv->tx_queue[i];
572 		grp->num_tx_queues++;
573 		grp->tstat |= (TSTAT_CLEAR_THALT >> i);
574 		priv->tqueue |= (TQUEUE_EN0 >> i);
575 		priv->tx_queue[i]->grp = grp;
576 	}
577 
578 	priv->num_grps++;
579 
580 	return 0;
581 }
582 
583 static int gfar_of_group_count(struct device_node *np)
584 {
585 	struct device_node *child;
586 	int num = 0;
587 
588 	for_each_available_child_of_node(np, child)
589 		if (of_node_name_eq(child, "queue-group"))
590 			num++;
591 
592 	return num;
593 }
594 
595 /* Reads the controller's registers to determine what interface
596  * connects it to the PHY.
597  */
598 static phy_interface_t gfar_get_interface(struct net_device *dev)
599 {
600 	struct gfar_private *priv = netdev_priv(dev);
601 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
602 	u32 ecntrl;
603 
604 	ecntrl = gfar_read(&regs->ecntrl);
605 
606 	if (ecntrl & ECNTRL_SGMII_MODE)
607 		return PHY_INTERFACE_MODE_SGMII;
608 
609 	if (ecntrl & ECNTRL_TBI_MODE) {
610 		if (ecntrl & ECNTRL_REDUCED_MODE)
611 			return PHY_INTERFACE_MODE_RTBI;
612 		else
613 			return PHY_INTERFACE_MODE_TBI;
614 	}
615 
616 	if (ecntrl & ECNTRL_REDUCED_MODE) {
617 		if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
618 			return PHY_INTERFACE_MODE_RMII;
619 		}
620 		else {
621 			phy_interface_t interface = priv->interface;
622 
623 			/* This isn't autodetected right now, so it must
624 			 * be set by the device tree or platform code.
625 			 */
626 			if (interface == PHY_INTERFACE_MODE_RGMII_ID)
627 				return PHY_INTERFACE_MODE_RGMII_ID;
628 
629 			return PHY_INTERFACE_MODE_RGMII;
630 		}
631 	}
632 
633 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
634 		return PHY_INTERFACE_MODE_GMII;
635 
636 	return PHY_INTERFACE_MODE_MII;
637 }
638 
639 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
640 {
641 	const char *model;
642 	const void *mac_addr;
643 	int err = 0, i;
644 	phy_interface_t interface;
645 	struct net_device *dev = NULL;
646 	struct gfar_private *priv = NULL;
647 	struct device_node *np = ofdev->dev.of_node;
648 	struct device_node *child = NULL;
649 	u32 stash_len = 0;
650 	u32 stash_idx = 0;
651 	unsigned int num_tx_qs, num_rx_qs;
652 	unsigned short mode, poll_mode;
653 
654 	if (!np)
655 		return -ENODEV;
656 
657 	if (of_device_is_compatible(np, "fsl,etsec2")) {
658 		mode = MQ_MG_MODE;
659 		poll_mode = GFAR_SQ_POLLING;
660 	} else {
661 		mode = SQ_SG_MODE;
662 		poll_mode = GFAR_SQ_POLLING;
663 	}
664 
665 	if (mode == SQ_SG_MODE) {
666 		num_tx_qs = 1;
667 		num_rx_qs = 1;
668 	} else { /* MQ_MG_MODE */
669 		/* get the actual number of supported groups */
670 		unsigned int num_grps = gfar_of_group_count(np);
671 
672 		if (num_grps == 0 || num_grps > MAXGROUPS) {
673 			dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
674 				num_grps);
675 			pr_err("Cannot do alloc_etherdev, aborting\n");
676 			return -EINVAL;
677 		}
678 
679 		if (poll_mode == GFAR_SQ_POLLING) {
680 			num_tx_qs = num_grps; /* one txq per int group */
681 			num_rx_qs = num_grps; /* one rxq per int group */
682 		} else { /* GFAR_MQ_POLLING */
683 			u32 tx_queues, rx_queues;
684 			int ret;
685 
686 			/* parse the num of HW tx and rx queues */
687 			ret = of_property_read_u32(np, "fsl,num_tx_queues",
688 						   &tx_queues);
689 			num_tx_qs = ret ? 1 : tx_queues;
690 
691 			ret = of_property_read_u32(np, "fsl,num_rx_queues",
692 						   &rx_queues);
693 			num_rx_qs = ret ? 1 : rx_queues;
694 		}
695 	}
696 
697 	if (num_tx_qs > MAX_TX_QS) {
698 		pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
699 		       num_tx_qs, MAX_TX_QS);
700 		pr_err("Cannot do alloc_etherdev, aborting\n");
701 		return -EINVAL;
702 	}
703 
704 	if (num_rx_qs > MAX_RX_QS) {
705 		pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
706 		       num_rx_qs, MAX_RX_QS);
707 		pr_err("Cannot do alloc_etherdev, aborting\n");
708 		return -EINVAL;
709 	}
710 
711 	*pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
712 	dev = *pdev;
713 	if (NULL == dev)
714 		return -ENOMEM;
715 
716 	priv = netdev_priv(dev);
717 	priv->ndev = dev;
718 
719 	priv->mode = mode;
720 	priv->poll_mode = poll_mode;
721 
722 	priv->num_tx_queues = num_tx_qs;
723 	netif_set_real_num_rx_queues(dev, num_rx_qs);
724 	priv->num_rx_queues = num_rx_qs;
725 
726 	err = gfar_alloc_tx_queues(priv);
727 	if (err)
728 		goto tx_alloc_failed;
729 
730 	err = gfar_alloc_rx_queues(priv);
731 	if (err)
732 		goto rx_alloc_failed;
733 
734 	err = of_property_read_string(np, "model", &model);
735 	if (err) {
736 		pr_err("Device model property missing, aborting\n");
737 		goto rx_alloc_failed;
738 	}
739 
740 	/* Init Rx queue filer rule set linked list */
741 	INIT_LIST_HEAD(&priv->rx_list.list);
742 	priv->rx_list.count = 0;
743 	mutex_init(&priv->rx_queue_access);
744 
745 	for (i = 0; i < MAXGROUPS; i++)
746 		priv->gfargrp[i].regs = NULL;
747 
748 	/* Parse and initialize group specific information */
749 	if (priv->mode == MQ_MG_MODE) {
750 		for_each_available_child_of_node(np, child) {
751 			if (!of_node_name_eq(child, "queue-group"))
752 				continue;
753 
754 			err = gfar_parse_group(child, priv, model);
755 			if (err)
756 				goto err_grp_init;
757 		}
758 	} else { /* SQ_SG_MODE */
759 		err = gfar_parse_group(np, priv, model);
760 		if (err)
761 			goto err_grp_init;
762 	}
763 
764 	if (of_property_read_bool(np, "bd-stash")) {
765 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
766 		priv->bd_stash_en = 1;
767 	}
768 
769 	err = of_property_read_u32(np, "rx-stash-len", &stash_len);
770 
771 	if (err == 0)
772 		priv->rx_stash_size = stash_len;
773 
774 	err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
775 
776 	if (err == 0)
777 		priv->rx_stash_index = stash_idx;
778 
779 	if (stash_len || stash_idx)
780 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
781 
782 	mac_addr = of_get_mac_address(np);
783 
784 	if (!IS_ERR(mac_addr))
785 		ether_addr_copy(dev->dev_addr, mac_addr);
786 
787 	if (model && !strcasecmp(model, "TSEC"))
788 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
789 				     FSL_GIANFAR_DEV_HAS_COALESCE |
790 				     FSL_GIANFAR_DEV_HAS_RMON |
791 				     FSL_GIANFAR_DEV_HAS_MULTI_INTR;
792 
793 	if (model && !strcasecmp(model, "eTSEC"))
794 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
795 				     FSL_GIANFAR_DEV_HAS_COALESCE |
796 				     FSL_GIANFAR_DEV_HAS_RMON |
797 				     FSL_GIANFAR_DEV_HAS_MULTI_INTR |
798 				     FSL_GIANFAR_DEV_HAS_CSUM |
799 				     FSL_GIANFAR_DEV_HAS_VLAN |
800 				     FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
801 				     FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
802 				     FSL_GIANFAR_DEV_HAS_TIMER |
803 				     FSL_GIANFAR_DEV_HAS_RX_FILER;
804 
805 	/* Use PHY connection type from the DT node if one is specified there.
806 	 * rgmii-id really needs to be specified. Other types can be
807 	 * detected by hardware
808 	 */
809 	err = of_get_phy_mode(np, &interface);
810 	if (!err)
811 		priv->interface = interface;
812 	else
813 		priv->interface = gfar_get_interface(dev);
814 
815 	if (of_find_property(np, "fsl,magic-packet", NULL))
816 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
817 
818 	if (of_get_property(np, "fsl,wake-on-filer", NULL))
819 		priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
820 
821 	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
822 
823 	/* In the case of a fixed PHY, the DT node associated
824 	 * to the PHY is the Ethernet MAC DT node.
825 	 */
826 	if (!priv->phy_node && of_phy_is_fixed_link(np)) {
827 		err = of_phy_register_fixed_link(np);
828 		if (err)
829 			goto err_grp_init;
830 
831 		priv->phy_node = of_node_get(np);
832 	}
833 
834 	/* Find the TBI PHY.  If it's not there, we don't support SGMII */
835 	priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
836 
837 	return 0;
838 
839 err_grp_init:
840 	unmap_group_regs(priv);
841 rx_alloc_failed:
842 	gfar_free_rx_queues(priv);
843 tx_alloc_failed:
844 	gfar_free_tx_queues(priv);
845 	free_gfar_dev(priv);
846 	return err;
847 }
848 
849 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
850 				   u32 class)
851 {
852 	u32 rqfpr = FPR_FILER_MASK;
853 	u32 rqfcr = 0x0;
854 
855 	rqfar--;
856 	rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
857 	priv->ftp_rqfpr[rqfar] = rqfpr;
858 	priv->ftp_rqfcr[rqfar] = rqfcr;
859 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
860 
861 	rqfar--;
862 	rqfcr = RQFCR_CMP_NOMATCH;
863 	priv->ftp_rqfpr[rqfar] = rqfpr;
864 	priv->ftp_rqfcr[rqfar] = rqfcr;
865 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
866 
867 	rqfar--;
868 	rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
869 	rqfpr = class;
870 	priv->ftp_rqfcr[rqfar] = rqfcr;
871 	priv->ftp_rqfpr[rqfar] = rqfpr;
872 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
873 
874 	rqfar--;
875 	rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
876 	rqfpr = class;
877 	priv->ftp_rqfcr[rqfar] = rqfcr;
878 	priv->ftp_rqfpr[rqfar] = rqfpr;
879 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
880 
881 	return rqfar;
882 }
883 
884 static void gfar_init_filer_table(struct gfar_private *priv)
885 {
886 	int i = 0x0;
887 	u32 rqfar = MAX_FILER_IDX;
888 	u32 rqfcr = 0x0;
889 	u32 rqfpr = FPR_FILER_MASK;
890 
891 	/* Default rule */
892 	rqfcr = RQFCR_CMP_MATCH;
893 	priv->ftp_rqfcr[rqfar] = rqfcr;
894 	priv->ftp_rqfpr[rqfar] = rqfpr;
895 	gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
896 
897 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
898 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
899 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
900 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
901 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
902 	rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
903 
904 	/* cur_filer_idx indicated the first non-masked rule */
905 	priv->cur_filer_idx = rqfar;
906 
907 	/* Rest are masked rules */
908 	rqfcr = RQFCR_CMP_NOMATCH;
909 	for (i = 0; i < rqfar; i++) {
910 		priv->ftp_rqfcr[i] = rqfcr;
911 		priv->ftp_rqfpr[i] = rqfpr;
912 		gfar_write_filer(priv, i, rqfcr, rqfpr);
913 	}
914 }
915 
916 #ifdef CONFIG_PPC
917 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
918 {
919 	unsigned int pvr = mfspr(SPRN_PVR);
920 	unsigned int svr = mfspr(SPRN_SVR);
921 	unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
922 	unsigned int rev = svr & 0xffff;
923 
924 	/* MPC8313 Rev 2.0 and higher; All MPC837x */
925 	if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
926 	    (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
927 		priv->errata |= GFAR_ERRATA_74;
928 
929 	/* MPC8313 and MPC837x all rev */
930 	if ((pvr == 0x80850010 && mod == 0x80b0) ||
931 	    (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
932 		priv->errata |= GFAR_ERRATA_76;
933 
934 	/* MPC8313 Rev < 2.0 */
935 	if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
936 		priv->errata |= GFAR_ERRATA_12;
937 }
938 
939 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
940 {
941 	unsigned int svr = mfspr(SPRN_SVR);
942 
943 	if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
944 		priv->errata |= GFAR_ERRATA_12;
945 	/* P2020/P1010 Rev 1; MPC8548 Rev 2 */
946 	if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
947 	    ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
948 	    ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
949 		priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
950 }
951 #endif
952 
953 static void gfar_detect_errata(struct gfar_private *priv)
954 {
955 	struct device *dev = &priv->ofdev->dev;
956 
957 	/* no plans to fix */
958 	priv->errata |= GFAR_ERRATA_A002;
959 
960 #ifdef CONFIG_PPC
961 	if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
962 		__gfar_detect_errata_85xx(priv);
963 	else /* non-mpc85xx parts, i.e. e300 core based */
964 		__gfar_detect_errata_83xx(priv);
965 #endif
966 
967 	if (priv->errata)
968 		dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
969 			 priv->errata);
970 }
971 
972 static void gfar_init_addr_hash_table(struct gfar_private *priv)
973 {
974 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
975 
976 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
977 		priv->extended_hash = 1;
978 		priv->hash_width = 9;
979 
980 		priv->hash_regs[0] = &regs->igaddr0;
981 		priv->hash_regs[1] = &regs->igaddr1;
982 		priv->hash_regs[2] = &regs->igaddr2;
983 		priv->hash_regs[3] = &regs->igaddr3;
984 		priv->hash_regs[4] = &regs->igaddr4;
985 		priv->hash_regs[5] = &regs->igaddr5;
986 		priv->hash_regs[6] = &regs->igaddr6;
987 		priv->hash_regs[7] = &regs->igaddr7;
988 		priv->hash_regs[8] = &regs->gaddr0;
989 		priv->hash_regs[9] = &regs->gaddr1;
990 		priv->hash_regs[10] = &regs->gaddr2;
991 		priv->hash_regs[11] = &regs->gaddr3;
992 		priv->hash_regs[12] = &regs->gaddr4;
993 		priv->hash_regs[13] = &regs->gaddr5;
994 		priv->hash_regs[14] = &regs->gaddr6;
995 		priv->hash_regs[15] = &regs->gaddr7;
996 
997 	} else {
998 		priv->extended_hash = 0;
999 		priv->hash_width = 8;
1000 
1001 		priv->hash_regs[0] = &regs->gaddr0;
1002 		priv->hash_regs[1] = &regs->gaddr1;
1003 		priv->hash_regs[2] = &regs->gaddr2;
1004 		priv->hash_regs[3] = &regs->gaddr3;
1005 		priv->hash_regs[4] = &regs->gaddr4;
1006 		priv->hash_regs[5] = &regs->gaddr5;
1007 		priv->hash_regs[6] = &regs->gaddr6;
1008 		priv->hash_regs[7] = &regs->gaddr7;
1009 	}
1010 }
1011 
1012 static int __gfar_is_rx_idle(struct gfar_private *priv)
1013 {
1014 	u32 res;
1015 
1016 	/* Normaly TSEC should not hang on GRS commands, so we should
1017 	 * actually wait for IEVENT_GRSC flag.
1018 	 */
1019 	if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1020 		return 0;
1021 
1022 	/* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1023 	 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1024 	 * and the Rx can be safely reset.
1025 	 */
1026 	res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1027 	res &= 0x7f807f80;
1028 	if ((res & 0xffff) == (res >> 16))
1029 		return 1;
1030 
1031 	return 0;
1032 }
1033 
1034 /* Halt the receive and transmit queues */
1035 static void gfar_halt_nodisable(struct gfar_private *priv)
1036 {
1037 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1038 	u32 tempval;
1039 	unsigned int timeout;
1040 	int stopped;
1041 
1042 	gfar_ints_disable(priv);
1043 
1044 	if (gfar_is_dma_stopped(priv))
1045 		return;
1046 
1047 	/* Stop the DMA, and wait for it to stop */
1048 	tempval = gfar_read(&regs->dmactrl);
1049 	tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1050 	gfar_write(&regs->dmactrl, tempval);
1051 
1052 retry:
1053 	timeout = 1000;
1054 	while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1055 		cpu_relax();
1056 		timeout--;
1057 	}
1058 
1059 	if (!timeout)
1060 		stopped = gfar_is_dma_stopped(priv);
1061 
1062 	if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1063 	    !__gfar_is_rx_idle(priv))
1064 		goto retry;
1065 }
1066 
1067 /* Halt the receive and transmit queues */
1068 static void gfar_halt(struct gfar_private *priv)
1069 {
1070 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1071 	u32 tempval;
1072 
1073 	/* Dissable the Rx/Tx hw queues */
1074 	gfar_write(&regs->rqueue, 0);
1075 	gfar_write(&regs->tqueue, 0);
1076 
1077 	mdelay(10);
1078 
1079 	gfar_halt_nodisable(priv);
1080 
1081 	/* Disable Rx/Tx DMA */
1082 	tempval = gfar_read(&regs->maccfg1);
1083 	tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1084 	gfar_write(&regs->maccfg1, tempval);
1085 }
1086 
1087 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1088 {
1089 	struct txbd8 *txbdp;
1090 	struct gfar_private *priv = netdev_priv(tx_queue->dev);
1091 	int i, j;
1092 
1093 	txbdp = tx_queue->tx_bd_base;
1094 
1095 	for (i = 0; i < tx_queue->tx_ring_size; i++) {
1096 		if (!tx_queue->tx_skbuff[i])
1097 			continue;
1098 
1099 		dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1100 				 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1101 		txbdp->lstatus = 0;
1102 		for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1103 		     j++) {
1104 			txbdp++;
1105 			dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1106 				       be16_to_cpu(txbdp->length),
1107 				       DMA_TO_DEVICE);
1108 		}
1109 		txbdp++;
1110 		dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1111 		tx_queue->tx_skbuff[i] = NULL;
1112 	}
1113 	kfree(tx_queue->tx_skbuff);
1114 	tx_queue->tx_skbuff = NULL;
1115 }
1116 
1117 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1118 {
1119 	int i;
1120 
1121 	struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1122 
1123 	dev_kfree_skb(rx_queue->skb);
1124 
1125 	for (i = 0; i < rx_queue->rx_ring_size; i++) {
1126 		struct	gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1127 
1128 		rxbdp->lstatus = 0;
1129 		rxbdp->bufPtr = 0;
1130 		rxbdp++;
1131 
1132 		if (!rxb->page)
1133 			continue;
1134 
1135 		dma_unmap_page(rx_queue->dev, rxb->dma,
1136 			       PAGE_SIZE, DMA_FROM_DEVICE);
1137 		__free_page(rxb->page);
1138 
1139 		rxb->page = NULL;
1140 	}
1141 
1142 	kfree(rx_queue->rx_buff);
1143 	rx_queue->rx_buff = NULL;
1144 }
1145 
1146 /* If there are any tx skbs or rx skbs still around, free them.
1147  * Then free tx_skbuff and rx_skbuff
1148  */
1149 static void free_skb_resources(struct gfar_private *priv)
1150 {
1151 	struct gfar_priv_tx_q *tx_queue = NULL;
1152 	struct gfar_priv_rx_q *rx_queue = NULL;
1153 	int i;
1154 
1155 	/* Go through all the buffer descriptors and free their data buffers */
1156 	for (i = 0; i < priv->num_tx_queues; i++) {
1157 		struct netdev_queue *txq;
1158 
1159 		tx_queue = priv->tx_queue[i];
1160 		txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1161 		if (tx_queue->tx_skbuff)
1162 			free_skb_tx_queue(tx_queue);
1163 		netdev_tx_reset_queue(txq);
1164 	}
1165 
1166 	for (i = 0; i < priv->num_rx_queues; i++) {
1167 		rx_queue = priv->rx_queue[i];
1168 		if (rx_queue->rx_buff)
1169 			free_skb_rx_queue(rx_queue);
1170 	}
1171 
1172 	dma_free_coherent(priv->dev,
1173 			  sizeof(struct txbd8) * priv->total_tx_ring_size +
1174 			  sizeof(struct rxbd8) * priv->total_rx_ring_size,
1175 			  priv->tx_queue[0]->tx_bd_base,
1176 			  priv->tx_queue[0]->tx_bd_dma_base);
1177 }
1178 
1179 void stop_gfar(struct net_device *dev)
1180 {
1181 	struct gfar_private *priv = netdev_priv(dev);
1182 
1183 	netif_tx_stop_all_queues(dev);
1184 
1185 	smp_mb__before_atomic();
1186 	set_bit(GFAR_DOWN, &priv->state);
1187 	smp_mb__after_atomic();
1188 
1189 	disable_napi(priv);
1190 
1191 	/* disable ints and gracefully shut down Rx/Tx DMA */
1192 	gfar_halt(priv);
1193 
1194 	phy_stop(dev->phydev);
1195 
1196 	free_skb_resources(priv);
1197 }
1198 
1199 static void gfar_start(struct gfar_private *priv)
1200 {
1201 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1202 	u32 tempval;
1203 	int i = 0;
1204 
1205 	/* Enable Rx/Tx hw queues */
1206 	gfar_write(&regs->rqueue, priv->rqueue);
1207 	gfar_write(&regs->tqueue, priv->tqueue);
1208 
1209 	/* Initialize DMACTRL to have WWR and WOP */
1210 	tempval = gfar_read(&regs->dmactrl);
1211 	tempval |= DMACTRL_INIT_SETTINGS;
1212 	gfar_write(&regs->dmactrl, tempval);
1213 
1214 	/* Make sure we aren't stopped */
1215 	tempval = gfar_read(&regs->dmactrl);
1216 	tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1217 	gfar_write(&regs->dmactrl, tempval);
1218 
1219 	for (i = 0; i < priv->num_grps; i++) {
1220 		regs = priv->gfargrp[i].regs;
1221 		/* Clear THLT/RHLT, so that the DMA starts polling now */
1222 		gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1223 		gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1224 	}
1225 
1226 	/* Enable Rx/Tx DMA */
1227 	tempval = gfar_read(&regs->maccfg1);
1228 	tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1229 	gfar_write(&regs->maccfg1, tempval);
1230 
1231 	gfar_ints_enable(priv);
1232 
1233 	netif_trans_update(priv->ndev); /* prevent tx timeout */
1234 }
1235 
1236 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1237 {
1238 	struct page *page;
1239 	dma_addr_t addr;
1240 
1241 	page = dev_alloc_page();
1242 	if (unlikely(!page))
1243 		return false;
1244 
1245 	addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1246 	if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1247 		__free_page(page);
1248 
1249 		return false;
1250 	}
1251 
1252 	rxb->dma = addr;
1253 	rxb->page = page;
1254 	rxb->page_offset = 0;
1255 
1256 	return true;
1257 }
1258 
1259 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1260 {
1261 	struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1262 	struct gfar_extra_stats *estats = &priv->extra_stats;
1263 
1264 	netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1265 	atomic64_inc(&estats->rx_alloc_err);
1266 }
1267 
1268 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1269 				int alloc_cnt)
1270 {
1271 	struct rxbd8 *bdp;
1272 	struct gfar_rx_buff *rxb;
1273 	int i;
1274 
1275 	i = rx_queue->next_to_use;
1276 	bdp = &rx_queue->rx_bd_base[i];
1277 	rxb = &rx_queue->rx_buff[i];
1278 
1279 	while (alloc_cnt--) {
1280 		/* try reuse page */
1281 		if (unlikely(!rxb->page)) {
1282 			if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1283 				gfar_rx_alloc_err(rx_queue);
1284 				break;
1285 			}
1286 		}
1287 
1288 		/* Setup the new RxBD */
1289 		gfar_init_rxbdp(rx_queue, bdp,
1290 				rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1291 
1292 		/* Update to the next pointer */
1293 		bdp++;
1294 		rxb++;
1295 
1296 		if (unlikely(++i == rx_queue->rx_ring_size)) {
1297 			i = 0;
1298 			bdp = rx_queue->rx_bd_base;
1299 			rxb = rx_queue->rx_buff;
1300 		}
1301 	}
1302 
1303 	rx_queue->next_to_use = i;
1304 	rx_queue->next_to_alloc = i;
1305 }
1306 
1307 static void gfar_init_bds(struct net_device *ndev)
1308 {
1309 	struct gfar_private *priv = netdev_priv(ndev);
1310 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1311 	struct gfar_priv_tx_q *tx_queue = NULL;
1312 	struct gfar_priv_rx_q *rx_queue = NULL;
1313 	struct txbd8 *txbdp;
1314 	u32 __iomem *rfbptr;
1315 	int i, j;
1316 
1317 	for (i = 0; i < priv->num_tx_queues; i++) {
1318 		tx_queue = priv->tx_queue[i];
1319 		/* Initialize some variables in our dev structure */
1320 		tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1321 		tx_queue->dirty_tx = tx_queue->tx_bd_base;
1322 		tx_queue->cur_tx = tx_queue->tx_bd_base;
1323 		tx_queue->skb_curtx = 0;
1324 		tx_queue->skb_dirtytx = 0;
1325 
1326 		/* Initialize Transmit Descriptor Ring */
1327 		txbdp = tx_queue->tx_bd_base;
1328 		for (j = 0; j < tx_queue->tx_ring_size; j++) {
1329 			txbdp->lstatus = 0;
1330 			txbdp->bufPtr = 0;
1331 			txbdp++;
1332 		}
1333 
1334 		/* Set the last descriptor in the ring to indicate wrap */
1335 		txbdp--;
1336 		txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1337 					    TXBD_WRAP);
1338 	}
1339 
1340 	rfbptr = &regs->rfbptr0;
1341 	for (i = 0; i < priv->num_rx_queues; i++) {
1342 		rx_queue = priv->rx_queue[i];
1343 
1344 		rx_queue->next_to_clean = 0;
1345 		rx_queue->next_to_use = 0;
1346 		rx_queue->next_to_alloc = 0;
1347 
1348 		/* make sure next_to_clean != next_to_use after this
1349 		 * by leaving at least 1 unused descriptor
1350 		 */
1351 		gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1352 
1353 		rx_queue->rfbptr = rfbptr;
1354 		rfbptr += 2;
1355 	}
1356 }
1357 
1358 static int gfar_alloc_skb_resources(struct net_device *ndev)
1359 {
1360 	void *vaddr;
1361 	dma_addr_t addr;
1362 	int i, j;
1363 	struct gfar_private *priv = netdev_priv(ndev);
1364 	struct device *dev = priv->dev;
1365 	struct gfar_priv_tx_q *tx_queue = NULL;
1366 	struct gfar_priv_rx_q *rx_queue = NULL;
1367 
1368 	priv->total_tx_ring_size = 0;
1369 	for (i = 0; i < priv->num_tx_queues; i++)
1370 		priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1371 
1372 	priv->total_rx_ring_size = 0;
1373 	for (i = 0; i < priv->num_rx_queues; i++)
1374 		priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1375 
1376 	/* Allocate memory for the buffer descriptors */
1377 	vaddr = dma_alloc_coherent(dev,
1378 				   (priv->total_tx_ring_size *
1379 				    sizeof(struct txbd8)) +
1380 				   (priv->total_rx_ring_size *
1381 				    sizeof(struct rxbd8)),
1382 				   &addr, GFP_KERNEL);
1383 	if (!vaddr)
1384 		return -ENOMEM;
1385 
1386 	for (i = 0; i < priv->num_tx_queues; i++) {
1387 		tx_queue = priv->tx_queue[i];
1388 		tx_queue->tx_bd_base = vaddr;
1389 		tx_queue->tx_bd_dma_base = addr;
1390 		tx_queue->dev = ndev;
1391 		/* enet DMA only understands physical addresses */
1392 		addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1393 		vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1394 	}
1395 
1396 	/* Start the rx descriptor ring where the tx ring leaves off */
1397 	for (i = 0; i < priv->num_rx_queues; i++) {
1398 		rx_queue = priv->rx_queue[i];
1399 		rx_queue->rx_bd_base = vaddr;
1400 		rx_queue->rx_bd_dma_base = addr;
1401 		rx_queue->ndev = ndev;
1402 		rx_queue->dev = dev;
1403 		addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1404 		vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1405 	}
1406 
1407 	/* Setup the skbuff rings */
1408 	for (i = 0; i < priv->num_tx_queues; i++) {
1409 		tx_queue = priv->tx_queue[i];
1410 		tx_queue->tx_skbuff =
1411 			kmalloc_array(tx_queue->tx_ring_size,
1412 				      sizeof(*tx_queue->tx_skbuff),
1413 				      GFP_KERNEL);
1414 		if (!tx_queue->tx_skbuff)
1415 			goto cleanup;
1416 
1417 		for (j = 0; j < tx_queue->tx_ring_size; j++)
1418 			tx_queue->tx_skbuff[j] = NULL;
1419 	}
1420 
1421 	for (i = 0; i < priv->num_rx_queues; i++) {
1422 		rx_queue = priv->rx_queue[i];
1423 		rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1424 					    sizeof(*rx_queue->rx_buff),
1425 					    GFP_KERNEL);
1426 		if (!rx_queue->rx_buff)
1427 			goto cleanup;
1428 	}
1429 
1430 	gfar_init_bds(ndev);
1431 
1432 	return 0;
1433 
1434 cleanup:
1435 	free_skb_resources(priv);
1436 	return -ENOMEM;
1437 }
1438 
1439 /* Bring the controller up and running */
1440 int startup_gfar(struct net_device *ndev)
1441 {
1442 	struct gfar_private *priv = netdev_priv(ndev);
1443 	int err;
1444 
1445 	gfar_mac_reset(priv);
1446 
1447 	err = gfar_alloc_skb_resources(ndev);
1448 	if (err)
1449 		return err;
1450 
1451 	gfar_init_tx_rx_base(priv);
1452 
1453 	smp_mb__before_atomic();
1454 	clear_bit(GFAR_DOWN, &priv->state);
1455 	smp_mb__after_atomic();
1456 
1457 	/* Start Rx/Tx DMA and enable the interrupts */
1458 	gfar_start(priv);
1459 
1460 	/* force link state update after mac reset */
1461 	priv->oldlink = 0;
1462 	priv->oldspeed = 0;
1463 	priv->oldduplex = -1;
1464 
1465 	phy_start(ndev->phydev);
1466 
1467 	enable_napi(priv);
1468 
1469 	netif_tx_wake_all_queues(ndev);
1470 
1471 	return 0;
1472 }
1473 
1474 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1475 {
1476 	struct net_device *ndev = priv->ndev;
1477 	struct phy_device *phydev = ndev->phydev;
1478 	u32 val = 0;
1479 
1480 	if (!phydev->duplex)
1481 		return val;
1482 
1483 	if (!priv->pause_aneg_en) {
1484 		if (priv->tx_pause_en)
1485 			val |= MACCFG1_TX_FLOW;
1486 		if (priv->rx_pause_en)
1487 			val |= MACCFG1_RX_FLOW;
1488 	} else {
1489 		u16 lcl_adv, rmt_adv;
1490 		u8 flowctrl;
1491 		/* get link partner capabilities */
1492 		rmt_adv = 0;
1493 		if (phydev->pause)
1494 			rmt_adv = LPA_PAUSE_CAP;
1495 		if (phydev->asym_pause)
1496 			rmt_adv |= LPA_PAUSE_ASYM;
1497 
1498 		lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1499 		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1500 		if (flowctrl & FLOW_CTRL_TX)
1501 			val |= MACCFG1_TX_FLOW;
1502 		if (flowctrl & FLOW_CTRL_RX)
1503 			val |= MACCFG1_RX_FLOW;
1504 	}
1505 
1506 	return val;
1507 }
1508 
1509 static noinline void gfar_update_link_state(struct gfar_private *priv)
1510 {
1511 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
1512 	struct net_device *ndev = priv->ndev;
1513 	struct phy_device *phydev = ndev->phydev;
1514 	struct gfar_priv_rx_q *rx_queue = NULL;
1515 	int i;
1516 
1517 	if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1518 		return;
1519 
1520 	if (phydev->link) {
1521 		u32 tempval1 = gfar_read(&regs->maccfg1);
1522 		u32 tempval = gfar_read(&regs->maccfg2);
1523 		u32 ecntrl = gfar_read(&regs->ecntrl);
1524 		u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1525 
1526 		if (phydev->duplex != priv->oldduplex) {
1527 			if (!(phydev->duplex))
1528 				tempval &= ~(MACCFG2_FULL_DUPLEX);
1529 			else
1530 				tempval |= MACCFG2_FULL_DUPLEX;
1531 
1532 			priv->oldduplex = phydev->duplex;
1533 		}
1534 
1535 		if (phydev->speed != priv->oldspeed) {
1536 			switch (phydev->speed) {
1537 			case 1000:
1538 				tempval =
1539 				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1540 
1541 				ecntrl &= ~(ECNTRL_R100);
1542 				break;
1543 			case 100:
1544 			case 10:
1545 				tempval =
1546 				    ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1547 
1548 				/* Reduced mode distinguishes
1549 				 * between 10 and 100
1550 				 */
1551 				if (phydev->speed == SPEED_100)
1552 					ecntrl |= ECNTRL_R100;
1553 				else
1554 					ecntrl &= ~(ECNTRL_R100);
1555 				break;
1556 			default:
1557 				netif_warn(priv, link, priv->ndev,
1558 					   "Ack!  Speed (%d) is not 10/100/1000!\n",
1559 					   phydev->speed);
1560 				break;
1561 			}
1562 
1563 			priv->oldspeed = phydev->speed;
1564 		}
1565 
1566 		tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1567 		tempval1 |= gfar_get_flowctrl_cfg(priv);
1568 
1569 		/* Turn last free buffer recording on */
1570 		if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1571 			for (i = 0; i < priv->num_rx_queues; i++) {
1572 				u32 bdp_dma;
1573 
1574 				rx_queue = priv->rx_queue[i];
1575 				bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1576 				gfar_write(rx_queue->rfbptr, bdp_dma);
1577 			}
1578 
1579 			priv->tx_actual_en = 1;
1580 		}
1581 
1582 		if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1583 			priv->tx_actual_en = 0;
1584 
1585 		gfar_write(&regs->maccfg1, tempval1);
1586 		gfar_write(&regs->maccfg2, tempval);
1587 		gfar_write(&regs->ecntrl, ecntrl);
1588 
1589 		if (!priv->oldlink)
1590 			priv->oldlink = 1;
1591 
1592 	} else if (priv->oldlink) {
1593 		priv->oldlink = 0;
1594 		priv->oldspeed = 0;
1595 		priv->oldduplex = -1;
1596 	}
1597 
1598 	if (netif_msg_link(priv))
1599 		phy_print_status(phydev);
1600 }
1601 
1602 /* Called every time the controller might need to be made
1603  * aware of new link state.  The PHY code conveys this
1604  * information through variables in the phydev structure, and this
1605  * function converts those variables into the appropriate
1606  * register values, and can bring down the device if needed.
1607  */
1608 static void adjust_link(struct net_device *dev)
1609 {
1610 	struct gfar_private *priv = netdev_priv(dev);
1611 	struct phy_device *phydev = dev->phydev;
1612 
1613 	if (unlikely(phydev->link != priv->oldlink ||
1614 		     (phydev->link && (phydev->duplex != priv->oldduplex ||
1615 				       phydev->speed != priv->oldspeed))))
1616 		gfar_update_link_state(priv);
1617 }
1618 
1619 /* Initialize TBI PHY interface for communicating with the
1620  * SERDES lynx PHY on the chip.  We communicate with this PHY
1621  * through the MDIO bus on each controller, treating it as a
1622  * "normal" PHY at the address found in the TBIPA register.  We assume
1623  * that the TBIPA register is valid.  Either the MDIO bus code will set
1624  * it to a value that doesn't conflict with other PHYs on the bus, or the
1625  * value doesn't matter, as there are no other PHYs on the bus.
1626  */
1627 static void gfar_configure_serdes(struct net_device *dev)
1628 {
1629 	struct gfar_private *priv = netdev_priv(dev);
1630 	struct phy_device *tbiphy;
1631 
1632 	if (!priv->tbi_node) {
1633 		dev_warn(&dev->dev, "error: SGMII mode requires that the "
1634 				    "device tree specify a tbi-handle\n");
1635 		return;
1636 	}
1637 
1638 	tbiphy = of_phy_find_device(priv->tbi_node);
1639 	if (!tbiphy) {
1640 		dev_err(&dev->dev, "error: Could not get TBI device\n");
1641 		return;
1642 	}
1643 
1644 	/* If the link is already up, we must already be ok, and don't need to
1645 	 * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1646 	 * everything for us?  Resetting it takes the link down and requires
1647 	 * several seconds for it to come back.
1648 	 */
1649 	if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1650 		put_device(&tbiphy->mdio.dev);
1651 		return;
1652 	}
1653 
1654 	/* Single clk mode, mii mode off(for serdes communication) */
1655 	phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1656 
1657 	phy_write(tbiphy, MII_ADVERTISE,
1658 		  ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1659 		  ADVERTISE_1000XPSE_ASYM);
1660 
1661 	phy_write(tbiphy, MII_BMCR,
1662 		  BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1663 		  BMCR_SPEED1000);
1664 
1665 	put_device(&tbiphy->mdio.dev);
1666 }
1667 
1668 /* Initializes driver's PHY state, and attaches to the PHY.
1669  * Returns 0 on success.
1670  */
1671 static int init_phy(struct net_device *dev)
1672 {
1673 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1674 	struct gfar_private *priv = netdev_priv(dev);
1675 	phy_interface_t interface = priv->interface;
1676 	struct phy_device *phydev;
1677 	struct ethtool_eee edata;
1678 
1679 	linkmode_set_bit_array(phy_10_100_features_array,
1680 			       ARRAY_SIZE(phy_10_100_features_array),
1681 			       mask);
1682 	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1683 	linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1684 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1685 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1686 
1687 	priv->oldlink = 0;
1688 	priv->oldspeed = 0;
1689 	priv->oldduplex = -1;
1690 
1691 	phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1692 				interface);
1693 	if (!phydev) {
1694 		dev_err(&dev->dev, "could not attach to PHY\n");
1695 		return -ENODEV;
1696 	}
1697 
1698 	if (interface == PHY_INTERFACE_MODE_SGMII)
1699 		gfar_configure_serdes(dev);
1700 
1701 	/* Remove any features not supported by the controller */
1702 	linkmode_and(phydev->supported, phydev->supported, mask);
1703 	linkmode_copy(phydev->advertising, phydev->supported);
1704 
1705 	/* Add support for flow control */
1706 	phy_support_asym_pause(phydev);
1707 
1708 	/* disable EEE autoneg, EEE not supported by eTSEC */
1709 	memset(&edata, 0, sizeof(struct ethtool_eee));
1710 	phy_ethtool_set_eee(phydev, &edata);
1711 
1712 	return 0;
1713 }
1714 
1715 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1716 {
1717 	struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1718 
1719 	memset(fcb, 0, GMAC_FCB_LEN);
1720 
1721 	return fcb;
1722 }
1723 
1724 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1725 				    int fcb_length)
1726 {
1727 	/* If we're here, it's a IP packet with a TCP or UDP
1728 	 * payload.  We set it to checksum, using a pseudo-header
1729 	 * we provide
1730 	 */
1731 	u8 flags = TXFCB_DEFAULT;
1732 
1733 	/* Tell the controller what the protocol is
1734 	 * And provide the already calculated phcs
1735 	 */
1736 	if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1737 		flags |= TXFCB_UDP;
1738 		fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1739 	} else
1740 		fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1741 
1742 	/* l3os is the distance between the start of the
1743 	 * frame (skb->data) and the start of the IP hdr.
1744 	 * l4os is the distance between the start of the
1745 	 * l3 hdr and the l4 hdr
1746 	 */
1747 	fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1748 	fcb->l4os = skb_network_header_len(skb);
1749 
1750 	fcb->flags = flags;
1751 }
1752 
1753 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1754 {
1755 	fcb->flags |= TXFCB_VLN;
1756 	fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1757 }
1758 
1759 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1760 				      struct txbd8 *base, int ring_size)
1761 {
1762 	struct txbd8 *new_bd = bdp + stride;
1763 
1764 	return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1765 }
1766 
1767 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1768 				      int ring_size)
1769 {
1770 	return skip_txbd(bdp, 1, base, ring_size);
1771 }
1772 
1773 /* eTSEC12: csum generation not supported for some fcb offsets */
1774 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1775 				       unsigned long fcb_addr)
1776 {
1777 	return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1778 	       (fcb_addr % 0x20) > 0x18);
1779 }
1780 
1781 /* eTSEC76: csum generation for frames larger than 2500 may
1782  * cause excess delays before start of transmission
1783  */
1784 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1785 				       unsigned int len)
1786 {
1787 	return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1788 	       (len > 2500));
1789 }
1790 
1791 /* This is called by the kernel when a frame is ready for transmission.
1792  * It is pointed to by the dev->hard_start_xmit function pointer
1793  */
1794 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1795 {
1796 	struct gfar_private *priv = netdev_priv(dev);
1797 	struct gfar_priv_tx_q *tx_queue = NULL;
1798 	struct netdev_queue *txq;
1799 	struct gfar __iomem *regs = NULL;
1800 	struct txfcb *fcb = NULL;
1801 	struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1802 	u32 lstatus;
1803 	skb_frag_t *frag;
1804 	int i, rq = 0;
1805 	int do_tstamp, do_csum, do_vlan;
1806 	u32 bufaddr;
1807 	unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1808 
1809 	rq = skb->queue_mapping;
1810 	tx_queue = priv->tx_queue[rq];
1811 	txq = netdev_get_tx_queue(dev, rq);
1812 	base = tx_queue->tx_bd_base;
1813 	regs = tx_queue->grp->regs;
1814 
1815 	do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1816 	do_vlan = skb_vlan_tag_present(skb);
1817 	do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1818 		    priv->hwts_tx_en;
1819 
1820 	if (do_csum || do_vlan)
1821 		fcb_len = GMAC_FCB_LEN;
1822 
1823 	/* check if time stamp should be generated */
1824 	if (unlikely(do_tstamp))
1825 		fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1826 
1827 	/* make space for additional header when fcb is needed */
1828 	if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
1829 		struct sk_buff *skb_new;
1830 
1831 		skb_new = skb_realloc_headroom(skb, fcb_len);
1832 		if (!skb_new) {
1833 			dev->stats.tx_errors++;
1834 			dev_kfree_skb_any(skb);
1835 			return NETDEV_TX_OK;
1836 		}
1837 
1838 		if (skb->sk)
1839 			skb_set_owner_w(skb_new, skb->sk);
1840 		dev_consume_skb_any(skb);
1841 		skb = skb_new;
1842 	}
1843 
1844 	/* total number of fragments in the SKB */
1845 	nr_frags = skb_shinfo(skb)->nr_frags;
1846 
1847 	/* calculate the required number of TxBDs for this skb */
1848 	if (unlikely(do_tstamp))
1849 		nr_txbds = nr_frags + 2;
1850 	else
1851 		nr_txbds = nr_frags + 1;
1852 
1853 	/* check if there is space to queue this packet */
1854 	if (nr_txbds > tx_queue->num_txbdfree) {
1855 		/* no space, stop the queue */
1856 		netif_tx_stop_queue(txq);
1857 		dev->stats.tx_fifo_errors++;
1858 		return NETDEV_TX_BUSY;
1859 	}
1860 
1861 	/* Update transmit stats */
1862 	bytes_sent = skb->len;
1863 	tx_queue->stats.tx_bytes += bytes_sent;
1864 	/* keep Tx bytes on wire for BQL accounting */
1865 	GFAR_CB(skb)->bytes_sent = bytes_sent;
1866 	tx_queue->stats.tx_packets++;
1867 
1868 	txbdp = txbdp_start = tx_queue->cur_tx;
1869 	lstatus = be32_to_cpu(txbdp->lstatus);
1870 
1871 	/* Add TxPAL between FCB and frame if required */
1872 	if (unlikely(do_tstamp)) {
1873 		skb_push(skb, GMAC_TXPAL_LEN);
1874 		memset(skb->data, 0, GMAC_TXPAL_LEN);
1875 	}
1876 
1877 	/* Add TxFCB if required */
1878 	if (fcb_len) {
1879 		fcb = gfar_add_fcb(skb);
1880 		lstatus |= BD_LFLAG(TXBD_TOE);
1881 	}
1882 
1883 	/* Set up checksumming */
1884 	if (do_csum) {
1885 		gfar_tx_checksum(skb, fcb, fcb_len);
1886 
1887 		if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1888 		    unlikely(gfar_csum_errata_76(priv, skb->len))) {
1889 			__skb_pull(skb, GMAC_FCB_LEN);
1890 			skb_checksum_help(skb);
1891 			if (do_vlan || do_tstamp) {
1892 				/* put back a new fcb for vlan/tstamp TOE */
1893 				fcb = gfar_add_fcb(skb);
1894 			} else {
1895 				/* Tx TOE not used */
1896 				lstatus &= ~(BD_LFLAG(TXBD_TOE));
1897 				fcb = NULL;
1898 			}
1899 		}
1900 	}
1901 
1902 	if (do_vlan)
1903 		gfar_tx_vlan(skb, fcb);
1904 
1905 	bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1906 				 DMA_TO_DEVICE);
1907 	if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1908 		goto dma_map_err;
1909 
1910 	txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1911 
1912 	/* Time stamp insertion requires one additional TxBD */
1913 	if (unlikely(do_tstamp))
1914 		txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1915 						 tx_queue->tx_ring_size);
1916 
1917 	if (likely(!nr_frags)) {
1918 		if (likely(!do_tstamp))
1919 			lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1920 	} else {
1921 		u32 lstatus_start = lstatus;
1922 
1923 		/* Place the fragment addresses and lengths into the TxBDs */
1924 		frag = &skb_shinfo(skb)->frags[0];
1925 		for (i = 0; i < nr_frags; i++, frag++) {
1926 			unsigned int size;
1927 
1928 			/* Point at the next BD, wrapping as needed */
1929 			txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1930 
1931 			size = skb_frag_size(frag);
1932 
1933 			lstatus = be32_to_cpu(txbdp->lstatus) | size |
1934 				  BD_LFLAG(TXBD_READY);
1935 
1936 			/* Handle the last BD specially */
1937 			if (i == nr_frags - 1)
1938 				lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1939 
1940 			bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1941 						   size, DMA_TO_DEVICE);
1942 			if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1943 				goto dma_map_err;
1944 
1945 			/* set the TxBD length and buffer pointer */
1946 			txbdp->bufPtr = cpu_to_be32(bufaddr);
1947 			txbdp->lstatus = cpu_to_be32(lstatus);
1948 		}
1949 
1950 		lstatus = lstatus_start;
1951 	}
1952 
1953 	/* If time stamping is requested one additional TxBD must be set up. The
1954 	 * first TxBD points to the FCB and must have a data length of
1955 	 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1956 	 * the full frame length.
1957 	 */
1958 	if (unlikely(do_tstamp)) {
1959 		u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1960 
1961 		bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1962 		bufaddr += fcb_len;
1963 
1964 		lstatus_ts |= BD_LFLAG(TXBD_READY) |
1965 			      (skb_headlen(skb) - fcb_len);
1966 		if (!nr_frags)
1967 			lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1968 
1969 		txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1970 		txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1971 		lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1972 
1973 		/* Setup tx hardware time stamping */
1974 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1975 		fcb->ptp = 1;
1976 	} else {
1977 		lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1978 	}
1979 
1980 	netdev_tx_sent_queue(txq, bytes_sent);
1981 
1982 	gfar_wmb();
1983 
1984 	txbdp_start->lstatus = cpu_to_be32(lstatus);
1985 
1986 	gfar_wmb(); /* force lstatus write before tx_skbuff */
1987 
1988 	tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1989 
1990 	/* Update the current skb pointer to the next entry we will use
1991 	 * (wrapping if necessary)
1992 	 */
1993 	tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1994 			      TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1995 
1996 	tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1997 
1998 	/* We can work in parallel with gfar_clean_tx_ring(), except
1999 	 * when modifying num_txbdfree. Note that we didn't grab the lock
2000 	 * when we were reading the num_txbdfree and checking for available
2001 	 * space, that's because outside of this function it can only grow.
2002 	 */
2003 	spin_lock_bh(&tx_queue->txlock);
2004 	/* reduce TxBD free count */
2005 	tx_queue->num_txbdfree -= (nr_txbds);
2006 	spin_unlock_bh(&tx_queue->txlock);
2007 
2008 	/* If the next BD still needs to be cleaned up, then the bds
2009 	 * are full.  We need to tell the kernel to stop sending us stuff.
2010 	 */
2011 	if (!tx_queue->num_txbdfree) {
2012 		netif_tx_stop_queue(txq);
2013 
2014 		dev->stats.tx_fifo_errors++;
2015 	}
2016 
2017 	/* Tell the DMA to go go go */
2018 	gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2019 
2020 	return NETDEV_TX_OK;
2021 
2022 dma_map_err:
2023 	txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2024 	if (do_tstamp)
2025 		txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2026 	for (i = 0; i < nr_frags; i++) {
2027 		lstatus = be32_to_cpu(txbdp->lstatus);
2028 		if (!(lstatus & BD_LFLAG(TXBD_READY)))
2029 			break;
2030 
2031 		lstatus &= ~BD_LFLAG(TXBD_READY);
2032 		txbdp->lstatus = cpu_to_be32(lstatus);
2033 		bufaddr = be32_to_cpu(txbdp->bufPtr);
2034 		dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2035 			       DMA_TO_DEVICE);
2036 		txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2037 	}
2038 	gfar_wmb();
2039 	dev_kfree_skb_any(skb);
2040 	return NETDEV_TX_OK;
2041 }
2042 
2043 /* Changes the mac address if the controller is not running. */
2044 static int gfar_set_mac_address(struct net_device *dev)
2045 {
2046 	gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2047 
2048 	return 0;
2049 }
2050 
2051 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2052 {
2053 	struct gfar_private *priv = netdev_priv(dev);
2054 
2055 	while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2056 		cpu_relax();
2057 
2058 	if (dev->flags & IFF_UP)
2059 		stop_gfar(dev);
2060 
2061 	dev->mtu = new_mtu;
2062 
2063 	if (dev->flags & IFF_UP)
2064 		startup_gfar(dev);
2065 
2066 	clear_bit_unlock(GFAR_RESETTING, &priv->state);
2067 
2068 	return 0;
2069 }
2070 
2071 static void reset_gfar(struct net_device *ndev)
2072 {
2073 	struct gfar_private *priv = netdev_priv(ndev);
2074 
2075 	while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2076 		cpu_relax();
2077 
2078 	stop_gfar(ndev);
2079 	startup_gfar(ndev);
2080 
2081 	clear_bit_unlock(GFAR_RESETTING, &priv->state);
2082 }
2083 
2084 /* gfar_reset_task gets scheduled when a packet has not been
2085  * transmitted after a set amount of time.
2086  * For now, assume that clearing out all the structures, and
2087  * starting over will fix the problem.
2088  */
2089 static void gfar_reset_task(struct work_struct *work)
2090 {
2091 	struct gfar_private *priv = container_of(work, struct gfar_private,
2092 						 reset_task);
2093 	reset_gfar(priv->ndev);
2094 }
2095 
2096 static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2097 {
2098 	struct gfar_private *priv = netdev_priv(dev);
2099 
2100 	dev->stats.tx_errors++;
2101 	schedule_work(&priv->reset_task);
2102 }
2103 
2104 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2105 {
2106 	struct hwtstamp_config config;
2107 	struct gfar_private *priv = netdev_priv(netdev);
2108 
2109 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2110 		return -EFAULT;
2111 
2112 	/* reserved for future extensions */
2113 	if (config.flags)
2114 		return -EINVAL;
2115 
2116 	switch (config.tx_type) {
2117 	case HWTSTAMP_TX_OFF:
2118 		priv->hwts_tx_en = 0;
2119 		break;
2120 	case HWTSTAMP_TX_ON:
2121 		if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2122 			return -ERANGE;
2123 		priv->hwts_tx_en = 1;
2124 		break;
2125 	default:
2126 		return -ERANGE;
2127 	}
2128 
2129 	switch (config.rx_filter) {
2130 	case HWTSTAMP_FILTER_NONE:
2131 		if (priv->hwts_rx_en) {
2132 			priv->hwts_rx_en = 0;
2133 			reset_gfar(netdev);
2134 		}
2135 		break;
2136 	default:
2137 		if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2138 			return -ERANGE;
2139 		if (!priv->hwts_rx_en) {
2140 			priv->hwts_rx_en = 1;
2141 			reset_gfar(netdev);
2142 		}
2143 		config.rx_filter = HWTSTAMP_FILTER_ALL;
2144 		break;
2145 	}
2146 
2147 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2148 		-EFAULT : 0;
2149 }
2150 
2151 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2152 {
2153 	struct hwtstamp_config config;
2154 	struct gfar_private *priv = netdev_priv(netdev);
2155 
2156 	config.flags = 0;
2157 	config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2158 	config.rx_filter = (priv->hwts_rx_en ?
2159 			    HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2160 
2161 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2162 		-EFAULT : 0;
2163 }
2164 
2165 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2166 {
2167 	struct phy_device *phydev = dev->phydev;
2168 
2169 	if (!netif_running(dev))
2170 		return -EINVAL;
2171 
2172 	if (cmd == SIOCSHWTSTAMP)
2173 		return gfar_hwtstamp_set(dev, rq);
2174 	if (cmd == SIOCGHWTSTAMP)
2175 		return gfar_hwtstamp_get(dev, rq);
2176 
2177 	if (!phydev)
2178 		return -ENODEV;
2179 
2180 	return phy_mii_ioctl(phydev, rq, cmd);
2181 }
2182 
2183 /* Interrupt Handler for Transmit complete */
2184 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2185 {
2186 	struct net_device *dev = tx_queue->dev;
2187 	struct netdev_queue *txq;
2188 	struct gfar_private *priv = netdev_priv(dev);
2189 	struct txbd8 *bdp, *next = NULL;
2190 	struct txbd8 *lbdp = NULL;
2191 	struct txbd8 *base = tx_queue->tx_bd_base;
2192 	struct sk_buff *skb;
2193 	int skb_dirtytx;
2194 	int tx_ring_size = tx_queue->tx_ring_size;
2195 	int frags = 0, nr_txbds = 0;
2196 	int i;
2197 	int howmany = 0;
2198 	int tqi = tx_queue->qindex;
2199 	unsigned int bytes_sent = 0;
2200 	u32 lstatus;
2201 	size_t buflen;
2202 
2203 	txq = netdev_get_tx_queue(dev, tqi);
2204 	bdp = tx_queue->dirty_tx;
2205 	skb_dirtytx = tx_queue->skb_dirtytx;
2206 
2207 	while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2208 		bool do_tstamp;
2209 
2210 		do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2211 			    priv->hwts_tx_en;
2212 
2213 		frags = skb_shinfo(skb)->nr_frags;
2214 
2215 		/* When time stamping, one additional TxBD must be freed.
2216 		 * Also, we need to dma_unmap_single() the TxPAL.
2217 		 */
2218 		if (unlikely(do_tstamp))
2219 			nr_txbds = frags + 2;
2220 		else
2221 			nr_txbds = frags + 1;
2222 
2223 		lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2224 
2225 		lstatus = be32_to_cpu(lbdp->lstatus);
2226 
2227 		/* Only clean completed frames */
2228 		if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2229 		    (lstatus & BD_LENGTH_MASK))
2230 			break;
2231 
2232 		if (unlikely(do_tstamp)) {
2233 			next = next_txbd(bdp, base, tx_ring_size);
2234 			buflen = be16_to_cpu(next->length) +
2235 				 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2236 		} else
2237 			buflen = be16_to_cpu(bdp->length);
2238 
2239 		dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2240 				 buflen, DMA_TO_DEVICE);
2241 
2242 		if (unlikely(do_tstamp)) {
2243 			struct skb_shared_hwtstamps shhwtstamps;
2244 			u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2245 					  ~0x7UL);
2246 
2247 			memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2248 			shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2249 			skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2250 			skb_tstamp_tx(skb, &shhwtstamps);
2251 			gfar_clear_txbd_status(bdp);
2252 			bdp = next;
2253 		}
2254 
2255 		gfar_clear_txbd_status(bdp);
2256 		bdp = next_txbd(bdp, base, tx_ring_size);
2257 
2258 		for (i = 0; i < frags; i++) {
2259 			dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2260 				       be16_to_cpu(bdp->length),
2261 				       DMA_TO_DEVICE);
2262 			gfar_clear_txbd_status(bdp);
2263 			bdp = next_txbd(bdp, base, tx_ring_size);
2264 		}
2265 
2266 		bytes_sent += GFAR_CB(skb)->bytes_sent;
2267 
2268 		dev_kfree_skb_any(skb);
2269 
2270 		tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2271 
2272 		skb_dirtytx = (skb_dirtytx + 1) &
2273 			      TX_RING_MOD_MASK(tx_ring_size);
2274 
2275 		howmany++;
2276 		spin_lock(&tx_queue->txlock);
2277 		tx_queue->num_txbdfree += nr_txbds;
2278 		spin_unlock(&tx_queue->txlock);
2279 	}
2280 
2281 	/* If we freed a buffer, we can restart transmission, if necessary */
2282 	if (tx_queue->num_txbdfree &&
2283 	    netif_tx_queue_stopped(txq) &&
2284 	    !(test_bit(GFAR_DOWN, &priv->state)))
2285 		netif_wake_subqueue(priv->ndev, tqi);
2286 
2287 	/* Update dirty indicators */
2288 	tx_queue->skb_dirtytx = skb_dirtytx;
2289 	tx_queue->dirty_tx = bdp;
2290 
2291 	netdev_tx_completed_queue(txq, howmany, bytes_sent);
2292 }
2293 
2294 static void count_errors(u32 lstatus, struct net_device *ndev)
2295 {
2296 	struct gfar_private *priv = netdev_priv(ndev);
2297 	struct net_device_stats *stats = &ndev->stats;
2298 	struct gfar_extra_stats *estats = &priv->extra_stats;
2299 
2300 	/* If the packet was truncated, none of the other errors matter */
2301 	if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2302 		stats->rx_length_errors++;
2303 
2304 		atomic64_inc(&estats->rx_trunc);
2305 
2306 		return;
2307 	}
2308 	/* Count the errors, if there were any */
2309 	if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2310 		stats->rx_length_errors++;
2311 
2312 		if (lstatus & BD_LFLAG(RXBD_LARGE))
2313 			atomic64_inc(&estats->rx_large);
2314 		else
2315 			atomic64_inc(&estats->rx_short);
2316 	}
2317 	if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2318 		stats->rx_frame_errors++;
2319 		atomic64_inc(&estats->rx_nonoctet);
2320 	}
2321 	if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2322 		atomic64_inc(&estats->rx_crcerr);
2323 		stats->rx_crc_errors++;
2324 	}
2325 	if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2326 		atomic64_inc(&estats->rx_overrun);
2327 		stats->rx_over_errors++;
2328 	}
2329 }
2330 
2331 static irqreturn_t gfar_receive(int irq, void *grp_id)
2332 {
2333 	struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2334 	unsigned long flags;
2335 	u32 imask, ievent;
2336 
2337 	ievent = gfar_read(&grp->regs->ievent);
2338 
2339 	if (unlikely(ievent & IEVENT_FGPI)) {
2340 		gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2341 		return IRQ_HANDLED;
2342 	}
2343 
2344 	if (likely(napi_schedule_prep(&grp->napi_rx))) {
2345 		spin_lock_irqsave(&grp->grplock, flags);
2346 		imask = gfar_read(&grp->regs->imask);
2347 		imask &= IMASK_RX_DISABLED;
2348 		gfar_write(&grp->regs->imask, imask);
2349 		spin_unlock_irqrestore(&grp->grplock, flags);
2350 		__napi_schedule(&grp->napi_rx);
2351 	} else {
2352 		/* Clear IEVENT, so interrupts aren't called again
2353 		 * because of the packets that have already arrived.
2354 		 */
2355 		gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2356 	}
2357 
2358 	return IRQ_HANDLED;
2359 }
2360 
2361 /* Interrupt Handler for Transmit complete */
2362 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2363 {
2364 	struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2365 	unsigned long flags;
2366 	u32 imask;
2367 
2368 	if (likely(napi_schedule_prep(&grp->napi_tx))) {
2369 		spin_lock_irqsave(&grp->grplock, flags);
2370 		imask = gfar_read(&grp->regs->imask);
2371 		imask &= IMASK_TX_DISABLED;
2372 		gfar_write(&grp->regs->imask, imask);
2373 		spin_unlock_irqrestore(&grp->grplock, flags);
2374 		__napi_schedule(&grp->napi_tx);
2375 	} else {
2376 		/* Clear IEVENT, so interrupts aren't called again
2377 		 * because of the packets that have already arrived.
2378 		 */
2379 		gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2380 	}
2381 
2382 	return IRQ_HANDLED;
2383 }
2384 
2385 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2386 			     struct sk_buff *skb, bool first)
2387 {
2388 	int size = lstatus & BD_LENGTH_MASK;
2389 	struct page *page = rxb->page;
2390 
2391 	if (likely(first)) {
2392 		skb_put(skb, size);
2393 	} else {
2394 		/* the last fragments' length contains the full frame length */
2395 		if (lstatus & BD_LFLAG(RXBD_LAST))
2396 			size -= skb->len;
2397 
2398 		skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2399 				rxb->page_offset + RXBUF_ALIGNMENT,
2400 				size, GFAR_RXB_TRUESIZE);
2401 	}
2402 
2403 	/* try reuse page */
2404 	if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2405 		return false;
2406 
2407 	/* change offset to the other half */
2408 	rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2409 
2410 	page_ref_inc(page);
2411 
2412 	return true;
2413 }
2414 
2415 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2416 			       struct gfar_rx_buff *old_rxb)
2417 {
2418 	struct gfar_rx_buff *new_rxb;
2419 	u16 nta = rxq->next_to_alloc;
2420 
2421 	new_rxb = &rxq->rx_buff[nta];
2422 
2423 	/* find next buf that can reuse a page */
2424 	nta++;
2425 	rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2426 
2427 	/* copy page reference */
2428 	*new_rxb = *old_rxb;
2429 
2430 	/* sync for use by the device */
2431 	dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2432 					 old_rxb->page_offset,
2433 					 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2434 }
2435 
2436 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2437 					    u32 lstatus, struct sk_buff *skb)
2438 {
2439 	struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2440 	struct page *page = rxb->page;
2441 	bool first = false;
2442 
2443 	if (likely(!skb)) {
2444 		void *buff_addr = page_address(page) + rxb->page_offset;
2445 
2446 		skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2447 		if (unlikely(!skb)) {
2448 			gfar_rx_alloc_err(rx_queue);
2449 			return NULL;
2450 		}
2451 		skb_reserve(skb, RXBUF_ALIGNMENT);
2452 		first = true;
2453 	}
2454 
2455 	dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2456 				      GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2457 
2458 	if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2459 		/* reuse the free half of the page */
2460 		gfar_reuse_rx_page(rx_queue, rxb);
2461 	} else {
2462 		/* page cannot be reused, unmap it */
2463 		dma_unmap_page(rx_queue->dev, rxb->dma,
2464 			       PAGE_SIZE, DMA_FROM_DEVICE);
2465 	}
2466 
2467 	/* clear rxb content */
2468 	rxb->page = NULL;
2469 
2470 	return skb;
2471 }
2472 
2473 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2474 {
2475 	/* If valid headers were found, and valid sums
2476 	 * were verified, then we tell the kernel that no
2477 	 * checksumming is necessary.  Otherwise, it is [FIXME]
2478 	 */
2479 	if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2480 	    (RXFCB_CIP | RXFCB_CTU))
2481 		skb->ip_summed = CHECKSUM_UNNECESSARY;
2482 	else
2483 		skb_checksum_none_assert(skb);
2484 }
2485 
2486 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2487 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2488 {
2489 	struct gfar_private *priv = netdev_priv(ndev);
2490 	struct rxfcb *fcb = NULL;
2491 
2492 	/* fcb is at the beginning if exists */
2493 	fcb = (struct rxfcb *)skb->data;
2494 
2495 	/* Remove the FCB from the skb
2496 	 * Remove the padded bytes, if there are any
2497 	 */
2498 	if (priv->uses_rxfcb)
2499 		skb_pull(skb, GMAC_FCB_LEN);
2500 
2501 	/* Get receive timestamp from the skb */
2502 	if (priv->hwts_rx_en) {
2503 		struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2504 		u64 *ns = (u64 *) skb->data;
2505 
2506 		memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2507 		shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2508 	}
2509 
2510 	if (priv->padding)
2511 		skb_pull(skb, priv->padding);
2512 
2513 	/* Trim off the FCS */
2514 	pskb_trim(skb, skb->len - ETH_FCS_LEN);
2515 
2516 	if (ndev->features & NETIF_F_RXCSUM)
2517 		gfar_rx_checksum(skb, fcb);
2518 
2519 	/* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2520 	 * Even if vlan rx accel is disabled, on some chips
2521 	 * RXFCB_VLN is pseudo randomly set.
2522 	 */
2523 	if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2524 	    be16_to_cpu(fcb->flags) & RXFCB_VLN)
2525 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2526 				       be16_to_cpu(fcb->vlctl));
2527 }
2528 
2529 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2530  * until the budget/quota has been reached. Returns the number
2531  * of frames handled
2532  */
2533 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2534 			      int rx_work_limit)
2535 {
2536 	struct net_device *ndev = rx_queue->ndev;
2537 	struct gfar_private *priv = netdev_priv(ndev);
2538 	struct rxbd8 *bdp;
2539 	int i, howmany = 0;
2540 	struct sk_buff *skb = rx_queue->skb;
2541 	int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2542 	unsigned int total_bytes = 0, total_pkts = 0;
2543 
2544 	/* Get the first full descriptor */
2545 	i = rx_queue->next_to_clean;
2546 
2547 	while (rx_work_limit--) {
2548 		u32 lstatus;
2549 
2550 		if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2551 			gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2552 			cleaned_cnt = 0;
2553 		}
2554 
2555 		bdp = &rx_queue->rx_bd_base[i];
2556 		lstatus = be32_to_cpu(bdp->lstatus);
2557 		if (lstatus & BD_LFLAG(RXBD_EMPTY))
2558 			break;
2559 
2560 		/* order rx buffer descriptor reads */
2561 		rmb();
2562 
2563 		/* fetch next to clean buffer from the ring */
2564 		skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2565 		if (unlikely(!skb))
2566 			break;
2567 
2568 		cleaned_cnt++;
2569 		howmany++;
2570 
2571 		if (unlikely(++i == rx_queue->rx_ring_size))
2572 			i = 0;
2573 
2574 		rx_queue->next_to_clean = i;
2575 
2576 		/* fetch next buffer if not the last in frame */
2577 		if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2578 			continue;
2579 
2580 		if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2581 			count_errors(lstatus, ndev);
2582 
2583 			/* discard faulty buffer */
2584 			dev_kfree_skb(skb);
2585 			skb = NULL;
2586 			rx_queue->stats.rx_dropped++;
2587 			continue;
2588 		}
2589 
2590 		gfar_process_frame(ndev, skb);
2591 
2592 		/* Increment the number of packets */
2593 		total_pkts++;
2594 		total_bytes += skb->len;
2595 
2596 		skb_record_rx_queue(skb, rx_queue->qindex);
2597 
2598 		skb->protocol = eth_type_trans(skb, ndev);
2599 
2600 		/* Send the packet up the stack */
2601 		napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2602 
2603 		skb = NULL;
2604 	}
2605 
2606 	/* Store incomplete frames for completion */
2607 	rx_queue->skb = skb;
2608 
2609 	rx_queue->stats.rx_packets += total_pkts;
2610 	rx_queue->stats.rx_bytes += total_bytes;
2611 
2612 	if (cleaned_cnt)
2613 		gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2614 
2615 	/* Update Last Free RxBD pointer for LFC */
2616 	if (unlikely(priv->tx_actual_en)) {
2617 		u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2618 
2619 		gfar_write(rx_queue->rfbptr, bdp_dma);
2620 	}
2621 
2622 	return howmany;
2623 }
2624 
2625 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2626 {
2627 	struct gfar_priv_grp *gfargrp =
2628 		container_of(napi, struct gfar_priv_grp, napi_rx);
2629 	struct gfar __iomem *regs = gfargrp->regs;
2630 	struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2631 	int work_done = 0;
2632 
2633 	/* Clear IEVENT, so interrupts aren't called again
2634 	 * because of the packets that have already arrived
2635 	 */
2636 	gfar_write(&regs->ievent, IEVENT_RX_MASK);
2637 
2638 	work_done = gfar_clean_rx_ring(rx_queue, budget);
2639 
2640 	if (work_done < budget) {
2641 		u32 imask;
2642 		napi_complete_done(napi, work_done);
2643 		/* Clear the halt bit in RSTAT */
2644 		gfar_write(&regs->rstat, gfargrp->rstat);
2645 
2646 		spin_lock_irq(&gfargrp->grplock);
2647 		imask = gfar_read(&regs->imask);
2648 		imask |= IMASK_RX_DEFAULT;
2649 		gfar_write(&regs->imask, imask);
2650 		spin_unlock_irq(&gfargrp->grplock);
2651 	}
2652 
2653 	return work_done;
2654 }
2655 
2656 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2657 {
2658 	struct gfar_priv_grp *gfargrp =
2659 		container_of(napi, struct gfar_priv_grp, napi_tx);
2660 	struct gfar __iomem *regs = gfargrp->regs;
2661 	struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2662 	u32 imask;
2663 
2664 	/* Clear IEVENT, so interrupts aren't called again
2665 	 * because of the packets that have already arrived
2666 	 */
2667 	gfar_write(&regs->ievent, IEVENT_TX_MASK);
2668 
2669 	/* run Tx cleanup to completion */
2670 	if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2671 		gfar_clean_tx_ring(tx_queue);
2672 
2673 	napi_complete(napi);
2674 
2675 	spin_lock_irq(&gfargrp->grplock);
2676 	imask = gfar_read(&regs->imask);
2677 	imask |= IMASK_TX_DEFAULT;
2678 	gfar_write(&regs->imask, imask);
2679 	spin_unlock_irq(&gfargrp->grplock);
2680 
2681 	return 0;
2682 }
2683 
2684 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2685 {
2686 	struct gfar_priv_grp *gfargrp =
2687 		container_of(napi, struct gfar_priv_grp, napi_rx);
2688 	struct gfar_private *priv = gfargrp->priv;
2689 	struct gfar __iomem *regs = gfargrp->regs;
2690 	struct gfar_priv_rx_q *rx_queue = NULL;
2691 	int work_done = 0, work_done_per_q = 0;
2692 	int i, budget_per_q = 0;
2693 	unsigned long rstat_rxf;
2694 	int num_act_queues;
2695 
2696 	/* Clear IEVENT, so interrupts aren't called again
2697 	 * because of the packets that have already arrived
2698 	 */
2699 	gfar_write(&regs->ievent, IEVENT_RX_MASK);
2700 
2701 	rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2702 
2703 	num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2704 	if (num_act_queues)
2705 		budget_per_q = budget/num_act_queues;
2706 
2707 	for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2708 		/* skip queue if not active */
2709 		if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2710 			continue;
2711 
2712 		rx_queue = priv->rx_queue[i];
2713 		work_done_per_q =
2714 			gfar_clean_rx_ring(rx_queue, budget_per_q);
2715 		work_done += work_done_per_q;
2716 
2717 		/* finished processing this queue */
2718 		if (work_done_per_q < budget_per_q) {
2719 			/* clear active queue hw indication */
2720 			gfar_write(&regs->rstat,
2721 				   RSTAT_CLEAR_RXF0 >> i);
2722 			num_act_queues--;
2723 
2724 			if (!num_act_queues)
2725 				break;
2726 		}
2727 	}
2728 
2729 	if (!num_act_queues) {
2730 		u32 imask;
2731 		napi_complete_done(napi, work_done);
2732 
2733 		/* Clear the halt bit in RSTAT */
2734 		gfar_write(&regs->rstat, gfargrp->rstat);
2735 
2736 		spin_lock_irq(&gfargrp->grplock);
2737 		imask = gfar_read(&regs->imask);
2738 		imask |= IMASK_RX_DEFAULT;
2739 		gfar_write(&regs->imask, imask);
2740 		spin_unlock_irq(&gfargrp->grplock);
2741 	}
2742 
2743 	return work_done;
2744 }
2745 
2746 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2747 {
2748 	struct gfar_priv_grp *gfargrp =
2749 		container_of(napi, struct gfar_priv_grp, napi_tx);
2750 	struct gfar_private *priv = gfargrp->priv;
2751 	struct gfar __iomem *regs = gfargrp->regs;
2752 	struct gfar_priv_tx_q *tx_queue = NULL;
2753 	int has_tx_work = 0;
2754 	int i;
2755 
2756 	/* Clear IEVENT, so interrupts aren't called again
2757 	 * because of the packets that have already arrived
2758 	 */
2759 	gfar_write(&regs->ievent, IEVENT_TX_MASK);
2760 
2761 	for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2762 		tx_queue = priv->tx_queue[i];
2763 		/* run Tx cleanup to completion */
2764 		if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2765 			gfar_clean_tx_ring(tx_queue);
2766 			has_tx_work = 1;
2767 		}
2768 	}
2769 
2770 	if (!has_tx_work) {
2771 		u32 imask;
2772 		napi_complete(napi);
2773 
2774 		spin_lock_irq(&gfargrp->grplock);
2775 		imask = gfar_read(&regs->imask);
2776 		imask |= IMASK_TX_DEFAULT;
2777 		gfar_write(&regs->imask, imask);
2778 		spin_unlock_irq(&gfargrp->grplock);
2779 	}
2780 
2781 	return 0;
2782 }
2783 
2784 /* GFAR error interrupt handler */
2785 static irqreturn_t gfar_error(int irq, void *grp_id)
2786 {
2787 	struct gfar_priv_grp *gfargrp = grp_id;
2788 	struct gfar __iomem *regs = gfargrp->regs;
2789 	struct gfar_private *priv= gfargrp->priv;
2790 	struct net_device *dev = priv->ndev;
2791 
2792 	/* Save ievent for future reference */
2793 	u32 events = gfar_read(&regs->ievent);
2794 
2795 	/* Clear IEVENT */
2796 	gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2797 
2798 	/* Magic Packet is not an error. */
2799 	if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2800 	    (events & IEVENT_MAG))
2801 		events &= ~IEVENT_MAG;
2802 
2803 	/* Hmm... */
2804 	if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2805 		netdev_dbg(dev,
2806 			   "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2807 			   events, gfar_read(&regs->imask));
2808 
2809 	/* Update the error counters */
2810 	if (events & IEVENT_TXE) {
2811 		dev->stats.tx_errors++;
2812 
2813 		if (events & IEVENT_LC)
2814 			dev->stats.tx_window_errors++;
2815 		if (events & IEVENT_CRL)
2816 			dev->stats.tx_aborted_errors++;
2817 		if (events & IEVENT_XFUN) {
2818 			netif_dbg(priv, tx_err, dev,
2819 				  "TX FIFO underrun, packet dropped\n");
2820 			dev->stats.tx_dropped++;
2821 			atomic64_inc(&priv->extra_stats.tx_underrun);
2822 
2823 			schedule_work(&priv->reset_task);
2824 		}
2825 		netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2826 	}
2827 	if (events & IEVENT_BSY) {
2828 		dev->stats.rx_over_errors++;
2829 		atomic64_inc(&priv->extra_stats.rx_bsy);
2830 
2831 		netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2832 			  gfar_read(&regs->rstat));
2833 	}
2834 	if (events & IEVENT_BABR) {
2835 		dev->stats.rx_errors++;
2836 		atomic64_inc(&priv->extra_stats.rx_babr);
2837 
2838 		netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2839 	}
2840 	if (events & IEVENT_EBERR) {
2841 		atomic64_inc(&priv->extra_stats.eberr);
2842 		netif_dbg(priv, rx_err, dev, "bus error\n");
2843 	}
2844 	if (events & IEVENT_RXC)
2845 		netif_dbg(priv, rx_status, dev, "control frame\n");
2846 
2847 	if (events & IEVENT_BABT) {
2848 		atomic64_inc(&priv->extra_stats.tx_babt);
2849 		netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2850 	}
2851 	return IRQ_HANDLED;
2852 }
2853 
2854 /* The interrupt handler for devices with one interrupt */
2855 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2856 {
2857 	struct gfar_priv_grp *gfargrp = grp_id;
2858 
2859 	/* Save ievent for future reference */
2860 	u32 events = gfar_read(&gfargrp->regs->ievent);
2861 
2862 	/* Check for reception */
2863 	if (events & IEVENT_RX_MASK)
2864 		gfar_receive(irq, grp_id);
2865 
2866 	/* Check for transmit completion */
2867 	if (events & IEVENT_TX_MASK)
2868 		gfar_transmit(irq, grp_id);
2869 
2870 	/* Check for errors */
2871 	if (events & IEVENT_ERR_MASK)
2872 		gfar_error(irq, grp_id);
2873 
2874 	return IRQ_HANDLED;
2875 }
2876 
2877 #ifdef CONFIG_NET_POLL_CONTROLLER
2878 /* Polling 'interrupt' - used by things like netconsole to send skbs
2879  * without having to re-enable interrupts. It's not called while
2880  * the interrupt routine is executing.
2881  */
2882 static void gfar_netpoll(struct net_device *dev)
2883 {
2884 	struct gfar_private *priv = netdev_priv(dev);
2885 	int i;
2886 
2887 	/* If the device has multiple interrupts, run tx/rx */
2888 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2889 		for (i = 0; i < priv->num_grps; i++) {
2890 			struct gfar_priv_grp *grp = &priv->gfargrp[i];
2891 
2892 			disable_irq(gfar_irq(grp, TX)->irq);
2893 			disable_irq(gfar_irq(grp, RX)->irq);
2894 			disable_irq(gfar_irq(grp, ER)->irq);
2895 			gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2896 			enable_irq(gfar_irq(grp, ER)->irq);
2897 			enable_irq(gfar_irq(grp, RX)->irq);
2898 			enable_irq(gfar_irq(grp, TX)->irq);
2899 		}
2900 	} else {
2901 		for (i = 0; i < priv->num_grps; i++) {
2902 			struct gfar_priv_grp *grp = &priv->gfargrp[i];
2903 
2904 			disable_irq(gfar_irq(grp, TX)->irq);
2905 			gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2906 			enable_irq(gfar_irq(grp, TX)->irq);
2907 		}
2908 	}
2909 }
2910 #endif
2911 
2912 static void free_grp_irqs(struct gfar_priv_grp *grp)
2913 {
2914 	free_irq(gfar_irq(grp, TX)->irq, grp);
2915 	free_irq(gfar_irq(grp, RX)->irq, grp);
2916 	free_irq(gfar_irq(grp, ER)->irq, grp);
2917 }
2918 
2919 static int register_grp_irqs(struct gfar_priv_grp *grp)
2920 {
2921 	struct gfar_private *priv = grp->priv;
2922 	struct net_device *dev = priv->ndev;
2923 	int err;
2924 
2925 	/* If the device has multiple interrupts, register for
2926 	 * them.  Otherwise, only register for the one
2927 	 */
2928 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2929 		/* Install our interrupt handlers for Error,
2930 		 * Transmit, and Receive
2931 		 */
2932 		err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2933 				  gfar_irq(grp, ER)->name, grp);
2934 		if (err < 0) {
2935 			netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2936 				  gfar_irq(grp, ER)->irq);
2937 
2938 			goto err_irq_fail;
2939 		}
2940 		enable_irq_wake(gfar_irq(grp, ER)->irq);
2941 
2942 		err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2943 				  gfar_irq(grp, TX)->name, grp);
2944 		if (err < 0) {
2945 			netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2946 				  gfar_irq(grp, TX)->irq);
2947 			goto tx_irq_fail;
2948 		}
2949 		err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2950 				  gfar_irq(grp, RX)->name, grp);
2951 		if (err < 0) {
2952 			netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2953 				  gfar_irq(grp, RX)->irq);
2954 			goto rx_irq_fail;
2955 		}
2956 		enable_irq_wake(gfar_irq(grp, RX)->irq);
2957 
2958 	} else {
2959 		err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2960 				  gfar_irq(grp, TX)->name, grp);
2961 		if (err < 0) {
2962 			netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2963 				  gfar_irq(grp, TX)->irq);
2964 			goto err_irq_fail;
2965 		}
2966 		enable_irq_wake(gfar_irq(grp, TX)->irq);
2967 	}
2968 
2969 	return 0;
2970 
2971 rx_irq_fail:
2972 	free_irq(gfar_irq(grp, TX)->irq, grp);
2973 tx_irq_fail:
2974 	free_irq(gfar_irq(grp, ER)->irq, grp);
2975 err_irq_fail:
2976 	return err;
2977 
2978 }
2979 
2980 static void gfar_free_irq(struct gfar_private *priv)
2981 {
2982 	int i;
2983 
2984 	/* Free the IRQs */
2985 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2986 		for (i = 0; i < priv->num_grps; i++)
2987 			free_grp_irqs(&priv->gfargrp[i]);
2988 	} else {
2989 		for (i = 0; i < priv->num_grps; i++)
2990 			free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2991 				 &priv->gfargrp[i]);
2992 	}
2993 }
2994 
2995 static int gfar_request_irq(struct gfar_private *priv)
2996 {
2997 	int err, i, j;
2998 
2999 	for (i = 0; i < priv->num_grps; i++) {
3000 		err = register_grp_irqs(&priv->gfargrp[i]);
3001 		if (err) {
3002 			for (j = 0; j < i; j++)
3003 				free_grp_irqs(&priv->gfargrp[j]);
3004 			return err;
3005 		}
3006 	}
3007 
3008 	return 0;
3009 }
3010 
3011 /* Called when something needs to use the ethernet device
3012  * Returns 0 for success.
3013  */
3014 static int gfar_enet_open(struct net_device *dev)
3015 {
3016 	struct gfar_private *priv = netdev_priv(dev);
3017 	int err;
3018 
3019 	err = init_phy(dev);
3020 	if (err)
3021 		return err;
3022 
3023 	err = gfar_request_irq(priv);
3024 	if (err)
3025 		return err;
3026 
3027 	err = startup_gfar(dev);
3028 	if (err)
3029 		return err;
3030 
3031 	return err;
3032 }
3033 
3034 /* Stops the kernel queue, and halts the controller */
3035 static int gfar_close(struct net_device *dev)
3036 {
3037 	struct gfar_private *priv = netdev_priv(dev);
3038 
3039 	cancel_work_sync(&priv->reset_task);
3040 	stop_gfar(dev);
3041 
3042 	/* Disconnect from the PHY */
3043 	phy_disconnect(dev->phydev);
3044 
3045 	gfar_free_irq(priv);
3046 
3047 	return 0;
3048 }
3049 
3050 /* Clears each of the exact match registers to zero, so they
3051  * don't interfere with normal reception
3052  */
3053 static void gfar_clear_exact_match(struct net_device *dev)
3054 {
3055 	int idx;
3056 	static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3057 
3058 	for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3059 		gfar_set_mac_for_addr(dev, idx, zero_arr);
3060 }
3061 
3062 /* Update the hash table based on the current list of multicast
3063  * addresses we subscribe to.  Also, change the promiscuity of
3064  * the device based on the flags (this function is called
3065  * whenever dev->flags is changed
3066  */
3067 static void gfar_set_multi(struct net_device *dev)
3068 {
3069 	struct netdev_hw_addr *ha;
3070 	struct gfar_private *priv = netdev_priv(dev);
3071 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3072 	u32 tempval;
3073 
3074 	if (dev->flags & IFF_PROMISC) {
3075 		/* Set RCTRL to PROM */
3076 		tempval = gfar_read(&regs->rctrl);
3077 		tempval |= RCTRL_PROM;
3078 		gfar_write(&regs->rctrl, tempval);
3079 	} else {
3080 		/* Set RCTRL to not PROM */
3081 		tempval = gfar_read(&regs->rctrl);
3082 		tempval &= ~(RCTRL_PROM);
3083 		gfar_write(&regs->rctrl, tempval);
3084 	}
3085 
3086 	if (dev->flags & IFF_ALLMULTI) {
3087 		/* Set the hash to rx all multicast frames */
3088 		gfar_write(&regs->igaddr0, 0xffffffff);
3089 		gfar_write(&regs->igaddr1, 0xffffffff);
3090 		gfar_write(&regs->igaddr2, 0xffffffff);
3091 		gfar_write(&regs->igaddr3, 0xffffffff);
3092 		gfar_write(&regs->igaddr4, 0xffffffff);
3093 		gfar_write(&regs->igaddr5, 0xffffffff);
3094 		gfar_write(&regs->igaddr6, 0xffffffff);
3095 		gfar_write(&regs->igaddr7, 0xffffffff);
3096 		gfar_write(&regs->gaddr0, 0xffffffff);
3097 		gfar_write(&regs->gaddr1, 0xffffffff);
3098 		gfar_write(&regs->gaddr2, 0xffffffff);
3099 		gfar_write(&regs->gaddr3, 0xffffffff);
3100 		gfar_write(&regs->gaddr4, 0xffffffff);
3101 		gfar_write(&regs->gaddr5, 0xffffffff);
3102 		gfar_write(&regs->gaddr6, 0xffffffff);
3103 		gfar_write(&regs->gaddr7, 0xffffffff);
3104 	} else {
3105 		int em_num;
3106 		int idx;
3107 
3108 		/* zero out the hash */
3109 		gfar_write(&regs->igaddr0, 0x0);
3110 		gfar_write(&regs->igaddr1, 0x0);
3111 		gfar_write(&regs->igaddr2, 0x0);
3112 		gfar_write(&regs->igaddr3, 0x0);
3113 		gfar_write(&regs->igaddr4, 0x0);
3114 		gfar_write(&regs->igaddr5, 0x0);
3115 		gfar_write(&regs->igaddr6, 0x0);
3116 		gfar_write(&regs->igaddr7, 0x0);
3117 		gfar_write(&regs->gaddr0, 0x0);
3118 		gfar_write(&regs->gaddr1, 0x0);
3119 		gfar_write(&regs->gaddr2, 0x0);
3120 		gfar_write(&regs->gaddr3, 0x0);
3121 		gfar_write(&regs->gaddr4, 0x0);
3122 		gfar_write(&regs->gaddr5, 0x0);
3123 		gfar_write(&regs->gaddr6, 0x0);
3124 		gfar_write(&regs->gaddr7, 0x0);
3125 
3126 		/* If we have extended hash tables, we need to
3127 		 * clear the exact match registers to prepare for
3128 		 * setting them
3129 		 */
3130 		if (priv->extended_hash) {
3131 			em_num = GFAR_EM_NUM + 1;
3132 			gfar_clear_exact_match(dev);
3133 			idx = 1;
3134 		} else {
3135 			idx = 0;
3136 			em_num = 0;
3137 		}
3138 
3139 		if (netdev_mc_empty(dev))
3140 			return;
3141 
3142 		/* Parse the list, and set the appropriate bits */
3143 		netdev_for_each_mc_addr(ha, dev) {
3144 			if (idx < em_num) {
3145 				gfar_set_mac_for_addr(dev, idx, ha->addr);
3146 				idx++;
3147 			} else
3148 				gfar_set_hash_for_addr(dev, ha->addr);
3149 		}
3150 	}
3151 }
3152 
3153 void gfar_mac_reset(struct gfar_private *priv)
3154 {
3155 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3156 	u32 tempval;
3157 
3158 	/* Reset MAC layer */
3159 	gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
3160 
3161 	/* We need to delay at least 3 TX clocks */
3162 	udelay(3);
3163 
3164 	/* the soft reset bit is not self-resetting, so we need to
3165 	 * clear it before resuming normal operation
3166 	 */
3167 	gfar_write(&regs->maccfg1, 0);
3168 
3169 	udelay(3);
3170 
3171 	gfar_rx_offload_en(priv);
3172 
3173 	/* Initialize the max receive frame/buffer lengths */
3174 	gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3175 	gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
3176 
3177 	/* Initialize the Minimum Frame Length Register */
3178 	gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
3179 
3180 	/* Initialize MACCFG2. */
3181 	tempval = MACCFG2_INIT_SETTINGS;
3182 
3183 	/* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3184 	 * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
3185 	 * and by checking RxBD[LG] and discarding larger than MAXFRM.
3186 	 */
3187 	if (gfar_has_errata(priv, GFAR_ERRATA_74))
3188 		tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3189 
3190 	gfar_write(&regs->maccfg2, tempval);
3191 
3192 	/* Clear mac addr hash registers */
3193 	gfar_write(&regs->igaddr0, 0);
3194 	gfar_write(&regs->igaddr1, 0);
3195 	gfar_write(&regs->igaddr2, 0);
3196 	gfar_write(&regs->igaddr3, 0);
3197 	gfar_write(&regs->igaddr4, 0);
3198 	gfar_write(&regs->igaddr5, 0);
3199 	gfar_write(&regs->igaddr6, 0);
3200 	gfar_write(&regs->igaddr7, 0);
3201 
3202 	gfar_write(&regs->gaddr0, 0);
3203 	gfar_write(&regs->gaddr1, 0);
3204 	gfar_write(&regs->gaddr2, 0);
3205 	gfar_write(&regs->gaddr3, 0);
3206 	gfar_write(&regs->gaddr4, 0);
3207 	gfar_write(&regs->gaddr5, 0);
3208 	gfar_write(&regs->gaddr6, 0);
3209 	gfar_write(&regs->gaddr7, 0);
3210 
3211 	if (priv->extended_hash)
3212 		gfar_clear_exact_match(priv->ndev);
3213 
3214 	gfar_mac_rx_config(priv);
3215 
3216 	gfar_mac_tx_config(priv);
3217 
3218 	gfar_set_mac_address(priv->ndev);
3219 
3220 	gfar_set_multi(priv->ndev);
3221 
3222 	/* clear ievent and imask before configuring coalescing */
3223 	gfar_ints_disable(priv);
3224 
3225 	/* Configure the coalescing support */
3226 	gfar_configure_coalescing_all(priv);
3227 }
3228 
3229 static void gfar_hw_init(struct gfar_private *priv)
3230 {
3231 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3232 	u32 attrs;
3233 
3234 	/* Stop the DMA engine now, in case it was running before
3235 	 * (The firmware could have used it, and left it running).
3236 	 */
3237 	gfar_halt(priv);
3238 
3239 	gfar_mac_reset(priv);
3240 
3241 	/* Zero out the rmon mib registers if it has them */
3242 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3243 		memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3244 
3245 		/* Mask off the CAM interrupts */
3246 		gfar_write(&regs->rmon.cam1, 0xffffffff);
3247 		gfar_write(&regs->rmon.cam2, 0xffffffff);
3248 	}
3249 
3250 	/* Initialize ECNTRL */
3251 	gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
3252 
3253 	/* Set the extraction length and index */
3254 	attrs = ATTRELI_EL(priv->rx_stash_size) |
3255 		ATTRELI_EI(priv->rx_stash_index);
3256 
3257 	gfar_write(&regs->attreli, attrs);
3258 
3259 	/* Start with defaults, and add stashing
3260 	 * depending on driver parameters
3261 	 */
3262 	attrs = ATTR_INIT_SETTINGS;
3263 
3264 	if (priv->bd_stash_en)
3265 		attrs |= ATTR_BDSTASH;
3266 
3267 	if (priv->rx_stash_size != 0)
3268 		attrs |= ATTR_BUFSTASH;
3269 
3270 	gfar_write(&regs->attr, attrs);
3271 
3272 	/* FIFO configs */
3273 	gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3274 	gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3275 	gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3276 
3277 	/* Program the interrupt steering regs, only for MG devices */
3278 	if (priv->num_grps > 1)
3279 		gfar_write_isrg(priv);
3280 }
3281 
3282 static const struct net_device_ops gfar_netdev_ops = {
3283 	.ndo_open = gfar_enet_open,
3284 	.ndo_start_xmit = gfar_start_xmit,
3285 	.ndo_stop = gfar_close,
3286 	.ndo_change_mtu = gfar_change_mtu,
3287 	.ndo_set_features = gfar_set_features,
3288 	.ndo_set_rx_mode = gfar_set_multi,
3289 	.ndo_tx_timeout = gfar_timeout,
3290 	.ndo_do_ioctl = gfar_ioctl,
3291 	.ndo_get_stats = gfar_get_stats,
3292 	.ndo_change_carrier = fixed_phy_change_carrier,
3293 	.ndo_set_mac_address = gfar_set_mac_addr,
3294 	.ndo_validate_addr = eth_validate_addr,
3295 #ifdef CONFIG_NET_POLL_CONTROLLER
3296 	.ndo_poll_controller = gfar_netpoll,
3297 #endif
3298 };
3299 
3300 /* Set up the ethernet device structure, private data,
3301  * and anything else we need before we start
3302  */
3303 static int gfar_probe(struct platform_device *ofdev)
3304 {
3305 	struct device_node *np = ofdev->dev.of_node;
3306 	struct net_device *dev = NULL;
3307 	struct gfar_private *priv = NULL;
3308 	int err = 0, i;
3309 
3310 	err = gfar_of_init(ofdev, &dev);
3311 
3312 	if (err)
3313 		return err;
3314 
3315 	priv = netdev_priv(dev);
3316 	priv->ndev = dev;
3317 	priv->ofdev = ofdev;
3318 	priv->dev = &ofdev->dev;
3319 	SET_NETDEV_DEV(dev, &ofdev->dev);
3320 
3321 	INIT_WORK(&priv->reset_task, gfar_reset_task);
3322 
3323 	platform_set_drvdata(ofdev, priv);
3324 
3325 	gfar_detect_errata(priv);
3326 
3327 	/* Set the dev->base_addr to the gfar reg region */
3328 	dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3329 
3330 	/* Fill in the dev structure */
3331 	dev->watchdog_timeo = TX_TIMEOUT;
3332 	/* MTU range: 50 - 9586 */
3333 	dev->mtu = 1500;
3334 	dev->min_mtu = 50;
3335 	dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3336 	dev->netdev_ops = &gfar_netdev_ops;
3337 	dev->ethtool_ops = &gfar_ethtool_ops;
3338 
3339 	/* Register for napi ...We are registering NAPI for each grp */
3340 	for (i = 0; i < priv->num_grps; i++) {
3341 		if (priv->poll_mode == GFAR_SQ_POLLING) {
3342 			netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3343 				       gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3344 			netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3345 				       gfar_poll_tx_sq, 2);
3346 		} else {
3347 			netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3348 				       gfar_poll_rx, GFAR_DEV_WEIGHT);
3349 			netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3350 				       gfar_poll_tx, 2);
3351 		}
3352 	}
3353 
3354 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3355 		dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3356 				   NETIF_F_RXCSUM;
3357 		dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3358 				 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3359 	}
3360 
3361 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3362 		dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3363 				    NETIF_F_HW_VLAN_CTAG_RX;
3364 		dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3365 	}
3366 
3367 	dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3368 
3369 	gfar_init_addr_hash_table(priv);
3370 
3371 	/* Insert receive time stamps into padding alignment bytes, and
3372 	 * plus 2 bytes padding to ensure the cpu alignment.
3373 	 */
3374 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3375 		priv->padding = 8 + DEFAULT_PADDING;
3376 
3377 	if (dev->features & NETIF_F_IP_CSUM ||
3378 	    priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3379 		dev->needed_headroom = GMAC_FCB_LEN;
3380 
3381 	/* Initializing some of the rx/tx queue level parameters */
3382 	for (i = 0; i < priv->num_tx_queues; i++) {
3383 		priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3384 		priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3385 		priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3386 		priv->tx_queue[i]->txic = DEFAULT_TXIC;
3387 	}
3388 
3389 	for (i = 0; i < priv->num_rx_queues; i++) {
3390 		priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3391 		priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3392 		priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3393 	}
3394 
3395 	/* Always enable rx filer if available */
3396 	priv->rx_filer_enable =
3397 	    (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3398 	/* Enable most messages by default */
3399 	priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3400 	/* use pritority h/w tx queue scheduling for single queue devices */
3401 	if (priv->num_tx_queues == 1)
3402 		priv->prio_sched_en = 1;
3403 
3404 	set_bit(GFAR_DOWN, &priv->state);
3405 
3406 	gfar_hw_init(priv);
3407 
3408 	/* Carrier starts down, phylib will bring it up */
3409 	netif_carrier_off(dev);
3410 
3411 	err = register_netdev(dev);
3412 
3413 	if (err) {
3414 		pr_err("%s: Cannot register net device, aborting\n", dev->name);
3415 		goto register_fail;
3416 	}
3417 
3418 	if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3419 		priv->wol_supported |= GFAR_WOL_MAGIC;
3420 
3421 	if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3422 	    priv->rx_filer_enable)
3423 		priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3424 
3425 	device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3426 
3427 	/* fill out IRQ number and name fields */
3428 	for (i = 0; i < priv->num_grps; i++) {
3429 		struct gfar_priv_grp *grp = &priv->gfargrp[i];
3430 		if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3431 			sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3432 				dev->name, "_g", '0' + i, "_tx");
3433 			sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3434 				dev->name, "_g", '0' + i, "_rx");
3435 			sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3436 				dev->name, "_g", '0' + i, "_er");
3437 		} else
3438 			strcpy(gfar_irq(grp, TX)->name, dev->name);
3439 	}
3440 
3441 	/* Initialize the filer table */
3442 	gfar_init_filer_table(priv);
3443 
3444 	/* Print out the device info */
3445 	netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3446 
3447 	/* Even more device info helps when determining which kernel
3448 	 * provided which set of benchmarks.
3449 	 */
3450 	netdev_info(dev, "Running with NAPI enabled\n");
3451 	for (i = 0; i < priv->num_rx_queues; i++)
3452 		netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3453 			    i, priv->rx_queue[i]->rx_ring_size);
3454 	for (i = 0; i < priv->num_tx_queues; i++)
3455 		netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3456 			    i, priv->tx_queue[i]->tx_ring_size);
3457 
3458 	return 0;
3459 
3460 register_fail:
3461 	if (of_phy_is_fixed_link(np))
3462 		of_phy_deregister_fixed_link(np);
3463 	unmap_group_regs(priv);
3464 	gfar_free_rx_queues(priv);
3465 	gfar_free_tx_queues(priv);
3466 	of_node_put(priv->phy_node);
3467 	of_node_put(priv->tbi_node);
3468 	free_gfar_dev(priv);
3469 	return err;
3470 }
3471 
3472 static int gfar_remove(struct platform_device *ofdev)
3473 {
3474 	struct gfar_private *priv = platform_get_drvdata(ofdev);
3475 	struct device_node *np = ofdev->dev.of_node;
3476 
3477 	of_node_put(priv->phy_node);
3478 	of_node_put(priv->tbi_node);
3479 
3480 	unregister_netdev(priv->ndev);
3481 
3482 	if (of_phy_is_fixed_link(np))
3483 		of_phy_deregister_fixed_link(np);
3484 
3485 	unmap_group_regs(priv);
3486 	gfar_free_rx_queues(priv);
3487 	gfar_free_tx_queues(priv);
3488 	free_gfar_dev(priv);
3489 
3490 	return 0;
3491 }
3492 
3493 #ifdef CONFIG_PM
3494 
3495 static void __gfar_filer_disable(struct gfar_private *priv)
3496 {
3497 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3498 	u32 temp;
3499 
3500 	temp = gfar_read(&regs->rctrl);
3501 	temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3502 	gfar_write(&regs->rctrl, temp);
3503 }
3504 
3505 static void __gfar_filer_enable(struct gfar_private *priv)
3506 {
3507 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3508 	u32 temp;
3509 
3510 	temp = gfar_read(&regs->rctrl);
3511 	temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3512 	gfar_write(&regs->rctrl, temp);
3513 }
3514 
3515 /* Filer rules implementing wol capabilities */
3516 static void gfar_filer_config_wol(struct gfar_private *priv)
3517 {
3518 	unsigned int i;
3519 	u32 rqfcr;
3520 
3521 	__gfar_filer_disable(priv);
3522 
3523 	/* clear the filer table, reject any packet by default */
3524 	rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3525 	for (i = 0; i <= MAX_FILER_IDX; i++)
3526 		gfar_write_filer(priv, i, rqfcr, 0);
3527 
3528 	i = 0;
3529 	if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3530 		/* unicast packet, accept it */
3531 		struct net_device *ndev = priv->ndev;
3532 		/* get the default rx queue index */
3533 		u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3534 		u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3535 				    (ndev->dev_addr[1] << 8) |
3536 				     ndev->dev_addr[2];
3537 
3538 		rqfcr = (qindex << 10) | RQFCR_AND |
3539 			RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3540 
3541 		gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3542 
3543 		dest_mac_addr = (ndev->dev_addr[3] << 16) |
3544 				(ndev->dev_addr[4] << 8) |
3545 				 ndev->dev_addr[5];
3546 		rqfcr = (qindex << 10) | RQFCR_GPI |
3547 			RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3548 		gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3549 	}
3550 
3551 	__gfar_filer_enable(priv);
3552 }
3553 
3554 static void gfar_filer_restore_table(struct gfar_private *priv)
3555 {
3556 	u32 rqfcr, rqfpr;
3557 	unsigned int i;
3558 
3559 	__gfar_filer_disable(priv);
3560 
3561 	for (i = 0; i <= MAX_FILER_IDX; i++) {
3562 		rqfcr = priv->ftp_rqfcr[i];
3563 		rqfpr = priv->ftp_rqfpr[i];
3564 		gfar_write_filer(priv, i, rqfcr, rqfpr);
3565 	}
3566 
3567 	__gfar_filer_enable(priv);
3568 }
3569 
3570 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3571 static void gfar_start_wol_filer(struct gfar_private *priv)
3572 {
3573 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3574 	u32 tempval;
3575 	int i = 0;
3576 
3577 	/* Enable Rx hw queues */
3578 	gfar_write(&regs->rqueue, priv->rqueue);
3579 
3580 	/* Initialize DMACTRL to have WWR and WOP */
3581 	tempval = gfar_read(&regs->dmactrl);
3582 	tempval |= DMACTRL_INIT_SETTINGS;
3583 	gfar_write(&regs->dmactrl, tempval);
3584 
3585 	/* Make sure we aren't stopped */
3586 	tempval = gfar_read(&regs->dmactrl);
3587 	tempval &= ~DMACTRL_GRS;
3588 	gfar_write(&regs->dmactrl, tempval);
3589 
3590 	for (i = 0; i < priv->num_grps; i++) {
3591 		regs = priv->gfargrp[i].regs;
3592 		/* Clear RHLT, so that the DMA starts polling now */
3593 		gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
3594 		/* enable the Filer General Purpose Interrupt */
3595 		gfar_write(&regs->imask, IMASK_FGPI);
3596 	}
3597 
3598 	/* Enable Rx DMA */
3599 	tempval = gfar_read(&regs->maccfg1);
3600 	tempval |= MACCFG1_RX_EN;
3601 	gfar_write(&regs->maccfg1, tempval);
3602 }
3603 
3604 static int gfar_suspend(struct device *dev)
3605 {
3606 	struct gfar_private *priv = dev_get_drvdata(dev);
3607 	struct net_device *ndev = priv->ndev;
3608 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3609 	u32 tempval;
3610 	u16 wol = priv->wol_opts;
3611 
3612 	if (!netif_running(ndev))
3613 		return 0;
3614 
3615 	disable_napi(priv);
3616 	netif_tx_lock(ndev);
3617 	netif_device_detach(ndev);
3618 	netif_tx_unlock(ndev);
3619 
3620 	gfar_halt(priv);
3621 
3622 	if (wol & GFAR_WOL_MAGIC) {
3623 		/* Enable interrupt on Magic Packet */
3624 		gfar_write(&regs->imask, IMASK_MAG);
3625 
3626 		/* Enable Magic Packet mode */
3627 		tempval = gfar_read(&regs->maccfg2);
3628 		tempval |= MACCFG2_MPEN;
3629 		gfar_write(&regs->maccfg2, tempval);
3630 
3631 		/* re-enable the Rx block */
3632 		tempval = gfar_read(&regs->maccfg1);
3633 		tempval |= MACCFG1_RX_EN;
3634 		gfar_write(&regs->maccfg1, tempval);
3635 
3636 	} else if (wol & GFAR_WOL_FILER_UCAST) {
3637 		gfar_filer_config_wol(priv);
3638 		gfar_start_wol_filer(priv);
3639 
3640 	} else {
3641 		phy_stop(ndev->phydev);
3642 	}
3643 
3644 	return 0;
3645 }
3646 
3647 static int gfar_resume(struct device *dev)
3648 {
3649 	struct gfar_private *priv = dev_get_drvdata(dev);
3650 	struct net_device *ndev = priv->ndev;
3651 	struct gfar __iomem *regs = priv->gfargrp[0].regs;
3652 	u32 tempval;
3653 	u16 wol = priv->wol_opts;
3654 
3655 	if (!netif_running(ndev))
3656 		return 0;
3657 
3658 	if (wol & GFAR_WOL_MAGIC) {
3659 		/* Disable Magic Packet mode */
3660 		tempval = gfar_read(&regs->maccfg2);
3661 		tempval &= ~MACCFG2_MPEN;
3662 		gfar_write(&regs->maccfg2, tempval);
3663 
3664 	} else if (wol & GFAR_WOL_FILER_UCAST) {
3665 		/* need to stop rx only, tx is already down */
3666 		gfar_halt(priv);
3667 		gfar_filer_restore_table(priv);
3668 
3669 	} else {
3670 		phy_start(ndev->phydev);
3671 	}
3672 
3673 	gfar_start(priv);
3674 
3675 	netif_device_attach(ndev);
3676 	enable_napi(priv);
3677 
3678 	return 0;
3679 }
3680 
3681 static int gfar_restore(struct device *dev)
3682 {
3683 	struct gfar_private *priv = dev_get_drvdata(dev);
3684 	struct net_device *ndev = priv->ndev;
3685 
3686 	if (!netif_running(ndev)) {
3687 		netif_device_attach(ndev);
3688 
3689 		return 0;
3690 	}
3691 
3692 	gfar_init_bds(ndev);
3693 
3694 	gfar_mac_reset(priv);
3695 
3696 	gfar_init_tx_rx_base(priv);
3697 
3698 	gfar_start(priv);
3699 
3700 	priv->oldlink = 0;
3701 	priv->oldspeed = 0;
3702 	priv->oldduplex = -1;
3703 
3704 	if (ndev->phydev)
3705 		phy_start(ndev->phydev);
3706 
3707 	netif_device_attach(ndev);
3708 	enable_napi(priv);
3709 
3710 	return 0;
3711 }
3712 
3713 static const struct dev_pm_ops gfar_pm_ops = {
3714 	.suspend = gfar_suspend,
3715 	.resume = gfar_resume,
3716 	.freeze = gfar_suspend,
3717 	.thaw = gfar_resume,
3718 	.restore = gfar_restore,
3719 };
3720 
3721 #define GFAR_PM_OPS (&gfar_pm_ops)
3722 
3723 #else
3724 
3725 #define GFAR_PM_OPS NULL
3726 
3727 #endif
3728 
3729 static const struct of_device_id gfar_match[] =
3730 {
3731 	{
3732 		.type = "network",
3733 		.compatible = "gianfar",
3734 	},
3735 	{
3736 		.compatible = "fsl,etsec2",
3737 	},
3738 	{},
3739 };
3740 MODULE_DEVICE_TABLE(of, gfar_match);
3741 
3742 /* Structure for a device driver */
3743 static struct platform_driver gfar_driver = {
3744 	.driver = {
3745 		.name = "fsl-gianfar",
3746 		.pm = GFAR_PM_OPS,
3747 		.of_match_table = gfar_match,
3748 	},
3749 	.probe = gfar_probe,
3750 	.remove = gfar_remove,
3751 };
3752 
3753 module_platform_driver(gfar_driver);
3754