1 /* drivers/net/ethernet/freescale/gianfar.c 2 * 3 * Gianfar Ethernet Driver 4 * This driver is designed for the non-CPM ethernet controllers 5 * on the 85xx and 83xx family of integrated processors 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. 13 * Copyright 2007 MontaVista Software, Inc. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * Gianfar: AKA Lambda Draconis, "Dragon" 21 * RA 11 31 24.2 22 * Dec +69 19 52 23 * V 3.84 24 * B-V +1.62 25 * 26 * Theory of operation 27 * 28 * The driver is initialized through of_device. Configuration information 29 * is therefore conveyed through an OF-style device tree. 30 * 31 * The Gianfar Ethernet Controller uses a ring of buffer 32 * descriptors. The beginning is indicated by a register 33 * pointing to the physical address of the start of the ring. 34 * The end is determined by a "wrap" bit being set in the 35 * last descriptor of the ring. 36 * 37 * When a packet is received, the RXF bit in the 38 * IEVENT register is set, triggering an interrupt when the 39 * corresponding bit in the IMASK register is also set (if 40 * interrupt coalescing is active, then the interrupt may not 41 * happen immediately, but will wait until either a set number 42 * of frames or amount of time have passed). In NAPI, the 43 * interrupt handler will signal there is work to be done, and 44 * exit. This method will start at the last known empty 45 * descriptor, and process every subsequent descriptor until there 46 * are none left with data (NAPI will stop after a set number of 47 * packets to give time to other tasks, but will eventually 48 * process all the packets). The data arrives inside a 49 * pre-allocated skb, and so after the skb is passed up to the 50 * stack, a new skb must be allocated, and the address field in 51 * the buffer descriptor must be updated to indicate this new 52 * skb. 53 * 54 * When the kernel requests that a packet be transmitted, the 55 * driver starts where it left off last time, and points the 56 * descriptor at the buffer which was passed in. The driver 57 * then informs the DMA engine that there are packets ready to 58 * be transmitted. Once the controller is finished transmitting 59 * the packet, an interrupt may be triggered (under the same 60 * conditions as for reception, but depending on the TXF bit). 61 * The driver then cleans up the buffer. 62 */ 63 64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 65 #define DEBUG 66 67 #include <linux/kernel.h> 68 #include <linux/string.h> 69 #include <linux/errno.h> 70 #include <linux/unistd.h> 71 #include <linux/slab.h> 72 #include <linux/interrupt.h> 73 #include <linux/init.h> 74 #include <linux/delay.h> 75 #include <linux/netdevice.h> 76 #include <linux/etherdevice.h> 77 #include <linux/skbuff.h> 78 #include <linux/if_vlan.h> 79 #include <linux/spinlock.h> 80 #include <linux/mm.h> 81 #include <linux/of_mdio.h> 82 #include <linux/of_platform.h> 83 #include <linux/ip.h> 84 #include <linux/tcp.h> 85 #include <linux/udp.h> 86 #include <linux/in.h> 87 #include <linux/net_tstamp.h> 88 89 #include <asm/io.h> 90 #include <asm/reg.h> 91 #include <asm/irq.h> 92 #include <asm/uaccess.h> 93 #include <linux/module.h> 94 #include <linux/dma-mapping.h> 95 #include <linux/crc32.h> 96 #include <linux/mii.h> 97 #include <linux/phy.h> 98 #include <linux/phy_fixed.h> 99 #include <linux/of.h> 100 #include <linux/of_net.h> 101 102 #include "gianfar.h" 103 104 #define TX_TIMEOUT (1*HZ) 105 106 const char gfar_driver_version[] = "1.3"; 107 108 static int gfar_enet_open(struct net_device *dev); 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); 110 static void gfar_reset_task(struct work_struct *work); 111 static void gfar_timeout(struct net_device *dev); 112 static int gfar_close(struct net_device *dev); 113 struct sk_buff *gfar_new_skb(struct net_device *dev); 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 115 struct sk_buff *skb); 116 static int gfar_set_mac_address(struct net_device *dev); 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu); 118 static irqreturn_t gfar_error(int irq, void *dev_id); 119 static irqreturn_t gfar_transmit(int irq, void *dev_id); 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id); 121 static void adjust_link(struct net_device *dev); 122 static void init_registers(struct net_device *dev); 123 static int init_phy(struct net_device *dev); 124 static int gfar_probe(struct platform_device *ofdev); 125 static int gfar_remove(struct platform_device *ofdev); 126 static void free_skb_resources(struct gfar_private *priv); 127 static void gfar_set_multi(struct net_device *dev); 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); 129 static void gfar_configure_serdes(struct net_device *dev); 130 static int gfar_poll(struct napi_struct *napi, int budget); 131 #ifdef CONFIG_NET_POLL_CONTROLLER 132 static void gfar_netpoll(struct net_device *dev); 133 #endif 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); 135 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 136 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 137 int amount_pull, struct napi_struct *napi); 138 void gfar_halt(struct net_device *dev); 139 static void gfar_halt_nodisable(struct net_device *dev); 140 void gfar_start(struct net_device *dev); 141 static void gfar_clear_exact_match(struct net_device *dev); 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 143 const u8 *addr); 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 145 146 MODULE_AUTHOR("Freescale Semiconductor, Inc"); 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver"); 148 MODULE_LICENSE("GPL"); 149 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 151 dma_addr_t buf) 152 { 153 u32 lstatus; 154 155 bdp->bufPtr = buf; 156 157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); 158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) 159 lstatus |= BD_LFLAG(RXBD_WRAP); 160 161 eieio(); 162 163 bdp->lstatus = lstatus; 164 } 165 166 static int gfar_init_bds(struct net_device *ndev) 167 { 168 struct gfar_private *priv = netdev_priv(ndev); 169 struct gfar_priv_tx_q *tx_queue = NULL; 170 struct gfar_priv_rx_q *rx_queue = NULL; 171 struct txbd8 *txbdp; 172 struct rxbd8 *rxbdp; 173 int i, j; 174 175 for (i = 0; i < priv->num_tx_queues; i++) { 176 tx_queue = priv->tx_queue[i]; 177 /* Initialize some variables in our dev structure */ 178 tx_queue->num_txbdfree = tx_queue->tx_ring_size; 179 tx_queue->dirty_tx = tx_queue->tx_bd_base; 180 tx_queue->cur_tx = tx_queue->tx_bd_base; 181 tx_queue->skb_curtx = 0; 182 tx_queue->skb_dirtytx = 0; 183 184 /* Initialize Transmit Descriptor Ring */ 185 txbdp = tx_queue->tx_bd_base; 186 for (j = 0; j < tx_queue->tx_ring_size; j++) { 187 txbdp->lstatus = 0; 188 txbdp->bufPtr = 0; 189 txbdp++; 190 } 191 192 /* Set the last descriptor in the ring to indicate wrap */ 193 txbdp--; 194 txbdp->status |= TXBD_WRAP; 195 } 196 197 for (i = 0; i < priv->num_rx_queues; i++) { 198 rx_queue = priv->rx_queue[i]; 199 rx_queue->cur_rx = rx_queue->rx_bd_base; 200 rx_queue->skb_currx = 0; 201 rxbdp = rx_queue->rx_bd_base; 202 203 for (j = 0; j < rx_queue->rx_ring_size; j++) { 204 struct sk_buff *skb = rx_queue->rx_skbuff[j]; 205 206 if (skb) { 207 gfar_init_rxbdp(rx_queue, rxbdp, 208 rxbdp->bufPtr); 209 } else { 210 skb = gfar_new_skb(ndev); 211 if (!skb) { 212 netdev_err(ndev, "Can't allocate RX buffers\n"); 213 return -ENOMEM; 214 } 215 rx_queue->rx_skbuff[j] = skb; 216 217 gfar_new_rxbdp(rx_queue, rxbdp, skb); 218 } 219 220 rxbdp++; 221 } 222 223 } 224 225 return 0; 226 } 227 228 static int gfar_alloc_skb_resources(struct net_device *ndev) 229 { 230 void *vaddr; 231 dma_addr_t addr; 232 int i, j, k; 233 struct gfar_private *priv = netdev_priv(ndev); 234 struct device *dev = priv->dev; 235 struct gfar_priv_tx_q *tx_queue = NULL; 236 struct gfar_priv_rx_q *rx_queue = NULL; 237 238 priv->total_tx_ring_size = 0; 239 for (i = 0; i < priv->num_tx_queues; i++) 240 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; 241 242 priv->total_rx_ring_size = 0; 243 for (i = 0; i < priv->num_rx_queues; i++) 244 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; 245 246 /* Allocate memory for the buffer descriptors */ 247 vaddr = dma_alloc_coherent(dev, 248 (priv->total_tx_ring_size * 249 sizeof(struct txbd8)) + 250 (priv->total_rx_ring_size * 251 sizeof(struct rxbd8)), 252 &addr, GFP_KERNEL); 253 if (!vaddr) 254 return -ENOMEM; 255 256 for (i = 0; i < priv->num_tx_queues; i++) { 257 tx_queue = priv->tx_queue[i]; 258 tx_queue->tx_bd_base = vaddr; 259 tx_queue->tx_bd_dma_base = addr; 260 tx_queue->dev = ndev; 261 /* enet DMA only understands physical addresses */ 262 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 263 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; 264 } 265 266 /* Start the rx descriptor ring where the tx ring leaves off */ 267 for (i = 0; i < priv->num_rx_queues; i++) { 268 rx_queue = priv->rx_queue[i]; 269 rx_queue->rx_bd_base = vaddr; 270 rx_queue->rx_bd_dma_base = addr; 271 rx_queue->dev = ndev; 272 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 273 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; 274 } 275 276 /* Setup the skbuff rings */ 277 for (i = 0; i < priv->num_tx_queues; i++) { 278 tx_queue = priv->tx_queue[i]; 279 tx_queue->tx_skbuff = 280 kmalloc_array(tx_queue->tx_ring_size, 281 sizeof(*tx_queue->tx_skbuff), 282 GFP_KERNEL); 283 if (!tx_queue->tx_skbuff) 284 goto cleanup; 285 286 for (k = 0; k < tx_queue->tx_ring_size; k++) 287 tx_queue->tx_skbuff[k] = NULL; 288 } 289 290 for (i = 0; i < priv->num_rx_queues; i++) { 291 rx_queue = priv->rx_queue[i]; 292 rx_queue->rx_skbuff = 293 kmalloc_array(rx_queue->rx_ring_size, 294 sizeof(*rx_queue->rx_skbuff), 295 GFP_KERNEL); 296 if (!rx_queue->rx_skbuff) 297 goto cleanup; 298 299 for (j = 0; j < rx_queue->rx_ring_size; j++) 300 rx_queue->rx_skbuff[j] = NULL; 301 } 302 303 if (gfar_init_bds(ndev)) 304 goto cleanup; 305 306 return 0; 307 308 cleanup: 309 free_skb_resources(priv); 310 return -ENOMEM; 311 } 312 313 static void gfar_init_tx_rx_base(struct gfar_private *priv) 314 { 315 struct gfar __iomem *regs = priv->gfargrp[0].regs; 316 u32 __iomem *baddr; 317 int i; 318 319 baddr = ®s->tbase0; 320 for (i = 0; i < priv->num_tx_queues; i++) { 321 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); 322 baddr += 2; 323 } 324 325 baddr = ®s->rbase0; 326 for (i = 0; i < priv->num_rx_queues; i++) { 327 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); 328 baddr += 2; 329 } 330 } 331 332 static void gfar_init_mac(struct net_device *ndev) 333 { 334 struct gfar_private *priv = netdev_priv(ndev); 335 struct gfar __iomem *regs = priv->gfargrp[0].regs; 336 u32 rctrl = 0; 337 u32 tctrl = 0; 338 u32 attrs = 0; 339 340 /* write the tx/rx base registers */ 341 gfar_init_tx_rx_base(priv); 342 343 /* Configure the coalescing support */ 344 gfar_configure_coalescing_all(priv); 345 346 /* set this when rx hw offload (TOE) functions are being used */ 347 priv->uses_rxfcb = 0; 348 349 if (priv->rx_filer_enable) { 350 rctrl |= RCTRL_FILREN; 351 /* Program the RIR0 reg with the required distribution */ 352 gfar_write(®s->rir0, DEFAULT_RIR0); 353 } 354 355 /* Restore PROMISC mode */ 356 if (ndev->flags & IFF_PROMISC) 357 rctrl |= RCTRL_PROM; 358 359 if (ndev->features & NETIF_F_RXCSUM) { 360 rctrl |= RCTRL_CHECKSUMMING; 361 priv->uses_rxfcb = 1; 362 } 363 364 if (priv->extended_hash) { 365 rctrl |= RCTRL_EXTHASH; 366 367 gfar_clear_exact_match(ndev); 368 rctrl |= RCTRL_EMEN; 369 } 370 371 if (priv->padding) { 372 rctrl &= ~RCTRL_PAL_MASK; 373 rctrl |= RCTRL_PADDING(priv->padding); 374 } 375 376 /* Insert receive time stamps into padding alignment bytes */ 377 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { 378 rctrl &= ~RCTRL_PAL_MASK; 379 rctrl |= RCTRL_PADDING(8); 380 priv->padding = 8; 381 } 382 383 /* Enable HW time stamping if requested from user space */ 384 if (priv->hwts_rx_en) { 385 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 386 priv->uses_rxfcb = 1; 387 } 388 389 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { 390 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; 391 priv->uses_rxfcb = 1; 392 } 393 394 /* Init rctrl based on our settings */ 395 gfar_write(®s->rctrl, rctrl); 396 397 if (ndev->features & NETIF_F_IP_CSUM) 398 tctrl |= TCTRL_INIT_CSUM; 399 400 if (priv->prio_sched_en) 401 tctrl |= TCTRL_TXSCHED_PRIO; 402 else { 403 tctrl |= TCTRL_TXSCHED_WRRS; 404 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); 405 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); 406 } 407 408 gfar_write(®s->tctrl, tctrl); 409 410 /* Set the extraction length and index */ 411 attrs = ATTRELI_EL(priv->rx_stash_size) | 412 ATTRELI_EI(priv->rx_stash_index); 413 414 gfar_write(®s->attreli, attrs); 415 416 /* Start with defaults, and add stashing or locking 417 * depending on the approprate variables 418 */ 419 attrs = ATTR_INIT_SETTINGS; 420 421 if (priv->bd_stash_en) 422 attrs |= ATTR_BDSTASH; 423 424 if (priv->rx_stash_size != 0) 425 attrs |= ATTR_BUFSTASH; 426 427 gfar_write(®s->attr, attrs); 428 429 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); 430 gfar_write(®s->fifo_tx_starve, priv->fifo_starve); 431 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); 432 } 433 434 static struct net_device_stats *gfar_get_stats(struct net_device *dev) 435 { 436 struct gfar_private *priv = netdev_priv(dev); 437 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; 438 unsigned long tx_packets = 0, tx_bytes = 0; 439 int i; 440 441 for (i = 0; i < priv->num_rx_queues; i++) { 442 rx_packets += priv->rx_queue[i]->stats.rx_packets; 443 rx_bytes += priv->rx_queue[i]->stats.rx_bytes; 444 rx_dropped += priv->rx_queue[i]->stats.rx_dropped; 445 } 446 447 dev->stats.rx_packets = rx_packets; 448 dev->stats.rx_bytes = rx_bytes; 449 dev->stats.rx_dropped = rx_dropped; 450 451 for (i = 0; i < priv->num_tx_queues; i++) { 452 tx_bytes += priv->tx_queue[i]->stats.tx_bytes; 453 tx_packets += priv->tx_queue[i]->stats.tx_packets; 454 } 455 456 dev->stats.tx_bytes = tx_bytes; 457 dev->stats.tx_packets = tx_packets; 458 459 return &dev->stats; 460 } 461 462 static const struct net_device_ops gfar_netdev_ops = { 463 .ndo_open = gfar_enet_open, 464 .ndo_start_xmit = gfar_start_xmit, 465 .ndo_stop = gfar_close, 466 .ndo_change_mtu = gfar_change_mtu, 467 .ndo_set_features = gfar_set_features, 468 .ndo_set_rx_mode = gfar_set_multi, 469 .ndo_tx_timeout = gfar_timeout, 470 .ndo_do_ioctl = gfar_ioctl, 471 .ndo_get_stats = gfar_get_stats, 472 .ndo_set_mac_address = eth_mac_addr, 473 .ndo_validate_addr = eth_validate_addr, 474 #ifdef CONFIG_NET_POLL_CONTROLLER 475 .ndo_poll_controller = gfar_netpoll, 476 #endif 477 }; 478 479 void lock_rx_qs(struct gfar_private *priv) 480 { 481 int i; 482 483 for (i = 0; i < priv->num_rx_queues; i++) 484 spin_lock(&priv->rx_queue[i]->rxlock); 485 } 486 487 void lock_tx_qs(struct gfar_private *priv) 488 { 489 int i; 490 491 for (i = 0; i < priv->num_tx_queues; i++) 492 spin_lock(&priv->tx_queue[i]->txlock); 493 } 494 495 void unlock_rx_qs(struct gfar_private *priv) 496 { 497 int i; 498 499 for (i = 0; i < priv->num_rx_queues; i++) 500 spin_unlock(&priv->rx_queue[i]->rxlock); 501 } 502 503 void unlock_tx_qs(struct gfar_private *priv) 504 { 505 int i; 506 507 for (i = 0; i < priv->num_tx_queues; i++) 508 spin_unlock(&priv->tx_queue[i]->txlock); 509 } 510 511 static void free_tx_pointers(struct gfar_private *priv) 512 { 513 int i; 514 515 for (i = 0; i < priv->num_tx_queues; i++) 516 kfree(priv->tx_queue[i]); 517 } 518 519 static void free_rx_pointers(struct gfar_private *priv) 520 { 521 int i; 522 523 for (i = 0; i < priv->num_rx_queues; i++) 524 kfree(priv->rx_queue[i]); 525 } 526 527 static void unmap_group_regs(struct gfar_private *priv) 528 { 529 int i; 530 531 for (i = 0; i < MAXGROUPS; i++) 532 if (priv->gfargrp[i].regs) 533 iounmap(priv->gfargrp[i].regs); 534 } 535 536 static void free_gfar_dev(struct gfar_private *priv) 537 { 538 int i, j; 539 540 for (i = 0; i < priv->num_grps; i++) 541 for (j = 0; j < GFAR_NUM_IRQS; j++) { 542 kfree(priv->gfargrp[i].irqinfo[j]); 543 priv->gfargrp[i].irqinfo[j] = NULL; 544 } 545 546 free_netdev(priv->ndev); 547 } 548 549 static void disable_napi(struct gfar_private *priv) 550 { 551 int i; 552 553 for (i = 0; i < priv->num_grps; i++) 554 napi_disable(&priv->gfargrp[i].napi); 555 } 556 557 static void enable_napi(struct gfar_private *priv) 558 { 559 int i; 560 561 for (i = 0; i < priv->num_grps; i++) 562 napi_enable(&priv->gfargrp[i].napi); 563 } 564 565 static int gfar_parse_group(struct device_node *np, 566 struct gfar_private *priv, const char *model) 567 { 568 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; 569 u32 *queue_mask; 570 int i; 571 572 for (i = 0; i < GFAR_NUM_IRQS; i++) { 573 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), 574 GFP_KERNEL); 575 if (!grp->irqinfo[i]) 576 return -ENOMEM; 577 } 578 579 grp->regs = of_iomap(np, 0); 580 if (!grp->regs) 581 return -ENOMEM; 582 583 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); 584 585 /* If we aren't the FEC we have multiple interrupts */ 586 if (model && strcasecmp(model, "FEC")) { 587 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); 588 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); 589 if (gfar_irq(grp, TX)->irq == NO_IRQ || 590 gfar_irq(grp, RX)->irq == NO_IRQ || 591 gfar_irq(grp, ER)->irq == NO_IRQ) 592 return -EINVAL; 593 } 594 595 grp->grp_id = priv->num_grps; 596 grp->priv = priv; 597 spin_lock_init(&grp->grplock); 598 if (priv->mode == MQ_MG_MODE) { 599 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); 600 grp->rx_bit_map = queue_mask ? 601 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); 602 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); 603 grp->tx_bit_map = queue_mask ? 604 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); 605 } else { 606 grp->rx_bit_map = 0xFF; 607 grp->tx_bit_map = 0xFF; 608 } 609 priv->num_grps++; 610 611 return 0; 612 } 613 614 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) 615 { 616 const char *model; 617 const char *ctype; 618 const void *mac_addr; 619 int err = 0, i; 620 struct net_device *dev = NULL; 621 struct gfar_private *priv = NULL; 622 struct device_node *np = ofdev->dev.of_node; 623 struct device_node *child = NULL; 624 const u32 *stash; 625 const u32 *stash_len; 626 const u32 *stash_idx; 627 unsigned int num_tx_qs, num_rx_qs; 628 u32 *tx_queues, *rx_queues; 629 630 if (!np || !of_device_is_available(np)) 631 return -ENODEV; 632 633 /* parse the num of tx and rx queues */ 634 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); 635 num_tx_qs = tx_queues ? *tx_queues : 1; 636 637 if (num_tx_qs > MAX_TX_QS) { 638 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", 639 num_tx_qs, MAX_TX_QS); 640 pr_err("Cannot do alloc_etherdev, aborting\n"); 641 return -EINVAL; 642 } 643 644 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); 645 num_rx_qs = rx_queues ? *rx_queues : 1; 646 647 if (num_rx_qs > MAX_RX_QS) { 648 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", 649 num_rx_qs, MAX_RX_QS); 650 pr_err("Cannot do alloc_etherdev, aborting\n"); 651 return -EINVAL; 652 } 653 654 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); 655 dev = *pdev; 656 if (NULL == dev) 657 return -ENOMEM; 658 659 priv = netdev_priv(dev); 660 priv->ndev = dev; 661 662 priv->num_tx_queues = num_tx_qs; 663 netif_set_real_num_rx_queues(dev, num_rx_qs); 664 priv->num_rx_queues = num_rx_qs; 665 priv->num_grps = 0x0; 666 667 /* Init Rx queue filer rule set linked list */ 668 INIT_LIST_HEAD(&priv->rx_list.list); 669 priv->rx_list.count = 0; 670 mutex_init(&priv->rx_queue_access); 671 672 model = of_get_property(np, "model", NULL); 673 674 for (i = 0; i < MAXGROUPS; i++) 675 priv->gfargrp[i].regs = NULL; 676 677 /* Parse and initialize group specific information */ 678 if (of_device_is_compatible(np, "fsl,etsec2")) { 679 priv->mode = MQ_MG_MODE; 680 for_each_child_of_node(np, child) { 681 err = gfar_parse_group(child, priv, model); 682 if (err) 683 goto err_grp_init; 684 } 685 } else { 686 priv->mode = SQ_SG_MODE; 687 err = gfar_parse_group(np, priv, model); 688 if (err) 689 goto err_grp_init; 690 } 691 692 for (i = 0; i < priv->num_tx_queues; i++) 693 priv->tx_queue[i] = NULL; 694 for (i = 0; i < priv->num_rx_queues; i++) 695 priv->rx_queue[i] = NULL; 696 697 for (i = 0; i < priv->num_tx_queues; i++) { 698 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), 699 GFP_KERNEL); 700 if (!priv->tx_queue[i]) { 701 err = -ENOMEM; 702 goto tx_alloc_failed; 703 } 704 priv->tx_queue[i]->tx_skbuff = NULL; 705 priv->tx_queue[i]->qindex = i; 706 priv->tx_queue[i]->dev = dev; 707 spin_lock_init(&(priv->tx_queue[i]->txlock)); 708 } 709 710 for (i = 0; i < priv->num_rx_queues; i++) { 711 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), 712 GFP_KERNEL); 713 if (!priv->rx_queue[i]) { 714 err = -ENOMEM; 715 goto rx_alloc_failed; 716 } 717 priv->rx_queue[i]->rx_skbuff = NULL; 718 priv->rx_queue[i]->qindex = i; 719 priv->rx_queue[i]->dev = dev; 720 spin_lock_init(&(priv->rx_queue[i]->rxlock)); 721 } 722 723 724 stash = of_get_property(np, "bd-stash", NULL); 725 726 if (stash) { 727 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; 728 priv->bd_stash_en = 1; 729 } 730 731 stash_len = of_get_property(np, "rx-stash-len", NULL); 732 733 if (stash_len) 734 priv->rx_stash_size = *stash_len; 735 736 stash_idx = of_get_property(np, "rx-stash-idx", NULL); 737 738 if (stash_idx) 739 priv->rx_stash_index = *stash_idx; 740 741 if (stash_len || stash_idx) 742 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; 743 744 mac_addr = of_get_mac_address(np); 745 746 if (mac_addr) 747 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 748 749 if (model && !strcasecmp(model, "TSEC")) 750 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 751 FSL_GIANFAR_DEV_HAS_COALESCE | 752 FSL_GIANFAR_DEV_HAS_RMON | 753 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 754 755 if (model && !strcasecmp(model, "eTSEC")) 756 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 757 FSL_GIANFAR_DEV_HAS_COALESCE | 758 FSL_GIANFAR_DEV_HAS_RMON | 759 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 760 FSL_GIANFAR_DEV_HAS_PADDING | 761 FSL_GIANFAR_DEV_HAS_CSUM | 762 FSL_GIANFAR_DEV_HAS_VLAN | 763 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 764 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | 765 FSL_GIANFAR_DEV_HAS_TIMER; 766 767 ctype = of_get_property(np, "phy-connection-type", NULL); 768 769 /* We only care about rgmii-id. The rest are autodetected */ 770 if (ctype && !strcmp(ctype, "rgmii-id")) 771 priv->interface = PHY_INTERFACE_MODE_RGMII_ID; 772 else 773 priv->interface = PHY_INTERFACE_MODE_MII; 774 775 if (of_get_property(np, "fsl,magic-packet", NULL)) 776 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; 777 778 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 779 780 /* Find the TBI PHY. If it's not there, we don't support SGMII */ 781 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); 782 783 return 0; 784 785 rx_alloc_failed: 786 free_rx_pointers(priv); 787 tx_alloc_failed: 788 free_tx_pointers(priv); 789 err_grp_init: 790 unmap_group_regs(priv); 791 free_gfar_dev(priv); 792 return err; 793 } 794 795 static int gfar_hwtstamp_ioctl(struct net_device *netdev, 796 struct ifreq *ifr, int cmd) 797 { 798 struct hwtstamp_config config; 799 struct gfar_private *priv = netdev_priv(netdev); 800 801 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 802 return -EFAULT; 803 804 /* reserved for future extensions */ 805 if (config.flags) 806 return -EINVAL; 807 808 switch (config.tx_type) { 809 case HWTSTAMP_TX_OFF: 810 priv->hwts_tx_en = 0; 811 break; 812 case HWTSTAMP_TX_ON: 813 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 814 return -ERANGE; 815 priv->hwts_tx_en = 1; 816 break; 817 default: 818 return -ERANGE; 819 } 820 821 switch (config.rx_filter) { 822 case HWTSTAMP_FILTER_NONE: 823 if (priv->hwts_rx_en) { 824 stop_gfar(netdev); 825 priv->hwts_rx_en = 0; 826 startup_gfar(netdev); 827 } 828 break; 829 default: 830 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) 831 return -ERANGE; 832 if (!priv->hwts_rx_en) { 833 stop_gfar(netdev); 834 priv->hwts_rx_en = 1; 835 startup_gfar(netdev); 836 } 837 config.rx_filter = HWTSTAMP_FILTER_ALL; 838 break; 839 } 840 841 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 842 -EFAULT : 0; 843 } 844 845 /* Ioctl MII Interface */ 846 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 847 { 848 struct gfar_private *priv = netdev_priv(dev); 849 850 if (!netif_running(dev)) 851 return -EINVAL; 852 853 if (cmd == SIOCSHWTSTAMP) 854 return gfar_hwtstamp_ioctl(dev, rq, cmd); 855 856 if (!priv->phydev) 857 return -ENODEV; 858 859 return phy_mii_ioctl(priv->phydev, rq, cmd); 860 } 861 862 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) 863 { 864 unsigned int new_bit_map = 0x0; 865 int mask = 0x1 << (max_qs - 1), i; 866 867 for (i = 0; i < max_qs; i++) { 868 if (bit_map & mask) 869 new_bit_map = new_bit_map + (1 << i); 870 mask = mask >> 0x1; 871 } 872 return new_bit_map; 873 } 874 875 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 876 u32 class) 877 { 878 u32 rqfpr = FPR_FILER_MASK; 879 u32 rqfcr = 0x0; 880 881 rqfar--; 882 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; 883 priv->ftp_rqfpr[rqfar] = rqfpr; 884 priv->ftp_rqfcr[rqfar] = rqfcr; 885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 886 887 rqfar--; 888 rqfcr = RQFCR_CMP_NOMATCH; 889 priv->ftp_rqfpr[rqfar] = rqfpr; 890 priv->ftp_rqfcr[rqfar] = rqfcr; 891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 892 893 rqfar--; 894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; 895 rqfpr = class; 896 priv->ftp_rqfcr[rqfar] = rqfcr; 897 priv->ftp_rqfpr[rqfar] = rqfpr; 898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 899 900 rqfar--; 901 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; 902 rqfpr = class; 903 priv->ftp_rqfcr[rqfar] = rqfcr; 904 priv->ftp_rqfpr[rqfar] = rqfpr; 905 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 906 907 return rqfar; 908 } 909 910 static void gfar_init_filer_table(struct gfar_private *priv) 911 { 912 int i = 0x0; 913 u32 rqfar = MAX_FILER_IDX; 914 u32 rqfcr = 0x0; 915 u32 rqfpr = FPR_FILER_MASK; 916 917 /* Default rule */ 918 rqfcr = RQFCR_CMP_MATCH; 919 priv->ftp_rqfcr[rqfar] = rqfcr; 920 priv->ftp_rqfpr[rqfar] = rqfpr; 921 gfar_write_filer(priv, rqfar, rqfcr, rqfpr); 922 923 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); 924 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); 925 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); 926 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); 927 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); 928 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); 929 930 /* cur_filer_idx indicated the first non-masked rule */ 931 priv->cur_filer_idx = rqfar; 932 933 /* Rest are masked rules */ 934 rqfcr = RQFCR_CMP_NOMATCH; 935 for (i = 0; i < rqfar; i++) { 936 priv->ftp_rqfcr[i] = rqfcr; 937 priv->ftp_rqfpr[i] = rqfpr; 938 gfar_write_filer(priv, i, rqfcr, rqfpr); 939 } 940 } 941 942 static void gfar_detect_errata(struct gfar_private *priv) 943 { 944 struct device *dev = &priv->ofdev->dev; 945 unsigned int pvr = mfspr(SPRN_PVR); 946 unsigned int svr = mfspr(SPRN_SVR); 947 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ 948 unsigned int rev = svr & 0xffff; 949 950 /* MPC8313 Rev 2.0 and higher; All MPC837x */ 951 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || 952 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 953 priv->errata |= GFAR_ERRATA_74; 954 955 /* MPC8313 and MPC837x all rev */ 956 if ((pvr == 0x80850010 && mod == 0x80b0) || 957 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 958 priv->errata |= GFAR_ERRATA_76; 959 960 /* MPC8313 and MPC837x all rev */ 961 if ((pvr == 0x80850010 && mod == 0x80b0) || 962 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) 963 priv->errata |= GFAR_ERRATA_A002; 964 965 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ 966 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || 967 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) 968 priv->errata |= GFAR_ERRATA_12; 969 970 if (priv->errata) 971 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", 972 priv->errata); 973 } 974 975 /* Set up the ethernet device structure, private data, 976 * and anything else we need before we start 977 */ 978 static int gfar_probe(struct platform_device *ofdev) 979 { 980 u32 tempval; 981 struct net_device *dev = NULL; 982 struct gfar_private *priv = NULL; 983 struct gfar __iomem *regs = NULL; 984 int err = 0, i, grp_idx = 0; 985 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; 986 u32 isrg = 0; 987 u32 __iomem *baddr; 988 989 err = gfar_of_init(ofdev, &dev); 990 991 if (err) 992 return err; 993 994 priv = netdev_priv(dev); 995 priv->ndev = dev; 996 priv->ofdev = ofdev; 997 priv->dev = &ofdev->dev; 998 SET_NETDEV_DEV(dev, &ofdev->dev); 999 1000 spin_lock_init(&priv->bflock); 1001 INIT_WORK(&priv->reset_task, gfar_reset_task); 1002 1003 dev_set_drvdata(&ofdev->dev, priv); 1004 regs = priv->gfargrp[0].regs; 1005 1006 gfar_detect_errata(priv); 1007 1008 /* Stop the DMA engine now, in case it was running before 1009 * (The firmware could have used it, and left it running). 1010 */ 1011 gfar_halt(dev); 1012 1013 /* Reset MAC layer */ 1014 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); 1015 1016 /* We need to delay at least 3 TX clocks */ 1017 udelay(2); 1018 1019 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 1020 gfar_write(®s->maccfg1, tempval); 1021 1022 /* Initialize MACCFG2. */ 1023 tempval = MACCFG2_INIT_SETTINGS; 1024 if (gfar_has_errata(priv, GFAR_ERRATA_74)) 1025 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; 1026 gfar_write(®s->maccfg2, tempval); 1027 1028 /* Initialize ECNTRL */ 1029 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); 1030 1031 /* Set the dev->base_addr to the gfar reg region */ 1032 dev->base_addr = (unsigned long) regs; 1033 1034 /* Fill in the dev structure */ 1035 dev->watchdog_timeo = TX_TIMEOUT; 1036 dev->mtu = 1500; 1037 dev->netdev_ops = &gfar_netdev_ops; 1038 dev->ethtool_ops = &gfar_ethtool_ops; 1039 1040 /* Register for napi ...We are registering NAPI for each grp */ 1041 for (i = 0; i < priv->num_grps; i++) 1042 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, 1043 GFAR_DEV_WEIGHT); 1044 1045 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1046 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1047 NETIF_F_RXCSUM; 1048 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | 1049 NETIF_F_RXCSUM | NETIF_F_HIGHDMA; 1050 } 1051 1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1053 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1054 NETIF_F_HW_VLAN_CTAG_RX; 1055 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1056 } 1057 1058 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1059 priv->extended_hash = 1; 1060 priv->hash_width = 9; 1061 1062 priv->hash_regs[0] = ®s->igaddr0; 1063 priv->hash_regs[1] = ®s->igaddr1; 1064 priv->hash_regs[2] = ®s->igaddr2; 1065 priv->hash_regs[3] = ®s->igaddr3; 1066 priv->hash_regs[4] = ®s->igaddr4; 1067 priv->hash_regs[5] = ®s->igaddr5; 1068 priv->hash_regs[6] = ®s->igaddr6; 1069 priv->hash_regs[7] = ®s->igaddr7; 1070 priv->hash_regs[8] = ®s->gaddr0; 1071 priv->hash_regs[9] = ®s->gaddr1; 1072 priv->hash_regs[10] = ®s->gaddr2; 1073 priv->hash_regs[11] = ®s->gaddr3; 1074 priv->hash_regs[12] = ®s->gaddr4; 1075 priv->hash_regs[13] = ®s->gaddr5; 1076 priv->hash_regs[14] = ®s->gaddr6; 1077 priv->hash_regs[15] = ®s->gaddr7; 1078 1079 } else { 1080 priv->extended_hash = 0; 1081 priv->hash_width = 8; 1082 1083 priv->hash_regs[0] = ®s->gaddr0; 1084 priv->hash_regs[1] = ®s->gaddr1; 1085 priv->hash_regs[2] = ®s->gaddr2; 1086 priv->hash_regs[3] = ®s->gaddr3; 1087 priv->hash_regs[4] = ®s->gaddr4; 1088 priv->hash_regs[5] = ®s->gaddr5; 1089 priv->hash_regs[6] = ®s->gaddr6; 1090 priv->hash_regs[7] = ®s->gaddr7; 1091 } 1092 1093 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) 1094 priv->padding = DEFAULT_PADDING; 1095 else 1096 priv->padding = 0; 1097 1098 if (dev->features & NETIF_F_IP_CSUM || 1099 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) 1100 dev->needed_headroom = GMAC_FCB_LEN; 1101 1102 /* Program the isrg regs only if number of grps > 1 */ 1103 if (priv->num_grps > 1) { 1104 baddr = ®s->isrg0; 1105 for (i = 0; i < priv->num_grps; i++) { 1106 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); 1107 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); 1108 gfar_write(baddr, isrg); 1109 baddr++; 1110 isrg = 0x0; 1111 } 1112 } 1113 1114 /* Need to reverse the bit maps as bit_map's MSB is q0 1115 * but, for_each_set_bit parses from right to left, which 1116 * basically reverses the queue numbers 1117 */ 1118 for (i = 0; i< priv->num_grps; i++) { 1119 priv->gfargrp[i].tx_bit_map = 1120 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); 1121 priv->gfargrp[i].rx_bit_map = 1122 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); 1123 } 1124 1125 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 1126 * also assign queues to groups 1127 */ 1128 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1129 priv->gfargrp[grp_idx].num_rx_queues = 0x0; 1130 1131 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, 1132 priv->num_rx_queues) { 1133 priv->gfargrp[grp_idx].num_rx_queues++; 1134 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; 1135 rstat = rstat | (RSTAT_CLEAR_RHALT >> i); 1136 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); 1137 } 1138 priv->gfargrp[grp_idx].num_tx_queues = 0x0; 1139 1140 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, 1141 priv->num_tx_queues) { 1142 priv->gfargrp[grp_idx].num_tx_queues++; 1143 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; 1144 tstat = tstat | (TSTAT_CLEAR_THALT >> i); 1145 tqueue = tqueue | (TQUEUE_EN0 >> i); 1146 } 1147 priv->gfargrp[grp_idx].rstat = rstat; 1148 priv->gfargrp[grp_idx].tstat = tstat; 1149 rstat = tstat =0; 1150 } 1151 1152 gfar_write(®s->rqueue, rqueue); 1153 gfar_write(®s->tqueue, tqueue); 1154 1155 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 1156 1157 /* Initializing some of the rx/tx queue level parameters */ 1158 for (i = 0; i < priv->num_tx_queues; i++) { 1159 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; 1160 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; 1161 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; 1162 priv->tx_queue[i]->txic = DEFAULT_TXIC; 1163 } 1164 1165 for (i = 0; i < priv->num_rx_queues; i++) { 1166 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; 1167 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; 1168 priv->rx_queue[i]->rxic = DEFAULT_RXIC; 1169 } 1170 1171 /* always enable rx filer */ 1172 priv->rx_filer_enable = 1; 1173 /* Enable most messages by default */ 1174 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; 1175 /* use pritority h/w tx queue scheduling for single queue devices */ 1176 if (priv->num_tx_queues == 1) 1177 priv->prio_sched_en = 1; 1178 1179 /* Carrier starts down, phylib will bring it up */ 1180 netif_carrier_off(dev); 1181 1182 err = register_netdev(dev); 1183 1184 if (err) { 1185 pr_err("%s: Cannot register net device, aborting\n", dev->name); 1186 goto register_fail; 1187 } 1188 1189 device_init_wakeup(&dev->dev, 1190 priv->device_flags & 1191 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1192 1193 /* fill out IRQ number and name fields */ 1194 for (i = 0; i < priv->num_grps; i++) { 1195 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 1196 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1197 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", 1198 dev->name, "_g", '0' + i, "_tx"); 1199 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", 1200 dev->name, "_g", '0' + i, "_rx"); 1201 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", 1202 dev->name, "_g", '0' + i, "_er"); 1203 } else 1204 strcpy(gfar_irq(grp, TX)->name, dev->name); 1205 } 1206 1207 /* Initialize the filer table */ 1208 gfar_init_filer_table(priv); 1209 1210 /* Create all the sysfs files */ 1211 gfar_init_sysfs(dev); 1212 1213 /* Print out the device info */ 1214 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1215 1216 /* Even more device info helps when determining which kernel 1217 * provided which set of benchmarks. 1218 */ 1219 netdev_info(dev, "Running with NAPI enabled\n"); 1220 for (i = 0; i < priv->num_rx_queues; i++) 1221 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", 1222 i, priv->rx_queue[i]->rx_ring_size); 1223 for (i = 0; i < priv->num_tx_queues; i++) 1224 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", 1225 i, priv->tx_queue[i]->tx_ring_size); 1226 1227 return 0; 1228 1229 register_fail: 1230 unmap_group_regs(priv); 1231 free_tx_pointers(priv); 1232 free_rx_pointers(priv); 1233 if (priv->phy_node) 1234 of_node_put(priv->phy_node); 1235 if (priv->tbi_node) 1236 of_node_put(priv->tbi_node); 1237 free_gfar_dev(priv); 1238 return err; 1239 } 1240 1241 static int gfar_remove(struct platform_device *ofdev) 1242 { 1243 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); 1244 1245 if (priv->phy_node) 1246 of_node_put(priv->phy_node); 1247 if (priv->tbi_node) 1248 of_node_put(priv->tbi_node); 1249 1250 dev_set_drvdata(&ofdev->dev, NULL); 1251 1252 unregister_netdev(priv->ndev); 1253 unmap_group_regs(priv); 1254 free_gfar_dev(priv); 1255 1256 return 0; 1257 } 1258 1259 #ifdef CONFIG_PM 1260 1261 static int gfar_suspend(struct device *dev) 1262 { 1263 struct gfar_private *priv = dev_get_drvdata(dev); 1264 struct net_device *ndev = priv->ndev; 1265 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1266 unsigned long flags; 1267 u32 tempval; 1268 1269 int magic_packet = priv->wol_en && 1270 (priv->device_flags & 1271 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1272 1273 netif_device_detach(ndev); 1274 1275 if (netif_running(ndev)) { 1276 1277 local_irq_save(flags); 1278 lock_tx_qs(priv); 1279 lock_rx_qs(priv); 1280 1281 gfar_halt_nodisable(ndev); 1282 1283 /* Disable Tx, and Rx if wake-on-LAN is disabled. */ 1284 tempval = gfar_read(®s->maccfg1); 1285 1286 tempval &= ~MACCFG1_TX_EN; 1287 1288 if (!magic_packet) 1289 tempval &= ~MACCFG1_RX_EN; 1290 1291 gfar_write(®s->maccfg1, tempval); 1292 1293 unlock_rx_qs(priv); 1294 unlock_tx_qs(priv); 1295 local_irq_restore(flags); 1296 1297 disable_napi(priv); 1298 1299 if (magic_packet) { 1300 /* Enable interrupt on Magic Packet */ 1301 gfar_write(®s->imask, IMASK_MAG); 1302 1303 /* Enable Magic Packet mode */ 1304 tempval = gfar_read(®s->maccfg2); 1305 tempval |= MACCFG2_MPEN; 1306 gfar_write(®s->maccfg2, tempval); 1307 } else { 1308 phy_stop(priv->phydev); 1309 } 1310 } 1311 1312 return 0; 1313 } 1314 1315 static int gfar_resume(struct device *dev) 1316 { 1317 struct gfar_private *priv = dev_get_drvdata(dev); 1318 struct net_device *ndev = priv->ndev; 1319 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1320 unsigned long flags; 1321 u32 tempval; 1322 int magic_packet = priv->wol_en && 1323 (priv->device_flags & 1324 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); 1325 1326 if (!netif_running(ndev)) { 1327 netif_device_attach(ndev); 1328 return 0; 1329 } 1330 1331 if (!magic_packet && priv->phydev) 1332 phy_start(priv->phydev); 1333 1334 /* Disable Magic Packet mode, in case something 1335 * else woke us up. 1336 */ 1337 local_irq_save(flags); 1338 lock_tx_qs(priv); 1339 lock_rx_qs(priv); 1340 1341 tempval = gfar_read(®s->maccfg2); 1342 tempval &= ~MACCFG2_MPEN; 1343 gfar_write(®s->maccfg2, tempval); 1344 1345 gfar_start(ndev); 1346 1347 unlock_rx_qs(priv); 1348 unlock_tx_qs(priv); 1349 local_irq_restore(flags); 1350 1351 netif_device_attach(ndev); 1352 1353 enable_napi(priv); 1354 1355 return 0; 1356 } 1357 1358 static int gfar_restore(struct device *dev) 1359 { 1360 struct gfar_private *priv = dev_get_drvdata(dev); 1361 struct net_device *ndev = priv->ndev; 1362 1363 if (!netif_running(ndev)) { 1364 netif_device_attach(ndev); 1365 1366 return 0; 1367 } 1368 1369 if (gfar_init_bds(ndev)) { 1370 free_skb_resources(priv); 1371 return -ENOMEM; 1372 } 1373 1374 init_registers(ndev); 1375 gfar_set_mac_address(ndev); 1376 gfar_init_mac(ndev); 1377 gfar_start(ndev); 1378 1379 priv->oldlink = 0; 1380 priv->oldspeed = 0; 1381 priv->oldduplex = -1; 1382 1383 if (priv->phydev) 1384 phy_start(priv->phydev); 1385 1386 netif_device_attach(ndev); 1387 enable_napi(priv); 1388 1389 return 0; 1390 } 1391 1392 static struct dev_pm_ops gfar_pm_ops = { 1393 .suspend = gfar_suspend, 1394 .resume = gfar_resume, 1395 .freeze = gfar_suspend, 1396 .thaw = gfar_resume, 1397 .restore = gfar_restore, 1398 }; 1399 1400 #define GFAR_PM_OPS (&gfar_pm_ops) 1401 1402 #else 1403 1404 #define GFAR_PM_OPS NULL 1405 1406 #endif 1407 1408 /* Reads the controller's registers to determine what interface 1409 * connects it to the PHY. 1410 */ 1411 static phy_interface_t gfar_get_interface(struct net_device *dev) 1412 { 1413 struct gfar_private *priv = netdev_priv(dev); 1414 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1415 u32 ecntrl; 1416 1417 ecntrl = gfar_read(®s->ecntrl); 1418 1419 if (ecntrl & ECNTRL_SGMII_MODE) 1420 return PHY_INTERFACE_MODE_SGMII; 1421 1422 if (ecntrl & ECNTRL_TBI_MODE) { 1423 if (ecntrl & ECNTRL_REDUCED_MODE) 1424 return PHY_INTERFACE_MODE_RTBI; 1425 else 1426 return PHY_INTERFACE_MODE_TBI; 1427 } 1428 1429 if (ecntrl & ECNTRL_REDUCED_MODE) { 1430 if (ecntrl & ECNTRL_REDUCED_MII_MODE) { 1431 return PHY_INTERFACE_MODE_RMII; 1432 } 1433 else { 1434 phy_interface_t interface = priv->interface; 1435 1436 /* This isn't autodetected right now, so it must 1437 * be set by the device tree or platform code. 1438 */ 1439 if (interface == PHY_INTERFACE_MODE_RGMII_ID) 1440 return PHY_INTERFACE_MODE_RGMII_ID; 1441 1442 return PHY_INTERFACE_MODE_RGMII; 1443 } 1444 } 1445 1446 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) 1447 return PHY_INTERFACE_MODE_GMII; 1448 1449 return PHY_INTERFACE_MODE_MII; 1450 } 1451 1452 1453 /* Initializes driver's PHY state, and attaches to the PHY. 1454 * Returns 0 on success. 1455 */ 1456 static int init_phy(struct net_device *dev) 1457 { 1458 struct gfar_private *priv = netdev_priv(dev); 1459 uint gigabit_support = 1460 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? 1461 SUPPORTED_1000baseT_Full : 0; 1462 phy_interface_t interface; 1463 1464 priv->oldlink = 0; 1465 priv->oldspeed = 0; 1466 priv->oldduplex = -1; 1467 1468 interface = gfar_get_interface(dev); 1469 1470 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, 1471 interface); 1472 if (!priv->phydev) 1473 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, 1474 interface); 1475 if (!priv->phydev) { 1476 dev_err(&dev->dev, "could not attach to PHY\n"); 1477 return -ENODEV; 1478 } 1479 1480 if (interface == PHY_INTERFACE_MODE_SGMII) 1481 gfar_configure_serdes(dev); 1482 1483 /* Remove any features not supported by the controller */ 1484 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); 1485 priv->phydev->advertising = priv->phydev->supported; 1486 1487 return 0; 1488 } 1489 1490 /* Initialize TBI PHY interface for communicating with the 1491 * SERDES lynx PHY on the chip. We communicate with this PHY 1492 * through the MDIO bus on each controller, treating it as a 1493 * "normal" PHY at the address found in the TBIPA register. We assume 1494 * that the TBIPA register is valid. Either the MDIO bus code will set 1495 * it to a value that doesn't conflict with other PHYs on the bus, or the 1496 * value doesn't matter, as there are no other PHYs on the bus. 1497 */ 1498 static void gfar_configure_serdes(struct net_device *dev) 1499 { 1500 struct gfar_private *priv = netdev_priv(dev); 1501 struct phy_device *tbiphy; 1502 1503 if (!priv->tbi_node) { 1504 dev_warn(&dev->dev, "error: SGMII mode requires that the " 1505 "device tree specify a tbi-handle\n"); 1506 return; 1507 } 1508 1509 tbiphy = of_phy_find_device(priv->tbi_node); 1510 if (!tbiphy) { 1511 dev_err(&dev->dev, "error: Could not get TBI device\n"); 1512 return; 1513 } 1514 1515 /* If the link is already up, we must already be ok, and don't need to 1516 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured 1517 * everything for us? Resetting it takes the link down and requires 1518 * several seconds for it to come back. 1519 */ 1520 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) 1521 return; 1522 1523 /* Single clk mode, mii mode off(for serdes communication) */ 1524 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); 1525 1526 phy_write(tbiphy, MII_ADVERTISE, 1527 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | 1528 ADVERTISE_1000XPSE_ASYM); 1529 1530 phy_write(tbiphy, MII_BMCR, 1531 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | 1532 BMCR_SPEED1000); 1533 } 1534 1535 static void init_registers(struct net_device *dev) 1536 { 1537 struct gfar_private *priv = netdev_priv(dev); 1538 struct gfar __iomem *regs = NULL; 1539 int i; 1540 1541 for (i = 0; i < priv->num_grps; i++) { 1542 regs = priv->gfargrp[i].regs; 1543 /* Clear IEVENT */ 1544 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 1545 1546 /* Initialize IMASK */ 1547 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1548 } 1549 1550 regs = priv->gfargrp[0].regs; 1551 /* Init hash registers to zero */ 1552 gfar_write(®s->igaddr0, 0); 1553 gfar_write(®s->igaddr1, 0); 1554 gfar_write(®s->igaddr2, 0); 1555 gfar_write(®s->igaddr3, 0); 1556 gfar_write(®s->igaddr4, 0); 1557 gfar_write(®s->igaddr5, 0); 1558 gfar_write(®s->igaddr6, 0); 1559 gfar_write(®s->igaddr7, 0); 1560 1561 gfar_write(®s->gaddr0, 0); 1562 gfar_write(®s->gaddr1, 0); 1563 gfar_write(®s->gaddr2, 0); 1564 gfar_write(®s->gaddr3, 0); 1565 gfar_write(®s->gaddr4, 0); 1566 gfar_write(®s->gaddr5, 0); 1567 gfar_write(®s->gaddr6, 0); 1568 gfar_write(®s->gaddr7, 0); 1569 1570 /* Zero out the rmon mib registers if it has them */ 1571 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { 1572 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); 1573 1574 /* Mask off the CAM interrupts */ 1575 gfar_write(®s->rmon.cam1, 0xffffffff); 1576 gfar_write(®s->rmon.cam2, 0xffffffff); 1577 } 1578 1579 /* Initialize the max receive buffer length */ 1580 gfar_write(®s->mrblr, priv->rx_buffer_size); 1581 1582 /* Initialize the Minimum Frame Length Register */ 1583 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); 1584 } 1585 1586 static int __gfar_is_rx_idle(struct gfar_private *priv) 1587 { 1588 u32 res; 1589 1590 /* Normaly TSEC should not hang on GRS commands, so we should 1591 * actually wait for IEVENT_GRSC flag. 1592 */ 1593 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) 1594 return 0; 1595 1596 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are 1597 * the same as bits 23-30, the eTSEC Rx is assumed to be idle 1598 * and the Rx can be safely reset. 1599 */ 1600 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); 1601 res &= 0x7f807f80; 1602 if ((res & 0xffff) == (res >> 16)) 1603 return 1; 1604 1605 return 0; 1606 } 1607 1608 /* Halt the receive and transmit queues */ 1609 static void gfar_halt_nodisable(struct net_device *dev) 1610 { 1611 struct gfar_private *priv = netdev_priv(dev); 1612 struct gfar __iomem *regs = NULL; 1613 u32 tempval; 1614 int i; 1615 1616 for (i = 0; i < priv->num_grps; i++) { 1617 regs = priv->gfargrp[i].regs; 1618 /* Mask all interrupts */ 1619 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1620 1621 /* Clear all interrupts */ 1622 gfar_write(®s->ievent, IEVENT_INIT_CLEAR); 1623 } 1624 1625 regs = priv->gfargrp[0].regs; 1626 /* Stop the DMA, and wait for it to stop */ 1627 tempval = gfar_read(®s->dmactrl); 1628 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != 1629 (DMACTRL_GRS | DMACTRL_GTS)) { 1630 int ret; 1631 1632 tempval |= (DMACTRL_GRS | DMACTRL_GTS); 1633 gfar_write(®s->dmactrl, tempval); 1634 1635 do { 1636 ret = spin_event_timeout(((gfar_read(®s->ievent) & 1637 (IEVENT_GRSC | IEVENT_GTSC)) == 1638 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); 1639 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) 1640 ret = __gfar_is_rx_idle(priv); 1641 } while (!ret); 1642 } 1643 } 1644 1645 /* Halt the receive and transmit queues */ 1646 void gfar_halt(struct net_device *dev) 1647 { 1648 struct gfar_private *priv = netdev_priv(dev); 1649 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1650 u32 tempval; 1651 1652 gfar_halt_nodisable(dev); 1653 1654 /* Disable Rx and Tx */ 1655 tempval = gfar_read(®s->maccfg1); 1656 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1657 gfar_write(®s->maccfg1, tempval); 1658 } 1659 1660 static void free_grp_irqs(struct gfar_priv_grp *grp) 1661 { 1662 free_irq(gfar_irq(grp, TX)->irq, grp); 1663 free_irq(gfar_irq(grp, RX)->irq, grp); 1664 free_irq(gfar_irq(grp, ER)->irq, grp); 1665 } 1666 1667 void stop_gfar(struct net_device *dev) 1668 { 1669 struct gfar_private *priv = netdev_priv(dev); 1670 unsigned long flags; 1671 int i; 1672 1673 phy_stop(priv->phydev); 1674 1675 1676 /* Lock it down */ 1677 local_irq_save(flags); 1678 lock_tx_qs(priv); 1679 lock_rx_qs(priv); 1680 1681 gfar_halt(dev); 1682 1683 unlock_rx_qs(priv); 1684 unlock_tx_qs(priv); 1685 local_irq_restore(flags); 1686 1687 /* Free the IRQs */ 1688 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1689 for (i = 0; i < priv->num_grps; i++) 1690 free_grp_irqs(&priv->gfargrp[i]); 1691 } else { 1692 for (i = 0; i < priv->num_grps; i++) 1693 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, 1694 &priv->gfargrp[i]); 1695 } 1696 1697 free_skb_resources(priv); 1698 } 1699 1700 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) 1701 { 1702 struct txbd8 *txbdp; 1703 struct gfar_private *priv = netdev_priv(tx_queue->dev); 1704 int i, j; 1705 1706 txbdp = tx_queue->tx_bd_base; 1707 1708 for (i = 0; i < tx_queue->tx_ring_size; i++) { 1709 if (!tx_queue->tx_skbuff[i]) 1710 continue; 1711 1712 dma_unmap_single(priv->dev, txbdp->bufPtr, 1713 txbdp->length, DMA_TO_DEVICE); 1714 txbdp->lstatus = 0; 1715 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; 1716 j++) { 1717 txbdp++; 1718 dma_unmap_page(priv->dev, txbdp->bufPtr, 1719 txbdp->length, DMA_TO_DEVICE); 1720 } 1721 txbdp++; 1722 dev_kfree_skb_any(tx_queue->tx_skbuff[i]); 1723 tx_queue->tx_skbuff[i] = NULL; 1724 } 1725 kfree(tx_queue->tx_skbuff); 1726 tx_queue->tx_skbuff = NULL; 1727 } 1728 1729 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) 1730 { 1731 struct rxbd8 *rxbdp; 1732 struct gfar_private *priv = netdev_priv(rx_queue->dev); 1733 int i; 1734 1735 rxbdp = rx_queue->rx_bd_base; 1736 1737 for (i = 0; i < rx_queue->rx_ring_size; i++) { 1738 if (rx_queue->rx_skbuff[i]) { 1739 dma_unmap_single(priv->dev, rxbdp->bufPtr, 1740 priv->rx_buffer_size, 1741 DMA_FROM_DEVICE); 1742 dev_kfree_skb_any(rx_queue->rx_skbuff[i]); 1743 rx_queue->rx_skbuff[i] = NULL; 1744 } 1745 rxbdp->lstatus = 0; 1746 rxbdp->bufPtr = 0; 1747 rxbdp++; 1748 } 1749 kfree(rx_queue->rx_skbuff); 1750 rx_queue->rx_skbuff = NULL; 1751 } 1752 1753 /* If there are any tx skbs or rx skbs still around, free them. 1754 * Then free tx_skbuff and rx_skbuff 1755 */ 1756 static void free_skb_resources(struct gfar_private *priv) 1757 { 1758 struct gfar_priv_tx_q *tx_queue = NULL; 1759 struct gfar_priv_rx_q *rx_queue = NULL; 1760 int i; 1761 1762 /* Go through all the buffer descriptors and free their data buffers */ 1763 for (i = 0; i < priv->num_tx_queues; i++) { 1764 struct netdev_queue *txq; 1765 1766 tx_queue = priv->tx_queue[i]; 1767 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); 1768 if (tx_queue->tx_skbuff) 1769 free_skb_tx_queue(tx_queue); 1770 netdev_tx_reset_queue(txq); 1771 } 1772 1773 for (i = 0; i < priv->num_rx_queues; i++) { 1774 rx_queue = priv->rx_queue[i]; 1775 if (rx_queue->rx_skbuff) 1776 free_skb_rx_queue(rx_queue); 1777 } 1778 1779 dma_free_coherent(priv->dev, 1780 sizeof(struct txbd8) * priv->total_tx_ring_size + 1781 sizeof(struct rxbd8) * priv->total_rx_ring_size, 1782 priv->tx_queue[0]->tx_bd_base, 1783 priv->tx_queue[0]->tx_bd_dma_base); 1784 } 1785 1786 void gfar_start(struct net_device *dev) 1787 { 1788 struct gfar_private *priv = netdev_priv(dev); 1789 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1790 u32 tempval; 1791 int i = 0; 1792 1793 /* Enable Rx and Tx in MACCFG1 */ 1794 tempval = gfar_read(®s->maccfg1); 1795 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1796 gfar_write(®s->maccfg1, tempval); 1797 1798 /* Initialize DMACTRL to have WWR and WOP */ 1799 tempval = gfar_read(®s->dmactrl); 1800 tempval |= DMACTRL_INIT_SETTINGS; 1801 gfar_write(®s->dmactrl, tempval); 1802 1803 /* Make sure we aren't stopped */ 1804 tempval = gfar_read(®s->dmactrl); 1805 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); 1806 gfar_write(®s->dmactrl, tempval); 1807 1808 for (i = 0; i < priv->num_grps; i++) { 1809 regs = priv->gfargrp[i].regs; 1810 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1811 gfar_write(®s->tstat, priv->gfargrp[i].tstat); 1812 gfar_write(®s->rstat, priv->gfargrp[i].rstat); 1813 /* Unmask the interrupts we look for */ 1814 gfar_write(®s->imask, IMASK_DEFAULT); 1815 } 1816 1817 dev->trans_start = jiffies; /* prevent tx timeout */ 1818 } 1819 1820 static void gfar_configure_coalescing(struct gfar_private *priv, 1821 unsigned long tx_mask, unsigned long rx_mask) 1822 { 1823 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1824 u32 __iomem *baddr; 1825 1826 if (priv->mode == MQ_MG_MODE) { 1827 int i = 0; 1828 1829 baddr = ®s->txic0; 1830 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { 1831 gfar_write(baddr + i, 0); 1832 if (likely(priv->tx_queue[i]->txcoalescing)) 1833 gfar_write(baddr + i, priv->tx_queue[i]->txic); 1834 } 1835 1836 baddr = ®s->rxic0; 1837 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { 1838 gfar_write(baddr + i, 0); 1839 if (likely(priv->rx_queue[i]->rxcoalescing)) 1840 gfar_write(baddr + i, priv->rx_queue[i]->rxic); 1841 } 1842 } else { 1843 /* Backward compatible case -- even if we enable 1844 * multiple queues, there's only single reg to program 1845 */ 1846 gfar_write(®s->txic, 0); 1847 if (likely(priv->tx_queue[0]->txcoalescing)) 1848 gfar_write(®s->txic, priv->tx_queue[0]->txic); 1849 1850 gfar_write(®s->rxic, 0); 1851 if (unlikely(priv->rx_queue[0]->rxcoalescing)) 1852 gfar_write(®s->rxic, priv->rx_queue[0]->rxic); 1853 } 1854 } 1855 1856 void gfar_configure_coalescing_all(struct gfar_private *priv) 1857 { 1858 gfar_configure_coalescing(priv, 0xFF, 0xFF); 1859 } 1860 1861 static int register_grp_irqs(struct gfar_priv_grp *grp) 1862 { 1863 struct gfar_private *priv = grp->priv; 1864 struct net_device *dev = priv->ndev; 1865 int err; 1866 1867 /* If the device has multiple interrupts, register for 1868 * them. Otherwise, only register for the one 1869 */ 1870 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 1871 /* Install our interrupt handlers for Error, 1872 * Transmit, and Receive 1873 */ 1874 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, 1875 gfar_irq(grp, ER)->name, grp); 1876 if (err < 0) { 1877 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1878 gfar_irq(grp, ER)->irq); 1879 1880 goto err_irq_fail; 1881 } 1882 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, 1883 gfar_irq(grp, TX)->name, grp); 1884 if (err < 0) { 1885 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1886 gfar_irq(grp, TX)->irq); 1887 goto tx_irq_fail; 1888 } 1889 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, 1890 gfar_irq(grp, RX)->name, grp); 1891 if (err < 0) { 1892 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1893 gfar_irq(grp, RX)->irq); 1894 goto rx_irq_fail; 1895 } 1896 } else { 1897 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, 1898 gfar_irq(grp, TX)->name, grp); 1899 if (err < 0) { 1900 netif_err(priv, intr, dev, "Can't get IRQ %d\n", 1901 gfar_irq(grp, TX)->irq); 1902 goto err_irq_fail; 1903 } 1904 } 1905 1906 return 0; 1907 1908 rx_irq_fail: 1909 free_irq(gfar_irq(grp, TX)->irq, grp); 1910 tx_irq_fail: 1911 free_irq(gfar_irq(grp, ER)->irq, grp); 1912 err_irq_fail: 1913 return err; 1914 1915 } 1916 1917 /* Bring the controller up and running */ 1918 int startup_gfar(struct net_device *ndev) 1919 { 1920 struct gfar_private *priv = netdev_priv(ndev); 1921 struct gfar __iomem *regs = NULL; 1922 int err, i, j; 1923 1924 for (i = 0; i < priv->num_grps; i++) { 1925 regs= priv->gfargrp[i].regs; 1926 gfar_write(®s->imask, IMASK_INIT_CLEAR); 1927 } 1928 1929 regs= priv->gfargrp[0].regs; 1930 err = gfar_alloc_skb_resources(ndev); 1931 if (err) 1932 return err; 1933 1934 gfar_init_mac(ndev); 1935 1936 for (i = 0; i < priv->num_grps; i++) { 1937 err = register_grp_irqs(&priv->gfargrp[i]); 1938 if (err) { 1939 for (j = 0; j < i; j++) 1940 free_grp_irqs(&priv->gfargrp[j]); 1941 goto irq_fail; 1942 } 1943 } 1944 1945 /* Start the controller */ 1946 gfar_start(ndev); 1947 1948 phy_start(priv->phydev); 1949 1950 gfar_configure_coalescing_all(priv); 1951 1952 return 0; 1953 1954 irq_fail: 1955 free_skb_resources(priv); 1956 return err; 1957 } 1958 1959 /* Called when something needs to use the ethernet device 1960 * Returns 0 for success. 1961 */ 1962 static int gfar_enet_open(struct net_device *dev) 1963 { 1964 struct gfar_private *priv = netdev_priv(dev); 1965 int err; 1966 1967 enable_napi(priv); 1968 1969 /* Initialize a bunch of registers */ 1970 init_registers(dev); 1971 1972 gfar_set_mac_address(dev); 1973 1974 err = init_phy(dev); 1975 1976 if (err) { 1977 disable_napi(priv); 1978 return err; 1979 } 1980 1981 err = startup_gfar(dev); 1982 if (err) { 1983 disable_napi(priv); 1984 return err; 1985 } 1986 1987 netif_tx_start_all_queues(dev); 1988 1989 device_set_wakeup_enable(&dev->dev, priv->wol_en); 1990 1991 return err; 1992 } 1993 1994 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) 1995 { 1996 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); 1997 1998 memset(fcb, 0, GMAC_FCB_LEN); 1999 2000 return fcb; 2001 } 2002 2003 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, 2004 int fcb_length) 2005 { 2006 /* If we're here, it's a IP packet with a TCP or UDP 2007 * payload. We set it to checksum, using a pseudo-header 2008 * we provide 2009 */ 2010 u8 flags = TXFCB_DEFAULT; 2011 2012 /* Tell the controller what the protocol is 2013 * And provide the already calculated phcs 2014 */ 2015 if (ip_hdr(skb)->protocol == IPPROTO_UDP) { 2016 flags |= TXFCB_UDP; 2017 fcb->phcs = udp_hdr(skb)->check; 2018 } else 2019 fcb->phcs = tcp_hdr(skb)->check; 2020 2021 /* l3os is the distance between the start of the 2022 * frame (skb->data) and the start of the IP hdr. 2023 * l4os is the distance between the start of the 2024 * l3 hdr and the l4 hdr 2025 */ 2026 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); 2027 fcb->l4os = skb_network_header_len(skb); 2028 2029 fcb->flags = flags; 2030 } 2031 2032 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) 2033 { 2034 fcb->flags |= TXFCB_VLN; 2035 fcb->vlctl = vlan_tx_tag_get(skb); 2036 } 2037 2038 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, 2039 struct txbd8 *base, int ring_size) 2040 { 2041 struct txbd8 *new_bd = bdp + stride; 2042 2043 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; 2044 } 2045 2046 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, 2047 int ring_size) 2048 { 2049 return skip_txbd(bdp, 1, base, ring_size); 2050 } 2051 2052 /* This is called by the kernel when a frame is ready for transmission. 2053 * It is pointed to by the dev->hard_start_xmit function pointer 2054 */ 2055 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) 2056 { 2057 struct gfar_private *priv = netdev_priv(dev); 2058 struct gfar_priv_tx_q *tx_queue = NULL; 2059 struct netdev_queue *txq; 2060 struct gfar __iomem *regs = NULL; 2061 struct txfcb *fcb = NULL; 2062 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; 2063 u32 lstatus; 2064 int i, rq = 0, do_tstamp = 0; 2065 u32 bufaddr; 2066 unsigned long flags; 2067 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN; 2068 2069 /* TOE=1 frames larger than 2500 bytes may see excess delays 2070 * before start of transmission. 2071 */ 2072 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && 2073 skb->ip_summed == CHECKSUM_PARTIAL && 2074 skb->len > 2500)) { 2075 int ret; 2076 2077 ret = skb_checksum_help(skb); 2078 if (ret) 2079 return ret; 2080 } 2081 2082 rq = skb->queue_mapping; 2083 tx_queue = priv->tx_queue[rq]; 2084 txq = netdev_get_tx_queue(dev, rq); 2085 base = tx_queue->tx_bd_base; 2086 regs = tx_queue->grp->regs; 2087 2088 /* check if time stamp should be generated */ 2089 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 2090 priv->hwts_tx_en)) { 2091 do_tstamp = 1; 2092 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2093 } 2094 2095 /* make space for additional header when fcb is needed */ 2096 if (((skb->ip_summed == CHECKSUM_PARTIAL) || 2097 vlan_tx_tag_present(skb) || 2098 unlikely(do_tstamp)) && 2099 (skb_headroom(skb) < fcb_length)) { 2100 struct sk_buff *skb_new; 2101 2102 skb_new = skb_realloc_headroom(skb, fcb_length); 2103 if (!skb_new) { 2104 dev->stats.tx_errors++; 2105 kfree_skb(skb); 2106 return NETDEV_TX_OK; 2107 } 2108 2109 if (skb->sk) 2110 skb_set_owner_w(skb_new, skb->sk); 2111 consume_skb(skb); 2112 skb = skb_new; 2113 } 2114 2115 /* total number of fragments in the SKB */ 2116 nr_frags = skb_shinfo(skb)->nr_frags; 2117 2118 /* calculate the required number of TxBDs for this skb */ 2119 if (unlikely(do_tstamp)) 2120 nr_txbds = nr_frags + 2; 2121 else 2122 nr_txbds = nr_frags + 1; 2123 2124 /* check if there is space to queue this packet */ 2125 if (nr_txbds > tx_queue->num_txbdfree) { 2126 /* no space, stop the queue */ 2127 netif_tx_stop_queue(txq); 2128 dev->stats.tx_fifo_errors++; 2129 return NETDEV_TX_BUSY; 2130 } 2131 2132 /* Update transmit stats */ 2133 tx_queue->stats.tx_bytes += skb->len; 2134 tx_queue->stats.tx_packets++; 2135 2136 txbdp = txbdp_start = tx_queue->cur_tx; 2137 lstatus = txbdp->lstatus; 2138 2139 /* Time stamp insertion requires one additional TxBD */ 2140 if (unlikely(do_tstamp)) 2141 txbdp_tstamp = txbdp = next_txbd(txbdp, base, 2142 tx_queue->tx_ring_size); 2143 2144 if (nr_frags == 0) { 2145 if (unlikely(do_tstamp)) 2146 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | 2147 TXBD_INTERRUPT); 2148 else 2149 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2150 } else { 2151 /* Place the fragment addresses and lengths into the TxBDs */ 2152 for (i = 0; i < nr_frags; i++) { 2153 /* Point at the next BD, wrapping as needed */ 2154 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2155 2156 length = skb_shinfo(skb)->frags[i].size; 2157 2158 lstatus = txbdp->lstatus | length | 2159 BD_LFLAG(TXBD_READY); 2160 2161 /* Handle the last BD specially */ 2162 if (i == nr_frags - 1) 2163 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); 2164 2165 bufaddr = skb_frag_dma_map(priv->dev, 2166 &skb_shinfo(skb)->frags[i], 2167 0, 2168 length, 2169 DMA_TO_DEVICE); 2170 2171 /* set the TxBD length and buffer pointer */ 2172 txbdp->bufPtr = bufaddr; 2173 txbdp->lstatus = lstatus; 2174 } 2175 2176 lstatus = txbdp_start->lstatus; 2177 } 2178 2179 /* Add TxPAL between FCB and frame if required */ 2180 if (unlikely(do_tstamp)) { 2181 skb_push(skb, GMAC_TXPAL_LEN); 2182 memset(skb->data, 0, GMAC_TXPAL_LEN); 2183 } 2184 2185 /* Set up checksumming */ 2186 if (CHECKSUM_PARTIAL == skb->ip_summed) { 2187 fcb = gfar_add_fcb(skb); 2188 /* as specified by errata */ 2189 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) && 2190 ((unsigned long)fcb % 0x20) > 0x18)) { 2191 __skb_pull(skb, GMAC_FCB_LEN); 2192 skb_checksum_help(skb); 2193 } else { 2194 lstatus |= BD_LFLAG(TXBD_TOE); 2195 gfar_tx_checksum(skb, fcb, fcb_length); 2196 } 2197 } 2198 2199 if (vlan_tx_tag_present(skb)) { 2200 if (unlikely(NULL == fcb)) { 2201 fcb = gfar_add_fcb(skb); 2202 lstatus |= BD_LFLAG(TXBD_TOE); 2203 } 2204 2205 gfar_tx_vlan(skb, fcb); 2206 } 2207 2208 /* Setup tx hardware time stamping if requested */ 2209 if (unlikely(do_tstamp)) { 2210 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2211 if (fcb == NULL) 2212 fcb = gfar_add_fcb(skb); 2213 fcb->ptp = 1; 2214 lstatus |= BD_LFLAG(TXBD_TOE); 2215 } 2216 2217 txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, 2218 skb_headlen(skb), DMA_TO_DEVICE); 2219 2220 /* If time stamping is requested one additional TxBD must be set up. The 2221 * first TxBD points to the FCB and must have a data length of 2222 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with 2223 * the full frame length. 2224 */ 2225 if (unlikely(do_tstamp)) { 2226 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length; 2227 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | 2228 (skb_headlen(skb) - fcb_length); 2229 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; 2230 } else { 2231 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); 2232 } 2233 2234 netdev_tx_sent_queue(txq, skb->len); 2235 2236 /* We can work in parallel with gfar_clean_tx_ring(), except 2237 * when modifying num_txbdfree. Note that we didn't grab the lock 2238 * when we were reading the num_txbdfree and checking for available 2239 * space, that's because outside of this function it can only grow, 2240 * and once we've got needed space, it cannot suddenly disappear. 2241 * 2242 * The lock also protects us from gfar_error(), which can modify 2243 * regs->tstat and thus retrigger the transfers, which is why we 2244 * also must grab the lock before setting ready bit for the first 2245 * to be transmitted BD. 2246 */ 2247 spin_lock_irqsave(&tx_queue->txlock, flags); 2248 2249 /* The powerpc-specific eieio() is used, as wmb() has too strong 2250 * semantics (it requires synchronization between cacheable and 2251 * uncacheable mappings, which eieio doesn't provide and which we 2252 * don't need), thus requiring a more expensive sync instruction. At 2253 * some point, the set of architecture-independent barrier functions 2254 * should be expanded to include weaker barriers. 2255 */ 2256 eieio(); 2257 2258 txbdp_start->lstatus = lstatus; 2259 2260 eieio(); /* force lstatus write before tx_skbuff */ 2261 2262 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; 2263 2264 /* Update the current skb pointer to the next entry we will use 2265 * (wrapping if necessary) 2266 */ 2267 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & 2268 TX_RING_MOD_MASK(tx_queue->tx_ring_size); 2269 2270 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); 2271 2272 /* reduce TxBD free count */ 2273 tx_queue->num_txbdfree -= (nr_txbds); 2274 2275 /* If the next BD still needs to be cleaned up, then the bds 2276 * are full. We need to tell the kernel to stop sending us stuff. 2277 */ 2278 if (!tx_queue->num_txbdfree) { 2279 netif_tx_stop_queue(txq); 2280 2281 dev->stats.tx_fifo_errors++; 2282 } 2283 2284 /* Tell the DMA to go go go */ 2285 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); 2286 2287 /* Unlock priv */ 2288 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2289 2290 return NETDEV_TX_OK; 2291 } 2292 2293 /* Stops the kernel queue, and halts the controller */ 2294 static int gfar_close(struct net_device *dev) 2295 { 2296 struct gfar_private *priv = netdev_priv(dev); 2297 2298 disable_napi(priv); 2299 2300 cancel_work_sync(&priv->reset_task); 2301 stop_gfar(dev); 2302 2303 /* Disconnect from the PHY */ 2304 phy_disconnect(priv->phydev); 2305 priv->phydev = NULL; 2306 2307 netif_tx_stop_all_queues(dev); 2308 2309 return 0; 2310 } 2311 2312 /* Changes the mac address if the controller is not running. */ 2313 static int gfar_set_mac_address(struct net_device *dev) 2314 { 2315 gfar_set_mac_for_addr(dev, 0, dev->dev_addr); 2316 2317 return 0; 2318 } 2319 2320 /* Check if rx parser should be activated */ 2321 void gfar_check_rx_parser_mode(struct gfar_private *priv) 2322 { 2323 struct gfar __iomem *regs; 2324 u32 tempval; 2325 2326 regs = priv->gfargrp[0].regs; 2327 2328 tempval = gfar_read(®s->rctrl); 2329 /* If parse is no longer required, then disable parser */ 2330 if (tempval & RCTRL_REQ_PARSER) { 2331 tempval |= RCTRL_PRSDEP_INIT; 2332 priv->uses_rxfcb = 1; 2333 } else { 2334 tempval &= ~RCTRL_PRSDEP_INIT; 2335 priv->uses_rxfcb = 0; 2336 } 2337 gfar_write(®s->rctrl, tempval); 2338 } 2339 2340 /* Enables and disables VLAN insertion/extraction */ 2341 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) 2342 { 2343 struct gfar_private *priv = netdev_priv(dev); 2344 struct gfar __iomem *regs = NULL; 2345 unsigned long flags; 2346 u32 tempval; 2347 2348 regs = priv->gfargrp[0].regs; 2349 local_irq_save(flags); 2350 lock_rx_qs(priv); 2351 2352 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 2353 /* Enable VLAN tag insertion */ 2354 tempval = gfar_read(®s->tctrl); 2355 tempval |= TCTRL_VLINS; 2356 gfar_write(®s->tctrl, tempval); 2357 } else { 2358 /* Disable VLAN tag insertion */ 2359 tempval = gfar_read(®s->tctrl); 2360 tempval &= ~TCTRL_VLINS; 2361 gfar_write(®s->tctrl, tempval); 2362 } 2363 2364 if (features & NETIF_F_HW_VLAN_CTAG_RX) { 2365 /* Enable VLAN tag extraction */ 2366 tempval = gfar_read(®s->rctrl); 2367 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); 2368 gfar_write(®s->rctrl, tempval); 2369 priv->uses_rxfcb = 1; 2370 } else { 2371 /* Disable VLAN tag extraction */ 2372 tempval = gfar_read(®s->rctrl); 2373 tempval &= ~RCTRL_VLEX; 2374 gfar_write(®s->rctrl, tempval); 2375 2376 gfar_check_rx_parser_mode(priv); 2377 } 2378 2379 gfar_change_mtu(dev, dev->mtu); 2380 2381 unlock_rx_qs(priv); 2382 local_irq_restore(flags); 2383 } 2384 2385 static int gfar_change_mtu(struct net_device *dev, int new_mtu) 2386 { 2387 int tempsize, tempval; 2388 struct gfar_private *priv = netdev_priv(dev); 2389 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2390 int oldsize = priv->rx_buffer_size; 2391 int frame_size = new_mtu + ETH_HLEN; 2392 2393 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { 2394 netif_err(priv, drv, dev, "Invalid MTU setting\n"); 2395 return -EINVAL; 2396 } 2397 2398 if (priv->uses_rxfcb) 2399 frame_size += GMAC_FCB_LEN; 2400 2401 frame_size += priv->padding; 2402 2403 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + 2404 INCREMENTAL_BUFFER_SIZE; 2405 2406 /* Only stop and start the controller if it isn't already 2407 * stopped, and we changed something 2408 */ 2409 if ((oldsize != tempsize) && (dev->flags & IFF_UP)) 2410 stop_gfar(dev); 2411 2412 priv->rx_buffer_size = tempsize; 2413 2414 dev->mtu = new_mtu; 2415 2416 gfar_write(®s->mrblr, priv->rx_buffer_size); 2417 gfar_write(®s->maxfrm, priv->rx_buffer_size); 2418 2419 /* If the mtu is larger than the max size for standard 2420 * ethernet frames (ie, a jumbo frame), then set maccfg2 2421 * to allow huge frames, and to check the length 2422 */ 2423 tempval = gfar_read(®s->maccfg2); 2424 2425 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || 2426 gfar_has_errata(priv, GFAR_ERRATA_74)) 2427 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); 2428 else 2429 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); 2430 2431 gfar_write(®s->maccfg2, tempval); 2432 2433 if ((oldsize != tempsize) && (dev->flags & IFF_UP)) 2434 startup_gfar(dev); 2435 2436 return 0; 2437 } 2438 2439 /* gfar_reset_task gets scheduled when a packet has not been 2440 * transmitted after a set amount of time. 2441 * For now, assume that clearing out all the structures, and 2442 * starting over will fix the problem. 2443 */ 2444 static void gfar_reset_task(struct work_struct *work) 2445 { 2446 struct gfar_private *priv = container_of(work, struct gfar_private, 2447 reset_task); 2448 struct net_device *dev = priv->ndev; 2449 2450 if (dev->flags & IFF_UP) { 2451 netif_tx_stop_all_queues(dev); 2452 stop_gfar(dev); 2453 startup_gfar(dev); 2454 netif_tx_start_all_queues(dev); 2455 } 2456 2457 netif_tx_schedule_all(dev); 2458 } 2459 2460 static void gfar_timeout(struct net_device *dev) 2461 { 2462 struct gfar_private *priv = netdev_priv(dev); 2463 2464 dev->stats.tx_errors++; 2465 schedule_work(&priv->reset_task); 2466 } 2467 2468 static void gfar_align_skb(struct sk_buff *skb) 2469 { 2470 /* We need the data buffer to be aligned properly. We will reserve 2471 * as many bytes as needed to align the data properly 2472 */ 2473 skb_reserve(skb, RXBUF_ALIGNMENT - 2474 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); 2475 } 2476 2477 /* Interrupt Handler for Transmit complete */ 2478 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) 2479 { 2480 struct net_device *dev = tx_queue->dev; 2481 struct netdev_queue *txq; 2482 struct gfar_private *priv = netdev_priv(dev); 2483 struct txbd8 *bdp, *next = NULL; 2484 struct txbd8 *lbdp = NULL; 2485 struct txbd8 *base = tx_queue->tx_bd_base; 2486 struct sk_buff *skb; 2487 int skb_dirtytx; 2488 int tx_ring_size = tx_queue->tx_ring_size; 2489 int frags = 0, nr_txbds = 0; 2490 int i; 2491 int howmany = 0; 2492 int tqi = tx_queue->qindex; 2493 unsigned int bytes_sent = 0; 2494 u32 lstatus; 2495 size_t buflen; 2496 2497 txq = netdev_get_tx_queue(dev, tqi); 2498 bdp = tx_queue->dirty_tx; 2499 skb_dirtytx = tx_queue->skb_dirtytx; 2500 2501 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { 2502 unsigned long flags; 2503 2504 frags = skb_shinfo(skb)->nr_frags; 2505 2506 /* When time stamping, one additional TxBD must be freed. 2507 * Also, we need to dma_unmap_single() the TxPAL. 2508 */ 2509 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) 2510 nr_txbds = frags + 2; 2511 else 2512 nr_txbds = frags + 1; 2513 2514 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); 2515 2516 lstatus = lbdp->lstatus; 2517 2518 /* Only clean completed frames */ 2519 if ((lstatus & BD_LFLAG(TXBD_READY)) && 2520 (lstatus & BD_LENGTH_MASK)) 2521 break; 2522 2523 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2524 next = next_txbd(bdp, base, tx_ring_size); 2525 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; 2526 } else 2527 buflen = bdp->length; 2528 2529 dma_unmap_single(priv->dev, bdp->bufPtr, 2530 buflen, DMA_TO_DEVICE); 2531 2532 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { 2533 struct skb_shared_hwtstamps shhwtstamps; 2534 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); 2535 2536 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 2537 shhwtstamps.hwtstamp = ns_to_ktime(*ns); 2538 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); 2539 skb_tstamp_tx(skb, &shhwtstamps); 2540 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2541 bdp = next; 2542 } 2543 2544 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2545 bdp = next_txbd(bdp, base, tx_ring_size); 2546 2547 for (i = 0; i < frags; i++) { 2548 dma_unmap_page(priv->dev, bdp->bufPtr, 2549 bdp->length, DMA_TO_DEVICE); 2550 bdp->lstatus &= BD_LFLAG(TXBD_WRAP); 2551 bdp = next_txbd(bdp, base, tx_ring_size); 2552 } 2553 2554 bytes_sent += skb->len; 2555 2556 dev_kfree_skb_any(skb); 2557 2558 tx_queue->tx_skbuff[skb_dirtytx] = NULL; 2559 2560 skb_dirtytx = (skb_dirtytx + 1) & 2561 TX_RING_MOD_MASK(tx_ring_size); 2562 2563 howmany++; 2564 spin_lock_irqsave(&tx_queue->txlock, flags); 2565 tx_queue->num_txbdfree += nr_txbds; 2566 spin_unlock_irqrestore(&tx_queue->txlock, flags); 2567 } 2568 2569 /* If we freed a buffer, we can restart transmission, if necessary */ 2570 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) 2571 netif_wake_subqueue(dev, tqi); 2572 2573 /* Update dirty indicators */ 2574 tx_queue->skb_dirtytx = skb_dirtytx; 2575 tx_queue->dirty_tx = bdp; 2576 2577 netdev_tx_completed_queue(txq, howmany, bytes_sent); 2578 } 2579 2580 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) 2581 { 2582 unsigned long flags; 2583 2584 spin_lock_irqsave(&gfargrp->grplock, flags); 2585 if (napi_schedule_prep(&gfargrp->napi)) { 2586 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); 2587 __napi_schedule(&gfargrp->napi); 2588 } else { 2589 /* Clear IEVENT, so interrupts aren't called again 2590 * because of the packets that have already arrived. 2591 */ 2592 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); 2593 } 2594 spin_unlock_irqrestore(&gfargrp->grplock, flags); 2595 2596 } 2597 2598 /* Interrupt Handler for Transmit complete */ 2599 static irqreturn_t gfar_transmit(int irq, void *grp_id) 2600 { 2601 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); 2602 return IRQ_HANDLED; 2603 } 2604 2605 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, 2606 struct sk_buff *skb) 2607 { 2608 struct net_device *dev = rx_queue->dev; 2609 struct gfar_private *priv = netdev_priv(dev); 2610 dma_addr_t buf; 2611 2612 buf = dma_map_single(priv->dev, skb->data, 2613 priv->rx_buffer_size, DMA_FROM_DEVICE); 2614 gfar_init_rxbdp(rx_queue, bdp, buf); 2615 } 2616 2617 static struct sk_buff *gfar_alloc_skb(struct net_device *dev) 2618 { 2619 struct gfar_private *priv = netdev_priv(dev); 2620 struct sk_buff *skb; 2621 2622 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); 2623 if (!skb) 2624 return NULL; 2625 2626 gfar_align_skb(skb); 2627 2628 return skb; 2629 } 2630 2631 struct sk_buff *gfar_new_skb(struct net_device *dev) 2632 { 2633 return gfar_alloc_skb(dev); 2634 } 2635 2636 static inline void count_errors(unsigned short status, struct net_device *dev) 2637 { 2638 struct gfar_private *priv = netdev_priv(dev); 2639 struct net_device_stats *stats = &dev->stats; 2640 struct gfar_extra_stats *estats = &priv->extra_stats; 2641 2642 /* If the packet was truncated, none of the other errors matter */ 2643 if (status & RXBD_TRUNCATED) { 2644 stats->rx_length_errors++; 2645 2646 atomic64_inc(&estats->rx_trunc); 2647 2648 return; 2649 } 2650 /* Count the errors, if there were any */ 2651 if (status & (RXBD_LARGE | RXBD_SHORT)) { 2652 stats->rx_length_errors++; 2653 2654 if (status & RXBD_LARGE) 2655 atomic64_inc(&estats->rx_large); 2656 else 2657 atomic64_inc(&estats->rx_short); 2658 } 2659 if (status & RXBD_NONOCTET) { 2660 stats->rx_frame_errors++; 2661 atomic64_inc(&estats->rx_nonoctet); 2662 } 2663 if (status & RXBD_CRCERR) { 2664 atomic64_inc(&estats->rx_crcerr); 2665 stats->rx_crc_errors++; 2666 } 2667 if (status & RXBD_OVERRUN) { 2668 atomic64_inc(&estats->rx_overrun); 2669 stats->rx_crc_errors++; 2670 } 2671 } 2672 2673 irqreturn_t gfar_receive(int irq, void *grp_id) 2674 { 2675 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); 2676 return IRQ_HANDLED; 2677 } 2678 2679 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) 2680 { 2681 /* If valid headers were found, and valid sums 2682 * were verified, then we tell the kernel that no 2683 * checksumming is necessary. Otherwise, it is [FIXME] 2684 */ 2685 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) 2686 skb->ip_summed = CHECKSUM_UNNECESSARY; 2687 else 2688 skb_checksum_none_assert(skb); 2689 } 2690 2691 2692 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ 2693 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 2694 int amount_pull, struct napi_struct *napi) 2695 { 2696 struct gfar_private *priv = netdev_priv(dev); 2697 struct rxfcb *fcb = NULL; 2698 2699 /* fcb is at the beginning if exists */ 2700 fcb = (struct rxfcb *)skb->data; 2701 2702 /* Remove the FCB from the skb 2703 * Remove the padded bytes, if there are any 2704 */ 2705 if (amount_pull) { 2706 skb_record_rx_queue(skb, fcb->rq); 2707 skb_pull(skb, amount_pull); 2708 } 2709 2710 /* Get receive timestamp from the skb */ 2711 if (priv->hwts_rx_en) { 2712 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); 2713 u64 *ns = (u64 *) skb->data; 2714 2715 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 2716 shhwtstamps->hwtstamp = ns_to_ktime(*ns); 2717 } 2718 2719 if (priv->padding) 2720 skb_pull(skb, priv->padding); 2721 2722 if (dev->features & NETIF_F_RXCSUM) 2723 gfar_rx_checksum(skb, fcb); 2724 2725 /* Tell the skb what kind of packet this is */ 2726 skb->protocol = eth_type_trans(skb, dev); 2727 2728 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. 2729 * Even if vlan rx accel is disabled, on some chips 2730 * RXFCB_VLN is pseudo randomly set. 2731 */ 2732 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && 2733 fcb->flags & RXFCB_VLN) 2734 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); 2735 2736 /* Send the packet up the stack */ 2737 napi_gro_receive(napi, skb); 2738 2739 } 2740 2741 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring 2742 * until the budget/quota has been reached. Returns the number 2743 * of frames handled 2744 */ 2745 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) 2746 { 2747 struct net_device *dev = rx_queue->dev; 2748 struct rxbd8 *bdp, *base; 2749 struct sk_buff *skb; 2750 int pkt_len; 2751 int amount_pull; 2752 int howmany = 0; 2753 struct gfar_private *priv = netdev_priv(dev); 2754 2755 /* Get the first full descriptor */ 2756 bdp = rx_queue->cur_rx; 2757 base = rx_queue->rx_bd_base; 2758 2759 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; 2760 2761 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { 2762 struct sk_buff *newskb; 2763 2764 rmb(); 2765 2766 /* Add another skb for the future */ 2767 newskb = gfar_new_skb(dev); 2768 2769 skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; 2770 2771 dma_unmap_single(priv->dev, bdp->bufPtr, 2772 priv->rx_buffer_size, DMA_FROM_DEVICE); 2773 2774 if (unlikely(!(bdp->status & RXBD_ERR) && 2775 bdp->length > priv->rx_buffer_size)) 2776 bdp->status = RXBD_LARGE; 2777 2778 /* We drop the frame if we failed to allocate a new buffer */ 2779 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || 2780 bdp->status & RXBD_ERR)) { 2781 count_errors(bdp->status, dev); 2782 2783 if (unlikely(!newskb)) 2784 newskb = skb; 2785 else if (skb) 2786 dev_kfree_skb(skb); 2787 } else { 2788 /* Increment the number of packets */ 2789 rx_queue->stats.rx_packets++; 2790 howmany++; 2791 2792 if (likely(skb)) { 2793 pkt_len = bdp->length - ETH_FCS_LEN; 2794 /* Remove the FCS from the packet length */ 2795 skb_put(skb, pkt_len); 2796 rx_queue->stats.rx_bytes += pkt_len; 2797 skb_record_rx_queue(skb, rx_queue->qindex); 2798 gfar_process_frame(dev, skb, amount_pull, 2799 &rx_queue->grp->napi); 2800 2801 } else { 2802 netif_warn(priv, rx_err, dev, "Missing skb!\n"); 2803 rx_queue->stats.rx_dropped++; 2804 atomic64_inc(&priv->extra_stats.rx_skbmissing); 2805 } 2806 2807 } 2808 2809 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; 2810 2811 /* Setup the new bdp */ 2812 gfar_new_rxbdp(rx_queue, bdp, newskb); 2813 2814 /* Update to the next pointer */ 2815 bdp = next_bd(bdp, base, rx_queue->rx_ring_size); 2816 2817 /* update to point at the next skb */ 2818 rx_queue->skb_currx = (rx_queue->skb_currx + 1) & 2819 RX_RING_MOD_MASK(rx_queue->rx_ring_size); 2820 } 2821 2822 /* Update the current rxbd pointer to be the next one */ 2823 rx_queue->cur_rx = bdp; 2824 2825 return howmany; 2826 } 2827 2828 static int gfar_poll(struct napi_struct *napi, int budget) 2829 { 2830 struct gfar_priv_grp *gfargrp = 2831 container_of(napi, struct gfar_priv_grp, napi); 2832 struct gfar_private *priv = gfargrp->priv; 2833 struct gfar __iomem *regs = gfargrp->regs; 2834 struct gfar_priv_tx_q *tx_queue = NULL; 2835 struct gfar_priv_rx_q *rx_queue = NULL; 2836 int work_done = 0, work_done_per_q = 0; 2837 int i, budget_per_q = 0; 2838 int has_tx_work; 2839 unsigned long rstat_rxf; 2840 int num_act_queues; 2841 2842 /* Clear IEVENT, so interrupts aren't called again 2843 * because of the packets that have already arrived 2844 */ 2845 gfar_write(®s->ievent, IEVENT_RTX_MASK); 2846 2847 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; 2848 2849 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); 2850 if (num_act_queues) 2851 budget_per_q = budget/num_act_queues; 2852 2853 while (1) { 2854 has_tx_work = 0; 2855 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { 2856 tx_queue = priv->tx_queue[i]; 2857 /* run Tx cleanup to completion */ 2858 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { 2859 gfar_clean_tx_ring(tx_queue); 2860 has_tx_work = 1; 2861 } 2862 } 2863 2864 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { 2865 /* skip queue if not active */ 2866 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) 2867 continue; 2868 2869 rx_queue = priv->rx_queue[i]; 2870 work_done_per_q = 2871 gfar_clean_rx_ring(rx_queue, budget_per_q); 2872 work_done += work_done_per_q; 2873 2874 /* finished processing this queue */ 2875 if (work_done_per_q < budget_per_q) { 2876 /* clear active queue hw indication */ 2877 gfar_write(®s->rstat, 2878 RSTAT_CLEAR_RXF0 >> i); 2879 rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i); 2880 num_act_queues--; 2881 2882 if (!num_act_queues) 2883 break; 2884 /* recompute budget per Rx queue */ 2885 budget_per_q = 2886 (budget - work_done) / num_act_queues; 2887 } 2888 } 2889 2890 if (work_done >= budget) 2891 break; 2892 2893 if (!num_act_queues && !has_tx_work) { 2894 2895 napi_complete(napi); 2896 2897 /* Clear the halt bit in RSTAT */ 2898 gfar_write(®s->rstat, gfargrp->rstat); 2899 2900 gfar_write(®s->imask, IMASK_DEFAULT); 2901 2902 /* If we are coalescing interrupts, update the timer 2903 * Otherwise, clear it 2904 */ 2905 gfar_configure_coalescing(priv, gfargrp->rx_bit_map, 2906 gfargrp->tx_bit_map); 2907 break; 2908 } 2909 } 2910 2911 return work_done; 2912 } 2913 2914 #ifdef CONFIG_NET_POLL_CONTROLLER 2915 /* Polling 'interrupt' - used by things like netconsole to send skbs 2916 * without having to re-enable interrupts. It's not called while 2917 * the interrupt routine is executing. 2918 */ 2919 static void gfar_netpoll(struct net_device *dev) 2920 { 2921 struct gfar_private *priv = netdev_priv(dev); 2922 int i; 2923 2924 /* If the device has multiple interrupts, run tx/rx */ 2925 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { 2926 for (i = 0; i < priv->num_grps; i++) { 2927 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2928 2929 disable_irq(gfar_irq(grp, TX)->irq); 2930 disable_irq(gfar_irq(grp, RX)->irq); 2931 disable_irq(gfar_irq(grp, ER)->irq); 2932 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2933 enable_irq(gfar_irq(grp, ER)->irq); 2934 enable_irq(gfar_irq(grp, RX)->irq); 2935 enable_irq(gfar_irq(grp, TX)->irq); 2936 } 2937 } else { 2938 for (i = 0; i < priv->num_grps; i++) { 2939 struct gfar_priv_grp *grp = &priv->gfargrp[i]; 2940 2941 disable_irq(gfar_irq(grp, TX)->irq); 2942 gfar_interrupt(gfar_irq(grp, TX)->irq, grp); 2943 enable_irq(gfar_irq(grp, TX)->irq); 2944 } 2945 } 2946 } 2947 #endif 2948 2949 /* The interrupt handler for devices with one interrupt */ 2950 static irqreturn_t gfar_interrupt(int irq, void *grp_id) 2951 { 2952 struct gfar_priv_grp *gfargrp = grp_id; 2953 2954 /* Save ievent for future reference */ 2955 u32 events = gfar_read(&gfargrp->regs->ievent); 2956 2957 /* Check for reception */ 2958 if (events & IEVENT_RX_MASK) 2959 gfar_receive(irq, grp_id); 2960 2961 /* Check for transmit completion */ 2962 if (events & IEVENT_TX_MASK) 2963 gfar_transmit(irq, grp_id); 2964 2965 /* Check for errors */ 2966 if (events & IEVENT_ERR_MASK) 2967 gfar_error(irq, grp_id); 2968 2969 return IRQ_HANDLED; 2970 } 2971 2972 /* Called every time the controller might need to be made 2973 * aware of new link state. The PHY code conveys this 2974 * information through variables in the phydev structure, and this 2975 * function converts those variables into the appropriate 2976 * register values, and can bring down the device if needed. 2977 */ 2978 static void adjust_link(struct net_device *dev) 2979 { 2980 struct gfar_private *priv = netdev_priv(dev); 2981 struct gfar __iomem *regs = priv->gfargrp[0].regs; 2982 unsigned long flags; 2983 struct phy_device *phydev = priv->phydev; 2984 int new_state = 0; 2985 2986 local_irq_save(flags); 2987 lock_tx_qs(priv); 2988 2989 if (phydev->link) { 2990 u32 tempval = gfar_read(®s->maccfg2); 2991 u32 ecntrl = gfar_read(®s->ecntrl); 2992 2993 /* Now we make sure that we can be in full duplex mode. 2994 * If not, we operate in half-duplex mode. 2995 */ 2996 if (phydev->duplex != priv->oldduplex) { 2997 new_state = 1; 2998 if (!(phydev->duplex)) 2999 tempval &= ~(MACCFG2_FULL_DUPLEX); 3000 else 3001 tempval |= MACCFG2_FULL_DUPLEX; 3002 3003 priv->oldduplex = phydev->duplex; 3004 } 3005 3006 if (phydev->speed != priv->oldspeed) { 3007 new_state = 1; 3008 switch (phydev->speed) { 3009 case 1000: 3010 tempval = 3011 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); 3012 3013 ecntrl &= ~(ECNTRL_R100); 3014 break; 3015 case 100: 3016 case 10: 3017 tempval = 3018 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); 3019 3020 /* Reduced mode distinguishes 3021 * between 10 and 100 3022 */ 3023 if (phydev->speed == SPEED_100) 3024 ecntrl |= ECNTRL_R100; 3025 else 3026 ecntrl &= ~(ECNTRL_R100); 3027 break; 3028 default: 3029 netif_warn(priv, link, dev, 3030 "Ack! Speed (%d) is not 10/100/1000!\n", 3031 phydev->speed); 3032 break; 3033 } 3034 3035 priv->oldspeed = phydev->speed; 3036 } 3037 3038 gfar_write(®s->maccfg2, tempval); 3039 gfar_write(®s->ecntrl, ecntrl); 3040 3041 if (!priv->oldlink) { 3042 new_state = 1; 3043 priv->oldlink = 1; 3044 } 3045 } else if (priv->oldlink) { 3046 new_state = 1; 3047 priv->oldlink = 0; 3048 priv->oldspeed = 0; 3049 priv->oldduplex = -1; 3050 } 3051 3052 if (new_state && netif_msg_link(priv)) 3053 phy_print_status(phydev); 3054 unlock_tx_qs(priv); 3055 local_irq_restore(flags); 3056 } 3057 3058 /* Update the hash table based on the current list of multicast 3059 * addresses we subscribe to. Also, change the promiscuity of 3060 * the device based on the flags (this function is called 3061 * whenever dev->flags is changed 3062 */ 3063 static void gfar_set_multi(struct net_device *dev) 3064 { 3065 struct netdev_hw_addr *ha; 3066 struct gfar_private *priv = netdev_priv(dev); 3067 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3068 u32 tempval; 3069 3070 if (dev->flags & IFF_PROMISC) { 3071 /* Set RCTRL to PROM */ 3072 tempval = gfar_read(®s->rctrl); 3073 tempval |= RCTRL_PROM; 3074 gfar_write(®s->rctrl, tempval); 3075 } else { 3076 /* Set RCTRL to not PROM */ 3077 tempval = gfar_read(®s->rctrl); 3078 tempval &= ~(RCTRL_PROM); 3079 gfar_write(®s->rctrl, tempval); 3080 } 3081 3082 if (dev->flags & IFF_ALLMULTI) { 3083 /* Set the hash to rx all multicast frames */ 3084 gfar_write(®s->igaddr0, 0xffffffff); 3085 gfar_write(®s->igaddr1, 0xffffffff); 3086 gfar_write(®s->igaddr2, 0xffffffff); 3087 gfar_write(®s->igaddr3, 0xffffffff); 3088 gfar_write(®s->igaddr4, 0xffffffff); 3089 gfar_write(®s->igaddr5, 0xffffffff); 3090 gfar_write(®s->igaddr6, 0xffffffff); 3091 gfar_write(®s->igaddr7, 0xffffffff); 3092 gfar_write(®s->gaddr0, 0xffffffff); 3093 gfar_write(®s->gaddr1, 0xffffffff); 3094 gfar_write(®s->gaddr2, 0xffffffff); 3095 gfar_write(®s->gaddr3, 0xffffffff); 3096 gfar_write(®s->gaddr4, 0xffffffff); 3097 gfar_write(®s->gaddr5, 0xffffffff); 3098 gfar_write(®s->gaddr6, 0xffffffff); 3099 gfar_write(®s->gaddr7, 0xffffffff); 3100 } else { 3101 int em_num; 3102 int idx; 3103 3104 /* zero out the hash */ 3105 gfar_write(®s->igaddr0, 0x0); 3106 gfar_write(®s->igaddr1, 0x0); 3107 gfar_write(®s->igaddr2, 0x0); 3108 gfar_write(®s->igaddr3, 0x0); 3109 gfar_write(®s->igaddr4, 0x0); 3110 gfar_write(®s->igaddr5, 0x0); 3111 gfar_write(®s->igaddr6, 0x0); 3112 gfar_write(®s->igaddr7, 0x0); 3113 gfar_write(®s->gaddr0, 0x0); 3114 gfar_write(®s->gaddr1, 0x0); 3115 gfar_write(®s->gaddr2, 0x0); 3116 gfar_write(®s->gaddr3, 0x0); 3117 gfar_write(®s->gaddr4, 0x0); 3118 gfar_write(®s->gaddr5, 0x0); 3119 gfar_write(®s->gaddr6, 0x0); 3120 gfar_write(®s->gaddr7, 0x0); 3121 3122 /* If we have extended hash tables, we need to 3123 * clear the exact match registers to prepare for 3124 * setting them 3125 */ 3126 if (priv->extended_hash) { 3127 em_num = GFAR_EM_NUM + 1; 3128 gfar_clear_exact_match(dev); 3129 idx = 1; 3130 } else { 3131 idx = 0; 3132 em_num = 0; 3133 } 3134 3135 if (netdev_mc_empty(dev)) 3136 return; 3137 3138 /* Parse the list, and set the appropriate bits */ 3139 netdev_for_each_mc_addr(ha, dev) { 3140 if (idx < em_num) { 3141 gfar_set_mac_for_addr(dev, idx, ha->addr); 3142 idx++; 3143 } else 3144 gfar_set_hash_for_addr(dev, ha->addr); 3145 } 3146 } 3147 } 3148 3149 3150 /* Clears each of the exact match registers to zero, so they 3151 * don't interfere with normal reception 3152 */ 3153 static void gfar_clear_exact_match(struct net_device *dev) 3154 { 3155 int idx; 3156 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; 3157 3158 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) 3159 gfar_set_mac_for_addr(dev, idx, zero_arr); 3160 } 3161 3162 /* Set the appropriate hash bit for the given addr */ 3163 /* The algorithm works like so: 3164 * 1) Take the Destination Address (ie the multicast address), and 3165 * do a CRC on it (little endian), and reverse the bits of the 3166 * result. 3167 * 2) Use the 8 most significant bits as a hash into a 256-entry 3168 * table. The table is controlled through 8 32-bit registers: 3169 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is 3170 * gaddr7. This means that the 3 most significant bits in the 3171 * hash index which gaddr register to use, and the 5 other bits 3172 * indicate which bit (assuming an IBM numbering scheme, which 3173 * for PowerPC (tm) is usually the case) in the register holds 3174 * the entry. 3175 */ 3176 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) 3177 { 3178 u32 tempval; 3179 struct gfar_private *priv = netdev_priv(dev); 3180 u32 result = ether_crc(ETH_ALEN, addr); 3181 int width = priv->hash_width; 3182 u8 whichbit = (result >> (32 - width)) & 0x1f; 3183 u8 whichreg = result >> (32 - width + 5); 3184 u32 value = (1 << (31-whichbit)); 3185 3186 tempval = gfar_read(priv->hash_regs[whichreg]); 3187 tempval |= value; 3188 gfar_write(priv->hash_regs[whichreg], tempval); 3189 } 3190 3191 3192 /* There are multiple MAC Address register pairs on some controllers 3193 * This function sets the numth pair to a given address 3194 */ 3195 static void gfar_set_mac_for_addr(struct net_device *dev, int num, 3196 const u8 *addr) 3197 { 3198 struct gfar_private *priv = netdev_priv(dev); 3199 struct gfar __iomem *regs = priv->gfargrp[0].regs; 3200 int idx; 3201 char tmpbuf[ETH_ALEN]; 3202 u32 tempval; 3203 u32 __iomem *macptr = ®s->macstnaddr1; 3204 3205 macptr += num*2; 3206 3207 /* Now copy it into the mac registers backwards, cuz 3208 * little endian is silly 3209 */ 3210 for (idx = 0; idx < ETH_ALEN; idx++) 3211 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; 3212 3213 gfar_write(macptr, *((u32 *) (tmpbuf))); 3214 3215 tempval = *((u32 *) (tmpbuf + 4)); 3216 3217 gfar_write(macptr+1, tempval); 3218 } 3219 3220 /* GFAR error interrupt handler */ 3221 static irqreturn_t gfar_error(int irq, void *grp_id) 3222 { 3223 struct gfar_priv_grp *gfargrp = grp_id; 3224 struct gfar __iomem *regs = gfargrp->regs; 3225 struct gfar_private *priv= gfargrp->priv; 3226 struct net_device *dev = priv->ndev; 3227 3228 /* Save ievent for future reference */ 3229 u32 events = gfar_read(®s->ievent); 3230 3231 /* Clear IEVENT */ 3232 gfar_write(®s->ievent, events & IEVENT_ERR_MASK); 3233 3234 /* Magic Packet is not an error. */ 3235 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && 3236 (events & IEVENT_MAG)) 3237 events &= ~IEVENT_MAG; 3238 3239 /* Hmm... */ 3240 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) 3241 netdev_dbg(dev, 3242 "error interrupt (ievent=0x%08x imask=0x%08x)\n", 3243 events, gfar_read(®s->imask)); 3244 3245 /* Update the error counters */ 3246 if (events & IEVENT_TXE) { 3247 dev->stats.tx_errors++; 3248 3249 if (events & IEVENT_LC) 3250 dev->stats.tx_window_errors++; 3251 if (events & IEVENT_CRL) 3252 dev->stats.tx_aborted_errors++; 3253 if (events & IEVENT_XFUN) { 3254 unsigned long flags; 3255 3256 netif_dbg(priv, tx_err, dev, 3257 "TX FIFO underrun, packet dropped\n"); 3258 dev->stats.tx_dropped++; 3259 atomic64_inc(&priv->extra_stats.tx_underrun); 3260 3261 local_irq_save(flags); 3262 lock_tx_qs(priv); 3263 3264 /* Reactivate the Tx Queues */ 3265 gfar_write(®s->tstat, gfargrp->tstat); 3266 3267 unlock_tx_qs(priv); 3268 local_irq_restore(flags); 3269 } 3270 netif_dbg(priv, tx_err, dev, "Transmit Error\n"); 3271 } 3272 if (events & IEVENT_BSY) { 3273 dev->stats.rx_errors++; 3274 atomic64_inc(&priv->extra_stats.rx_bsy); 3275 3276 gfar_receive(irq, grp_id); 3277 3278 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", 3279 gfar_read(®s->rstat)); 3280 } 3281 if (events & IEVENT_BABR) { 3282 dev->stats.rx_errors++; 3283 atomic64_inc(&priv->extra_stats.rx_babr); 3284 3285 netif_dbg(priv, rx_err, dev, "babbling RX error\n"); 3286 } 3287 if (events & IEVENT_EBERR) { 3288 atomic64_inc(&priv->extra_stats.eberr); 3289 netif_dbg(priv, rx_err, dev, "bus error\n"); 3290 } 3291 if (events & IEVENT_RXC) 3292 netif_dbg(priv, rx_status, dev, "control frame\n"); 3293 3294 if (events & IEVENT_BABT) { 3295 atomic64_inc(&priv->extra_stats.tx_babt); 3296 netif_dbg(priv, tx_err, dev, "babbling TX error\n"); 3297 } 3298 return IRQ_HANDLED; 3299 } 3300 3301 static struct of_device_id gfar_match[] = 3302 { 3303 { 3304 .type = "network", 3305 .compatible = "gianfar", 3306 }, 3307 { 3308 .compatible = "fsl,etsec2", 3309 }, 3310 {}, 3311 }; 3312 MODULE_DEVICE_TABLE(of, gfar_match); 3313 3314 /* Structure for a device driver */ 3315 static struct platform_driver gfar_driver = { 3316 .driver = { 3317 .name = "fsl-gianfar", 3318 .owner = THIS_MODULE, 3319 .pm = GFAR_PM_OPS, 3320 .of_match_table = gfar_match, 3321 }, 3322 .probe = gfar_probe, 3323 .remove = gfar_remove, 3324 }; 3325 3326 module_platform_driver(gfar_driver); 3327